Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ahci/ahci.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/8.4/sys/dev/ahci/ahci.c 247100 2013-02-21 15:26:26Z mav $"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/led/led.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include "ahci.h" 52 53 #include <cam/cam.h> 54 #include <cam/cam_ccb.h> 55 #include <cam/cam_sim.h> 56 #include <cam/cam_xpt_sim.h> 57 #include <cam/cam_debug.h> 58 59 /* local prototypes */ 60 static int ahci_setup_interrupt(device_t dev); 61 static void ahci_intr(void *data); 62 static void ahci_intr_one(void *data); 63 static int ahci_suspend(device_t dev); 64 static int ahci_resume(device_t dev); 65 static int ahci_ch_init(device_t dev); 66 static int ahci_ch_deinit(device_t dev); 67 static int ahci_ch_suspend(device_t dev); 68 static int ahci_ch_resume(device_t dev); 69 static void ahci_ch_pm(void *arg); 70 static void ahci_ch_intr_locked(void *data); 71 static void ahci_ch_intr(void *data); 72 static void ahci_ch_led(void *priv, int onoff); 73 static int ahci_ctlr_reset(device_t dev); 74 static int ahci_ctlr_setup(device_t dev); 75 static void ahci_begin_transaction(device_t dev, union ccb *ccb); 76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 77 static void ahci_execute_transaction(struct ahci_slot *slot); 78 static void ahci_timeout(struct ahci_slot *slot); 79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 81 static void ahci_dmainit(device_t dev); 82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 83 static void ahci_dmafini(device_t dev); 84 static void ahci_slotsalloc(device_t dev); 85 static void ahci_slotsfree(device_t dev); 86 static void ahci_reset(device_t dev); 87 static void ahci_start(device_t dev, int fbs); 88 static void ahci_stop(device_t dev); 89 static void ahci_clo(device_t dev); 90 static void ahci_start_fr(device_t dev); 91 static void ahci_stop_fr(device_t dev); 92 93 static int ahci_sata_connect(struct ahci_channel *ch); 94 static int ahci_sata_phy_reset(device_t dev); 95 static int ahci_wait_ready(device_t dev, int t, int t0); 96 97 static void ahci_issue_recovery(device_t dev); 98 static void ahci_process_read_log(device_t dev, union ccb *ccb); 99 static void ahci_process_request_sense(device_t dev, union ccb *ccb); 100 101 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 102 static void ahcipoll(struct cam_sim *sim); 103 104 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 105 106 static struct { 107 uint32_t id; 108 uint8_t rev; 109 const char *name; 110 int quirks; 111 #define AHCI_Q_NOFORCE 1 112 #define AHCI_Q_NOPMP 2 113 #define AHCI_Q_NONCQ 4 114 #define AHCI_Q_1CH 8 115 #define AHCI_Q_2CH 16 116 #define AHCI_Q_4CH 32 117 #define AHCI_Q_EDGEIS 64 118 #define AHCI_Q_SATA2 128 119 #define AHCI_Q_NOBSYRES 256 120 #define AHCI_Q_NOAA 512 121 #define AHCI_Q_NOCOUNT 1024 122 #define AHCI_Q_ALTSIG 2048 123 #define AHCI_Q_NOMSI 4096 124 } ahci_ids[] = { 125 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI}, 126 {0x43901002, 0x00, "ATI IXP700", 0}, 127 {0x43911002, 0x00, "ATI IXP700", 0}, 128 {0x43921002, 0x00, "ATI IXP700", 0}, 129 {0x43931002, 0x00, "ATI IXP700", 0}, 130 {0x43941002, 0x00, "ATI IXP800", 0}, 131 {0x43951002, 0x00, "ATI IXP800", 0}, 132 {0x78001022, 0x00, "AMD Hudson-2", 0}, 133 {0x78011022, 0x00, "AMD Hudson-2", 0}, 134 {0x78021022, 0x00, "AMD Hudson-2", 0}, 135 {0x78031022, 0x00, "AMD Hudson-2", 0}, 136 {0x78041022, 0x00, "AMD Hudson-2", 0}, 137 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 138 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 139 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 140 {0x26818086, 0x00, "Intel ESB2", 0}, 141 {0x26828086, 0x00, "Intel ESB2", 0}, 142 {0x26838086, 0x00, "Intel ESB2", 0}, 143 {0x27c18086, 0x00, "Intel ICH7", 0}, 144 {0x27c38086, 0x00, "Intel ICH7", 0}, 145 {0x27c58086, 0x00, "Intel ICH7M", 0}, 146 {0x27c68086, 0x00, "Intel ICH7M", 0}, 147 {0x28218086, 0x00, "Intel ICH8", 0}, 148 {0x28228086, 0x00, "Intel ICH8", 0}, 149 {0x28248086, 0x00, "Intel ICH8", 0}, 150 {0x28298086, 0x00, "Intel ICH8M", 0}, 151 {0x282a8086, 0x00, "Intel ICH8M", 0}, 152 {0x29228086, 0x00, "Intel ICH9", 0}, 153 {0x29238086, 0x00, "Intel ICH9", 0}, 154 {0x29248086, 0x00, "Intel ICH9", 0}, 155 {0x29258086, 0x00, "Intel ICH9", 0}, 156 {0x29278086, 0x00, "Intel ICH9", 0}, 157 {0x29298086, 0x00, "Intel ICH9M", 0}, 158 {0x292a8086, 0x00, "Intel ICH9M", 0}, 159 {0x292b8086, 0x00, "Intel ICH9M", 0}, 160 {0x292c8086, 0x00, "Intel ICH9M", 0}, 161 {0x292f8086, 0x00, "Intel ICH9M", 0}, 162 {0x294d8086, 0x00, "Intel ICH9", 0}, 163 {0x294e8086, 0x00, "Intel ICH9M", 0}, 164 {0x3a058086, 0x00, "Intel ICH10", 0}, 165 {0x3a228086, 0x00, "Intel ICH10", 0}, 166 {0x3a258086, 0x00, "Intel ICH10", 0}, 167 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 168 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 169 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 170 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 171 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 172 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 173 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 174 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 175 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 176 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 177 {0x1d028086, 0x00, "Intel Patsburg", 0}, 178 {0x1d048086, 0x00, "Intel Patsburg", 0}, 179 {0x1d068086, 0x00, "Intel Patsburg", 0}, 180 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 181 {0x1e028086, 0x00, "Intel Panther Point", 0}, 182 {0x1e038086, 0x00, "Intel Panther Point", 0}, 183 {0x1e048086, 0x00, "Intel Panther Point", 0}, 184 {0x1e058086, 0x00, "Intel Panther Point", 0}, 185 {0x1e068086, 0x00, "Intel Panther Point", 0}, 186 {0x1e078086, 0x00, "Intel Panther Point", 0}, 187 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 188 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 189 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 190 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 191 {0x8c048086, 0x00, "Intel Lynx Point", 0}, 192 {0x8c058086, 0x00, "Intel Lynx Point", 0}, 193 {0x8c068086, 0x00, "Intel Lynx Point", 0}, 194 {0x8c078086, 0x00, "Intel Lynx Point", 0}, 195 {0x8c0e8086, 0x00, "Intel Lynx Point", 0}, 196 {0x8c0f8086, 0x00, "Intel Lynx Point", 0}, 197 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 198 {0x2360197b, 0x00, "JMicron JMB360", 0}, 199 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 200 {0x2362197b, 0x00, "JMicron JMB362", 0}, 201 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 202 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 203 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 204 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 205 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 206 AHCI_Q_EDGEIS}, 207 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 208 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 209 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 210 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 211 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 212 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 213 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 214 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 215 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 216 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 217 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 218 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 219 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 220 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 221 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 222 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 223 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 224 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 225 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 226 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 227 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 228 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 229 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 230 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 231 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 232 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 233 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 234 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 235 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 236 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 237 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 238 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 239 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 240 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 241 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 242 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 243 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 244 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 245 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 246 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 247 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 248 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 249 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 250 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 251 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 252 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 253 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 254 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 255 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 256 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 257 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 258 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 259 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 260 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 261 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 262 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 263 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 264 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 265 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 266 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 267 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 268 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 269 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 270 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 271 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 272 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 273 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 274 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 275 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 276 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 277 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 278 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 279 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 280 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 281 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 282 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 283 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 284 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 285 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 286 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 287 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 288 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 289 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 290 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 291 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 292 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 293 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 294 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 295 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 296 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 297 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 298 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 299 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 300 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 301 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 302 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 303 {0x11841039, 0x00, "SiS 966", 0}, 304 {0x11851039, 0x00, "SiS 968", 0}, 305 {0x01861039, 0x00, "SiS 968", 0}, 306 {0x00000000, 0x00, NULL, 0} 307 }; 308 309 #define recovery_type spriv_field0 310 #define RECOVERY_NONE 0 311 #define RECOVERY_READ_LOG 1 312 #define RECOVERY_REQUEST_SENSE 2 313 #define recovery_slot spriv_field1 314 315 static int force_ahci = 1; 316 TUNABLE_INT("hw.ahci.force", &force_ahci); 317 318 static int 319 ahci_probe(device_t dev) 320 { 321 char buf[64]; 322 int i, valid = 0; 323 uint32_t devid = pci_get_devid(dev); 324 uint8_t revid = pci_get_revid(dev); 325 326 /* Is this a possible AHCI candidate? */ 327 if (pci_get_class(dev) == PCIC_STORAGE && 328 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 329 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 330 valid = 1; 331 /* Is this a known AHCI chip? */ 332 for (i = 0; ahci_ids[i].id != 0; i++) { 333 if (ahci_ids[i].id == devid && 334 ahci_ids[i].rev <= revid && 335 (valid || (force_ahci == 1 && 336 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 337 /* Do not attach JMicrons with single PCI function. */ 338 if (pci_get_vendor(dev) == 0x197b && 339 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 340 return (ENXIO); 341 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 342 ahci_ids[i].name); 343 device_set_desc_copy(dev, buf); 344 return (BUS_PROBE_VENDOR); 345 } 346 } 347 if (!valid) 348 return (ENXIO); 349 device_set_desc_copy(dev, "AHCI SATA controller"); 350 return (BUS_PROBE_VENDOR); 351 } 352 353 static int 354 ahci_ata_probe(device_t dev) 355 { 356 char buf[64]; 357 int i; 358 uint32_t devid = pci_get_devid(dev); 359 uint8_t revid = pci_get_revid(dev); 360 361 if ((intptr_t)device_get_ivars(dev) >= 0) 362 return (ENXIO); 363 /* Is this a known AHCI chip? */ 364 for (i = 0; ahci_ids[i].id != 0; i++) { 365 if (ahci_ids[i].id == devid && 366 ahci_ids[i].rev <= revid) { 367 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 368 ahci_ids[i].name); 369 device_set_desc_copy(dev, buf); 370 return (BUS_PROBE_VENDOR); 371 } 372 } 373 device_set_desc_copy(dev, "AHCI SATA controller"); 374 return (BUS_PROBE_VENDOR); 375 } 376 377 static int 378 ahci_attach(device_t dev) 379 { 380 struct ahci_controller *ctlr = device_get_softc(dev); 381 device_t child; 382 int error, unit, speed, i; 383 uint32_t devid = pci_get_devid(dev); 384 uint8_t revid = pci_get_revid(dev); 385 u_int32_t version; 386 387 ctlr->dev = dev; 388 i = 0; 389 while (ahci_ids[i].id != 0 && 390 (ahci_ids[i].id != devid || 391 ahci_ids[i].rev > revid)) 392 i++; 393 ctlr->quirks = ahci_ids[i].quirks; 394 resource_int_value(device_get_name(dev), 395 device_get_unit(dev), "ccc", &ctlr->ccc); 396 /* if we have a memory BAR(5) we are likely on an AHCI part */ 397 ctlr->r_rid = PCIR_BAR(5); 398 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 399 &ctlr->r_rid, RF_ACTIVE))) 400 return ENXIO; 401 /* Setup our own memory management for channels. */ 402 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 403 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 404 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 405 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 406 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 407 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 408 return (error); 409 } 410 if ((error = rman_manage_region(&ctlr->sc_iomem, 411 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 412 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 413 rman_fini(&ctlr->sc_iomem); 414 return (error); 415 } 416 pci_enable_busmaster(dev); 417 /* Reset controller */ 418 if ((error = ahci_ctlr_reset(dev)) != 0) { 419 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 420 rman_fini(&ctlr->sc_iomem); 421 return (error); 422 }; 423 /* Get the HW capabilities */ 424 version = ATA_INL(ctlr->r_mem, AHCI_VS); 425 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 426 if (version >= 0x00010200) 427 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 428 if (ctlr->caps & AHCI_CAP_EMS) 429 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 430 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 431 432 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 433 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 434 (ctlr->quirks & AHCI_Q_ALTSIG) && 435 (ctlr->caps & AHCI_CAP_SPM) == 0) 436 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 437 438 if (ctlr->quirks & AHCI_Q_1CH) { 439 ctlr->caps &= ~AHCI_CAP_NPMASK; 440 ctlr->ichannels &= 0x01; 441 } 442 if (ctlr->quirks & AHCI_Q_2CH) { 443 ctlr->caps &= ~AHCI_CAP_NPMASK; 444 ctlr->caps |= 1; 445 ctlr->ichannels &= 0x03; 446 } 447 if (ctlr->quirks & AHCI_Q_4CH) { 448 ctlr->caps &= ~AHCI_CAP_NPMASK; 449 ctlr->caps |= 3; 450 ctlr->ichannels &= 0x0f; 451 } 452 ctlr->channels = MAX(flsl(ctlr->ichannels), 453 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 454 if (ctlr->quirks & AHCI_Q_NOPMP) 455 ctlr->caps &= ~AHCI_CAP_SPM; 456 if (ctlr->quirks & AHCI_Q_NONCQ) 457 ctlr->caps &= ~AHCI_CAP_SNCQ; 458 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 459 ctlr->ccc = 0; 460 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF); 461 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 462 ahci_ctlr_setup(dev); 463 /* Setup interrupts. */ 464 if (ahci_setup_interrupt(dev)) { 465 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 466 rman_fini(&ctlr->sc_iomem); 467 return ENXIO; 468 } 469 /* Announce HW capabilities. */ 470 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 471 device_printf(dev, 472 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 473 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 474 ((version >> 4) & 0xf0) + (version & 0x0f), 475 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 476 ((speed == 1) ? "1.5":((speed == 2) ? "3": 477 ((speed == 3) ? "6":"?"))), 478 (ctlr->caps & AHCI_CAP_SPM) ? 479 "supported" : "not supported", 480 (ctlr->caps & AHCI_CAP_FBSS) ? 481 " with FBS" : ""); 482 if (bootverbose) { 483 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 484 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 485 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 486 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 487 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 488 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 489 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 490 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 491 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 492 ((speed == 1) ? "1.5":((speed == 2) ? "3": 493 ((speed == 3) ? "6":"?")))); 494 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 495 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 496 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 497 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 498 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 499 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 500 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 501 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 502 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 503 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 504 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 505 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 506 } 507 if (bootverbose && version >= 0x00010200) { 508 device_printf(dev, "Caps2:%s%s%s\n", 509 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 510 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 511 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 512 } 513 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 514 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 515 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 516 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 517 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 518 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 519 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 520 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 521 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 522 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 523 } 524 /* Attach all channels on this controller */ 525 for (unit = 0; unit < ctlr->channels; unit++) { 526 child = device_add_child(dev, "ahcich", -1); 527 if (child == NULL) { 528 device_printf(dev, "failed to add channel device\n"); 529 continue; 530 } 531 device_set_ivars(child, (void *)(intptr_t)unit); 532 if ((ctlr->ichannels & (1 << unit)) == 0) 533 device_disable(child); 534 } 535 bus_generic_attach(dev); 536 return 0; 537 } 538 539 static int 540 ahci_detach(device_t dev) 541 { 542 struct ahci_controller *ctlr = device_get_softc(dev); 543 device_t *children; 544 int nchildren, i; 545 546 /* Detach & delete all children */ 547 if (!device_get_children(dev, &children, &nchildren)) { 548 for (i = 0; i < nchildren; i++) 549 device_delete_child(dev, children[i]); 550 free(children, M_TEMP); 551 } 552 /* Free interrupts. */ 553 for (i = 0; i < ctlr->numirqs; i++) { 554 if (ctlr->irqs[i].r_irq) { 555 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 556 ctlr->irqs[i].handle); 557 bus_release_resource(dev, SYS_RES_IRQ, 558 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 559 } 560 } 561 pci_release_msi(dev); 562 /* Free memory. */ 563 rman_fini(&ctlr->sc_iomem); 564 if (ctlr->r_mem) 565 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 566 mtx_destroy(&ctlr->em_mtx); 567 return (0); 568 } 569 570 static int 571 ahci_ctlr_reset(device_t dev) 572 { 573 struct ahci_controller *ctlr = device_get_softc(dev); 574 int timeout; 575 576 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 577 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 578 pci_write_config(dev, 0x92, 0x01, 1); 579 /* Enable AHCI mode */ 580 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 581 /* Reset AHCI controller */ 582 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 583 for (timeout = 1000; timeout > 0; timeout--) { 584 DELAY(1000); 585 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 586 break; 587 } 588 if (timeout == 0) { 589 device_printf(dev, "AHCI controller reset failure\n"); 590 return ENXIO; 591 } 592 /* Reenable AHCI mode */ 593 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 594 return (0); 595 } 596 597 static int 598 ahci_ctlr_setup(device_t dev) 599 { 600 struct ahci_controller *ctlr = device_get_softc(dev); 601 /* Clear interrupts */ 602 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 603 /* Configure CCC */ 604 if (ctlr->ccc) { 605 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 606 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 607 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 608 (4 << AHCI_CCCC_CC_SHIFT) | 609 AHCI_CCCC_EN); 610 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 611 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 612 if (bootverbose) { 613 device_printf(dev, 614 "CCC with %dms/4cmd enabled on vector %d\n", 615 ctlr->ccc, ctlr->cccv); 616 } 617 } 618 /* Enable AHCI interrupts */ 619 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 620 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 621 return (0); 622 } 623 624 static int 625 ahci_suspend(device_t dev) 626 { 627 struct ahci_controller *ctlr = device_get_softc(dev); 628 629 bus_generic_suspend(dev); 630 /* Disable interupts, so the state change(s) doesn't trigger */ 631 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 632 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 633 return 0; 634 } 635 636 static int 637 ahci_resume(device_t dev) 638 { 639 int res; 640 641 if ((res = ahci_ctlr_reset(dev)) != 0) 642 return (res); 643 ahci_ctlr_setup(dev); 644 return (bus_generic_resume(dev)); 645 } 646 647 static int 648 ahci_setup_interrupt(device_t dev) 649 { 650 struct ahci_controller *ctlr = device_get_softc(dev); 651 int i, msi = 1; 652 653 /* Process hints. */ 654 if (ctlr->quirks & AHCI_Q_NOMSI) 655 msi = 0; 656 resource_int_value(device_get_name(dev), 657 device_get_unit(dev), "msi", &msi); 658 if (msi < 0) 659 msi = 0; 660 else if (msi == 1) 661 msi = min(1, pci_msi_count(dev)); 662 else if (msi > 1) 663 msi = pci_msi_count(dev); 664 /* Allocate MSI if needed/present. */ 665 if (msi && pci_alloc_msi(dev, &msi) == 0) { 666 ctlr->numirqs = msi; 667 } else { 668 msi = 0; 669 ctlr->numirqs = 1; 670 } 671 /* Check for single MSI vector fallback. */ 672 if (ctlr->numirqs > 1 && 673 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 674 device_printf(dev, "Falling back to one MSI\n"); 675 ctlr->numirqs = 1; 676 } 677 /* Allocate all IRQs. */ 678 for (i = 0; i < ctlr->numirqs; i++) { 679 ctlr->irqs[i].ctlr = ctlr; 680 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 681 if (ctlr->numirqs == 1 || i >= ctlr->channels || 682 (ctlr->ccc && i == ctlr->cccv)) 683 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 684 else if (i == ctlr->numirqs - 1) 685 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 686 else 687 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 688 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 689 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 690 device_printf(dev, "unable to map interrupt\n"); 691 return ENXIO; 692 } 693 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 694 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 695 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 696 /* SOS XXX release r_irq */ 697 device_printf(dev, "unable to setup interrupt\n"); 698 return ENXIO; 699 } 700 } 701 return (0); 702 } 703 704 /* 705 * Common case interrupt handler. 706 */ 707 static void 708 ahci_intr(void *data) 709 { 710 struct ahci_controller_irq *irq = data; 711 struct ahci_controller *ctlr = irq->ctlr; 712 u_int32_t is, ise = 0; 713 void *arg; 714 int unit; 715 716 if (irq->mode == AHCI_IRQ_MODE_ALL) { 717 unit = 0; 718 if (ctlr->ccc) 719 is = ctlr->ichannels; 720 else 721 is = ATA_INL(ctlr->r_mem, AHCI_IS); 722 } else { /* AHCI_IRQ_MODE_AFTER */ 723 unit = irq->r_irq_rid - 1; 724 is = ATA_INL(ctlr->r_mem, AHCI_IS); 725 } 726 /* CCC interrupt is edge triggered. */ 727 if (ctlr->ccc) 728 ise = 1 << ctlr->cccv; 729 /* Some controllers have edge triggered IS. */ 730 if (ctlr->quirks & AHCI_Q_EDGEIS) 731 ise |= is; 732 if (ise != 0) 733 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 734 for (; unit < ctlr->channels; unit++) { 735 if ((is & (1 << unit)) != 0 && 736 (arg = ctlr->interrupt[unit].argument)) { 737 ctlr->interrupt[unit].function(arg); 738 } 739 } 740 /* AHCI declares level triggered IS. */ 741 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 742 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 743 } 744 745 /* 746 * Simplified interrupt handler for multivector MSI mode. 747 */ 748 static void 749 ahci_intr_one(void *data) 750 { 751 struct ahci_controller_irq *irq = data; 752 struct ahci_controller *ctlr = irq->ctlr; 753 void *arg; 754 int unit; 755 756 unit = irq->r_irq_rid - 1; 757 /* Some controllers have edge triggered IS. */ 758 if (ctlr->quirks & AHCI_Q_EDGEIS) 759 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 760 if ((arg = ctlr->interrupt[unit].argument)) 761 ctlr->interrupt[unit].function(arg); 762 /* AHCI declares level triggered IS. */ 763 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 764 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 765 } 766 767 static struct resource * 768 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 769 u_long start, u_long end, u_long count, u_int flags) 770 { 771 struct ahci_controller *ctlr = device_get_softc(dev); 772 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 773 struct resource *res = NULL; 774 int offset = AHCI_OFFSET + (unit << 7); 775 long st; 776 777 switch (type) { 778 case SYS_RES_MEMORY: 779 st = rman_get_start(ctlr->r_mem); 780 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 781 st + offset + 127, 128, RF_ACTIVE, child); 782 if (res) { 783 bus_space_handle_t bsh; 784 bus_space_tag_t bst; 785 bsh = rman_get_bushandle(ctlr->r_mem); 786 bst = rman_get_bustag(ctlr->r_mem); 787 bus_space_subregion(bst, bsh, offset, 128, &bsh); 788 rman_set_bushandle(res, bsh); 789 rman_set_bustag(res, bst); 790 } 791 break; 792 case SYS_RES_IRQ: 793 if (*rid == ATA_IRQ_RID) 794 res = ctlr->irqs[0].r_irq; 795 break; 796 } 797 return (res); 798 } 799 800 static int 801 ahci_release_resource(device_t dev, device_t child, int type, int rid, 802 struct resource *r) 803 { 804 805 switch (type) { 806 case SYS_RES_MEMORY: 807 rman_release_resource(r); 808 return (0); 809 case SYS_RES_IRQ: 810 if (rid != ATA_IRQ_RID) 811 return ENOENT; 812 return (0); 813 } 814 return (EINVAL); 815 } 816 817 static int 818 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 819 int flags, driver_filter_t *filter, driver_intr_t *function, 820 void *argument, void **cookiep) 821 { 822 struct ahci_controller *ctlr = device_get_softc(dev); 823 int unit = (intptr_t)device_get_ivars(child); 824 825 if (filter != NULL) { 826 printf("ahci.c: we cannot use a filter here\n"); 827 return (EINVAL); 828 } 829 ctlr->interrupt[unit].function = function; 830 ctlr->interrupt[unit].argument = argument; 831 return (0); 832 } 833 834 static int 835 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 836 void *cookie) 837 { 838 struct ahci_controller *ctlr = device_get_softc(dev); 839 int unit = (intptr_t)device_get_ivars(child); 840 841 ctlr->interrupt[unit].function = NULL; 842 ctlr->interrupt[unit].argument = NULL; 843 return (0); 844 } 845 846 static int 847 ahci_print_child(device_t dev, device_t child) 848 { 849 int retval; 850 851 retval = bus_print_child_header(dev, child); 852 retval += printf(" at channel %d", 853 (int)(intptr_t)device_get_ivars(child)); 854 retval += bus_print_child_footer(dev, child); 855 856 return (retval); 857 } 858 859 static int 860 ahci_child_location_str(device_t dev, device_t child, char *buf, 861 size_t buflen) 862 { 863 864 snprintf(buf, buflen, "channel=%d", 865 (int)(intptr_t)device_get_ivars(child)); 866 return (0); 867 } 868 869 devclass_t ahci_devclass; 870 static device_method_t ahci_methods[] = { 871 DEVMETHOD(device_probe, ahci_probe), 872 DEVMETHOD(device_attach, ahci_attach), 873 DEVMETHOD(device_detach, ahci_detach), 874 DEVMETHOD(device_suspend, ahci_suspend), 875 DEVMETHOD(device_resume, ahci_resume), 876 DEVMETHOD(bus_print_child, ahci_print_child), 877 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 878 DEVMETHOD(bus_release_resource, ahci_release_resource), 879 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 880 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 881 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 882 { 0, 0 } 883 }; 884 static driver_t ahci_driver = { 885 "ahci", 886 ahci_methods, 887 sizeof(struct ahci_controller) 888 }; 889 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 890 static device_method_t ahci_ata_methods[] = { 891 DEVMETHOD(device_probe, ahci_ata_probe), 892 DEVMETHOD(device_attach, ahci_attach), 893 DEVMETHOD(device_detach, ahci_detach), 894 DEVMETHOD(device_suspend, ahci_suspend), 895 DEVMETHOD(device_resume, ahci_resume), 896 DEVMETHOD(bus_print_child, ahci_print_child), 897 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 898 DEVMETHOD(bus_release_resource, ahci_release_resource), 899 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 900 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 901 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 902 { 0, 0 } 903 }; 904 static driver_t ahci_ata_driver = { 905 "ahci", 906 ahci_ata_methods, 907 sizeof(struct ahci_controller) 908 }; 909 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 910 MODULE_VERSION(ahci, 1); 911 MODULE_DEPEND(ahci, cam, 1, 1, 1); 912 913 static int 914 ahci_ch_probe(device_t dev) 915 { 916 917 device_set_desc_copy(dev, "AHCI channel"); 918 return (0); 919 } 920 921 static int 922 ahci_ch_attach(device_t dev) 923 { 924 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 925 struct ahci_channel *ch = device_get_softc(dev); 926 struct cam_devq *devq; 927 int rid, error, i, sata_rev = 0; 928 u_int32_t version; 929 char buf[32]; 930 931 ch->dev = dev; 932 ch->unit = (intptr_t)device_get_ivars(dev); 933 ch->caps = ctlr->caps; 934 ch->caps2 = ctlr->caps2; 935 ch->quirks = ctlr->quirks; 936 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 937 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 938 resource_int_value(device_get_name(dev), 939 device_get_unit(dev), "pm_level", &ch->pm_level); 940 if (ch->pm_level > 3) 941 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 942 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 943 /* Limit speed for my onboard JMicron external port. 944 * It is not eSATA really. */ 945 if (pci_get_devid(ctlr->dev) == 0x2363197b && 946 pci_get_subvendor(ctlr->dev) == 0x1043 && 947 pci_get_subdevice(ctlr->dev) == 0x81e4 && 948 ch->unit == 0) 949 sata_rev = 1; 950 if (ch->quirks & AHCI_Q_SATA2) 951 sata_rev = 2; 952 resource_int_value(device_get_name(dev), 953 device_get_unit(dev), "sata_rev", &sata_rev); 954 for (i = 0; i < 16; i++) { 955 ch->user[i].revision = sata_rev; 956 ch->user[i].mode = 0; 957 ch->user[i].bytecount = 8192; 958 ch->user[i].tags = ch->numslots; 959 ch->user[i].caps = 0; 960 ch->curr[i] = ch->user[i]; 961 if (ch->pm_level) { 962 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 963 CTS_SATA_CAPS_H_APST | 964 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 965 } 966 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 967 CTS_SATA_CAPS_H_AN; 968 } 969 rid = ch->unit; 970 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 971 &rid, RF_ACTIVE))) 972 return (ENXIO); 973 ahci_dmainit(dev); 974 ahci_slotsalloc(dev); 975 ahci_ch_init(dev); 976 mtx_lock(&ch->mtx); 977 rid = ATA_IRQ_RID; 978 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 979 &rid, RF_SHAREABLE | RF_ACTIVE))) { 980 device_printf(dev, "Unable to map interrupt\n"); 981 error = ENXIO; 982 goto err0; 983 } 984 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 985 ahci_ch_intr_locked, dev, &ch->ih))) { 986 device_printf(dev, "Unable to setup interrupt\n"); 987 error = ENXIO; 988 goto err1; 989 } 990 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 991 version = ATA_INL(ctlr->r_mem, AHCI_VS); 992 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 993 ch->chcaps |= AHCI_P_CMD_FBSCP; 994 if (bootverbose) { 995 device_printf(dev, "Caps:%s%s%s%s%s\n", 996 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 997 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 998 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 999 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1000 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1001 } 1002 /* Create the device queue for our SIM. */ 1003 devq = cam_simq_alloc(ch->numslots); 1004 if (devq == NULL) { 1005 device_printf(dev, "Unable to allocate simq\n"); 1006 error = ENOMEM; 1007 goto err1; 1008 } 1009 /* Construct SIM entry */ 1010 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1011 device_get_unit(dev), &ch->mtx, 1012 min(2, ch->numslots), 1013 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1014 devq); 1015 if (ch->sim == NULL) { 1016 cam_simq_free(devq); 1017 device_printf(dev, "unable to allocate sim\n"); 1018 error = ENOMEM; 1019 goto err1; 1020 } 1021 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1022 device_printf(dev, "unable to register xpt bus\n"); 1023 error = ENXIO; 1024 goto err2; 1025 } 1026 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1027 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1028 device_printf(dev, "unable to create path\n"); 1029 error = ENXIO; 1030 goto err3; 1031 } 1032 if (ch->pm_level > 3) { 1033 callout_reset(&ch->pm_timer, 1034 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1035 ahci_ch_pm, dev); 1036 } 1037 mtx_unlock(&ch->mtx); 1038 if ((ch->caps & AHCI_CAP_EMS) && 1039 (ctlr->capsem & AHCI_EM_LED)) { 1040 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1041 ch->leds[i].dev = dev; 1042 ch->leds[i].num = i; 1043 } 1044 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) { 1045 snprintf(buf, sizeof(buf), "%s.act", 1046 device_get_nameunit(dev)); 1047 ch->leds[0].led = led_create(ahci_ch_led, 1048 &ch->leds[0], buf); 1049 } 1050 snprintf(buf, sizeof(buf), "%s.locate", 1051 device_get_nameunit(dev)); 1052 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf); 1053 snprintf(buf, sizeof(buf), "%s.fault", 1054 device_get_nameunit(dev)); 1055 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf); 1056 } 1057 return (0); 1058 1059 err3: 1060 xpt_bus_deregister(cam_sim_path(ch->sim)); 1061 err2: 1062 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1063 err1: 1064 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1065 err0: 1066 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1067 mtx_unlock(&ch->mtx); 1068 mtx_destroy(&ch->mtx); 1069 return (error); 1070 } 1071 1072 static int 1073 ahci_ch_detach(device_t dev) 1074 { 1075 struct ahci_channel *ch = device_get_softc(dev); 1076 int i; 1077 1078 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1079 if (ch->leds[i].led) 1080 led_destroy(ch->leds[i].led); 1081 } 1082 mtx_lock(&ch->mtx); 1083 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1084 /* Forget about reset. */ 1085 if (ch->resetting) { 1086 ch->resetting = 0; 1087 xpt_release_simq(ch->sim, TRUE); 1088 } 1089 xpt_free_path(ch->path); 1090 xpt_bus_deregister(cam_sim_path(ch->sim)); 1091 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1092 mtx_unlock(&ch->mtx); 1093 1094 if (ch->pm_level > 3) 1095 callout_drain(&ch->pm_timer); 1096 callout_drain(&ch->reset_timer); 1097 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1098 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1099 1100 ahci_ch_deinit(dev); 1101 ahci_slotsfree(dev); 1102 ahci_dmafini(dev); 1103 1104 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1105 mtx_destroy(&ch->mtx); 1106 return (0); 1107 } 1108 1109 static int 1110 ahci_ch_init(device_t dev) 1111 { 1112 struct ahci_channel *ch = device_get_softc(dev); 1113 uint64_t work; 1114 1115 /* Disable port interrupts */ 1116 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1117 /* Setup work areas */ 1118 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1119 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1120 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1121 work = ch->dma.rfis_bus; 1122 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1123 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1124 /* Activate the channel and power/spin up device */ 1125 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1126 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1127 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1128 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1129 ahci_start_fr(dev); 1130 ahci_start(dev, 1); 1131 return (0); 1132 } 1133 1134 static int 1135 ahci_ch_deinit(device_t dev) 1136 { 1137 struct ahci_channel *ch = device_get_softc(dev); 1138 1139 /* Disable port interrupts. */ 1140 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1141 /* Reset command register. */ 1142 ahci_stop(dev); 1143 ahci_stop_fr(dev); 1144 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1145 /* Allow everything, including partial and slumber modes. */ 1146 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1147 /* Request slumber mode transition and give some time to get there. */ 1148 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1149 DELAY(100); 1150 /* Disable PHY. */ 1151 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1152 return (0); 1153 } 1154 1155 static int 1156 ahci_ch_suspend(device_t dev) 1157 { 1158 struct ahci_channel *ch = device_get_softc(dev); 1159 1160 mtx_lock(&ch->mtx); 1161 xpt_freeze_simq(ch->sim, 1); 1162 /* Forget about reset. */ 1163 if (ch->resetting) { 1164 ch->resetting = 0; 1165 callout_stop(&ch->reset_timer); 1166 xpt_release_simq(ch->sim, TRUE); 1167 } 1168 while (ch->oslots) 1169 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1170 ahci_ch_deinit(dev); 1171 mtx_unlock(&ch->mtx); 1172 return (0); 1173 } 1174 1175 static int 1176 ahci_ch_resume(device_t dev) 1177 { 1178 struct ahci_channel *ch = device_get_softc(dev); 1179 1180 mtx_lock(&ch->mtx); 1181 ahci_ch_init(dev); 1182 ahci_reset(dev); 1183 xpt_release_simq(ch->sim, TRUE); 1184 mtx_unlock(&ch->mtx); 1185 return (0); 1186 } 1187 1188 devclass_t ahcich_devclass; 1189 static device_method_t ahcich_methods[] = { 1190 DEVMETHOD(device_probe, ahci_ch_probe), 1191 DEVMETHOD(device_attach, ahci_ch_attach), 1192 DEVMETHOD(device_detach, ahci_ch_detach), 1193 DEVMETHOD(device_suspend, ahci_ch_suspend), 1194 DEVMETHOD(device_resume, ahci_ch_resume), 1195 { 0, 0 } 1196 }; 1197 static driver_t ahcich_driver = { 1198 "ahcich", 1199 ahcich_methods, 1200 sizeof(struct ahci_channel) 1201 }; 1202 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1203 1204 static void 1205 ahci_ch_setleds(device_t dev) 1206 { 1207 struct ahci_channel *ch; 1208 struct ahci_controller *ctlr; 1209 size_t buf; 1210 int i, timeout; 1211 int16_t val; 1212 1213 ctlr = device_get_softc(device_get_parent(dev)); 1214 ch = device_get_softc(dev); 1215 1216 val = 0; 1217 for (i = 0; i < AHCI_NUM_LEDS; i++) 1218 val |= ch->leds[i].state << (i * 3); 1219 1220 buf = (ctlr->emloc & 0xffff0000) >> 14; 1221 mtx_lock(&ctlr->em_mtx); 1222 timeout = 1000; 1223 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) && 1224 --timeout > 0) 1225 DELAY(1000); 1226 if (timeout == 0) 1227 device_printf(dev, "EM timeout\n"); 1228 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24)); 1229 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16)); 1230 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM); 1231 mtx_unlock(&ctlr->em_mtx); 1232 } 1233 1234 static void 1235 ahci_ch_led(void *priv, int onoff) 1236 { 1237 struct ahci_led *led; 1238 1239 led = (struct ahci_led *)priv; 1240 1241 led->state = onoff; 1242 ahci_ch_setleds(led->dev); 1243 } 1244 1245 struct ahci_dc_cb_args { 1246 bus_addr_t maddr; 1247 int error; 1248 }; 1249 1250 static void 1251 ahci_dmainit(device_t dev) 1252 { 1253 struct ahci_channel *ch = device_get_softc(dev); 1254 struct ahci_dc_cb_args dcba; 1255 size_t rfsize; 1256 1257 if (ch->caps & AHCI_CAP_64BIT) 1258 ch->dma.max_address = BUS_SPACE_MAXADDR; 1259 else 1260 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1261 /* Command area. */ 1262 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1263 ch->dma.max_address, BUS_SPACE_MAXADDR, 1264 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1265 0, NULL, NULL, &ch->dma.work_tag)) 1266 goto error; 1267 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1268 &ch->dma.work_map)) 1269 goto error; 1270 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1271 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1272 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1273 goto error; 1274 } 1275 ch->dma.work_bus = dcba.maddr; 1276 /* FIS receive area. */ 1277 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1278 rfsize = 4096; 1279 else 1280 rfsize = 256; 1281 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1282 ch->dma.max_address, BUS_SPACE_MAXADDR, 1283 NULL, NULL, rfsize, 1, rfsize, 1284 0, NULL, NULL, &ch->dma.rfis_tag)) 1285 goto error; 1286 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1287 &ch->dma.rfis_map)) 1288 goto error; 1289 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1290 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1291 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1292 goto error; 1293 } 1294 ch->dma.rfis_bus = dcba.maddr; 1295 /* Data area. */ 1296 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1297 ch->dma.max_address, BUS_SPACE_MAXADDR, 1298 NULL, NULL, 1299 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1300 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1301 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1302 goto error; 1303 } 1304 return; 1305 1306 error: 1307 device_printf(dev, "WARNING - DMA initialization failed\n"); 1308 ahci_dmafini(dev); 1309 } 1310 1311 static void 1312 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1313 { 1314 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1315 1316 if (!(dcba->error = error)) 1317 dcba->maddr = segs[0].ds_addr; 1318 } 1319 1320 static void 1321 ahci_dmafini(device_t dev) 1322 { 1323 struct ahci_channel *ch = device_get_softc(dev); 1324 1325 if (ch->dma.data_tag) { 1326 bus_dma_tag_destroy(ch->dma.data_tag); 1327 ch->dma.data_tag = NULL; 1328 } 1329 if (ch->dma.rfis_bus) { 1330 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1331 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1332 ch->dma.rfis_bus = 0; 1333 ch->dma.rfis_map = NULL; 1334 ch->dma.rfis = NULL; 1335 } 1336 if (ch->dma.work_bus) { 1337 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1338 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1339 ch->dma.work_bus = 0; 1340 ch->dma.work_map = NULL; 1341 ch->dma.work = NULL; 1342 } 1343 if (ch->dma.work_tag) { 1344 bus_dma_tag_destroy(ch->dma.work_tag); 1345 ch->dma.work_tag = NULL; 1346 } 1347 } 1348 1349 static void 1350 ahci_slotsalloc(device_t dev) 1351 { 1352 struct ahci_channel *ch = device_get_softc(dev); 1353 int i; 1354 1355 /* Alloc and setup command/dma slots */ 1356 bzero(ch->slot, sizeof(ch->slot)); 1357 for (i = 0; i < ch->numslots; i++) { 1358 struct ahci_slot *slot = &ch->slot[i]; 1359 1360 slot->dev = dev; 1361 slot->slot = i; 1362 slot->state = AHCI_SLOT_EMPTY; 1363 slot->ccb = NULL; 1364 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1365 1366 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1367 device_printf(ch->dev, "FAILURE - create data_map\n"); 1368 } 1369 } 1370 1371 static void 1372 ahci_slotsfree(device_t dev) 1373 { 1374 struct ahci_channel *ch = device_get_softc(dev); 1375 int i; 1376 1377 /* Free all dma slots */ 1378 for (i = 0; i < ch->numslots; i++) { 1379 struct ahci_slot *slot = &ch->slot[i]; 1380 1381 callout_drain(&slot->timeout); 1382 if (slot->dma.data_map) { 1383 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1384 slot->dma.data_map = NULL; 1385 } 1386 } 1387 } 1388 1389 static int 1390 ahci_phy_check_events(device_t dev, u_int32_t serr) 1391 { 1392 struct ahci_channel *ch = device_get_softc(dev); 1393 1394 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1395 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1396 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1397 union ccb *ccb; 1398 1399 if (bootverbose) { 1400 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1401 device_printf(dev, "CONNECT requested\n"); 1402 else 1403 device_printf(dev, "DISCONNECT requested\n"); 1404 } 1405 ahci_reset(dev); 1406 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1407 return (0); 1408 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1409 cam_sim_path(ch->sim), 1410 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1411 xpt_free_ccb(ccb); 1412 return (0); 1413 } 1414 xpt_rescan(ccb); 1415 return (1); 1416 } 1417 return (0); 1418 } 1419 1420 static void 1421 ahci_cpd_check_events(device_t dev) 1422 { 1423 struct ahci_channel *ch = device_get_softc(dev); 1424 u_int32_t status; 1425 union ccb *ccb; 1426 1427 if (ch->pm_level == 0) 1428 return; 1429 1430 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1431 if ((status & AHCI_P_CMD_CPD) == 0) 1432 return; 1433 1434 if (bootverbose) { 1435 if (status & AHCI_P_CMD_CPS) { 1436 device_printf(dev, "COLD CONNECT requested\n"); 1437 } else 1438 device_printf(dev, "COLD DISCONNECT requested\n"); 1439 } 1440 ahci_reset(dev); 1441 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1442 return; 1443 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1444 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1445 xpt_free_ccb(ccb); 1446 return; 1447 } 1448 xpt_rescan(ccb); 1449 } 1450 1451 static void 1452 ahci_notify_events(device_t dev, u_int32_t status) 1453 { 1454 struct ahci_channel *ch = device_get_softc(dev); 1455 struct cam_path *dpath; 1456 int i; 1457 1458 if (ch->caps & AHCI_CAP_SSNTF) 1459 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1460 if (bootverbose) 1461 device_printf(dev, "SNTF 0x%04x\n", status); 1462 for (i = 0; i < 16; i++) { 1463 if ((status & (1 << i)) == 0) 1464 continue; 1465 if (xpt_create_path(&dpath, NULL, 1466 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1467 xpt_async(AC_SCSI_AEN, dpath, NULL); 1468 xpt_free_path(dpath); 1469 } 1470 } 1471 } 1472 1473 static void 1474 ahci_ch_intr_locked(void *data) 1475 { 1476 device_t dev = (device_t)data; 1477 struct ahci_channel *ch = device_get_softc(dev); 1478 1479 mtx_lock(&ch->mtx); 1480 xpt_batch_start(ch->sim); 1481 ahci_ch_intr(data); 1482 xpt_batch_done(ch->sim); 1483 mtx_unlock(&ch->mtx); 1484 } 1485 1486 static void 1487 ahci_ch_pm(void *arg) 1488 { 1489 device_t dev = (device_t)arg; 1490 struct ahci_channel *ch = device_get_softc(dev); 1491 uint32_t work; 1492 1493 if (ch->numrslots != 0) 1494 return; 1495 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1496 if (ch->pm_level == 4) 1497 work |= AHCI_P_CMD_PARTIAL; 1498 else 1499 work |= AHCI_P_CMD_SLUMBER; 1500 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1501 } 1502 1503 static void 1504 ahci_ch_intr(void *data) 1505 { 1506 device_t dev = (device_t)data; 1507 struct ahci_channel *ch = device_get_softc(dev); 1508 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1509 enum ahci_err_type et; 1510 int i, ccs, port, reset = 0; 1511 1512 /* Read and clear interrupt statuses. */ 1513 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1514 if (istatus == 0) 1515 return; 1516 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1517 /* Read command statuses. */ 1518 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1519 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1520 if (istatus & AHCI_P_IX_SDB) { 1521 if (ch->caps & AHCI_CAP_SSNTF) 1522 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1523 else if (ch->fbs_enabled) { 1524 u_int8_t *fis = ch->dma.rfis + 0x58; 1525 1526 for (i = 0; i < 16; i++) { 1527 if (fis[1] & 0x80) { 1528 fis[1] &= 0x7f; 1529 sntf |= 1 << i; 1530 } 1531 fis += 256; 1532 } 1533 } else { 1534 u_int8_t *fis = ch->dma.rfis + 0x58; 1535 1536 if (fis[1] & 0x80) 1537 sntf = (1 << (fis[1] & 0x0f)); 1538 } 1539 } 1540 /* Process PHY events */ 1541 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1542 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1543 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1544 if (serr) { 1545 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1546 reset = ahci_phy_check_events(dev, serr); 1547 } 1548 } 1549 /* Process cold presence detection events */ 1550 if ((istatus & AHCI_P_IX_CPD) && !reset) 1551 ahci_cpd_check_events(dev); 1552 /* Process command errors */ 1553 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1554 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1555 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1556 >> AHCI_P_CMD_CCS_SHIFT; 1557 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1558 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1559 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1560 port = -1; 1561 if (ch->fbs_enabled) { 1562 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1563 if (fbs & AHCI_P_FBS_SDE) { 1564 port = (fbs & AHCI_P_FBS_DWE) 1565 >> AHCI_P_FBS_DWE_SHIFT; 1566 } else { 1567 for (i = 0; i < 16; i++) { 1568 if (ch->numrslotspd[i] == 0) 1569 continue; 1570 if (port == -1) 1571 port = i; 1572 else if (port != i) { 1573 port = -2; 1574 break; 1575 } 1576 } 1577 } 1578 } 1579 err = ch->rslots & (cstatus | sstatus); 1580 } else { 1581 ccs = 0; 1582 err = 0; 1583 port = -1; 1584 } 1585 /* Complete all successfull commands. */ 1586 ok = ch->rslots & ~(cstatus | sstatus); 1587 for (i = 0; i < ch->numslots; i++) { 1588 if ((ok >> i) & 1) 1589 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1590 } 1591 /* On error, complete the rest of commands with error statuses. */ 1592 if (err) { 1593 if (ch->frozen) { 1594 union ccb *fccb = ch->frozen; 1595 ch->frozen = NULL; 1596 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1597 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1598 xpt_freeze_devq(fccb->ccb_h.path, 1); 1599 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1600 } 1601 xpt_done(fccb); 1602 } 1603 for (i = 0; i < ch->numslots; i++) { 1604 /* XXX: reqests in loading state. */ 1605 if (((err >> i) & 1) == 0) 1606 continue; 1607 if (port >= 0 && 1608 ch->slot[i].ccb->ccb_h.target_id != port) 1609 continue; 1610 if (istatus & AHCI_P_IX_TFE) { 1611 if (port != -2) { 1612 /* Task File Error */ 1613 if (ch->numtslotspd[ 1614 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1615 /* Untagged operation. */ 1616 if (i == ccs) 1617 et = AHCI_ERR_TFE; 1618 else 1619 et = AHCI_ERR_INNOCENT; 1620 } else { 1621 /* Tagged operation. */ 1622 et = AHCI_ERR_NCQ; 1623 } 1624 } else { 1625 et = AHCI_ERR_TFE; 1626 ch->fatalerr = 1; 1627 } 1628 } else if (istatus & AHCI_P_IX_IF) { 1629 if (ch->numtslots == 0 && i != ccs && port != -2) 1630 et = AHCI_ERR_INNOCENT; 1631 else 1632 et = AHCI_ERR_SATA; 1633 } else 1634 et = AHCI_ERR_INVALID; 1635 ahci_end_transaction(&ch->slot[i], et); 1636 } 1637 /* 1638 * We can't reinit port if there are some other 1639 * commands active, use resume to complete them. 1640 */ 1641 if (ch->rslots != 0 && !ch->recoverycmd) 1642 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1643 } 1644 /* Process NOTIFY events */ 1645 if (sntf) 1646 ahci_notify_events(dev, sntf); 1647 } 1648 1649 /* Must be called with channel locked. */ 1650 static int 1651 ahci_check_collision(device_t dev, union ccb *ccb) 1652 { 1653 struct ahci_channel *ch = device_get_softc(dev); 1654 int t = ccb->ccb_h.target_id; 1655 1656 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1657 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1658 /* Tagged command while we have no supported tag free. */ 1659 if (((~ch->oslots) & (0xffffffff >> (32 - 1660 ch->curr[t].tags))) == 0) 1661 return (1); 1662 /* If we have FBS */ 1663 if (ch->fbs_enabled) { 1664 /* Tagged command while untagged are active. */ 1665 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1666 return (1); 1667 } else { 1668 /* Tagged command while untagged are active. */ 1669 if (ch->numrslots != 0 && ch->numtslots == 0) 1670 return (1); 1671 /* Tagged command while tagged to other target is active. */ 1672 if (ch->numtslots != 0 && 1673 ch->taggedtarget != ccb->ccb_h.target_id) 1674 return (1); 1675 } 1676 } else { 1677 /* If we have FBS */ 1678 if (ch->fbs_enabled) { 1679 /* Untagged command while tagged are active. */ 1680 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1681 return (1); 1682 } else { 1683 /* Untagged command while tagged are active. */ 1684 if (ch->numrslots != 0 && ch->numtslots != 0) 1685 return (1); 1686 } 1687 } 1688 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1689 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1690 /* Atomic command while anything active. */ 1691 if (ch->numrslots != 0) 1692 return (1); 1693 } 1694 /* We have some atomic command running. */ 1695 if (ch->aslots != 0) 1696 return (1); 1697 return (0); 1698 } 1699 1700 /* Must be called with channel locked. */ 1701 static void 1702 ahci_begin_transaction(device_t dev, union ccb *ccb) 1703 { 1704 struct ahci_channel *ch = device_get_softc(dev); 1705 struct ahci_slot *slot; 1706 int tag, tags; 1707 1708 /* Choose empty slot. */ 1709 tags = ch->numslots; 1710 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1711 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1712 tags = ch->curr[ccb->ccb_h.target_id].tags; 1713 tag = ch->lastslot; 1714 while (1) { 1715 if (tag >= tags) 1716 tag = 0; 1717 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1718 break; 1719 tag++; 1720 }; 1721 ch->lastslot = tag; 1722 /* Occupy chosen slot. */ 1723 slot = &ch->slot[tag]; 1724 slot->ccb = ccb; 1725 /* Stop PM timer. */ 1726 if (ch->numrslots == 0 && ch->pm_level > 3) 1727 callout_stop(&ch->pm_timer); 1728 /* Update channel stats. */ 1729 ch->oslots |= (1 << slot->slot); 1730 ch->numrslots++; 1731 ch->numrslotspd[ccb->ccb_h.target_id]++; 1732 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1733 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1734 ch->numtslots++; 1735 ch->numtslotspd[ccb->ccb_h.target_id]++; 1736 ch->taggedtarget = ccb->ccb_h.target_id; 1737 } 1738 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1739 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1740 ch->aslots |= (1 << slot->slot); 1741 slot->dma.nsegs = 0; 1742 /* If request moves data, setup and load SG list */ 1743 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1744 void *buf; 1745 bus_size_t size; 1746 1747 slot->state = AHCI_SLOT_LOADING; 1748 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1749 buf = ccb->ataio.data_ptr; 1750 size = ccb->ataio.dxfer_len; 1751 } else { 1752 buf = ccb->csio.data_ptr; 1753 size = ccb->csio.dxfer_len; 1754 } 1755 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1756 buf, size, ahci_dmasetprd, slot, 0); 1757 } else 1758 ahci_execute_transaction(slot); 1759 } 1760 1761 /* Locked by busdma engine. */ 1762 static void 1763 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1764 { 1765 struct ahci_slot *slot = arg; 1766 struct ahci_channel *ch = device_get_softc(slot->dev); 1767 struct ahci_cmd_tab *ctp; 1768 struct ahci_dma_prd *prd; 1769 int i; 1770 1771 if (error) { 1772 device_printf(slot->dev, "DMA load error\n"); 1773 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1774 return; 1775 } 1776 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1777 /* Get a piece of the workspace for this request */ 1778 ctp = (struct ahci_cmd_tab *) 1779 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1780 /* Fill S/G table */ 1781 prd = &ctp->prd_tab[0]; 1782 for (i = 0; i < nsegs; i++) { 1783 prd[i].dba = htole64(segs[i].ds_addr); 1784 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1785 } 1786 slot->dma.nsegs = nsegs; 1787 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1788 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1789 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1790 ahci_execute_transaction(slot); 1791 } 1792 1793 /* Must be called with channel locked. */ 1794 static void 1795 ahci_execute_transaction(struct ahci_slot *slot) 1796 { 1797 device_t dev = slot->dev; 1798 struct ahci_channel *ch = device_get_softc(dev); 1799 struct ahci_cmd_tab *ctp; 1800 struct ahci_cmd_list *clp; 1801 union ccb *ccb = slot->ccb; 1802 int port = ccb->ccb_h.target_id & 0x0f; 1803 int fis_size, i, softreset; 1804 uint8_t *fis = ch->dma.rfis + 0x40; 1805 uint8_t val; 1806 1807 /* Get a piece of the workspace for this request */ 1808 ctp = (struct ahci_cmd_tab *) 1809 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1810 /* Setup the FIS for this request */ 1811 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1812 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1813 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1814 return; 1815 } 1816 /* Setup the command list entry */ 1817 clp = (struct ahci_cmd_list *) 1818 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1819 clp->cmd_flags = htole16( 1820 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1821 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1822 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1823 (fis_size / sizeof(u_int32_t)) | 1824 (port << 12)); 1825 clp->prd_length = htole16(slot->dma.nsegs); 1826 /* Special handling for Soft Reset command. */ 1827 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1828 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1829 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1830 softreset = 1; 1831 /* Kick controller into sane state */ 1832 ahci_stop(dev); 1833 ahci_clo(dev); 1834 ahci_start(dev, 0); 1835 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1836 } else { 1837 softreset = 2; 1838 /* Prepare FIS receive area for check. */ 1839 for (i = 0; i < 20; i++) 1840 fis[i] = 0xff; 1841 } 1842 } else 1843 softreset = 0; 1844 clp->bytecount = 0; 1845 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1846 (AHCI_CT_SIZE * slot->slot)); 1847 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1848 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1849 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1850 BUS_DMASYNC_PREREAD); 1851 /* Set ACTIVE bit for NCQ commands. */ 1852 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1853 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1854 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1855 } 1856 /* If FBS is enabled, set PMP port. */ 1857 if (ch->fbs_enabled) { 1858 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1859 (port << AHCI_P_FBS_DEV_SHIFT)); 1860 } 1861 /* Issue command to the controller. */ 1862 slot->state = AHCI_SLOT_RUNNING; 1863 ch->rslots |= (1 << slot->slot); 1864 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1865 /* Device reset commands doesn't interrupt. Poll them. */ 1866 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1867 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1868 int count, timeout = ccb->ccb_h.timeout * 100; 1869 enum ahci_err_type et = AHCI_ERR_NONE; 1870 1871 for (count = 0; count < timeout; count++) { 1872 DELAY(10); 1873 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1874 break; 1875 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1876 softreset != 1) { 1877 #if 0 1878 device_printf(ch->dev, 1879 "Poll error on slot %d, TFD: %04x\n", 1880 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1881 #endif 1882 et = AHCI_ERR_TFE; 1883 break; 1884 } 1885 /* Workaround for ATI SB600/SB700 chipsets. */ 1886 if (ccb->ccb_h.target_id == 15 && 1887 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1888 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1889 et = AHCI_ERR_TIMEOUT; 1890 break; 1891 } 1892 } 1893 1894 /* Marvell controllers do not wait for readyness. */ 1895 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1896 et == AHCI_ERR_NONE) { 1897 while ((val = fis[2]) & ATA_S_BUSY) { 1898 DELAY(10); 1899 if (count++ >= timeout) 1900 break; 1901 } 1902 } 1903 1904 if (timeout && (count >= timeout)) { 1905 device_printf(dev, "Poll timeout on slot %d port %d\n", 1906 slot->slot, port); 1907 device_printf(dev, "is %08x cs %08x ss %08x " 1908 "rs %08x tfd %02x serr %08x cmd %08x\n", 1909 ATA_INL(ch->r_mem, AHCI_P_IS), 1910 ATA_INL(ch->r_mem, AHCI_P_CI), 1911 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1912 ATA_INL(ch->r_mem, AHCI_P_TFD), 1913 ATA_INL(ch->r_mem, AHCI_P_SERR), 1914 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1915 et = AHCI_ERR_TIMEOUT; 1916 } 1917 1918 /* Kick controller into sane state and enable FBS. */ 1919 if (softreset == 2) 1920 ch->eslots |= (1 << slot->slot); 1921 ahci_end_transaction(slot, et); 1922 return; 1923 } 1924 /* Start command execution timeout */ 1925 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1926 (timeout_t*)ahci_timeout, slot); 1927 return; 1928 } 1929 1930 /* Must be called with channel locked. */ 1931 static void 1932 ahci_process_timeout(device_t dev) 1933 { 1934 struct ahci_channel *ch = device_get_softc(dev); 1935 int i; 1936 1937 mtx_assert(&ch->mtx, MA_OWNED); 1938 /* Handle the rest of commands. */ 1939 for (i = 0; i < ch->numslots; i++) { 1940 /* Do we have a running request on slot? */ 1941 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1942 continue; 1943 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1944 } 1945 } 1946 1947 /* Must be called with channel locked. */ 1948 static void 1949 ahci_rearm_timeout(device_t dev) 1950 { 1951 struct ahci_channel *ch = device_get_softc(dev); 1952 int i; 1953 1954 mtx_assert(&ch->mtx, MA_OWNED); 1955 for (i = 0; i < ch->numslots; i++) { 1956 struct ahci_slot *slot = &ch->slot[i]; 1957 1958 /* Do we have a running request on slot? */ 1959 if (slot->state < AHCI_SLOT_RUNNING) 1960 continue; 1961 if ((ch->toslots & (1 << i)) == 0) 1962 continue; 1963 callout_reset(&slot->timeout, 1964 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1965 (timeout_t*)ahci_timeout, slot); 1966 } 1967 } 1968 1969 /* Locked by callout mechanism. */ 1970 static void 1971 ahci_timeout(struct ahci_slot *slot) 1972 { 1973 device_t dev = slot->dev; 1974 struct ahci_channel *ch = device_get_softc(dev); 1975 uint32_t sstatus; 1976 int ccs; 1977 int i; 1978 1979 /* Check for stale timeout. */ 1980 if (slot->state < AHCI_SLOT_RUNNING) 1981 return; 1982 1983 /* Check if slot was not being executed last time we checked. */ 1984 if (slot->state < AHCI_SLOT_EXECUTING) { 1985 /* Check if slot started executing. */ 1986 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1987 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1988 >> AHCI_P_CMD_CCS_SHIFT; 1989 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1990 ch->fbs_enabled || ch->wrongccs) 1991 slot->state = AHCI_SLOT_EXECUTING; 1992 else if ((ch->rslots & (1 << ccs)) == 0) { 1993 ch->wrongccs = 1; 1994 slot->state = AHCI_SLOT_EXECUTING; 1995 } 1996 1997 callout_reset(&slot->timeout, 1998 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1999 (timeout_t*)ahci_timeout, slot); 2000 return; 2001 } 2002 2003 device_printf(dev, "Timeout on slot %d port %d\n", 2004 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2005 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2006 "serr %08x cmd %08x\n", 2007 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2008 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2009 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2010 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2011 2012 /* Handle frozen command. */ 2013 if (ch->frozen) { 2014 union ccb *fccb = ch->frozen; 2015 ch->frozen = NULL; 2016 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2017 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2018 xpt_freeze_devq(fccb->ccb_h.path, 1); 2019 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2020 } 2021 xpt_done(fccb); 2022 } 2023 if (!ch->fbs_enabled && !ch->wrongccs) { 2024 /* Without FBS we know real timeout source. */ 2025 ch->fatalerr = 1; 2026 /* Handle command with timeout. */ 2027 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2028 /* Handle the rest of commands. */ 2029 for (i = 0; i < ch->numslots; i++) { 2030 /* Do we have a running request on slot? */ 2031 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2032 continue; 2033 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2034 } 2035 } else { 2036 /* With FBS we wait for other commands timeout and pray. */ 2037 if (ch->toslots == 0) 2038 xpt_freeze_simq(ch->sim, 1); 2039 ch->toslots |= (1 << slot->slot); 2040 if ((ch->rslots & ~ch->toslots) == 0) 2041 ahci_process_timeout(dev); 2042 else 2043 device_printf(dev, " ... waiting for slots %08x\n", 2044 ch->rslots & ~ch->toslots); 2045 } 2046 } 2047 2048 /* Must be called with channel locked. */ 2049 static void 2050 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2051 { 2052 device_t dev = slot->dev; 2053 struct ahci_channel *ch = device_get_softc(dev); 2054 union ccb *ccb = slot->ccb; 2055 struct ahci_cmd_list *clp; 2056 int lastto; 2057 uint32_t sig; 2058 2059 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2060 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2061 clp = (struct ahci_cmd_list *) 2062 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2063 /* Read result registers to the result struct 2064 * May be incorrect if several commands finished same time, 2065 * so read only when sure or have to. 2066 */ 2067 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2068 struct ata_res *res = &ccb->ataio.res; 2069 2070 if ((et == AHCI_ERR_TFE) || 2071 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2072 u_int8_t *fis = ch->dma.rfis + 0x40; 2073 2074 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2075 BUS_DMASYNC_POSTREAD); 2076 if (ch->fbs_enabled) { 2077 fis += ccb->ccb_h.target_id * 256; 2078 res->status = fis[2]; 2079 res->error = fis[3]; 2080 } else { 2081 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2082 2083 res->status = tfd; 2084 res->error = tfd >> 8; 2085 } 2086 res->lba_low = fis[4]; 2087 res->lba_mid = fis[5]; 2088 res->lba_high = fis[6]; 2089 res->device = fis[7]; 2090 res->lba_low_exp = fis[8]; 2091 res->lba_mid_exp = fis[9]; 2092 res->lba_high_exp = fis[10]; 2093 res->sector_count = fis[12]; 2094 res->sector_count_exp = fis[13]; 2095 2096 /* 2097 * Some weird controllers do not return signature in 2098 * FIS receive area. Read it from PxSIG register. 2099 */ 2100 if ((ch->quirks & AHCI_Q_ALTSIG) && 2101 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2102 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2103 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2104 res->lba_high = sig >> 24; 2105 res->lba_mid = sig >> 16; 2106 res->lba_low = sig >> 8; 2107 res->sector_count = sig; 2108 } 2109 } else 2110 bzero(res, sizeof(*res)); 2111 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2112 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2113 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2114 ccb->ataio.resid = 2115 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2116 } 2117 } else { 2118 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2119 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2120 ccb->csio.resid = 2121 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2122 } 2123 } 2124 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2125 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2126 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2127 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2128 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2129 } 2130 if (et != AHCI_ERR_NONE) 2131 ch->eslots |= (1 << slot->slot); 2132 /* In case of error, freeze device for proper recovery. */ 2133 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2134 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2135 xpt_freeze_devq(ccb->ccb_h.path, 1); 2136 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2137 } 2138 /* Set proper result status. */ 2139 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2140 switch (et) { 2141 case AHCI_ERR_NONE: 2142 ccb->ccb_h.status |= CAM_REQ_CMP; 2143 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2144 ccb->csio.scsi_status = SCSI_STATUS_OK; 2145 break; 2146 case AHCI_ERR_INVALID: 2147 ch->fatalerr = 1; 2148 ccb->ccb_h.status |= CAM_REQ_INVALID; 2149 break; 2150 case AHCI_ERR_INNOCENT: 2151 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2152 break; 2153 case AHCI_ERR_TFE: 2154 case AHCI_ERR_NCQ: 2155 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2156 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2157 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2158 } else { 2159 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2160 } 2161 break; 2162 case AHCI_ERR_SATA: 2163 ch->fatalerr = 1; 2164 if (!ch->recoverycmd) { 2165 xpt_freeze_simq(ch->sim, 1); 2166 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2167 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2168 } 2169 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2170 break; 2171 case AHCI_ERR_TIMEOUT: 2172 if (!ch->recoverycmd) { 2173 xpt_freeze_simq(ch->sim, 1); 2174 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2175 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2176 } 2177 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2178 break; 2179 default: 2180 ch->fatalerr = 1; 2181 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2182 } 2183 /* Free slot. */ 2184 ch->oslots &= ~(1 << slot->slot); 2185 ch->rslots &= ~(1 << slot->slot); 2186 ch->aslots &= ~(1 << slot->slot); 2187 slot->state = AHCI_SLOT_EMPTY; 2188 slot->ccb = NULL; 2189 /* Update channel stats. */ 2190 ch->numrslots--; 2191 ch->numrslotspd[ccb->ccb_h.target_id]--; 2192 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2193 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2194 ch->numtslots--; 2195 ch->numtslotspd[ccb->ccb_h.target_id]--; 2196 } 2197 /* Cancel timeout state if request completed normally. */ 2198 if (et != AHCI_ERR_TIMEOUT) { 2199 lastto = (ch->toslots == (1 << slot->slot)); 2200 ch->toslots &= ~(1 << slot->slot); 2201 if (lastto) 2202 xpt_release_simq(ch->sim, TRUE); 2203 } 2204 /* If it was first request of reset sequence and there is no error, 2205 * proceed to second request. */ 2206 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2207 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2208 (ccb->ataio.cmd.control & ATA_A_RESET) && 2209 et == AHCI_ERR_NONE) { 2210 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2211 ahci_begin_transaction(dev, ccb); 2212 return; 2213 } 2214 /* If it was our READ LOG command - process it. */ 2215 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2216 ahci_process_read_log(dev, ccb); 2217 /* If it was our REQUEST SENSE command - process it. */ 2218 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2219 ahci_process_request_sense(dev, ccb); 2220 /* If it was NCQ or ATAPI command error, put result on hold. */ 2221 } else if (et == AHCI_ERR_NCQ || 2222 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2223 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2224 ch->hold[slot->slot] = ccb; 2225 ch->numhslots++; 2226 } else 2227 xpt_done(ccb); 2228 /* If we have no other active commands, ... */ 2229 if (ch->rslots == 0) { 2230 /* if there was fatal error - reset port. */ 2231 if (ch->toslots != 0 || ch->fatalerr) { 2232 ahci_reset(dev); 2233 } else { 2234 /* if we have slots in error, we can reinit port. */ 2235 if (ch->eslots != 0) { 2236 ahci_stop(dev); 2237 ahci_clo(dev); 2238 ahci_start(dev, 1); 2239 } 2240 /* if there commands on hold, we can do READ LOG. */ 2241 if (!ch->recoverycmd && ch->numhslots) 2242 ahci_issue_recovery(dev); 2243 } 2244 /* If all the rest of commands are in timeout - give them chance. */ 2245 } else if ((ch->rslots & ~ch->toslots) == 0 && 2246 et != AHCI_ERR_TIMEOUT) 2247 ahci_rearm_timeout(dev); 2248 /* Unfreeze frozen command. */ 2249 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2250 union ccb *fccb = ch->frozen; 2251 ch->frozen = NULL; 2252 ahci_begin_transaction(dev, fccb); 2253 xpt_release_simq(ch->sim, TRUE); 2254 } 2255 /* Start PM timer. */ 2256 if (ch->numrslots == 0 && ch->pm_level > 3 && 2257 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2258 callout_schedule(&ch->pm_timer, 2259 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2260 } 2261 } 2262 2263 static void 2264 ahci_issue_recovery(device_t dev) 2265 { 2266 struct ahci_channel *ch = device_get_softc(dev); 2267 union ccb *ccb; 2268 struct ccb_ataio *ataio; 2269 struct ccb_scsiio *csio; 2270 int i; 2271 2272 /* Find some held command. */ 2273 for (i = 0; i < ch->numslots; i++) { 2274 if (ch->hold[i]) 2275 break; 2276 } 2277 ccb = xpt_alloc_ccb_nowait(); 2278 if (ccb == NULL) { 2279 device_printf(dev, "Unable to allocate recovery command\n"); 2280 completeall: 2281 /* We can't do anything -- complete held commands. */ 2282 for (i = 0; i < ch->numslots; i++) { 2283 if (ch->hold[i] == NULL) 2284 continue; 2285 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2286 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2287 xpt_done(ch->hold[i]); 2288 ch->hold[i] = NULL; 2289 ch->numhslots--; 2290 } 2291 ahci_reset(dev); 2292 return; 2293 } 2294 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2295 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2296 /* READ LOG */ 2297 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2298 ccb->ccb_h.func_code = XPT_ATA_IO; 2299 ccb->ccb_h.flags = CAM_DIR_IN; 2300 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2301 ataio = &ccb->ataio; 2302 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2303 if (ataio->data_ptr == NULL) { 2304 xpt_free_ccb(ccb); 2305 device_printf(dev, 2306 "Unable to allocate memory for READ LOG command\n"); 2307 goto completeall; 2308 } 2309 ataio->dxfer_len = 512; 2310 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2311 ataio->cmd.flags = CAM_ATAIO_48BIT; 2312 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2313 ataio->cmd.sector_count = 1; 2314 ataio->cmd.sector_count_exp = 0; 2315 ataio->cmd.lba_low = 0x10; 2316 ataio->cmd.lba_mid = 0; 2317 ataio->cmd.lba_mid_exp = 0; 2318 } else { 2319 /* REQUEST SENSE */ 2320 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2321 ccb->ccb_h.recovery_slot = i; 2322 ccb->ccb_h.func_code = XPT_SCSI_IO; 2323 ccb->ccb_h.flags = CAM_DIR_IN; 2324 ccb->ccb_h.status = 0; 2325 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2326 csio = &ccb->csio; 2327 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2328 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2329 csio->cdb_len = 6; 2330 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2331 csio->cdb_io.cdb_bytes[0] = 0x03; 2332 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2333 } 2334 /* Freeze SIM while doing recovery. */ 2335 ch->recoverycmd = 1; 2336 xpt_freeze_simq(ch->sim, 1); 2337 ahci_begin_transaction(dev, ccb); 2338 } 2339 2340 static void 2341 ahci_process_read_log(device_t dev, union ccb *ccb) 2342 { 2343 struct ahci_channel *ch = device_get_softc(dev); 2344 uint8_t *data; 2345 struct ata_res *res; 2346 int i; 2347 2348 ch->recoverycmd = 0; 2349 2350 data = ccb->ataio.data_ptr; 2351 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2352 (data[0] & 0x80) == 0) { 2353 for (i = 0; i < ch->numslots; i++) { 2354 if (!ch->hold[i]) 2355 continue; 2356 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2357 continue; 2358 if ((data[0] & 0x1F) == i) { 2359 res = &ch->hold[i]->ataio.res; 2360 res->status = data[2]; 2361 res->error = data[3]; 2362 res->lba_low = data[4]; 2363 res->lba_mid = data[5]; 2364 res->lba_high = data[6]; 2365 res->device = data[7]; 2366 res->lba_low_exp = data[8]; 2367 res->lba_mid_exp = data[9]; 2368 res->lba_high_exp = data[10]; 2369 res->sector_count = data[12]; 2370 res->sector_count_exp = data[13]; 2371 } else { 2372 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2373 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2374 } 2375 xpt_done(ch->hold[i]); 2376 ch->hold[i] = NULL; 2377 ch->numhslots--; 2378 } 2379 } else { 2380 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2381 device_printf(dev, "Error while READ LOG EXT\n"); 2382 else if ((data[0] & 0x80) == 0) { 2383 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2384 } 2385 for (i = 0; i < ch->numslots; i++) { 2386 if (!ch->hold[i]) 2387 continue; 2388 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2389 continue; 2390 xpt_done(ch->hold[i]); 2391 ch->hold[i] = NULL; 2392 ch->numhslots--; 2393 } 2394 } 2395 free(ccb->ataio.data_ptr, M_AHCI); 2396 xpt_free_ccb(ccb); 2397 xpt_release_simq(ch->sim, TRUE); 2398 } 2399 2400 static void 2401 ahci_process_request_sense(device_t dev, union ccb *ccb) 2402 { 2403 struct ahci_channel *ch = device_get_softc(dev); 2404 int i; 2405 2406 ch->recoverycmd = 0; 2407 2408 i = ccb->ccb_h.recovery_slot; 2409 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2410 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2411 } else { 2412 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2413 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2414 } 2415 xpt_done(ch->hold[i]); 2416 ch->hold[i] = NULL; 2417 ch->numhslots--; 2418 xpt_free_ccb(ccb); 2419 xpt_release_simq(ch->sim, TRUE); 2420 } 2421 2422 static void 2423 ahci_start(device_t dev, int fbs) 2424 { 2425 struct ahci_channel *ch = device_get_softc(dev); 2426 u_int32_t cmd; 2427 2428 /* Clear SATA error register */ 2429 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2430 /* Clear any interrupts pending on this channel */ 2431 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2432 /* Configure FIS-based switching if supported. */ 2433 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2434 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2435 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2436 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2437 } 2438 /* Start operations on this channel */ 2439 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2440 cmd &= ~AHCI_P_CMD_PMA; 2441 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2442 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2443 } 2444 2445 static void 2446 ahci_stop(device_t dev) 2447 { 2448 struct ahci_channel *ch = device_get_softc(dev); 2449 u_int32_t cmd; 2450 int timeout; 2451 2452 /* Kill all activity on this channel */ 2453 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2454 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2455 /* Wait for activity stop. */ 2456 timeout = 0; 2457 do { 2458 DELAY(10); 2459 if (timeout++ > 50000) { 2460 device_printf(dev, "stopping AHCI engine failed\n"); 2461 break; 2462 } 2463 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2464 ch->eslots = 0; 2465 } 2466 2467 static void 2468 ahci_clo(device_t dev) 2469 { 2470 struct ahci_channel *ch = device_get_softc(dev); 2471 u_int32_t cmd; 2472 int timeout; 2473 2474 /* Issue Command List Override if supported */ 2475 if (ch->caps & AHCI_CAP_SCLO) { 2476 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2477 cmd |= AHCI_P_CMD_CLO; 2478 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2479 timeout = 0; 2480 do { 2481 DELAY(10); 2482 if (timeout++ > 50000) { 2483 device_printf(dev, "executing CLO failed\n"); 2484 break; 2485 } 2486 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2487 } 2488 } 2489 2490 static void 2491 ahci_stop_fr(device_t dev) 2492 { 2493 struct ahci_channel *ch = device_get_softc(dev); 2494 u_int32_t cmd; 2495 int timeout; 2496 2497 /* Kill all FIS reception on this channel */ 2498 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2499 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2500 /* Wait for FIS reception stop. */ 2501 timeout = 0; 2502 do { 2503 DELAY(10); 2504 if (timeout++ > 50000) { 2505 device_printf(dev, "stopping AHCI FR engine failed\n"); 2506 break; 2507 } 2508 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2509 } 2510 2511 static void 2512 ahci_start_fr(device_t dev) 2513 { 2514 struct ahci_channel *ch = device_get_softc(dev); 2515 u_int32_t cmd; 2516 2517 /* Start FIS reception on this channel */ 2518 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2519 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2520 } 2521 2522 static int 2523 ahci_wait_ready(device_t dev, int t, int t0) 2524 { 2525 struct ahci_channel *ch = device_get_softc(dev); 2526 int timeout = 0; 2527 uint32_t val; 2528 2529 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2530 (ATA_S_BUSY | ATA_S_DRQ)) { 2531 if (timeout > t) { 2532 if (t != 0) { 2533 device_printf(dev, 2534 "AHCI reset: device not ready after %dms " 2535 "(tfd = %08x)\n", 2536 MAX(t, 0) + t0, val); 2537 } 2538 return (EBUSY); 2539 } 2540 DELAY(1000); 2541 timeout++; 2542 } 2543 if (bootverbose) 2544 device_printf(dev, "AHCI reset: device ready after %dms\n", 2545 timeout + t0); 2546 return (0); 2547 } 2548 2549 static void 2550 ahci_reset_to(void *arg) 2551 { 2552 device_t dev = arg; 2553 struct ahci_channel *ch = device_get_softc(dev); 2554 2555 if (ch->resetting == 0) 2556 return; 2557 ch->resetting--; 2558 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2559 (310 - ch->resetting) * 100) == 0) { 2560 ch->resetting = 0; 2561 ahci_start(dev, 1); 2562 xpt_release_simq(ch->sim, TRUE); 2563 return; 2564 } 2565 if (ch->resetting == 0) { 2566 ahci_clo(dev); 2567 ahci_start(dev, 1); 2568 xpt_release_simq(ch->sim, TRUE); 2569 return; 2570 } 2571 callout_schedule(&ch->reset_timer, hz / 10); 2572 } 2573 2574 static void 2575 ahci_reset(device_t dev) 2576 { 2577 struct ahci_channel *ch = device_get_softc(dev); 2578 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2579 int i; 2580 2581 xpt_freeze_simq(ch->sim, 1); 2582 if (bootverbose) 2583 device_printf(dev, "AHCI reset...\n"); 2584 /* Forget about previous reset. */ 2585 if (ch->resetting) { 2586 ch->resetting = 0; 2587 callout_stop(&ch->reset_timer); 2588 xpt_release_simq(ch->sim, TRUE); 2589 } 2590 /* Requeue freezed command. */ 2591 if (ch->frozen) { 2592 union ccb *fccb = ch->frozen; 2593 ch->frozen = NULL; 2594 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2595 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2596 xpt_freeze_devq(fccb->ccb_h.path, 1); 2597 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2598 } 2599 xpt_done(fccb); 2600 } 2601 /* Kill the engine and requeue all running commands. */ 2602 ahci_stop(dev); 2603 for (i = 0; i < ch->numslots; i++) { 2604 /* Do we have a running request on slot? */ 2605 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2606 continue; 2607 /* XXX; Commands in loading state. */ 2608 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2609 } 2610 for (i = 0; i < ch->numslots; i++) { 2611 if (!ch->hold[i]) 2612 continue; 2613 xpt_done(ch->hold[i]); 2614 ch->hold[i] = NULL; 2615 ch->numhslots--; 2616 } 2617 if (ch->toslots != 0) 2618 xpt_release_simq(ch->sim, TRUE); 2619 ch->eslots = 0; 2620 ch->toslots = 0; 2621 ch->wrongccs = 0; 2622 ch->fatalerr = 0; 2623 /* Tell the XPT about the event */ 2624 xpt_async(AC_BUS_RESET, ch->path, NULL); 2625 /* Disable port interrupts */ 2626 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2627 /* Reset and reconnect PHY, */ 2628 if (!ahci_sata_phy_reset(dev)) { 2629 if (bootverbose) 2630 device_printf(dev, 2631 "AHCI reset: device not found\n"); 2632 ch->devices = 0; 2633 /* Enable wanted port interrupts */ 2634 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2635 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2636 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2637 xpt_release_simq(ch->sim, TRUE); 2638 return; 2639 } 2640 if (bootverbose) 2641 device_printf(dev, "AHCI reset: device found\n"); 2642 /* Wait for clearing busy status. */ 2643 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2644 if (dumping) 2645 ahci_clo(dev); 2646 else 2647 ch->resetting = 310; 2648 } 2649 ch->devices = 1; 2650 /* Enable wanted port interrupts */ 2651 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2652 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2653 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2654 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2655 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2656 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2657 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2658 if (ch->resetting) 2659 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2660 else { 2661 ahci_start(dev, 1); 2662 xpt_release_simq(ch->sim, TRUE); 2663 } 2664 } 2665 2666 static int 2667 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2668 { 2669 struct ahci_channel *ch = device_get_softc(dev); 2670 u_int8_t *fis = &ctp->cfis[0]; 2671 2672 bzero(ctp->cfis, 64); 2673 fis[0] = 0x27; /* host to device */ 2674 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2675 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2676 fis[1] |= 0x80; 2677 fis[2] = ATA_PACKET_CMD; 2678 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2679 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2680 fis[3] = ATA_F_DMA; 2681 else { 2682 fis[5] = ccb->csio.dxfer_len; 2683 fis[6] = ccb->csio.dxfer_len >> 8; 2684 } 2685 fis[7] = ATA_D_LBA; 2686 fis[15] = ATA_A_4BIT; 2687 bzero(ctp->acmd, 32); 2688 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2689 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2690 ctp->acmd, ccb->csio.cdb_len); 2691 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2692 fis[1] |= 0x80; 2693 fis[2] = ccb->ataio.cmd.command; 2694 fis[3] = ccb->ataio.cmd.features; 2695 fis[4] = ccb->ataio.cmd.lba_low; 2696 fis[5] = ccb->ataio.cmd.lba_mid; 2697 fis[6] = ccb->ataio.cmd.lba_high; 2698 fis[7] = ccb->ataio.cmd.device; 2699 fis[8] = ccb->ataio.cmd.lba_low_exp; 2700 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2701 fis[10] = ccb->ataio.cmd.lba_high_exp; 2702 fis[11] = ccb->ataio.cmd.features_exp; 2703 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2704 fis[12] = tag << 3; 2705 fis[13] = 0; 2706 } else { 2707 fis[12] = ccb->ataio.cmd.sector_count; 2708 fis[13] = ccb->ataio.cmd.sector_count_exp; 2709 } 2710 fis[15] = ATA_A_4BIT; 2711 } else { 2712 fis[15] = ccb->ataio.cmd.control; 2713 } 2714 return (20); 2715 } 2716 2717 static int 2718 ahci_sata_connect(struct ahci_channel *ch) 2719 { 2720 u_int32_t status; 2721 int timeout, found = 0; 2722 2723 /* Wait up to 100ms for "connect well" */ 2724 for (timeout = 0; timeout < 1000 ; timeout++) { 2725 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2726 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2727 found = 1; 2728 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2729 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2730 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2731 break; 2732 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2733 if (bootverbose) { 2734 device_printf(ch->dev, "SATA offline status=%08x\n", 2735 status); 2736 } 2737 return (0); 2738 } 2739 if (found == 0 && timeout >= 100) 2740 break; 2741 DELAY(100); 2742 } 2743 if (timeout >= 1000 || !found) { 2744 if (bootverbose) { 2745 device_printf(ch->dev, 2746 "SATA connect timeout time=%dus status=%08x\n", 2747 timeout * 100, status); 2748 } 2749 return (0); 2750 } 2751 if (bootverbose) { 2752 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2753 timeout * 100, status); 2754 } 2755 /* Clear SATA error register */ 2756 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2757 return (1); 2758 } 2759 2760 static int 2761 ahci_sata_phy_reset(device_t dev) 2762 { 2763 struct ahci_channel *ch = device_get_softc(dev); 2764 int sata_rev; 2765 uint32_t val; 2766 2767 if (ch->listening) { 2768 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2769 val |= AHCI_P_CMD_SUD; 2770 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2771 ch->listening = 0; 2772 } 2773 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2774 if (sata_rev == 1) 2775 val = ATA_SC_SPD_SPEED_GEN1; 2776 else if (sata_rev == 2) 2777 val = ATA_SC_SPD_SPEED_GEN2; 2778 else if (sata_rev == 3) 2779 val = ATA_SC_SPD_SPEED_GEN3; 2780 else 2781 val = 0; 2782 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2783 ATA_SC_DET_RESET | val | 2784 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2785 DELAY(1000); 2786 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2787 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2788 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2789 if (!ahci_sata_connect(ch)) { 2790 if (ch->caps & AHCI_CAP_SSS) { 2791 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2792 val &= ~AHCI_P_CMD_SUD; 2793 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2794 ch->listening = 1; 2795 } else if (ch->pm_level > 0) 2796 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2797 return (0); 2798 } 2799 return (1); 2800 } 2801 2802 static int 2803 ahci_check_ids(device_t dev, union ccb *ccb) 2804 { 2805 struct ahci_channel *ch = device_get_softc(dev); 2806 2807 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2808 ccb->ccb_h.status = CAM_TID_INVALID; 2809 xpt_done(ccb); 2810 return (-1); 2811 } 2812 if (ccb->ccb_h.target_lun != 0) { 2813 ccb->ccb_h.status = CAM_LUN_INVALID; 2814 xpt_done(ccb); 2815 return (-1); 2816 } 2817 return (0); 2818 } 2819 2820 static void 2821 ahciaction(struct cam_sim *sim, union ccb *ccb) 2822 { 2823 device_t dev; 2824 struct ahci_channel *ch; 2825 2826 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2827 ccb->ccb_h.func_code)); 2828 2829 ch = (struct ahci_channel *)cam_sim_softc(sim); 2830 dev = ch->dev; 2831 switch (ccb->ccb_h.func_code) { 2832 /* Common cases first */ 2833 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2834 case XPT_SCSI_IO: 2835 if (ahci_check_ids(dev, ccb)) 2836 return; 2837 if (ch->devices == 0 || 2838 (ch->pm_present == 0 && 2839 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2840 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2841 break; 2842 } 2843 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2844 /* Check for command collision. */ 2845 if (ahci_check_collision(dev, ccb)) { 2846 /* Freeze command. */ 2847 ch->frozen = ccb; 2848 /* We have only one frozen slot, so freeze simq also. */ 2849 xpt_freeze_simq(ch->sim, 1); 2850 return; 2851 } 2852 ahci_begin_transaction(dev, ccb); 2853 return; 2854 case XPT_EN_LUN: /* Enable LUN as a target */ 2855 case XPT_TARGET_IO: /* Execute target I/O request */ 2856 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2857 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2858 case XPT_ABORT: /* Abort the specified CCB */ 2859 /* XXX Implement */ 2860 ccb->ccb_h.status = CAM_REQ_INVALID; 2861 break; 2862 case XPT_SET_TRAN_SETTINGS: 2863 { 2864 struct ccb_trans_settings *cts = &ccb->cts; 2865 struct ahci_device *d; 2866 2867 if (ahci_check_ids(dev, ccb)) 2868 return; 2869 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2870 d = &ch->curr[ccb->ccb_h.target_id]; 2871 else 2872 d = &ch->user[ccb->ccb_h.target_id]; 2873 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2874 d->revision = cts->xport_specific.sata.revision; 2875 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2876 d->mode = cts->xport_specific.sata.mode; 2877 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2878 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2879 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2880 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2881 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2882 ch->pm_present = cts->xport_specific.sata.pm_present; 2883 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2884 d->atapi = cts->xport_specific.sata.atapi; 2885 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2886 d->caps = cts->xport_specific.sata.caps; 2887 ccb->ccb_h.status = CAM_REQ_CMP; 2888 break; 2889 } 2890 case XPT_GET_TRAN_SETTINGS: 2891 /* Get default/user set transfer settings for the target */ 2892 { 2893 struct ccb_trans_settings *cts = &ccb->cts; 2894 struct ahci_device *d; 2895 uint32_t status; 2896 2897 if (ahci_check_ids(dev, ccb)) 2898 return; 2899 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2900 d = &ch->curr[ccb->ccb_h.target_id]; 2901 else 2902 d = &ch->user[ccb->ccb_h.target_id]; 2903 cts->protocol = PROTO_UNSPECIFIED; 2904 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2905 cts->transport = XPORT_SATA; 2906 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2907 cts->proto_specific.valid = 0; 2908 cts->xport_specific.sata.valid = 0; 2909 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2910 (ccb->ccb_h.target_id == 15 || 2911 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2912 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2913 if (status & 0x0f0) { 2914 cts->xport_specific.sata.revision = 2915 (status & 0x0f0) >> 4; 2916 cts->xport_specific.sata.valid |= 2917 CTS_SATA_VALID_REVISION; 2918 } 2919 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2920 if (ch->pm_level) { 2921 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2922 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2923 if (ch->caps2 & AHCI_CAP2_APST) 2924 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2925 } 2926 if ((ch->caps & AHCI_CAP_SNCQ) && 2927 (ch->quirks & AHCI_Q_NOAA) == 0) 2928 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2929 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2930 cts->xport_specific.sata.caps &= 2931 ch->user[ccb->ccb_h.target_id].caps; 2932 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2933 } else { 2934 cts->xport_specific.sata.revision = d->revision; 2935 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2936 cts->xport_specific.sata.caps = d->caps; 2937 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2938 } 2939 cts->xport_specific.sata.mode = d->mode; 2940 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2941 cts->xport_specific.sata.bytecount = d->bytecount; 2942 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2943 cts->xport_specific.sata.pm_present = ch->pm_present; 2944 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2945 cts->xport_specific.sata.tags = d->tags; 2946 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2947 cts->xport_specific.sata.atapi = d->atapi; 2948 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2949 ccb->ccb_h.status = CAM_REQ_CMP; 2950 break; 2951 } 2952 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2953 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2954 ahci_reset(dev); 2955 ccb->ccb_h.status = CAM_REQ_CMP; 2956 break; 2957 case XPT_TERM_IO: /* Terminate the I/O process */ 2958 /* XXX Implement */ 2959 ccb->ccb_h.status = CAM_REQ_INVALID; 2960 break; 2961 case XPT_PATH_INQ: /* Path routing inquiry */ 2962 { 2963 struct ccb_pathinq *cpi = &ccb->cpi; 2964 2965 cpi->version_num = 1; /* XXX??? */ 2966 cpi->hba_inquiry = PI_SDTR_ABLE; 2967 if (ch->caps & AHCI_CAP_SNCQ) 2968 cpi->hba_inquiry |= PI_TAG_ABLE; 2969 if (ch->caps & AHCI_CAP_SPM) 2970 cpi->hba_inquiry |= PI_SATAPM; 2971 cpi->target_sprt = 0; 2972 cpi->hba_misc = PIM_SEQSCAN; 2973 cpi->hba_eng_cnt = 0; 2974 if (ch->caps & AHCI_CAP_SPM) 2975 cpi->max_target = 15; 2976 else 2977 cpi->max_target = 0; 2978 cpi->max_lun = 0; 2979 cpi->initiator_id = 0; 2980 cpi->bus_id = cam_sim_bus(sim); 2981 cpi->base_transfer_speed = 150000; 2982 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2983 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2984 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2985 cpi->unit_number = cam_sim_unit(sim); 2986 cpi->transport = XPORT_SATA; 2987 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2988 cpi->protocol = PROTO_ATA; 2989 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2990 cpi->maxio = MAXPHYS; 2991 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2992 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2993 cpi->maxio = min(cpi->maxio, 128 * 512); 2994 cpi->ccb_h.status = CAM_REQ_CMP; 2995 break; 2996 } 2997 default: 2998 ccb->ccb_h.status = CAM_REQ_INVALID; 2999 break; 3000 } 3001 xpt_done(ccb); 3002 } 3003 3004 static void 3005 ahcipoll(struct cam_sim *sim) 3006 { 3007 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3008 3009 ahci_ch_intr(ch->dev); 3010 if (ch->resetting != 0 && 3011 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3012 ch->resetpolldiv = 1000; 3013 ahci_reset_to(ch->dev); 3014 } 3015 }
Cache object: a6ee512711f0699351335f543e38a0a8
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]