Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ahci/ahci.c
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1 /*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/led/led.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include "ahci.h" 52 53 #include <cam/cam.h> 54 #include <cam/cam_ccb.h> 55 #include <cam/cam_sim.h> 56 #include <cam/cam_xpt_sim.h> 57 #include <cam/cam_debug.h> 58 59 /* local prototypes */ 60 static int ahci_setup_interrupt(device_t dev); 61 static void ahci_intr(void *data); 62 static void ahci_intr_one(void *data); 63 static int ahci_suspend(device_t dev); 64 static int ahci_resume(device_t dev); 65 static int ahci_ch_init(device_t dev); 66 static int ahci_ch_deinit(device_t dev); 67 static int ahci_ch_suspend(device_t dev); 68 static int ahci_ch_resume(device_t dev); 69 static void ahci_ch_pm(void *arg); 70 static void ahci_ch_intr_locked(void *data); 71 static void ahci_ch_intr(void *data); 72 static void ahci_ch_led(void *priv, int onoff); 73 static int ahci_ctlr_reset(device_t dev); 74 static int ahci_ctlr_setup(device_t dev); 75 static void ahci_begin_transaction(device_t dev, union ccb *ccb); 76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 77 static void ahci_execute_transaction(struct ahci_slot *slot); 78 static void ahci_timeout(struct ahci_slot *slot); 79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 81 static void ahci_dmainit(device_t dev); 82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 83 static void ahci_dmafini(device_t dev); 84 static void ahci_slotsalloc(device_t dev); 85 static void ahci_slotsfree(device_t dev); 86 static void ahci_reset(device_t dev); 87 static void ahci_start(device_t dev, int fbs); 88 static void ahci_stop(device_t dev); 89 static void ahci_clo(device_t dev); 90 static void ahci_start_fr(device_t dev); 91 static void ahci_stop_fr(device_t dev); 92 93 static int ahci_sata_connect(struct ahci_channel *ch); 94 static int ahci_sata_phy_reset(device_t dev); 95 static int ahci_wait_ready(device_t dev, int t, int t0); 96 97 static void ahci_issue_recovery(device_t dev); 98 static void ahci_process_read_log(device_t dev, union ccb *ccb); 99 static void ahci_process_request_sense(device_t dev, union ccb *ccb); 100 101 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 102 static void ahcipoll(struct cam_sim *sim); 103 104 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 105 106 static struct { 107 uint32_t id; 108 uint8_t rev; 109 const char *name; 110 int quirks; 111 #define AHCI_Q_NOFORCE 1 112 #define AHCI_Q_NOPMP 2 113 #define AHCI_Q_NONCQ 4 114 #define AHCI_Q_1CH 8 115 #define AHCI_Q_2CH 16 116 #define AHCI_Q_4CH 32 117 #define AHCI_Q_EDGEIS 64 118 #define AHCI_Q_SATA2 128 119 #define AHCI_Q_NOBSYRES 256 120 #define AHCI_Q_NOAA 512 121 #define AHCI_Q_NOCOUNT 1024 122 #define AHCI_Q_ALTSIG 2048 123 #define AHCI_Q_NOMSI 4096 124 125 #define AHCI_Q_BIT_STRING \ 126 "\020" \ 127 "\001NOFORCE" \ 128 "\002NOPMP" \ 129 "\003NONCQ" \ 130 "\0041CH" \ 131 "\0052CH" \ 132 "\0064CH" \ 133 "\007EDGEIS" \ 134 "\010SATA2" \ 135 "\011NOBSYRES" \ 136 "\012NOAA" \ 137 "\013NOCOUNT" \ 138 "\014ALTSIG" \ 139 "\015NOMSI" 140 } ahci_ids[] = { 141 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI}, 142 {0x43901002, 0x00, "ATI IXP700", 0}, 143 {0x43911002, 0x00, "ATI IXP700", 0}, 144 {0x43921002, 0x00, "ATI IXP700", 0}, 145 {0x43931002, 0x00, "ATI IXP700", 0}, 146 {0x43941002, 0x00, "ATI IXP800", 0}, 147 {0x43951002, 0x00, "ATI IXP800", 0}, 148 {0x78001022, 0x00, "AMD Hudson-2", 0}, 149 {0x78011022, 0x00, "AMD Hudson-2", 0}, 150 {0x78021022, 0x00, "AMD Hudson-2", 0}, 151 {0x78031022, 0x00, "AMD Hudson-2", 0}, 152 {0x78041022, 0x00, "AMD Hudson-2", 0}, 153 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 154 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 155 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 156 {0x26818086, 0x00, "Intel ESB2", 0}, 157 {0x26828086, 0x00, "Intel ESB2", 0}, 158 {0x26838086, 0x00, "Intel ESB2", 0}, 159 {0x27c18086, 0x00, "Intel ICH7", 0}, 160 {0x27c38086, 0x00, "Intel ICH7", 0}, 161 {0x27c58086, 0x00, "Intel ICH7M", 0}, 162 {0x27c68086, 0x00, "Intel ICH7M", 0}, 163 {0x28218086, 0x00, "Intel ICH8", 0}, 164 {0x28228086, 0x00, "Intel ICH8", 0}, 165 {0x28248086, 0x00, "Intel ICH8", 0}, 166 {0x28298086, 0x00, "Intel ICH8M", 0}, 167 {0x282a8086, 0x00, "Intel ICH8M", 0}, 168 {0x29228086, 0x00, "Intel ICH9", 0}, 169 {0x29238086, 0x00, "Intel ICH9", 0}, 170 {0x29248086, 0x00, "Intel ICH9", 0}, 171 {0x29258086, 0x00, "Intel ICH9", 0}, 172 {0x29278086, 0x00, "Intel ICH9", 0}, 173 {0x29298086, 0x00, "Intel ICH9M", 0}, 174 {0x292a8086, 0x00, "Intel ICH9M", 0}, 175 {0x292b8086, 0x00, "Intel ICH9M", 0}, 176 {0x292c8086, 0x00, "Intel ICH9M", 0}, 177 {0x292f8086, 0x00, "Intel ICH9M", 0}, 178 {0x294d8086, 0x00, "Intel ICH9", 0}, 179 {0x294e8086, 0x00, "Intel ICH9M", 0}, 180 {0x3a058086, 0x00, "Intel ICH10", 0}, 181 {0x3a228086, 0x00, "Intel ICH10", 0}, 182 {0x3a258086, 0x00, "Intel ICH10", 0}, 183 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 184 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 185 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 186 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 187 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 188 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 189 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 190 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 191 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 192 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 193 {0x1d028086, 0x00, "Intel Patsburg", 0}, 194 {0x1d048086, 0x00, "Intel Patsburg", 0}, 195 {0x1d068086, 0x00, "Intel Patsburg", 0}, 196 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 197 {0x1e028086, 0x00, "Intel Panther Point", 0}, 198 {0x1e038086, 0x00, "Intel Panther Point", 0}, 199 {0x1e048086, 0x00, "Intel Panther Point", 0}, 200 {0x1e058086, 0x00, "Intel Panther Point", 0}, 201 {0x1e068086, 0x00, "Intel Panther Point", 0}, 202 {0x1e078086, 0x00, "Intel Panther Point", 0}, 203 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 204 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 205 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 206 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 207 {0x8c048086, 0x00, "Intel Lynx Point", 0}, 208 {0x8c058086, 0x00, "Intel Lynx Point", 0}, 209 {0x8c068086, 0x00, "Intel Lynx Point", 0}, 210 {0x8c078086, 0x00, "Intel Lynx Point", 0}, 211 {0x8c0e8086, 0x00, "Intel Lynx Point", 0}, 212 {0x8c0f8086, 0x00, "Intel Lynx Point", 0}, 213 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 214 {0x2360197b, 0x00, "JMicron JMB360", 0}, 215 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 216 {0x2362197b, 0x00, "JMicron JMB362", 0}, 217 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 218 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 219 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 220 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 221 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 222 AHCI_Q_EDGEIS}, 223 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 224 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 225 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 226 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 227 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 228 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 229 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 230 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 231 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 232 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 233 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 234 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 235 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 236 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 237 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 238 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 239 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 240 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 241 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 242 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 243 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 244 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 245 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 246 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 247 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 248 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES}, 249 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES}, 250 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES}, 251 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 252 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 253 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 254 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 255 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 256 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 257 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 258 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 259 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 260 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 261 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 262 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 263 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 264 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 265 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 266 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 267 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 268 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 269 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 270 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 271 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 272 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 273 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 274 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 275 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 276 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 277 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 278 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 279 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 280 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 281 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 282 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 283 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 284 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 285 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 286 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 287 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 288 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 289 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 290 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 291 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 292 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 293 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 294 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 295 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 296 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 297 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 298 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 299 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 300 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 301 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 302 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 303 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 304 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 305 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 306 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 307 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 308 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 309 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 310 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 311 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 312 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 313 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 314 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 315 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 316 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 317 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 318 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 319 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 320 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 321 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 322 {0x11841039, 0x00, "SiS 966", 0}, 323 {0x11851039, 0x00, "SiS 968", 0}, 324 {0x01861039, 0x00, "SiS 968", 0}, 325 {0x00000000, 0x00, NULL, 0} 326 }; 327 328 #define recovery_type spriv_field0 329 #define RECOVERY_NONE 0 330 #define RECOVERY_READ_LOG 1 331 #define RECOVERY_REQUEST_SENSE 2 332 #define recovery_slot spriv_field1 333 334 static int force_ahci = 1; 335 TUNABLE_INT("hw.ahci.force", &force_ahci); 336 337 static int 338 ahci_probe(device_t dev) 339 { 340 char buf[64]; 341 int i, valid = 0; 342 uint32_t devid = pci_get_devid(dev); 343 uint8_t revid = pci_get_revid(dev); 344 345 /* Is this a possible AHCI candidate? */ 346 if (pci_get_class(dev) == PCIC_STORAGE && 347 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 348 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 349 valid = 1; 350 /* Is this a known AHCI chip? */ 351 for (i = 0; ahci_ids[i].id != 0; i++) { 352 if (ahci_ids[i].id == devid && 353 ahci_ids[i].rev <= revid && 354 (valid || (force_ahci == 1 && 355 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 356 /* Do not attach JMicrons with single PCI function. */ 357 if (pci_get_vendor(dev) == 0x197b && 358 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 359 return (ENXIO); 360 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 361 ahci_ids[i].name); 362 device_set_desc_copy(dev, buf); 363 return (BUS_PROBE_VENDOR); 364 } 365 } 366 if (!valid) 367 return (ENXIO); 368 device_set_desc_copy(dev, "AHCI SATA controller"); 369 return (BUS_PROBE_VENDOR); 370 } 371 372 static int 373 ahci_ata_probe(device_t dev) 374 { 375 char buf[64]; 376 int i; 377 uint32_t devid = pci_get_devid(dev); 378 uint8_t revid = pci_get_revid(dev); 379 380 if ((intptr_t)device_get_ivars(dev) >= 0) 381 return (ENXIO); 382 /* Is this a known AHCI chip? */ 383 for (i = 0; ahci_ids[i].id != 0; i++) { 384 if (ahci_ids[i].id == devid && 385 ahci_ids[i].rev <= revid) { 386 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 387 ahci_ids[i].name); 388 device_set_desc_copy(dev, buf); 389 return (BUS_PROBE_VENDOR); 390 } 391 } 392 device_set_desc_copy(dev, "AHCI SATA controller"); 393 return (BUS_PROBE_VENDOR); 394 } 395 396 static int 397 ahci_attach(device_t dev) 398 { 399 struct ahci_controller *ctlr = device_get_softc(dev); 400 device_t child; 401 int error, unit, speed, i; 402 uint32_t devid = pci_get_devid(dev); 403 uint8_t revid = pci_get_revid(dev); 404 u_int32_t version; 405 406 ctlr->dev = dev; 407 i = 0; 408 while (ahci_ids[i].id != 0 && 409 (ahci_ids[i].id != devid || 410 ahci_ids[i].rev > revid)) 411 i++; 412 ctlr->quirks = ahci_ids[i].quirks; 413 resource_int_value(device_get_name(dev), 414 device_get_unit(dev), "ccc", &ctlr->ccc); 415 /* if we have a memory BAR(5) we are likely on an AHCI part */ 416 ctlr->r_rid = PCIR_BAR(5); 417 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 418 &ctlr->r_rid, RF_ACTIVE))) 419 return ENXIO; 420 /* Setup our own memory management for channels. */ 421 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 422 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 423 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 424 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 425 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 426 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 427 return (error); 428 } 429 if ((error = rman_manage_region(&ctlr->sc_iomem, 430 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 431 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 432 rman_fini(&ctlr->sc_iomem); 433 return (error); 434 } 435 pci_enable_busmaster(dev); 436 /* Reset controller */ 437 if ((error = ahci_ctlr_reset(dev)) != 0) { 438 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 439 rman_fini(&ctlr->sc_iomem); 440 return (error); 441 }; 442 /* Get the HW capabilities */ 443 version = ATA_INL(ctlr->r_mem, AHCI_VS); 444 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 445 if (version >= 0x00010200) 446 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 447 if (ctlr->caps & AHCI_CAP_EMS) 448 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 449 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 450 451 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 452 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 453 (ctlr->quirks & AHCI_Q_ALTSIG) && 454 (ctlr->caps & AHCI_CAP_SPM) == 0) 455 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 456 457 if (ctlr->quirks & AHCI_Q_1CH) { 458 ctlr->caps &= ~AHCI_CAP_NPMASK; 459 ctlr->ichannels &= 0x01; 460 } 461 if (ctlr->quirks & AHCI_Q_2CH) { 462 ctlr->caps &= ~AHCI_CAP_NPMASK; 463 ctlr->caps |= 1; 464 ctlr->ichannels &= 0x03; 465 } 466 if (ctlr->quirks & AHCI_Q_4CH) { 467 ctlr->caps &= ~AHCI_CAP_NPMASK; 468 ctlr->caps |= 3; 469 ctlr->ichannels &= 0x0f; 470 } 471 ctlr->channels = MAX(flsl(ctlr->ichannels), 472 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 473 if (ctlr->quirks & AHCI_Q_NOPMP) 474 ctlr->caps &= ~AHCI_CAP_SPM; 475 if (ctlr->quirks & AHCI_Q_NONCQ) 476 ctlr->caps &= ~AHCI_CAP_SNCQ; 477 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 478 ctlr->ccc = 0; 479 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF); 480 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 481 ahci_ctlr_setup(dev); 482 /* Setup interrupts. */ 483 if (ahci_setup_interrupt(dev)) { 484 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 485 rman_fini(&ctlr->sc_iomem); 486 return ENXIO; 487 } 488 /* Announce HW capabilities. */ 489 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 490 device_printf(dev, 491 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 492 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 493 ((version >> 4) & 0xf0) + (version & 0x0f), 494 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 495 ((speed == 1) ? "1.5":((speed == 2) ? "3": 496 ((speed == 3) ? "6":"?"))), 497 (ctlr->caps & AHCI_CAP_SPM) ? 498 "supported" : "not supported", 499 (ctlr->caps & AHCI_CAP_FBSS) ? 500 " with FBS" : ""); 501 if (ctlr->quirks != 0) { 502 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 503 AHCI_Q_BIT_STRING); 504 } 505 if (bootverbose) { 506 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 507 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 508 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 509 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 510 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 511 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 512 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 513 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 514 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 515 ((speed == 1) ? "1.5":((speed == 2) ? "3": 516 ((speed == 3) ? "6":"?")))); 517 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 518 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 519 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 520 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 521 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 522 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 523 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 524 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 525 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 526 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 527 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 528 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 529 } 530 if (bootverbose && version >= 0x00010200) { 531 device_printf(dev, "Caps2:%s%s%s\n", 532 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 533 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 534 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 535 } 536 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 537 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 538 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 539 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 540 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 541 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 542 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 543 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 544 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 545 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 546 } 547 /* Attach all channels on this controller */ 548 for (unit = 0; unit < ctlr->channels; unit++) { 549 child = device_add_child(dev, "ahcich", -1); 550 if (child == NULL) { 551 device_printf(dev, "failed to add channel device\n"); 552 continue; 553 } 554 device_set_ivars(child, (void *)(intptr_t)unit); 555 if ((ctlr->ichannels & (1 << unit)) == 0) 556 device_disable(child); 557 } 558 bus_generic_attach(dev); 559 return 0; 560 } 561 562 static int 563 ahci_detach(device_t dev) 564 { 565 struct ahci_controller *ctlr = device_get_softc(dev); 566 device_t *children; 567 int nchildren, i; 568 569 /* Detach & delete all children */ 570 if (!device_get_children(dev, &children, &nchildren)) { 571 for (i = 0; i < nchildren; i++) 572 device_delete_child(dev, children[i]); 573 free(children, M_TEMP); 574 } 575 /* Free interrupts. */ 576 for (i = 0; i < ctlr->numirqs; i++) { 577 if (ctlr->irqs[i].r_irq) { 578 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 579 ctlr->irqs[i].handle); 580 bus_release_resource(dev, SYS_RES_IRQ, 581 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 582 } 583 } 584 pci_release_msi(dev); 585 /* Free memory. */ 586 rman_fini(&ctlr->sc_iomem); 587 if (ctlr->r_mem) 588 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 589 mtx_destroy(&ctlr->em_mtx); 590 return (0); 591 } 592 593 static int 594 ahci_ctlr_reset(device_t dev) 595 { 596 struct ahci_controller *ctlr = device_get_softc(dev); 597 int timeout; 598 599 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 600 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 601 pci_write_config(dev, 0x92, 0x01, 1); 602 /* Enable AHCI mode */ 603 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 604 /* Reset AHCI controller */ 605 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 606 for (timeout = 1000; timeout > 0; timeout--) { 607 DELAY(1000); 608 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 609 break; 610 } 611 if (timeout == 0) { 612 device_printf(dev, "AHCI controller reset failure\n"); 613 return ENXIO; 614 } 615 /* Reenable AHCI mode */ 616 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 617 return (0); 618 } 619 620 static int 621 ahci_ctlr_setup(device_t dev) 622 { 623 struct ahci_controller *ctlr = device_get_softc(dev); 624 /* Clear interrupts */ 625 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 626 /* Configure CCC */ 627 if (ctlr->ccc) { 628 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 629 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 630 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 631 (4 << AHCI_CCCC_CC_SHIFT) | 632 AHCI_CCCC_EN); 633 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 634 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 635 if (bootverbose) { 636 device_printf(dev, 637 "CCC with %dms/4cmd enabled on vector %d\n", 638 ctlr->ccc, ctlr->cccv); 639 } 640 } 641 /* Enable AHCI interrupts */ 642 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 643 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 644 return (0); 645 } 646 647 static int 648 ahci_suspend(device_t dev) 649 { 650 struct ahci_controller *ctlr = device_get_softc(dev); 651 652 bus_generic_suspend(dev); 653 /* Disable interupts, so the state change(s) doesn't trigger */ 654 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 655 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 656 return 0; 657 } 658 659 static int 660 ahci_resume(device_t dev) 661 { 662 int res; 663 664 if ((res = ahci_ctlr_reset(dev)) != 0) 665 return (res); 666 ahci_ctlr_setup(dev); 667 return (bus_generic_resume(dev)); 668 } 669 670 static int 671 ahci_setup_interrupt(device_t dev) 672 { 673 struct ahci_controller *ctlr = device_get_softc(dev); 674 int i, msi = 1; 675 676 /* Process hints. */ 677 if (ctlr->quirks & AHCI_Q_NOMSI) 678 msi = 0; 679 resource_int_value(device_get_name(dev), 680 device_get_unit(dev), "msi", &msi); 681 if (msi < 0) 682 msi = 0; 683 else if (msi == 1) 684 msi = min(1, pci_msi_count(dev)); 685 else if (msi > 1) 686 msi = pci_msi_count(dev); 687 /* Allocate MSI if needed/present. */ 688 if (msi && pci_alloc_msi(dev, &msi) == 0) { 689 ctlr->numirqs = msi; 690 } else { 691 msi = 0; 692 ctlr->numirqs = 1; 693 } 694 /* Check for single MSI vector fallback. */ 695 if (ctlr->numirqs > 1 && 696 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 697 device_printf(dev, "Falling back to one MSI\n"); 698 ctlr->numirqs = 1; 699 } 700 /* Allocate all IRQs. */ 701 for (i = 0; i < ctlr->numirqs; i++) { 702 ctlr->irqs[i].ctlr = ctlr; 703 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 704 if (ctlr->numirqs == 1 || i >= ctlr->channels || 705 (ctlr->ccc && i == ctlr->cccv)) 706 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 707 else if (i == ctlr->numirqs - 1) 708 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 709 else 710 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 711 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 712 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 713 device_printf(dev, "unable to map interrupt\n"); 714 return ENXIO; 715 } 716 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 717 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 718 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 719 /* SOS XXX release r_irq */ 720 device_printf(dev, "unable to setup interrupt\n"); 721 return ENXIO; 722 } 723 } 724 return (0); 725 } 726 727 /* 728 * Common case interrupt handler. 729 */ 730 static void 731 ahci_intr(void *data) 732 { 733 struct ahci_controller_irq *irq = data; 734 struct ahci_controller *ctlr = irq->ctlr; 735 u_int32_t is, ise = 0; 736 void *arg; 737 int unit; 738 739 if (irq->mode == AHCI_IRQ_MODE_ALL) { 740 unit = 0; 741 if (ctlr->ccc) 742 is = ctlr->ichannels; 743 else 744 is = ATA_INL(ctlr->r_mem, AHCI_IS); 745 } else { /* AHCI_IRQ_MODE_AFTER */ 746 unit = irq->r_irq_rid - 1; 747 is = ATA_INL(ctlr->r_mem, AHCI_IS); 748 } 749 /* CCC interrupt is edge triggered. */ 750 if (ctlr->ccc) 751 ise = 1 << ctlr->cccv; 752 /* Some controllers have edge triggered IS. */ 753 if (ctlr->quirks & AHCI_Q_EDGEIS) 754 ise |= is; 755 if (ise != 0) 756 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 757 for (; unit < ctlr->channels; unit++) { 758 if ((is & (1 << unit)) != 0 && 759 (arg = ctlr->interrupt[unit].argument)) { 760 ctlr->interrupt[unit].function(arg); 761 } 762 } 763 /* AHCI declares level triggered IS. */ 764 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 765 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 766 } 767 768 /* 769 * Simplified interrupt handler for multivector MSI mode. 770 */ 771 static void 772 ahci_intr_one(void *data) 773 { 774 struct ahci_controller_irq *irq = data; 775 struct ahci_controller *ctlr = irq->ctlr; 776 void *arg; 777 int unit; 778 779 unit = irq->r_irq_rid - 1; 780 /* Some controllers have edge triggered IS. */ 781 if (ctlr->quirks & AHCI_Q_EDGEIS) 782 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 783 if ((arg = ctlr->interrupt[unit].argument)) 784 ctlr->interrupt[unit].function(arg); 785 /* AHCI declares level triggered IS. */ 786 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 787 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 788 } 789 790 static struct resource * 791 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 792 u_long start, u_long end, u_long count, u_int flags) 793 { 794 struct ahci_controller *ctlr = device_get_softc(dev); 795 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 796 struct resource *res = NULL; 797 int offset = AHCI_OFFSET + (unit << 7); 798 long st; 799 800 switch (type) { 801 case SYS_RES_MEMORY: 802 st = rman_get_start(ctlr->r_mem); 803 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 804 st + offset + 127, 128, RF_ACTIVE, child); 805 if (res) { 806 bus_space_handle_t bsh; 807 bus_space_tag_t bst; 808 bsh = rman_get_bushandle(ctlr->r_mem); 809 bst = rman_get_bustag(ctlr->r_mem); 810 bus_space_subregion(bst, bsh, offset, 128, &bsh); 811 rman_set_bushandle(res, bsh); 812 rman_set_bustag(res, bst); 813 } 814 break; 815 case SYS_RES_IRQ: 816 if (*rid == ATA_IRQ_RID) 817 res = ctlr->irqs[0].r_irq; 818 break; 819 } 820 return (res); 821 } 822 823 static int 824 ahci_release_resource(device_t dev, device_t child, int type, int rid, 825 struct resource *r) 826 { 827 828 switch (type) { 829 case SYS_RES_MEMORY: 830 rman_release_resource(r); 831 return (0); 832 case SYS_RES_IRQ: 833 if (rid != ATA_IRQ_RID) 834 return ENOENT; 835 return (0); 836 } 837 return (EINVAL); 838 } 839 840 static int 841 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 842 int flags, driver_filter_t *filter, driver_intr_t *function, 843 void *argument, void **cookiep) 844 { 845 struct ahci_controller *ctlr = device_get_softc(dev); 846 int unit = (intptr_t)device_get_ivars(child); 847 848 if (filter != NULL) { 849 printf("ahci.c: we cannot use a filter here\n"); 850 return (EINVAL); 851 } 852 ctlr->interrupt[unit].function = function; 853 ctlr->interrupt[unit].argument = argument; 854 return (0); 855 } 856 857 static int 858 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 859 void *cookie) 860 { 861 struct ahci_controller *ctlr = device_get_softc(dev); 862 int unit = (intptr_t)device_get_ivars(child); 863 864 ctlr->interrupt[unit].function = NULL; 865 ctlr->interrupt[unit].argument = NULL; 866 return (0); 867 } 868 869 static int 870 ahci_print_child(device_t dev, device_t child) 871 { 872 int retval; 873 874 retval = bus_print_child_header(dev, child); 875 retval += printf(" at channel %d", 876 (int)(intptr_t)device_get_ivars(child)); 877 retval += bus_print_child_footer(dev, child); 878 879 return (retval); 880 } 881 882 static int 883 ahci_child_location_str(device_t dev, device_t child, char *buf, 884 size_t buflen) 885 { 886 887 snprintf(buf, buflen, "channel=%d", 888 (int)(intptr_t)device_get_ivars(child)); 889 return (0); 890 } 891 892 devclass_t ahci_devclass; 893 static device_method_t ahci_methods[] = { 894 DEVMETHOD(device_probe, ahci_probe), 895 DEVMETHOD(device_attach, ahci_attach), 896 DEVMETHOD(device_detach, ahci_detach), 897 DEVMETHOD(device_suspend, ahci_suspend), 898 DEVMETHOD(device_resume, ahci_resume), 899 DEVMETHOD(bus_print_child, ahci_print_child), 900 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 901 DEVMETHOD(bus_release_resource, ahci_release_resource), 902 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 903 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 904 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 905 { 0, 0 } 906 }; 907 static driver_t ahci_driver = { 908 "ahci", 909 ahci_methods, 910 sizeof(struct ahci_controller) 911 }; 912 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 913 static device_method_t ahci_ata_methods[] = { 914 DEVMETHOD(device_probe, ahci_ata_probe), 915 DEVMETHOD(device_attach, ahci_attach), 916 DEVMETHOD(device_detach, ahci_detach), 917 DEVMETHOD(device_suspend, ahci_suspend), 918 DEVMETHOD(device_resume, ahci_resume), 919 DEVMETHOD(bus_print_child, ahci_print_child), 920 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 921 DEVMETHOD(bus_release_resource, ahci_release_resource), 922 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 923 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 924 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 925 { 0, 0 } 926 }; 927 static driver_t ahci_ata_driver = { 928 "ahci", 929 ahci_ata_methods, 930 sizeof(struct ahci_controller) 931 }; 932 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 933 MODULE_VERSION(ahci, 1); 934 MODULE_DEPEND(ahci, cam, 1, 1, 1); 935 936 static int 937 ahci_ch_probe(device_t dev) 938 { 939 940 device_set_desc_copy(dev, "AHCI channel"); 941 return (0); 942 } 943 944 static int 945 ahci_ch_attach(device_t dev) 946 { 947 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 948 struct ahci_channel *ch = device_get_softc(dev); 949 struct cam_devq *devq; 950 int rid, error, i, sata_rev = 0; 951 u_int32_t version; 952 char buf[32]; 953 954 ch->dev = dev; 955 ch->unit = (intptr_t)device_get_ivars(dev); 956 ch->caps = ctlr->caps; 957 ch->caps2 = ctlr->caps2; 958 ch->quirks = ctlr->quirks; 959 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 960 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 961 resource_int_value(device_get_name(dev), 962 device_get_unit(dev), "pm_level", &ch->pm_level); 963 if (ch->pm_level > 3) 964 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 965 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 966 /* Limit speed for my onboard JMicron external port. 967 * It is not eSATA really. */ 968 if (pci_get_devid(ctlr->dev) == 0x2363197b && 969 pci_get_subvendor(ctlr->dev) == 0x1043 && 970 pci_get_subdevice(ctlr->dev) == 0x81e4 && 971 ch->unit == 0) 972 sata_rev = 1; 973 if (ch->quirks & AHCI_Q_SATA2) 974 sata_rev = 2; 975 resource_int_value(device_get_name(dev), 976 device_get_unit(dev), "sata_rev", &sata_rev); 977 for (i = 0; i < 16; i++) { 978 ch->user[i].revision = sata_rev; 979 ch->user[i].mode = 0; 980 ch->user[i].bytecount = 8192; 981 ch->user[i].tags = ch->numslots; 982 ch->user[i].caps = 0; 983 ch->curr[i] = ch->user[i]; 984 if (ch->pm_level) { 985 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 986 CTS_SATA_CAPS_H_APST | 987 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 988 } 989 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 990 CTS_SATA_CAPS_H_AN; 991 } 992 rid = ch->unit; 993 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 994 &rid, RF_ACTIVE))) 995 return (ENXIO); 996 ahci_dmainit(dev); 997 ahci_slotsalloc(dev); 998 ahci_ch_init(dev); 999 mtx_lock(&ch->mtx); 1000 rid = ATA_IRQ_RID; 1001 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1002 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1003 device_printf(dev, "Unable to map interrupt\n"); 1004 error = ENXIO; 1005 goto err0; 1006 } 1007 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1008 ahci_ch_intr_locked, dev, &ch->ih))) { 1009 device_printf(dev, "Unable to setup interrupt\n"); 1010 error = ENXIO; 1011 goto err1; 1012 } 1013 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1014 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1015 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1016 ch->chcaps |= AHCI_P_CMD_FBSCP; 1017 if (bootverbose) { 1018 device_printf(dev, "Caps:%s%s%s%s%s\n", 1019 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1020 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1021 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1022 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1023 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1024 } 1025 /* Create the device queue for our SIM. */ 1026 devq = cam_simq_alloc(ch->numslots); 1027 if (devq == NULL) { 1028 device_printf(dev, "Unable to allocate simq\n"); 1029 error = ENOMEM; 1030 goto err1; 1031 } 1032 /* Construct SIM entry */ 1033 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1034 device_get_unit(dev), &ch->mtx, 1035 min(2, ch->numslots), 1036 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1037 devq); 1038 if (ch->sim == NULL) { 1039 cam_simq_free(devq); 1040 device_printf(dev, "unable to allocate sim\n"); 1041 error = ENOMEM; 1042 goto err1; 1043 } 1044 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1045 device_printf(dev, "unable to register xpt bus\n"); 1046 error = ENXIO; 1047 goto err2; 1048 } 1049 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1050 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1051 device_printf(dev, "unable to create path\n"); 1052 error = ENXIO; 1053 goto err3; 1054 } 1055 if (ch->pm_level > 3) { 1056 callout_reset(&ch->pm_timer, 1057 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1058 ahci_ch_pm, dev); 1059 } 1060 mtx_unlock(&ch->mtx); 1061 if ((ch->caps & AHCI_CAP_EMS) && 1062 (ctlr->capsem & AHCI_EM_LED)) { 1063 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1064 ch->leds[i].dev = dev; 1065 ch->leds[i].num = i; 1066 } 1067 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) { 1068 snprintf(buf, sizeof(buf), "%s.act", 1069 device_get_nameunit(dev)); 1070 ch->leds[0].led = led_create(ahci_ch_led, 1071 &ch->leds[0], buf); 1072 } 1073 snprintf(buf, sizeof(buf), "%s.locate", 1074 device_get_nameunit(dev)); 1075 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf); 1076 snprintf(buf, sizeof(buf), "%s.fault", 1077 device_get_nameunit(dev)); 1078 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf); 1079 } 1080 return (0); 1081 1082 err3: 1083 xpt_bus_deregister(cam_sim_path(ch->sim)); 1084 err2: 1085 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1086 err1: 1087 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1088 err0: 1089 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1090 mtx_unlock(&ch->mtx); 1091 mtx_destroy(&ch->mtx); 1092 return (error); 1093 } 1094 1095 static int 1096 ahci_ch_detach(device_t dev) 1097 { 1098 struct ahci_channel *ch = device_get_softc(dev); 1099 int i; 1100 1101 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1102 if (ch->leds[i].led) 1103 led_destroy(ch->leds[i].led); 1104 } 1105 mtx_lock(&ch->mtx); 1106 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1107 /* Forget about reset. */ 1108 if (ch->resetting) { 1109 ch->resetting = 0; 1110 xpt_release_simq(ch->sim, TRUE); 1111 } 1112 xpt_free_path(ch->path); 1113 xpt_bus_deregister(cam_sim_path(ch->sim)); 1114 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1115 mtx_unlock(&ch->mtx); 1116 1117 if (ch->pm_level > 3) 1118 callout_drain(&ch->pm_timer); 1119 callout_drain(&ch->reset_timer); 1120 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1121 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1122 1123 ahci_ch_deinit(dev); 1124 ahci_slotsfree(dev); 1125 ahci_dmafini(dev); 1126 1127 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1128 mtx_destroy(&ch->mtx); 1129 return (0); 1130 } 1131 1132 static int 1133 ahci_ch_init(device_t dev) 1134 { 1135 struct ahci_channel *ch = device_get_softc(dev); 1136 uint64_t work; 1137 1138 /* Disable port interrupts */ 1139 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1140 /* Setup work areas */ 1141 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1142 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1143 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1144 work = ch->dma.rfis_bus; 1145 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1146 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1147 /* Activate the channel and power/spin up device */ 1148 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1149 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1150 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1151 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1152 ahci_start_fr(dev); 1153 ahci_start(dev, 1); 1154 return (0); 1155 } 1156 1157 static int 1158 ahci_ch_deinit(device_t dev) 1159 { 1160 struct ahci_channel *ch = device_get_softc(dev); 1161 1162 /* Disable port interrupts. */ 1163 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1164 /* Reset command register. */ 1165 ahci_stop(dev); 1166 ahci_stop_fr(dev); 1167 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1168 /* Allow everything, including partial and slumber modes. */ 1169 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1170 /* Request slumber mode transition and give some time to get there. */ 1171 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1172 DELAY(100); 1173 /* Disable PHY. */ 1174 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1175 return (0); 1176 } 1177 1178 static int 1179 ahci_ch_suspend(device_t dev) 1180 { 1181 struct ahci_channel *ch = device_get_softc(dev); 1182 1183 mtx_lock(&ch->mtx); 1184 xpt_freeze_simq(ch->sim, 1); 1185 /* Forget about reset. */ 1186 if (ch->resetting) { 1187 ch->resetting = 0; 1188 callout_stop(&ch->reset_timer); 1189 xpt_release_simq(ch->sim, TRUE); 1190 } 1191 while (ch->oslots) 1192 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1193 ahci_ch_deinit(dev); 1194 mtx_unlock(&ch->mtx); 1195 return (0); 1196 } 1197 1198 static int 1199 ahci_ch_resume(device_t dev) 1200 { 1201 struct ahci_channel *ch = device_get_softc(dev); 1202 1203 mtx_lock(&ch->mtx); 1204 ahci_ch_init(dev); 1205 ahci_reset(dev); 1206 xpt_release_simq(ch->sim, TRUE); 1207 mtx_unlock(&ch->mtx); 1208 return (0); 1209 } 1210 1211 devclass_t ahcich_devclass; 1212 static device_method_t ahcich_methods[] = { 1213 DEVMETHOD(device_probe, ahci_ch_probe), 1214 DEVMETHOD(device_attach, ahci_ch_attach), 1215 DEVMETHOD(device_detach, ahci_ch_detach), 1216 DEVMETHOD(device_suspend, ahci_ch_suspend), 1217 DEVMETHOD(device_resume, ahci_ch_resume), 1218 { 0, 0 } 1219 }; 1220 static driver_t ahcich_driver = { 1221 "ahcich", 1222 ahcich_methods, 1223 sizeof(struct ahci_channel) 1224 }; 1225 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1226 1227 static void 1228 ahci_ch_setleds(device_t dev) 1229 { 1230 struct ahci_channel *ch; 1231 struct ahci_controller *ctlr; 1232 size_t buf; 1233 int i, timeout; 1234 int16_t val; 1235 1236 ctlr = device_get_softc(device_get_parent(dev)); 1237 ch = device_get_softc(dev); 1238 1239 val = 0; 1240 for (i = 0; i < AHCI_NUM_LEDS; i++) 1241 val |= ch->leds[i].state << (i * 3); 1242 1243 buf = (ctlr->emloc & 0xffff0000) >> 14; 1244 mtx_lock(&ctlr->em_mtx); 1245 timeout = 1000; 1246 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) && 1247 --timeout > 0) 1248 DELAY(1000); 1249 if (timeout == 0) 1250 device_printf(dev, "EM timeout\n"); 1251 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24)); 1252 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16)); 1253 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM); 1254 mtx_unlock(&ctlr->em_mtx); 1255 } 1256 1257 static void 1258 ahci_ch_led(void *priv, int onoff) 1259 { 1260 struct ahci_led *led; 1261 1262 led = (struct ahci_led *)priv; 1263 1264 led->state = onoff; 1265 ahci_ch_setleds(led->dev); 1266 } 1267 1268 struct ahci_dc_cb_args { 1269 bus_addr_t maddr; 1270 int error; 1271 }; 1272 1273 static void 1274 ahci_dmainit(device_t dev) 1275 { 1276 struct ahci_channel *ch = device_get_softc(dev); 1277 struct ahci_dc_cb_args dcba; 1278 size_t rfsize; 1279 1280 if (ch->caps & AHCI_CAP_64BIT) 1281 ch->dma.max_address = BUS_SPACE_MAXADDR; 1282 else 1283 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1284 /* Command area. */ 1285 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1286 ch->dma.max_address, BUS_SPACE_MAXADDR, 1287 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1288 0, NULL, NULL, &ch->dma.work_tag)) 1289 goto error; 1290 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1291 &ch->dma.work_map)) 1292 goto error; 1293 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1294 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1295 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1296 goto error; 1297 } 1298 ch->dma.work_bus = dcba.maddr; 1299 /* FIS receive area. */ 1300 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1301 rfsize = 4096; 1302 else 1303 rfsize = 256; 1304 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1305 ch->dma.max_address, BUS_SPACE_MAXADDR, 1306 NULL, NULL, rfsize, 1, rfsize, 1307 0, NULL, NULL, &ch->dma.rfis_tag)) 1308 goto error; 1309 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1310 &ch->dma.rfis_map)) 1311 goto error; 1312 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1313 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1314 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1315 goto error; 1316 } 1317 ch->dma.rfis_bus = dcba.maddr; 1318 /* Data area. */ 1319 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1320 ch->dma.max_address, BUS_SPACE_MAXADDR, 1321 NULL, NULL, 1322 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1323 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1324 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1325 goto error; 1326 } 1327 return; 1328 1329 error: 1330 device_printf(dev, "WARNING - DMA initialization failed\n"); 1331 ahci_dmafini(dev); 1332 } 1333 1334 static void 1335 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1336 { 1337 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1338 1339 if (!(dcba->error = error)) 1340 dcba->maddr = segs[0].ds_addr; 1341 } 1342 1343 static void 1344 ahci_dmafini(device_t dev) 1345 { 1346 struct ahci_channel *ch = device_get_softc(dev); 1347 1348 if (ch->dma.data_tag) { 1349 bus_dma_tag_destroy(ch->dma.data_tag); 1350 ch->dma.data_tag = NULL; 1351 } 1352 if (ch->dma.rfis_bus) { 1353 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1354 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1355 ch->dma.rfis_bus = 0; 1356 ch->dma.rfis_map = NULL; 1357 ch->dma.rfis = NULL; 1358 } 1359 if (ch->dma.work_bus) { 1360 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1361 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1362 ch->dma.work_bus = 0; 1363 ch->dma.work_map = NULL; 1364 ch->dma.work = NULL; 1365 } 1366 if (ch->dma.work_tag) { 1367 bus_dma_tag_destroy(ch->dma.work_tag); 1368 ch->dma.work_tag = NULL; 1369 } 1370 } 1371 1372 static void 1373 ahci_slotsalloc(device_t dev) 1374 { 1375 struct ahci_channel *ch = device_get_softc(dev); 1376 int i; 1377 1378 /* Alloc and setup command/dma slots */ 1379 bzero(ch->slot, sizeof(ch->slot)); 1380 for (i = 0; i < ch->numslots; i++) { 1381 struct ahci_slot *slot = &ch->slot[i]; 1382 1383 slot->dev = dev; 1384 slot->slot = i; 1385 slot->state = AHCI_SLOT_EMPTY; 1386 slot->ccb = NULL; 1387 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1388 1389 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1390 device_printf(ch->dev, "FAILURE - create data_map\n"); 1391 } 1392 } 1393 1394 static void 1395 ahci_slotsfree(device_t dev) 1396 { 1397 struct ahci_channel *ch = device_get_softc(dev); 1398 int i; 1399 1400 /* Free all dma slots */ 1401 for (i = 0; i < ch->numslots; i++) { 1402 struct ahci_slot *slot = &ch->slot[i]; 1403 1404 callout_drain(&slot->timeout); 1405 if (slot->dma.data_map) { 1406 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1407 slot->dma.data_map = NULL; 1408 } 1409 } 1410 } 1411 1412 static int 1413 ahci_phy_check_events(device_t dev, u_int32_t serr) 1414 { 1415 struct ahci_channel *ch = device_get_softc(dev); 1416 1417 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1418 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1419 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1420 union ccb *ccb; 1421 1422 if (bootverbose) { 1423 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1424 device_printf(dev, "CONNECT requested\n"); 1425 else 1426 device_printf(dev, "DISCONNECT requested\n"); 1427 } 1428 ahci_reset(dev); 1429 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1430 return (0); 1431 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1432 cam_sim_path(ch->sim), 1433 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1434 xpt_free_ccb(ccb); 1435 return (0); 1436 } 1437 xpt_rescan(ccb); 1438 return (1); 1439 } 1440 return (0); 1441 } 1442 1443 static void 1444 ahci_cpd_check_events(device_t dev) 1445 { 1446 struct ahci_channel *ch = device_get_softc(dev); 1447 u_int32_t status; 1448 union ccb *ccb; 1449 1450 if (ch->pm_level == 0) 1451 return; 1452 1453 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1454 if ((status & AHCI_P_CMD_CPD) == 0) 1455 return; 1456 1457 if (bootverbose) { 1458 if (status & AHCI_P_CMD_CPS) { 1459 device_printf(dev, "COLD CONNECT requested\n"); 1460 } else 1461 device_printf(dev, "COLD DISCONNECT requested\n"); 1462 } 1463 ahci_reset(dev); 1464 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1465 return; 1466 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1467 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1468 xpt_free_ccb(ccb); 1469 return; 1470 } 1471 xpt_rescan(ccb); 1472 } 1473 1474 static void 1475 ahci_notify_events(device_t dev, u_int32_t status) 1476 { 1477 struct ahci_channel *ch = device_get_softc(dev); 1478 struct cam_path *dpath; 1479 int i; 1480 1481 if (ch->caps & AHCI_CAP_SSNTF) 1482 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1483 if (bootverbose) 1484 device_printf(dev, "SNTF 0x%04x\n", status); 1485 for (i = 0; i < 16; i++) { 1486 if ((status & (1 << i)) == 0) 1487 continue; 1488 if (xpt_create_path(&dpath, NULL, 1489 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1490 xpt_async(AC_SCSI_AEN, dpath, NULL); 1491 xpt_free_path(dpath); 1492 } 1493 } 1494 } 1495 1496 static void 1497 ahci_ch_intr_locked(void *data) 1498 { 1499 device_t dev = (device_t)data; 1500 struct ahci_channel *ch = device_get_softc(dev); 1501 1502 mtx_lock(&ch->mtx); 1503 xpt_batch_start(ch->sim); 1504 ahci_ch_intr(data); 1505 xpt_batch_done(ch->sim); 1506 mtx_unlock(&ch->mtx); 1507 } 1508 1509 static void 1510 ahci_ch_pm(void *arg) 1511 { 1512 device_t dev = (device_t)arg; 1513 struct ahci_channel *ch = device_get_softc(dev); 1514 uint32_t work; 1515 1516 if (ch->numrslots != 0) 1517 return; 1518 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1519 if (ch->pm_level == 4) 1520 work |= AHCI_P_CMD_PARTIAL; 1521 else 1522 work |= AHCI_P_CMD_SLUMBER; 1523 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1524 } 1525 1526 static void 1527 ahci_ch_intr(void *data) 1528 { 1529 device_t dev = (device_t)data; 1530 struct ahci_channel *ch = device_get_softc(dev); 1531 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1532 enum ahci_err_type et; 1533 int i, ccs, port, reset = 0; 1534 1535 /* Read and clear interrupt statuses. */ 1536 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1537 if (istatus == 0) 1538 return; 1539 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1540 /* Read command statuses. */ 1541 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1542 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1543 if (istatus & AHCI_P_IX_SDB) { 1544 if (ch->caps & AHCI_CAP_SSNTF) 1545 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1546 else if (ch->fbs_enabled) { 1547 u_int8_t *fis = ch->dma.rfis + 0x58; 1548 1549 for (i = 0; i < 16; i++) { 1550 if (fis[1] & 0x80) { 1551 fis[1] &= 0x7f; 1552 sntf |= 1 << i; 1553 } 1554 fis += 256; 1555 } 1556 } else { 1557 u_int8_t *fis = ch->dma.rfis + 0x58; 1558 1559 if (fis[1] & 0x80) 1560 sntf = (1 << (fis[1] & 0x0f)); 1561 } 1562 } 1563 /* Process PHY events */ 1564 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1565 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1566 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1567 if (serr) { 1568 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1569 reset = ahci_phy_check_events(dev, serr); 1570 } 1571 } 1572 /* Process cold presence detection events */ 1573 if ((istatus & AHCI_P_IX_CPD) && !reset) 1574 ahci_cpd_check_events(dev); 1575 /* Process command errors */ 1576 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1577 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1578 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1579 >> AHCI_P_CMD_CCS_SHIFT; 1580 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1581 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1582 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1583 port = -1; 1584 if (ch->fbs_enabled) { 1585 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1586 if (fbs & AHCI_P_FBS_SDE) { 1587 port = (fbs & AHCI_P_FBS_DWE) 1588 >> AHCI_P_FBS_DWE_SHIFT; 1589 } else { 1590 for (i = 0; i < 16; i++) { 1591 if (ch->numrslotspd[i] == 0) 1592 continue; 1593 if (port == -1) 1594 port = i; 1595 else if (port != i) { 1596 port = -2; 1597 break; 1598 } 1599 } 1600 } 1601 } 1602 err = ch->rslots & (cstatus | sstatus); 1603 } else { 1604 ccs = 0; 1605 err = 0; 1606 port = -1; 1607 } 1608 /* Complete all successfull commands. */ 1609 ok = ch->rslots & ~(cstatus | sstatus); 1610 for (i = 0; i < ch->numslots; i++) { 1611 if ((ok >> i) & 1) 1612 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1613 } 1614 /* On error, complete the rest of commands with error statuses. */ 1615 if (err) { 1616 if (ch->frozen) { 1617 union ccb *fccb = ch->frozen; 1618 ch->frozen = NULL; 1619 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1620 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1621 xpt_freeze_devq(fccb->ccb_h.path, 1); 1622 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1623 } 1624 xpt_done(fccb); 1625 } 1626 for (i = 0; i < ch->numslots; i++) { 1627 /* XXX: reqests in loading state. */ 1628 if (((err >> i) & 1) == 0) 1629 continue; 1630 if (port >= 0 && 1631 ch->slot[i].ccb->ccb_h.target_id != port) 1632 continue; 1633 if (istatus & AHCI_P_IX_TFE) { 1634 if (port != -2) { 1635 /* Task File Error */ 1636 if (ch->numtslotspd[ 1637 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1638 /* Untagged operation. */ 1639 if (i == ccs) 1640 et = AHCI_ERR_TFE; 1641 else 1642 et = AHCI_ERR_INNOCENT; 1643 } else { 1644 /* Tagged operation. */ 1645 et = AHCI_ERR_NCQ; 1646 } 1647 } else { 1648 et = AHCI_ERR_TFE; 1649 ch->fatalerr = 1; 1650 } 1651 } else if (istatus & AHCI_P_IX_IF) { 1652 if (ch->numtslots == 0 && i != ccs && port != -2) 1653 et = AHCI_ERR_INNOCENT; 1654 else 1655 et = AHCI_ERR_SATA; 1656 } else 1657 et = AHCI_ERR_INVALID; 1658 ahci_end_transaction(&ch->slot[i], et); 1659 } 1660 /* 1661 * We can't reinit port if there are some other 1662 * commands active, use resume to complete them. 1663 */ 1664 if (ch->rslots != 0 && !ch->recoverycmd) 1665 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1666 } 1667 /* Process NOTIFY events */ 1668 if (sntf) 1669 ahci_notify_events(dev, sntf); 1670 } 1671 1672 /* Must be called with channel locked. */ 1673 static int 1674 ahci_check_collision(device_t dev, union ccb *ccb) 1675 { 1676 struct ahci_channel *ch = device_get_softc(dev); 1677 int t = ccb->ccb_h.target_id; 1678 1679 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1680 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1681 /* Tagged command while we have no supported tag free. */ 1682 if (((~ch->oslots) & (0xffffffff >> (32 - 1683 ch->curr[t].tags))) == 0) 1684 return (1); 1685 /* If we have FBS */ 1686 if (ch->fbs_enabled) { 1687 /* Tagged command while untagged are active. */ 1688 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1689 return (1); 1690 } else { 1691 /* Tagged command while untagged are active. */ 1692 if (ch->numrslots != 0 && ch->numtslots == 0) 1693 return (1); 1694 /* Tagged command while tagged to other target is active. */ 1695 if (ch->numtslots != 0 && 1696 ch->taggedtarget != ccb->ccb_h.target_id) 1697 return (1); 1698 } 1699 } else { 1700 /* If we have FBS */ 1701 if (ch->fbs_enabled) { 1702 /* Untagged command while tagged are active. */ 1703 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1704 return (1); 1705 } else { 1706 /* Untagged command while tagged are active. */ 1707 if (ch->numrslots != 0 && ch->numtslots != 0) 1708 return (1); 1709 } 1710 } 1711 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1712 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1713 /* Atomic command while anything active. */ 1714 if (ch->numrslots != 0) 1715 return (1); 1716 } 1717 /* We have some atomic command running. */ 1718 if (ch->aslots != 0) 1719 return (1); 1720 return (0); 1721 } 1722 1723 /* Must be called with channel locked. */ 1724 static void 1725 ahci_begin_transaction(device_t dev, union ccb *ccb) 1726 { 1727 struct ahci_channel *ch = device_get_softc(dev); 1728 struct ahci_slot *slot; 1729 int tag, tags; 1730 1731 /* Choose empty slot. */ 1732 tags = ch->numslots; 1733 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1734 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1735 tags = ch->curr[ccb->ccb_h.target_id].tags; 1736 tag = ch->lastslot; 1737 while (1) { 1738 if (tag >= tags) 1739 tag = 0; 1740 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1741 break; 1742 tag++; 1743 }; 1744 ch->lastslot = tag; 1745 /* Occupy chosen slot. */ 1746 slot = &ch->slot[tag]; 1747 slot->ccb = ccb; 1748 /* Stop PM timer. */ 1749 if (ch->numrslots == 0 && ch->pm_level > 3) 1750 callout_stop(&ch->pm_timer); 1751 /* Update channel stats. */ 1752 ch->oslots |= (1 << slot->slot); 1753 ch->numrslots++; 1754 ch->numrslotspd[ccb->ccb_h.target_id]++; 1755 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1756 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1757 ch->numtslots++; 1758 ch->numtslotspd[ccb->ccb_h.target_id]++; 1759 ch->taggedtarget = ccb->ccb_h.target_id; 1760 } 1761 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1762 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1763 ch->aslots |= (1 << slot->slot); 1764 slot->dma.nsegs = 0; 1765 /* If request moves data, setup and load SG list */ 1766 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1767 void *buf; 1768 bus_size_t size; 1769 1770 slot->state = AHCI_SLOT_LOADING; 1771 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1772 buf = ccb->ataio.data_ptr; 1773 size = ccb->ataio.dxfer_len; 1774 } else { 1775 buf = ccb->csio.data_ptr; 1776 size = ccb->csio.dxfer_len; 1777 } 1778 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1779 buf, size, ahci_dmasetprd, slot, 0); 1780 } else 1781 ahci_execute_transaction(slot); 1782 } 1783 1784 /* Locked by busdma engine. */ 1785 static void 1786 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1787 { 1788 struct ahci_slot *slot = arg; 1789 struct ahci_channel *ch = device_get_softc(slot->dev); 1790 struct ahci_cmd_tab *ctp; 1791 struct ahci_dma_prd *prd; 1792 int i; 1793 1794 if (error) { 1795 device_printf(slot->dev, "DMA load error\n"); 1796 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1797 return; 1798 } 1799 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1800 /* Get a piece of the workspace for this request */ 1801 ctp = (struct ahci_cmd_tab *) 1802 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1803 /* Fill S/G table */ 1804 prd = &ctp->prd_tab[0]; 1805 for (i = 0; i < nsegs; i++) { 1806 prd[i].dba = htole64(segs[i].ds_addr); 1807 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1808 } 1809 slot->dma.nsegs = nsegs; 1810 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1811 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1812 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1813 ahci_execute_transaction(slot); 1814 } 1815 1816 /* Must be called with channel locked. */ 1817 static void 1818 ahci_execute_transaction(struct ahci_slot *slot) 1819 { 1820 device_t dev = slot->dev; 1821 struct ahci_channel *ch = device_get_softc(dev); 1822 struct ahci_cmd_tab *ctp; 1823 struct ahci_cmd_list *clp; 1824 union ccb *ccb = slot->ccb; 1825 int port = ccb->ccb_h.target_id & 0x0f; 1826 int fis_size, i, softreset; 1827 uint8_t *fis = ch->dma.rfis + 0x40; 1828 uint8_t val; 1829 1830 /* Get a piece of the workspace for this request */ 1831 ctp = (struct ahci_cmd_tab *) 1832 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1833 /* Setup the FIS for this request */ 1834 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1835 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1836 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1837 return; 1838 } 1839 /* Setup the command list entry */ 1840 clp = (struct ahci_cmd_list *) 1841 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1842 clp->cmd_flags = htole16( 1843 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1844 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1845 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1846 (fis_size / sizeof(u_int32_t)) | 1847 (port << 12)); 1848 clp->prd_length = htole16(slot->dma.nsegs); 1849 /* Special handling for Soft Reset command. */ 1850 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1851 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1852 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1853 softreset = 1; 1854 /* Kick controller into sane state */ 1855 ahci_stop(dev); 1856 ahci_clo(dev); 1857 ahci_start(dev, 0); 1858 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1859 } else { 1860 softreset = 2; 1861 /* Prepare FIS receive area for check. */ 1862 for (i = 0; i < 20; i++) 1863 fis[i] = 0xff; 1864 } 1865 } else 1866 softreset = 0; 1867 clp->bytecount = 0; 1868 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1869 (AHCI_CT_SIZE * slot->slot)); 1870 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1871 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1872 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1873 BUS_DMASYNC_PREREAD); 1874 /* Set ACTIVE bit for NCQ commands. */ 1875 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1876 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1877 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1878 } 1879 /* If FBS is enabled, set PMP port. */ 1880 if (ch->fbs_enabled) { 1881 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1882 (port << AHCI_P_FBS_DEV_SHIFT)); 1883 } 1884 /* Issue command to the controller. */ 1885 slot->state = AHCI_SLOT_RUNNING; 1886 ch->rslots |= (1 << slot->slot); 1887 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1888 /* Device reset commands doesn't interrupt. Poll them. */ 1889 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1890 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1891 int count, timeout = ccb->ccb_h.timeout * 100; 1892 enum ahci_err_type et = AHCI_ERR_NONE; 1893 1894 for (count = 0; count < timeout; count++) { 1895 DELAY(10); 1896 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1897 break; 1898 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1899 softreset != 1) { 1900 #if 0 1901 device_printf(ch->dev, 1902 "Poll error on slot %d, TFD: %04x\n", 1903 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1904 #endif 1905 et = AHCI_ERR_TFE; 1906 break; 1907 } 1908 /* Workaround for ATI SB600/SB700 chipsets. */ 1909 if (ccb->ccb_h.target_id == 15 && 1910 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1911 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1912 et = AHCI_ERR_TIMEOUT; 1913 break; 1914 } 1915 } 1916 1917 /* Marvell controllers do not wait for readyness. */ 1918 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1919 et == AHCI_ERR_NONE) { 1920 while ((val = fis[2]) & ATA_S_BUSY) { 1921 DELAY(10); 1922 if (count++ >= timeout) 1923 break; 1924 } 1925 } 1926 1927 if (timeout && (count >= timeout)) { 1928 device_printf(dev, "Poll timeout on slot %d port %d\n", 1929 slot->slot, port); 1930 device_printf(dev, "is %08x cs %08x ss %08x " 1931 "rs %08x tfd %02x serr %08x cmd %08x\n", 1932 ATA_INL(ch->r_mem, AHCI_P_IS), 1933 ATA_INL(ch->r_mem, AHCI_P_CI), 1934 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1935 ATA_INL(ch->r_mem, AHCI_P_TFD), 1936 ATA_INL(ch->r_mem, AHCI_P_SERR), 1937 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1938 et = AHCI_ERR_TIMEOUT; 1939 } 1940 1941 /* Kick controller into sane state and enable FBS. */ 1942 if (softreset == 2) 1943 ch->eslots |= (1 << slot->slot); 1944 ahci_end_transaction(slot, et); 1945 return; 1946 } 1947 /* Start command execution timeout */ 1948 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1949 (timeout_t*)ahci_timeout, slot); 1950 return; 1951 } 1952 1953 /* Must be called with channel locked. */ 1954 static void 1955 ahci_process_timeout(device_t dev) 1956 { 1957 struct ahci_channel *ch = device_get_softc(dev); 1958 int i; 1959 1960 mtx_assert(&ch->mtx, MA_OWNED); 1961 /* Handle the rest of commands. */ 1962 for (i = 0; i < ch->numslots; i++) { 1963 /* Do we have a running request on slot? */ 1964 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1965 continue; 1966 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1967 } 1968 } 1969 1970 /* Must be called with channel locked. */ 1971 static void 1972 ahci_rearm_timeout(device_t dev) 1973 { 1974 struct ahci_channel *ch = device_get_softc(dev); 1975 int i; 1976 1977 mtx_assert(&ch->mtx, MA_OWNED); 1978 for (i = 0; i < ch->numslots; i++) { 1979 struct ahci_slot *slot = &ch->slot[i]; 1980 1981 /* Do we have a running request on slot? */ 1982 if (slot->state < AHCI_SLOT_RUNNING) 1983 continue; 1984 if ((ch->toslots & (1 << i)) == 0) 1985 continue; 1986 callout_reset(&slot->timeout, 1987 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1988 (timeout_t*)ahci_timeout, slot); 1989 } 1990 } 1991 1992 /* Locked by callout mechanism. */ 1993 static void 1994 ahci_timeout(struct ahci_slot *slot) 1995 { 1996 device_t dev = slot->dev; 1997 struct ahci_channel *ch = device_get_softc(dev); 1998 uint32_t sstatus; 1999 int ccs; 2000 int i; 2001 2002 /* Check for stale timeout. */ 2003 if (slot->state < AHCI_SLOT_RUNNING) 2004 return; 2005 2006 /* Check if slot was not being executed last time we checked. */ 2007 if (slot->state < AHCI_SLOT_EXECUTING) { 2008 /* Check if slot started executing. */ 2009 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 2010 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 2011 >> AHCI_P_CMD_CCS_SHIFT; 2012 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 2013 ch->fbs_enabled || ch->wrongccs) 2014 slot->state = AHCI_SLOT_EXECUTING; 2015 else if ((ch->rslots & (1 << ccs)) == 0) { 2016 ch->wrongccs = 1; 2017 slot->state = AHCI_SLOT_EXECUTING; 2018 } 2019 2020 callout_reset(&slot->timeout, 2021 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2022 (timeout_t*)ahci_timeout, slot); 2023 return; 2024 } 2025 2026 device_printf(dev, "Timeout on slot %d port %d\n", 2027 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2028 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2029 "serr %08x cmd %08x\n", 2030 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2031 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2032 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2033 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2034 2035 /* Handle frozen command. */ 2036 if (ch->frozen) { 2037 union ccb *fccb = ch->frozen; 2038 ch->frozen = NULL; 2039 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2040 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2041 xpt_freeze_devq(fccb->ccb_h.path, 1); 2042 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2043 } 2044 xpt_done(fccb); 2045 } 2046 if (!ch->fbs_enabled && !ch->wrongccs) { 2047 /* Without FBS we know real timeout source. */ 2048 ch->fatalerr = 1; 2049 /* Handle command with timeout. */ 2050 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2051 /* Handle the rest of commands. */ 2052 for (i = 0; i < ch->numslots; i++) { 2053 /* Do we have a running request on slot? */ 2054 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2055 continue; 2056 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2057 } 2058 } else { 2059 /* With FBS we wait for other commands timeout and pray. */ 2060 if (ch->toslots == 0) 2061 xpt_freeze_simq(ch->sim, 1); 2062 ch->toslots |= (1 << slot->slot); 2063 if ((ch->rslots & ~ch->toslots) == 0) 2064 ahci_process_timeout(dev); 2065 else 2066 device_printf(dev, " ... waiting for slots %08x\n", 2067 ch->rslots & ~ch->toslots); 2068 } 2069 } 2070 2071 /* Must be called with channel locked. */ 2072 static void 2073 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2074 { 2075 device_t dev = slot->dev; 2076 struct ahci_channel *ch = device_get_softc(dev); 2077 union ccb *ccb = slot->ccb; 2078 struct ahci_cmd_list *clp; 2079 int lastto; 2080 uint32_t sig; 2081 2082 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2084 clp = (struct ahci_cmd_list *) 2085 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2086 /* Read result registers to the result struct 2087 * May be incorrect if several commands finished same time, 2088 * so read only when sure or have to. 2089 */ 2090 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2091 struct ata_res *res = &ccb->ataio.res; 2092 2093 if ((et == AHCI_ERR_TFE) || 2094 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2095 u_int8_t *fis = ch->dma.rfis + 0x40; 2096 2097 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2098 BUS_DMASYNC_POSTREAD); 2099 if (ch->fbs_enabled) { 2100 fis += ccb->ccb_h.target_id * 256; 2101 res->status = fis[2]; 2102 res->error = fis[3]; 2103 } else { 2104 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2105 2106 res->status = tfd; 2107 res->error = tfd >> 8; 2108 } 2109 res->lba_low = fis[4]; 2110 res->lba_mid = fis[5]; 2111 res->lba_high = fis[6]; 2112 res->device = fis[7]; 2113 res->lba_low_exp = fis[8]; 2114 res->lba_mid_exp = fis[9]; 2115 res->lba_high_exp = fis[10]; 2116 res->sector_count = fis[12]; 2117 res->sector_count_exp = fis[13]; 2118 2119 /* 2120 * Some weird controllers do not return signature in 2121 * FIS receive area. Read it from PxSIG register. 2122 */ 2123 if ((ch->quirks & AHCI_Q_ALTSIG) && 2124 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2125 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2126 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2127 res->lba_high = sig >> 24; 2128 res->lba_mid = sig >> 16; 2129 res->lba_low = sig >> 8; 2130 res->sector_count = sig; 2131 } 2132 } else 2133 bzero(res, sizeof(*res)); 2134 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2135 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2136 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2137 ccb->ataio.resid = 2138 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2139 } 2140 } else { 2141 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2142 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2143 ccb->csio.resid = 2144 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2145 } 2146 } 2147 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2148 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2149 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2150 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2151 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2152 } 2153 if (et != AHCI_ERR_NONE) 2154 ch->eslots |= (1 << slot->slot); 2155 /* In case of error, freeze device for proper recovery. */ 2156 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2157 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2158 xpt_freeze_devq(ccb->ccb_h.path, 1); 2159 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2160 } 2161 /* Set proper result status. */ 2162 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2163 switch (et) { 2164 case AHCI_ERR_NONE: 2165 ccb->ccb_h.status |= CAM_REQ_CMP; 2166 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2167 ccb->csio.scsi_status = SCSI_STATUS_OK; 2168 break; 2169 case AHCI_ERR_INVALID: 2170 ch->fatalerr = 1; 2171 ccb->ccb_h.status |= CAM_REQ_INVALID; 2172 break; 2173 case AHCI_ERR_INNOCENT: 2174 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2175 break; 2176 case AHCI_ERR_TFE: 2177 case AHCI_ERR_NCQ: 2178 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2179 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2180 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2181 } else { 2182 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2183 } 2184 break; 2185 case AHCI_ERR_SATA: 2186 ch->fatalerr = 1; 2187 if (!ch->recoverycmd) { 2188 xpt_freeze_simq(ch->sim, 1); 2189 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2190 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2191 } 2192 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2193 break; 2194 case AHCI_ERR_TIMEOUT: 2195 if (!ch->recoverycmd) { 2196 xpt_freeze_simq(ch->sim, 1); 2197 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2198 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2199 } 2200 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2201 break; 2202 default: 2203 ch->fatalerr = 1; 2204 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2205 } 2206 /* Free slot. */ 2207 ch->oslots &= ~(1 << slot->slot); 2208 ch->rslots &= ~(1 << slot->slot); 2209 ch->aslots &= ~(1 << slot->slot); 2210 slot->state = AHCI_SLOT_EMPTY; 2211 slot->ccb = NULL; 2212 /* Update channel stats. */ 2213 ch->numrslots--; 2214 ch->numrslotspd[ccb->ccb_h.target_id]--; 2215 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2216 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2217 ch->numtslots--; 2218 ch->numtslotspd[ccb->ccb_h.target_id]--; 2219 } 2220 /* Cancel timeout state if request completed normally. */ 2221 if (et != AHCI_ERR_TIMEOUT) { 2222 lastto = (ch->toslots == (1 << slot->slot)); 2223 ch->toslots &= ~(1 << slot->slot); 2224 if (lastto) 2225 xpt_release_simq(ch->sim, TRUE); 2226 } 2227 /* If it was first request of reset sequence and there is no error, 2228 * proceed to second request. */ 2229 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2230 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2231 (ccb->ataio.cmd.control & ATA_A_RESET) && 2232 et == AHCI_ERR_NONE) { 2233 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2234 ahci_begin_transaction(dev, ccb); 2235 return; 2236 } 2237 /* If it was our READ LOG command - process it. */ 2238 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2239 ahci_process_read_log(dev, ccb); 2240 /* If it was our REQUEST SENSE command - process it. */ 2241 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2242 ahci_process_request_sense(dev, ccb); 2243 /* If it was NCQ or ATAPI command error, put result on hold. */ 2244 } else if (et == AHCI_ERR_NCQ || 2245 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2246 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2247 ch->hold[slot->slot] = ccb; 2248 ch->numhslots++; 2249 } else 2250 xpt_done(ccb); 2251 /* If we have no other active commands, ... */ 2252 if (ch->rslots == 0) { 2253 /* if there was fatal error - reset port. */ 2254 if (ch->toslots != 0 || ch->fatalerr) { 2255 ahci_reset(dev); 2256 } else { 2257 /* if we have slots in error, we can reinit port. */ 2258 if (ch->eslots != 0) { 2259 ahci_stop(dev); 2260 ahci_clo(dev); 2261 ahci_start(dev, 1); 2262 } 2263 /* if there commands on hold, we can do READ LOG. */ 2264 if (!ch->recoverycmd && ch->numhslots) 2265 ahci_issue_recovery(dev); 2266 } 2267 /* If all the rest of commands are in timeout - give them chance. */ 2268 } else if ((ch->rslots & ~ch->toslots) == 0 && 2269 et != AHCI_ERR_TIMEOUT) 2270 ahci_rearm_timeout(dev); 2271 /* Unfreeze frozen command. */ 2272 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2273 union ccb *fccb = ch->frozen; 2274 ch->frozen = NULL; 2275 ahci_begin_transaction(dev, fccb); 2276 xpt_release_simq(ch->sim, TRUE); 2277 } 2278 /* Start PM timer. */ 2279 if (ch->numrslots == 0 && ch->pm_level > 3 && 2280 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2281 callout_schedule(&ch->pm_timer, 2282 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2283 } 2284 } 2285 2286 static void 2287 ahci_issue_recovery(device_t dev) 2288 { 2289 struct ahci_channel *ch = device_get_softc(dev); 2290 union ccb *ccb; 2291 struct ccb_ataio *ataio; 2292 struct ccb_scsiio *csio; 2293 int i; 2294 2295 /* Find some held command. */ 2296 for (i = 0; i < ch->numslots; i++) { 2297 if (ch->hold[i]) 2298 break; 2299 } 2300 ccb = xpt_alloc_ccb_nowait(); 2301 if (ccb == NULL) { 2302 device_printf(dev, "Unable to allocate recovery command\n"); 2303 completeall: 2304 /* We can't do anything -- complete held commands. */ 2305 for (i = 0; i < ch->numslots; i++) { 2306 if (ch->hold[i] == NULL) 2307 continue; 2308 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2309 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2310 xpt_done(ch->hold[i]); 2311 ch->hold[i] = NULL; 2312 ch->numhslots--; 2313 } 2314 ahci_reset(dev); 2315 return; 2316 } 2317 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2318 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2319 /* READ LOG */ 2320 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2321 ccb->ccb_h.func_code = XPT_ATA_IO; 2322 ccb->ccb_h.flags = CAM_DIR_IN; 2323 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2324 ataio = &ccb->ataio; 2325 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2326 if (ataio->data_ptr == NULL) { 2327 xpt_free_ccb(ccb); 2328 device_printf(dev, 2329 "Unable to allocate memory for READ LOG command\n"); 2330 goto completeall; 2331 } 2332 ataio->dxfer_len = 512; 2333 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2334 ataio->cmd.flags = CAM_ATAIO_48BIT; 2335 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2336 ataio->cmd.sector_count = 1; 2337 ataio->cmd.sector_count_exp = 0; 2338 ataio->cmd.lba_low = 0x10; 2339 ataio->cmd.lba_mid = 0; 2340 ataio->cmd.lba_mid_exp = 0; 2341 } else { 2342 /* REQUEST SENSE */ 2343 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2344 ccb->ccb_h.recovery_slot = i; 2345 ccb->ccb_h.func_code = XPT_SCSI_IO; 2346 ccb->ccb_h.flags = CAM_DIR_IN; 2347 ccb->ccb_h.status = 0; 2348 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2349 csio = &ccb->csio; 2350 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2351 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2352 csio->cdb_len = 6; 2353 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2354 csio->cdb_io.cdb_bytes[0] = 0x03; 2355 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2356 } 2357 /* Freeze SIM while doing recovery. */ 2358 ch->recoverycmd = 1; 2359 xpt_freeze_simq(ch->sim, 1); 2360 ahci_begin_transaction(dev, ccb); 2361 } 2362 2363 static void 2364 ahci_process_read_log(device_t dev, union ccb *ccb) 2365 { 2366 struct ahci_channel *ch = device_get_softc(dev); 2367 uint8_t *data; 2368 struct ata_res *res; 2369 int i; 2370 2371 ch->recoverycmd = 0; 2372 2373 data = ccb->ataio.data_ptr; 2374 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2375 (data[0] & 0x80) == 0) { 2376 for (i = 0; i < ch->numslots; i++) { 2377 if (!ch->hold[i]) 2378 continue; 2379 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2380 continue; 2381 if ((data[0] & 0x1F) == i) { 2382 res = &ch->hold[i]->ataio.res; 2383 res->status = data[2]; 2384 res->error = data[3]; 2385 res->lba_low = data[4]; 2386 res->lba_mid = data[5]; 2387 res->lba_high = data[6]; 2388 res->device = data[7]; 2389 res->lba_low_exp = data[8]; 2390 res->lba_mid_exp = data[9]; 2391 res->lba_high_exp = data[10]; 2392 res->sector_count = data[12]; 2393 res->sector_count_exp = data[13]; 2394 } else { 2395 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2396 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2397 } 2398 xpt_done(ch->hold[i]); 2399 ch->hold[i] = NULL; 2400 ch->numhslots--; 2401 } 2402 } else { 2403 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2404 device_printf(dev, "Error while READ LOG EXT\n"); 2405 else if ((data[0] & 0x80) == 0) { 2406 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2407 } 2408 for (i = 0; i < ch->numslots; i++) { 2409 if (!ch->hold[i]) 2410 continue; 2411 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2412 continue; 2413 xpt_done(ch->hold[i]); 2414 ch->hold[i] = NULL; 2415 ch->numhslots--; 2416 } 2417 } 2418 free(ccb->ataio.data_ptr, M_AHCI); 2419 xpt_free_ccb(ccb); 2420 xpt_release_simq(ch->sim, TRUE); 2421 } 2422 2423 static void 2424 ahci_process_request_sense(device_t dev, union ccb *ccb) 2425 { 2426 struct ahci_channel *ch = device_get_softc(dev); 2427 int i; 2428 2429 ch->recoverycmd = 0; 2430 2431 i = ccb->ccb_h.recovery_slot; 2432 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2433 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2434 } else { 2435 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2436 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2437 } 2438 xpt_done(ch->hold[i]); 2439 ch->hold[i] = NULL; 2440 ch->numhslots--; 2441 xpt_free_ccb(ccb); 2442 xpt_release_simq(ch->sim, TRUE); 2443 } 2444 2445 static void 2446 ahci_start(device_t dev, int fbs) 2447 { 2448 struct ahci_channel *ch = device_get_softc(dev); 2449 u_int32_t cmd; 2450 2451 /* Clear SATA error register */ 2452 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2453 /* Clear any interrupts pending on this channel */ 2454 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2455 /* Configure FIS-based switching if supported. */ 2456 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2457 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2458 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2459 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2460 } 2461 /* Start operations on this channel */ 2462 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2463 cmd &= ~AHCI_P_CMD_PMA; 2464 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2465 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2466 } 2467 2468 static void 2469 ahci_stop(device_t dev) 2470 { 2471 struct ahci_channel *ch = device_get_softc(dev); 2472 u_int32_t cmd; 2473 int timeout; 2474 2475 /* Kill all activity on this channel */ 2476 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2477 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2478 /* Wait for activity stop. */ 2479 timeout = 0; 2480 do { 2481 DELAY(10); 2482 if (timeout++ > 50000) { 2483 device_printf(dev, "stopping AHCI engine failed\n"); 2484 break; 2485 } 2486 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2487 ch->eslots = 0; 2488 } 2489 2490 static void 2491 ahci_clo(device_t dev) 2492 { 2493 struct ahci_channel *ch = device_get_softc(dev); 2494 u_int32_t cmd; 2495 int timeout; 2496 2497 /* Issue Command List Override if supported */ 2498 if (ch->caps & AHCI_CAP_SCLO) { 2499 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2500 cmd |= AHCI_P_CMD_CLO; 2501 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2502 timeout = 0; 2503 do { 2504 DELAY(10); 2505 if (timeout++ > 50000) { 2506 device_printf(dev, "executing CLO failed\n"); 2507 break; 2508 } 2509 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2510 } 2511 } 2512 2513 static void 2514 ahci_stop_fr(device_t dev) 2515 { 2516 struct ahci_channel *ch = device_get_softc(dev); 2517 u_int32_t cmd; 2518 int timeout; 2519 2520 /* Kill all FIS reception on this channel */ 2521 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2522 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2523 /* Wait for FIS reception stop. */ 2524 timeout = 0; 2525 do { 2526 DELAY(10); 2527 if (timeout++ > 50000) { 2528 device_printf(dev, "stopping AHCI FR engine failed\n"); 2529 break; 2530 } 2531 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2532 } 2533 2534 static void 2535 ahci_start_fr(device_t dev) 2536 { 2537 struct ahci_channel *ch = device_get_softc(dev); 2538 u_int32_t cmd; 2539 2540 /* Start FIS reception on this channel */ 2541 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2542 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2543 } 2544 2545 static int 2546 ahci_wait_ready(device_t dev, int t, int t0) 2547 { 2548 struct ahci_channel *ch = device_get_softc(dev); 2549 int timeout = 0; 2550 uint32_t val; 2551 2552 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2553 (ATA_S_BUSY | ATA_S_DRQ)) { 2554 if (timeout > t) { 2555 if (t != 0) { 2556 device_printf(dev, 2557 "AHCI reset: device not ready after %dms " 2558 "(tfd = %08x)\n", 2559 MAX(t, 0) + t0, val); 2560 } 2561 return (EBUSY); 2562 } 2563 DELAY(1000); 2564 timeout++; 2565 } 2566 if (bootverbose) 2567 device_printf(dev, "AHCI reset: device ready after %dms\n", 2568 timeout + t0); 2569 return (0); 2570 } 2571 2572 static void 2573 ahci_reset_to(void *arg) 2574 { 2575 device_t dev = arg; 2576 struct ahci_channel *ch = device_get_softc(dev); 2577 2578 if (ch->resetting == 0) 2579 return; 2580 ch->resetting--; 2581 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2582 (310 - ch->resetting) * 100) == 0) { 2583 ch->resetting = 0; 2584 ahci_start(dev, 1); 2585 xpt_release_simq(ch->sim, TRUE); 2586 return; 2587 } 2588 if (ch->resetting == 0) { 2589 ahci_clo(dev); 2590 ahci_start(dev, 1); 2591 xpt_release_simq(ch->sim, TRUE); 2592 return; 2593 } 2594 callout_schedule(&ch->reset_timer, hz / 10); 2595 } 2596 2597 static void 2598 ahci_reset(device_t dev) 2599 { 2600 struct ahci_channel *ch = device_get_softc(dev); 2601 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2602 int i; 2603 2604 xpt_freeze_simq(ch->sim, 1); 2605 if (bootverbose) 2606 device_printf(dev, "AHCI reset...\n"); 2607 /* Forget about previous reset. */ 2608 if (ch->resetting) { 2609 ch->resetting = 0; 2610 callout_stop(&ch->reset_timer); 2611 xpt_release_simq(ch->sim, TRUE); 2612 } 2613 /* Requeue freezed command. */ 2614 if (ch->frozen) { 2615 union ccb *fccb = ch->frozen; 2616 ch->frozen = NULL; 2617 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2618 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2619 xpt_freeze_devq(fccb->ccb_h.path, 1); 2620 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2621 } 2622 xpt_done(fccb); 2623 } 2624 /* Kill the engine and requeue all running commands. */ 2625 ahci_stop(dev); 2626 for (i = 0; i < ch->numslots; i++) { 2627 /* Do we have a running request on slot? */ 2628 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2629 continue; 2630 /* XXX; Commands in loading state. */ 2631 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2632 } 2633 for (i = 0; i < ch->numslots; i++) { 2634 if (!ch->hold[i]) 2635 continue; 2636 xpt_done(ch->hold[i]); 2637 ch->hold[i] = NULL; 2638 ch->numhslots--; 2639 } 2640 if (ch->toslots != 0) 2641 xpt_release_simq(ch->sim, TRUE); 2642 ch->eslots = 0; 2643 ch->toslots = 0; 2644 ch->wrongccs = 0; 2645 ch->fatalerr = 0; 2646 /* Tell the XPT about the event */ 2647 xpt_async(AC_BUS_RESET, ch->path, NULL); 2648 /* Disable port interrupts */ 2649 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2650 /* Reset and reconnect PHY, */ 2651 if (!ahci_sata_phy_reset(dev)) { 2652 if (bootverbose) 2653 device_printf(dev, 2654 "AHCI reset: device not found\n"); 2655 ch->devices = 0; 2656 /* Enable wanted port interrupts */ 2657 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2658 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2659 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2660 xpt_release_simq(ch->sim, TRUE); 2661 return; 2662 } 2663 if (bootverbose) 2664 device_printf(dev, "AHCI reset: device found\n"); 2665 /* Wait for clearing busy status. */ 2666 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2667 if (dumping) 2668 ahci_clo(dev); 2669 else 2670 ch->resetting = 310; 2671 } 2672 ch->devices = 1; 2673 /* Enable wanted port interrupts */ 2674 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2675 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2676 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2677 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2678 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2679 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2680 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2681 if (ch->resetting) 2682 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2683 else { 2684 ahci_start(dev, 1); 2685 xpt_release_simq(ch->sim, TRUE); 2686 } 2687 } 2688 2689 static int 2690 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2691 { 2692 struct ahci_channel *ch = device_get_softc(dev); 2693 u_int8_t *fis = &ctp->cfis[0]; 2694 2695 bzero(ctp->cfis, 64); 2696 fis[0] = 0x27; /* host to device */ 2697 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2698 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2699 fis[1] |= 0x80; 2700 fis[2] = ATA_PACKET_CMD; 2701 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2702 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2703 fis[3] = ATA_F_DMA; 2704 else { 2705 fis[5] = ccb->csio.dxfer_len; 2706 fis[6] = ccb->csio.dxfer_len >> 8; 2707 } 2708 fis[7] = ATA_D_LBA; 2709 fis[15] = ATA_A_4BIT; 2710 bzero(ctp->acmd, 32); 2711 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2712 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2713 ctp->acmd, ccb->csio.cdb_len); 2714 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2715 fis[1] |= 0x80; 2716 fis[2] = ccb->ataio.cmd.command; 2717 fis[3] = ccb->ataio.cmd.features; 2718 fis[4] = ccb->ataio.cmd.lba_low; 2719 fis[5] = ccb->ataio.cmd.lba_mid; 2720 fis[6] = ccb->ataio.cmd.lba_high; 2721 fis[7] = ccb->ataio.cmd.device; 2722 fis[8] = ccb->ataio.cmd.lba_low_exp; 2723 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2724 fis[10] = ccb->ataio.cmd.lba_high_exp; 2725 fis[11] = ccb->ataio.cmd.features_exp; 2726 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2727 fis[12] = tag << 3; 2728 fis[13] = 0; 2729 } else { 2730 fis[12] = ccb->ataio.cmd.sector_count; 2731 fis[13] = ccb->ataio.cmd.sector_count_exp; 2732 } 2733 fis[15] = ATA_A_4BIT; 2734 } else { 2735 fis[15] = ccb->ataio.cmd.control; 2736 } 2737 return (20); 2738 } 2739 2740 static int 2741 ahci_sata_connect(struct ahci_channel *ch) 2742 { 2743 u_int32_t status; 2744 int timeout, found = 0; 2745 2746 /* Wait up to 100ms for "connect well" */ 2747 for (timeout = 0; timeout < 1000 ; timeout++) { 2748 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2749 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2750 found = 1; 2751 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2752 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2753 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2754 break; 2755 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2756 if (bootverbose) { 2757 device_printf(ch->dev, "SATA offline status=%08x\n", 2758 status); 2759 } 2760 return (0); 2761 } 2762 if (found == 0 && timeout >= 100) 2763 break; 2764 DELAY(100); 2765 } 2766 if (timeout >= 1000 || !found) { 2767 if (bootverbose) { 2768 device_printf(ch->dev, 2769 "SATA connect timeout time=%dus status=%08x\n", 2770 timeout * 100, status); 2771 } 2772 return (0); 2773 } 2774 if (bootverbose) { 2775 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2776 timeout * 100, status); 2777 } 2778 /* Clear SATA error register */ 2779 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2780 return (1); 2781 } 2782 2783 static int 2784 ahci_sata_phy_reset(device_t dev) 2785 { 2786 struct ahci_channel *ch = device_get_softc(dev); 2787 int sata_rev; 2788 uint32_t val; 2789 2790 if (ch->listening) { 2791 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2792 val |= AHCI_P_CMD_SUD; 2793 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2794 ch->listening = 0; 2795 } 2796 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2797 if (sata_rev == 1) 2798 val = ATA_SC_SPD_SPEED_GEN1; 2799 else if (sata_rev == 2) 2800 val = ATA_SC_SPD_SPEED_GEN2; 2801 else if (sata_rev == 3) 2802 val = ATA_SC_SPD_SPEED_GEN3; 2803 else 2804 val = 0; 2805 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2806 ATA_SC_DET_RESET | val | 2807 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2808 DELAY(1000); 2809 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2810 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2811 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2812 if (!ahci_sata_connect(ch)) { 2813 if (ch->caps & AHCI_CAP_SSS) { 2814 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2815 val &= ~AHCI_P_CMD_SUD; 2816 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2817 ch->listening = 1; 2818 } else if (ch->pm_level > 0) 2819 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2820 return (0); 2821 } 2822 return (1); 2823 } 2824 2825 static int 2826 ahci_check_ids(device_t dev, union ccb *ccb) 2827 { 2828 struct ahci_channel *ch = device_get_softc(dev); 2829 2830 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2831 ccb->ccb_h.status = CAM_TID_INVALID; 2832 xpt_done(ccb); 2833 return (-1); 2834 } 2835 if (ccb->ccb_h.target_lun != 0) { 2836 ccb->ccb_h.status = CAM_LUN_INVALID; 2837 xpt_done(ccb); 2838 return (-1); 2839 } 2840 return (0); 2841 } 2842 2843 static void 2844 ahciaction(struct cam_sim *sim, union ccb *ccb) 2845 { 2846 device_t dev; 2847 struct ahci_channel *ch; 2848 2849 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2850 ccb->ccb_h.func_code)); 2851 2852 ch = (struct ahci_channel *)cam_sim_softc(sim); 2853 dev = ch->dev; 2854 switch (ccb->ccb_h.func_code) { 2855 /* Common cases first */ 2856 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2857 case XPT_SCSI_IO: 2858 if (ahci_check_ids(dev, ccb)) 2859 return; 2860 if (ch->devices == 0 || 2861 (ch->pm_present == 0 && 2862 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2863 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2864 break; 2865 } 2866 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2867 /* Check for command collision. */ 2868 if (ahci_check_collision(dev, ccb)) { 2869 /* Freeze command. */ 2870 ch->frozen = ccb; 2871 /* We have only one frozen slot, so freeze simq also. */ 2872 xpt_freeze_simq(ch->sim, 1); 2873 return; 2874 } 2875 ahci_begin_transaction(dev, ccb); 2876 return; 2877 case XPT_EN_LUN: /* Enable LUN as a target */ 2878 case XPT_TARGET_IO: /* Execute target I/O request */ 2879 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2880 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2881 case XPT_ABORT: /* Abort the specified CCB */ 2882 /* XXX Implement */ 2883 ccb->ccb_h.status = CAM_REQ_INVALID; 2884 break; 2885 case XPT_SET_TRAN_SETTINGS: 2886 { 2887 struct ccb_trans_settings *cts = &ccb->cts; 2888 struct ahci_device *d; 2889 2890 if (ahci_check_ids(dev, ccb)) 2891 return; 2892 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2893 d = &ch->curr[ccb->ccb_h.target_id]; 2894 else 2895 d = &ch->user[ccb->ccb_h.target_id]; 2896 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2897 d->revision = cts->xport_specific.sata.revision; 2898 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2899 d->mode = cts->xport_specific.sata.mode; 2900 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2901 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2902 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2903 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2904 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2905 ch->pm_present = cts->xport_specific.sata.pm_present; 2906 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2907 d->atapi = cts->xport_specific.sata.atapi; 2908 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2909 d->caps = cts->xport_specific.sata.caps; 2910 ccb->ccb_h.status = CAM_REQ_CMP; 2911 break; 2912 } 2913 case XPT_GET_TRAN_SETTINGS: 2914 /* Get default/user set transfer settings for the target */ 2915 { 2916 struct ccb_trans_settings *cts = &ccb->cts; 2917 struct ahci_device *d; 2918 uint32_t status; 2919 2920 if (ahci_check_ids(dev, ccb)) 2921 return; 2922 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2923 d = &ch->curr[ccb->ccb_h.target_id]; 2924 else 2925 d = &ch->user[ccb->ccb_h.target_id]; 2926 cts->protocol = PROTO_UNSPECIFIED; 2927 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2928 cts->transport = XPORT_SATA; 2929 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2930 cts->proto_specific.valid = 0; 2931 cts->xport_specific.sata.valid = 0; 2932 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2933 (ccb->ccb_h.target_id == 15 || 2934 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2935 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2936 if (status & 0x0f0) { 2937 cts->xport_specific.sata.revision = 2938 (status & 0x0f0) >> 4; 2939 cts->xport_specific.sata.valid |= 2940 CTS_SATA_VALID_REVISION; 2941 } 2942 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2943 if (ch->pm_level) { 2944 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2945 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2946 if (ch->caps2 & AHCI_CAP2_APST) 2947 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2948 } 2949 if ((ch->caps & AHCI_CAP_SNCQ) && 2950 (ch->quirks & AHCI_Q_NOAA) == 0) 2951 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2952 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2953 cts->xport_specific.sata.caps &= 2954 ch->user[ccb->ccb_h.target_id].caps; 2955 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2956 } else { 2957 cts->xport_specific.sata.revision = d->revision; 2958 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2959 cts->xport_specific.sata.caps = d->caps; 2960 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2961 } 2962 cts->xport_specific.sata.mode = d->mode; 2963 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2964 cts->xport_specific.sata.bytecount = d->bytecount; 2965 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2966 cts->xport_specific.sata.pm_present = ch->pm_present; 2967 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2968 cts->xport_specific.sata.tags = d->tags; 2969 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2970 cts->xport_specific.sata.atapi = d->atapi; 2971 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2972 ccb->ccb_h.status = CAM_REQ_CMP; 2973 break; 2974 } 2975 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2976 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2977 ahci_reset(dev); 2978 ccb->ccb_h.status = CAM_REQ_CMP; 2979 break; 2980 case XPT_TERM_IO: /* Terminate the I/O process */ 2981 /* XXX Implement */ 2982 ccb->ccb_h.status = CAM_REQ_INVALID; 2983 break; 2984 case XPT_PATH_INQ: /* Path routing inquiry */ 2985 { 2986 struct ccb_pathinq *cpi = &ccb->cpi; 2987 2988 cpi->version_num = 1; /* XXX??? */ 2989 cpi->hba_inquiry = PI_SDTR_ABLE; 2990 if (ch->caps & AHCI_CAP_SNCQ) 2991 cpi->hba_inquiry |= PI_TAG_ABLE; 2992 if (ch->caps & AHCI_CAP_SPM) 2993 cpi->hba_inquiry |= PI_SATAPM; 2994 cpi->target_sprt = 0; 2995 cpi->hba_misc = PIM_SEQSCAN; 2996 cpi->hba_eng_cnt = 0; 2997 if (ch->caps & AHCI_CAP_SPM) 2998 cpi->max_target = 15; 2999 else 3000 cpi->max_target = 0; 3001 cpi->max_lun = 0; 3002 cpi->initiator_id = 0; 3003 cpi->bus_id = cam_sim_bus(sim); 3004 cpi->base_transfer_speed = 150000; 3005 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3006 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 3007 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3008 cpi->unit_number = cam_sim_unit(sim); 3009 cpi->transport = XPORT_SATA; 3010 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 3011 cpi->protocol = PROTO_ATA; 3012 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 3013 cpi->maxio = MAXPHYS; 3014 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 3015 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 3016 cpi->maxio = min(cpi->maxio, 128 * 512); 3017 cpi->ccb_h.status = CAM_REQ_CMP; 3018 break; 3019 } 3020 default: 3021 ccb->ccb_h.status = CAM_REQ_INVALID; 3022 break; 3023 } 3024 xpt_done(ccb); 3025 } 3026 3027 static void 3028 ahcipoll(struct cam_sim *sim) 3029 { 3030 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3031 3032 ahci_ch_intr(ch->dev); 3033 if (ch->resetting != 0 && 3034 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3035 ch->resetpolldiv = 1000; 3036 ahci_reset_to(ch->dev); 3037 } 3038 }
Cache object: 376eaa59427d4e985714844ca915a2bf
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