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sys/dev/ahci/ahci.c
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1 /*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/9.0/sys/dev/ahci/ahci.c 225873 2011-09-29 10:37:59Z mav $"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/led/led.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include "ahci.h" 52 53 #include <cam/cam.h> 54 #include <cam/cam_ccb.h> 55 #include <cam/cam_sim.h> 56 #include <cam/cam_xpt_sim.h> 57 #include <cam/cam_debug.h> 58 59 /* local prototypes */ 60 static int ahci_setup_interrupt(device_t dev); 61 static void ahci_intr(void *data); 62 static void ahci_intr_one(void *data); 63 static int ahci_suspend(device_t dev); 64 static int ahci_resume(device_t dev); 65 static int ahci_ch_init(device_t dev); 66 static int ahci_ch_deinit(device_t dev); 67 static int ahci_ch_suspend(device_t dev); 68 static int ahci_ch_resume(device_t dev); 69 static void ahci_ch_pm(void *arg); 70 static void ahci_ch_intr_locked(void *data); 71 static void ahci_ch_intr(void *data); 72 static void ahci_ch_led(void *priv, int onoff); 73 static int ahci_ctlr_reset(device_t dev); 74 static int ahci_ctlr_setup(device_t dev); 75 static void ahci_begin_transaction(device_t dev, union ccb *ccb); 76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 77 static void ahci_execute_transaction(struct ahci_slot *slot); 78 static void ahci_timeout(struct ahci_slot *slot); 79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 81 static void ahci_dmainit(device_t dev); 82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 83 static void ahci_dmafini(device_t dev); 84 static void ahci_slotsalloc(device_t dev); 85 static void ahci_slotsfree(device_t dev); 86 static void ahci_reset(device_t dev); 87 static void ahci_start(device_t dev, int fbs); 88 static void ahci_stop(device_t dev); 89 static void ahci_clo(device_t dev); 90 static void ahci_start_fr(device_t dev); 91 static void ahci_stop_fr(device_t dev); 92 93 static int ahci_sata_connect(struct ahci_channel *ch); 94 static int ahci_sata_phy_reset(device_t dev); 95 static int ahci_wait_ready(device_t dev, int t, int t0); 96 97 static void ahci_issue_recovery(device_t dev); 98 static void ahci_process_read_log(device_t dev, union ccb *ccb); 99 static void ahci_process_request_sense(device_t dev, union ccb *ccb); 100 101 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 102 static void ahcipoll(struct cam_sim *sim); 103 104 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 105 106 static struct { 107 uint32_t id; 108 uint8_t rev; 109 const char *name; 110 int quirks; 111 #define AHCI_Q_NOFORCE 1 112 #define AHCI_Q_NOPMP 2 113 #define AHCI_Q_NONCQ 4 114 #define AHCI_Q_1CH 8 115 #define AHCI_Q_2CH 16 116 #define AHCI_Q_4CH 32 117 #define AHCI_Q_EDGEIS 64 118 #define AHCI_Q_SATA2 128 119 #define AHCI_Q_NOBSYRES 256 120 #define AHCI_Q_NOAA 512 121 #define AHCI_Q_NOCOUNT 1024 122 #define AHCI_Q_ALTSIG 2048 123 } ahci_ids[] = { 124 {0x43801002, 0x00, "ATI IXP600", 0}, 125 {0x43901002, 0x00, "ATI IXP700", 0}, 126 {0x43911002, 0x00, "ATI IXP700", 0}, 127 {0x43921002, 0x00, "ATI IXP700", 0}, 128 {0x43931002, 0x00, "ATI IXP700", 0}, 129 {0x43941002, 0x00, "ATI IXP800", 0}, 130 {0x43951002, 0x00, "ATI IXP800", 0}, 131 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 132 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 133 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 134 {0x26818086, 0x00, "Intel ESB2", 0}, 135 {0x26828086, 0x00, "Intel ESB2", 0}, 136 {0x26838086, 0x00, "Intel ESB2", 0}, 137 {0x27c18086, 0x00, "Intel ICH7", 0}, 138 {0x27c38086, 0x00, "Intel ICH7", 0}, 139 {0x27c58086, 0x00, "Intel ICH7M", 0}, 140 {0x27c68086, 0x00, "Intel ICH7M", 0}, 141 {0x28218086, 0x00, "Intel ICH8", 0}, 142 {0x28228086, 0x00, "Intel ICH8", 0}, 143 {0x28248086, 0x00, "Intel ICH8", 0}, 144 {0x28298086, 0x00, "Intel ICH8M", 0}, 145 {0x282a8086, 0x00, "Intel ICH8M", 0}, 146 {0x29228086, 0x00, "Intel ICH9", 0}, 147 {0x29238086, 0x00, "Intel ICH9", 0}, 148 {0x29248086, 0x00, "Intel ICH9", 0}, 149 {0x29258086, 0x00, "Intel ICH9", 0}, 150 {0x29278086, 0x00, "Intel ICH9", 0}, 151 {0x29298086, 0x00, "Intel ICH9M", 0}, 152 {0x292a8086, 0x00, "Intel ICH9M", 0}, 153 {0x292b8086, 0x00, "Intel ICH9M", 0}, 154 {0x292c8086, 0x00, "Intel ICH9M", 0}, 155 {0x292f8086, 0x00, "Intel ICH9M", 0}, 156 {0x294d8086, 0x00, "Intel ICH9", 0}, 157 {0x294e8086, 0x00, "Intel ICH9M", 0}, 158 {0x3a058086, 0x00, "Intel ICH10", 0}, 159 {0x3a228086, 0x00, "Intel ICH10", 0}, 160 {0x3a258086, 0x00, "Intel ICH10", 0}, 161 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 162 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 163 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 164 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 165 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 166 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 167 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 168 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 169 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 170 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 171 {0x1d028086, 0x00, "Intel Patsburg", 0}, 172 {0x1d048086, 0x00, "Intel Patsburg", 0}, 173 {0x1d068086, 0x00, "Intel Patsburg", 0}, 174 {0x1e028086, 0x00, "Intel Panther Point", 0}, 175 {0x1e038086, 0x00, "Intel Panther Point", 0}, 176 {0x1e048086, 0x00, "Intel Panther Point", 0}, 177 {0x1e058086, 0x00, "Intel Panther Point", 0}, 178 {0x1e068086, 0x00, "Intel Panther Point", 0}, 179 {0x1e078086, 0x00, "Intel Panther Point", 0}, 180 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 181 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 182 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 183 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 184 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 185 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 186 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 187 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 188 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 189 AHCI_Q_EDGEIS}, 190 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 191 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 192 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 193 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 194 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 195 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 196 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 197 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 198 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 199 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 200 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 201 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 202 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 203 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 204 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 205 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 206 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 207 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 208 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 209 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 210 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 211 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 212 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 213 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 214 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 215 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 216 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 217 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 218 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 219 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 220 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 221 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 222 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 223 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 224 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 225 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 226 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 227 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 228 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 229 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 230 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 231 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 232 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 233 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 234 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 235 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 236 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 237 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 238 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 239 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 240 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 241 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 242 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 243 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 244 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 245 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 246 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 247 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 248 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 249 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 250 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 251 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 252 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 253 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 254 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 255 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 256 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 257 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 258 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 259 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 260 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 261 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 262 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 263 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 264 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 265 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 266 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 267 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 268 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 269 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 270 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 271 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 272 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 273 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 274 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 275 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 276 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 277 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 278 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 279 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 280 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 281 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 282 {0x11841039, 0x00, "SiS 966", 0}, 283 {0x11851039, 0x00, "SiS 968", 0}, 284 {0x01861039, 0x00, "SiS 968", 0}, 285 {0x00000000, 0x00, NULL, 0} 286 }; 287 288 #define recovery_type spriv_field0 289 #define RECOVERY_NONE 0 290 #define RECOVERY_READ_LOG 1 291 #define RECOVERY_REQUEST_SENSE 2 292 #define recovery_slot spriv_field1 293 294 static int 295 ahci_probe(device_t dev) 296 { 297 char buf[64]; 298 int i, valid = 0; 299 uint32_t devid = pci_get_devid(dev); 300 uint8_t revid = pci_get_revid(dev); 301 302 /* Is this a possible AHCI candidate? */ 303 if (pci_get_class(dev) == PCIC_STORAGE && 304 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 305 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 306 valid = 1; 307 /* Is this a known AHCI chip? */ 308 for (i = 0; ahci_ids[i].id != 0; i++) { 309 if (ahci_ids[i].id == devid && 310 ahci_ids[i].rev <= revid && 311 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 312 /* Do not attach JMicrons with single PCI function. */ 313 if (pci_get_vendor(dev) == 0x197b && 314 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 315 return (ENXIO); 316 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 317 ahci_ids[i].name); 318 device_set_desc_copy(dev, buf); 319 return (BUS_PROBE_VENDOR); 320 } 321 } 322 if (!valid) 323 return (ENXIO); 324 device_set_desc_copy(dev, "AHCI SATA controller"); 325 return (BUS_PROBE_VENDOR); 326 } 327 328 static int 329 ahci_ata_probe(device_t dev) 330 { 331 char buf[64]; 332 int i; 333 uint32_t devid = pci_get_devid(dev); 334 uint8_t revid = pci_get_revid(dev); 335 336 if ((intptr_t)device_get_ivars(dev) >= 0) 337 return (ENXIO); 338 /* Is this a known AHCI chip? */ 339 for (i = 0; ahci_ids[i].id != 0; i++) { 340 if (ahci_ids[i].id == devid && 341 ahci_ids[i].rev <= revid) { 342 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 343 ahci_ids[i].name); 344 device_set_desc_copy(dev, buf); 345 return (BUS_PROBE_VENDOR); 346 } 347 } 348 device_set_desc_copy(dev, "AHCI SATA controller"); 349 return (BUS_PROBE_VENDOR); 350 } 351 352 static int 353 ahci_attach(device_t dev) 354 { 355 struct ahci_controller *ctlr = device_get_softc(dev); 356 device_t child; 357 int error, unit, speed, i; 358 uint32_t devid = pci_get_devid(dev); 359 uint8_t revid = pci_get_revid(dev); 360 u_int32_t version; 361 362 ctlr->dev = dev; 363 i = 0; 364 while (ahci_ids[i].id != 0 && 365 (ahci_ids[i].id != devid || 366 ahci_ids[i].rev > revid)) 367 i++; 368 ctlr->quirks = ahci_ids[i].quirks; 369 resource_int_value(device_get_name(dev), 370 device_get_unit(dev), "ccc", &ctlr->ccc); 371 /* if we have a memory BAR(5) we are likely on an AHCI part */ 372 ctlr->r_rid = PCIR_BAR(5); 373 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 374 &ctlr->r_rid, RF_ACTIVE))) 375 return ENXIO; 376 /* Setup our own memory management for channels. */ 377 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 378 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 379 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 380 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 381 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 382 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 383 return (error); 384 } 385 if ((error = rman_manage_region(&ctlr->sc_iomem, 386 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 387 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 388 rman_fini(&ctlr->sc_iomem); 389 return (error); 390 } 391 pci_enable_busmaster(dev); 392 /* Reset controller */ 393 if ((error = ahci_ctlr_reset(dev)) != 0) { 394 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 395 rman_fini(&ctlr->sc_iomem); 396 return (error); 397 }; 398 /* Get the HW capabilities */ 399 version = ATA_INL(ctlr->r_mem, AHCI_VS); 400 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 401 if (version >= 0x00010020) 402 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 403 if (ctlr->caps & AHCI_CAP_EMS) 404 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 405 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 406 407 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 408 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 409 (ctlr->quirks & AHCI_Q_ALTSIG) && 410 (ctlr->caps & AHCI_CAP_SPM) == 0) 411 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 412 413 if (ctlr->quirks & AHCI_Q_1CH) { 414 ctlr->caps &= ~AHCI_CAP_NPMASK; 415 ctlr->ichannels &= 0x01; 416 } 417 if (ctlr->quirks & AHCI_Q_2CH) { 418 ctlr->caps &= ~AHCI_CAP_NPMASK; 419 ctlr->caps |= 1; 420 ctlr->ichannels &= 0x03; 421 } 422 if (ctlr->quirks & AHCI_Q_4CH) { 423 ctlr->caps &= ~AHCI_CAP_NPMASK; 424 ctlr->caps |= 3; 425 ctlr->ichannels &= 0x0f; 426 } 427 ctlr->channels = MAX(flsl(ctlr->ichannels), 428 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 429 if (ctlr->quirks & AHCI_Q_NOPMP) 430 ctlr->caps &= ~AHCI_CAP_SPM; 431 if (ctlr->quirks & AHCI_Q_NONCQ) 432 ctlr->caps &= ~AHCI_CAP_SNCQ; 433 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 434 ctlr->ccc = 0; 435 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF); 436 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 437 ahci_ctlr_setup(dev); 438 /* Setup interrupts. */ 439 if (ahci_setup_interrupt(dev)) { 440 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 441 rman_fini(&ctlr->sc_iomem); 442 return ENXIO; 443 } 444 /* Announce HW capabilities. */ 445 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 446 device_printf(dev, 447 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 448 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 449 ((version >> 4) & 0xf0) + (version & 0x0f), 450 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 451 ((speed == 1) ? "1.5":((speed == 2) ? "3": 452 ((speed == 3) ? "6":"?"))), 453 (ctlr->caps & AHCI_CAP_SPM) ? 454 "supported" : "not supported", 455 (ctlr->caps & AHCI_CAP_FBSS) ? 456 " with FBS" : ""); 457 if (bootverbose) { 458 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 459 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 460 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 461 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 462 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 463 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 464 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 465 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 466 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 467 ((speed == 1) ? "1.5":((speed == 2) ? "3": 468 ((speed == 3) ? "6":"?")))); 469 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 470 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 471 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 472 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 473 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 474 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 475 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 476 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 477 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 478 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 479 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 480 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 481 } 482 if (bootverbose && version >= 0x00010020) { 483 device_printf(dev, "Caps2:%s%s%s\n", 484 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 485 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 486 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 487 } 488 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 489 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 490 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 491 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 492 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 493 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 494 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 495 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 496 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 497 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 498 } 499 /* Attach all channels on this controller */ 500 for (unit = 0; unit < ctlr->channels; unit++) { 501 if ((ctlr->ichannels & (1 << unit)) == 0) 502 continue; 503 child = device_add_child(dev, "ahcich", -1); 504 if (child == NULL) 505 device_printf(dev, "failed to add channel device\n"); 506 else 507 device_set_ivars(child, (void *)(intptr_t)unit); 508 } 509 bus_generic_attach(dev); 510 return 0; 511 } 512 513 static int 514 ahci_detach(device_t dev) 515 { 516 struct ahci_controller *ctlr = device_get_softc(dev); 517 device_t *children; 518 int nchildren, i; 519 520 /* Detach & delete all children */ 521 if (!device_get_children(dev, &children, &nchildren)) { 522 for (i = 0; i < nchildren; i++) 523 device_delete_child(dev, children[i]); 524 free(children, M_TEMP); 525 } 526 /* Free interrupts. */ 527 for (i = 0; i < ctlr->numirqs; i++) { 528 if (ctlr->irqs[i].r_irq) { 529 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 530 ctlr->irqs[i].handle); 531 bus_release_resource(dev, SYS_RES_IRQ, 532 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 533 } 534 } 535 pci_release_msi(dev); 536 /* Free memory. */ 537 rman_fini(&ctlr->sc_iomem); 538 if (ctlr->r_mem) 539 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 540 mtx_destroy(&ctlr->em_mtx); 541 return (0); 542 } 543 544 static int 545 ahci_ctlr_reset(device_t dev) 546 { 547 struct ahci_controller *ctlr = device_get_softc(dev); 548 int timeout; 549 550 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 551 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 552 pci_write_config(dev, 0x92, 0x01, 1); 553 /* Enable AHCI mode */ 554 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 555 /* Reset AHCI controller */ 556 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 557 for (timeout = 1000; timeout > 0; timeout--) { 558 DELAY(1000); 559 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 560 break; 561 } 562 if (timeout == 0) { 563 device_printf(dev, "AHCI controller reset failure\n"); 564 return ENXIO; 565 } 566 /* Reenable AHCI mode */ 567 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 568 return (0); 569 } 570 571 static int 572 ahci_ctlr_setup(device_t dev) 573 { 574 struct ahci_controller *ctlr = device_get_softc(dev); 575 /* Clear interrupts */ 576 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 577 /* Configure CCC */ 578 if (ctlr->ccc) { 579 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 580 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 581 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 582 (4 << AHCI_CCCC_CC_SHIFT) | 583 AHCI_CCCC_EN); 584 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 585 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 586 if (bootverbose) { 587 device_printf(dev, 588 "CCC with %dms/4cmd enabled on vector %d\n", 589 ctlr->ccc, ctlr->cccv); 590 } 591 } 592 /* Enable AHCI interrupts */ 593 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 594 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 595 return (0); 596 } 597 598 static int 599 ahci_suspend(device_t dev) 600 { 601 struct ahci_controller *ctlr = device_get_softc(dev); 602 603 bus_generic_suspend(dev); 604 /* Disable interupts, so the state change(s) doesn't trigger */ 605 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 606 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 607 return 0; 608 } 609 610 static int 611 ahci_resume(device_t dev) 612 { 613 int res; 614 615 if ((res = ahci_ctlr_reset(dev)) != 0) 616 return (res); 617 ahci_ctlr_setup(dev); 618 return (bus_generic_resume(dev)); 619 } 620 621 static int 622 ahci_setup_interrupt(device_t dev) 623 { 624 struct ahci_controller *ctlr = device_get_softc(dev); 625 int i, msi = 1; 626 627 /* Process hints. */ 628 resource_int_value(device_get_name(dev), 629 device_get_unit(dev), "msi", &msi); 630 if (msi < 0) 631 msi = 0; 632 else if (msi == 1) 633 msi = min(1, pci_msi_count(dev)); 634 else if (msi > 1) 635 msi = pci_msi_count(dev); 636 /* Allocate MSI if needed/present. */ 637 if (msi && pci_alloc_msi(dev, &msi) == 0) { 638 ctlr->numirqs = msi; 639 } else { 640 msi = 0; 641 ctlr->numirqs = 1; 642 } 643 /* Check for single MSI vector fallback. */ 644 if (ctlr->numirqs > 1 && 645 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 646 device_printf(dev, "Falling back to one MSI\n"); 647 ctlr->numirqs = 1; 648 } 649 /* Allocate all IRQs. */ 650 for (i = 0; i < ctlr->numirqs; i++) { 651 ctlr->irqs[i].ctlr = ctlr; 652 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 653 if (ctlr->numirqs == 1 || i >= ctlr->channels || 654 (ctlr->ccc && i == ctlr->cccv)) 655 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 656 else if (i == ctlr->numirqs - 1) 657 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 658 else 659 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 660 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 661 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 662 device_printf(dev, "unable to map interrupt\n"); 663 return ENXIO; 664 } 665 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 666 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 667 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 668 /* SOS XXX release r_irq */ 669 device_printf(dev, "unable to setup interrupt\n"); 670 return ENXIO; 671 } 672 if (ctlr->numirqs > 1) { 673 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 674 ctlr->irqs[i].handle, 675 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 676 "ch%d" : "%d", i); 677 } 678 } 679 return (0); 680 } 681 682 /* 683 * Common case interrupt handler. 684 */ 685 static void 686 ahci_intr(void *data) 687 { 688 struct ahci_controller_irq *irq = data; 689 struct ahci_controller *ctlr = irq->ctlr; 690 u_int32_t is, ise = 0; 691 void *arg; 692 int unit; 693 694 if (irq->mode == AHCI_IRQ_MODE_ALL) { 695 unit = 0; 696 if (ctlr->ccc) 697 is = ctlr->ichannels; 698 else 699 is = ATA_INL(ctlr->r_mem, AHCI_IS); 700 } else { /* AHCI_IRQ_MODE_AFTER */ 701 unit = irq->r_irq_rid - 1; 702 is = ATA_INL(ctlr->r_mem, AHCI_IS); 703 } 704 /* CCC interrupt is edge triggered. */ 705 if (ctlr->ccc) 706 ise = 1 << ctlr->cccv; 707 /* Some controllers have edge triggered IS. */ 708 if (ctlr->quirks & AHCI_Q_EDGEIS) 709 ise |= is; 710 if (ise != 0) 711 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 712 for (; unit < ctlr->channels; unit++) { 713 if ((is & (1 << unit)) != 0 && 714 (arg = ctlr->interrupt[unit].argument)) { 715 ctlr->interrupt[unit].function(arg); 716 } 717 } 718 /* AHCI declares level triggered IS. */ 719 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 720 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 721 } 722 723 /* 724 * Simplified interrupt handler for multivector MSI mode. 725 */ 726 static void 727 ahci_intr_one(void *data) 728 { 729 struct ahci_controller_irq *irq = data; 730 struct ahci_controller *ctlr = irq->ctlr; 731 void *arg; 732 int unit; 733 734 unit = irq->r_irq_rid - 1; 735 /* Some controllers have edge triggered IS. */ 736 if (ctlr->quirks & AHCI_Q_EDGEIS) 737 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 738 if ((arg = ctlr->interrupt[unit].argument)) 739 ctlr->interrupt[unit].function(arg); 740 /* AHCI declares level triggered IS. */ 741 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 742 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 743 } 744 745 static struct resource * 746 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 747 u_long start, u_long end, u_long count, u_int flags) 748 { 749 struct ahci_controller *ctlr = device_get_softc(dev); 750 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 751 struct resource *res = NULL; 752 int offset = AHCI_OFFSET + (unit << 7); 753 long st; 754 755 switch (type) { 756 case SYS_RES_MEMORY: 757 st = rman_get_start(ctlr->r_mem); 758 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 759 st + offset + 127, 128, RF_ACTIVE, child); 760 if (res) { 761 bus_space_handle_t bsh; 762 bus_space_tag_t bst; 763 bsh = rman_get_bushandle(ctlr->r_mem); 764 bst = rman_get_bustag(ctlr->r_mem); 765 bus_space_subregion(bst, bsh, offset, 128, &bsh); 766 rman_set_bushandle(res, bsh); 767 rman_set_bustag(res, bst); 768 } 769 break; 770 case SYS_RES_IRQ: 771 if (*rid == ATA_IRQ_RID) 772 res = ctlr->irqs[0].r_irq; 773 break; 774 } 775 return (res); 776 } 777 778 static int 779 ahci_release_resource(device_t dev, device_t child, int type, int rid, 780 struct resource *r) 781 { 782 783 switch (type) { 784 case SYS_RES_MEMORY: 785 rman_release_resource(r); 786 return (0); 787 case SYS_RES_IRQ: 788 if (rid != ATA_IRQ_RID) 789 return ENOENT; 790 return (0); 791 } 792 return (EINVAL); 793 } 794 795 static int 796 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 797 int flags, driver_filter_t *filter, driver_intr_t *function, 798 void *argument, void **cookiep) 799 { 800 struct ahci_controller *ctlr = device_get_softc(dev); 801 int unit = (intptr_t)device_get_ivars(child); 802 803 if (filter != NULL) { 804 printf("ahci.c: we cannot use a filter here\n"); 805 return (EINVAL); 806 } 807 ctlr->interrupt[unit].function = function; 808 ctlr->interrupt[unit].argument = argument; 809 return (0); 810 } 811 812 static int 813 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 814 void *cookie) 815 { 816 struct ahci_controller *ctlr = device_get_softc(dev); 817 int unit = (intptr_t)device_get_ivars(child); 818 819 ctlr->interrupt[unit].function = NULL; 820 ctlr->interrupt[unit].argument = NULL; 821 return (0); 822 } 823 824 static int 825 ahci_print_child(device_t dev, device_t child) 826 { 827 int retval; 828 829 retval = bus_print_child_header(dev, child); 830 retval += printf(" at channel %d", 831 (int)(intptr_t)device_get_ivars(child)); 832 retval += bus_print_child_footer(dev, child); 833 834 return (retval); 835 } 836 837 static int 838 ahci_child_location_str(device_t dev, device_t child, char *buf, 839 size_t buflen) 840 { 841 842 snprintf(buf, buflen, "channel=%d", 843 (int)(intptr_t)device_get_ivars(child)); 844 return (0); 845 } 846 847 devclass_t ahci_devclass; 848 static device_method_t ahci_methods[] = { 849 DEVMETHOD(device_probe, ahci_probe), 850 DEVMETHOD(device_attach, ahci_attach), 851 DEVMETHOD(device_detach, ahci_detach), 852 DEVMETHOD(device_suspend, ahci_suspend), 853 DEVMETHOD(device_resume, ahci_resume), 854 DEVMETHOD(bus_print_child, ahci_print_child), 855 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 856 DEVMETHOD(bus_release_resource, ahci_release_resource), 857 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 858 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 859 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 860 { 0, 0 } 861 }; 862 static driver_t ahci_driver = { 863 "ahci", 864 ahci_methods, 865 sizeof(struct ahci_controller) 866 }; 867 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 868 static device_method_t ahci_ata_methods[] = { 869 DEVMETHOD(device_probe, ahci_ata_probe), 870 DEVMETHOD(device_attach, ahci_attach), 871 DEVMETHOD(device_detach, ahci_detach), 872 DEVMETHOD(device_suspend, ahci_suspend), 873 DEVMETHOD(device_resume, ahci_resume), 874 DEVMETHOD(bus_print_child, ahci_print_child), 875 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 876 DEVMETHOD(bus_release_resource, ahci_release_resource), 877 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 878 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 879 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 880 { 0, 0 } 881 }; 882 static driver_t ahci_ata_driver = { 883 "ahci", 884 ahci_ata_methods, 885 sizeof(struct ahci_controller) 886 }; 887 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 888 MODULE_VERSION(ahci, 1); 889 MODULE_DEPEND(ahci, cam, 1, 1, 1); 890 891 static int 892 ahci_ch_probe(device_t dev) 893 { 894 895 device_set_desc_copy(dev, "AHCI channel"); 896 return (0); 897 } 898 899 static int 900 ahci_ch_attach(device_t dev) 901 { 902 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 903 struct ahci_channel *ch = device_get_softc(dev); 904 struct cam_devq *devq; 905 int rid, error, i, sata_rev = 0; 906 u_int32_t version; 907 char buf[32]; 908 909 ch->dev = dev; 910 ch->unit = (intptr_t)device_get_ivars(dev); 911 ch->caps = ctlr->caps; 912 ch->caps2 = ctlr->caps2; 913 ch->quirks = ctlr->quirks; 914 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 915 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 916 resource_int_value(device_get_name(dev), 917 device_get_unit(dev), "pm_level", &ch->pm_level); 918 if (ch->pm_level > 3) 919 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 920 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 921 /* Limit speed for my onboard JMicron external port. 922 * It is not eSATA really. */ 923 if (pci_get_devid(ctlr->dev) == 0x2363197b && 924 pci_get_subvendor(ctlr->dev) == 0x1043 && 925 pci_get_subdevice(ctlr->dev) == 0x81e4 && 926 ch->unit == 0) 927 sata_rev = 1; 928 if (ch->quirks & AHCI_Q_SATA2) 929 sata_rev = 2; 930 resource_int_value(device_get_name(dev), 931 device_get_unit(dev), "sata_rev", &sata_rev); 932 for (i = 0; i < 16; i++) { 933 ch->user[i].revision = sata_rev; 934 ch->user[i].mode = 0; 935 ch->user[i].bytecount = 8192; 936 ch->user[i].tags = ch->numslots; 937 ch->user[i].caps = 0; 938 ch->curr[i] = ch->user[i]; 939 if (ch->pm_level) { 940 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 941 CTS_SATA_CAPS_H_APST | 942 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 943 } 944 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 945 CTS_SATA_CAPS_H_AN; 946 } 947 rid = ch->unit; 948 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 949 &rid, RF_ACTIVE))) 950 return (ENXIO); 951 ahci_dmainit(dev); 952 ahci_slotsalloc(dev); 953 ahci_ch_init(dev); 954 mtx_lock(&ch->mtx); 955 rid = ATA_IRQ_RID; 956 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 957 &rid, RF_SHAREABLE | RF_ACTIVE))) { 958 device_printf(dev, "Unable to map interrupt\n"); 959 error = ENXIO; 960 goto err0; 961 } 962 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 963 ahci_ch_intr_locked, dev, &ch->ih))) { 964 device_printf(dev, "Unable to setup interrupt\n"); 965 error = ENXIO; 966 goto err1; 967 } 968 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 969 version = ATA_INL(ctlr->r_mem, AHCI_VS); 970 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 971 ch->chcaps |= AHCI_P_CMD_FBSCP; 972 if (bootverbose) { 973 device_printf(dev, "Caps:%s%s%s%s%s\n", 974 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 975 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 976 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 977 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 978 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 979 } 980 /* Create the device queue for our SIM. */ 981 devq = cam_simq_alloc(ch->numslots); 982 if (devq == NULL) { 983 device_printf(dev, "Unable to allocate simq\n"); 984 error = ENOMEM; 985 goto err1; 986 } 987 /* Construct SIM entry */ 988 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 989 device_get_unit(dev), &ch->mtx, 990 min(2, ch->numslots), 991 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 992 devq); 993 if (ch->sim == NULL) { 994 cam_simq_free(devq); 995 device_printf(dev, "unable to allocate sim\n"); 996 error = ENOMEM; 997 goto err1; 998 } 999 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1000 device_printf(dev, "unable to register xpt bus\n"); 1001 error = ENXIO; 1002 goto err2; 1003 } 1004 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1005 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1006 device_printf(dev, "unable to create path\n"); 1007 error = ENXIO; 1008 goto err3; 1009 } 1010 if (ch->pm_level > 3) { 1011 callout_reset(&ch->pm_timer, 1012 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1013 ahci_ch_pm, dev); 1014 } 1015 mtx_unlock(&ch->mtx); 1016 if ((ch->caps & AHCI_CAP_EMS) && 1017 (ctlr->capsem & AHCI_EM_LED)) { 1018 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1019 ch->leds[i].dev = dev; 1020 ch->leds[i].num = i; 1021 } 1022 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) { 1023 snprintf(buf, sizeof(buf), "%s.act", 1024 device_get_nameunit(dev)); 1025 ch->leds[0].led = led_create(ahci_ch_led, 1026 &ch->leds[0], buf); 1027 } 1028 snprintf(buf, sizeof(buf), "%s.locate", 1029 device_get_nameunit(dev)); 1030 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf); 1031 snprintf(buf, sizeof(buf), "%s.fault", 1032 device_get_nameunit(dev)); 1033 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf); 1034 } 1035 return (0); 1036 1037 err3: 1038 xpt_bus_deregister(cam_sim_path(ch->sim)); 1039 err2: 1040 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1041 err1: 1042 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1043 err0: 1044 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1045 mtx_unlock(&ch->mtx); 1046 mtx_destroy(&ch->mtx); 1047 return (error); 1048 } 1049 1050 static int 1051 ahci_ch_detach(device_t dev) 1052 { 1053 struct ahci_channel *ch = device_get_softc(dev); 1054 int i; 1055 1056 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1057 if (ch->leds[i].led) 1058 led_destroy(ch->leds[i].led); 1059 } 1060 mtx_lock(&ch->mtx); 1061 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1062 /* Forget about reset. */ 1063 if (ch->resetting) { 1064 ch->resetting = 0; 1065 xpt_release_simq(ch->sim, TRUE); 1066 } 1067 xpt_free_path(ch->path); 1068 xpt_bus_deregister(cam_sim_path(ch->sim)); 1069 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1070 mtx_unlock(&ch->mtx); 1071 1072 if (ch->pm_level > 3) 1073 callout_drain(&ch->pm_timer); 1074 callout_drain(&ch->reset_timer); 1075 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1076 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1077 1078 ahci_ch_deinit(dev); 1079 ahci_slotsfree(dev); 1080 ahci_dmafini(dev); 1081 1082 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1083 mtx_destroy(&ch->mtx); 1084 return (0); 1085 } 1086 1087 static int 1088 ahci_ch_init(device_t dev) 1089 { 1090 struct ahci_channel *ch = device_get_softc(dev); 1091 uint64_t work; 1092 1093 /* Disable port interrupts */ 1094 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1095 /* Setup work areas */ 1096 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1097 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1098 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1099 work = ch->dma.rfis_bus; 1100 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1101 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1102 /* Activate the channel and power/spin up device */ 1103 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1104 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1105 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1106 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1107 ahci_start_fr(dev); 1108 ahci_start(dev, 1); 1109 return (0); 1110 } 1111 1112 static int 1113 ahci_ch_deinit(device_t dev) 1114 { 1115 struct ahci_channel *ch = device_get_softc(dev); 1116 1117 /* Disable port interrupts. */ 1118 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1119 /* Reset command register. */ 1120 ahci_stop(dev); 1121 ahci_stop_fr(dev); 1122 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1123 /* Allow everything, including partial and slumber modes. */ 1124 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1125 /* Request slumber mode transition and give some time to get there. */ 1126 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1127 DELAY(100); 1128 /* Disable PHY. */ 1129 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1130 return (0); 1131 } 1132 1133 static int 1134 ahci_ch_suspend(device_t dev) 1135 { 1136 struct ahci_channel *ch = device_get_softc(dev); 1137 1138 mtx_lock(&ch->mtx); 1139 xpt_freeze_simq(ch->sim, 1); 1140 /* Forget about reset. */ 1141 if (ch->resetting) { 1142 ch->resetting = 0; 1143 callout_stop(&ch->reset_timer); 1144 xpt_release_simq(ch->sim, TRUE); 1145 } 1146 while (ch->oslots) 1147 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1148 ahci_ch_deinit(dev); 1149 mtx_unlock(&ch->mtx); 1150 return (0); 1151 } 1152 1153 static int 1154 ahci_ch_resume(device_t dev) 1155 { 1156 struct ahci_channel *ch = device_get_softc(dev); 1157 1158 mtx_lock(&ch->mtx); 1159 ahci_ch_init(dev); 1160 ahci_reset(dev); 1161 xpt_release_simq(ch->sim, TRUE); 1162 mtx_unlock(&ch->mtx); 1163 return (0); 1164 } 1165 1166 devclass_t ahcich_devclass; 1167 static device_method_t ahcich_methods[] = { 1168 DEVMETHOD(device_probe, ahci_ch_probe), 1169 DEVMETHOD(device_attach, ahci_ch_attach), 1170 DEVMETHOD(device_detach, ahci_ch_detach), 1171 DEVMETHOD(device_suspend, ahci_ch_suspend), 1172 DEVMETHOD(device_resume, ahci_ch_resume), 1173 { 0, 0 } 1174 }; 1175 static driver_t ahcich_driver = { 1176 "ahcich", 1177 ahcich_methods, 1178 sizeof(struct ahci_channel) 1179 }; 1180 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1181 1182 static void 1183 ahci_ch_setleds(device_t dev) 1184 { 1185 struct ahci_channel *ch; 1186 struct ahci_controller *ctlr; 1187 size_t buf; 1188 int i, timeout; 1189 int16_t val; 1190 1191 ctlr = device_get_softc(device_get_parent(dev)); 1192 ch = device_get_softc(dev); 1193 1194 val = 0; 1195 for (i = 0; i < AHCI_NUM_LEDS; i++) 1196 val |= ch->leds[i].state << (i * 3); 1197 1198 buf = (ctlr->emloc & 0xffff0000) >> 14; 1199 mtx_lock(&ctlr->em_mtx); 1200 timeout = 1000; 1201 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) && 1202 --timeout > 0) 1203 DELAY(1000); 1204 if (timeout == 0) 1205 device_printf(dev, "EM timeout\n"); 1206 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24)); 1207 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16)); 1208 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM); 1209 mtx_unlock(&ctlr->em_mtx); 1210 } 1211 1212 static void 1213 ahci_ch_led(void *priv, int onoff) 1214 { 1215 struct ahci_led *led; 1216 1217 led = (struct ahci_led *)priv; 1218 1219 led->state = onoff; 1220 ahci_ch_setleds(led->dev); 1221 } 1222 1223 struct ahci_dc_cb_args { 1224 bus_addr_t maddr; 1225 int error; 1226 }; 1227 1228 static void 1229 ahci_dmainit(device_t dev) 1230 { 1231 struct ahci_channel *ch = device_get_softc(dev); 1232 struct ahci_dc_cb_args dcba; 1233 size_t rfsize; 1234 1235 if (ch->caps & AHCI_CAP_64BIT) 1236 ch->dma.max_address = BUS_SPACE_MAXADDR; 1237 else 1238 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1239 /* Command area. */ 1240 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1241 ch->dma.max_address, BUS_SPACE_MAXADDR, 1242 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1243 0, NULL, NULL, &ch->dma.work_tag)) 1244 goto error; 1245 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1246 &ch->dma.work_map)) 1247 goto error; 1248 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1249 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1250 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1251 goto error; 1252 } 1253 ch->dma.work_bus = dcba.maddr; 1254 /* FIS receive area. */ 1255 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1256 rfsize = 4096; 1257 else 1258 rfsize = 256; 1259 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1260 ch->dma.max_address, BUS_SPACE_MAXADDR, 1261 NULL, NULL, rfsize, 1, rfsize, 1262 0, NULL, NULL, &ch->dma.rfis_tag)) 1263 goto error; 1264 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1265 &ch->dma.rfis_map)) 1266 goto error; 1267 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1268 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1269 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1270 goto error; 1271 } 1272 ch->dma.rfis_bus = dcba.maddr; 1273 /* Data area. */ 1274 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1275 ch->dma.max_address, BUS_SPACE_MAXADDR, 1276 NULL, NULL, 1277 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1278 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1279 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1280 goto error; 1281 } 1282 return; 1283 1284 error: 1285 device_printf(dev, "WARNING - DMA initialization failed\n"); 1286 ahci_dmafini(dev); 1287 } 1288 1289 static void 1290 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1291 { 1292 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1293 1294 if (!(dcba->error = error)) 1295 dcba->maddr = segs[0].ds_addr; 1296 } 1297 1298 static void 1299 ahci_dmafini(device_t dev) 1300 { 1301 struct ahci_channel *ch = device_get_softc(dev); 1302 1303 if (ch->dma.data_tag) { 1304 bus_dma_tag_destroy(ch->dma.data_tag); 1305 ch->dma.data_tag = NULL; 1306 } 1307 if (ch->dma.rfis_bus) { 1308 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1309 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1310 ch->dma.rfis_bus = 0; 1311 ch->dma.rfis_map = NULL; 1312 ch->dma.rfis = NULL; 1313 } 1314 if (ch->dma.work_bus) { 1315 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1316 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1317 ch->dma.work_bus = 0; 1318 ch->dma.work_map = NULL; 1319 ch->dma.work = NULL; 1320 } 1321 if (ch->dma.work_tag) { 1322 bus_dma_tag_destroy(ch->dma.work_tag); 1323 ch->dma.work_tag = NULL; 1324 } 1325 } 1326 1327 static void 1328 ahci_slotsalloc(device_t dev) 1329 { 1330 struct ahci_channel *ch = device_get_softc(dev); 1331 int i; 1332 1333 /* Alloc and setup command/dma slots */ 1334 bzero(ch->slot, sizeof(ch->slot)); 1335 for (i = 0; i < ch->numslots; i++) { 1336 struct ahci_slot *slot = &ch->slot[i]; 1337 1338 slot->dev = dev; 1339 slot->slot = i; 1340 slot->state = AHCI_SLOT_EMPTY; 1341 slot->ccb = NULL; 1342 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1343 1344 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1345 device_printf(ch->dev, "FAILURE - create data_map\n"); 1346 } 1347 } 1348 1349 static void 1350 ahci_slotsfree(device_t dev) 1351 { 1352 struct ahci_channel *ch = device_get_softc(dev); 1353 int i; 1354 1355 /* Free all dma slots */ 1356 for (i = 0; i < ch->numslots; i++) { 1357 struct ahci_slot *slot = &ch->slot[i]; 1358 1359 callout_drain(&slot->timeout); 1360 if (slot->dma.data_map) { 1361 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1362 slot->dma.data_map = NULL; 1363 } 1364 } 1365 } 1366 1367 static int 1368 ahci_phy_check_events(device_t dev, u_int32_t serr) 1369 { 1370 struct ahci_channel *ch = device_get_softc(dev); 1371 1372 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1373 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1374 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1375 union ccb *ccb; 1376 1377 if (bootverbose) { 1378 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1379 device_printf(dev, "CONNECT requested\n"); 1380 else 1381 device_printf(dev, "DISCONNECT requested\n"); 1382 } 1383 ahci_reset(dev); 1384 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1385 return (0); 1386 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1387 cam_sim_path(ch->sim), 1388 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1389 xpt_free_ccb(ccb); 1390 return (0); 1391 } 1392 xpt_rescan(ccb); 1393 return (1); 1394 } 1395 return (0); 1396 } 1397 1398 static void 1399 ahci_cpd_check_events(device_t dev) 1400 { 1401 struct ahci_channel *ch = device_get_softc(dev); 1402 u_int32_t status; 1403 union ccb *ccb; 1404 1405 if (ch->pm_level == 0) 1406 return; 1407 1408 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1409 if ((status & AHCI_P_CMD_CPD) == 0) 1410 return; 1411 1412 if (bootverbose) { 1413 if (status & AHCI_P_CMD_CPS) { 1414 device_printf(dev, "COLD CONNECT requested\n"); 1415 } else 1416 device_printf(dev, "COLD DISCONNECT requested\n"); 1417 } 1418 ahci_reset(dev); 1419 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1420 return; 1421 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1422 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1423 xpt_free_ccb(ccb); 1424 return; 1425 } 1426 xpt_rescan(ccb); 1427 } 1428 1429 static void 1430 ahci_notify_events(device_t dev, u_int32_t status) 1431 { 1432 struct ahci_channel *ch = device_get_softc(dev); 1433 struct cam_path *dpath; 1434 int i; 1435 1436 if (ch->caps & AHCI_CAP_SSNTF) 1437 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1438 if (bootverbose) 1439 device_printf(dev, "SNTF 0x%04x\n", status); 1440 for (i = 0; i < 16; i++) { 1441 if ((status & (1 << i)) == 0) 1442 continue; 1443 if (xpt_create_path(&dpath, NULL, 1444 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1445 xpt_async(AC_SCSI_AEN, dpath, NULL); 1446 xpt_free_path(dpath); 1447 } 1448 } 1449 } 1450 1451 static void 1452 ahci_ch_intr_locked(void *data) 1453 { 1454 device_t dev = (device_t)data; 1455 struct ahci_channel *ch = device_get_softc(dev); 1456 1457 mtx_lock(&ch->mtx); 1458 ahci_ch_intr(data); 1459 mtx_unlock(&ch->mtx); 1460 } 1461 1462 static void 1463 ahci_ch_pm(void *arg) 1464 { 1465 device_t dev = (device_t)arg; 1466 struct ahci_channel *ch = device_get_softc(dev); 1467 uint32_t work; 1468 1469 if (ch->numrslots != 0) 1470 return; 1471 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1472 if (ch->pm_level == 4) 1473 work |= AHCI_P_CMD_PARTIAL; 1474 else 1475 work |= AHCI_P_CMD_SLUMBER; 1476 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1477 } 1478 1479 static void 1480 ahci_ch_intr(void *data) 1481 { 1482 device_t dev = (device_t)data; 1483 struct ahci_channel *ch = device_get_softc(dev); 1484 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1485 enum ahci_err_type et; 1486 int i, ccs, port, reset = 0; 1487 1488 /* Read and clear interrupt statuses. */ 1489 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1490 if (istatus == 0) 1491 return; 1492 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1493 /* Read command statuses. */ 1494 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1495 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1496 if (istatus & AHCI_P_IX_SDB) { 1497 if (ch->caps & AHCI_CAP_SSNTF) 1498 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1499 else if (ch->fbs_enabled) { 1500 u_int8_t *fis = ch->dma.rfis + 0x58; 1501 1502 for (i = 0; i < 16; i++) { 1503 if (fis[1] & 0x80) { 1504 fis[1] &= 0x7f; 1505 sntf |= 1 << i; 1506 } 1507 fis += 256; 1508 } 1509 } else { 1510 u_int8_t *fis = ch->dma.rfis + 0x58; 1511 1512 if (fis[1] & 0x80) 1513 sntf = (1 << (fis[1] & 0x0f)); 1514 } 1515 } 1516 /* Process PHY events */ 1517 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1518 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1519 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1520 if (serr) { 1521 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1522 reset = ahci_phy_check_events(dev, serr); 1523 } 1524 } 1525 /* Process cold presence detection events */ 1526 if ((istatus & AHCI_P_IX_CPD) && !reset) 1527 ahci_cpd_check_events(dev); 1528 /* Process command errors */ 1529 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1530 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1531 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1532 >> AHCI_P_CMD_CCS_SHIFT; 1533 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1534 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1535 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1536 port = -1; 1537 if (ch->fbs_enabled) { 1538 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1539 if (fbs & AHCI_P_FBS_SDE) { 1540 port = (fbs & AHCI_P_FBS_DWE) 1541 >> AHCI_P_FBS_DWE_SHIFT; 1542 } else { 1543 for (i = 0; i < 16; i++) { 1544 if (ch->numrslotspd[i] == 0) 1545 continue; 1546 if (port == -1) 1547 port = i; 1548 else if (port != i) { 1549 port = -2; 1550 break; 1551 } 1552 } 1553 } 1554 } 1555 err = ch->rslots & (cstatus | sstatus); 1556 } else { 1557 ccs = 0; 1558 err = 0; 1559 port = -1; 1560 } 1561 /* Complete all successfull commands. */ 1562 ok = ch->rslots & ~(cstatus | sstatus); 1563 for (i = 0; i < ch->numslots; i++) { 1564 if ((ok >> i) & 1) 1565 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1566 } 1567 /* On error, complete the rest of commands with error statuses. */ 1568 if (err) { 1569 if (ch->frozen) { 1570 union ccb *fccb = ch->frozen; 1571 ch->frozen = NULL; 1572 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1573 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1574 xpt_freeze_devq(fccb->ccb_h.path, 1); 1575 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1576 } 1577 xpt_done(fccb); 1578 } 1579 for (i = 0; i < ch->numslots; i++) { 1580 /* XXX: reqests in loading state. */ 1581 if (((err >> i) & 1) == 0) 1582 continue; 1583 if (port >= 0 && 1584 ch->slot[i].ccb->ccb_h.target_id != port) 1585 continue; 1586 if (istatus & AHCI_P_IX_TFE) { 1587 if (port != -2) { 1588 /* Task File Error */ 1589 if (ch->numtslotspd[ 1590 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1591 /* Untagged operation. */ 1592 if (i == ccs) 1593 et = AHCI_ERR_TFE; 1594 else 1595 et = AHCI_ERR_INNOCENT; 1596 } else { 1597 /* Tagged operation. */ 1598 et = AHCI_ERR_NCQ; 1599 } 1600 } else { 1601 et = AHCI_ERR_TFE; 1602 ch->fatalerr = 1; 1603 } 1604 } else if (istatus & AHCI_P_IX_IF) { 1605 if (ch->numtslots == 0 && i != ccs && port != -2) 1606 et = AHCI_ERR_INNOCENT; 1607 else 1608 et = AHCI_ERR_SATA; 1609 } else 1610 et = AHCI_ERR_INVALID; 1611 ahci_end_transaction(&ch->slot[i], et); 1612 } 1613 /* 1614 * We can't reinit port if there are some other 1615 * commands active, use resume to complete them. 1616 */ 1617 if (ch->rslots != 0 && !ch->recoverycmd) 1618 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1619 } 1620 /* Process NOTIFY events */ 1621 if (sntf) 1622 ahci_notify_events(dev, sntf); 1623 } 1624 1625 /* Must be called with channel locked. */ 1626 static int 1627 ahci_check_collision(device_t dev, union ccb *ccb) 1628 { 1629 struct ahci_channel *ch = device_get_softc(dev); 1630 int t = ccb->ccb_h.target_id; 1631 1632 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1633 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1634 /* Tagged command while we have no supported tag free. */ 1635 if (((~ch->oslots) & (0xffffffff >> (32 - 1636 ch->curr[t].tags))) == 0) 1637 return (1); 1638 /* If we have FBS */ 1639 if (ch->fbs_enabled) { 1640 /* Tagged command while untagged are active. */ 1641 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1642 return (1); 1643 } else { 1644 /* Tagged command while untagged are active. */ 1645 if (ch->numrslots != 0 && ch->numtslots == 0) 1646 return (1); 1647 /* Tagged command while tagged to other target is active. */ 1648 if (ch->numtslots != 0 && 1649 ch->taggedtarget != ccb->ccb_h.target_id) 1650 return (1); 1651 } 1652 } else { 1653 /* If we have FBS */ 1654 if (ch->fbs_enabled) { 1655 /* Untagged command while tagged are active. */ 1656 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1657 return (1); 1658 } else { 1659 /* Untagged command while tagged are active. */ 1660 if (ch->numrslots != 0 && ch->numtslots != 0) 1661 return (1); 1662 } 1663 } 1664 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1665 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1666 /* Atomic command while anything active. */ 1667 if (ch->numrslots != 0) 1668 return (1); 1669 } 1670 /* We have some atomic command running. */ 1671 if (ch->aslots != 0) 1672 return (1); 1673 return (0); 1674 } 1675 1676 /* Must be called with channel locked. */ 1677 static void 1678 ahci_begin_transaction(device_t dev, union ccb *ccb) 1679 { 1680 struct ahci_channel *ch = device_get_softc(dev); 1681 struct ahci_slot *slot; 1682 int tag, tags; 1683 1684 /* Choose empty slot. */ 1685 tags = ch->numslots; 1686 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1687 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1688 tags = ch->curr[ccb->ccb_h.target_id].tags; 1689 tag = ch->lastslot; 1690 while (1) { 1691 if (tag >= tags) 1692 tag = 0; 1693 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1694 break; 1695 tag++; 1696 }; 1697 ch->lastslot = tag; 1698 /* Occupy chosen slot. */ 1699 slot = &ch->slot[tag]; 1700 slot->ccb = ccb; 1701 /* Stop PM timer. */ 1702 if (ch->numrslots == 0 && ch->pm_level > 3) 1703 callout_stop(&ch->pm_timer); 1704 /* Update channel stats. */ 1705 ch->oslots |= (1 << slot->slot); 1706 ch->numrslots++; 1707 ch->numrslotspd[ccb->ccb_h.target_id]++; 1708 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1709 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1710 ch->numtslots++; 1711 ch->numtslotspd[ccb->ccb_h.target_id]++; 1712 ch->taggedtarget = ccb->ccb_h.target_id; 1713 } 1714 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1715 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1716 ch->aslots |= (1 << slot->slot); 1717 slot->dma.nsegs = 0; 1718 /* If request moves data, setup and load SG list */ 1719 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1720 void *buf; 1721 bus_size_t size; 1722 1723 slot->state = AHCI_SLOT_LOADING; 1724 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1725 buf = ccb->ataio.data_ptr; 1726 size = ccb->ataio.dxfer_len; 1727 } else { 1728 buf = ccb->csio.data_ptr; 1729 size = ccb->csio.dxfer_len; 1730 } 1731 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1732 buf, size, ahci_dmasetprd, slot, 0); 1733 } else 1734 ahci_execute_transaction(slot); 1735 } 1736 1737 /* Locked by busdma engine. */ 1738 static void 1739 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1740 { 1741 struct ahci_slot *slot = arg; 1742 struct ahci_channel *ch = device_get_softc(slot->dev); 1743 struct ahci_cmd_tab *ctp; 1744 struct ahci_dma_prd *prd; 1745 int i; 1746 1747 if (error) { 1748 device_printf(slot->dev, "DMA load error\n"); 1749 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1750 return; 1751 } 1752 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1753 /* Get a piece of the workspace for this request */ 1754 ctp = (struct ahci_cmd_tab *) 1755 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1756 /* Fill S/G table */ 1757 prd = &ctp->prd_tab[0]; 1758 for (i = 0; i < nsegs; i++) { 1759 prd[i].dba = htole64(segs[i].ds_addr); 1760 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1761 } 1762 slot->dma.nsegs = nsegs; 1763 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1764 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1765 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1766 ahci_execute_transaction(slot); 1767 } 1768 1769 /* Must be called with channel locked. */ 1770 static void 1771 ahci_execute_transaction(struct ahci_slot *slot) 1772 { 1773 device_t dev = slot->dev; 1774 struct ahci_channel *ch = device_get_softc(dev); 1775 struct ahci_cmd_tab *ctp; 1776 struct ahci_cmd_list *clp; 1777 union ccb *ccb = slot->ccb; 1778 int port = ccb->ccb_h.target_id & 0x0f; 1779 int fis_size, i, softreset; 1780 uint8_t *fis = ch->dma.rfis + 0x40; 1781 uint8_t val; 1782 1783 /* Get a piece of the workspace for this request */ 1784 ctp = (struct ahci_cmd_tab *) 1785 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1786 /* Setup the FIS for this request */ 1787 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1788 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1789 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1790 return; 1791 } 1792 /* Setup the command list entry */ 1793 clp = (struct ahci_cmd_list *) 1794 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1795 clp->cmd_flags = htole16( 1796 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1797 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1798 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1799 (fis_size / sizeof(u_int32_t)) | 1800 (port << 12)); 1801 clp->prd_length = htole16(slot->dma.nsegs); 1802 /* Special handling for Soft Reset command. */ 1803 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1804 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1805 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1806 softreset = 1; 1807 /* Kick controller into sane state */ 1808 ahci_stop(dev); 1809 ahci_clo(dev); 1810 ahci_start(dev, 0); 1811 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1812 } else { 1813 softreset = 2; 1814 /* Prepare FIS receive area for check. */ 1815 for (i = 0; i < 20; i++) 1816 fis[i] = 0xff; 1817 } 1818 } else 1819 softreset = 0; 1820 clp->bytecount = 0; 1821 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1822 (AHCI_CT_SIZE * slot->slot)); 1823 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1824 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1825 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1826 BUS_DMASYNC_PREREAD); 1827 /* Set ACTIVE bit for NCQ commands. */ 1828 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1829 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1830 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1831 } 1832 /* If FBS is enabled, set PMP port. */ 1833 if (ch->fbs_enabled) { 1834 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1835 (port << AHCI_P_FBS_DEV_SHIFT)); 1836 } 1837 /* Issue command to the controller. */ 1838 slot->state = AHCI_SLOT_RUNNING; 1839 ch->rslots |= (1 << slot->slot); 1840 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1841 /* Device reset commands doesn't interrupt. Poll them. */ 1842 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1843 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1844 int count, timeout = ccb->ccb_h.timeout * 100; 1845 enum ahci_err_type et = AHCI_ERR_NONE; 1846 1847 for (count = 0; count < timeout; count++) { 1848 DELAY(10); 1849 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1850 break; 1851 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1852 softreset != 1) { 1853 #if 0 1854 device_printf(ch->dev, 1855 "Poll error on slot %d, TFD: %04x\n", 1856 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1857 #endif 1858 et = AHCI_ERR_TFE; 1859 break; 1860 } 1861 /* Workaround for ATI SB600/SB700 chipsets. */ 1862 if (ccb->ccb_h.target_id == 15 && 1863 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1864 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1865 et = AHCI_ERR_TIMEOUT; 1866 break; 1867 } 1868 } 1869 1870 /* Marvell controllers do not wait for readyness. */ 1871 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1872 et == AHCI_ERR_NONE) { 1873 while ((val = fis[2]) & ATA_S_BUSY) { 1874 DELAY(10); 1875 if (count++ >= timeout) 1876 break; 1877 } 1878 } 1879 1880 if (timeout && (count >= timeout)) { 1881 device_printf(dev, "Poll timeout on slot %d port %d\n", 1882 slot->slot, port); 1883 device_printf(dev, "is %08x cs %08x ss %08x " 1884 "rs %08x tfd %02x serr %08x cmd %08x\n", 1885 ATA_INL(ch->r_mem, AHCI_P_IS), 1886 ATA_INL(ch->r_mem, AHCI_P_CI), 1887 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1888 ATA_INL(ch->r_mem, AHCI_P_TFD), 1889 ATA_INL(ch->r_mem, AHCI_P_SERR), 1890 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1891 et = AHCI_ERR_TIMEOUT; 1892 } 1893 1894 /* Kick controller into sane state and enable FBS. */ 1895 if (softreset == 2) 1896 ch->eslots |= (1 << slot->slot); 1897 ahci_end_transaction(slot, et); 1898 return; 1899 } 1900 /* Start command execution timeout */ 1901 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1902 (timeout_t*)ahci_timeout, slot); 1903 return; 1904 } 1905 1906 /* Must be called with channel locked. */ 1907 static void 1908 ahci_process_timeout(device_t dev) 1909 { 1910 struct ahci_channel *ch = device_get_softc(dev); 1911 int i; 1912 1913 mtx_assert(&ch->mtx, MA_OWNED); 1914 /* Handle the rest of commands. */ 1915 for (i = 0; i < ch->numslots; i++) { 1916 /* Do we have a running request on slot? */ 1917 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1918 continue; 1919 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1920 } 1921 } 1922 1923 /* Must be called with channel locked. */ 1924 static void 1925 ahci_rearm_timeout(device_t dev) 1926 { 1927 struct ahci_channel *ch = device_get_softc(dev); 1928 int i; 1929 1930 mtx_assert(&ch->mtx, MA_OWNED); 1931 for (i = 0; i < ch->numslots; i++) { 1932 struct ahci_slot *slot = &ch->slot[i]; 1933 1934 /* Do we have a running request on slot? */ 1935 if (slot->state < AHCI_SLOT_RUNNING) 1936 continue; 1937 if ((ch->toslots & (1 << i)) == 0) 1938 continue; 1939 callout_reset(&slot->timeout, 1940 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1941 (timeout_t*)ahci_timeout, slot); 1942 } 1943 } 1944 1945 /* Locked by callout mechanism. */ 1946 static void 1947 ahci_timeout(struct ahci_slot *slot) 1948 { 1949 device_t dev = slot->dev; 1950 struct ahci_channel *ch = device_get_softc(dev); 1951 uint32_t sstatus; 1952 int ccs; 1953 int i; 1954 1955 /* Check for stale timeout. */ 1956 if (slot->state < AHCI_SLOT_RUNNING) 1957 return; 1958 1959 /* Check if slot was not being executed last time we checked. */ 1960 if (slot->state < AHCI_SLOT_EXECUTING) { 1961 /* Check if slot started executing. */ 1962 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1963 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1964 >> AHCI_P_CMD_CCS_SHIFT; 1965 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1966 ch->fbs_enabled || ch->wrongccs) 1967 slot->state = AHCI_SLOT_EXECUTING; 1968 else if ((ch->rslots & (1 << ccs)) == 0) { 1969 ch->wrongccs = 1; 1970 slot->state = AHCI_SLOT_EXECUTING; 1971 } 1972 1973 callout_reset(&slot->timeout, 1974 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1975 (timeout_t*)ahci_timeout, slot); 1976 return; 1977 } 1978 1979 device_printf(dev, "Timeout on slot %d port %d\n", 1980 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1981 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1982 "serr %08x cmd %08x\n", 1983 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1984 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1985 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1986 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1987 1988 /* Handle frozen command. */ 1989 if (ch->frozen) { 1990 union ccb *fccb = ch->frozen; 1991 ch->frozen = NULL; 1992 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1993 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1994 xpt_freeze_devq(fccb->ccb_h.path, 1); 1995 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1996 } 1997 xpt_done(fccb); 1998 } 1999 if (!ch->fbs_enabled && !ch->wrongccs) { 2000 /* Without FBS we know real timeout source. */ 2001 ch->fatalerr = 1; 2002 /* Handle command with timeout. */ 2003 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2004 /* Handle the rest of commands. */ 2005 for (i = 0; i < ch->numslots; i++) { 2006 /* Do we have a running request on slot? */ 2007 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2008 continue; 2009 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2010 } 2011 } else { 2012 /* With FBS we wait for other commands timeout and pray. */ 2013 if (ch->toslots == 0) 2014 xpt_freeze_simq(ch->sim, 1); 2015 ch->toslots |= (1 << slot->slot); 2016 if ((ch->rslots & ~ch->toslots) == 0) 2017 ahci_process_timeout(dev); 2018 else 2019 device_printf(dev, " ... waiting for slots %08x\n", 2020 ch->rslots & ~ch->toslots); 2021 } 2022 } 2023 2024 /* Must be called with channel locked. */ 2025 static void 2026 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2027 { 2028 device_t dev = slot->dev; 2029 struct ahci_channel *ch = device_get_softc(dev); 2030 union ccb *ccb = slot->ccb; 2031 struct ahci_cmd_list *clp; 2032 int lastto; 2033 uint32_t sig; 2034 2035 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2036 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2037 clp = (struct ahci_cmd_list *) 2038 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2039 /* Read result registers to the result struct 2040 * May be incorrect if several commands finished same time, 2041 * so read only when sure or have to. 2042 */ 2043 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2044 struct ata_res *res = &ccb->ataio.res; 2045 2046 if ((et == AHCI_ERR_TFE) || 2047 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2048 u_int8_t *fis = ch->dma.rfis + 0x40; 2049 2050 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2051 BUS_DMASYNC_POSTREAD); 2052 if (ch->fbs_enabled) { 2053 fis += ccb->ccb_h.target_id * 256; 2054 res->status = fis[2]; 2055 res->error = fis[3]; 2056 } else { 2057 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2058 2059 res->status = tfd; 2060 res->error = tfd >> 8; 2061 } 2062 res->lba_low = fis[4]; 2063 res->lba_mid = fis[5]; 2064 res->lba_high = fis[6]; 2065 res->device = fis[7]; 2066 res->lba_low_exp = fis[8]; 2067 res->lba_mid_exp = fis[9]; 2068 res->lba_high_exp = fis[10]; 2069 res->sector_count = fis[12]; 2070 res->sector_count_exp = fis[13]; 2071 2072 /* 2073 * Some weird controllers do not return signature in 2074 * FIS receive area. Read it from PxSIG register. 2075 */ 2076 if ((ch->quirks & AHCI_Q_ALTSIG) && 2077 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2078 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2079 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2080 res->lba_high = sig >> 24; 2081 res->lba_mid = sig >> 16; 2082 res->lba_low = sig >> 8; 2083 res->sector_count = sig; 2084 } 2085 } else 2086 bzero(res, sizeof(*res)); 2087 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2088 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2089 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2090 ccb->ataio.resid = 2091 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2092 } 2093 } else { 2094 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2095 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2096 ccb->csio.resid = 2097 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2098 } 2099 } 2100 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2101 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2102 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2103 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2104 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2105 } 2106 if (et != AHCI_ERR_NONE) 2107 ch->eslots |= (1 << slot->slot); 2108 /* In case of error, freeze device for proper recovery. */ 2109 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2110 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2111 xpt_freeze_devq(ccb->ccb_h.path, 1); 2112 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2113 } 2114 /* Set proper result status. */ 2115 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2116 switch (et) { 2117 case AHCI_ERR_NONE: 2118 ccb->ccb_h.status |= CAM_REQ_CMP; 2119 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2120 ccb->csio.scsi_status = SCSI_STATUS_OK; 2121 break; 2122 case AHCI_ERR_INVALID: 2123 ch->fatalerr = 1; 2124 ccb->ccb_h.status |= CAM_REQ_INVALID; 2125 break; 2126 case AHCI_ERR_INNOCENT: 2127 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2128 break; 2129 case AHCI_ERR_TFE: 2130 case AHCI_ERR_NCQ: 2131 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2132 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2133 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2134 } else { 2135 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2136 } 2137 break; 2138 case AHCI_ERR_SATA: 2139 ch->fatalerr = 1; 2140 if (!ch->recoverycmd) { 2141 xpt_freeze_simq(ch->sim, 1); 2142 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2143 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2144 } 2145 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2146 break; 2147 case AHCI_ERR_TIMEOUT: 2148 if (!ch->recoverycmd) { 2149 xpt_freeze_simq(ch->sim, 1); 2150 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2151 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2152 } 2153 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2154 break; 2155 default: 2156 ch->fatalerr = 1; 2157 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2158 } 2159 /* Free slot. */ 2160 ch->oslots &= ~(1 << slot->slot); 2161 ch->rslots &= ~(1 << slot->slot); 2162 ch->aslots &= ~(1 << slot->slot); 2163 slot->state = AHCI_SLOT_EMPTY; 2164 slot->ccb = NULL; 2165 /* Update channel stats. */ 2166 ch->numrslots--; 2167 ch->numrslotspd[ccb->ccb_h.target_id]--; 2168 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2169 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2170 ch->numtslots--; 2171 ch->numtslotspd[ccb->ccb_h.target_id]--; 2172 } 2173 /* Cancel timeout state if request completed normally. */ 2174 if (et != AHCI_ERR_TIMEOUT) { 2175 lastto = (ch->toslots == (1 << slot->slot)); 2176 ch->toslots &= ~(1 << slot->slot); 2177 if (lastto) 2178 xpt_release_simq(ch->sim, TRUE); 2179 } 2180 /* If it was first request of reset sequence and there is no error, 2181 * proceed to second request. */ 2182 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2183 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2184 (ccb->ataio.cmd.control & ATA_A_RESET) && 2185 et == AHCI_ERR_NONE) { 2186 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2187 ahci_begin_transaction(dev, ccb); 2188 return; 2189 } 2190 /* If it was our READ LOG command - process it. */ 2191 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2192 ahci_process_read_log(dev, ccb); 2193 /* If it was our REQUEST SENSE command - process it. */ 2194 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2195 ahci_process_request_sense(dev, ccb); 2196 /* If it was NCQ or ATAPI command error, put result on hold. */ 2197 } else if (et == AHCI_ERR_NCQ || 2198 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2199 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2200 ch->hold[slot->slot] = ccb; 2201 ch->numhslots++; 2202 } else 2203 xpt_done(ccb); 2204 /* If we have no other active commands, ... */ 2205 if (ch->rslots == 0) { 2206 /* if there was fatal error - reset port. */ 2207 if (ch->toslots != 0 || ch->fatalerr) { 2208 ahci_reset(dev); 2209 } else { 2210 /* if we have slots in error, we can reinit port. */ 2211 if (ch->eslots != 0) { 2212 ahci_stop(dev); 2213 ahci_clo(dev); 2214 ahci_start(dev, 1); 2215 } 2216 /* if there commands on hold, we can do READ LOG. */ 2217 if (!ch->recoverycmd && ch->numhslots) 2218 ahci_issue_recovery(dev); 2219 } 2220 /* If all the rest of commands are in timeout - give them chance. */ 2221 } else if ((ch->rslots & ~ch->toslots) == 0 && 2222 et != AHCI_ERR_TIMEOUT) 2223 ahci_rearm_timeout(dev); 2224 /* Unfreeze frozen command. */ 2225 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2226 union ccb *fccb = ch->frozen; 2227 ch->frozen = NULL; 2228 ahci_begin_transaction(dev, fccb); 2229 xpt_release_simq(ch->sim, TRUE); 2230 } 2231 /* Start PM timer. */ 2232 if (ch->numrslots == 0 && ch->pm_level > 3 && 2233 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2234 callout_schedule(&ch->pm_timer, 2235 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2236 } 2237 } 2238 2239 static void 2240 ahci_issue_recovery(device_t dev) 2241 { 2242 struct ahci_channel *ch = device_get_softc(dev); 2243 union ccb *ccb; 2244 struct ccb_ataio *ataio; 2245 struct ccb_scsiio *csio; 2246 int i; 2247 2248 /* Find some held command. */ 2249 for (i = 0; i < ch->numslots; i++) { 2250 if (ch->hold[i]) 2251 break; 2252 } 2253 ccb = xpt_alloc_ccb_nowait(); 2254 if (ccb == NULL) { 2255 device_printf(dev, "Unable to allocate recovery command\n"); 2256 completeall: 2257 /* We can't do anything -- complete held commands. */ 2258 for (i = 0; i < ch->numslots; i++) { 2259 if (ch->hold[i] == NULL) 2260 continue; 2261 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2262 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2263 xpt_done(ch->hold[i]); 2264 ch->hold[i] = NULL; 2265 ch->numhslots--; 2266 } 2267 ahci_reset(dev); 2268 return; 2269 } 2270 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2271 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2272 /* READ LOG */ 2273 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2274 ccb->ccb_h.func_code = XPT_ATA_IO; 2275 ccb->ccb_h.flags = CAM_DIR_IN; 2276 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2277 ataio = &ccb->ataio; 2278 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2279 if (ataio->data_ptr == NULL) { 2280 xpt_free_ccb(ccb); 2281 device_printf(dev, 2282 "Unable to allocate memory for READ LOG command\n"); 2283 goto completeall; 2284 } 2285 ataio->dxfer_len = 512; 2286 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2287 ataio->cmd.flags = CAM_ATAIO_48BIT; 2288 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2289 ataio->cmd.sector_count = 1; 2290 ataio->cmd.sector_count_exp = 0; 2291 ataio->cmd.lba_low = 0x10; 2292 ataio->cmd.lba_mid = 0; 2293 ataio->cmd.lba_mid_exp = 0; 2294 } else { 2295 /* REQUEST SENSE */ 2296 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2297 ccb->ccb_h.recovery_slot = i; 2298 ccb->ccb_h.func_code = XPT_SCSI_IO; 2299 ccb->ccb_h.flags = CAM_DIR_IN; 2300 ccb->ccb_h.status = 0; 2301 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2302 csio = &ccb->csio; 2303 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2304 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2305 csio->cdb_len = 6; 2306 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2307 csio->cdb_io.cdb_bytes[0] = 0x03; 2308 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2309 } 2310 /* Freeze SIM while doing recovery. */ 2311 ch->recoverycmd = 1; 2312 xpt_freeze_simq(ch->sim, 1); 2313 ahci_begin_transaction(dev, ccb); 2314 } 2315 2316 static void 2317 ahci_process_read_log(device_t dev, union ccb *ccb) 2318 { 2319 struct ahci_channel *ch = device_get_softc(dev); 2320 uint8_t *data; 2321 struct ata_res *res; 2322 int i; 2323 2324 ch->recoverycmd = 0; 2325 2326 data = ccb->ataio.data_ptr; 2327 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2328 (data[0] & 0x80) == 0) { 2329 for (i = 0; i < ch->numslots; i++) { 2330 if (!ch->hold[i]) 2331 continue; 2332 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2333 continue; 2334 if ((data[0] & 0x1F) == i) { 2335 res = &ch->hold[i]->ataio.res; 2336 res->status = data[2]; 2337 res->error = data[3]; 2338 res->lba_low = data[4]; 2339 res->lba_mid = data[5]; 2340 res->lba_high = data[6]; 2341 res->device = data[7]; 2342 res->lba_low_exp = data[8]; 2343 res->lba_mid_exp = data[9]; 2344 res->lba_high_exp = data[10]; 2345 res->sector_count = data[12]; 2346 res->sector_count_exp = data[13]; 2347 } else { 2348 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2349 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2350 } 2351 xpt_done(ch->hold[i]); 2352 ch->hold[i] = NULL; 2353 ch->numhslots--; 2354 } 2355 } else { 2356 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2357 device_printf(dev, "Error while READ LOG EXT\n"); 2358 else if ((data[0] & 0x80) == 0) { 2359 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2360 } 2361 for (i = 0; i < ch->numslots; i++) { 2362 if (!ch->hold[i]) 2363 continue; 2364 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2365 continue; 2366 xpt_done(ch->hold[i]); 2367 ch->hold[i] = NULL; 2368 ch->numhslots--; 2369 } 2370 } 2371 free(ccb->ataio.data_ptr, M_AHCI); 2372 xpt_free_ccb(ccb); 2373 xpt_release_simq(ch->sim, TRUE); 2374 } 2375 2376 static void 2377 ahci_process_request_sense(device_t dev, union ccb *ccb) 2378 { 2379 struct ahci_channel *ch = device_get_softc(dev); 2380 int i; 2381 2382 ch->recoverycmd = 0; 2383 2384 i = ccb->ccb_h.recovery_slot; 2385 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2386 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2387 } else { 2388 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2389 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2390 } 2391 xpt_done(ch->hold[i]); 2392 ch->hold[i] = NULL; 2393 ch->numhslots--; 2394 xpt_free_ccb(ccb); 2395 xpt_release_simq(ch->sim, TRUE); 2396 } 2397 2398 static void 2399 ahci_start(device_t dev, int fbs) 2400 { 2401 struct ahci_channel *ch = device_get_softc(dev); 2402 u_int32_t cmd; 2403 2404 /* Clear SATA error register */ 2405 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2406 /* Clear any interrupts pending on this channel */ 2407 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2408 /* Configure FIS-based switching if supported. */ 2409 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2410 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2411 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2412 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2413 } 2414 /* Start operations on this channel */ 2415 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2416 cmd &= ~AHCI_P_CMD_PMA; 2417 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2418 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2419 } 2420 2421 static void 2422 ahci_stop(device_t dev) 2423 { 2424 struct ahci_channel *ch = device_get_softc(dev); 2425 u_int32_t cmd; 2426 int timeout; 2427 2428 /* Kill all activity on this channel */ 2429 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2430 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2431 /* Wait for activity stop. */ 2432 timeout = 0; 2433 do { 2434 DELAY(10); 2435 if (timeout++ > 50000) { 2436 device_printf(dev, "stopping AHCI engine failed\n"); 2437 break; 2438 } 2439 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2440 ch->eslots = 0; 2441 } 2442 2443 static void 2444 ahci_clo(device_t dev) 2445 { 2446 struct ahci_channel *ch = device_get_softc(dev); 2447 u_int32_t cmd; 2448 int timeout; 2449 2450 /* Issue Command List Override if supported */ 2451 if (ch->caps & AHCI_CAP_SCLO) { 2452 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2453 cmd |= AHCI_P_CMD_CLO; 2454 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2455 timeout = 0; 2456 do { 2457 DELAY(10); 2458 if (timeout++ > 50000) { 2459 device_printf(dev, "executing CLO failed\n"); 2460 break; 2461 } 2462 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2463 } 2464 } 2465 2466 static void 2467 ahci_stop_fr(device_t dev) 2468 { 2469 struct ahci_channel *ch = device_get_softc(dev); 2470 u_int32_t cmd; 2471 int timeout; 2472 2473 /* Kill all FIS reception on this channel */ 2474 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2475 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2476 /* Wait for FIS reception stop. */ 2477 timeout = 0; 2478 do { 2479 DELAY(10); 2480 if (timeout++ > 50000) { 2481 device_printf(dev, "stopping AHCI FR engine failed\n"); 2482 break; 2483 } 2484 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2485 } 2486 2487 static void 2488 ahci_start_fr(device_t dev) 2489 { 2490 struct ahci_channel *ch = device_get_softc(dev); 2491 u_int32_t cmd; 2492 2493 /* Start FIS reception on this channel */ 2494 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2495 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2496 } 2497 2498 static int 2499 ahci_wait_ready(device_t dev, int t, int t0) 2500 { 2501 struct ahci_channel *ch = device_get_softc(dev); 2502 int timeout = 0; 2503 uint32_t val; 2504 2505 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2506 (ATA_S_BUSY | ATA_S_DRQ)) { 2507 if (timeout > t) { 2508 if (t != 0) { 2509 device_printf(dev, 2510 "AHCI reset: device not ready after %dms " 2511 "(tfd = %08x)\n", 2512 MAX(t, 0) + t0, val); 2513 } 2514 return (EBUSY); 2515 } 2516 DELAY(1000); 2517 timeout++; 2518 } 2519 if (bootverbose) 2520 device_printf(dev, "AHCI reset: device ready after %dms\n", 2521 timeout + t0); 2522 return (0); 2523 } 2524 2525 static void 2526 ahci_reset_to(void *arg) 2527 { 2528 device_t dev = arg; 2529 struct ahci_channel *ch = device_get_softc(dev); 2530 2531 if (ch->resetting == 0) 2532 return; 2533 ch->resetting--; 2534 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2535 (310 - ch->resetting) * 100) == 0) { 2536 ch->resetting = 0; 2537 ahci_start(dev, 1); 2538 xpt_release_simq(ch->sim, TRUE); 2539 return; 2540 } 2541 if (ch->resetting == 0) { 2542 ahci_clo(dev); 2543 ahci_start(dev, 1); 2544 xpt_release_simq(ch->sim, TRUE); 2545 return; 2546 } 2547 callout_schedule(&ch->reset_timer, hz / 10); 2548 } 2549 2550 static void 2551 ahci_reset(device_t dev) 2552 { 2553 struct ahci_channel *ch = device_get_softc(dev); 2554 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2555 int i; 2556 2557 xpt_freeze_simq(ch->sim, 1); 2558 if (bootverbose) 2559 device_printf(dev, "AHCI reset...\n"); 2560 /* Forget about previous reset. */ 2561 if (ch->resetting) { 2562 ch->resetting = 0; 2563 callout_stop(&ch->reset_timer); 2564 xpt_release_simq(ch->sim, TRUE); 2565 } 2566 /* Requeue freezed command. */ 2567 if (ch->frozen) { 2568 union ccb *fccb = ch->frozen; 2569 ch->frozen = NULL; 2570 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2571 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2572 xpt_freeze_devq(fccb->ccb_h.path, 1); 2573 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2574 } 2575 xpt_done(fccb); 2576 } 2577 /* Kill the engine and requeue all running commands. */ 2578 ahci_stop(dev); 2579 for (i = 0; i < ch->numslots; i++) { 2580 /* Do we have a running request on slot? */ 2581 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2582 continue; 2583 /* XXX; Commands in loading state. */ 2584 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2585 } 2586 for (i = 0; i < ch->numslots; i++) { 2587 if (!ch->hold[i]) 2588 continue; 2589 xpt_done(ch->hold[i]); 2590 ch->hold[i] = NULL; 2591 ch->numhslots--; 2592 } 2593 if (ch->toslots != 0) 2594 xpt_release_simq(ch->sim, TRUE); 2595 ch->eslots = 0; 2596 ch->toslots = 0; 2597 ch->wrongccs = 0; 2598 ch->fatalerr = 0; 2599 /* Tell the XPT about the event */ 2600 xpt_async(AC_BUS_RESET, ch->path, NULL); 2601 /* Disable port interrupts */ 2602 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2603 /* Reset and reconnect PHY, */ 2604 if (!ahci_sata_phy_reset(dev)) { 2605 if (bootverbose) 2606 device_printf(dev, 2607 "AHCI reset: device not found\n"); 2608 ch->devices = 0; 2609 /* Enable wanted port interrupts */ 2610 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2611 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2612 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2613 xpt_release_simq(ch->sim, TRUE); 2614 return; 2615 } 2616 if (bootverbose) 2617 device_printf(dev, "AHCI reset: device found\n"); 2618 /* Wait for clearing busy status. */ 2619 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2620 if (dumping) 2621 ahci_clo(dev); 2622 else 2623 ch->resetting = 310; 2624 } 2625 ch->devices = 1; 2626 /* Enable wanted port interrupts */ 2627 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2628 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2629 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2630 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2631 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2632 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2633 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2634 if (ch->resetting) 2635 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2636 else { 2637 ahci_start(dev, 1); 2638 xpt_release_simq(ch->sim, TRUE); 2639 } 2640 } 2641 2642 static int 2643 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2644 { 2645 struct ahci_channel *ch = device_get_softc(dev); 2646 u_int8_t *fis = &ctp->cfis[0]; 2647 2648 bzero(ctp->cfis, 64); 2649 fis[0] = 0x27; /* host to device */ 2650 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2651 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2652 fis[1] |= 0x80; 2653 fis[2] = ATA_PACKET_CMD; 2654 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2655 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2656 fis[3] = ATA_F_DMA; 2657 else { 2658 fis[5] = ccb->csio.dxfer_len; 2659 fis[6] = ccb->csio.dxfer_len >> 8; 2660 } 2661 fis[7] = ATA_D_LBA; 2662 fis[15] = ATA_A_4BIT; 2663 bzero(ctp->acmd, 32); 2664 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2665 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2666 ctp->acmd, ccb->csio.cdb_len); 2667 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2668 fis[1] |= 0x80; 2669 fis[2] = ccb->ataio.cmd.command; 2670 fis[3] = ccb->ataio.cmd.features; 2671 fis[4] = ccb->ataio.cmd.lba_low; 2672 fis[5] = ccb->ataio.cmd.lba_mid; 2673 fis[6] = ccb->ataio.cmd.lba_high; 2674 fis[7] = ccb->ataio.cmd.device; 2675 fis[8] = ccb->ataio.cmd.lba_low_exp; 2676 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2677 fis[10] = ccb->ataio.cmd.lba_high_exp; 2678 fis[11] = ccb->ataio.cmd.features_exp; 2679 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2680 fis[12] = tag << 3; 2681 fis[13] = 0; 2682 } else { 2683 fis[12] = ccb->ataio.cmd.sector_count; 2684 fis[13] = ccb->ataio.cmd.sector_count_exp; 2685 } 2686 fis[15] = ATA_A_4BIT; 2687 } else { 2688 fis[15] = ccb->ataio.cmd.control; 2689 } 2690 return (20); 2691 } 2692 2693 static int 2694 ahci_sata_connect(struct ahci_channel *ch) 2695 { 2696 u_int32_t status; 2697 int timeout, found = 0; 2698 2699 /* Wait up to 100ms for "connect well" */ 2700 for (timeout = 0; timeout < 1000 ; timeout++) { 2701 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2702 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2703 found = 1; 2704 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2705 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2706 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2707 break; 2708 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2709 if (bootverbose) { 2710 device_printf(ch->dev, "SATA offline status=%08x\n", 2711 status); 2712 } 2713 return (0); 2714 } 2715 if (found == 0 && timeout >= 100) 2716 break; 2717 DELAY(100); 2718 } 2719 if (timeout >= 1000 || !found) { 2720 if (bootverbose) { 2721 device_printf(ch->dev, 2722 "SATA connect timeout time=%dus status=%08x\n", 2723 timeout * 100, status); 2724 } 2725 return (0); 2726 } 2727 if (bootverbose) { 2728 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2729 timeout * 100, status); 2730 } 2731 /* Clear SATA error register */ 2732 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2733 return (1); 2734 } 2735 2736 static int 2737 ahci_sata_phy_reset(device_t dev) 2738 { 2739 struct ahci_channel *ch = device_get_softc(dev); 2740 int sata_rev; 2741 uint32_t val; 2742 2743 if (ch->listening) { 2744 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2745 val |= AHCI_P_CMD_SUD; 2746 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2747 ch->listening = 0; 2748 } 2749 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2750 if (sata_rev == 1) 2751 val = ATA_SC_SPD_SPEED_GEN1; 2752 else if (sata_rev == 2) 2753 val = ATA_SC_SPD_SPEED_GEN2; 2754 else if (sata_rev == 3) 2755 val = ATA_SC_SPD_SPEED_GEN3; 2756 else 2757 val = 0; 2758 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2759 ATA_SC_DET_RESET | val | 2760 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2761 DELAY(1000); 2762 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2763 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2764 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2765 if (!ahci_sata_connect(ch)) { 2766 if (ch->caps & AHCI_CAP_SSS) { 2767 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2768 val &= ~AHCI_P_CMD_SUD; 2769 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2770 ch->listening = 1; 2771 } else if (ch->pm_level > 0) 2772 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2773 return (0); 2774 } 2775 return (1); 2776 } 2777 2778 static int 2779 ahci_check_ids(device_t dev, union ccb *ccb) 2780 { 2781 struct ahci_channel *ch = device_get_softc(dev); 2782 2783 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2784 ccb->ccb_h.status = CAM_TID_INVALID; 2785 xpt_done(ccb); 2786 return (-1); 2787 } 2788 if (ccb->ccb_h.target_lun != 0) { 2789 ccb->ccb_h.status = CAM_LUN_INVALID; 2790 xpt_done(ccb); 2791 return (-1); 2792 } 2793 return (0); 2794 } 2795 2796 static void 2797 ahciaction(struct cam_sim *sim, union ccb *ccb) 2798 { 2799 device_t dev, parent; 2800 struct ahci_channel *ch; 2801 2802 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2803 ccb->ccb_h.func_code)); 2804 2805 ch = (struct ahci_channel *)cam_sim_softc(sim); 2806 dev = ch->dev; 2807 switch (ccb->ccb_h.func_code) { 2808 /* Common cases first */ 2809 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2810 case XPT_SCSI_IO: 2811 if (ahci_check_ids(dev, ccb)) 2812 return; 2813 if (ch->devices == 0 || 2814 (ch->pm_present == 0 && 2815 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2816 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2817 break; 2818 } 2819 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2820 /* Check for command collision. */ 2821 if (ahci_check_collision(dev, ccb)) { 2822 /* Freeze command. */ 2823 ch->frozen = ccb; 2824 /* We have only one frozen slot, so freeze simq also. */ 2825 xpt_freeze_simq(ch->sim, 1); 2826 return; 2827 } 2828 ahci_begin_transaction(dev, ccb); 2829 return; 2830 case XPT_EN_LUN: /* Enable LUN as a target */ 2831 case XPT_TARGET_IO: /* Execute target I/O request */ 2832 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2833 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2834 case XPT_ABORT: /* Abort the specified CCB */ 2835 /* XXX Implement */ 2836 ccb->ccb_h.status = CAM_REQ_INVALID; 2837 break; 2838 case XPT_SET_TRAN_SETTINGS: 2839 { 2840 struct ccb_trans_settings *cts = &ccb->cts; 2841 struct ahci_device *d; 2842 2843 if (ahci_check_ids(dev, ccb)) 2844 return; 2845 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2846 d = &ch->curr[ccb->ccb_h.target_id]; 2847 else 2848 d = &ch->user[ccb->ccb_h.target_id]; 2849 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2850 d->revision = cts->xport_specific.sata.revision; 2851 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2852 d->mode = cts->xport_specific.sata.mode; 2853 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2854 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2855 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2856 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2857 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2858 ch->pm_present = cts->xport_specific.sata.pm_present; 2859 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2860 d->atapi = cts->xport_specific.sata.atapi; 2861 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2862 d->caps = cts->xport_specific.sata.caps; 2863 ccb->ccb_h.status = CAM_REQ_CMP; 2864 break; 2865 } 2866 case XPT_GET_TRAN_SETTINGS: 2867 /* Get default/user set transfer settings for the target */ 2868 { 2869 struct ccb_trans_settings *cts = &ccb->cts; 2870 struct ahci_device *d; 2871 uint32_t status; 2872 2873 if (ahci_check_ids(dev, ccb)) 2874 return; 2875 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2876 d = &ch->curr[ccb->ccb_h.target_id]; 2877 else 2878 d = &ch->user[ccb->ccb_h.target_id]; 2879 cts->protocol = PROTO_ATA; 2880 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2881 cts->transport = XPORT_SATA; 2882 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2883 cts->proto_specific.valid = 0; 2884 cts->xport_specific.sata.valid = 0; 2885 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2886 (ccb->ccb_h.target_id == 15 || 2887 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2888 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2889 if (status & 0x0f0) { 2890 cts->xport_specific.sata.revision = 2891 (status & 0x0f0) >> 4; 2892 cts->xport_specific.sata.valid |= 2893 CTS_SATA_VALID_REVISION; 2894 } 2895 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2896 if (ch->pm_level) { 2897 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2898 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2899 if (ch->caps2 & AHCI_CAP2_APST) 2900 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2901 } 2902 if ((ch->caps & AHCI_CAP_SNCQ) && 2903 (ch->quirks & AHCI_Q_NOAA) == 0) 2904 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2905 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2906 cts->xport_specific.sata.caps &= 2907 ch->user[ccb->ccb_h.target_id].caps; 2908 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2909 } else { 2910 cts->xport_specific.sata.revision = d->revision; 2911 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2912 cts->xport_specific.sata.caps = d->caps; 2913 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2914 } 2915 cts->xport_specific.sata.mode = d->mode; 2916 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2917 cts->xport_specific.sata.bytecount = d->bytecount; 2918 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2919 cts->xport_specific.sata.pm_present = ch->pm_present; 2920 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2921 cts->xport_specific.sata.tags = d->tags; 2922 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2923 cts->xport_specific.sata.atapi = d->atapi; 2924 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2925 ccb->ccb_h.status = CAM_REQ_CMP; 2926 break; 2927 } 2928 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2929 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2930 ahci_reset(dev); 2931 ccb->ccb_h.status = CAM_REQ_CMP; 2932 break; 2933 case XPT_TERM_IO: /* Terminate the I/O process */ 2934 /* XXX Implement */ 2935 ccb->ccb_h.status = CAM_REQ_INVALID; 2936 break; 2937 case XPT_PATH_INQ: /* Path routing inquiry */ 2938 { 2939 struct ccb_pathinq *cpi = &ccb->cpi; 2940 2941 parent = device_get_parent(dev); 2942 cpi->version_num = 1; /* XXX??? */ 2943 cpi->hba_inquiry = PI_SDTR_ABLE; 2944 if (ch->caps & AHCI_CAP_SNCQ) 2945 cpi->hba_inquiry |= PI_TAG_ABLE; 2946 if (ch->caps & AHCI_CAP_SPM) 2947 cpi->hba_inquiry |= PI_SATAPM; 2948 cpi->target_sprt = 0; 2949 cpi->hba_misc = PIM_SEQSCAN; 2950 cpi->hba_eng_cnt = 0; 2951 if (ch->caps & AHCI_CAP_SPM) 2952 cpi->max_target = 15; 2953 else 2954 cpi->max_target = 0; 2955 cpi->max_lun = 0; 2956 cpi->initiator_id = 0; 2957 cpi->bus_id = cam_sim_bus(sim); 2958 cpi->base_transfer_speed = 150000; 2959 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2960 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2961 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2962 cpi->unit_number = cam_sim_unit(sim); 2963 cpi->transport = XPORT_SATA; 2964 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2965 cpi->protocol = PROTO_ATA; 2966 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2967 cpi->maxio = MAXPHYS; 2968 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2969 if (pci_get_devid(parent) == 0x43801002) 2970 cpi->maxio = min(cpi->maxio, 128 * 512); 2971 cpi->hba_vendor = pci_get_vendor(parent); 2972 cpi->hba_device = pci_get_device(parent); 2973 cpi->hba_subvendor = pci_get_subvendor(parent); 2974 cpi->hba_subdevice = pci_get_subdevice(parent); 2975 cpi->ccb_h.status = CAM_REQ_CMP; 2976 break; 2977 } 2978 default: 2979 ccb->ccb_h.status = CAM_REQ_INVALID; 2980 break; 2981 } 2982 xpt_done(ccb); 2983 } 2984 2985 static void 2986 ahcipoll(struct cam_sim *sim) 2987 { 2988 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2989 2990 ahci_ch_intr(ch->dev); 2991 if (ch->resetting != 0 && 2992 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2993 ch->resetpolldiv = 1000; 2994 ahci_reset_to(ch->dev); 2995 } 2996 }
Cache object: 00623ff79d44d629847dc3cc780d8d95
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