Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ahci/ahci.c
Version:
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1 /*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/led/led.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include "ahci.h" 52 53 #include <cam/cam.h> 54 #include <cam/cam_ccb.h> 55 #include <cam/cam_sim.h> 56 #include <cam/cam_xpt_sim.h> 57 #include <cam/cam_debug.h> 58 59 /* local prototypes */ 60 static int ahci_setup_interrupt(device_t dev); 61 static void ahci_intr(void *data); 62 static void ahci_intr_one(void *data); 63 static int ahci_suspend(device_t dev); 64 static int ahci_resume(device_t dev); 65 static int ahci_ch_init(device_t dev); 66 static int ahci_ch_deinit(device_t dev); 67 static int ahci_ch_suspend(device_t dev); 68 static int ahci_ch_resume(device_t dev); 69 static void ahci_ch_pm(void *arg); 70 static void ahci_ch_intr_locked(void *data); 71 static void ahci_ch_intr(void *data); 72 static void ahci_ch_led(void *priv, int onoff); 73 static int ahci_ctlr_reset(device_t dev); 74 static int ahci_ctlr_setup(device_t dev); 75 static void ahci_begin_transaction(device_t dev, union ccb *ccb); 76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 77 static void ahci_execute_transaction(struct ahci_slot *slot); 78 static void ahci_timeout(struct ahci_slot *slot); 79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 81 static void ahci_dmainit(device_t dev); 82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 83 static void ahci_dmafini(device_t dev); 84 static void ahci_slotsalloc(device_t dev); 85 static void ahci_slotsfree(device_t dev); 86 static void ahci_reset(device_t dev); 87 static void ahci_start(device_t dev, int fbs); 88 static void ahci_stop(device_t dev); 89 static void ahci_clo(device_t dev); 90 static void ahci_start_fr(device_t dev); 91 static void ahci_stop_fr(device_t dev); 92 93 static int ahci_sata_connect(struct ahci_channel *ch); 94 static int ahci_sata_phy_reset(device_t dev); 95 static int ahci_wait_ready(device_t dev, int t, int t0); 96 97 static void ahci_issue_recovery(device_t dev); 98 static void ahci_process_read_log(device_t dev, union ccb *ccb); 99 static void ahci_process_request_sense(device_t dev, union ccb *ccb); 100 101 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 102 static void ahcipoll(struct cam_sim *sim); 103 104 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 105 106 static const struct { 107 uint32_t id; 108 uint8_t rev; 109 const char *name; 110 int quirks; 111 #define AHCI_Q_NOFORCE 1 112 #define AHCI_Q_NOPMP 2 113 #define AHCI_Q_NONCQ 4 114 #define AHCI_Q_1CH 8 115 #define AHCI_Q_2CH 16 116 #define AHCI_Q_4CH 32 117 #define AHCI_Q_EDGEIS 64 118 #define AHCI_Q_SATA2 128 119 #define AHCI_Q_NOBSYRES 256 120 #define AHCI_Q_NOAA 512 121 #define AHCI_Q_NOCOUNT 1024 122 #define AHCI_Q_ALTSIG 2048 123 #define AHCI_Q_NOMSI 4096 124 125 #define AHCI_Q_BIT_STRING \ 126 "\020" \ 127 "\001NOFORCE" \ 128 "\002NOPMP" \ 129 "\003NONCQ" \ 130 "\0041CH" \ 131 "\0052CH" \ 132 "\0064CH" \ 133 "\007EDGEIS" \ 134 "\010SATA2" \ 135 "\011NOBSYRES" \ 136 "\012NOAA" \ 137 "\013NOCOUNT" \ 138 "\014ALTSIG" \ 139 "\015NOMSI" 140 } ahci_ids[] = { 141 {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI}, 142 {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 143 {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 144 {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 145 {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 146 {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 147 {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0}, 148 {0x78001022, 0x00, "AMD Hudson-2", 0}, 149 {0x78011022, 0x00, "AMD Hudson-2", 0}, 150 {0x78021022, 0x00, "AMD Hudson-2", 0}, 151 {0x78031022, 0x00, "AMD Hudson-2", 0}, 152 {0x78041022, 0x00, "AMD Hudson-2", 0}, 153 {0x06111b21, 0x00, "ASMedia ASM2106", 0}, 154 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 155 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 156 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 157 {0x26818086, 0x00, "Intel ESB2", 0}, 158 {0x26828086, 0x00, "Intel ESB2", 0}, 159 {0x26838086, 0x00, "Intel ESB2", 0}, 160 {0x27c18086, 0x00, "Intel ICH7", 0}, 161 {0x27c38086, 0x00, "Intel ICH7", 0}, 162 {0x27c58086, 0x00, "Intel ICH7M", 0}, 163 {0x27c68086, 0x00, "Intel ICH7M", 0}, 164 {0x28218086, 0x00, "Intel ICH8", 0}, 165 {0x28228086, 0x00, "Intel ICH8", 0}, 166 {0x28248086, 0x00, "Intel ICH8", 0}, 167 {0x28298086, 0x00, "Intel ICH8M", 0}, 168 {0x282a8086, 0x00, "Intel ICH8M", 0}, 169 {0x29228086, 0x00, "Intel ICH9", 0}, 170 {0x29238086, 0x00, "Intel ICH9", 0}, 171 {0x29248086, 0x00, "Intel ICH9", 0}, 172 {0x29258086, 0x00, "Intel ICH9", 0}, 173 {0x29278086, 0x00, "Intel ICH9", 0}, 174 {0x29298086, 0x00, "Intel ICH9M", 0}, 175 {0x292a8086, 0x00, "Intel ICH9M", 0}, 176 {0x292b8086, 0x00, "Intel ICH9M", 0}, 177 {0x292c8086, 0x00, "Intel ICH9M", 0}, 178 {0x292f8086, 0x00, "Intel ICH9M", 0}, 179 {0x294d8086, 0x00, "Intel ICH9", 0}, 180 {0x294e8086, 0x00, "Intel ICH9M", 0}, 181 {0x3a058086, 0x00, "Intel ICH10", 0}, 182 {0x3a228086, 0x00, "Intel ICH10", 0}, 183 {0x3a258086, 0x00, "Intel ICH10", 0}, 184 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 185 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 186 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 187 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 188 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 189 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 190 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 191 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 192 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 193 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 194 {0x1d028086, 0x00, "Intel Patsburg", 0}, 195 {0x1d048086, 0x00, "Intel Patsburg", 0}, 196 {0x1d068086, 0x00, "Intel Patsburg", 0}, 197 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 198 {0x1e028086, 0x00, "Intel Panther Point", 0}, 199 {0x1e038086, 0x00, "Intel Panther Point", 0}, 200 {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0}, 201 {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0}, 202 {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0}, 203 {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0}, 204 {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0}, 205 {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0}, 206 {0x1f228086, 0x00, "Intel Avoton", 0}, 207 {0x1f238086, 0x00, "Intel Avoton", 0}, 208 {0x1f248086, 0x00, "Intel Avoton (RAID)", 0}, 209 {0x1f258086, 0x00, "Intel Avoton (RAID)", 0}, 210 {0x1f268086, 0x00, "Intel Avoton (RAID)", 0}, 211 {0x1f278086, 0x00, "Intel Avoton (RAID)", 0}, 212 {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0}, 213 {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0}, 214 {0x1f328086, 0x00, "Intel Avoton", 0}, 215 {0x1f338086, 0x00, "Intel Avoton", 0}, 216 {0x1f348086, 0x00, "Intel Avoton (RAID)", 0}, 217 {0x1f358086, 0x00, "Intel Avoton (RAID)", 0}, 218 {0x1f368086, 0x00, "Intel Avoton (RAID)", 0}, 219 {0x1f378086, 0x00, "Intel Avoton (RAID)", 0}, 220 {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0}, 221 {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0}, 222 {0x23a38086, 0x00, "Intel Coleto Creek", 0}, 223 {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0}, 224 {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0}, 225 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 226 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 227 {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0}, 228 {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0}, 229 {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0}, 230 {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0}, 231 {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0}, 232 {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0}, 233 {0x8c828086, 0x00, "Intel Wildcat Point", 0}, 234 {0x8c838086, 0x00, "Intel Wildcat Point", 0}, 235 {0x8c848086, 0x00, "Intel Wildcat Point (RAID)", 0}, 236 {0x8c858086, 0x00, "Intel Wildcat Point (RAID)", 0}, 237 {0x8c868086, 0x00, "Intel Wildcat Point (RAID)", 0}, 238 {0x8c878086, 0x00, "Intel Wildcat Point (RAID)", 0}, 239 {0x8c8e8086, 0x00, "Intel Wildcat Point (RAID)", 0}, 240 {0x8c8f8086, 0x00, "Intel Wildcat Point (RAID)", 0}, 241 {0x8d028086, 0x00, "Intel Wellsburg", 0}, 242 {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0}, 243 {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0}, 244 {0x8d628086, 0x00, "Intel Wellsburg", 0}, 245 {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0}, 246 {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0}, 247 {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0}, 248 {0x9c028086, 0x00, "Intel Lynx Point-LP", 0}, 249 {0x9c038086, 0x00, "Intel Lynx Point-LP", 0}, 250 {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 251 {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 252 {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 253 {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 254 {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 255 {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 256 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 257 {0x2360197b, 0x00, "JMicron JMB360", 0}, 258 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE | AHCI_Q_1CH}, 259 {0x2362197b, 0x00, "JMicron JMB362", 0}, 260 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 261 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 262 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 263 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 264 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 265 AHCI_Q_EDGEIS}, 266 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 267 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 268 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 269 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 270 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 271 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 272 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS}, 273 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG}, 274 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2}, 275 {0x91251b4b, 0x00, "Marvell 88SE9125", 0}, 276 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG}, 277 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG}, 278 {0x91721b4b, 0x00, "Marvell 88SE9172", 0}, 279 {0x91821b4b, 0x00, "Marvell 88SE9182", 0}, 280 {0x91831b4b, 0x00, "Marvell 88SS9183", 0}, 281 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0}, 282 {0x92151b4b, 0x00, "Marvell 88SE9215", 0}, 283 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG}, 284 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG}, 285 {0x92351b4b, 0x00, "Marvell 88SE9235", 0}, 286 {0x06201103, 0x00, "HighPoint RocketRAID 620", 0}, 287 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0}, 288 {0x06221103, 0x00, "HighPoint RocketRAID 622", 0}, 289 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0}, 290 {0x06401103, 0x00, "HighPoint RocketRAID 640", 0}, 291 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0}, 292 {0x06441103, 0x00, "HighPoint RocketRAID 644", 0}, 293 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0}, 294 {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0}, 295 {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0}, 296 {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0}, 297 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 298 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 299 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 300 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 301 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 302 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 303 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 304 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 305 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 306 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 307 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 308 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 309 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 310 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 311 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 312 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 313 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 314 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 315 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 316 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 317 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 318 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 319 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 320 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 321 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 322 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 323 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 324 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 325 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 326 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 327 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 328 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 329 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 330 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 331 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 332 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 333 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 334 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 335 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 336 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 337 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 338 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 339 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 340 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 341 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 342 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 343 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 344 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 345 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 346 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 347 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 348 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 349 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 350 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 351 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 352 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 353 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 354 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 355 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 356 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 357 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 358 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 359 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 360 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 361 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 362 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 363 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 364 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 365 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 366 {0x3781105a, 0x00, "Promise TX8660", 0}, 367 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 368 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 369 {0x11841039, 0x00, "SiS 966", 0}, 370 {0x11851039, 0x00, "SiS 968", 0}, 371 {0x01861039, 0x00, "SiS 968", 0}, 372 {0x00000000, 0x00, NULL, 0} 373 }; 374 375 #define recovery_type spriv_field0 376 #define RECOVERY_NONE 0 377 #define RECOVERY_READ_LOG 1 378 #define RECOVERY_REQUEST_SENSE 2 379 #define recovery_slot spriv_field1 380 381 static int force_ahci = 1; 382 TUNABLE_INT("hw.ahci.force", &force_ahci); 383 384 static int 385 ahci_probe(device_t dev) 386 { 387 char buf[64]; 388 int i, valid = 0; 389 uint32_t devid = pci_get_devid(dev); 390 uint8_t revid = pci_get_revid(dev); 391 392 /* Is this a possible AHCI candidate? */ 393 if (pci_get_class(dev) == PCIC_STORAGE && 394 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 395 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 396 valid = 1; 397 /* Is this a known AHCI chip? */ 398 for (i = 0; ahci_ids[i].id != 0; i++) { 399 if (ahci_ids[i].id == devid && 400 ahci_ids[i].rev <= revid && 401 (valid || (force_ahci == 1 && 402 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 403 /* Do not attach JMicrons with single PCI function. */ 404 if (pci_get_vendor(dev) == 0x197b && 405 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 406 return (ENXIO); 407 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 408 ahci_ids[i].name); 409 device_set_desc_copy(dev, buf); 410 return (BUS_PROBE_VENDOR); 411 } 412 } 413 if (!valid) 414 return (ENXIO); 415 device_set_desc_copy(dev, "AHCI SATA controller"); 416 return (BUS_PROBE_VENDOR); 417 } 418 419 static int 420 ahci_ata_probe(device_t dev) 421 { 422 char buf[64]; 423 int i; 424 uint32_t devid = pci_get_devid(dev); 425 uint8_t revid = pci_get_revid(dev); 426 427 if ((intptr_t)device_get_ivars(dev) >= 0) 428 return (ENXIO); 429 /* Is this a known AHCI chip? */ 430 for (i = 0; ahci_ids[i].id != 0; i++) { 431 if (ahci_ids[i].id == devid && 432 ahci_ids[i].rev <= revid) { 433 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 434 ahci_ids[i].name); 435 device_set_desc_copy(dev, buf); 436 return (BUS_PROBE_VENDOR); 437 } 438 } 439 device_set_desc_copy(dev, "AHCI SATA controller"); 440 return (BUS_PROBE_VENDOR); 441 } 442 443 static int 444 ahci_attach(device_t dev) 445 { 446 struct ahci_controller *ctlr = device_get_softc(dev); 447 device_t child; 448 int error, unit, speed, i; 449 uint32_t devid = pci_get_devid(dev); 450 uint8_t revid = pci_get_revid(dev); 451 u_int32_t version; 452 453 ctlr->dev = dev; 454 i = 0; 455 while (ahci_ids[i].id != 0 && 456 (ahci_ids[i].id != devid || 457 ahci_ids[i].rev > revid)) 458 i++; 459 ctlr->quirks = ahci_ids[i].quirks; 460 resource_int_value(device_get_name(dev), 461 device_get_unit(dev), "ccc", &ctlr->ccc); 462 /* if we have a memory BAR(5) we are likely on an AHCI part */ 463 ctlr->r_rid = PCIR_BAR(5); 464 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 465 &ctlr->r_rid, RF_ACTIVE))) 466 return ENXIO; 467 /* Setup our own memory management for channels. */ 468 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 469 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 470 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 471 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 472 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 473 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 474 return (error); 475 } 476 if ((error = rman_manage_region(&ctlr->sc_iomem, 477 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 478 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 479 rman_fini(&ctlr->sc_iomem); 480 return (error); 481 } 482 pci_enable_busmaster(dev); 483 /* Reset controller */ 484 if ((error = ahci_ctlr_reset(dev)) != 0) { 485 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 486 rman_fini(&ctlr->sc_iomem); 487 return (error); 488 }; 489 /* Get the HW capabilities */ 490 version = ATA_INL(ctlr->r_mem, AHCI_VS); 491 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 492 if (version >= 0x00010200) 493 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 494 if (ctlr->caps & AHCI_CAP_EMS) 495 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 496 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 497 498 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 499 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 500 (ctlr->caps & AHCI_CAP_SPM) == 0) 501 ctlr->quirks |= AHCI_Q_NOBSYRES; 502 503 if (ctlr->quirks & AHCI_Q_1CH) { 504 ctlr->caps &= ~AHCI_CAP_NPMASK; 505 ctlr->ichannels &= 0x01; 506 } 507 if (ctlr->quirks & AHCI_Q_2CH) { 508 ctlr->caps &= ~AHCI_CAP_NPMASK; 509 ctlr->caps |= 1; 510 ctlr->ichannels &= 0x03; 511 } 512 if (ctlr->quirks & AHCI_Q_4CH) { 513 ctlr->caps &= ~AHCI_CAP_NPMASK; 514 ctlr->caps |= 3; 515 ctlr->ichannels &= 0x0f; 516 } 517 ctlr->channels = MAX(flsl(ctlr->ichannels), 518 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 519 if (ctlr->quirks & AHCI_Q_NOPMP) 520 ctlr->caps &= ~AHCI_CAP_SPM; 521 if (ctlr->quirks & AHCI_Q_NONCQ) 522 ctlr->caps &= ~AHCI_CAP_SNCQ; 523 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 524 ctlr->ccc = 0; 525 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF); 526 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 527 528 /* Create controller-wide DMA tag. */ 529 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 530 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 531 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 532 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 533 0, NULL, NULL, &ctlr->dma_tag)) { 534 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 535 ctlr->r_mem); 536 rman_fini(&ctlr->sc_iomem); 537 return ENXIO; 538 } 539 540 ahci_ctlr_setup(dev); 541 /* Setup interrupts. */ 542 if (ahci_setup_interrupt(dev)) { 543 bus_dma_tag_destroy(ctlr->dma_tag); 544 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 545 rman_fini(&ctlr->sc_iomem); 546 return ENXIO; 547 } 548 /* Announce HW capabilities. */ 549 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 550 device_printf(dev, 551 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 552 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 553 ((version >> 4) & 0xf0) + (version & 0x0f), 554 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 555 ((speed == 1) ? "1.5":((speed == 2) ? "3": 556 ((speed == 3) ? "6":"?"))), 557 (ctlr->caps & AHCI_CAP_SPM) ? 558 "supported" : "not supported", 559 (ctlr->caps & AHCI_CAP_FBSS) ? 560 " with FBS" : ""); 561 if (ctlr->quirks != 0) { 562 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 563 AHCI_Q_BIT_STRING); 564 } 565 if (bootverbose) { 566 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 567 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 568 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 569 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 570 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 571 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 572 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 573 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 574 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 575 ((speed == 1) ? "1.5":((speed == 2) ? "3": 576 ((speed == 3) ? "6":"?")))); 577 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 578 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 579 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 580 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 581 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 582 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 583 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 584 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 585 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 586 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 587 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 588 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 589 } 590 if (bootverbose && version >= 0x00010200) { 591 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 592 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 593 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 594 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 595 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 596 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 597 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 598 } 599 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 600 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 601 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 602 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 603 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 604 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 605 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 606 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 607 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 608 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 609 } 610 /* Attach all channels on this controller */ 611 for (unit = 0; unit < ctlr->channels; unit++) { 612 child = device_add_child(dev, "ahcich", -1); 613 if (child == NULL) { 614 device_printf(dev, "failed to add channel device\n"); 615 continue; 616 } 617 device_set_ivars(child, (void *)(intptr_t)unit); 618 if ((ctlr->ichannels & (1 << unit)) == 0) 619 device_disable(child); 620 } 621 bus_generic_attach(dev); 622 return 0; 623 } 624 625 static int 626 ahci_detach(device_t dev) 627 { 628 struct ahci_controller *ctlr = device_get_softc(dev); 629 int i; 630 631 /* Detach & delete all children */ 632 device_delete_children(dev); 633 634 /* Free interrupts. */ 635 for (i = 0; i < ctlr->numirqs; i++) { 636 if (ctlr->irqs[i].r_irq) { 637 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 638 ctlr->irqs[i].handle); 639 bus_release_resource(dev, SYS_RES_IRQ, 640 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 641 } 642 } 643 pci_release_msi(dev); 644 bus_dma_tag_destroy(ctlr->dma_tag); 645 /* Free memory. */ 646 rman_fini(&ctlr->sc_iomem); 647 if (ctlr->r_mem) 648 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 649 mtx_destroy(&ctlr->em_mtx); 650 return (0); 651 } 652 653 static int 654 ahci_ctlr_reset(device_t dev) 655 { 656 struct ahci_controller *ctlr = device_get_softc(dev); 657 int timeout; 658 659 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 660 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 661 pci_write_config(dev, 0x92, 0x01, 1); 662 /* Enable AHCI mode */ 663 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 664 /* Reset AHCI controller */ 665 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 666 for (timeout = 1000; timeout > 0; timeout--) { 667 DELAY(1000); 668 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 669 break; 670 } 671 if (timeout == 0) { 672 device_printf(dev, "AHCI controller reset failure\n"); 673 return ENXIO; 674 } 675 /* Reenable AHCI mode */ 676 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 677 return (0); 678 } 679 680 static int 681 ahci_ctlr_setup(device_t dev) 682 { 683 struct ahci_controller *ctlr = device_get_softc(dev); 684 /* Clear interrupts */ 685 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 686 /* Configure CCC */ 687 if (ctlr->ccc) { 688 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 689 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 690 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 691 (4 << AHCI_CCCC_CC_SHIFT) | 692 AHCI_CCCC_EN); 693 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 694 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 695 if (bootverbose) { 696 device_printf(dev, 697 "CCC with %dms/4cmd enabled on vector %d\n", 698 ctlr->ccc, ctlr->cccv); 699 } 700 } 701 /* Enable AHCI interrupts */ 702 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 703 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 704 return (0); 705 } 706 707 static int 708 ahci_suspend(device_t dev) 709 { 710 struct ahci_controller *ctlr = device_get_softc(dev); 711 712 bus_generic_suspend(dev); 713 /* Disable interupts, so the state change(s) doesn't trigger */ 714 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 715 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 716 return 0; 717 } 718 719 static int 720 ahci_resume(device_t dev) 721 { 722 int res; 723 724 if ((res = ahci_ctlr_reset(dev)) != 0) 725 return (res); 726 ahci_ctlr_setup(dev); 727 return (bus_generic_resume(dev)); 728 } 729 730 static int 731 ahci_setup_interrupt(device_t dev) 732 { 733 struct ahci_controller *ctlr = device_get_softc(dev); 734 int i, msi = 1; 735 736 /* Process hints. */ 737 if (ctlr->quirks & AHCI_Q_NOMSI) 738 msi = 0; 739 resource_int_value(device_get_name(dev), 740 device_get_unit(dev), "msi", &msi); 741 if (msi < 0) 742 msi = 0; 743 else if (msi == 1) 744 msi = min(1, pci_msi_count(dev)); 745 else if (msi > 1) 746 msi = pci_msi_count(dev); 747 /* Allocate MSI if needed/present. */ 748 if (msi && pci_alloc_msi(dev, &msi) == 0) { 749 ctlr->numirqs = msi; 750 } else { 751 msi = 0; 752 ctlr->numirqs = 1; 753 } 754 /* Check for single MSI vector fallback. */ 755 if (ctlr->numirqs > 1 && 756 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 757 device_printf(dev, "Falling back to one MSI\n"); 758 ctlr->numirqs = 1; 759 } 760 /* Allocate all IRQs. */ 761 for (i = 0; i < ctlr->numirqs; i++) { 762 ctlr->irqs[i].ctlr = ctlr; 763 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 764 if (ctlr->numirqs == 1 || i >= ctlr->channels || 765 (ctlr->ccc && i == ctlr->cccv)) 766 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 767 else if (i == ctlr->numirqs - 1) 768 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 769 else 770 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 771 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 772 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 773 device_printf(dev, "unable to map interrupt\n"); 774 return ENXIO; 775 } 776 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 777 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 778 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 779 /* SOS XXX release r_irq */ 780 device_printf(dev, "unable to setup interrupt\n"); 781 return ENXIO; 782 } 783 if (ctlr->numirqs > 1) { 784 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 785 ctlr->irqs[i].handle, 786 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 787 "ch%d" : "%d", i); 788 } 789 } 790 return (0); 791 } 792 793 /* 794 * Common case interrupt handler. 795 */ 796 static void 797 ahci_intr(void *data) 798 { 799 struct ahci_controller_irq *irq = data; 800 struct ahci_controller *ctlr = irq->ctlr; 801 u_int32_t is, ise = 0; 802 void *arg; 803 int unit; 804 805 if (irq->mode == AHCI_IRQ_MODE_ALL) { 806 unit = 0; 807 if (ctlr->ccc) 808 is = ctlr->ichannels; 809 else 810 is = ATA_INL(ctlr->r_mem, AHCI_IS); 811 } else { /* AHCI_IRQ_MODE_AFTER */ 812 unit = irq->r_irq_rid - 1; 813 is = ATA_INL(ctlr->r_mem, AHCI_IS); 814 } 815 /* CCC interrupt is edge triggered. */ 816 if (ctlr->ccc) 817 ise = 1 << ctlr->cccv; 818 /* Some controllers have edge triggered IS. */ 819 if (ctlr->quirks & AHCI_Q_EDGEIS) 820 ise |= is; 821 if (ise != 0) 822 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 823 for (; unit < ctlr->channels; unit++) { 824 if ((is & (1 << unit)) != 0 && 825 (arg = ctlr->interrupt[unit].argument)) { 826 ctlr->interrupt[unit].function(arg); 827 } 828 } 829 /* AHCI declares level triggered IS. */ 830 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 831 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 832 } 833 834 /* 835 * Simplified interrupt handler for multivector MSI mode. 836 */ 837 static void 838 ahci_intr_one(void *data) 839 { 840 struct ahci_controller_irq *irq = data; 841 struct ahci_controller *ctlr = irq->ctlr; 842 void *arg; 843 int unit; 844 845 unit = irq->r_irq_rid - 1; 846 /* Some controllers have edge triggered IS. */ 847 if (ctlr->quirks & AHCI_Q_EDGEIS) 848 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 849 if ((arg = ctlr->interrupt[unit].argument)) 850 ctlr->interrupt[unit].function(arg); 851 /* AHCI declares level triggered IS. */ 852 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 853 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 854 } 855 856 static struct resource * 857 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 858 u_long start, u_long end, u_long count, u_int flags) 859 { 860 struct ahci_controller *ctlr = device_get_softc(dev); 861 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 862 struct resource *res = NULL; 863 int offset = AHCI_OFFSET + (unit << 7); 864 long st; 865 866 switch (type) { 867 case SYS_RES_MEMORY: 868 st = rman_get_start(ctlr->r_mem); 869 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 870 st + offset + 127, 128, RF_ACTIVE, child); 871 if (res) { 872 bus_space_handle_t bsh; 873 bus_space_tag_t bst; 874 bsh = rman_get_bushandle(ctlr->r_mem); 875 bst = rman_get_bustag(ctlr->r_mem); 876 bus_space_subregion(bst, bsh, offset, 128, &bsh); 877 rman_set_bushandle(res, bsh); 878 rman_set_bustag(res, bst); 879 } 880 break; 881 case SYS_RES_IRQ: 882 if (*rid == ATA_IRQ_RID) 883 res = ctlr->irqs[0].r_irq; 884 break; 885 } 886 return (res); 887 } 888 889 static int 890 ahci_release_resource(device_t dev, device_t child, int type, int rid, 891 struct resource *r) 892 { 893 894 switch (type) { 895 case SYS_RES_MEMORY: 896 rman_release_resource(r); 897 return (0); 898 case SYS_RES_IRQ: 899 if (rid != ATA_IRQ_RID) 900 return ENOENT; 901 return (0); 902 } 903 return (EINVAL); 904 } 905 906 static int 907 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 908 int flags, driver_filter_t *filter, driver_intr_t *function, 909 void *argument, void **cookiep) 910 { 911 struct ahci_controller *ctlr = device_get_softc(dev); 912 int unit = (intptr_t)device_get_ivars(child); 913 914 if (filter != NULL) { 915 printf("ahci.c: we cannot use a filter here\n"); 916 return (EINVAL); 917 } 918 ctlr->interrupt[unit].function = function; 919 ctlr->interrupt[unit].argument = argument; 920 return (0); 921 } 922 923 static int 924 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 925 void *cookie) 926 { 927 struct ahci_controller *ctlr = device_get_softc(dev); 928 int unit = (intptr_t)device_get_ivars(child); 929 930 ctlr->interrupt[unit].function = NULL; 931 ctlr->interrupt[unit].argument = NULL; 932 return (0); 933 } 934 935 static int 936 ahci_print_child(device_t dev, device_t child) 937 { 938 int retval; 939 940 retval = bus_print_child_header(dev, child); 941 retval += printf(" at channel %d", 942 (int)(intptr_t)device_get_ivars(child)); 943 retval += bus_print_child_footer(dev, child); 944 945 return (retval); 946 } 947 948 static int 949 ahci_child_location_str(device_t dev, device_t child, char *buf, 950 size_t buflen) 951 { 952 953 snprintf(buf, buflen, "channel=%d", 954 (int)(intptr_t)device_get_ivars(child)); 955 return (0); 956 } 957 958 static bus_dma_tag_t 959 ahci_get_dma_tag(device_t dev, device_t child) 960 { 961 struct ahci_controller *ctlr = device_get_softc(dev); 962 963 return (ctlr->dma_tag); 964 } 965 966 devclass_t ahci_devclass; 967 static device_method_t ahci_methods[] = { 968 DEVMETHOD(device_probe, ahci_probe), 969 DEVMETHOD(device_attach, ahci_attach), 970 DEVMETHOD(device_detach, ahci_detach), 971 DEVMETHOD(device_suspend, ahci_suspend), 972 DEVMETHOD(device_resume, ahci_resume), 973 DEVMETHOD(bus_print_child, ahci_print_child), 974 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 975 DEVMETHOD(bus_release_resource, ahci_release_resource), 976 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 977 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 978 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 979 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 980 DEVMETHOD_END 981 }; 982 static driver_t ahci_driver = { 983 "ahci", 984 ahci_methods, 985 sizeof(struct ahci_controller) 986 }; 987 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, NULL, NULL); 988 static device_method_t ahci_ata_methods[] = { 989 DEVMETHOD(device_probe, ahci_ata_probe), 990 DEVMETHOD(device_attach, ahci_attach), 991 DEVMETHOD(device_detach, ahci_detach), 992 DEVMETHOD(device_suspend, ahci_suspend), 993 DEVMETHOD(device_resume, ahci_resume), 994 DEVMETHOD(bus_print_child, ahci_print_child), 995 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 996 DEVMETHOD(bus_release_resource, ahci_release_resource), 997 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 998 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 999 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1000 DEVMETHOD_END 1001 }; 1002 static driver_t ahci_ata_driver = { 1003 "ahci", 1004 ahci_ata_methods, 1005 sizeof(struct ahci_controller) 1006 }; 1007 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, NULL, NULL); 1008 MODULE_VERSION(ahci, 1); 1009 MODULE_DEPEND(ahci, cam, 1, 1, 1); 1010 1011 static int 1012 ahci_ch_probe(device_t dev) 1013 { 1014 1015 device_set_desc_copy(dev, "AHCI channel"); 1016 return (0); 1017 } 1018 1019 static int 1020 ahci_ch_attach(device_t dev) 1021 { 1022 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1023 struct ahci_channel *ch = device_get_softc(dev); 1024 struct cam_devq *devq; 1025 int rid, error, i, sata_rev = 0; 1026 u_int32_t version; 1027 char buf[32]; 1028 1029 ch->dev = dev; 1030 ch->unit = (intptr_t)device_get_ivars(dev); 1031 ch->caps = ctlr->caps; 1032 ch->caps2 = ctlr->caps2; 1033 ch->quirks = ctlr->quirks; 1034 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 1035 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 1036 resource_int_value(device_get_name(dev), 1037 device_get_unit(dev), "pm_level", &ch->pm_level); 1038 if (ch->pm_level > 3) 1039 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 1040 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 1041 /* Limit speed for my onboard JMicron external port. 1042 * It is not eSATA really. */ 1043 if (pci_get_devid(ctlr->dev) == 0x2363197b && 1044 pci_get_subvendor(ctlr->dev) == 0x1043 && 1045 pci_get_subdevice(ctlr->dev) == 0x81e4 && 1046 ch->unit == 0) 1047 sata_rev = 1; 1048 if (ch->quirks & AHCI_Q_SATA2) 1049 sata_rev = 2; 1050 resource_int_value(device_get_name(dev), 1051 device_get_unit(dev), "sata_rev", &sata_rev); 1052 for (i = 0; i < 16; i++) { 1053 ch->user[i].revision = sata_rev; 1054 ch->user[i].mode = 0; 1055 ch->user[i].bytecount = 8192; 1056 ch->user[i].tags = ch->numslots; 1057 ch->user[i].caps = 0; 1058 ch->curr[i] = ch->user[i]; 1059 if (ch->pm_level) { 1060 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 1061 CTS_SATA_CAPS_H_APST | 1062 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1063 } 1064 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1065 CTS_SATA_CAPS_H_AN; 1066 } 1067 rid = ch->unit; 1068 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1069 &rid, RF_ACTIVE))) 1070 return (ENXIO); 1071 ahci_dmainit(dev); 1072 ahci_slotsalloc(dev); 1073 ahci_ch_init(dev); 1074 mtx_lock(&ch->mtx); 1075 rid = ATA_IRQ_RID; 1076 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1077 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1078 device_printf(dev, "Unable to map interrupt\n"); 1079 error = ENXIO; 1080 goto err0; 1081 } 1082 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1083 ahci_ch_intr_locked, dev, &ch->ih))) { 1084 device_printf(dev, "Unable to setup interrupt\n"); 1085 error = ENXIO; 1086 goto err1; 1087 } 1088 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1089 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1090 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1091 ch->chcaps |= AHCI_P_CMD_FBSCP; 1092 if (bootverbose) { 1093 device_printf(dev, "Caps:%s%s%s%s%s\n", 1094 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1095 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1096 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1097 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1098 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1099 } 1100 /* Create the device queue for our SIM. */ 1101 devq = cam_simq_alloc(ch->numslots); 1102 if (devq == NULL) { 1103 device_printf(dev, "Unable to allocate simq\n"); 1104 error = ENOMEM; 1105 goto err1; 1106 } 1107 /* Construct SIM entry */ 1108 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1109 device_get_unit(dev), &ch->mtx, 1110 min(2, ch->numslots), 1111 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1112 devq); 1113 if (ch->sim == NULL) { 1114 cam_simq_free(devq); 1115 device_printf(dev, "unable to allocate sim\n"); 1116 error = ENOMEM; 1117 goto err1; 1118 } 1119 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1120 device_printf(dev, "unable to register xpt bus\n"); 1121 error = ENXIO; 1122 goto err2; 1123 } 1124 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1125 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1126 device_printf(dev, "unable to create path\n"); 1127 error = ENXIO; 1128 goto err3; 1129 } 1130 if (ch->pm_level > 3) { 1131 callout_reset(&ch->pm_timer, 1132 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1133 ahci_ch_pm, dev); 1134 } 1135 mtx_unlock(&ch->mtx); 1136 if ((ch->caps & AHCI_CAP_EMS) && 1137 (ctlr->capsem & AHCI_EM_LED)) { 1138 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1139 ch->leds[i].dev = dev; 1140 ch->leds[i].num = i; 1141 } 1142 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) { 1143 snprintf(buf, sizeof(buf), "%s.act", 1144 device_get_nameunit(dev)); 1145 ch->leds[0].led = led_create(ahci_ch_led, 1146 &ch->leds[0], buf); 1147 } 1148 snprintf(buf, sizeof(buf), "%s.locate", 1149 device_get_nameunit(dev)); 1150 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf); 1151 snprintf(buf, sizeof(buf), "%s.fault", 1152 device_get_nameunit(dev)); 1153 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf); 1154 } 1155 return (0); 1156 1157 err3: 1158 xpt_bus_deregister(cam_sim_path(ch->sim)); 1159 err2: 1160 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1161 err1: 1162 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1163 err0: 1164 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1165 mtx_unlock(&ch->mtx); 1166 mtx_destroy(&ch->mtx); 1167 return (error); 1168 } 1169 1170 static int 1171 ahci_ch_detach(device_t dev) 1172 { 1173 struct ahci_channel *ch = device_get_softc(dev); 1174 int i; 1175 1176 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1177 if (ch->leds[i].led) 1178 led_destroy(ch->leds[i].led); 1179 } 1180 mtx_lock(&ch->mtx); 1181 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1182 /* Forget about reset. */ 1183 if (ch->resetting) { 1184 ch->resetting = 0; 1185 xpt_release_simq(ch->sim, TRUE); 1186 } 1187 xpt_free_path(ch->path); 1188 xpt_bus_deregister(cam_sim_path(ch->sim)); 1189 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1190 mtx_unlock(&ch->mtx); 1191 1192 if (ch->pm_level > 3) 1193 callout_drain(&ch->pm_timer); 1194 callout_drain(&ch->reset_timer); 1195 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1196 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1197 1198 ahci_ch_deinit(dev); 1199 ahci_slotsfree(dev); 1200 ahci_dmafini(dev); 1201 1202 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1203 mtx_destroy(&ch->mtx); 1204 return (0); 1205 } 1206 1207 static int 1208 ahci_ch_init(device_t dev) 1209 { 1210 struct ahci_channel *ch = device_get_softc(dev); 1211 uint64_t work; 1212 1213 /* Disable port interrupts */ 1214 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1215 /* Setup work areas */ 1216 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1217 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1218 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1219 work = ch->dma.rfis_bus; 1220 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1221 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1222 /* Activate the channel and power/spin up device */ 1223 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1224 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1225 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1226 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1227 ahci_start_fr(dev); 1228 ahci_start(dev, 1); 1229 return (0); 1230 } 1231 1232 static int 1233 ahci_ch_deinit(device_t dev) 1234 { 1235 struct ahci_channel *ch = device_get_softc(dev); 1236 1237 /* Disable port interrupts. */ 1238 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1239 /* Reset command register. */ 1240 ahci_stop(dev); 1241 ahci_stop_fr(dev); 1242 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1243 /* Allow everything, including partial and slumber modes. */ 1244 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1245 /* Request slumber mode transition and give some time to get there. */ 1246 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1247 DELAY(100); 1248 /* Disable PHY. */ 1249 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1250 return (0); 1251 } 1252 1253 static int 1254 ahci_ch_suspend(device_t dev) 1255 { 1256 struct ahci_channel *ch = device_get_softc(dev); 1257 1258 mtx_lock(&ch->mtx); 1259 xpt_freeze_simq(ch->sim, 1); 1260 /* Forget about reset. */ 1261 if (ch->resetting) { 1262 ch->resetting = 0; 1263 callout_stop(&ch->reset_timer); 1264 xpt_release_simq(ch->sim, TRUE); 1265 } 1266 while (ch->oslots) 1267 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1268 ahci_ch_deinit(dev); 1269 mtx_unlock(&ch->mtx); 1270 return (0); 1271 } 1272 1273 static int 1274 ahci_ch_resume(device_t dev) 1275 { 1276 struct ahci_channel *ch = device_get_softc(dev); 1277 1278 mtx_lock(&ch->mtx); 1279 ahci_ch_init(dev); 1280 ahci_reset(dev); 1281 xpt_release_simq(ch->sim, TRUE); 1282 mtx_unlock(&ch->mtx); 1283 return (0); 1284 } 1285 1286 devclass_t ahcich_devclass; 1287 static device_method_t ahcich_methods[] = { 1288 DEVMETHOD(device_probe, ahci_ch_probe), 1289 DEVMETHOD(device_attach, ahci_ch_attach), 1290 DEVMETHOD(device_detach, ahci_ch_detach), 1291 DEVMETHOD(device_suspend, ahci_ch_suspend), 1292 DEVMETHOD(device_resume, ahci_ch_resume), 1293 DEVMETHOD_END 1294 }; 1295 static driver_t ahcich_driver = { 1296 "ahcich", 1297 ahcich_methods, 1298 sizeof(struct ahci_channel) 1299 }; 1300 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL); 1301 1302 static void 1303 ahci_ch_setleds(device_t dev) 1304 { 1305 struct ahci_channel *ch; 1306 struct ahci_controller *ctlr; 1307 size_t buf; 1308 int i, timeout; 1309 int16_t val; 1310 1311 ctlr = device_get_softc(device_get_parent(dev)); 1312 ch = device_get_softc(dev); 1313 1314 val = 0; 1315 for (i = 0; i < AHCI_NUM_LEDS; i++) 1316 val |= ch->leds[i].state << (i * 3); 1317 1318 buf = (ctlr->emloc & 0xffff0000) >> 14; 1319 mtx_lock(&ctlr->em_mtx); 1320 timeout = 1000; 1321 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) && 1322 --timeout > 0) 1323 DELAY(1000); 1324 if (timeout == 0) 1325 device_printf(dev, "EM timeout\n"); 1326 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24)); 1327 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16)); 1328 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM); 1329 mtx_unlock(&ctlr->em_mtx); 1330 } 1331 1332 static void 1333 ahci_ch_led(void *priv, int onoff) 1334 { 1335 struct ahci_led *led; 1336 1337 led = (struct ahci_led *)priv; 1338 1339 led->state = onoff; 1340 ahci_ch_setleds(led->dev); 1341 } 1342 1343 struct ahci_dc_cb_args { 1344 bus_addr_t maddr; 1345 int error; 1346 }; 1347 1348 static void 1349 ahci_dmainit(device_t dev) 1350 { 1351 struct ahci_channel *ch = device_get_softc(dev); 1352 struct ahci_dc_cb_args dcba; 1353 size_t rfsize; 1354 1355 /* Command area. */ 1356 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1357 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1358 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1359 0, NULL, NULL, &ch->dma.work_tag)) 1360 goto error; 1361 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1362 BUS_DMA_ZERO, &ch->dma.work_map)) 1363 goto error; 1364 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1365 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1366 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1367 goto error; 1368 } 1369 ch->dma.work_bus = dcba.maddr; 1370 /* FIS receive area. */ 1371 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1372 rfsize = 4096; 1373 else 1374 rfsize = 256; 1375 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1376 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1377 NULL, NULL, rfsize, 1, rfsize, 1378 0, NULL, NULL, &ch->dma.rfis_tag)) 1379 goto error; 1380 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1381 &ch->dma.rfis_map)) 1382 goto error; 1383 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1384 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1385 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1386 goto error; 1387 } 1388 ch->dma.rfis_bus = dcba.maddr; 1389 /* Data area. */ 1390 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1391 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1392 NULL, NULL, 1393 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1394 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1395 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1396 goto error; 1397 } 1398 return; 1399 1400 error: 1401 device_printf(dev, "WARNING - DMA initialization failed\n"); 1402 ahci_dmafini(dev); 1403 } 1404 1405 static void 1406 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1407 { 1408 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1409 1410 if (!(dcba->error = error)) 1411 dcba->maddr = segs[0].ds_addr; 1412 } 1413 1414 static void 1415 ahci_dmafini(device_t dev) 1416 { 1417 struct ahci_channel *ch = device_get_softc(dev); 1418 1419 if (ch->dma.data_tag) { 1420 bus_dma_tag_destroy(ch->dma.data_tag); 1421 ch->dma.data_tag = NULL; 1422 } 1423 if (ch->dma.rfis_bus) { 1424 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1425 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1426 ch->dma.rfis_bus = 0; 1427 ch->dma.rfis_map = NULL; 1428 ch->dma.rfis = NULL; 1429 } 1430 if (ch->dma.work_bus) { 1431 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1432 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1433 ch->dma.work_bus = 0; 1434 ch->dma.work_map = NULL; 1435 ch->dma.work = NULL; 1436 } 1437 if (ch->dma.work_tag) { 1438 bus_dma_tag_destroy(ch->dma.work_tag); 1439 ch->dma.work_tag = NULL; 1440 } 1441 } 1442 1443 static void 1444 ahci_slotsalloc(device_t dev) 1445 { 1446 struct ahci_channel *ch = device_get_softc(dev); 1447 int i; 1448 1449 /* Alloc and setup command/dma slots */ 1450 bzero(ch->slot, sizeof(ch->slot)); 1451 for (i = 0; i < ch->numslots; i++) { 1452 struct ahci_slot *slot = &ch->slot[i]; 1453 1454 slot->dev = dev; 1455 slot->slot = i; 1456 slot->state = AHCI_SLOT_EMPTY; 1457 slot->ccb = NULL; 1458 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1459 1460 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1461 device_printf(ch->dev, "FAILURE - create data_map\n"); 1462 } 1463 } 1464 1465 static void 1466 ahci_slotsfree(device_t dev) 1467 { 1468 struct ahci_channel *ch = device_get_softc(dev); 1469 int i; 1470 1471 /* Free all dma slots */ 1472 for (i = 0; i < ch->numslots; i++) { 1473 struct ahci_slot *slot = &ch->slot[i]; 1474 1475 callout_drain(&slot->timeout); 1476 if (slot->dma.data_map) { 1477 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1478 slot->dma.data_map = NULL; 1479 } 1480 } 1481 } 1482 1483 static int 1484 ahci_phy_check_events(device_t dev, u_int32_t serr) 1485 { 1486 struct ahci_channel *ch = device_get_softc(dev); 1487 1488 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1489 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1490 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1491 union ccb *ccb; 1492 1493 if (bootverbose) { 1494 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1495 device_printf(dev, "CONNECT requested\n"); 1496 else 1497 device_printf(dev, "DISCONNECT requested\n"); 1498 } 1499 ahci_reset(dev); 1500 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1501 return (0); 1502 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1503 cam_sim_path(ch->sim), 1504 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1505 xpt_free_ccb(ccb); 1506 return (0); 1507 } 1508 xpt_rescan(ccb); 1509 return (1); 1510 } 1511 return (0); 1512 } 1513 1514 static void 1515 ahci_cpd_check_events(device_t dev) 1516 { 1517 struct ahci_channel *ch = device_get_softc(dev); 1518 u_int32_t status; 1519 union ccb *ccb; 1520 1521 if (ch->pm_level == 0) 1522 return; 1523 1524 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1525 if ((status & AHCI_P_CMD_CPD) == 0) 1526 return; 1527 1528 if (bootverbose) { 1529 if (status & AHCI_P_CMD_CPS) { 1530 device_printf(dev, "COLD CONNECT requested\n"); 1531 } else 1532 device_printf(dev, "COLD DISCONNECT requested\n"); 1533 } 1534 ahci_reset(dev); 1535 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1536 return; 1537 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1538 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1539 xpt_free_ccb(ccb); 1540 return; 1541 } 1542 xpt_rescan(ccb); 1543 } 1544 1545 static void 1546 ahci_notify_events(device_t dev, u_int32_t status) 1547 { 1548 struct ahci_channel *ch = device_get_softc(dev); 1549 struct cam_path *dpath; 1550 int i; 1551 1552 if (ch->caps & AHCI_CAP_SSNTF) 1553 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1554 if (bootverbose) 1555 device_printf(dev, "SNTF 0x%04x\n", status); 1556 for (i = 0; i < 16; i++) { 1557 if ((status & (1 << i)) == 0) 1558 continue; 1559 if (xpt_create_path(&dpath, NULL, 1560 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1561 xpt_async(AC_SCSI_AEN, dpath, NULL); 1562 xpt_free_path(dpath); 1563 } 1564 } 1565 } 1566 1567 static void 1568 ahci_ch_intr_locked(void *data) 1569 { 1570 device_t dev = (device_t)data; 1571 struct ahci_channel *ch = device_get_softc(dev); 1572 1573 mtx_lock(&ch->mtx); 1574 xpt_batch_start(ch->sim); 1575 ahci_ch_intr(data); 1576 xpt_batch_done(ch->sim); 1577 mtx_unlock(&ch->mtx); 1578 } 1579 1580 static void 1581 ahci_ch_pm(void *arg) 1582 { 1583 device_t dev = (device_t)arg; 1584 struct ahci_channel *ch = device_get_softc(dev); 1585 uint32_t work; 1586 1587 if (ch->numrslots != 0) 1588 return; 1589 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1590 if (ch->pm_level == 4) 1591 work |= AHCI_P_CMD_PARTIAL; 1592 else 1593 work |= AHCI_P_CMD_SLUMBER; 1594 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1595 } 1596 1597 static void 1598 ahci_ch_intr(void *data) 1599 { 1600 device_t dev = (device_t)data; 1601 struct ahci_channel *ch = device_get_softc(dev); 1602 uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err; 1603 enum ahci_err_type et; 1604 int i, ccs, port, reset = 0; 1605 1606 /* Read and clear interrupt statuses. */ 1607 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1608 if (istatus == 0) 1609 return; 1610 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1611 /* Read command statuses. */ 1612 if (ch->numtslots != 0) 1613 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1614 else 1615 cstatus = 0; 1616 if (ch->numrslots != ch->numtslots) 1617 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1618 /* Read SNTF in one of possible ways. */ 1619 if ((istatus & AHCI_P_IX_SDB) && 1620 (ch->pm_present || ch->curr[0].atapi != 0)) { 1621 if (ch->caps & AHCI_CAP_SSNTF) 1622 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1623 else if (ch->fbs_enabled) { 1624 u_int8_t *fis = ch->dma.rfis + 0x58; 1625 1626 for (i = 0; i < 16; i++) { 1627 if (fis[1] & 0x80) { 1628 fis[1] &= 0x7f; 1629 sntf |= 1 << i; 1630 } 1631 fis += 256; 1632 } 1633 } else { 1634 u_int8_t *fis = ch->dma.rfis + 0x58; 1635 1636 if (fis[1] & 0x80) 1637 sntf = (1 << (fis[1] & 0x0f)); 1638 } 1639 } 1640 /* Process PHY events */ 1641 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1642 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1643 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1644 if (serr) { 1645 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1646 reset = ahci_phy_check_events(dev, serr); 1647 } 1648 } 1649 /* Process cold presence detection events */ 1650 if ((istatus & AHCI_P_IX_CPD) && !reset) 1651 ahci_cpd_check_events(dev); 1652 /* Process command errors */ 1653 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1654 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1655 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1656 >> AHCI_P_CMD_CCS_SHIFT; 1657 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1658 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1659 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1660 port = -1; 1661 if (ch->fbs_enabled) { 1662 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1663 if (fbs & AHCI_P_FBS_SDE) { 1664 port = (fbs & AHCI_P_FBS_DWE) 1665 >> AHCI_P_FBS_DWE_SHIFT; 1666 } else { 1667 for (i = 0; i < 16; i++) { 1668 if (ch->numrslotspd[i] == 0) 1669 continue; 1670 if (port == -1) 1671 port = i; 1672 else if (port != i) { 1673 port = -2; 1674 break; 1675 } 1676 } 1677 } 1678 } 1679 err = ch->rslots & cstatus; 1680 } else { 1681 ccs = 0; 1682 err = 0; 1683 port = -1; 1684 } 1685 /* Complete all successfull commands. */ 1686 ok = ch->rslots & ~cstatus; 1687 for (i = 0; i < ch->numslots; i++) { 1688 if ((ok >> i) & 1) 1689 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1690 } 1691 /* On error, complete the rest of commands with error statuses. */ 1692 if (err) { 1693 if (ch->frozen) { 1694 union ccb *fccb = ch->frozen; 1695 ch->frozen = NULL; 1696 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1697 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1698 xpt_freeze_devq(fccb->ccb_h.path, 1); 1699 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1700 } 1701 xpt_done(fccb); 1702 } 1703 for (i = 0; i < ch->numslots; i++) { 1704 /* XXX: reqests in loading state. */ 1705 if (((err >> i) & 1) == 0) 1706 continue; 1707 if (port >= 0 && 1708 ch->slot[i].ccb->ccb_h.target_id != port) 1709 continue; 1710 if (istatus & AHCI_P_IX_TFE) { 1711 if (port != -2) { 1712 /* Task File Error */ 1713 if (ch->numtslotspd[ 1714 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1715 /* Untagged operation. */ 1716 if (i == ccs) 1717 et = AHCI_ERR_TFE; 1718 else 1719 et = AHCI_ERR_INNOCENT; 1720 } else { 1721 /* Tagged operation. */ 1722 et = AHCI_ERR_NCQ; 1723 } 1724 } else { 1725 et = AHCI_ERR_TFE; 1726 ch->fatalerr = 1; 1727 } 1728 } else if (istatus & AHCI_P_IX_IF) { 1729 if (ch->numtslots == 0 && i != ccs && port != -2) 1730 et = AHCI_ERR_INNOCENT; 1731 else 1732 et = AHCI_ERR_SATA; 1733 } else 1734 et = AHCI_ERR_INVALID; 1735 ahci_end_transaction(&ch->slot[i], et); 1736 } 1737 /* 1738 * We can't reinit port if there are some other 1739 * commands active, use resume to complete them. 1740 */ 1741 if (ch->rslots != 0 && !ch->recoverycmd) 1742 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1743 } 1744 /* Process NOTIFY events */ 1745 if (sntf) 1746 ahci_notify_events(dev, sntf); 1747 } 1748 1749 /* Must be called with channel locked. */ 1750 static int 1751 ahci_check_collision(device_t dev, union ccb *ccb) 1752 { 1753 struct ahci_channel *ch = device_get_softc(dev); 1754 int t = ccb->ccb_h.target_id; 1755 1756 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1757 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1758 /* Tagged command while we have no supported tag free. */ 1759 if (((~ch->oslots) & (0xffffffff >> (32 - 1760 ch->curr[t].tags))) == 0) 1761 return (1); 1762 /* If we have FBS */ 1763 if (ch->fbs_enabled) { 1764 /* Tagged command while untagged are active. */ 1765 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1766 return (1); 1767 } else { 1768 /* Tagged command while untagged are active. */ 1769 if (ch->numrslots != 0 && ch->numtslots == 0) 1770 return (1); 1771 /* Tagged command while tagged to other target is active. */ 1772 if (ch->numtslots != 0 && 1773 ch->taggedtarget != ccb->ccb_h.target_id) 1774 return (1); 1775 } 1776 } else { 1777 /* If we have FBS */ 1778 if (ch->fbs_enabled) { 1779 /* Untagged command while tagged are active. */ 1780 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1781 return (1); 1782 } else { 1783 /* Untagged command while tagged are active. */ 1784 if (ch->numrslots != 0 && ch->numtslots != 0) 1785 return (1); 1786 } 1787 } 1788 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1789 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1790 /* Atomic command while anything active. */ 1791 if (ch->numrslots != 0) 1792 return (1); 1793 } 1794 /* We have some atomic command running. */ 1795 if (ch->aslots != 0) 1796 return (1); 1797 return (0); 1798 } 1799 1800 /* Must be called with channel locked. */ 1801 static void 1802 ahci_begin_transaction(device_t dev, union ccb *ccb) 1803 { 1804 struct ahci_channel *ch = device_get_softc(dev); 1805 struct ahci_slot *slot; 1806 int tag, tags; 1807 1808 /* Choose empty slot. */ 1809 tags = ch->numslots; 1810 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1811 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1812 tags = ch->curr[ccb->ccb_h.target_id].tags; 1813 tag = ch->lastslot; 1814 while (1) { 1815 if (tag >= tags) 1816 tag = 0; 1817 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1818 break; 1819 tag++; 1820 }; 1821 ch->lastslot = tag; 1822 /* Occupy chosen slot. */ 1823 slot = &ch->slot[tag]; 1824 slot->ccb = ccb; 1825 /* Stop PM timer. */ 1826 if (ch->numrslots == 0 && ch->pm_level > 3) 1827 callout_stop(&ch->pm_timer); 1828 /* Update channel stats. */ 1829 ch->oslots |= (1 << slot->slot); 1830 ch->numrslots++; 1831 ch->numrslotspd[ccb->ccb_h.target_id]++; 1832 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1833 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1834 ch->numtslots++; 1835 ch->numtslotspd[ccb->ccb_h.target_id]++; 1836 ch->taggedtarget = ccb->ccb_h.target_id; 1837 } 1838 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1839 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1840 ch->aslots |= (1 << slot->slot); 1841 slot->dma.nsegs = 0; 1842 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1843 slot->state = AHCI_SLOT_LOADING; 1844 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1845 ahci_dmasetprd, slot, 0); 1846 } else 1847 ahci_execute_transaction(slot); 1848 } 1849 1850 /* Locked by busdma engine. */ 1851 static void 1852 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1853 { 1854 struct ahci_slot *slot = arg; 1855 struct ahci_channel *ch = device_get_softc(slot->dev); 1856 struct ahci_cmd_tab *ctp; 1857 struct ahci_dma_prd *prd; 1858 int i; 1859 1860 if (error) { 1861 device_printf(slot->dev, "DMA load error\n"); 1862 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1863 return; 1864 } 1865 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1866 /* Get a piece of the workspace for this request */ 1867 ctp = (struct ahci_cmd_tab *) 1868 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1869 /* Fill S/G table */ 1870 prd = &ctp->prd_tab[0]; 1871 for (i = 0; i < nsegs; i++) { 1872 prd[i].dba = htole64(segs[i].ds_addr); 1873 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1874 } 1875 slot->dma.nsegs = nsegs; 1876 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1877 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1878 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1879 ahci_execute_transaction(slot); 1880 } 1881 1882 /* Must be called with channel locked. */ 1883 static void 1884 ahci_execute_transaction(struct ahci_slot *slot) 1885 { 1886 device_t dev = slot->dev; 1887 struct ahci_channel *ch = device_get_softc(dev); 1888 struct ahci_cmd_tab *ctp; 1889 struct ahci_cmd_list *clp; 1890 union ccb *ccb = slot->ccb; 1891 int port = ccb->ccb_h.target_id & 0x0f; 1892 int fis_size, i, softreset; 1893 uint8_t *fis = ch->dma.rfis + 0x40; 1894 uint8_t val; 1895 1896 /* Get a piece of the workspace for this request */ 1897 ctp = (struct ahci_cmd_tab *) 1898 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1899 /* Setup the FIS for this request */ 1900 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1901 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1902 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1903 return; 1904 } 1905 /* Setup the command list entry */ 1906 clp = (struct ahci_cmd_list *) 1907 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1908 clp->cmd_flags = htole16( 1909 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1910 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1911 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1912 (fis_size / sizeof(u_int32_t)) | 1913 (port << 12)); 1914 clp->prd_length = htole16(slot->dma.nsegs); 1915 /* Special handling for Soft Reset command. */ 1916 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1917 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1918 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1919 softreset = 1; 1920 /* Kick controller into sane state */ 1921 ahci_stop(dev); 1922 ahci_clo(dev); 1923 ahci_start(dev, 0); 1924 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1925 } else { 1926 softreset = 2; 1927 /* Prepare FIS receive area for check. */ 1928 for (i = 0; i < 20; i++) 1929 fis[i] = 0xff; 1930 } 1931 } else 1932 softreset = 0; 1933 clp->bytecount = 0; 1934 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1935 (AHCI_CT_SIZE * slot->slot)); 1936 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1937 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1938 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1939 BUS_DMASYNC_PREREAD); 1940 /* Set ACTIVE bit for NCQ commands. */ 1941 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1942 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1943 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1944 } 1945 /* If FBS is enabled, set PMP port. */ 1946 if (ch->fbs_enabled) { 1947 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1948 (port << AHCI_P_FBS_DEV_SHIFT)); 1949 } 1950 /* Issue command to the controller. */ 1951 slot->state = AHCI_SLOT_RUNNING; 1952 ch->rslots |= (1 << slot->slot); 1953 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1954 /* Device reset commands doesn't interrupt. Poll them. */ 1955 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1956 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1957 int count, timeout = ccb->ccb_h.timeout * 100; 1958 enum ahci_err_type et = AHCI_ERR_NONE; 1959 1960 for (count = 0; count < timeout; count++) { 1961 DELAY(10); 1962 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1963 break; 1964 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1965 softreset != 1) { 1966 #if 0 1967 device_printf(ch->dev, 1968 "Poll error on slot %d, TFD: %04x\n", 1969 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1970 #endif 1971 et = AHCI_ERR_TFE; 1972 break; 1973 } 1974 /* Workaround for ATI SB600/SB700 chipsets. */ 1975 if (ccb->ccb_h.target_id == 15 && 1976 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1977 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1978 et = AHCI_ERR_TIMEOUT; 1979 break; 1980 } 1981 } 1982 1983 /* 1984 * Marvell HBAs with non-RAID firmware do not wait for 1985 * readiness after soft reset, so we have to wait here. 1986 * Marvell RAIDs do not have this problem, but instead 1987 * sometimes forget to update FIS receive area, breaking 1988 * this wait. 1989 */ 1990 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1991 softreset == 2 && et == AHCI_ERR_NONE) { 1992 while ((val = fis[2]) & ATA_S_BUSY) { 1993 DELAY(10); 1994 if (count++ >= timeout) 1995 break; 1996 } 1997 } 1998 1999 if (timeout && (count >= timeout)) { 2000 device_printf(dev, "Poll timeout on slot %d port %d\n", 2001 slot->slot, port); 2002 device_printf(dev, "is %08x cs %08x ss %08x " 2003 "rs %08x tfd %02x serr %08x cmd %08x\n", 2004 ATA_INL(ch->r_mem, AHCI_P_IS), 2005 ATA_INL(ch->r_mem, AHCI_P_CI), 2006 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2007 ATA_INL(ch->r_mem, AHCI_P_TFD), 2008 ATA_INL(ch->r_mem, AHCI_P_SERR), 2009 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2010 et = AHCI_ERR_TIMEOUT; 2011 } 2012 2013 /* Kick controller into sane state and enable FBS. */ 2014 if (softreset == 2) 2015 ch->eslots |= (1 << slot->slot); 2016 ahci_end_transaction(slot, et); 2017 return; 2018 } 2019 /* Start command execution timeout */ 2020 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 2021 (timeout_t*)ahci_timeout, slot); 2022 return; 2023 } 2024 2025 /* Must be called with channel locked. */ 2026 static void 2027 ahci_process_timeout(device_t dev) 2028 { 2029 struct ahci_channel *ch = device_get_softc(dev); 2030 int i; 2031 2032 mtx_assert(&ch->mtx, MA_OWNED); 2033 /* Handle the rest of commands. */ 2034 for (i = 0; i < ch->numslots; i++) { 2035 /* Do we have a running request on slot? */ 2036 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2037 continue; 2038 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 2039 } 2040 } 2041 2042 /* Must be called with channel locked. */ 2043 static void 2044 ahci_rearm_timeout(device_t dev) 2045 { 2046 struct ahci_channel *ch = device_get_softc(dev); 2047 int i; 2048 2049 mtx_assert(&ch->mtx, MA_OWNED); 2050 for (i = 0; i < ch->numslots; i++) { 2051 struct ahci_slot *slot = &ch->slot[i]; 2052 2053 /* Do we have a running request on slot? */ 2054 if (slot->state < AHCI_SLOT_RUNNING) 2055 continue; 2056 if ((ch->toslots & (1 << i)) == 0) 2057 continue; 2058 callout_reset(&slot->timeout, 2059 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2060 (timeout_t*)ahci_timeout, slot); 2061 } 2062 } 2063 2064 /* Locked by callout mechanism. */ 2065 static void 2066 ahci_timeout(struct ahci_slot *slot) 2067 { 2068 device_t dev = slot->dev; 2069 struct ahci_channel *ch = device_get_softc(dev); 2070 uint32_t sstatus; 2071 int ccs; 2072 int i; 2073 2074 /* Check for stale timeout. */ 2075 if (slot->state < AHCI_SLOT_RUNNING) 2076 return; 2077 2078 /* Check if slot was not being executed last time we checked. */ 2079 if (slot->state < AHCI_SLOT_EXECUTING) { 2080 /* Check if slot started executing. */ 2081 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 2082 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 2083 >> AHCI_P_CMD_CCS_SHIFT; 2084 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 2085 ch->fbs_enabled || ch->wrongccs) 2086 slot->state = AHCI_SLOT_EXECUTING; 2087 else if ((ch->rslots & (1 << ccs)) == 0) { 2088 ch->wrongccs = 1; 2089 slot->state = AHCI_SLOT_EXECUTING; 2090 } 2091 2092 callout_reset(&slot->timeout, 2093 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2094 (timeout_t*)ahci_timeout, slot); 2095 return; 2096 } 2097 2098 device_printf(dev, "Timeout on slot %d port %d\n", 2099 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2100 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2101 "serr %08x cmd %08x\n", 2102 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2103 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2104 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2105 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2106 2107 /* Handle frozen command. */ 2108 if (ch->frozen) { 2109 union ccb *fccb = ch->frozen; 2110 ch->frozen = NULL; 2111 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2112 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2113 xpt_freeze_devq(fccb->ccb_h.path, 1); 2114 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2115 } 2116 xpt_done(fccb); 2117 } 2118 if (!ch->fbs_enabled && !ch->wrongccs) { 2119 /* Without FBS we know real timeout source. */ 2120 ch->fatalerr = 1; 2121 /* Handle command with timeout. */ 2122 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2123 /* Handle the rest of commands. */ 2124 for (i = 0; i < ch->numslots; i++) { 2125 /* Do we have a running request on slot? */ 2126 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2127 continue; 2128 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2129 } 2130 } else { 2131 /* With FBS we wait for other commands timeout and pray. */ 2132 if (ch->toslots == 0) 2133 xpt_freeze_simq(ch->sim, 1); 2134 ch->toslots |= (1 << slot->slot); 2135 if ((ch->rslots & ~ch->toslots) == 0) 2136 ahci_process_timeout(dev); 2137 else 2138 device_printf(dev, " ... waiting for slots %08x\n", 2139 ch->rslots & ~ch->toslots); 2140 } 2141 } 2142 2143 /* Must be called with channel locked. */ 2144 static void 2145 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2146 { 2147 device_t dev = slot->dev; 2148 struct ahci_channel *ch = device_get_softc(dev); 2149 union ccb *ccb = slot->ccb; 2150 struct ahci_cmd_list *clp; 2151 int lastto; 2152 uint32_t sig; 2153 2154 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2155 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2156 clp = (struct ahci_cmd_list *) 2157 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2158 /* Read result registers to the result struct 2159 * May be incorrect if several commands finished same time, 2160 * so read only when sure or have to. 2161 */ 2162 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2163 struct ata_res *res = &ccb->ataio.res; 2164 2165 if ((et == AHCI_ERR_TFE) || 2166 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2167 u_int8_t *fis = ch->dma.rfis + 0x40; 2168 2169 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2170 BUS_DMASYNC_POSTREAD); 2171 if (ch->fbs_enabled) { 2172 fis += ccb->ccb_h.target_id * 256; 2173 res->status = fis[2]; 2174 res->error = fis[3]; 2175 } else { 2176 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2177 2178 res->status = tfd; 2179 res->error = tfd >> 8; 2180 } 2181 res->lba_low = fis[4]; 2182 res->lba_mid = fis[5]; 2183 res->lba_high = fis[6]; 2184 res->device = fis[7]; 2185 res->lba_low_exp = fis[8]; 2186 res->lba_mid_exp = fis[9]; 2187 res->lba_high_exp = fis[10]; 2188 res->sector_count = fis[12]; 2189 res->sector_count_exp = fis[13]; 2190 2191 /* 2192 * Some weird controllers do not return signature in 2193 * FIS receive area. Read it from PxSIG register. 2194 */ 2195 if ((ch->quirks & AHCI_Q_ALTSIG) && 2196 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2197 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2198 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2199 res->lba_high = sig >> 24; 2200 res->lba_mid = sig >> 16; 2201 res->lba_low = sig >> 8; 2202 res->sector_count = sig; 2203 } 2204 } else 2205 bzero(res, sizeof(*res)); 2206 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2207 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2208 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2209 ccb->ataio.resid = 2210 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2211 } 2212 } else { 2213 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2214 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2215 ccb->csio.resid = 2216 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2217 } 2218 } 2219 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2220 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2221 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2222 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2223 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2224 } 2225 if (et != AHCI_ERR_NONE) 2226 ch->eslots |= (1 << slot->slot); 2227 /* In case of error, freeze device for proper recovery. */ 2228 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2229 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2230 xpt_freeze_devq(ccb->ccb_h.path, 1); 2231 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2232 } 2233 /* Set proper result status. */ 2234 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2235 switch (et) { 2236 case AHCI_ERR_NONE: 2237 ccb->ccb_h.status |= CAM_REQ_CMP; 2238 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2239 ccb->csio.scsi_status = SCSI_STATUS_OK; 2240 break; 2241 case AHCI_ERR_INVALID: 2242 ch->fatalerr = 1; 2243 ccb->ccb_h.status |= CAM_REQ_INVALID; 2244 break; 2245 case AHCI_ERR_INNOCENT: 2246 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2247 break; 2248 case AHCI_ERR_TFE: 2249 case AHCI_ERR_NCQ: 2250 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2251 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2252 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2253 } else { 2254 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2255 } 2256 break; 2257 case AHCI_ERR_SATA: 2258 ch->fatalerr = 1; 2259 if (!ch->recoverycmd) { 2260 xpt_freeze_simq(ch->sim, 1); 2261 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2262 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2263 } 2264 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2265 break; 2266 case AHCI_ERR_TIMEOUT: 2267 if (!ch->recoverycmd) { 2268 xpt_freeze_simq(ch->sim, 1); 2269 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2270 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2271 } 2272 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2273 break; 2274 default: 2275 ch->fatalerr = 1; 2276 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2277 } 2278 /* Free slot. */ 2279 ch->oslots &= ~(1 << slot->slot); 2280 ch->rslots &= ~(1 << slot->slot); 2281 ch->aslots &= ~(1 << slot->slot); 2282 slot->state = AHCI_SLOT_EMPTY; 2283 slot->ccb = NULL; 2284 /* Update channel stats. */ 2285 ch->numrslots--; 2286 ch->numrslotspd[ccb->ccb_h.target_id]--; 2287 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2288 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2289 ch->numtslots--; 2290 ch->numtslotspd[ccb->ccb_h.target_id]--; 2291 } 2292 /* Cancel timeout state if request completed normally. */ 2293 if (et != AHCI_ERR_TIMEOUT) { 2294 lastto = (ch->toslots == (1 << slot->slot)); 2295 ch->toslots &= ~(1 << slot->slot); 2296 if (lastto) 2297 xpt_release_simq(ch->sim, TRUE); 2298 } 2299 /* If it was first request of reset sequence and there is no error, 2300 * proceed to second request. */ 2301 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2302 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2303 (ccb->ataio.cmd.control & ATA_A_RESET) && 2304 et == AHCI_ERR_NONE) { 2305 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2306 ahci_begin_transaction(dev, ccb); 2307 return; 2308 } 2309 /* If it was our READ LOG command - process it. */ 2310 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2311 ahci_process_read_log(dev, ccb); 2312 /* If it was our REQUEST SENSE command - process it. */ 2313 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2314 ahci_process_request_sense(dev, ccb); 2315 /* If it was NCQ or ATAPI command error, put result on hold. */ 2316 } else if (et == AHCI_ERR_NCQ || 2317 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2318 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2319 ch->hold[slot->slot] = ccb; 2320 ch->numhslots++; 2321 } else 2322 xpt_done(ccb); 2323 /* If we have no other active commands, ... */ 2324 if (ch->rslots == 0) { 2325 /* if there was fatal error - reset port. */ 2326 if (ch->toslots != 0 || ch->fatalerr) { 2327 ahci_reset(dev); 2328 } else { 2329 /* if we have slots in error, we can reinit port. */ 2330 if (ch->eslots != 0) { 2331 ahci_stop(dev); 2332 ahci_clo(dev); 2333 ahci_start(dev, 1); 2334 } 2335 /* if there commands on hold, we can do READ LOG. */ 2336 if (!ch->recoverycmd && ch->numhslots) 2337 ahci_issue_recovery(dev); 2338 } 2339 /* If all the rest of commands are in timeout - give them chance. */ 2340 } else if ((ch->rslots & ~ch->toslots) == 0 && 2341 et != AHCI_ERR_TIMEOUT) 2342 ahci_rearm_timeout(dev); 2343 /* Unfreeze frozen command. */ 2344 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2345 union ccb *fccb = ch->frozen; 2346 ch->frozen = NULL; 2347 ahci_begin_transaction(dev, fccb); 2348 xpt_release_simq(ch->sim, TRUE); 2349 } 2350 /* Start PM timer. */ 2351 if (ch->numrslots == 0 && ch->pm_level > 3 && 2352 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2353 callout_schedule(&ch->pm_timer, 2354 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2355 } 2356 } 2357 2358 static void 2359 ahci_issue_recovery(device_t dev) 2360 { 2361 struct ahci_channel *ch = device_get_softc(dev); 2362 union ccb *ccb; 2363 struct ccb_ataio *ataio; 2364 struct ccb_scsiio *csio; 2365 int i; 2366 2367 /* Find some held command. */ 2368 for (i = 0; i < ch->numslots; i++) { 2369 if (ch->hold[i]) 2370 break; 2371 } 2372 ccb = xpt_alloc_ccb_nowait(); 2373 if (ccb == NULL) { 2374 device_printf(dev, "Unable to allocate recovery command\n"); 2375 completeall: 2376 /* We can't do anything -- complete held commands. */ 2377 for (i = 0; i < ch->numslots; i++) { 2378 if (ch->hold[i] == NULL) 2379 continue; 2380 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2381 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2382 xpt_done(ch->hold[i]); 2383 ch->hold[i] = NULL; 2384 ch->numhslots--; 2385 } 2386 ahci_reset(dev); 2387 return; 2388 } 2389 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2390 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2391 /* READ LOG */ 2392 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2393 ccb->ccb_h.func_code = XPT_ATA_IO; 2394 ccb->ccb_h.flags = CAM_DIR_IN; 2395 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2396 ataio = &ccb->ataio; 2397 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2398 if (ataio->data_ptr == NULL) { 2399 xpt_free_ccb(ccb); 2400 device_printf(dev, 2401 "Unable to allocate memory for READ LOG command\n"); 2402 goto completeall; 2403 } 2404 ataio->dxfer_len = 512; 2405 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2406 ataio->cmd.flags = CAM_ATAIO_48BIT; 2407 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2408 ataio->cmd.sector_count = 1; 2409 ataio->cmd.sector_count_exp = 0; 2410 ataio->cmd.lba_low = 0x10; 2411 ataio->cmd.lba_mid = 0; 2412 ataio->cmd.lba_mid_exp = 0; 2413 } else { 2414 /* REQUEST SENSE */ 2415 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2416 ccb->ccb_h.recovery_slot = i; 2417 ccb->ccb_h.func_code = XPT_SCSI_IO; 2418 ccb->ccb_h.flags = CAM_DIR_IN; 2419 ccb->ccb_h.status = 0; 2420 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2421 csio = &ccb->csio; 2422 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2423 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2424 csio->cdb_len = 6; 2425 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2426 csio->cdb_io.cdb_bytes[0] = 0x03; 2427 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2428 } 2429 /* Freeze SIM while doing recovery. */ 2430 ch->recoverycmd = 1; 2431 xpt_freeze_simq(ch->sim, 1); 2432 ahci_begin_transaction(dev, ccb); 2433 } 2434 2435 static void 2436 ahci_process_read_log(device_t dev, union ccb *ccb) 2437 { 2438 struct ahci_channel *ch = device_get_softc(dev); 2439 uint8_t *data; 2440 struct ata_res *res; 2441 int i; 2442 2443 ch->recoverycmd = 0; 2444 2445 data = ccb->ataio.data_ptr; 2446 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2447 (data[0] & 0x80) == 0) { 2448 for (i = 0; i < ch->numslots; i++) { 2449 if (!ch->hold[i]) 2450 continue; 2451 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2452 continue; 2453 if ((data[0] & 0x1F) == i) { 2454 res = &ch->hold[i]->ataio.res; 2455 res->status = data[2]; 2456 res->error = data[3]; 2457 res->lba_low = data[4]; 2458 res->lba_mid = data[5]; 2459 res->lba_high = data[6]; 2460 res->device = data[7]; 2461 res->lba_low_exp = data[8]; 2462 res->lba_mid_exp = data[9]; 2463 res->lba_high_exp = data[10]; 2464 res->sector_count = data[12]; 2465 res->sector_count_exp = data[13]; 2466 } else { 2467 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2468 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2469 } 2470 xpt_done(ch->hold[i]); 2471 ch->hold[i] = NULL; 2472 ch->numhslots--; 2473 } 2474 } else { 2475 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2476 device_printf(dev, "Error while READ LOG EXT\n"); 2477 else if ((data[0] & 0x80) == 0) { 2478 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2479 } 2480 for (i = 0; i < ch->numslots; i++) { 2481 if (!ch->hold[i]) 2482 continue; 2483 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2484 continue; 2485 xpt_done(ch->hold[i]); 2486 ch->hold[i] = NULL; 2487 ch->numhslots--; 2488 } 2489 } 2490 free(ccb->ataio.data_ptr, M_AHCI); 2491 xpt_free_ccb(ccb); 2492 xpt_release_simq(ch->sim, TRUE); 2493 } 2494 2495 static void 2496 ahci_process_request_sense(device_t dev, union ccb *ccb) 2497 { 2498 struct ahci_channel *ch = device_get_softc(dev); 2499 int i; 2500 2501 ch->recoverycmd = 0; 2502 2503 i = ccb->ccb_h.recovery_slot; 2504 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2505 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2506 } else { 2507 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2508 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2509 } 2510 xpt_done(ch->hold[i]); 2511 ch->hold[i] = NULL; 2512 ch->numhslots--; 2513 xpt_free_ccb(ccb); 2514 xpt_release_simq(ch->sim, TRUE); 2515 } 2516 2517 static void 2518 ahci_start(device_t dev, int fbs) 2519 { 2520 struct ahci_channel *ch = device_get_softc(dev); 2521 u_int32_t cmd; 2522 2523 /* Clear SATA error register */ 2524 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2525 /* Clear any interrupts pending on this channel */ 2526 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2527 /* Configure FIS-based switching if supported. */ 2528 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2529 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2530 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2531 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2532 } 2533 /* Start operations on this channel */ 2534 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2535 cmd &= ~AHCI_P_CMD_PMA; 2536 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2537 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2538 } 2539 2540 static void 2541 ahci_stop(device_t dev) 2542 { 2543 struct ahci_channel *ch = device_get_softc(dev); 2544 u_int32_t cmd; 2545 int timeout; 2546 2547 /* Kill all activity on this channel */ 2548 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2549 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2550 /* Wait for activity stop. */ 2551 timeout = 0; 2552 do { 2553 DELAY(10); 2554 if (timeout++ > 50000) { 2555 device_printf(dev, "stopping AHCI engine failed\n"); 2556 break; 2557 } 2558 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2559 ch->eslots = 0; 2560 } 2561 2562 static void 2563 ahci_clo(device_t dev) 2564 { 2565 struct ahci_channel *ch = device_get_softc(dev); 2566 u_int32_t cmd; 2567 int timeout; 2568 2569 /* Issue Command List Override if supported */ 2570 if (ch->caps & AHCI_CAP_SCLO) { 2571 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2572 cmd |= AHCI_P_CMD_CLO; 2573 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2574 timeout = 0; 2575 do { 2576 DELAY(10); 2577 if (timeout++ > 50000) { 2578 device_printf(dev, "executing CLO failed\n"); 2579 break; 2580 } 2581 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2582 } 2583 } 2584 2585 static void 2586 ahci_stop_fr(device_t dev) 2587 { 2588 struct ahci_channel *ch = device_get_softc(dev); 2589 u_int32_t cmd; 2590 int timeout; 2591 2592 /* Kill all FIS reception on this channel */ 2593 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2594 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2595 /* Wait for FIS reception stop. */ 2596 timeout = 0; 2597 do { 2598 DELAY(10); 2599 if (timeout++ > 50000) { 2600 device_printf(dev, "stopping AHCI FR engine failed\n"); 2601 break; 2602 } 2603 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2604 } 2605 2606 static void 2607 ahci_start_fr(device_t dev) 2608 { 2609 struct ahci_channel *ch = device_get_softc(dev); 2610 u_int32_t cmd; 2611 2612 /* Start FIS reception on this channel */ 2613 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2614 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2615 } 2616 2617 static int 2618 ahci_wait_ready(device_t dev, int t, int t0) 2619 { 2620 struct ahci_channel *ch = device_get_softc(dev); 2621 int timeout = 0; 2622 uint32_t val; 2623 2624 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2625 (ATA_S_BUSY | ATA_S_DRQ)) { 2626 if (timeout > t) { 2627 if (t != 0) { 2628 device_printf(dev, 2629 "AHCI reset: device not ready after %dms " 2630 "(tfd = %08x)\n", 2631 MAX(t, 0) + t0, val); 2632 } 2633 return (EBUSY); 2634 } 2635 DELAY(1000); 2636 timeout++; 2637 } 2638 if (bootverbose) 2639 device_printf(dev, "AHCI reset: device ready after %dms\n", 2640 timeout + t0); 2641 return (0); 2642 } 2643 2644 static void 2645 ahci_reset_to(void *arg) 2646 { 2647 device_t dev = arg; 2648 struct ahci_channel *ch = device_get_softc(dev); 2649 2650 if (ch->resetting == 0) 2651 return; 2652 ch->resetting--; 2653 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2654 (310 - ch->resetting) * 100) == 0) { 2655 ch->resetting = 0; 2656 ahci_start(dev, 1); 2657 xpt_release_simq(ch->sim, TRUE); 2658 return; 2659 } 2660 if (ch->resetting == 0) { 2661 ahci_clo(dev); 2662 ahci_start(dev, 1); 2663 xpt_release_simq(ch->sim, TRUE); 2664 return; 2665 } 2666 callout_schedule(&ch->reset_timer, hz / 10); 2667 } 2668 2669 static void 2670 ahci_reset(device_t dev) 2671 { 2672 struct ahci_channel *ch = device_get_softc(dev); 2673 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2674 int i; 2675 2676 xpt_freeze_simq(ch->sim, 1); 2677 if (bootverbose) 2678 device_printf(dev, "AHCI reset...\n"); 2679 /* Forget about previous reset. */ 2680 if (ch->resetting) { 2681 ch->resetting = 0; 2682 callout_stop(&ch->reset_timer); 2683 xpt_release_simq(ch->sim, TRUE); 2684 } 2685 /* Requeue freezed command. */ 2686 if (ch->frozen) { 2687 union ccb *fccb = ch->frozen; 2688 ch->frozen = NULL; 2689 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2690 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2691 xpt_freeze_devq(fccb->ccb_h.path, 1); 2692 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2693 } 2694 xpt_done(fccb); 2695 } 2696 /* Kill the engine and requeue all running commands. */ 2697 ahci_stop(dev); 2698 for (i = 0; i < ch->numslots; i++) { 2699 /* Do we have a running request on slot? */ 2700 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2701 continue; 2702 /* XXX; Commands in loading state. */ 2703 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2704 } 2705 for (i = 0; i < ch->numslots; i++) { 2706 if (!ch->hold[i]) 2707 continue; 2708 xpt_done(ch->hold[i]); 2709 ch->hold[i] = NULL; 2710 ch->numhslots--; 2711 } 2712 if (ch->toslots != 0) 2713 xpt_release_simq(ch->sim, TRUE); 2714 ch->eslots = 0; 2715 ch->toslots = 0; 2716 ch->wrongccs = 0; 2717 ch->fatalerr = 0; 2718 /* Tell the XPT about the event */ 2719 xpt_async(AC_BUS_RESET, ch->path, NULL); 2720 /* Disable port interrupts */ 2721 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2722 /* Reset and reconnect PHY, */ 2723 if (!ahci_sata_phy_reset(dev)) { 2724 if (bootverbose) 2725 device_printf(dev, 2726 "AHCI reset: device not found\n"); 2727 ch->devices = 0; 2728 /* Enable wanted port interrupts */ 2729 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2730 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2731 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2732 xpt_release_simq(ch->sim, TRUE); 2733 return; 2734 } 2735 if (bootverbose) 2736 device_printf(dev, "AHCI reset: device found\n"); 2737 /* Wait for clearing busy status. */ 2738 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2739 if (dumping) 2740 ahci_clo(dev); 2741 else 2742 ch->resetting = 310; 2743 } 2744 ch->devices = 1; 2745 /* Enable wanted port interrupts */ 2746 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2747 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2748 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2749 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2750 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2751 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2752 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2753 if (ch->resetting) 2754 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2755 else { 2756 ahci_start(dev, 1); 2757 xpt_release_simq(ch->sim, TRUE); 2758 } 2759 } 2760 2761 static int 2762 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2763 { 2764 struct ahci_channel *ch = device_get_softc(dev); 2765 u_int8_t *fis = &ctp->cfis[0]; 2766 2767 bzero(ctp->cfis, 16); 2768 fis[0] = 0x27; /* host to device */ 2769 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2770 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2771 fis[1] |= 0x80; 2772 fis[2] = ATA_PACKET_CMD; 2773 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2774 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2775 fis[3] = ATA_F_DMA; 2776 else { 2777 fis[5] = ccb->csio.dxfer_len; 2778 fis[6] = ccb->csio.dxfer_len >> 8; 2779 } 2780 fis[7] = ATA_D_LBA; 2781 fis[15] = ATA_A_4BIT; 2782 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2783 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2784 ctp->acmd, ccb->csio.cdb_len); 2785 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2786 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2787 fis[1] |= 0x80; 2788 fis[2] = ccb->ataio.cmd.command; 2789 fis[3] = ccb->ataio.cmd.features; 2790 fis[4] = ccb->ataio.cmd.lba_low; 2791 fis[5] = ccb->ataio.cmd.lba_mid; 2792 fis[6] = ccb->ataio.cmd.lba_high; 2793 fis[7] = ccb->ataio.cmd.device; 2794 fis[8] = ccb->ataio.cmd.lba_low_exp; 2795 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2796 fis[10] = ccb->ataio.cmd.lba_high_exp; 2797 fis[11] = ccb->ataio.cmd.features_exp; 2798 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2799 fis[12] = tag << 3; 2800 fis[13] = 0; 2801 } else { 2802 fis[12] = ccb->ataio.cmd.sector_count; 2803 fis[13] = ccb->ataio.cmd.sector_count_exp; 2804 } 2805 fis[15] = ATA_A_4BIT; 2806 } else { 2807 fis[15] = ccb->ataio.cmd.control; 2808 } 2809 return (20); 2810 } 2811 2812 static int 2813 ahci_sata_connect(struct ahci_channel *ch) 2814 { 2815 u_int32_t status; 2816 int timeout, found = 0; 2817 2818 /* Wait up to 100ms for "connect well" */ 2819 for (timeout = 0; timeout < 1000 ; timeout++) { 2820 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2821 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2822 found = 1; 2823 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2824 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2825 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2826 break; 2827 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2828 if (bootverbose) { 2829 device_printf(ch->dev, "SATA offline status=%08x\n", 2830 status); 2831 } 2832 return (0); 2833 } 2834 if (found == 0 && timeout >= 100) 2835 break; 2836 DELAY(100); 2837 } 2838 if (timeout >= 1000 || !found) { 2839 if (bootverbose) { 2840 device_printf(ch->dev, 2841 "SATA connect timeout time=%dus status=%08x\n", 2842 timeout * 100, status); 2843 } 2844 return (0); 2845 } 2846 if (bootverbose) { 2847 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2848 timeout * 100, status); 2849 } 2850 /* Clear SATA error register */ 2851 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2852 return (1); 2853 } 2854 2855 static int 2856 ahci_sata_phy_reset(device_t dev) 2857 { 2858 struct ahci_channel *ch = device_get_softc(dev); 2859 int sata_rev; 2860 uint32_t val; 2861 2862 if (ch->listening) { 2863 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2864 val |= AHCI_P_CMD_SUD; 2865 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2866 ch->listening = 0; 2867 } 2868 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2869 if (sata_rev == 1) 2870 val = ATA_SC_SPD_SPEED_GEN1; 2871 else if (sata_rev == 2) 2872 val = ATA_SC_SPD_SPEED_GEN2; 2873 else if (sata_rev == 3) 2874 val = ATA_SC_SPD_SPEED_GEN3; 2875 else 2876 val = 0; 2877 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2878 ATA_SC_DET_RESET | val | 2879 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2880 DELAY(1000); 2881 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2882 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2883 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2884 if (!ahci_sata_connect(ch)) { 2885 if (ch->caps & AHCI_CAP_SSS) { 2886 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2887 val &= ~AHCI_P_CMD_SUD; 2888 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2889 ch->listening = 1; 2890 } else if (ch->pm_level > 0) 2891 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2892 return (0); 2893 } 2894 return (1); 2895 } 2896 2897 static int 2898 ahci_check_ids(device_t dev, union ccb *ccb) 2899 { 2900 struct ahci_channel *ch = device_get_softc(dev); 2901 2902 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2903 ccb->ccb_h.status = CAM_TID_INVALID; 2904 xpt_done(ccb); 2905 return (-1); 2906 } 2907 if (ccb->ccb_h.target_lun != 0) { 2908 ccb->ccb_h.status = CAM_LUN_INVALID; 2909 xpt_done(ccb); 2910 return (-1); 2911 } 2912 return (0); 2913 } 2914 2915 static void 2916 ahciaction(struct cam_sim *sim, union ccb *ccb) 2917 { 2918 device_t dev, parent; 2919 struct ahci_channel *ch; 2920 2921 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2922 ccb->ccb_h.func_code)); 2923 2924 ch = (struct ahci_channel *)cam_sim_softc(sim); 2925 dev = ch->dev; 2926 switch (ccb->ccb_h.func_code) { 2927 /* Common cases first */ 2928 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2929 case XPT_SCSI_IO: 2930 if (ahci_check_ids(dev, ccb)) 2931 return; 2932 if (ch->devices == 0 || 2933 (ch->pm_present == 0 && 2934 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2935 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2936 break; 2937 } 2938 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2939 /* Check for command collision. */ 2940 if (ahci_check_collision(dev, ccb)) { 2941 /* Freeze command. */ 2942 ch->frozen = ccb; 2943 /* We have only one frozen slot, so freeze simq also. */ 2944 xpt_freeze_simq(ch->sim, 1); 2945 return; 2946 } 2947 ahci_begin_transaction(dev, ccb); 2948 return; 2949 case XPT_EN_LUN: /* Enable LUN as a target */ 2950 case XPT_TARGET_IO: /* Execute target I/O request */ 2951 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2952 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2953 case XPT_ABORT: /* Abort the specified CCB */ 2954 /* XXX Implement */ 2955 ccb->ccb_h.status = CAM_REQ_INVALID; 2956 break; 2957 case XPT_SET_TRAN_SETTINGS: 2958 { 2959 struct ccb_trans_settings *cts = &ccb->cts; 2960 struct ahci_device *d; 2961 2962 if (ahci_check_ids(dev, ccb)) 2963 return; 2964 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2965 d = &ch->curr[ccb->ccb_h.target_id]; 2966 else 2967 d = &ch->user[ccb->ccb_h.target_id]; 2968 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2969 d->revision = cts->xport_specific.sata.revision; 2970 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2971 d->mode = cts->xport_specific.sata.mode; 2972 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2973 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2974 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2975 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2976 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2977 ch->pm_present = cts->xport_specific.sata.pm_present; 2978 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2979 d->atapi = cts->xport_specific.sata.atapi; 2980 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2981 d->caps = cts->xport_specific.sata.caps; 2982 ccb->ccb_h.status = CAM_REQ_CMP; 2983 break; 2984 } 2985 case XPT_GET_TRAN_SETTINGS: 2986 /* Get default/user set transfer settings for the target */ 2987 { 2988 struct ccb_trans_settings *cts = &ccb->cts; 2989 struct ahci_device *d; 2990 uint32_t status; 2991 2992 if (ahci_check_ids(dev, ccb)) 2993 return; 2994 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2995 d = &ch->curr[ccb->ccb_h.target_id]; 2996 else 2997 d = &ch->user[ccb->ccb_h.target_id]; 2998 cts->protocol = PROTO_UNSPECIFIED; 2999 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 3000 cts->transport = XPORT_SATA; 3001 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 3002 cts->proto_specific.valid = 0; 3003 cts->xport_specific.sata.valid = 0; 3004 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 3005 (ccb->ccb_h.target_id == 15 || 3006 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 3007 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 3008 if (status & 0x0f0) { 3009 cts->xport_specific.sata.revision = 3010 (status & 0x0f0) >> 4; 3011 cts->xport_specific.sata.valid |= 3012 CTS_SATA_VALID_REVISION; 3013 } 3014 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 3015 if (ch->pm_level) { 3016 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 3017 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 3018 if (ch->caps2 & AHCI_CAP2_APST) 3019 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 3020 } 3021 if ((ch->caps & AHCI_CAP_SNCQ) && 3022 (ch->quirks & AHCI_Q_NOAA) == 0) 3023 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 3024 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 3025 cts->xport_specific.sata.caps &= 3026 ch->user[ccb->ccb_h.target_id].caps; 3027 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3028 } else { 3029 cts->xport_specific.sata.revision = d->revision; 3030 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 3031 cts->xport_specific.sata.caps = d->caps; 3032 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3033 } 3034 cts->xport_specific.sata.mode = d->mode; 3035 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 3036 cts->xport_specific.sata.bytecount = d->bytecount; 3037 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 3038 cts->xport_specific.sata.pm_present = ch->pm_present; 3039 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 3040 cts->xport_specific.sata.tags = d->tags; 3041 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 3042 cts->xport_specific.sata.atapi = d->atapi; 3043 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 3044 ccb->ccb_h.status = CAM_REQ_CMP; 3045 break; 3046 } 3047 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3048 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3049 ahci_reset(dev); 3050 ccb->ccb_h.status = CAM_REQ_CMP; 3051 break; 3052 case XPT_TERM_IO: /* Terminate the I/O process */ 3053 /* XXX Implement */ 3054 ccb->ccb_h.status = CAM_REQ_INVALID; 3055 break; 3056 case XPT_PATH_INQ: /* Path routing inquiry */ 3057 { 3058 struct ccb_pathinq *cpi = &ccb->cpi; 3059 3060 parent = device_get_parent(dev); 3061 cpi->version_num = 1; /* XXX??? */ 3062 cpi->hba_inquiry = PI_SDTR_ABLE; 3063 if (ch->caps & AHCI_CAP_SNCQ) 3064 cpi->hba_inquiry |= PI_TAG_ABLE; 3065 if (ch->caps & AHCI_CAP_SPM) 3066 cpi->hba_inquiry |= PI_SATAPM; 3067 cpi->target_sprt = 0; 3068 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 3069 cpi->hba_eng_cnt = 0; 3070 if (ch->caps & AHCI_CAP_SPM) 3071 cpi->max_target = 15; 3072 else 3073 cpi->max_target = 0; 3074 cpi->max_lun = 0; 3075 cpi->initiator_id = 0; 3076 cpi->bus_id = cam_sim_bus(sim); 3077 cpi->base_transfer_speed = 150000; 3078 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3079 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 3080 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3081 cpi->unit_number = cam_sim_unit(sim); 3082 cpi->transport = XPORT_SATA; 3083 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 3084 cpi->protocol = PROTO_ATA; 3085 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 3086 cpi->maxio = MAXPHYS; 3087 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 3088 if (pci_get_devid(parent) == 0x43801002) 3089 cpi->maxio = min(cpi->maxio, 128 * 512); 3090 cpi->hba_vendor = pci_get_vendor(parent); 3091 cpi->hba_device = pci_get_device(parent); 3092 cpi->hba_subvendor = pci_get_subvendor(parent); 3093 cpi->hba_subdevice = pci_get_subdevice(parent); 3094 cpi->ccb_h.status = CAM_REQ_CMP; 3095 break; 3096 } 3097 default: 3098 ccb->ccb_h.status = CAM_REQ_INVALID; 3099 break; 3100 } 3101 xpt_done(ccb); 3102 } 3103 3104 static void 3105 ahcipoll(struct cam_sim *sim) 3106 { 3107 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3108 3109 ahci_ch_intr(ch->dev); 3110 if (ch->resetting != 0 && 3111 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3112 ch->resetpolldiv = 1000; 3113 ahci_reset_to(ch->dev); 3114 } 3115 }
Cache object: 356ce349841fbc6967d6ae6e0d88deb7
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