Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ahci/ahci.h
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1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/10.1/sys/dev/ahci/ahci.h 261455 2014-02-04 03:36:42Z eadler $ 28 */ 29 30 /* ATA register defines */ 31 #define ATA_DATA 0 /* (RW) data */ 32 33 #define ATA_FEATURE 1 /* (W) feature */ 34 #define ATA_F_DMA 0x01 /* enable DMA */ 35 #define ATA_F_OVL 0x02 /* enable overlap */ 36 37 #define ATA_COUNT 2 /* (W) sector count */ 38 39 #define ATA_SECTOR 3 /* (RW) sector # */ 40 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 41 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43 #define ATA_D_LBA 0x40 /* use LBA addressing */ 44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45 46 #define ATA_COMMAND 7 /* (W) command */ 47 48 #define ATA_ERROR 8 /* (R) error */ 49 #define ATA_E_ILI 0x01 /* illegal length */ 50 #define ATA_E_NM 0x02 /* no media */ 51 #define ATA_E_ABORT 0x04 /* command aborted */ 52 #define ATA_E_MCR 0x08 /* media change request */ 53 #define ATA_E_IDNF 0x10 /* ID not found */ 54 #define ATA_E_MC 0x20 /* media changed */ 55 #define ATA_E_UNC 0x40 /* uncorrectable data */ 56 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 57 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58 59 #define ATA_IREASON 9 /* (R) interrupt reason */ 60 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 62 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 63 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 64 65 #define ATA_STATUS 10 /* (R) status */ 66 #define ATA_ALTSTAT 11 /* (R) alternate status */ 67 #define ATA_S_ERROR 0x01 /* error */ 68 #define ATA_S_INDEX 0x02 /* index */ 69 #define ATA_S_CORR 0x04 /* data corrected */ 70 #define ATA_S_DRQ 0x08 /* data request */ 71 #define ATA_S_DSC 0x10 /* drive seek completed */ 72 #define ATA_S_SERVICE 0x10 /* drive needs service */ 73 #define ATA_S_DWF 0x20 /* drive write fault */ 74 #define ATA_S_DMA 0x20 /* DMA ready */ 75 #define ATA_S_READY 0x40 /* drive ready */ 76 #define ATA_S_BUSY 0x80 /* busy */ 77 78 #define ATA_CONTROL 12 /* (W) control */ 79 #define ATA_A_IDS 0x02 /* disable interrupts */ 80 #define ATA_A_RESET 0x04 /* RESET controller */ 81 #define ATA_A_4BIT 0x08 /* 4 head bits */ 82 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 83 84 /* SATA register defines */ 85 #define ATA_SSTATUS 13 86 #define ATA_SS_DET_MASK 0x0000000f 87 #define ATA_SS_DET_NO_DEVICE 0x00000000 88 #define ATA_SS_DET_DEV_PRESENT 0x00000001 89 #define ATA_SS_DET_PHY_ONLINE 0x00000003 90 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 91 92 #define ATA_SS_SPD_MASK 0x000000f0 93 #define ATA_SS_SPD_NO_SPEED 0x00000000 94 #define ATA_SS_SPD_GEN1 0x00000010 95 #define ATA_SS_SPD_GEN2 0x00000020 96 #define ATA_SS_SPD_GEN3 0x00000040 97 98 #define ATA_SS_IPM_MASK 0x00000f00 99 #define ATA_SS_IPM_NO_DEVICE 0x00000000 100 #define ATA_SS_IPM_ACTIVE 0x00000100 101 #define ATA_SS_IPM_PARTIAL 0x00000200 102 #define ATA_SS_IPM_SLUMBER 0x00000600 103 #define ATA_SS_IPM_DEVSLEEP 0x00000800 104 105 #define ATA_SERROR 14 106 #define ATA_SE_DATA_CORRECTED 0x00000001 107 #define ATA_SE_COMM_CORRECTED 0x00000002 108 #define ATA_SE_DATA_ERR 0x00000100 109 #define ATA_SE_COMM_ERR 0x00000200 110 #define ATA_SE_PROT_ERR 0x00000400 111 #define ATA_SE_HOST_ERR 0x00000800 112 #define ATA_SE_PHY_CHANGED 0x00010000 113 #define ATA_SE_PHY_IERROR 0x00020000 114 #define ATA_SE_COMM_WAKE 0x00040000 115 #define ATA_SE_DECODE_ERR 0x00080000 116 #define ATA_SE_PARITY_ERR 0x00100000 117 #define ATA_SE_CRC_ERR 0x00200000 118 #define ATA_SE_HANDSHAKE_ERR 0x00400000 119 #define ATA_SE_LINKSEQ_ERR 0x00800000 120 #define ATA_SE_TRANSPORT_ERR 0x01000000 121 #define ATA_SE_UNKNOWN_FIS 0x02000000 122 #define ATA_SE_EXCHANGED 0x04000000 123 124 #define ATA_SCONTROL 15 125 #define ATA_SC_DET_MASK 0x0000000f 126 #define ATA_SC_DET_IDLE 0x00000000 127 #define ATA_SC_DET_RESET 0x00000001 128 #define ATA_SC_DET_DISABLE 0x00000004 129 130 #define ATA_SC_SPD_MASK 0x000000f0 131 #define ATA_SC_SPD_NO_SPEED 0x00000000 132 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 133 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 134 #define ATA_SC_SPD_SPEED_GEN3 0x00000040 135 136 #define ATA_SC_IPM_MASK 0x00000f00 137 #define ATA_SC_IPM_NONE 0x00000000 138 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 139 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 140 #define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 141 142 #define ATA_SACTIVE 16 143 144 #define AHCI_MAX_PORTS 32 145 #define AHCI_MAX_SLOTS 32 146 147 /* SATA AHCI v1.0 register defines */ 148 #define AHCI_CAP 0x00 149 #define AHCI_CAP_NPMASK 0x0000001f 150 #define AHCI_CAP_SXS 0x00000020 151 #define AHCI_CAP_EMS 0x00000040 152 #define AHCI_CAP_CCCS 0x00000080 153 #define AHCI_CAP_NCS 0x00001F00 154 #define AHCI_CAP_NCS_SHIFT 8 155 #define AHCI_CAP_PSC 0x00002000 156 #define AHCI_CAP_SSC 0x00004000 157 #define AHCI_CAP_PMD 0x00008000 158 #define AHCI_CAP_FBSS 0x00010000 159 #define AHCI_CAP_SPM 0x00020000 160 #define AHCI_CAP_SAM 0x00080000 161 #define AHCI_CAP_ISS 0x00F00000 162 #define AHCI_CAP_ISS_SHIFT 20 163 #define AHCI_CAP_SCLO 0x01000000 164 #define AHCI_CAP_SAL 0x02000000 165 #define AHCI_CAP_SALP 0x04000000 166 #define AHCI_CAP_SSS 0x08000000 167 #define AHCI_CAP_SMPS 0x10000000 168 #define AHCI_CAP_SSNTF 0x20000000 169 #define AHCI_CAP_SNCQ 0x40000000 170 #define AHCI_CAP_64BIT 0x80000000 171 172 #define AHCI_GHC 0x04 173 #define AHCI_GHC_AE 0x80000000 174 #define AHCI_GHC_MRSM 0x00000004 175 #define AHCI_GHC_IE 0x00000002 176 #define AHCI_GHC_HR 0x00000001 177 178 #define AHCI_IS 0x08 179 #define AHCI_PI 0x0c 180 #define AHCI_VS 0x10 181 182 #define AHCI_CCCC 0x14 183 #define AHCI_CCCC_TV_MASK 0xffff0000 184 #define AHCI_CCCC_TV_SHIFT 16 185 #define AHCI_CCCC_CC_MASK 0x0000ff00 186 #define AHCI_CCCC_CC_SHIFT 8 187 #define AHCI_CCCC_INT_MASK 0x000000f8 188 #define AHCI_CCCC_INT_SHIFT 3 189 #define AHCI_CCCC_EN 0x00000001 190 #define AHCI_CCCP 0x18 191 192 #define AHCI_EM_LOC 0x1C 193 #define AHCI_EM_CTL 0x20 194 #define AHCI_EM_MR 0x00000001 195 #define AHCI_EM_TM 0x00000100 196 #define AHCI_EM_RST 0x00000200 197 #define AHCI_EM_LED 0x00010000 198 #define AHCI_EM_SAFTE 0x00020000 199 #define AHCI_EM_SES2 0x00040000 200 #define AHCI_EM_SGPIO 0x00080000 201 #define AHCI_EM_SMB 0x01000000 202 #define AHCI_EM_XMT 0x02000000 203 #define AHCI_EM_ALHD 0x04000000 204 #define AHCI_EM_PM 0x08000000 205 206 #define AHCI_CAP2 0x24 207 #define AHCI_CAP2_BOH 0x00000001 208 #define AHCI_CAP2_NVMP 0x00000002 209 #define AHCI_CAP2_APST 0x00000004 210 #define AHCI_CAP2_SDS 0x00000008 211 #define AHCI_CAP2_SADM 0x00000010 212 #define AHCI_CAP2_DESO 0x00000020 213 214 #define AHCI_OFFSET 0x100 215 #define AHCI_STEP 0x80 216 217 #define AHCI_P_CLB 0x00 218 #define AHCI_P_CLBU 0x04 219 #define AHCI_P_FB 0x08 220 #define AHCI_P_FBU 0x0c 221 #define AHCI_P_IS 0x10 222 #define AHCI_P_IE 0x14 223 #define AHCI_P_IX_DHR 0x00000001 224 #define AHCI_P_IX_PS 0x00000002 225 #define AHCI_P_IX_DS 0x00000004 226 #define AHCI_P_IX_SDB 0x00000008 227 #define AHCI_P_IX_UF 0x00000010 228 #define AHCI_P_IX_DP 0x00000020 229 #define AHCI_P_IX_PC 0x00000040 230 #define AHCI_P_IX_MP 0x00000080 231 232 #define AHCI_P_IX_PRC 0x00400000 233 #define AHCI_P_IX_IPM 0x00800000 234 #define AHCI_P_IX_OF 0x01000000 235 #define AHCI_P_IX_INF 0x04000000 236 #define AHCI_P_IX_IF 0x08000000 237 #define AHCI_P_IX_HBD 0x10000000 238 #define AHCI_P_IX_HBF 0x20000000 239 #define AHCI_P_IX_TFE 0x40000000 240 #define AHCI_P_IX_CPD 0x80000000 241 242 #define AHCI_P_CMD 0x18 243 #define AHCI_P_CMD_ST 0x00000001 244 #define AHCI_P_CMD_SUD 0x00000002 245 #define AHCI_P_CMD_POD 0x00000004 246 #define AHCI_P_CMD_CLO 0x00000008 247 #define AHCI_P_CMD_FRE 0x00000010 248 #define AHCI_P_CMD_CCS_MASK 0x00001f00 249 #define AHCI_P_CMD_CCS_SHIFT 8 250 #define AHCI_P_CMD_ISS 0x00002000 251 #define AHCI_P_CMD_FR 0x00004000 252 #define AHCI_P_CMD_CR 0x00008000 253 #define AHCI_P_CMD_CPS 0x00010000 254 #define AHCI_P_CMD_PMA 0x00020000 255 #define AHCI_P_CMD_HPCP 0x00040000 256 #define AHCI_P_CMD_MPSP 0x00080000 257 #define AHCI_P_CMD_CPD 0x00100000 258 #define AHCI_P_CMD_ESP 0x00200000 259 #define AHCI_P_CMD_FBSCP 0x00400000 260 #define AHCI_P_CMD_APSTE 0x00800000 261 #define AHCI_P_CMD_ATAPI 0x01000000 262 #define AHCI_P_CMD_DLAE 0x02000000 263 #define AHCI_P_CMD_ALPE 0x04000000 264 #define AHCI_P_CMD_ASP 0x08000000 265 #define AHCI_P_CMD_ICC_MASK 0xf0000000 266 #define AHCI_P_CMD_NOOP 0x00000000 267 #define AHCI_P_CMD_ACTIVE 0x10000000 268 #define AHCI_P_CMD_PARTIAL 0x20000000 269 #define AHCI_P_CMD_SLUMBER 0x60000000 270 #define AHCI_P_CMD_DEVSLEEP 0x80000000 271 272 #define AHCI_P_TFD 0x20 273 #define AHCI_P_SIG 0x24 274 #define AHCI_P_SSTS 0x28 275 #define AHCI_P_SCTL 0x2c 276 #define AHCI_P_SERR 0x30 277 #define AHCI_P_SACT 0x34 278 #define AHCI_P_CI 0x38 279 #define AHCI_P_SNTF 0x3C 280 #define AHCI_P_FBS 0x40 281 #define AHCI_P_FBS_EN 0x00000001 282 #define AHCI_P_FBS_DEC 0x00000002 283 #define AHCI_P_FBS_SDE 0x00000004 284 #define AHCI_P_FBS_DEV 0x00000f00 285 #define AHCI_P_FBS_DEV_SHIFT 8 286 #define AHCI_P_FBS_ADO 0x0000f000 287 #define AHCI_P_FBS_ADO_SHIFT 12 288 #define AHCI_P_FBS_DWE 0x000f0000 289 #define AHCI_P_FBS_DWE_SHIFT 16 290 #define AHCI_P_DEVSLP 0x44 291 #define AHCI_P_DEVSLP_ADSE 0x00000001 292 #define AHCI_P_DEVSLP_DSP 0x00000002 293 #define AHCI_P_DEVSLP_DETO 0x000003fc 294 #define AHCI_P_DEVSLP_DETO_SHIFT 2 295 #define AHCI_P_DEVSLP_MDAT 0x00007c00 296 #define AHCI_P_DEVSLP_MDAT_SHIFT 10 297 #define AHCI_P_DEVSLP_DITO 0x01ff8000 298 #define AHCI_P_DEVSLP_DITO_SHIFT 15 299 #define AHCI_P_DEVSLP_DM 0x0e000000 300 #define AHCI_P_DEVSLP_DM_SHIFT 25 301 302 /* Just to be sure, if building as module. */ 303 #if MAXPHYS < 512 * 1024 304 #undef MAXPHYS 305 #define MAXPHYS 512 * 1024 306 #endif 307 /* Pessimistic prognosis on number of required S/G entries */ 308 #define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 309 /* Command list. 32 commands. First, 1Kbyte aligned. */ 310 #define AHCI_CL_OFFSET 0 311 #define AHCI_CL_SIZE 32 312 /* Command tables. Up to 32 commands, Each, 128byte aligned. */ 313 #define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 314 #define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 315 /* Total main work area. */ 316 #define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 317 318 struct ahci_dma_prd { 319 u_int64_t dba; 320 u_int32_t reserved; 321 u_int32_t dbc; /* 0 based */ 322 #define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 323 #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 324 #define AHCI_PRD_IPC (1U << 31) 325 } __packed; 326 327 struct ahci_cmd_tab { 328 u_int8_t cfis[64]; 329 u_int8_t acmd[32]; 330 u_int8_t reserved[32]; 331 struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES]; 332 } __packed; 333 334 struct ahci_cmd_list { 335 u_int16_t cmd_flags; 336 #define AHCI_CMD_ATAPI 0x0020 337 #define AHCI_CMD_WRITE 0x0040 338 #define AHCI_CMD_PREFETCH 0x0080 339 #define AHCI_CMD_RESET 0x0100 340 #define AHCI_CMD_BIST 0x0200 341 #define AHCI_CMD_CLR_BUSY 0x0400 342 343 u_int16_t prd_length; /* PRD entries */ 344 u_int32_t bytecount; 345 u_int64_t cmd_table_phys; /* 128byte aligned */ 346 } __packed; 347 348 /* misc defines */ 349 #define ATA_IRQ_RID 0 350 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 351 352 struct ata_dmaslot { 353 bus_dmamap_t data_map; /* data DMA map */ 354 int nsegs; /* Number of segs loaded */ 355 }; 356 357 /* structure holding DMA related information */ 358 struct ata_dma { 359 bus_dma_tag_t work_tag; /* workspace DMA tag */ 360 bus_dmamap_t work_map; /* workspace DMA map */ 361 uint8_t *work; /* workspace */ 362 bus_addr_t work_bus; /* bus address of work */ 363 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 364 bus_dmamap_t rfis_map; /* RFIS list DMA map */ 365 uint8_t *rfis; /* FIS receive area */ 366 bus_addr_t rfis_bus; /* bus address of rfis */ 367 bus_dma_tag_t data_tag; /* data DMA tag */ 368 }; 369 370 enum ahci_slot_states { 371 AHCI_SLOT_EMPTY, 372 AHCI_SLOT_LOADING, 373 AHCI_SLOT_RUNNING, 374 AHCI_SLOT_EXECUTING 375 }; 376 377 struct ahci_slot { 378 device_t dev; /* Device handle */ 379 u_int8_t slot; /* Number of this slot */ 380 enum ahci_slot_states state; /* Slot state */ 381 union ccb *ccb; /* CCB occupying slot */ 382 struct ata_dmaslot dma; /* DMA data of this slot */ 383 struct callout timeout; /* Execution timeout */ 384 }; 385 386 struct ahci_device { 387 int revision; 388 int mode; 389 u_int bytecount; 390 u_int atapi; 391 u_int tags; 392 u_int caps; 393 }; 394 395 struct ahci_led { 396 device_t dev; /* Device handle */ 397 struct cdev *led; 398 uint8_t num; /* Number of this led */ 399 uint8_t state; /* State of this led */ 400 }; 401 402 #define AHCI_NUM_LEDS 3 403 404 /* structure describing an ATA channel */ 405 struct ahci_channel { 406 device_t dev; /* Device handle */ 407 int unit; /* Physical channel */ 408 struct resource *r_mem; /* Memory of this channel */ 409 struct resource *r_irq; /* Interrupt of this channel */ 410 void *ih; /* Interrupt handle */ 411 struct ata_dma dma; /* DMA data */ 412 struct cam_sim *sim; 413 struct cam_path *path; 414 uint32_t caps; /* Controller capabilities */ 415 uint32_t caps2; /* Controller capabilities */ 416 uint32_t chcaps; /* Channel capabilities */ 417 uint32_t chscaps; /* Channel sleep capabilities */ 418 int quirks; 419 int numslots; /* Number of present slots */ 420 int pm_level; /* power management level */ 421 422 struct ahci_slot slot[AHCI_MAX_SLOTS]; 423 union ccb *hold[AHCI_MAX_SLOTS]; 424 struct mtx mtx; /* state lock */ 425 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */ 426 int batch; /* doneq is in use */ 427 int devices; /* What is present */ 428 int pm_present; /* PM presence reported */ 429 int fbs_enabled; /* FIS-based switching enabled */ 430 uint32_t oslots; /* Occupied slots */ 431 uint32_t rslots; /* Running slots */ 432 uint32_t aslots; /* Slots with atomic commands */ 433 uint32_t eslots; /* Slots in error */ 434 uint32_t toslots; /* Slots in timeout */ 435 int numrslots; /* Number of running slots */ 436 int numrslotspd[16];/* Number of running slots per dev */ 437 int numtslots; /* Number of tagged slots */ 438 int numtslotspd[16];/* Number of tagged slots per dev */ 439 int numhslots; /* Number of held slots */ 440 int recoverycmd; /* Our READ LOG active */ 441 int fatalerr; /* Fatal error happend */ 442 int lastslot; /* Last used slot */ 443 int taggedtarget; /* Last tagged target */ 444 int resetting; /* Hard-reset in progress. */ 445 int resetpolldiv; /* Hard-reset poll divider. */ 446 int listening; /* SUD bit is cleared. */ 447 int wrongccs; /* CCS field in CMD was wrong */ 448 union ccb *frozen; /* Frozen command */ 449 struct callout pm_timer; /* Power management events */ 450 struct callout reset_timer; /* Hard-reset timeout */ 451 452 struct ahci_device user[16]; /* User-specified settings */ 453 struct ahci_device curr[16]; /* Current settings */ 454 }; 455 456 struct ahci_enclosure { 457 device_t dev; /* Device handle */ 458 struct resource *r_memc; /* Control register */ 459 struct resource *r_memt; /* Transmit buffer */ 460 struct resource *r_memr; /* Recieve buffer */ 461 struct cam_sim *sim; 462 struct cam_path *path; 463 struct mtx mtx; /* state lock */ 464 struct ahci_led leds[AHCI_MAX_PORTS * 3]; 465 uint32_t capsem; /* Controller capabilities */ 466 uint8_t status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */ 467 int quirks; 468 int channels; 469 int ichannels; 470 }; 471 472 /* structure describing a AHCI controller */ 473 struct ahci_controller { 474 device_t dev; 475 bus_dma_tag_t dma_tag; 476 int r_rid; 477 struct resource *r_mem; 478 struct rman sc_iomem; 479 struct ahci_controller_irq { 480 struct ahci_controller *ctlr; 481 struct resource *r_irq; 482 void *handle; 483 int r_irq_rid; 484 int mode; 485 #define AHCI_IRQ_MODE_ALL 0 486 #define AHCI_IRQ_MODE_AFTER 1 487 #define AHCI_IRQ_MODE_ONE 2 488 } irqs[16]; 489 uint32_t caps; /* Controller capabilities */ 490 uint32_t caps2; /* Controller capabilities */ 491 uint32_t capsem; /* Controller capabilities */ 492 uint32_t emloc; /* EM buffer location */ 493 int quirks; 494 int numirqs; 495 int channels; 496 int ichannels; 497 int ccc; /* CCC timeout */ 498 int cccv; /* CCC vector */ 499 int direct; /* Direct command completion */ 500 int msi; /* MSI interupts */ 501 struct { 502 void (*function)(void *); 503 void *argument; 504 } interrupt[AHCI_MAX_PORTS]; 505 }; 506 507 enum ahci_err_type { 508 AHCI_ERR_NONE, /* No error */ 509 AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 510 AHCI_ERR_INNOCENT, /* Innocent victim. */ 511 AHCI_ERR_TFE, /* Task File Error. */ 512 AHCI_ERR_SATA, /* SATA error. */ 513 AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 514 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 515 * until READ LOG executed to reveal error. */ 516 }; 517 518 /* macros to hide busspace uglyness */ 519 #define ATA_INB(res, offset) \ 520 bus_read_1((res), (offset)) 521 #define ATA_INW(res, offset) \ 522 bus_read_2((res), (offset)) 523 #define ATA_INL(res, offset) \ 524 bus_read_4((res), (offset)) 525 #define ATA_INSW(res, offset, addr, count) \ 526 bus_read_multi_2((res), (offset), (addr), (count)) 527 #define ATA_INSW_STRM(res, offset, addr, count) \ 528 bus_read_multi_stream_2((res), (offset), (addr), (count)) 529 #define ATA_INSL(res, offset, addr, count) \ 530 bus_read_multi_4((res), (offset), (addr), (count)) 531 #define ATA_INSL_STRM(res, offset, addr, count) \ 532 bus_read_multi_stream_4((res), (offset), (addr), (count)) 533 #define ATA_OUTB(res, offset, value) \ 534 bus_write_1((res), (offset), (value)) 535 #define ATA_OUTW(res, offset, value) \ 536 bus_write_2((res), (offset), (value)) 537 #define ATA_OUTL(res, offset, value) \ 538 bus_write_4((res), (offset), (value)) 539 #define ATA_OUTSW(res, offset, addr, count) \ 540 bus_write_multi_2((res), (offset), (addr), (count)) 541 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 542 bus_write_multi_stream_2((res), (offset), (addr), (count)) 543 #define ATA_OUTSL(res, offset, addr, count) \ 544 bus_write_multi_4((res), (offset), (addr), (count)) 545 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 546 bus_write_multi_stream_4((res), (offset), (addr), (count))
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