The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/aic/aic6360reg.h

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    1 /*-
    2  * Copyright (c) 1994 Charles Hannum.
    3  * Copyright (c) 1994 Jarle Greipsland.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Jarle Greipsland
   17  * 4. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  * 
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   22  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   23  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   24  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   25  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   26  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
   28  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   29  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30  * POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 #define SCSISEQ         0x00    /* SCSI sequence control */
   36 #define SXFRCTL0        0x01    /* SCSI transfer control 0 */
   37 #define SXFRCTL1        0x02    /* SCSI transfer control 1 */
   38 #define SCSISIGI        0x03    /* SCSI signal in */
   39 #define SCSISIGO        0x03    /* SCSI signal out */
   40 #define SCSIRATE        0x04    /* SCSI rate control */
   41 #define SCSIID          0x05    /* SCSI ID */
   42 #define SELID           0x05    /* Selection/Reselection ID */
   43 #define SCSIDAT         0x06    /* SCSI Latched Data */
   44 #define SCSIBUS         0x07    /* SCSI Data Bus*/
   45 #define STCNT0          0x08    /* SCSI transfer count */
   46 #define STCNT1          0x09
   47 #define STCNT2          0x0a
   48 #define CLRSINT0        0x0b    /* Clear SCSI interrupts 0 */
   49 #define SSTAT0          0x0b    /* SCSI interrupt status 0 */
   50 #define CLRSINT1        0x0c    /* Clear SCSI interrupts 1 */
   51 #define SSTAT1          0x0c    /* SCSI status 1 */
   52 #define SSTAT2          0x0d    /* SCSI status 2 */
   53 #define SCSITEST        0x0e    /* SCSI test control */
   54 #define SSTAT3          0x0e    /* SCSI status 3 */
   55 #define CLRSERR         0x0f    /* Clear SCSI errors */
   56 #define SSTAT4          0x0f    /* SCSI status 4 */
   57 #define SIMODE0         0x10    /* SCSI interrupt mode 0 */
   58 #define SIMODE1         0x11    /* SCSI interrupt mode 1 */
   59 #define DMACNTRL0       0x12    /* DMA control 0 */
   60 #define DMACNTRL1       0x13    /* DMA control 1 */
   61 #define DMASTAT         0x14    /* DMA status */
   62 #define FIFOSTAT        0x15    /* FIFO status */
   63 #define DMADATA         0x16    /* DMA data */
   64 #define DMADATAL        0x16    /* DMA data low byte */
   65 #define DMADATAH        0x17    /* DMA data high byte */
   66 #define BRSTCNTRL       0x18    /* Burst Control */
   67 #define DMADATALONG     0x18
   68 #define PORTA           0x1a    /* Port A */
   69 #define PORTB           0x1b    /* Port B */
   70 #define REV             0x1c    /* Revision (001 for 6360) */
   71 #define STACK           0x1d    /* Stack */
   72 #define TEST            0x1e    /* Test register */
   73 #define ID              0x1f    /* ID register */
   74 
   75 #define IDSTRING_AIC6360  "(C)1991ADAPTECAIC6360           "
   76 #define IDSTRING_AIC6370  "(C)1994ADAPTECAIC6370"
   77 #define IDSTRING_GM82C700 "(C)1993 GoldStarGM82C700        "
   78 
   79 /* What all the bits do */
   80 
   81 /* SCSISEQ */
   82 #define TEMODEO         0x80
   83 #define ENSELO          0x40
   84 #define ENSELI          0x20
   85 #define ENRESELI        0x10
   86 #define ENAUTOATNO      0x08
   87 #define ENAUTOATNI      0x04
   88 #define ENAUTOATNP      0x02
   89 #define SCSIRSTO        0x01
   90 
   91 /* SXFRCTL0 */
   92 #define SCSIEN          0x80
   93 #define DMAEN           0x40
   94 #define CHEN            0x20
   95 #define CLRSTCNT        0x10
   96 #define SPIOEN          0x08
   97 #define CLRCH           0x02
   98 
   99 /* SXFRCTL1 */
  100 #define BITBUCKET       0x80
  101 #define SWRAPEN         0x40
  102 #define ENSPCHK         0x20
  103 #define STIMESEL1       0x10
  104 #define STIMESEL0       0x08
  105 #define STIMO_256ms     0x00
  106 #define STIMO_128ms     0x08
  107 #define STIMO_64ms      0x10
  108 #define STIMO_32ms      0x18
  109 #define ENSTIMER        0x04
  110 #define BYTEALIGN       0x02
  111 
  112 /* SCSISIGI */
  113 #define CDI             0x80
  114 #define IOI             0x40
  115 #define MSGI            0x20
  116 #define ATNI            0x10
  117 #define SELI            0x08
  118 #define BSYI            0x04
  119 #define REQI            0x02
  120 #define ACKI            0x01
  121 
  122 /* Important! The 3 most significant bits of this register, in initiator mode,
  123  * represents the "expected" SCSI bus phase and can be used to trigger phase
  124  * mismatch and phase change interrupts.  But more important:  If there is a
  125  * phase mismatch the chip will not transfer any data!  This is actually a nice
  126  * feature as it gives us a bit more control over what is happening when we are
  127  * bursting data (in) through the FIFOs and the phase suddenly changes from
  128  * DATA IN to STATUS or MESSAGE IN.  The transfer will stop and wait for the
  129  * proper phase to be set in this register instead of dumping the bits into the
  130  * FIFOs.
  131  */
  132 /* SCSISIGO */
  133 #define CDO             0x80
  134 #define IOO             0x40
  135 #define MSGO            0x20
  136 #define ATNO            0x10
  137 #define SELO            0x08
  138 #define BSYO            0x04
  139 #define REQO            0x02
  140 #define ACKO            0x01
  141 
  142 /* Information transfer phases */
  143 #define PH_DATAOUT      (0)
  144 #define PH_DATAIN       (IOI)
  145 #define PH_CMD          (CDI)
  146 #define PH_STAT         (CDI|IOI)
  147 #define PH_MSGOUT       (MSGI|CDI)
  148 #define PH_MSGIN        (MSGI|CDI|IOI)
  149 #define PH_MASK         (MSGI|CDI|IOI)
  150 
  151 /* SCSIRATE */
  152 #define SXFR2           0x40
  153 #define SXFR1           0x20
  154 #define SXFR0           0x10
  155 #define SOFS3           0x08
  156 #define SOFS2           0x04
  157 #define SOFS1           0x02
  158 #define SOFS0           0x01
  159 
  160 /* SCSI ID */
  161 #define OID2            0x40
  162 #define OID1            0x20
  163 #define OID0            0x10
  164 #define OID_S           4       /* shift value */
  165 #define TID2            0x04
  166 #define TID1            0x02
  167 #define TID0            0x01
  168 #define SCSI_ID_MASK    0x7
  169 
  170 /* SCSI selection/reselection ID (both target *and* initiator) */
  171 #define SELID7          0x80
  172 #define SELID6          0x40
  173 #define SELID5          0x20
  174 #define SELID4          0x10
  175 #define SELID3          0x08
  176 #define SELID2          0x04
  177 #define SELID1          0x02
  178 #define SELID0          0x01
  179 
  180 /* CLRSINT0                      Clears what? (interrupt and/or status bit) */
  181 #define SETSDONE        0x80
  182 #define CLRSELDO        0x40    /* I */
  183 #define CLRSELDI        0x20    /* I+ */
  184 #define CLRSELINGO      0x10    /* I */
  185 #define CLRSWRAP        0x08    /* I+S */
  186 #define CLRSDONE        0x04    /* I+S */
  187 #define CLRSPIORDY      0x02    /* I */
  188 #define CLRDMADONE      0x01    /* I */
  189 
  190 /* SSTAT0                          Howto clear */
  191 #define TARGET          0x80
  192 #define SELDO           0x40    /* Selfclearing */
  193 #define SELDI           0x20    /* Selfclearing when CLRSELDI is set */
  194 #define SELINGO         0x10    /* Selfclearing */
  195 #define SWRAP           0x08    /* CLRSWAP */
  196 #define SDONE           0x04    /* Not used in initiator mode */
  197 #define SPIORDY         0x02    /* Selfclearing (op on SCSIDAT) */
  198 #define DMADONE         0x01    /* Selfclearing (all FIFOs empty & T/C */
  199 
  200 /* CLRSINT1                      Clears what? */
  201 #define CLRSELTIMO      0x80    /* I+S */
  202 #define CLRATNO         0x40
  203 #define CLRSCSIRSTI     0x20    /* I+S */
  204 #define CLRBUSFREE      0x08    /* I+S */
  205 #define CLRSCSIPERR     0x04    /* I+S */
  206 #define CLRPHASECHG     0x02    /* I+S */
  207 #define CLRREQINIT      0x01    /* I+S */
  208 
  209 /* SSTAT1                       How to clear?  When set?*/
  210 #define SELTO           0x80    /* C            select out timeout */
  211 #define ATNTARG         0x40    /* Not used in initiator mode */
  212 #define SCSIRSTI        0x20    /* C            RST asserted */
  213 #define PHASEMIS        0x10    /* Selfclearing */
  214 #define BUSFREE         0x08    /* C            bus free condition */
  215 #define SCSIPERR        0x04    /* C            parity error on inbound data */
  216 #define PHASECHG        0x02    /* C         phase in SCSISIGI doesn't match */
  217 #define REQINIT         0x01    /* C or ACK     asserting edge of REQ */
  218 
  219 /* SSTAT2 */
  220 #define SOFFSET         0x20
  221 #define SEMPTY          0x10
  222 #define SFULL           0x08
  223 #define SFCNT2          0x04
  224 #define SFCNT1          0x02
  225 #define SFCNT0          0x01
  226 
  227 /* SCSITEST */
  228 #define SCTESTU         0x08
  229 #define SCTESTD         0x04
  230 #define STCTEST         0x01
  231 
  232 /* SSTAT3 */
  233 #define SCSICNT3        0x80
  234 #define SCSICNT2        0x40
  235 #define SCSICNT1        0x20
  236 #define SCSICNT0        0x10
  237 #define OFFCNT3         0x08
  238 #define OFFCNT2         0x04
  239 #define OFFCNT1         0x02
  240 #define OFFCNT0         0x01
  241 
  242 /* CLRSERR */
  243 #define CLRSYNCERR      0x04
  244 #define CLRFWERR        0x02
  245 #define CLRFRERR        0x01
  246 
  247 /* SSTAT4 */
  248 #define SYNCERR         0x04
  249 #define FWERR           0x02
  250 #define FRERR           0x01
  251 
  252 /* SIMODE0 */
  253 #define ENSELDO         0x40
  254 #define ENSELDI         0x20
  255 #define ENSELINGO       0x10
  256 #define ENSWRAP         0x08
  257 #define ENSDONE         0x04
  258 #define ENSPIORDY       0x02
  259 #define ENDMADONE       0x01
  260 
  261 /* SIMODE1 */
  262 #define ENSELTIMO       0x80
  263 #define ENATNTARG       0x40
  264 #define ENSCSIRST       0x20
  265 #define ENPHASEMIS      0x10
  266 #define ENBUSFREE       0x08
  267 #define ENSCSIPERR      0x04
  268 #define ENPHASECHG      0x02
  269 #define ENREQINIT       0x01
  270 
  271 /* DMACNTRL0 */
  272 #define ENDMA           0x80
  273 #define B8MODE          0x40
  274 #define DMA             0x20
  275 #define DWORDPIO        0x10
  276 #define WRITE           0x08
  277 #define INTEN           0x04
  278 #define RSTFIFO         0x02
  279 #define SWINT           0x01
  280 
  281 /* DMACNTRL1 */
  282 #define PWRDWN          0x80
  283 #define ENSTK32         0x40
  284 #define STK4            0x10
  285 #define STK3            0x08
  286 #define STK2            0x04
  287 #define STK1            0x02
  288 #define STK0            0x01
  289 
  290 /* DMASTAT */
  291 #define ATDONE          0x80
  292 #define WORDRDY         0x40
  293 #define INTSTAT         0x20
  294 #define DFIFOFULL       0x10
  295 #define DFIFOEMP        0x08
  296 #define DFIFOHF         0x04
  297 #define DWORDRDY        0x02
  298 
  299 /* BRSTCNTRL */
  300 #define BON3            0x80
  301 #define BON2            0x40
  302 #define BON1            0x20
  303 #define BON0            0x10
  304 #define BOFF3           0x08
  305 #define BOFF2           0x04
  306 #define BOFF1           0x02
  307 #define BOFF0           0x01
  308 
  309 /* TEST */
  310 #define BOFFTMR         0x40
  311 #define BONTMR          0x20
  312 #define STCNTH          0x10
  313 #define STCNTM          0x08
  314 #define STCNTL          0x04
  315 #define SCSIBLK         0x02
  316 #define DMABLK          0x01
  317 
  318 /* PORTA */
  319 #define PORTA_ID(a)     ((a) & 7)
  320 #define PORTA_IRQ(a)    ((((a) >> 3) & 3) + 9)
  321 #define PORTA_DRQ(a)    ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0)
  322 #define PORTA_PARITY(a) ((a) & 0x80)
  323 
  324 /* PORTB */
  325 #define PORTB_EXTTRAN(b)((b) & 1)
  326 #define PORTB_DISC(b)   ((b) & 4)
  327 #define PORTB_SYNC(b)   ((b) & 8)
  328 #define PORTB_FSYNC(b)  ((b) & 0x10)
  329 #define PORTB_BOOT(b)   ((b) & 0x40)
  330 #define PORTB_DMA(b)    ((b) & 0x80)
  331 
  332 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */
  333 #define EISA_BRST_TIM   ((15<<4) + 1)   /* 15us on, 1us off */
  334 
  335 #define FIFOSIZE        128

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