1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
41 */
42
43 #ifdef __linux__
44 #include "aic79xx_osm.h"
45 #include "aic79xx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
47 #else
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD: releng/5.3/sys/dev/aic7xxx/aic79xx.c 134644 2004-09-02 15:33:15Z gibbs $");
50 #include <dev/aic7xxx/aic79xx_osm.h>
51 #include <dev/aic7xxx/aic79xx_inline.h>
52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
53 #endif
54
55 /******************************** Globals *************************************/
56 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
57 uint32_t ahd_attach_to_HostRAID_controllers = 1;
58
59 /***************************** Lookup Tables **********************************/
60 char *ahd_chip_names[] =
61 {
62 "NONE",
63 "aic7901",
64 "aic7902",
65 "aic7901A"
66 };
67 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
68
69 /*
70 * Hardware error codes.
71 */
72 struct ahd_hard_error_entry {
73 uint8_t errno;
74 char *errmesg;
75 };
76
77 static struct ahd_hard_error_entry ahd_hard_errors[] = {
78 { DSCTMOUT, "Discard Timer has timed out" },
79 { ILLOPCODE, "Illegal Opcode in sequencer program" },
80 { SQPARERR, "Sequencer Parity Error" },
81 { DPARERR, "Data-path Parity Error" },
82 { MPARERR, "Scratch or SCB Memory Parity Error" },
83 { CIOPARERR, "CIOBUS Parity Error" },
84 };
85 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
86
87 static struct ahd_phase_table_entry ahd_phase_table[] =
88 {
89 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
90 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
91 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
92 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
93 { P_COMMAND, MSG_NOOP, "in Command phase" },
94 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
95 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
96 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
97 { P_BUSFREE, MSG_NOOP, "while idle" },
98 { 0, MSG_NOOP, "in unknown phase" }
99 };
100
101 /*
102 * In most cases we only wish to itterate over real phases, so
103 * exclude the last element from the count.
104 */
105 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
106
107 /* Our Sequencer Program */
108 #include "aic79xx_seq.h"
109
110 /**************************** Function Declarations ***************************/
111 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
112 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
113 u_int lqistat1);
114 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
115 u_int busfreetime);
116 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
117 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
118 static void ahd_force_renegotiation(struct ahd_softc *ahd,
119 struct ahd_devinfo *devinfo);
120
121 static struct ahd_tmode_tstate*
122 ahd_alloc_tstate(struct ahd_softc *ahd,
123 u_int scsi_id, char channel);
124 #ifdef AHD_TARGET_MODE
125 static void ahd_free_tstate(struct ahd_softc *ahd,
126 u_int scsi_id, char channel, int force);
127 #endif
128 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
129 struct ahd_initiator_tinfo *,
130 u_int *period,
131 u_int *ppr_options,
132 role_t role);
133 static void ahd_update_neg_table(struct ahd_softc *ahd,
134 struct ahd_devinfo *devinfo,
135 struct ahd_transinfo *tinfo);
136 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
137 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
138 struct ahd_devinfo *devinfo);
139 static void ahd_scb_devinfo(struct ahd_softc *ahd,
140 struct ahd_devinfo *devinfo,
141 struct scb *scb);
142 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
143 struct ahd_devinfo *devinfo,
144 struct scb *scb);
145 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
146 struct ahd_devinfo *devinfo);
147 static void ahd_construct_sdtr(struct ahd_softc *ahd,
148 struct ahd_devinfo *devinfo,
149 u_int period, u_int offset);
150 static void ahd_construct_wdtr(struct ahd_softc *ahd,
151 struct ahd_devinfo *devinfo,
152 u_int bus_width);
153 static void ahd_construct_ppr(struct ahd_softc *ahd,
154 struct ahd_devinfo *devinfo,
155 u_int period, u_int offset,
156 u_int bus_width, u_int ppr_options);
157 static void ahd_clear_msg_state(struct ahd_softc *ahd);
158 static void ahd_handle_message_phase(struct ahd_softc *ahd);
159 typedef enum {
160 AHDMSG_1B,
161 AHDMSG_2B,
162 AHDMSG_EXT
163 } ahd_msgtype;
164 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
165 u_int msgval, int full);
166 static int ahd_parse_msg(struct ahd_softc *ahd,
167 struct ahd_devinfo *devinfo);
168 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
169 struct ahd_devinfo *devinfo);
170 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
171 struct ahd_devinfo *devinfo);
172 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
173 static void ahd_handle_devreset(struct ahd_softc *ahd,
174 struct ahd_devinfo *devinfo,
175 u_int lun, cam_status status,
176 char *message, int verbose_level);
177 #if AHD_TARGET_MODE
178 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
179 struct ahd_devinfo *devinfo,
180 struct scb *scb);
181 #endif
182
183 static u_int ahd_sglist_size(struct ahd_softc *ahd);
184 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
185 static bus_dmamap_callback_t
186 ahd_dmamap_cb;
187 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
188 static int ahd_init_scbdata(struct ahd_softc *ahd);
189 static void ahd_fini_scbdata(struct ahd_softc *ahd);
190 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
191 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
192 static void ahd_add_col_list(struct ahd_softc *ahd,
193 struct scb *scb, u_int col_idx);
194 static void ahd_rem_col_list(struct ahd_softc *ahd,
195 struct scb *scb);
196 static void ahd_chip_init(struct ahd_softc *ahd);
197 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
198 struct scb *prev_scb,
199 struct scb *scb);
200 static int ahd_qinfifo_count(struct ahd_softc *ahd);
201 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
202 char channel, int lun, u_int tag,
203 role_t role, uint32_t status,
204 ahd_search_action action,
205 u_int *list_head, u_int *list_tail,
206 u_int tid);
207 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
208 u_int tid_prev, u_int tid_cur,
209 u_int tid_next);
210 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
211 u_int scbid);
212 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
213 u_int prev, u_int next, u_int tid);
214 static void ahd_reset_current_bus(struct ahd_softc *ahd);
215 static ahd_callback_t ahd_reset_poll;
216 static ahd_callback_t ahd_stat_timer;
217 #ifdef AHD_DUMP_SEQ
218 static void ahd_dumpseq(struct ahd_softc *ahd);
219 #endif
220 static void ahd_loadseq(struct ahd_softc *ahd);
221 static int ahd_check_patch(struct ahd_softc *ahd,
222 struct patch **start_patch,
223 u_int start_instr, u_int *skip_addr);
224 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
225 u_int address);
226 static void ahd_download_instr(struct ahd_softc *ahd,
227 u_int instrptr, uint8_t *dconsts);
228 static int ahd_probe_stack_size(struct ahd_softc *ahd);
229 static int ahd_other_scb_timeout(struct ahd_softc *ahd,
230 struct scb *scb,
231 struct scb *other_scb);
232 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
233 struct scb *scb);
234 static void ahd_run_data_fifo(struct ahd_softc *ahd,
235 struct scb *scb);
236
237 #ifdef AHD_TARGET_MODE
238 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
239 struct ahd_tmode_lstate *lstate,
240 u_int initiator_id,
241 u_int event_type,
242 u_int event_arg);
243 static void ahd_update_scsiid(struct ahd_softc *ahd,
244 u_int targid_mask);
245 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
246 struct target_cmd *cmd);
247 #endif
248
249 /******************************** Private Inlines *****************************/
250 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
251 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
252 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
253
254 static __inline void
255 ahd_assert_atn(struct ahd_softc *ahd)
256 {
257 ahd_outb(ahd, SCSISIGO, ATNO);
258 }
259
260 /*
261 * Determine if the current connection has a packetized
262 * agreement. This does not necessarily mean that we
263 * are currently in a packetized transfer. We could
264 * just as easily be sending or receiving a message.
265 */
266 static __inline int
267 ahd_currently_packetized(struct ahd_softc *ahd)
268 {
269 ahd_mode_state saved_modes;
270 int packetized;
271
272 saved_modes = ahd_save_modes(ahd);
273 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
274 /*
275 * The packetized bit refers to the last
276 * connection, not the current one. Check
277 * for non-zero LQISTATE instead.
278 */
279 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
280 packetized = ahd_inb(ahd, LQISTATE) != 0;
281 } else {
282 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
283 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
284 }
285 ahd_restore_modes(ahd, saved_modes);
286 return (packetized);
287 }
288
289 static __inline int
290 ahd_set_active_fifo(struct ahd_softc *ahd)
291 {
292 u_int active_fifo;
293
294 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
295 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
296 switch (active_fifo) {
297 case 0:
298 case 1:
299 ahd_set_modes(ahd, active_fifo, active_fifo);
300 return (1);
301 default:
302 return (0);
303 }
304 }
305
306 /************************* Sequencer Execution Control ************************/
307 /*
308 * Restart the sequencer program from address zero
309 */
310 void
311 ahd_restart(struct ahd_softc *ahd)
312 {
313
314 ahd_pause(ahd);
315
316 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
317
318 /* No more pending messages */
319 ahd_clear_msg_state(ahd);
320 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
321 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
322 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
323 ahd_outb(ahd, SEQINTCTL, 0);
324 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
325 ahd_outb(ahd, SEQ_FLAGS, 0);
326 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
327 ahd_outb(ahd, SAVED_LUN, 0xFF);
328
329 /*
330 * Ensure that the sequencer's idea of TQINPOS
331 * matches our own. The sequencer increments TQINPOS
332 * only after it sees a DMA complete and a reset could
333 * occur before the increment leaving the kernel to believe
334 * the command arrived but the sequencer to not.
335 */
336 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
337
338 /* Always allow reselection */
339 ahd_outb(ahd, SCSISEQ1,
340 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
341 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
342
343 /*
344 * Clear any pending sequencer interrupt. It is no
345 * longer relevant since we're resetting the Program
346 * Counter.
347 */
348 ahd_outb(ahd, CLRINT, CLRSEQINT);
349
350 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
351 ahd_unpause(ahd);
352 }
353
354 void
355 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
356 {
357 ahd_mode_state saved_modes;
358
359 #ifdef AHD_DEBUG
360 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
361 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
362 #endif
363 saved_modes = ahd_save_modes(ahd);
364 ahd_set_modes(ahd, fifo, fifo);
365 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
366 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
367 ahd_outb(ahd, CCSGCTL, CCSGRESET);
368 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
369 ahd_outb(ahd, SG_STATE, 0);
370 ahd_restore_modes(ahd, saved_modes);
371 }
372
373 /************************* Input/Output Queues ********************************/
374 /*
375 * Flush and completed commands that are sitting in the command
376 * complete queues down on the chip but have yet to be dma'ed back up.
377 */
378 void
379 ahd_flush_qoutfifo(struct ahd_softc *ahd)
380 {
381 struct scb *scb;
382 ahd_mode_state saved_modes;
383 u_int saved_scbptr;
384 u_int ccscbctl;
385 u_int scbid;
386 u_int next_scbid;
387
388 saved_modes = ahd_save_modes(ahd);
389
390 /*
391 * Flush the good status FIFO for completed packetized commands.
392 */
393 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
394 saved_scbptr = ahd_get_scbptr(ahd);
395 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
396 u_int fifo_mode;
397 u_int i;
398
399 scbid = ahd_inw(ahd, GSFIFO);
400 scb = ahd_lookup_scb(ahd, scbid);
401 if (scb == NULL) {
402 printf("%s: Warning - GSFIFO SCB %d invalid\n",
403 ahd_name(ahd), scbid);
404 continue;
405 }
406 /*
407 * Determine if this transaction is still active in
408 * any FIFO. If it is, we must flush that FIFO to
409 * the host before completing the command.
410 */
411 fifo_mode = 0;
412 rescan_fifos:
413 for (i = 0; i < 2; i++) {
414 /* Toggle to the other mode. */
415 fifo_mode ^= 1;
416 ahd_set_modes(ahd, fifo_mode, fifo_mode);
417
418 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
419 continue;
420
421 ahd_run_data_fifo(ahd, scb);
422
423 /*
424 * Running this FIFO may cause a CFG4DATA for
425 * this same transaction to assert in the other
426 * FIFO or a new snapshot SAVEPTRS interrupt
427 * in this FIFO. Even running a FIFO may not
428 * clear the transaction if we are still waiting
429 * for data to drain to the host. We must loop
430 * until the transaction is not active in either
431 * FIFO just to be sure. Reset our loop counter
432 * so we will visit both FIFOs again before
433 * declaring this transaction finished. We
434 * also delay a bit so that status has a chance
435 * to change before we look at this FIFO again.
436 */
437 aic_delay(200);
438 goto rescan_fifos;
439 }
440 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
441 ahd_set_scbptr(ahd, scbid);
442 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
443 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
444 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
445 & SG_LIST_NULL) != 0)) {
446 u_int comp_head;
447
448 /*
449 * The transfer completed with a residual.
450 * Place this SCB on the complete DMA list
451 * so that we update our in-core copy of the
452 * SCB before completing the command.
453 */
454 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
455 ahd_outb(ahd, SCB_SGPTR,
456 ahd_inb_scbram(ahd, SCB_SGPTR)
457 | SG_STATUS_VALID);
458 ahd_outw(ahd, SCB_TAG, scbid);
459 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
460 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
461 if (SCBID_IS_NULL(comp_head)) {
462 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
463 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
464 } else {
465 u_int tail;
466
467 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
468 ahd_set_scbptr(ahd, tail);
469 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
470 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
471 ahd_set_scbptr(ahd, scbid);
472 }
473 } else
474 ahd_complete_scb(ahd, scb);
475 }
476 ahd_set_scbptr(ahd, saved_scbptr);
477
478 /*
479 * Setup for command channel portion of flush.
480 */
481 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
482
483 /*
484 * Wait for any inprogress DMA to complete and clear DMA state
485 * if this if for an SCB in the qinfifo.
486 */
487 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
488
489 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
490 if ((ccscbctl & ARRDONE) != 0)
491 break;
492 } else if ((ccscbctl & CCSCBDONE) != 0)
493 break;
494 aic_delay(200);
495 }
496 /*
497 * We leave the sequencer to cleanup in the case of DMA's to
498 * update the qoutfifo. In all other cases (DMA's to the
499 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
500 * we disable the DMA engine so that the sequencer will not
501 * attempt to handle the DMA completion.
502 */
503 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
504 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
505
506 /*
507 * Complete any SCBs that just finished
508 * being DMA'ed into the qoutfifo.
509 */
510 ahd_run_qoutfifo(ahd);
511
512 saved_scbptr = ahd_get_scbptr(ahd);
513 /*
514 * Manually update/complete any completed SCBs that are waiting to be
515 * DMA'ed back up to the host.
516 */
517 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
518 while (!SCBID_IS_NULL(scbid)) {
519 uint8_t *hscb_ptr;
520 u_int i;
521
522 ahd_set_scbptr(ahd, scbid);
523 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
524 scb = ahd_lookup_scb(ahd, scbid);
525 if (scb == NULL) {
526 printf("%s: Warning - DMA-up and complete "
527 "SCB %d invalid\n", ahd_name(ahd), scbid);
528 continue;
529 }
530 hscb_ptr = (uint8_t *)scb->hscb;
531 for (i = 0; i < sizeof(struct hardware_scb); i++)
532 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
533
534 ahd_complete_scb(ahd, scb);
535 scbid = next_scbid;
536 }
537 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
538 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
539
540 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
541 while (!SCBID_IS_NULL(scbid)) {
542
543 ahd_set_scbptr(ahd, scbid);
544 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
545 scb = ahd_lookup_scb(ahd, scbid);
546 if (scb == NULL) {
547 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
548 ahd_name(ahd), scbid);
549 continue;
550 }
551
552 ahd_complete_scb(ahd, scb);
553 scbid = next_scbid;
554 }
555 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
556
557 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
558 while (!SCBID_IS_NULL(scbid)) {
559
560 ahd_set_scbptr(ahd, scbid);
561 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
562 scb = ahd_lookup_scb(ahd, scbid);
563 if (scb == NULL) {
564 printf("%s: Warning - Complete SCB %d invalid\n",
565 ahd_name(ahd), scbid);
566 continue;
567 }
568
569 ahd_complete_scb(ahd, scb);
570 scbid = next_scbid;
571 }
572 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
573
574 /*
575 * Restore state.
576 */
577 ahd_set_scbptr(ahd, saved_scbptr);
578 ahd_restore_modes(ahd, saved_modes);
579 ahd->flags |= AHD_UPDATE_PEND_CMDS;
580 }
581
582 /*
583 * Determine if an SCB for a packetized transaction
584 * is active in a FIFO.
585 */
586 static int
587 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
588 {
589
590 /*
591 * The FIFO is only active for our transaction if
592 * the SCBPTR matches the SCB's ID and the firmware
593 * has installed a handler for the FIFO or we have
594 * a pending SAVEPTRS or CFG4DATA interrupt.
595 */
596 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
597 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
598 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
599 return (0);
600
601 return (1);
602 }
603
604 /*
605 * Run a data fifo to completion for a transaction we know
606 * has completed across the SCSI bus (good status has been
607 * received). We are already set to the correct FIFO mode
608 * on entry to this routine.
609 *
610 * This function attempts to operate exactly as the firmware
611 * would when running this FIFO. Care must be taken to update
612 * this routine any time the firmware's FIFO algorithm is
613 * changed.
614 */
615 static void
616 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
617 {
618 u_int seqintsrc;
619
620 seqintsrc = ahd_inb(ahd, SEQINTSRC);
621 if ((seqintsrc & CFG4DATA) != 0) {
622 uint32_t datacnt;
623 uint32_t sgptr;
624
625 /*
626 * Clear full residual flag.
627 */
628 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
629 ahd_outb(ahd, SCB_SGPTR, sgptr);
630
631 /*
632 * Load datacnt and address.
633 */
634 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
635 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
636 sgptr |= LAST_SEG;
637 ahd_outb(ahd, SG_STATE, 0);
638 } else
639 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
640 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
641 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
642 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
643 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
644
645 /*
646 * Initialize Residual Fields.
647 */
648 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
649 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
650
651 /*
652 * Mark the SCB as having a FIFO in use.
653 */
654 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
655 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
656
657 /*
658 * Install a "fake" handler for this FIFO.
659 */
660 ahd_outw(ahd, LONGJMP_ADDR, 0);
661
662 /*
663 * Notify the hardware that we have satisfied
664 * this sequencer interrupt.
665 */
666 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
667 } else if ((seqintsrc & SAVEPTRS) != 0) {
668 uint32_t sgptr;
669 uint32_t resid;
670
671 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
672 /*
673 * Snapshot Save Pointers. All that
674 * is necessary to clear the snapshot
675 * is a CLRCHN.
676 */
677 goto clrchn;
678 }
679
680 /*
681 * Disable S/G fetch so the DMA engine
682 * is available to future users.
683 */
684 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
685 ahd_outb(ahd, CCSGCTL, 0);
686 ahd_outb(ahd, SG_STATE, 0);
687
688 /*
689 * Flush the data FIFO. Strickly only
690 * necessary for Rev A parts.
691 */
692 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
693
694 /*
695 * Calculate residual.
696 */
697 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
698 resid = ahd_inl(ahd, SHCNT);
699 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
700 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
701 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
702 /*
703 * Must back up to the correct S/G element.
704 * Typically this just means resetting our
705 * low byte to the offset in the SG_CACHE,
706 * but if we wrapped, we have to correct
707 * the other bytes of the sgptr too.
708 */
709 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
710 && (sgptr & 0x80) == 0)
711 sgptr -= 0x100;
712 sgptr &= ~0xFF;
713 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
714 & SG_ADDR_MASK;
715 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
716 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
717 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
718 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
719 sgptr | SG_LIST_NULL);
720 }
721 /*
722 * Save Pointers.
723 */
724 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
725 ahd_outl(ahd, SCB_DATACNT, resid);
726 ahd_outl(ahd, SCB_SGPTR, sgptr);
727 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
728 ahd_outb(ahd, SEQIMODE,
729 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
730 /*
731 * If the data is to the SCSI bus, we are
732 * done, otherwise wait for FIFOEMP.
733 */
734 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
735 goto clrchn;
736 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
737 uint32_t sgptr;
738 uint64_t data_addr;
739 uint32_t data_len;
740 u_int dfcntrl;
741
742 /*
743 * Disable S/G fetch so the DMA engine
744 * is available to future users. We won't
745 * be using the DMA engine to load segments.
746 */
747 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
748 ahd_outb(ahd, CCSGCTL, 0);
749 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
750 }
751
752 /*
753 * Wait for the DMA engine to notice that the
754 * host transfer is enabled and that there is
755 * space in the S/G FIFO for new segments before
756 * loading more segments.
757 */
758 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
759 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
760
761 /*
762 * Determine the offset of the next S/G
763 * element to load.
764 */
765 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
766 sgptr &= SG_PTR_MASK;
767 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
768 struct ahd_dma64_seg *sg;
769
770 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
771 data_addr = sg->addr;
772 data_len = sg->len;
773 sgptr += sizeof(*sg);
774 } else {
775 struct ahd_dma_seg *sg;
776
777 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
778 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
779 data_addr <<= 8;
780 data_addr |= sg->addr;
781 data_len = sg->len;
782 sgptr += sizeof(*sg);
783 }
784
785 /*
786 * Update residual information.
787 */
788 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
789 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
790
791 /*
792 * Load the S/G.
793 */
794 if (data_len & AHD_DMA_LAST_SEG) {
795 sgptr |= LAST_SEG;
796 ahd_outb(ahd, SG_STATE, 0);
797 }
798 ahd_outq(ahd, HADDR, data_addr);
799 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
800 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
801
802 /*
803 * Advertise the segment to the hardware.
804 */
805 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
806 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
807 /*
808 * Use SCSIENWRDIS so that SCSIEN
809 * is never modified by this
810 * operation.
811 */
812 dfcntrl |= SCSIENWRDIS;
813 }
814 ahd_outb(ahd, DFCNTRL, dfcntrl);
815 }
816 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
817
818 /*
819 * Transfer completed to the end of SG list
820 * and has flushed to the host.
821 */
822 ahd_outb(ahd, SCB_SGPTR,
823 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
824 goto clrchn;
825 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
826 clrchn:
827 /*
828 * Clear any handler for this FIFO, decrement
829 * the FIFO use count for the SCB, and release
830 * the FIFO.
831 */
832 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
833 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
834 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
835 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
836 }
837 }
838
839 /*
840 * Look for entries in the QoutFIFO that have completed.
841 * The valid_tag completion field indicates the validity
842 * of the entry - the valid value toggles each time through
843 * the queue. We use the sg_status field in the completion
844 * entry to avoid referencing the hscb if the completion
845 * occurred with no errors and no residual. sg_status is
846 * a copy of the first byte (little endian) of the sgptr
847 * hscb field.
848 */
849 void
850 ahd_run_qoutfifo(struct ahd_softc *ahd)
851 {
852 struct ahd_completion *completion;
853 struct scb *scb;
854 u_int scb_index;
855
856 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
857 panic("ahd_run_qoutfifo recursion");
858 ahd->flags |= AHD_RUNNING_QOUTFIFO;
859 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
860 for (;;) {
861 completion = &ahd->qoutfifo[ahd->qoutfifonext];
862
863 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
864 break;
865
866 scb_index = aic_le16toh(completion->tag);
867 scb = ahd_lookup_scb(ahd, scb_index);
868 if (scb == NULL) {
869 printf("%s: WARNING no command for scb %d "
870 "(cmdcmplt)\nQOUTPOS = %d\n",
871 ahd_name(ahd), scb_index,
872 ahd->qoutfifonext);
873 ahd_dump_card_state(ahd);
874 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
875 ahd_handle_scb_status(ahd, scb);
876 } else {
877 ahd_done(ahd, scb);
878 }
879
880 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
881 if (ahd->qoutfifonext == 0)
882 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
883 }
884 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
885 }
886
887 /************************* Interrupt Handling *********************************/
888 void
889 ahd_handle_hwerrint(struct ahd_softc *ahd)
890 {
891 /*
892 * Some catastrophic hardware error has occurred.
893 * Print it for the user and disable the controller.
894 */
895 int i;
896 int error;
897
898 error = ahd_inb(ahd, ERROR);
899 for (i = 0; i < num_errors; i++) {
900 if ((error & ahd_hard_errors[i].errno) != 0)
901 printf("%s: hwerrint, %s\n",
902 ahd_name(ahd), ahd_hard_errors[i].errmesg);
903 }
904
905 ahd_dump_card_state(ahd);
906 panic("BRKADRINT");
907
908 /* Tell everyone that this HBA is no longer available */
909 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
910 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
911 CAM_NO_HBA);
912
913 /* Tell the system that this controller has gone away. */
914 ahd_free(ahd);
915 }
916
917 void
918 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
919 {
920 u_int seqintcode;
921
922 /*
923 * Save the sequencer interrupt code and clear the SEQINT
924 * bit. We will unpause the sequencer, if appropriate,
925 * after servicing the request.
926 */
927 seqintcode = ahd_inb(ahd, SEQINTCODE);
928 ahd_outb(ahd, CLRINT, CLRSEQINT);
929 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
930 /*
931 * Unpause the sequencer and let it clear
932 * SEQINT by writing NO_SEQINT to it. This
933 * will cause the sequencer to be paused again,
934 * which is the expected state of this routine.
935 */
936 ahd_unpause(ahd);
937 while (!ahd_is_paused(ahd))
938 ;
939 ahd_outb(ahd, CLRINT, CLRSEQINT);
940 }
941 ahd_update_modes(ahd);
942 #ifdef AHD_DEBUG
943 if ((ahd_debug & AHD_SHOW_MISC) != 0)
944 printf("%s: Handle Seqint Called for code %d\n",
945 ahd_name(ahd), seqintcode);
946 #endif
947 switch (seqintcode) {
948 case ENTERING_NONPACK:
949 {
950 struct scb *scb;
951 u_int scbid;
952
953 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
954 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
955 scbid = ahd_get_scbptr(ahd);
956 scb = ahd_lookup_scb(ahd, scbid);
957 if (scb == NULL) {
958 /*
959 * Somehow need to know if this
960 * is from a selection or reselection.
961 * From that, we can determine target
962 * ID so we at least have an I_T nexus.
963 */
964 } else {
965 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
966 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
967 ahd_outb(ahd, SEQ_FLAGS, 0x0);
968 }
969 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
970 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
971 /*
972 * Phase change after read stream with
973 * CRC error with P0 asserted on last
974 * packet.
975 */
976 #ifdef AHD_DEBUG
977 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
978 printf("%s: Assuming LQIPHASE_NLQ with "
979 "P0 assertion\n", ahd_name(ahd));
980 #endif
981 }
982 #ifdef AHD_DEBUG
983 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
984 printf("%s: Entering NONPACK\n", ahd_name(ahd));
985 #endif
986 break;
987 }
988 case INVALID_SEQINT:
989 printf("%s: Invalid Sequencer interrupt occurred.\n",
990 ahd_name(ahd));
991 ahd_dump_card_state(ahd);
992 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
993 break;
994 case STATUS_OVERRUN:
995 {
996 struct scb *scb;
997 u_int scbid;
998
999 scbid = ahd_get_scbptr(ahd);
1000 scb = ahd_lookup_scb(ahd, scbid);
1001 if (scb != NULL)
1002 ahd_print_path(ahd, scb);
1003 else
1004 printf("%s: ", ahd_name(ahd));
1005 printf("SCB %d Packetized Status Overrun", scbid);
1006 ahd_dump_card_state(ahd);
1007 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1008 break;
1009 }
1010 case CFG4ISTAT_INTR:
1011 {
1012 struct scb *scb;
1013 u_int scbid;
1014
1015 scbid = ahd_get_scbptr(ahd);
1016 scb = ahd_lookup_scb(ahd, scbid);
1017 if (scb == NULL) {
1018 ahd_dump_card_state(ahd);
1019 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1020 panic("For safety");
1021 }
1022 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1023 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1024 ahd_outb(ahd, HCNT + 2, 0);
1025 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1026 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1027 break;
1028 }
1029 case ILLEGAL_PHASE:
1030 {
1031 u_int bus_phase;
1032
1033 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1034 printf("%s: ILLEGAL_PHASE 0x%x\n",
1035 ahd_name(ahd), bus_phase);
1036
1037 switch (bus_phase) {
1038 case P_DATAOUT:
1039 case P_DATAIN:
1040 case P_DATAOUT_DT:
1041 case P_DATAIN_DT:
1042 case P_MESGOUT:
1043 case P_STATUS:
1044 case P_MESGIN:
1045 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1046 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1047 break;
1048 case P_COMMAND:
1049 {
1050 struct ahd_devinfo devinfo;
1051 struct scb *scb;
1052 struct ahd_initiator_tinfo *targ_info;
1053 struct ahd_tmode_tstate *tstate;
1054 struct ahd_transinfo *tinfo;
1055 u_int scbid;
1056
1057 /*
1058 * If a target takes us into the command phase
1059 * assume that it has been externally reset and
1060 * has thus lost our previous packetized negotiation
1061 * agreement. Since we have not sent an identify
1062 * message and may not have fully qualified the
1063 * connection, we change our command to TUR, assert
1064 * ATN and ABORT the task when we go to message in
1065 * phase. The OSM will see the REQUEUE_REQUEST
1066 * status and retry the command.
1067 */
1068 scbid = ahd_get_scbptr(ahd);
1069 scb = ahd_lookup_scb(ahd, scbid);
1070 if (scb == NULL) {
1071 printf("Invalid phase with no valid SCB. "
1072 "Resetting bus.\n");
1073 ahd_reset_channel(ahd, 'A',
1074 /*Initiate Reset*/TRUE);
1075 break;
1076 }
1077 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1078 SCB_GET_TARGET(ahd, scb),
1079 SCB_GET_LUN(scb),
1080 SCB_GET_CHANNEL(ahd, scb),
1081 ROLE_INITIATOR);
1082 targ_info = ahd_fetch_transinfo(ahd,
1083 devinfo.channel,
1084 devinfo.our_scsiid,
1085 devinfo.target,
1086 &tstate);
1087 tinfo = &targ_info->curr;
1088 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1089 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1090 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1091 /*offset*/0, /*ppr_options*/0,
1092 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1093 ahd_outb(ahd, SCB_CDB_STORE, 0);
1094 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1095 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1096 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1097 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1098 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1099 ahd_outb(ahd, SCB_CDB_LEN, 6);
1100 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1101 scb->hscb->control |= MK_MESSAGE;
1102 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1103 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1104 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1105 /*
1106 * The lun is 0, regardless of the SCB's lun
1107 * as we have not sent an identify message.
1108 */
1109 ahd_outb(ahd, SAVED_LUN, 0);
1110 ahd_outb(ahd, SEQ_FLAGS, 0);
1111 ahd_assert_atn(ahd);
1112 scb->flags &= ~SCB_PACKETIZED;
1113 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1114 ahd_freeze_devq(ahd, scb);
1115 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
1116 aic_freeze_scb(scb);
1117
1118 /*
1119 * Allow the sequencer to continue with
1120 * non-pack processing.
1121 */
1122 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1123 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1124 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1125 ahd_outb(ahd, CLRLQOINT1, 0);
1126 }
1127 #ifdef AHD_DEBUG
1128 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1129 ahd_print_path(ahd, scb);
1130 printf("Unexpected command phase from "
1131 "packetized target\n");
1132 }
1133 #endif
1134 break;
1135 }
1136 }
1137 break;
1138 }
1139 case CFG4OVERRUN:
1140 {
1141 struct scb *scb;
1142 u_int scb_index;
1143
1144 #ifdef AHD_DEBUG
1145 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1146 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1147 ahd_inb(ahd, MODE_PTR));
1148 }
1149 #endif
1150 scb_index = ahd_get_scbptr(ahd);
1151 scb = ahd_lookup_scb(ahd, scb_index);
1152 if (scb == NULL) {
1153 /*
1154 * Attempt to transfer to an SCB that is
1155 * not outstanding.
1156 */
1157 ahd_assert_atn(ahd);
1158 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1159 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1160 ahd->msgout_len = 1;
1161 ahd->msgout_index = 0;
1162 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1163 /*
1164 * Clear status received flag to prevent any
1165 * attempt to complete this bogus SCB.
1166 */
1167 ahd_outb(ahd, SCB_CONTROL,
1168 ahd_inb_scbram(ahd, SCB_CONTROL)
1169 & ~STATUS_RCVD);
1170 }
1171 break;
1172 }
1173 case DUMP_CARD_STATE:
1174 {
1175 ahd_dump_card_state(ahd);
1176 break;
1177 }
1178 case PDATA_REINIT:
1179 {
1180 #ifdef AHD_DEBUG
1181 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1182 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1183 "SG_CACHE_SHADOW = 0x%x\n",
1184 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1185 ahd_inb(ahd, SG_CACHE_SHADOW));
1186 }
1187 #endif
1188 ahd_reinitialize_dataptrs(ahd);
1189 break;
1190 }
1191 case HOST_MSG_LOOP:
1192 {
1193 struct ahd_devinfo devinfo;
1194
1195 /*
1196 * The sequencer has encountered a message phase
1197 * that requires host assistance for completion.
1198 * While handling the message phase(s), we will be
1199 * notified by the sequencer after each byte is
1200 * transfered so we can track bus phase changes.
1201 *
1202 * If this is the first time we've seen a HOST_MSG_LOOP
1203 * interrupt, initialize the state of the host message
1204 * loop.
1205 */
1206 ahd_fetch_devinfo(ahd, &devinfo);
1207 if (ahd->msg_type == MSG_TYPE_NONE) {
1208 struct scb *scb;
1209 u_int scb_index;
1210 u_int bus_phase;
1211
1212 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1213 if (bus_phase != P_MESGIN
1214 && bus_phase != P_MESGOUT) {
1215 printf("ahd_intr: HOST_MSG_LOOP bad "
1216 "phase 0x%x\n", bus_phase);
1217 /*
1218 * Probably transitioned to bus free before
1219 * we got here. Just punt the message.
1220 */
1221 ahd_dump_card_state(ahd);
1222 ahd_clear_intstat(ahd);
1223 ahd_restart(ahd);
1224 return;
1225 }
1226
1227 scb_index = ahd_get_scbptr(ahd);
1228 scb = ahd_lookup_scb(ahd, scb_index);
1229 if (devinfo.role == ROLE_INITIATOR) {
1230 if (bus_phase == P_MESGOUT)
1231 ahd_setup_initiator_msgout(ahd,
1232 &devinfo,
1233 scb);
1234 else {
1235 ahd->msg_type =
1236 MSG_TYPE_INITIATOR_MSGIN;
1237 ahd->msgin_index = 0;
1238 }
1239 }
1240 #if AHD_TARGET_MODE
1241 else {
1242 if (bus_phase == P_MESGOUT) {
1243 ahd->msg_type =
1244 MSG_TYPE_TARGET_MSGOUT;
1245 ahd->msgin_index = 0;
1246 }
1247 else
1248 ahd_setup_target_msgin(ahd,
1249 &devinfo,
1250 scb);
1251 }
1252 #endif
1253 }
1254
1255 ahd_handle_message_phase(ahd);
1256 break;
1257 }
1258 case NO_MATCH:
1259 {
1260 /* Ensure we don't leave the selection hardware on */
1261 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1262 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1263
1264 printf("%s:%c:%d: no active SCB for reconnecting "
1265 "target - issuing BUS DEVICE RESET\n",
1266 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1267 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1268 "REG0 == 0x%x ACCUM = 0x%x\n",
1269 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1270 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1271 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1272 "SINDEX == 0x%x\n",
1273 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1274 ahd_find_busy_tcl(ahd,
1275 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1276 ahd_inb(ahd, SAVED_LUN))),
1277 ahd_inw(ahd, SINDEX));
1278 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1279 "SCB_CONTROL == 0x%x\n",
1280 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1281 ahd_inb_scbram(ahd, SCB_LUN),
1282 ahd_inb_scbram(ahd, SCB_CONTROL));
1283 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1284 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1285 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1286 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1287 ahd_dump_card_state(ahd);
1288 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1289 ahd->msgout_len = 1;
1290 ahd->msgout_index = 0;
1291 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1292 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1293 ahd_assert_atn(ahd);
1294 break;
1295 }
1296 case PROTO_VIOLATION:
1297 {
1298 ahd_handle_proto_violation(ahd);
1299 break;
1300 }
1301 case IGN_WIDE_RES:
1302 {
1303 struct ahd_devinfo devinfo;
1304
1305 ahd_fetch_devinfo(ahd, &devinfo);
1306 ahd_handle_ign_wide_residue(ahd, &devinfo);
1307 break;
1308 }
1309 case BAD_PHASE:
1310 {
1311 u_int lastphase;
1312
1313 lastphase = ahd_inb(ahd, LASTPHASE);
1314 printf("%s:%c:%d: unknown scsi bus phase %x, "
1315 "lastphase = 0x%x. Attempting to continue\n",
1316 ahd_name(ahd), 'A',
1317 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1318 lastphase, ahd_inb(ahd, SCSISIGI));
1319 break;
1320 }
1321 case MISSED_BUSFREE:
1322 {
1323 u_int lastphase;
1324
1325 lastphase = ahd_inb(ahd, LASTPHASE);
1326 printf("%s:%c:%d: Missed busfree. "
1327 "Lastphase = 0x%x, Curphase = 0x%x\n",
1328 ahd_name(ahd), 'A',
1329 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1330 lastphase, ahd_inb(ahd, SCSISIGI));
1331 ahd_restart(ahd);
1332 return;
1333 }
1334 case DATA_OVERRUN:
1335 {
1336 /*
1337 * When the sequencer detects an overrun, it
1338 * places the controller in "BITBUCKET" mode
1339 * and allows the target to complete its transfer.
1340 * Unfortunately, none of the counters get updated
1341 * when the controller is in this mode, so we have
1342 * no way of knowing how large the overrun was.
1343 */
1344 struct scb *scb;
1345 u_int scbindex;
1346 #ifdef AHD_DEBUG
1347 u_int lastphase;
1348 #endif
1349
1350 scbindex = ahd_get_scbptr(ahd);
1351 scb = ahd_lookup_scb(ahd, scbindex);
1352 #ifdef AHD_DEBUG
1353 lastphase = ahd_inb(ahd, LASTPHASE);
1354 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1355 ahd_print_path(ahd, scb);
1356 printf("data overrun detected %s. Tag == 0x%x.\n",
1357 ahd_lookup_phase_entry(lastphase)->phasemsg,
1358 SCB_GET_TAG(scb));
1359 ahd_print_path(ahd, scb);
1360 printf("%s seen Data Phase. Length = %ld. "
1361 "NumSGs = %d.\n",
1362 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1363 ? "Have" : "Haven't",
1364 aic_get_transfer_length(scb), scb->sg_count);
1365 ahd_dump_sglist(scb);
1366 }
1367 #endif
1368
1369 /*
1370 * Set this and it will take effect when the
1371 * target does a command complete.
1372 */
1373 ahd_freeze_devq(ahd, scb);
1374 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1375 aic_freeze_scb(scb);
1376 break;
1377 }
1378 case MKMSG_FAILED:
1379 {
1380 struct ahd_devinfo devinfo;
1381 struct scb *scb;
1382 u_int scbid;
1383
1384 ahd_fetch_devinfo(ahd, &devinfo);
1385 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1386 ahd_name(ahd), devinfo.channel, devinfo.target,
1387 devinfo.lun);
1388 scbid = ahd_get_scbptr(ahd);
1389 scb = ahd_lookup_scb(ahd, scbid);
1390 if (scb != NULL
1391 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1392 /*
1393 * Ensure that we didn't put a second instance of this
1394 * SCB into the QINFIFO.
1395 */
1396 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1397 SCB_GET_CHANNEL(ahd, scb),
1398 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1399 ROLE_INITIATOR, /*status*/0,
1400 SEARCH_REMOVE);
1401 ahd_outb(ahd, SCB_CONTROL,
1402 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1403 break;
1404 }
1405 case TASKMGMT_FUNC_COMPLETE:
1406 {
1407 u_int scbid;
1408 struct scb *scb;
1409
1410 scbid = ahd_get_scbptr(ahd);
1411 scb = ahd_lookup_scb(ahd, scbid);
1412 if (scb != NULL) {
1413 u_int lun;
1414 u_int tag;
1415 cam_status error;
1416
1417 ahd_print_path(ahd, scb);
1418 printf("Task Management Func 0x%x Complete\n",
1419 scb->hscb->task_management);
1420 lun = CAM_LUN_WILDCARD;
1421 tag = SCB_LIST_NULL;
1422
1423 switch (scb->hscb->task_management) {
1424 case SIU_TASKMGMT_ABORT_TASK:
1425 tag = SCB_GET_TAG(scb);
1426 case SIU_TASKMGMT_ABORT_TASK_SET:
1427 case SIU_TASKMGMT_CLEAR_TASK_SET:
1428 lun = scb->hscb->lun;
1429 error = CAM_REQ_ABORTED;
1430 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1431 'A', lun, tag, ROLE_INITIATOR,
1432 error);
1433 break;
1434 case SIU_TASKMGMT_LUN_RESET:
1435 lun = scb->hscb->lun;
1436 case SIU_TASKMGMT_TARGET_RESET:
1437 {
1438 struct ahd_devinfo devinfo;
1439
1440 ahd_scb_devinfo(ahd, &devinfo, scb);
1441 error = CAM_BDR_SENT;
1442 ahd_handle_devreset(ahd, &devinfo, lun,
1443 CAM_BDR_SENT,
1444 lun != CAM_LUN_WILDCARD
1445 ? "Lun Reset"
1446 : "Target Reset",
1447 /*verbose_level*/0);
1448 break;
1449 }
1450 default:
1451 panic("Unexpected TaskMgmt Func\n");
1452 break;
1453 }
1454 }
1455 break;
1456 }
1457 case TASKMGMT_CMD_CMPLT_OKAY:
1458 {
1459 u_int scbid;
1460 struct scb *scb;
1461
1462 /*
1463 * An ABORT TASK TMF failed to be delivered before
1464 * the targeted command completed normally.
1465 */
1466 scbid = ahd_get_scbptr(ahd);
1467 scb = ahd_lookup_scb(ahd, scbid);
1468 if (scb != NULL) {
1469 /*
1470 * Remove the second instance of this SCB from
1471 * the QINFIFO if it is still there.
1472 */
1473 ahd_print_path(ahd, scb);
1474 printf("SCB completes before TMF\n");
1475 /*
1476 * Handle losing the race. Wait until any
1477 * current selection completes. We will then
1478 * set the TMF back to zero in this SCB so that
1479 * the sequencer doesn't bother to issue another
1480 * sequencer interrupt for its completion.
1481 */
1482 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1483 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1484 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1485 ;
1486 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1487 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1488 SCB_GET_CHANNEL(ahd, scb),
1489 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1490 ROLE_INITIATOR, /*status*/0,
1491 SEARCH_REMOVE);
1492 }
1493 break;
1494 }
1495 case TRACEPOINT0:
1496 case TRACEPOINT1:
1497 case TRACEPOINT2:
1498 case TRACEPOINT3:
1499 printf("%s: Tracepoint %d\n", ahd_name(ahd),
1500 seqintcode - TRACEPOINT0);
1501 break;
1502 case NO_SEQINT:
1503 break;
1504 case SAW_HWERR:
1505 ahd_handle_hwerrint(ahd);
1506 break;
1507 default:
1508 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1509 seqintcode);
1510 break;
1511 }
1512 /*
1513 * The sequencer is paused immediately on
1514 * a SEQINT, so we should restart it when
1515 * we're done.
1516 */
1517 ahd_unpause(ahd);
1518 }
1519
1520 void
1521 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1522 {
1523 struct scb *scb;
1524 u_int status0;
1525 u_int status3;
1526 u_int status;
1527 u_int lqistat1;
1528 u_int lqostat0;
1529 u_int scbid;
1530 u_int busfreetime;
1531
1532 ahd_update_modes(ahd);
1533 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1534
1535 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1536 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1537 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1538 lqistat1 = ahd_inb(ahd, LQISTAT1);
1539 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1540 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1541 if ((status0 & (SELDI|SELDO)) != 0) {
1542 u_int simode0;
1543
1544 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1545 simode0 = ahd_inb(ahd, SIMODE0);
1546 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1547 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1548 }
1549 scbid = ahd_get_scbptr(ahd);
1550 scb = ahd_lookup_scb(ahd, scbid);
1551 if (scb != NULL
1552 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1553 scb = NULL;
1554
1555 if ((status0 & IOERR) != 0) {
1556 u_int now_lvd;
1557
1558 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1559 printf("%s: Transceiver State Has Changed to %s mode\n",
1560 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1561 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1562 /*
1563 * A change in I/O mode is equivalent to a bus reset.
1564 */
1565 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1566 ahd_pause(ahd);
1567 ahd_setup_iocell_workaround(ahd);
1568 ahd_unpause(ahd);
1569 } else if ((status0 & OVERRUN) != 0) {
1570
1571 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1572 ahd_name(ahd));
1573 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1574 } else if ((status & SCSIRSTI) != 0) {
1575
1576 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1577 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1578 } else if ((status & SCSIPERR) != 0) {
1579
1580 /* Make sure the sequencer is in a safe location. */
1581 ahd_clear_critical_section(ahd);
1582
1583 ahd_handle_transmission_error(ahd);
1584 } else if (lqostat0 != 0) {
1585
1586 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1587 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1588 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1589 ahd_outb(ahd, CLRLQOINT1, 0);
1590 } else if ((status & SELTO) != 0) {
1591 u_int scbid;
1592
1593 /* Stop the selection */
1594 ahd_outb(ahd, SCSISEQ0, 0);
1595
1596 /* Make sure the sequencer is in a safe location. */
1597 ahd_clear_critical_section(ahd);
1598
1599 /* No more pending messages */
1600 ahd_clear_msg_state(ahd);
1601
1602 /* Clear interrupt state */
1603 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1604
1605 /*
1606 * Although the driver does not care about the
1607 * 'Selection in Progress' status bit, the busy
1608 * LED does. SELINGO is only cleared by a sucessfull
1609 * selection, so we must manually clear it to insure
1610 * the LED turns off just incase no future successful
1611 * selections occur (e.g. no devices on the bus).
1612 */
1613 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1614
1615 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1616 scb = ahd_lookup_scb(ahd, scbid);
1617 if (scb == NULL) {
1618 printf("%s: ahd_intr - referenced scb not "
1619 "valid during SELTO scb(0x%x)\n",
1620 ahd_name(ahd), scbid);
1621 ahd_dump_card_state(ahd);
1622 } else {
1623 struct ahd_devinfo devinfo;
1624 #ifdef AHD_DEBUG
1625 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1626 ahd_print_path(ahd, scb);
1627 printf("Saw Selection Timeout for SCB 0x%x\n",
1628 scbid);
1629 }
1630 #endif
1631 ahd_scb_devinfo(ahd, &devinfo, scb);
1632 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1633 ahd_freeze_devq(ahd, scb);
1634
1635 /*
1636 * Cancel any pending transactions on the device
1637 * now that it seems to be missing. This will
1638 * also revert us to async/narrow transfers until
1639 * we can renegotiate with the device.
1640 */
1641 ahd_handle_devreset(ahd, &devinfo,
1642 CAM_LUN_WILDCARD,
1643 CAM_SEL_TIMEOUT,
1644 "Selection Timeout",
1645 /*verbose_level*/1);
1646 }
1647 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1648 ahd_iocell_first_selection(ahd);
1649 ahd_unpause(ahd);
1650 } else if ((status0 & (SELDI|SELDO)) != 0) {
1651
1652 ahd_iocell_first_selection(ahd);
1653 ahd_unpause(ahd);
1654 } else if (status3 != 0) {
1655 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1656 ahd_name(ahd), status3);
1657 ahd_outb(ahd, CLRSINT3, status3);
1658 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1659
1660 /* Make sure the sequencer is in a safe location. */
1661 ahd_clear_critical_section(ahd);
1662
1663 ahd_handle_lqiphase_error(ahd, lqistat1);
1664 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1665 /*
1666 * This status can be delayed during some
1667 * streaming operations. The SCSIPHASE
1668 * handler has already dealt with this case
1669 * so just clear the error.
1670 */
1671 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1672 } else if ((status & BUSFREE) != 0
1673 || (lqistat1 & LQOBUSFREE) != 0) {
1674 u_int lqostat1;
1675 int restart;
1676 int clear_fifo;
1677 int packetized;
1678 u_int mode;
1679
1680 /*
1681 * Clear our selection hardware as soon as possible.
1682 * We may have an entry in the waiting Q for this target,
1683 * that is affected by this busfree and we don't want to
1684 * go about selecting the target while we handle the event.
1685 */
1686 ahd_outb(ahd, SCSISEQ0, 0);
1687
1688 /* Make sure the sequencer is in a safe location. */
1689 ahd_clear_critical_section(ahd);
1690
1691 /*
1692 * Determine what we were up to at the time of
1693 * the busfree.
1694 */
1695 mode = AHD_MODE_SCSI;
1696 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1697 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1698 switch (busfreetime) {
1699 case BUSFREE_DFF0:
1700 case BUSFREE_DFF1:
1701 {
1702 u_int scbid;
1703 struct scb *scb;
1704
1705 mode = busfreetime == BUSFREE_DFF0
1706 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1707 ahd_set_modes(ahd, mode, mode);
1708 scbid = ahd_get_scbptr(ahd);
1709 scb = ahd_lookup_scb(ahd, scbid);
1710 if (scb == NULL) {
1711 printf("%s: Invalid SCB %d in DFF%d "
1712 "during unexpected busfree\n",
1713 ahd_name(ahd), scbid, mode);
1714 packetized = 0;
1715 } else
1716 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1717 clear_fifo = 1;
1718 break;
1719 }
1720 case BUSFREE_LQO:
1721 clear_fifo = 0;
1722 packetized = 1;
1723 break;
1724 default:
1725 clear_fifo = 0;
1726 packetized = (lqostat1 & LQOBUSFREE) != 0;
1727 if (!packetized
1728 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1729 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1730 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1731 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1732 /*
1733 * Assume packetized if we are not
1734 * on the bus in a non-packetized
1735 * capacity and any pending selection
1736 * was a packetized selection.
1737 */
1738 packetized = 1;
1739 break;
1740 }
1741
1742 #ifdef AHD_DEBUG
1743 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1744 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1745 busfreetime);
1746 #endif
1747 /*
1748 * Busfrees that occur in non-packetized phases are
1749 * handled by the nonpkt_busfree handler.
1750 */
1751 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1752 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1753 } else {
1754 packetized = 0;
1755 restart = ahd_handle_nonpkt_busfree(ahd);
1756 }
1757 /*
1758 * Clear the busfree interrupt status. The setting of
1759 * the interrupt is a pulse, so in a perfect world, we
1760 * would not need to muck with the ENBUSFREE logic. This
1761 * would ensure that if the bus moves on to another
1762 * connection, busfree protection is still in force. If
1763 * BUSFREEREV is broken, however, we must manually clear
1764 * the ENBUSFREE if the busfree occurred during a non-pack
1765 * connection so that we don't get false positives during
1766 * future, packetized, connections.
1767 */
1768 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1769 if (packetized == 0
1770 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1771 ahd_outb(ahd, SIMODE1,
1772 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1773
1774 if (clear_fifo)
1775 ahd_clear_fifo(ahd, mode);
1776
1777 ahd_clear_msg_state(ahd);
1778 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1779 if (restart) {
1780 ahd_restart(ahd);
1781 } else {
1782 ahd_unpause(ahd);
1783 }
1784 } else {
1785 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1786 ahd_name(ahd), status);
1787 ahd_dump_card_state(ahd);
1788 ahd_clear_intstat(ahd);
1789 ahd_unpause(ahd);
1790 }
1791 }
1792
1793 static void
1794 ahd_handle_transmission_error(struct ahd_softc *ahd)
1795 {
1796 struct scb *scb;
1797 u_int scbid;
1798 u_int lqistat1;
1799 u_int lqistat2;
1800 u_int msg_out;
1801 u_int curphase;
1802 u_int lastphase;
1803 u_int perrdiag;
1804 u_int cur_col;
1805 int silent;
1806
1807 scb = NULL;
1808 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1809 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1810 lqistat2 = ahd_inb(ahd, LQISTAT2);
1811 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1812 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1813 u_int lqistate;
1814
1815 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1816 lqistate = ahd_inb(ahd, LQISTATE);
1817 if ((lqistate >= 0x1E && lqistate <= 0x24)
1818 || (lqistate == 0x29)) {
1819 #ifdef AHD_DEBUG
1820 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1821 printf("%s: NLQCRC found via LQISTATE\n",
1822 ahd_name(ahd));
1823 }
1824 #endif
1825 lqistat1 |= LQICRCI_NLQ;
1826 }
1827 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1828 }
1829
1830 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1831 lastphase = ahd_inb(ahd, LASTPHASE);
1832 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1833 perrdiag = ahd_inb(ahd, PERRDIAG);
1834 msg_out = MSG_INITIATOR_DET_ERR;
1835 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1836
1837 /*
1838 * Try to find the SCB associated with this error.
1839 */
1840 silent = FALSE;
1841 if (lqistat1 == 0
1842 || (lqistat1 & LQICRCI_NLQ) != 0) {
1843 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1844 ahd_set_active_fifo(ahd);
1845 scbid = ahd_get_scbptr(ahd);
1846 scb = ahd_lookup_scb(ahd, scbid);
1847 if (scb != NULL && SCB_IS_SILENT(scb))
1848 silent = TRUE;
1849 }
1850
1851 cur_col = 0;
1852 if (silent == FALSE) {
1853 printf("%s: Transmission error detected\n", ahd_name(ahd));
1854 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1855 ahd_lastphase_print(lastphase, &cur_col, 50);
1856 ahd_scsisigi_print(curphase, &cur_col, 50);
1857 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1858 printf("\n");
1859 ahd_dump_card_state(ahd);
1860 }
1861
1862 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1863 if (silent == FALSE) {
1864 printf("%s: Gross protocol error during incoming "
1865 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1866 ahd_name(ahd), lqistat1);
1867 }
1868 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1869 return;
1870 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1871 /*
1872 * A CRC error has been detected on an incoming LQ.
1873 * The bus is currently hung on the last ACK.
1874 * Hit LQIRETRY to release the last ack, and
1875 * wait for the sequencer to determine that ATNO
1876 * is asserted while in message out to take us
1877 * to our host message loop. No NONPACKREQ or
1878 * LQIPHASE type errors will occur in this
1879 * scenario. After this first LQIRETRY, the LQI
1880 * manager will be in ISELO where it will
1881 * happily sit until another packet phase begins.
1882 * Unexpected bus free detection is enabled
1883 * through any phases that occur after we release
1884 * this last ack until the LQI manager sees a
1885 * packet phase. This implies we may have to
1886 * ignore a perfectly valid "unexected busfree"
1887 * after our "initiator detected error" message is
1888 * sent. A busfree is the expected response after
1889 * we tell the target that it's L_Q was corrupted.
1890 * (SPI4R09 10.7.3.3.3)
1891 */
1892 ahd_outb(ahd, LQCTL2, LQIRETRY);
1893 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1894 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1895 /*
1896 * We detected a CRC error in a NON-LQ packet.
1897 * The hardware has varying behavior in this situation
1898 * depending on whether this packet was part of a
1899 * stream or not.
1900 *
1901 * PKT by PKT mode:
1902 * The hardware has already acked the complete packet.
1903 * If the target honors our outstanding ATN condition,
1904 * we should be (or soon will be) in MSGOUT phase.
1905 * This will trigger the LQIPHASE_LQ status bit as the
1906 * hardware was expecting another LQ. Unexpected
1907 * busfree detection is enabled. Once LQIPHASE_LQ is
1908 * true (first entry into host message loop is much
1909 * the same), we must clear LQIPHASE_LQ and hit
1910 * LQIRETRY so the hardware is ready to handle
1911 * a future LQ. NONPACKREQ will not be asserted again
1912 * once we hit LQIRETRY until another packet is
1913 * processed. The target may either go busfree
1914 * or start another packet in response to our message.
1915 *
1916 * Read Streaming P0 asserted:
1917 * If we raise ATN and the target completes the entire
1918 * stream (P0 asserted during the last packet), the
1919 * hardware will ack all data and return to the ISTART
1920 * state. When the target reponds to our ATN condition,
1921 * LQIPHASE_LQ will be asserted. We should respond to
1922 * this with an LQIRETRY to prepare for any future
1923 * packets. NONPACKREQ will not be asserted again
1924 * once we hit LQIRETRY until another packet is
1925 * processed. The target may either go busfree or
1926 * start another packet in response to our message.
1927 * Busfree detection is enabled.
1928 *
1929 * Read Streaming P0 not asserted:
1930 * If we raise ATN and the target transitions to
1931 * MSGOUT in or after a packet where P0 is not
1932 * asserted, the hardware will assert LQIPHASE_NLQ.
1933 * We should respond to the LQIPHASE_NLQ with an
1934 * LQIRETRY. Should the target stay in a non-pkt
1935 * phase after we send our message, the hardware
1936 * will assert LQIPHASE_LQ. Recovery is then just as
1937 * listed above for the read streaming with P0 asserted.
1938 * Busfree detection is enabled.
1939 */
1940 if (silent == FALSE)
1941 printf("LQICRC_NLQ\n");
1942 if (scb == NULL) {
1943 printf("%s: No SCB valid for LQICRC_NLQ. "
1944 "Resetting bus\n", ahd_name(ahd));
1945 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1946 return;
1947 }
1948 } else if ((lqistat1 & LQIBADLQI) != 0) {
1949 printf("Need to handle BADLQI!\n");
1950 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1951 return;
1952 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1953 if ((curphase & ~P_DATAIN_DT) != 0) {
1954 /* Ack the byte. So we can continue. */
1955 if (silent == FALSE)
1956 printf("Acking %s to clear perror\n",
1957 ahd_lookup_phase_entry(curphase)->phasemsg);
1958 ahd_inb(ahd, SCSIDAT);
1959 }
1960
1961 if (curphase == P_MESGIN)
1962 msg_out = MSG_PARITY_ERROR;
1963 }
1964
1965 /*
1966 * We've set the hardware to assert ATN if we
1967 * get a parity error on "in" phases, so all we
1968 * need to do is stuff the message buffer with
1969 * the appropriate message. "In" phases have set
1970 * mesg_out to something other than MSG_NOP.
1971 */
1972 ahd->send_msg_perror = msg_out;
1973 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1974 scb->flags |= SCB_TRANSMISSION_ERROR;
1975 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1976 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1977 ahd_unpause(ahd);
1978 }
1979
1980 static void
1981 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1982 {
1983 /*
1984 * Clear the sources of the interrupts.
1985 */
1986 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1987 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1988
1989 /*
1990 * If the "illegal" phase changes were in response
1991 * to our ATN to flag a CRC error, AND we ended up
1992 * on packet boundaries, clear the error, restart the
1993 * LQI manager as appropriate, and go on our merry
1994 * way toward sending the message. Otherwise, reset
1995 * the bus to clear the error.
1996 */
1997 ahd_set_active_fifo(ahd);
1998 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
1999 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
2000 if ((lqistat1 & LQIPHASE_LQ) != 0) {
2001 printf("LQIRETRY for LQIPHASE_LQ\n");
2002 ahd_outb(ahd, LQCTL2, LQIRETRY);
2003 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
2004 printf("LQIRETRY for LQIPHASE_NLQ\n");
2005 ahd_outb(ahd, LQCTL2, LQIRETRY);
2006 } else
2007 panic("ahd_handle_lqiphase_error: No phase errors\n");
2008 ahd_dump_card_state(ahd);
2009 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2010 ahd_unpause(ahd);
2011 } else {
2012 printf("Reseting Channel for LQI Phase error\n");
2013 ahd_dump_card_state(ahd);
2014 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2015 }
2016 }
2017
2018 /*
2019 * Packetized unexpected or expected busfree.
2020 * Entered in mode based on busfreetime.
2021 */
2022 static int
2023 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2024 {
2025 u_int lqostat1;
2026
2027 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2028 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2029 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2030 if ((lqostat1 & LQOBUSFREE) != 0) {
2031 struct scb *scb;
2032 u_int scbid;
2033 u_int saved_scbptr;
2034 u_int waiting_h;
2035 u_int waiting_t;
2036 u_int next;
2037
2038 /*
2039 * The LQO manager detected an unexpected busfree
2040 * either:
2041 *
2042 * 1) During an outgoing LQ.
2043 * 2) After an outgoing LQ but before the first
2044 * REQ of the command packet.
2045 * 3) During an outgoing command packet.
2046 *
2047 * In all cases, CURRSCB is pointing to the
2048 * SCB that encountered the failure. Clean
2049 * up the queue, clear SELDO and LQOBUSFREE,
2050 * and allow the sequencer to restart the select
2051 * out at its lesure.
2052 */
2053 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2054 scbid = ahd_inw(ahd, CURRSCB);
2055 scb = ahd_lookup_scb(ahd, scbid);
2056 if (scb == NULL)
2057 panic("SCB not valid during LQOBUSFREE");
2058 /*
2059 * Clear the status.
2060 */
2061 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2062 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2063 ahd_outb(ahd, CLRLQOINT1, 0);
2064 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2065 ahd_flush_device_writes(ahd);
2066 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2067
2068 /*
2069 * Return the LQO manager to its idle loop. It will
2070 * not do this automatically if the busfree occurs
2071 * after the first REQ of either the LQ or command
2072 * packet or between the LQ and command packet.
2073 */
2074 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2075
2076 /*
2077 * Update the waiting for selection queue so
2078 * we restart on the correct SCB.
2079 */
2080 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2081 saved_scbptr = ahd_get_scbptr(ahd);
2082 if (waiting_h != scbid) {
2083
2084 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2085 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2086 if (waiting_t == waiting_h) {
2087 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2088 next = SCB_LIST_NULL;
2089 } else {
2090 ahd_set_scbptr(ahd, waiting_h);
2091 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2092 }
2093 ahd_set_scbptr(ahd, scbid);
2094 ahd_outw(ahd, SCB_NEXT2, next);
2095 }
2096 ahd_set_scbptr(ahd, saved_scbptr);
2097 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2098 if (SCB_IS_SILENT(scb) == FALSE) {
2099 ahd_print_path(ahd, scb);
2100 printf("Probable outgoing LQ CRC error. "
2101 "Retrying command\n");
2102 }
2103 scb->crc_retry_count++;
2104 } else {
2105 aic_set_transaction_status(scb, CAM_UNCOR_PARITY);
2106 aic_freeze_scb(scb);
2107 ahd_freeze_devq(ahd, scb);
2108 }
2109 /* Return unpausing the sequencer. */
2110 return (0);
2111 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2112 /*
2113 * Ignore what are really parity errors that
2114 * occur on the last REQ of a free running
2115 * clock prior to going busfree. Some drives
2116 * do not properly active negate just before
2117 * going busfree resulting in a parity glitch.
2118 */
2119 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2120 #ifdef AHD_DEBUG
2121 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2122 printf("%s: Parity on last REQ detected "
2123 "during busfree phase.\n",
2124 ahd_name(ahd));
2125 #endif
2126 /* Return unpausing the sequencer. */
2127 return (0);
2128 }
2129 if (ahd->src_mode != AHD_MODE_SCSI) {
2130 u_int scbid;
2131 struct scb *scb;
2132
2133 scbid = ahd_get_scbptr(ahd);
2134 scb = ahd_lookup_scb(ahd, scbid);
2135 ahd_print_path(ahd, scb);
2136 printf("Unexpected PKT busfree condition\n");
2137 ahd_dump_card_state(ahd);
2138 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2139 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2140 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2141
2142 /* Return restarting the sequencer. */
2143 return (1);
2144 }
2145 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2146 ahd_dump_card_state(ahd);
2147 /* Restart the sequencer. */
2148 return (1);
2149 }
2150
2151 /*
2152 * Non-packetized unexpected or expected busfree.
2153 */
2154 static int
2155 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2156 {
2157 struct ahd_devinfo devinfo;
2158 struct scb *scb;
2159 u_int lastphase;
2160 u_int saved_scsiid;
2161 u_int saved_lun;
2162 u_int target;
2163 u_int initiator_role_id;
2164 u_int scbid;
2165 u_int ppr_busfree;
2166 int printerror;
2167
2168 /*
2169 * Look at what phase we were last in. If its message out,
2170 * chances are pretty good that the busfree was in response
2171 * to one of our abort requests.
2172 */
2173 lastphase = ahd_inb(ahd, LASTPHASE);
2174 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2175 saved_lun = ahd_inb(ahd, SAVED_LUN);
2176 target = SCSIID_TARGET(ahd, saved_scsiid);
2177 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2178 ahd_compile_devinfo(&devinfo, initiator_role_id,
2179 target, saved_lun, 'A', ROLE_INITIATOR);
2180 printerror = 1;
2181
2182 scbid = ahd_get_scbptr(ahd);
2183 scb = ahd_lookup_scb(ahd, scbid);
2184 if (scb != NULL
2185 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2186 scb = NULL;
2187
2188 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2189 if (lastphase == P_MESGOUT) {
2190 u_int tag;
2191
2192 tag = SCB_LIST_NULL;
2193 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2194 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2195 int found;
2196 int sent_msg;
2197
2198 if (scb == NULL) {
2199 ahd_print_devinfo(ahd, &devinfo);
2200 printf("Abort for unidentified "
2201 "connection completed.\n");
2202 /* restart the sequencer. */
2203 return (1);
2204 }
2205 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2206 ahd_print_path(ahd, scb);
2207 printf("SCB %d - Abort%s Completed.\n",
2208 SCB_GET_TAG(scb),
2209 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2210
2211 if (sent_msg == MSG_ABORT_TAG)
2212 tag = SCB_GET_TAG(scb);
2213
2214 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2215 /*
2216 * This abort is in response to an
2217 * unexpected switch to command phase
2218 * for a packetized connection. Since
2219 * the identify message was never sent,
2220 * "saved lun" is 0. We really want to
2221 * abort only the SCB that encountered
2222 * this error, which could have a different
2223 * lun. The SCB will be retried so the OS
2224 * will see the UA after renegotiating to
2225 * packetized.
2226 */
2227 tag = SCB_GET_TAG(scb);
2228 saved_lun = scb->hscb->lun;
2229 }
2230 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2231 tag, ROLE_INITIATOR,
2232 CAM_REQ_ABORTED);
2233 printf("found == 0x%x\n", found);
2234 printerror = 0;
2235 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2236 MSG_BUS_DEV_RESET, TRUE)) {
2237 #ifdef __FreeBSD__
2238 /*
2239 * Don't mark the user's request for this BDR
2240 * as completing with CAM_BDR_SENT. CAM3
2241 * specifies CAM_REQ_CMP.
2242 */
2243 if (scb != NULL
2244 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2245 && ahd_match_scb(ahd, scb, target, 'A',
2246 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2247 ROLE_INITIATOR))
2248 aic_set_transaction_status(scb, CAM_REQ_CMP);
2249 #endif
2250 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2251 CAM_BDR_SENT, "Bus Device Reset",
2252 /*verbose_level*/0);
2253 printerror = 0;
2254 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2255 && ppr_busfree == 0) {
2256 struct ahd_initiator_tinfo *tinfo;
2257 struct ahd_tmode_tstate *tstate;
2258
2259 /*
2260 * PPR Rejected.
2261 *
2262 * If the previous negotiation was packetized,
2263 * this could be because the device has been
2264 * reset without our knowledge. Force our
2265 * current negotiation to async and retry the
2266 * negotiation. Otherwise retry the command
2267 * with non-ppr negotiation.
2268 */
2269 #ifdef AHD_DEBUG
2270 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2271 printf("PPR negotiation rejected busfree.\n");
2272 #endif
2273 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2274 devinfo.our_scsiid,
2275 devinfo.target, &tstate);
2276 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2277 ahd_set_width(ahd, &devinfo,
2278 MSG_EXT_WDTR_BUS_8_BIT,
2279 AHD_TRANS_CUR,
2280 /*paused*/TRUE);
2281 ahd_set_syncrate(ahd, &devinfo,
2282 /*period*/0, /*offset*/0,
2283 /*ppr_options*/0,
2284 AHD_TRANS_CUR,
2285 /*paused*/TRUE);
2286 /*
2287 * The expect PPR busfree handler below
2288 * will effect the retry and necessary
2289 * abort.
2290 */
2291 } else {
2292 tinfo->curr.transport_version = 2;
2293 tinfo->goal.transport_version = 2;
2294 tinfo->goal.ppr_options = 0;
2295 /*
2296 * Remove any SCBs in the waiting for selection
2297 * queue that may also be for this target so
2298 * that command ordering is preserved.
2299 */
2300 ahd_freeze_devq(ahd, scb);
2301 ahd_qinfifo_requeue_tail(ahd, scb);
2302 printerror = 0;
2303 }
2304 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2305 && ppr_busfree == 0) {
2306 /*
2307 * Negotiation Rejected. Go-narrow and
2308 * retry command.
2309 */
2310 #ifdef AHD_DEBUG
2311 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2312 printf("WDTR negotiation rejected busfree.\n");
2313 #endif
2314 ahd_set_width(ahd, &devinfo,
2315 MSG_EXT_WDTR_BUS_8_BIT,
2316 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2317 /*paused*/TRUE);
2318 /*
2319 * Remove any SCBs in the waiting for selection
2320 * queue that may also be for this target so that
2321 * command ordering is preserved.
2322 */
2323 ahd_freeze_devq(ahd, scb);
2324 ahd_qinfifo_requeue_tail(ahd, scb);
2325 printerror = 0;
2326 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2327 && ppr_busfree == 0) {
2328 /*
2329 * Negotiation Rejected. Go-async and
2330 * retry command.
2331 */
2332 #ifdef AHD_DEBUG
2333 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2334 printf("SDTR negotiation rejected busfree.\n");
2335 #endif
2336 ahd_set_syncrate(ahd, &devinfo,
2337 /*period*/0, /*offset*/0,
2338 /*ppr_options*/0,
2339 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2340 /*paused*/TRUE);
2341 /*
2342 * Remove any SCBs in the waiting for selection
2343 * queue that may also be for this target so that
2344 * command ordering is preserved.
2345 */
2346 ahd_freeze_devq(ahd, scb);
2347 ahd_qinfifo_requeue_tail(ahd, scb);
2348 printerror = 0;
2349 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2350 && ahd_sent_msg(ahd, AHDMSG_1B,
2351 MSG_INITIATOR_DET_ERR, TRUE)) {
2352
2353 #ifdef AHD_DEBUG
2354 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2355 printf("Expected IDE Busfree\n");
2356 #endif
2357 printerror = 0;
2358 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2359 && ahd_sent_msg(ahd, AHDMSG_1B,
2360 MSG_MESSAGE_REJECT, TRUE)) {
2361
2362 #ifdef AHD_DEBUG
2363 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2364 printf("Expected QAS Reject Busfree\n");
2365 #endif
2366 printerror = 0;
2367 }
2368 }
2369
2370 /*
2371 * The busfree required flag is honored at the end of
2372 * the message phases. We check it last in case we
2373 * had to send some other message that caused a busfree.
2374 */
2375 if (printerror != 0
2376 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2377 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2378
2379 ahd_freeze_devq(ahd, scb);
2380 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
2381 aic_freeze_scb(scb);
2382 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2383 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2384 SCB_GET_CHANNEL(ahd, scb),
2385 SCB_GET_LUN(scb), SCB_LIST_NULL,
2386 ROLE_INITIATOR, CAM_REQ_ABORTED);
2387 } else {
2388 #ifdef AHD_DEBUG
2389 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2390 printf("PPR Negotiation Busfree.\n");
2391 #endif
2392 ahd_done(ahd, scb);
2393 }
2394 printerror = 0;
2395 }
2396 if (printerror != 0) {
2397 int aborted;
2398
2399 aborted = 0;
2400 if (scb != NULL) {
2401 u_int tag;
2402
2403 if ((scb->hscb->control & TAG_ENB) != 0)
2404 tag = SCB_GET_TAG(scb);
2405 else
2406 tag = SCB_LIST_NULL;
2407 ahd_print_path(ahd, scb);
2408 aborted = ahd_abort_scbs(ahd, target, 'A',
2409 SCB_GET_LUN(scb), tag,
2410 ROLE_INITIATOR,
2411 CAM_UNEXP_BUSFREE);
2412 } else {
2413 /*
2414 * We had not fully identified this connection,
2415 * so we cannot abort anything.
2416 */
2417 printf("%s: ", ahd_name(ahd));
2418 }
2419 printf("Unexpected busfree %s, %d SCBs aborted, "
2420 "PRGMCNT == 0x%x\n",
2421 ahd_lookup_phase_entry(lastphase)->phasemsg,
2422 aborted,
2423 ahd_inw(ahd, PRGMCNT));
2424 ahd_dump_card_state(ahd);
2425 if (lastphase != P_BUSFREE)
2426 ahd_force_renegotiation(ahd, &devinfo);
2427 }
2428 /* Always restart the sequencer. */
2429 return (1);
2430 }
2431
2432 static void
2433 ahd_handle_proto_violation(struct ahd_softc *ahd)
2434 {
2435 struct ahd_devinfo devinfo;
2436 struct scb *scb;
2437 u_int scbid;
2438 u_int seq_flags;
2439 u_int curphase;
2440 u_int lastphase;
2441 int found;
2442
2443 ahd_fetch_devinfo(ahd, &devinfo);
2444 scbid = ahd_get_scbptr(ahd);
2445 scb = ahd_lookup_scb(ahd, scbid);
2446 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2447 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2448 lastphase = ahd_inb(ahd, LASTPHASE);
2449 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2450
2451 /*
2452 * The reconnecting target either did not send an
2453 * identify message, or did, but we didn't find an SCB
2454 * to match.
2455 */
2456 ahd_print_devinfo(ahd, &devinfo);
2457 printf("Target did not send an IDENTIFY message. "
2458 "LASTPHASE = 0x%x.\n", lastphase);
2459 scb = NULL;
2460 } else if (scb == NULL) {
2461 /*
2462 * We don't seem to have an SCB active for this
2463 * transaction. Print an error and reset the bus.
2464 */
2465 ahd_print_devinfo(ahd, &devinfo);
2466 printf("No SCB found during protocol violation\n");
2467 goto proto_violation_reset;
2468 } else {
2469 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2470 if ((seq_flags & NO_CDB_SENT) != 0) {
2471 ahd_print_path(ahd, scb);
2472 printf("No or incomplete CDB sent to device.\n");
2473 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2474 & STATUS_RCVD) == 0) {
2475 /*
2476 * The target never bothered to provide status to
2477 * us prior to completing the command. Since we don't
2478 * know the disposition of this command, we must attempt
2479 * to abort it. Assert ATN and prepare to send an abort
2480 * message.
2481 */
2482 ahd_print_path(ahd, scb);
2483 printf("Completed command without status.\n");
2484 } else {
2485 ahd_print_path(ahd, scb);
2486 printf("Unknown protocol violation.\n");
2487 ahd_dump_card_state(ahd);
2488 }
2489 }
2490 if ((lastphase & ~P_DATAIN_DT) == 0
2491 || lastphase == P_COMMAND) {
2492 proto_violation_reset:
2493 /*
2494 * Target either went directly to data
2495 * phase or didn't respond to our ATN.
2496 * The only safe thing to do is to blow
2497 * it away with a bus reset.
2498 */
2499 found = ahd_reset_channel(ahd, 'A', TRUE);
2500 printf("%s: Issued Channel %c Bus Reset. "
2501 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2502 } else {
2503 /*
2504 * Leave the selection hardware off in case
2505 * this abort attempt will affect yet to
2506 * be sent commands.
2507 */
2508 ahd_outb(ahd, SCSISEQ0,
2509 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2510 ahd_assert_atn(ahd);
2511 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2512 if (scb == NULL) {
2513 ahd_print_devinfo(ahd, &devinfo);
2514 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2515 ahd->msgout_len = 1;
2516 ahd->msgout_index = 0;
2517 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2518 } else {
2519 ahd_print_path(ahd, scb);
2520 scb->flags |= SCB_ABORT;
2521 }
2522 printf("Protocol violation %s. Attempting to abort.\n",
2523 ahd_lookup_phase_entry(curphase)->phasemsg);
2524 }
2525 }
2526
2527 /*
2528 * Force renegotiation to occur the next time we initiate
2529 * a command to the current device.
2530 */
2531 static void
2532 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2533 {
2534 struct ahd_initiator_tinfo *targ_info;
2535 struct ahd_tmode_tstate *tstate;
2536
2537 #ifdef AHD_DEBUG
2538 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2539 ahd_print_devinfo(ahd, devinfo);
2540 printf("Forcing renegotiation\n");
2541 }
2542 #endif
2543 targ_info = ahd_fetch_transinfo(ahd,
2544 devinfo->channel,
2545 devinfo->our_scsiid,
2546 devinfo->target,
2547 &tstate);
2548 ahd_update_neg_request(ahd, devinfo, tstate,
2549 targ_info, AHD_NEG_IF_NON_ASYNC);
2550 }
2551
2552 #define AHD_MAX_STEPS 2000
2553 void
2554 ahd_clear_critical_section(struct ahd_softc *ahd)
2555 {
2556 ahd_mode_state saved_modes;
2557 int stepping;
2558 int steps;
2559 int first_instr;
2560 u_int simode0;
2561 u_int simode1;
2562 u_int simode3;
2563 u_int lqimode0;
2564 u_int lqimode1;
2565 u_int lqomode0;
2566 u_int lqomode1;
2567
2568 if (ahd->num_critical_sections == 0)
2569 return;
2570
2571 stepping = FALSE;
2572 steps = 0;
2573 first_instr = 0;
2574 simode0 = 0;
2575 simode1 = 0;
2576 simode3 = 0;
2577 lqimode0 = 0;
2578 lqimode1 = 0;
2579 lqomode0 = 0;
2580 lqomode1 = 0;
2581 saved_modes = ahd_save_modes(ahd);
2582 for (;;) {
2583 struct cs *cs;
2584 u_int seqaddr;
2585 u_int i;
2586
2587 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2588 seqaddr = ahd_inw(ahd, CURADDR);
2589
2590 cs = ahd->critical_sections;
2591 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2592
2593 if (cs->begin < seqaddr && cs->end >= seqaddr)
2594 break;
2595 }
2596
2597 if (i == ahd->num_critical_sections)
2598 break;
2599
2600 if (steps > AHD_MAX_STEPS) {
2601 printf("%s: Infinite loop in critical section\n"
2602 "%s: First Instruction 0x%x now 0x%x\n",
2603 ahd_name(ahd), ahd_name(ahd), first_instr,
2604 seqaddr);
2605 ahd_dump_card_state(ahd);
2606 panic("critical section loop");
2607 }
2608
2609 steps++;
2610 #ifdef AHD_DEBUG
2611 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2612 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2613 seqaddr);
2614 #endif
2615 if (stepping == FALSE) {
2616
2617 first_instr = seqaddr;
2618 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2619 simode0 = ahd_inb(ahd, SIMODE0);
2620 simode3 = ahd_inb(ahd, SIMODE3);
2621 lqimode0 = ahd_inb(ahd, LQIMODE0);
2622 lqimode1 = ahd_inb(ahd, LQIMODE1);
2623 lqomode0 = ahd_inb(ahd, LQOMODE0);
2624 lqomode1 = ahd_inb(ahd, LQOMODE1);
2625 ahd_outb(ahd, SIMODE0, 0);
2626 ahd_outb(ahd, SIMODE3, 0);
2627 ahd_outb(ahd, LQIMODE0, 0);
2628 ahd_outb(ahd, LQIMODE1, 0);
2629 ahd_outb(ahd, LQOMODE0, 0);
2630 ahd_outb(ahd, LQOMODE1, 0);
2631 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2632 simode1 = ahd_inb(ahd, SIMODE1);
2633 /*
2634 * We don't clear ENBUSFREE. Unfortunately
2635 * we cannot re-enable busfree detection within
2636 * the current connection, so we must leave it
2637 * on while single stepping.
2638 */
2639 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2640 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2641 stepping = TRUE;
2642 }
2643 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2644 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2645 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2646 ahd_outb(ahd, HCNTRL, ahd->unpause);
2647 while (!ahd_is_paused(ahd))
2648 aic_delay(200);
2649 ahd_update_modes(ahd);
2650 }
2651 if (stepping) {
2652 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2653 ahd_outb(ahd, SIMODE0, simode0);
2654 ahd_outb(ahd, SIMODE3, simode3);
2655 ahd_outb(ahd, LQIMODE0, lqimode0);
2656 ahd_outb(ahd, LQIMODE1, lqimode1);
2657 ahd_outb(ahd, LQOMODE0, lqomode0);
2658 ahd_outb(ahd, LQOMODE1, lqomode1);
2659 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2660 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2661 ahd_outb(ahd, SIMODE1, simode1);
2662 /*
2663 * SCSIINT seems to glitch occassionally when
2664 * the interrupt masks are restored. Clear SCSIINT
2665 * one more time so that only persistent errors
2666 * are seen as a real interrupt.
2667 */
2668 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2669 }
2670 ahd_restore_modes(ahd, saved_modes);
2671 }
2672
2673 /*
2674 * Clear any pending interrupt status.
2675 */
2676 void
2677 ahd_clear_intstat(struct ahd_softc *ahd)
2678 {
2679 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2680 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2681 /* Clear any interrupt conditions this may have caused */
2682 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2683 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2684 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2685 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2686 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2687 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2688 |CLRLQOATNPKT|CLRLQOTCRC);
2689 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2690 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2691 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2692 ahd_outb(ahd, CLRLQOINT0, 0);
2693 ahd_outb(ahd, CLRLQOINT1, 0);
2694 }
2695 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2696 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2697 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2698 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2699 |CLRIOERR|CLROVERRUN);
2700 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2701 }
2702
2703 /**************************** Debugging Routines ******************************/
2704 #ifdef AHD_DEBUG
2705 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2706 #endif
2707 void
2708 ahd_print_scb(struct scb *scb)
2709 {
2710 struct hardware_scb *hscb;
2711 int i;
2712
2713 hscb = scb->hscb;
2714 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2715 (void *)scb,
2716 hscb->control,
2717 hscb->scsiid,
2718 hscb->lun,
2719 hscb->cdb_len);
2720 printf("Shared Data: ");
2721 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2722 printf("%#02x", hscb->shared_data.idata.cdb[i]);
2723 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2724 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2725 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2726 aic_le32toh(hscb->datacnt),
2727 aic_le32toh(hscb->sgptr),
2728 SCB_GET_TAG(scb));
2729 ahd_dump_sglist(scb);
2730 }
2731
2732 void
2733 ahd_dump_sglist(struct scb *scb)
2734 {
2735 int i;
2736
2737 if (scb->sg_count > 0) {
2738 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2739 struct ahd_dma64_seg *sg_list;
2740
2741 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2742 for (i = 0; i < scb->sg_count; i++) {
2743 uint64_t addr;
2744 uint32_t len;
2745
2746 addr = aic_le64toh(sg_list[i].addr);
2747 len = aic_le32toh(sg_list[i].len);
2748 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2749 i,
2750 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2751 (uint32_t)(addr & 0xFFFFFFFF),
2752 sg_list[i].len & AHD_SG_LEN_MASK,
2753 (sg_list[i].len & AHD_DMA_LAST_SEG)
2754 ? " Last" : "");
2755 }
2756 } else {
2757 struct ahd_dma_seg *sg_list;
2758
2759 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2760 for (i = 0; i < scb->sg_count; i++) {
2761 uint32_t len;
2762
2763 len = aic_le32toh(sg_list[i].len);
2764 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2765 i,
2766 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2767 aic_le32toh(sg_list[i].addr),
2768 len & AHD_SG_LEN_MASK,
2769 len & AHD_DMA_LAST_SEG ? " Last" : "");
2770 }
2771 }
2772 }
2773 }
2774
2775 /************************* Transfer Negotiation *******************************/
2776 /*
2777 * Allocate per target mode instance (ID we respond to as a target)
2778 * transfer negotiation data structures.
2779 */
2780 static struct ahd_tmode_tstate *
2781 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2782 {
2783 struct ahd_tmode_tstate *master_tstate;
2784 struct ahd_tmode_tstate *tstate;
2785 int i;
2786
2787 master_tstate = ahd->enabled_targets[ahd->our_id];
2788 if (ahd->enabled_targets[scsi_id] != NULL
2789 && ahd->enabled_targets[scsi_id] != master_tstate)
2790 panic("%s: ahd_alloc_tstate - Target already allocated",
2791 ahd_name(ahd));
2792 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
2793 if (tstate == NULL)
2794 return (NULL);
2795
2796 /*
2797 * If we have allocated a master tstate, copy user settings from
2798 * the master tstate (taken from SRAM or the EEPROM) for this
2799 * channel, but reset our current and goal settings to async/narrow
2800 * until an initiator talks to us.
2801 */
2802 if (master_tstate != NULL) {
2803 memcpy(tstate, master_tstate, sizeof(*tstate));
2804 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2805 for (i = 0; i < 16; i++) {
2806 memset(&tstate->transinfo[i].curr, 0,
2807 sizeof(tstate->transinfo[i].curr));
2808 memset(&tstate->transinfo[i].goal, 0,
2809 sizeof(tstate->transinfo[i].goal));
2810 }
2811 } else
2812 memset(tstate, 0, sizeof(*tstate));
2813 ahd->enabled_targets[scsi_id] = tstate;
2814 return (tstate);
2815 }
2816
2817 #ifdef AHD_TARGET_MODE
2818 /*
2819 * Free per target mode instance (ID we respond to as a target)
2820 * transfer negotiation data structures.
2821 */
2822 static void
2823 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2824 {
2825 struct ahd_tmode_tstate *tstate;
2826
2827 /*
2828 * Don't clean up our "master" tstate.
2829 * It has our default user settings.
2830 */
2831 if (scsi_id == ahd->our_id
2832 && force == FALSE)
2833 return;
2834
2835 tstate = ahd->enabled_targets[scsi_id];
2836 if (tstate != NULL)
2837 free(tstate, M_DEVBUF);
2838 ahd->enabled_targets[scsi_id] = NULL;
2839 }
2840 #endif
2841
2842 /*
2843 * Called when we have an active connection to a target on the bus,
2844 * this function finds the nearest period to the input period limited
2845 * by the capabilities of the bus connectivity of and sync settings for
2846 * the target.
2847 */
2848 void
2849 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2850 struct ahd_initiator_tinfo *tinfo,
2851 u_int *period, u_int *ppr_options, role_t role)
2852 {
2853 struct ahd_transinfo *transinfo;
2854 u_int maxsync;
2855
2856 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2857 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2858 maxsync = AHD_SYNCRATE_PACED;
2859 } else {
2860 maxsync = AHD_SYNCRATE_ULTRA;
2861 /* Can't do DT related options on an SE bus */
2862 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2863 }
2864 /*
2865 * Never allow a value higher than our current goal
2866 * period otherwise we may allow a target initiated
2867 * negotiation to go above the limit as set by the
2868 * user. In the case of an initiator initiated
2869 * sync negotiation, we limit based on the user
2870 * setting. This allows the system to still accept
2871 * incoming negotiations even if target initiated
2872 * negotiation is not performed.
2873 */
2874 if (role == ROLE_TARGET)
2875 transinfo = &tinfo->user;
2876 else
2877 transinfo = &tinfo->goal;
2878 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2879 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2880 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2881 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2882 }
2883 if (transinfo->period == 0) {
2884 *period = 0;
2885 *ppr_options = 0;
2886 } else {
2887 *period = MAX(*period, transinfo->period);
2888 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2889 }
2890 }
2891
2892 /*
2893 * Look up the valid period to SCSIRATE conversion in our table.
2894 * Return the period and offset that should be sent to the target
2895 * if this was the beginning of an SDTR.
2896 */
2897 void
2898 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2899 u_int *ppr_options, u_int maxsync)
2900 {
2901 if (*period < maxsync)
2902 *period = maxsync;
2903
2904 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2905 && *period > AHD_SYNCRATE_MIN_DT)
2906 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2907
2908 if (*period > AHD_SYNCRATE_MIN)
2909 *period = 0;
2910
2911 /* Honor PPR option conformance rules. */
2912 if (*period > AHD_SYNCRATE_PACED)
2913 *ppr_options &= ~MSG_EXT_PPR_RTI;
2914
2915 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2916 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2917
2918 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2919 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2920
2921 /* Skip all PACED only entries if IU is not available */
2922 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2923 && *period < AHD_SYNCRATE_DT)
2924 *period = AHD_SYNCRATE_DT;
2925
2926 /* Skip all DT only entries if DT is not available */
2927 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2928 && *period < AHD_SYNCRATE_ULTRA2)
2929 *period = AHD_SYNCRATE_ULTRA2;
2930 }
2931
2932 /*
2933 * Truncate the given synchronous offset to a value the
2934 * current adapter type and syncrate are capable of.
2935 */
2936 void
2937 ahd_validate_offset(struct ahd_softc *ahd,
2938 struct ahd_initiator_tinfo *tinfo,
2939 u_int period, u_int *offset, int wide,
2940 role_t role)
2941 {
2942 u_int maxoffset;
2943
2944 /* Limit offset to what we can do */
2945 if (period == 0)
2946 maxoffset = 0;
2947 else if (period <= AHD_SYNCRATE_PACED) {
2948 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2949 maxoffset = MAX_OFFSET_PACED_BUG;
2950 else
2951 maxoffset = MAX_OFFSET_PACED;
2952 } else
2953 maxoffset = MAX_OFFSET_NON_PACED;
2954 *offset = MIN(*offset, maxoffset);
2955 if (tinfo != NULL) {
2956 if (role == ROLE_TARGET)
2957 *offset = MIN(*offset, tinfo->user.offset);
2958 else
2959 *offset = MIN(*offset, tinfo->goal.offset);
2960 }
2961 }
2962
2963 /*
2964 * Truncate the given transfer width parameter to a value the
2965 * current adapter type is capable of.
2966 */
2967 void
2968 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2969 u_int *bus_width, role_t role)
2970 {
2971 switch (*bus_width) {
2972 default:
2973 if (ahd->features & AHD_WIDE) {
2974 /* Respond Wide */
2975 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2976 break;
2977 }
2978 /* FALLTHROUGH */
2979 case MSG_EXT_WDTR_BUS_8_BIT:
2980 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2981 break;
2982 }
2983 if (tinfo != NULL) {
2984 if (role == ROLE_TARGET)
2985 *bus_width = MIN(tinfo->user.width, *bus_width);
2986 else
2987 *bus_width = MIN(tinfo->goal.width, *bus_width);
2988 }
2989 }
2990
2991 /*
2992 * Update the bitmask of targets for which the controller should
2993 * negotiate with at the next convenient oportunity. This currently
2994 * means the next time we send the initial identify messages for
2995 * a new transaction.
2996 */
2997 int
2998 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2999 struct ahd_tmode_tstate *tstate,
3000 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
3001 {
3002 u_int auto_negotiate_orig;
3003
3004 auto_negotiate_orig = tstate->auto_negotiate;
3005 if (neg_type == AHD_NEG_ALWAYS) {
3006 /*
3007 * Force our "current" settings to be
3008 * unknown so that unless a bus reset
3009 * occurs the need to renegotiate is
3010 * recorded persistently.
3011 */
3012 if ((ahd->features & AHD_WIDE) != 0)
3013 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3014 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3015 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3016 }
3017 if (tinfo->curr.period != tinfo->goal.period
3018 || tinfo->curr.width != tinfo->goal.width
3019 || tinfo->curr.offset != tinfo->goal.offset
3020 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3021 || (neg_type == AHD_NEG_IF_NON_ASYNC
3022 && (tinfo->goal.offset != 0
3023 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3024 || tinfo->goal.ppr_options != 0)))
3025 tstate->auto_negotiate |= devinfo->target_mask;
3026 else
3027 tstate->auto_negotiate &= ~devinfo->target_mask;
3028
3029 return (auto_negotiate_orig != tstate->auto_negotiate);
3030 }
3031
3032 /*
3033 * Update the user/goal/curr tables of synchronous negotiation
3034 * parameters as well as, in the case of a current or active update,
3035 * any data structures on the host controller. In the case of an
3036 * active update, the specified target is currently talking to us on
3037 * the bus, so the transfer parameter update must take effect
3038 * immediately.
3039 */
3040 void
3041 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3042 u_int period, u_int offset, u_int ppr_options,
3043 u_int type, int paused)
3044 {
3045 struct ahd_initiator_tinfo *tinfo;
3046 struct ahd_tmode_tstate *tstate;
3047 u_int old_period;
3048 u_int old_offset;
3049 u_int old_ppr;
3050 int active;
3051 int update_needed;
3052
3053 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3054 update_needed = 0;
3055
3056 if (period == 0 || offset == 0) {
3057 period = 0;
3058 offset = 0;
3059 }
3060
3061 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3062 devinfo->target, &tstate);
3063
3064 if ((type & AHD_TRANS_USER) != 0) {
3065 tinfo->user.period = period;
3066 tinfo->user.offset = offset;
3067 tinfo->user.ppr_options = ppr_options;
3068 }
3069
3070 if ((type & AHD_TRANS_GOAL) != 0) {
3071 tinfo->goal.period = period;
3072 tinfo->goal.offset = offset;
3073 tinfo->goal.ppr_options = ppr_options;
3074 }
3075
3076 old_period = tinfo->curr.period;
3077 old_offset = tinfo->curr.offset;
3078 old_ppr = tinfo->curr.ppr_options;
3079
3080 if ((type & AHD_TRANS_CUR) != 0
3081 && (old_period != period
3082 || old_offset != offset
3083 || old_ppr != ppr_options)) {
3084
3085 update_needed++;
3086
3087 tinfo->curr.period = period;
3088 tinfo->curr.offset = offset;
3089 tinfo->curr.ppr_options = ppr_options;
3090
3091 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3092 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3093 if (bootverbose) {
3094 if (offset != 0) {
3095 int options;
3096
3097 printf("%s: target %d synchronous with "
3098 "period = 0x%x, offset = 0x%x",
3099 ahd_name(ahd), devinfo->target,
3100 period, offset);
3101 options = 0;
3102 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3103 printf("(RDSTRM");
3104 options++;
3105 }
3106 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3107 printf("%s", options ? "|DT" : "(DT");
3108 options++;
3109 }
3110 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3111 printf("%s", options ? "|IU" : "(IU");
3112 options++;
3113 }
3114 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3115 printf("%s", options ? "|RTI" : "(RTI");
3116 options++;
3117 }
3118 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3119 printf("%s", options ? "|QAS" : "(QAS");
3120 options++;
3121 }
3122 if (options != 0)
3123 printf(")\n");
3124 else
3125 printf("\n");
3126 } else {
3127 printf("%s: target %d using "
3128 "asynchronous transfers%s\n",
3129 ahd_name(ahd), devinfo->target,
3130 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3131 ? "(QAS)" : "");
3132 }
3133 }
3134 }
3135 /*
3136 * Always refresh the neg-table to handle the case of the
3137 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3138 * We will always renegotiate in that case if this is a
3139 * packetized request. Also manage the busfree expected flag
3140 * from this common routine so that we catch changes due to
3141 * WDTR or SDTR messages.
3142 */
3143 if ((type & AHD_TRANS_CUR) != 0) {
3144 if (!paused)
3145 ahd_pause(ahd);
3146 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3147 if (!paused)
3148 ahd_unpause(ahd);
3149 if (ahd->msg_type != MSG_TYPE_NONE) {
3150 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3151 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3152 #ifdef AHD_DEBUG
3153 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3154 ahd_print_devinfo(ahd, devinfo);
3155 printf("Expecting IU Change busfree\n");
3156 }
3157 #endif
3158 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3159 | MSG_FLAG_IU_REQ_CHANGED;
3160 }
3161 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3162 #ifdef AHD_DEBUG
3163 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3164 printf("PPR with IU_REQ outstanding\n");
3165 #endif
3166 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3167 }
3168 }
3169 }
3170
3171 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3172 tinfo, AHD_NEG_TO_GOAL);
3173
3174 if (update_needed && active)
3175 ahd_update_pending_scbs(ahd);
3176 }
3177
3178 /*
3179 * Update the user/goal/curr tables of wide negotiation
3180 * parameters as well as, in the case of a current or active update,
3181 * any data structures on the host controller. In the case of an
3182 * active update, the specified target is currently talking to us on
3183 * the bus, so the transfer parameter update must take effect
3184 * immediately.
3185 */
3186 void
3187 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3188 u_int width, u_int type, int paused)
3189 {
3190 struct ahd_initiator_tinfo *tinfo;
3191 struct ahd_tmode_tstate *tstate;
3192 u_int oldwidth;
3193 int active;
3194 int update_needed;
3195
3196 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3197 update_needed = 0;
3198 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3199 devinfo->target, &tstate);
3200
3201 if ((type & AHD_TRANS_USER) != 0)
3202 tinfo->user.width = width;
3203
3204 if ((type & AHD_TRANS_GOAL) != 0)
3205 tinfo->goal.width = width;
3206
3207 oldwidth = tinfo->curr.width;
3208 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3209
3210 update_needed++;
3211
3212 tinfo->curr.width = width;
3213 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3214 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3215 if (bootverbose) {
3216 printf("%s: target %d using %dbit transfers\n",
3217 ahd_name(ahd), devinfo->target,
3218 8 * (0x01 << width));
3219 }
3220 }
3221
3222 if ((type & AHD_TRANS_CUR) != 0) {
3223 if (!paused)
3224 ahd_pause(ahd);
3225 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3226 if (!paused)
3227 ahd_unpause(ahd);
3228 }
3229
3230 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3231 tinfo, AHD_NEG_TO_GOAL);
3232 if (update_needed && active)
3233 ahd_update_pending_scbs(ahd);
3234
3235 }
3236
3237 /*
3238 * Update the current state of tagged queuing for a given target.
3239 */
3240 void
3241 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3242 ahd_queue_alg alg)
3243 {
3244 ahd_platform_set_tags(ahd, devinfo, alg);
3245 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3246 devinfo->lun, AC_TRANSFER_NEG, &alg);
3247 }
3248
3249 static void
3250 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3251 struct ahd_transinfo *tinfo)
3252 {
3253 ahd_mode_state saved_modes;
3254 u_int period;
3255 u_int ppr_opts;
3256 u_int con_opts;
3257 u_int offset;
3258 u_int saved_negoaddr;
3259 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3260
3261 saved_modes = ahd_save_modes(ahd);
3262 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3263
3264 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3265 ahd_outb(ahd, NEGOADDR, devinfo->target);
3266 period = tinfo->period;
3267 offset = tinfo->offset;
3268 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3269 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3270 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3271 con_opts = 0;
3272 if (period == 0)
3273 period = AHD_SYNCRATE_ASYNC;
3274 if (period == AHD_SYNCRATE_160) {
3275
3276 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3277 /*
3278 * When the SPI4 spec was finalized, PACE transfers
3279 * was not made a configurable option in the PPR
3280 * message. Instead it is assumed to be enabled for
3281 * any syncrate faster than 80MHz. Nevertheless,
3282 * Harpoon2A4 allows this to be configurable.
3283 *
3284 * Harpoon2A4 also assumes at most 2 data bytes per
3285 * negotiated REQ/ACK offset. Paced transfers take
3286 * 4, so we must adjust our offset.
3287 */
3288 ppr_opts |= PPROPT_PACE;
3289 offset *= 2;
3290
3291 /*
3292 * Harpoon2A assumed that there would be a
3293 * fallback rate between 160MHz and 80Mhz,
3294 * so 7 is used as the period factor rather
3295 * than 8 for 160MHz.
3296 */
3297 period = AHD_SYNCRATE_REVA_160;
3298 }
3299 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3300 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3301 ~AHD_PRECOMP_MASK;
3302 } else {
3303 /*
3304 * Precomp should be disabled for non-paced transfers.
3305 */
3306 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3307
3308 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3309 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3310 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3311 /*
3312 * Slow down our CRC interval to be
3313 * compatible with non-packetized
3314 * U160 devices that can't handle a
3315 * CRC at full speed.
3316 */
3317 con_opts |= ENSLOWCRC;
3318 }
3319
3320 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3321 /*
3322 * On H2A4, revert to a slower slewrate
3323 * on non-paced transfers.
3324 */
3325 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3326 ~AHD_SLEWRATE_MASK;
3327 }
3328 }
3329
3330 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3331 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3332 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3333 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3334
3335 ahd_outb(ahd, NEGPERIOD, period);
3336 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3337 ahd_outb(ahd, NEGOFFSET, offset);
3338
3339 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3340 con_opts |= WIDEXFER;
3341
3342 /*
3343 * During packetized transfers, the target will
3344 * give us the oportunity to send command packets
3345 * without us asserting attention.
3346 */
3347 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3348 con_opts |= ENAUTOATNO;
3349 ahd_outb(ahd, NEGCONOPTS, con_opts);
3350 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3351 ahd_restore_modes(ahd, saved_modes);
3352 }
3353
3354 /*
3355 * When the transfer settings for a connection change, setup for
3356 * negotiation in pending SCBs to effect the change as quickly as
3357 * possible. We also cancel any negotiations that are scheduled
3358 * for inflight SCBs that have not been started yet.
3359 */
3360 static void
3361 ahd_update_pending_scbs(struct ahd_softc *ahd)
3362 {
3363 struct scb *pending_scb;
3364 int pending_scb_count;
3365 int paused;
3366 u_int saved_scbptr;
3367 ahd_mode_state saved_modes;
3368
3369 /*
3370 * Traverse the pending SCB list and ensure that all of the
3371 * SCBs there have the proper settings. We can only safely
3372 * clear the negotiation required flag (setting requires the
3373 * execution queue to be modified) and this is only possible
3374 * if we are not already attempting to select out for this
3375 * SCB. For this reason, all callers only call this routine
3376 * if we are changing the negotiation settings for the currently
3377 * active transaction on the bus.
3378 */
3379 pending_scb_count = 0;
3380 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3381 struct ahd_devinfo devinfo;
3382 struct ahd_initiator_tinfo *tinfo;
3383 struct ahd_tmode_tstate *tstate;
3384
3385 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3386 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3387 devinfo.our_scsiid,
3388 devinfo.target, &tstate);
3389 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3390 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3391 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3392 pending_scb->hscb->control &= ~MK_MESSAGE;
3393 }
3394 ahd_sync_scb(ahd, pending_scb,
3395 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3396 pending_scb_count++;
3397 }
3398
3399 if (pending_scb_count == 0)
3400 return;
3401
3402 if (ahd_is_paused(ahd)) {
3403 paused = 1;
3404 } else {
3405 paused = 0;
3406 ahd_pause(ahd);
3407 }
3408
3409 /*
3410 * Force the sequencer to reinitialize the selection for
3411 * the command at the head of the execution queue if it
3412 * has already been setup. The negotiation changes may
3413 * effect whether we select-out with ATN. It is only
3414 * safe to clear ENSELO when the bus is not free and no
3415 * selection is in progres or completed.
3416 */
3417 saved_modes = ahd_save_modes(ahd);
3418 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3419 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3420 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3421 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3422 saved_scbptr = ahd_get_scbptr(ahd);
3423 /* Ensure that the hscbs down on the card match the new information */
3424 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3425 u_int scb_tag;
3426 u_int control;
3427
3428 scb_tag = SCB_GET_TAG(pending_scb);
3429 ahd_set_scbptr(ahd, scb_tag);
3430 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3431 control &= ~MK_MESSAGE;
3432 control |= pending_scb->hscb->control & MK_MESSAGE;
3433 ahd_outb(ahd, SCB_CONTROL, control);
3434 }
3435 ahd_set_scbptr(ahd, saved_scbptr);
3436 ahd_restore_modes(ahd, saved_modes);
3437
3438 if (paused == 0)
3439 ahd_unpause(ahd);
3440 }
3441
3442 /**************************** Pathing Information *****************************/
3443 static void
3444 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3445 {
3446 ahd_mode_state saved_modes;
3447 u_int saved_scsiid;
3448 role_t role;
3449 int our_id;
3450
3451 saved_modes = ahd_save_modes(ahd);
3452 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3453
3454 if (ahd_inb(ahd, SSTAT0) & TARGET)
3455 role = ROLE_TARGET;
3456 else
3457 role = ROLE_INITIATOR;
3458
3459 if (role == ROLE_TARGET
3460 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3461 /* We were selected, so pull our id from TARGIDIN */
3462 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3463 } else if (role == ROLE_TARGET)
3464 our_id = ahd_inb(ahd, TOWNID);
3465 else
3466 our_id = ahd_inb(ahd, IOWNID);
3467
3468 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3469 ahd_compile_devinfo(devinfo,
3470 our_id,
3471 SCSIID_TARGET(ahd, saved_scsiid),
3472 ahd_inb(ahd, SAVED_LUN),
3473 SCSIID_CHANNEL(ahd, saved_scsiid),
3474 role);
3475 ahd_restore_modes(ahd, saved_modes);
3476 }
3477
3478 void
3479 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3480 {
3481 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3482 devinfo->target, devinfo->lun);
3483 }
3484
3485 struct ahd_phase_table_entry*
3486 ahd_lookup_phase_entry(int phase)
3487 {
3488 struct ahd_phase_table_entry *entry;
3489 struct ahd_phase_table_entry *last_entry;
3490
3491 /*
3492 * num_phases doesn't include the default entry which
3493 * will be returned if the phase doesn't match.
3494 */
3495 last_entry = &ahd_phase_table[num_phases];
3496 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3497 if (phase == entry->phase)
3498 break;
3499 }
3500 return (entry);
3501 }
3502
3503 void
3504 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3505 u_int lun, char channel, role_t role)
3506 {
3507 devinfo->our_scsiid = our_id;
3508 devinfo->target = target;
3509 devinfo->lun = lun;
3510 devinfo->target_offset = target;
3511 devinfo->channel = channel;
3512 devinfo->role = role;
3513 if (channel == 'B')
3514 devinfo->target_offset += 8;
3515 devinfo->target_mask = (0x01 << devinfo->target_offset);
3516 }
3517
3518 static void
3519 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3520 struct scb *scb)
3521 {
3522 role_t role;
3523 int our_id;
3524
3525 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3526 role = ROLE_INITIATOR;
3527 if ((scb->hscb->control & TARGET_SCB) != 0)
3528 role = ROLE_TARGET;
3529 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3530 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3531 }
3532
3533
3534 /************************ Message Phase Processing ****************************/
3535 /*
3536 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3537 * or enters the initial message out phase, we are interrupted. Fill our
3538 * outgoing message buffer with the appropriate message and beging handing
3539 * the message phase(s) manually.
3540 */
3541 static void
3542 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3543 struct scb *scb)
3544 {
3545 /*
3546 * To facilitate adding multiple messages together,
3547 * each routine should increment the index and len
3548 * variables instead of setting them explicitly.
3549 */
3550 ahd->msgout_index = 0;
3551 ahd->msgout_len = 0;
3552
3553 if (ahd_currently_packetized(ahd))
3554 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3555
3556 if (ahd->send_msg_perror
3557 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3558 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3559 ahd->msgout_len++;
3560 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3561 #ifdef AHD_DEBUG
3562 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3563 printf("Setting up for Parity Error delivery\n");
3564 #endif
3565 return;
3566 } else if (scb == NULL) {
3567 printf("%s: WARNING. No pending message for "
3568 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3569 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3570 ahd->msgout_len++;
3571 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3572 return;
3573 }
3574
3575 if ((scb->flags & SCB_DEVICE_RESET) == 0
3576 && (scb->flags & SCB_PACKETIZED) == 0
3577 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3578 u_int identify_msg;
3579
3580 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3581 if ((scb->hscb->control & DISCENB) != 0)
3582 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3583 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3584 ahd->msgout_len++;
3585
3586 if ((scb->hscb->control & TAG_ENB) != 0) {
3587 ahd->msgout_buf[ahd->msgout_index++] =
3588 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3589 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3590 ahd->msgout_len += 2;
3591 }
3592 }
3593
3594 if (scb->flags & SCB_DEVICE_RESET) {
3595 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3596 ahd->msgout_len++;
3597 ahd_print_path(ahd, scb);
3598 printf("Bus Device Reset Message Sent\n");
3599 /*
3600 * Clear our selection hardware in advance of
3601 * the busfree. We may have an entry in the waiting
3602 * Q for this target, and we don't want to go about
3603 * selecting while we handle the busfree and blow it
3604 * away.
3605 */
3606 ahd_outb(ahd, SCSISEQ0, 0);
3607 } else if ((scb->flags & SCB_ABORT) != 0) {
3608
3609 if ((scb->hscb->control & TAG_ENB) != 0) {
3610 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3611 } else {
3612 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3613 }
3614 ahd->msgout_len++;
3615 ahd_print_path(ahd, scb);
3616 printf("Abort%s Message Sent\n",
3617 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3618 /*
3619 * Clear our selection hardware in advance of
3620 * the busfree. We may have an entry in the waiting
3621 * Q for this target, and we don't want to go about
3622 * selecting while we handle the busfree and blow it
3623 * away.
3624 */
3625 ahd_outb(ahd, SCSISEQ0, 0);
3626 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3627 ahd_build_transfer_msg(ahd, devinfo);
3628 /*
3629 * Clear our selection hardware in advance of potential
3630 * PPR IU status change busfree. We may have an entry in
3631 * the waiting Q for this target, and we don't want to go
3632 * about selecting while we handle the busfree and blow
3633 * it away.
3634 */
3635 ahd_outb(ahd, SCSISEQ0, 0);
3636 } else {
3637 printf("ahd_intr: AWAITING_MSG for an SCB that "
3638 "does not have a waiting message\n");
3639 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3640 devinfo->target_mask);
3641 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3642 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3643 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3644 scb->flags);
3645 }
3646
3647 /*
3648 * Clear the MK_MESSAGE flag from the SCB so we aren't
3649 * asked to send this message again.
3650 */
3651 ahd_outb(ahd, SCB_CONTROL,
3652 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3653 scb->hscb->control &= ~MK_MESSAGE;
3654 ahd->msgout_index = 0;
3655 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3656 }
3657
3658 /*
3659 * Build an appropriate transfer negotiation message for the
3660 * currently active target.
3661 */
3662 static void
3663 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3664 {
3665 /*
3666 * We need to initiate transfer negotiations.
3667 * If our current and goal settings are identical,
3668 * we want to renegotiate due to a check condition.
3669 */
3670 struct ahd_initiator_tinfo *tinfo;
3671 struct ahd_tmode_tstate *tstate;
3672 int dowide;
3673 int dosync;
3674 int doppr;
3675 u_int period;
3676 u_int ppr_options;
3677 u_int offset;
3678
3679 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3680 devinfo->target, &tstate);
3681 /*
3682 * Filter our period based on the current connection.
3683 * If we can't perform DT transfers on this segment (not in LVD
3684 * mode for instance), then our decision to issue a PPR message
3685 * may change.
3686 */
3687 period = tinfo->goal.period;
3688 offset = tinfo->goal.offset;
3689 ppr_options = tinfo->goal.ppr_options;
3690 /* Target initiated PPR is not allowed in the SCSI spec */
3691 if (devinfo->role == ROLE_TARGET)
3692 ppr_options = 0;
3693 ahd_devlimited_syncrate(ahd, tinfo, &period,
3694 &ppr_options, devinfo->role);
3695 dowide = tinfo->curr.width != tinfo->goal.width;
3696 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3697 /*
3698 * Only use PPR if we have options that need it, even if the device
3699 * claims to support it. There might be an expander in the way
3700 * that doesn't.
3701 */
3702 doppr = ppr_options != 0;
3703
3704 if (!dowide && !dosync && !doppr) {
3705 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3706 dosync = tinfo->goal.offset != 0;
3707 }
3708
3709 if (!dowide && !dosync && !doppr) {
3710 /*
3711 * Force async with a WDTR message if we have a wide bus,
3712 * or just issue an SDTR with a 0 offset.
3713 */
3714 if ((ahd->features & AHD_WIDE) != 0)
3715 dowide = 1;
3716 else
3717 dosync = 1;
3718
3719 if (bootverbose) {
3720 ahd_print_devinfo(ahd, devinfo);
3721 printf("Ensuring async\n");
3722 }
3723 }
3724 /* Target initiated PPR is not allowed in the SCSI spec */
3725 if (devinfo->role == ROLE_TARGET)
3726 doppr = 0;
3727
3728 /*
3729 * Both the PPR message and SDTR message require the
3730 * goal syncrate to be limited to what the target device
3731 * is capable of handling (based on whether an LVD->SE
3732 * expander is on the bus), so combine these two cases.
3733 * Regardless, guarantee that if we are using WDTR and SDTR
3734 * messages that WDTR comes first.
3735 */
3736 if (doppr || (dosync && !dowide)) {
3737
3738 offset = tinfo->goal.offset;
3739 ahd_validate_offset(ahd, tinfo, period, &offset,
3740 doppr ? tinfo->goal.width
3741 : tinfo->curr.width,
3742 devinfo->role);
3743 if (doppr) {
3744 ahd_construct_ppr(ahd, devinfo, period, offset,
3745 tinfo->goal.width, ppr_options);
3746 } else {
3747 ahd_construct_sdtr(ahd, devinfo, period, offset);
3748 }
3749 } else {
3750 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3751 }
3752 }
3753
3754 /*
3755 * Build a synchronous negotiation message in our message
3756 * buffer based on the input parameters.
3757 */
3758 static void
3759 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3760 u_int period, u_int offset)
3761 {
3762 if (offset == 0)
3763 period = AHD_ASYNC_XFER_PERIOD;
3764 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3765 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3766 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3767 ahd->msgout_buf[ahd->msgout_index++] = period;
3768 ahd->msgout_buf[ahd->msgout_index++] = offset;
3769 ahd->msgout_len += 5;
3770 if (bootverbose) {
3771 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3772 ahd_name(ahd), devinfo->channel, devinfo->target,
3773 devinfo->lun, period, offset);
3774 }
3775 }
3776
3777 /*
3778 * Build a wide negotiateion message in our message
3779 * buffer based on the input parameters.
3780 */
3781 static void
3782 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3783 u_int bus_width)
3784 {
3785 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3786 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3787 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3788 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3789 ahd->msgout_len += 4;
3790 if (bootverbose) {
3791 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3792 ahd_name(ahd), devinfo->channel, devinfo->target,
3793 devinfo->lun, bus_width);
3794 }
3795 }
3796
3797 /*
3798 * Build a parallel protocol request message in our message
3799 * buffer based on the input parameters.
3800 */
3801 static void
3802 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3803 u_int period, u_int offset, u_int bus_width,
3804 u_int ppr_options)
3805 {
3806 /*
3807 * Always request precompensation from
3808 * the other target if we are running
3809 * at paced syncrates.
3810 */
3811 if (period <= AHD_SYNCRATE_PACED)
3812 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3813 if (offset == 0)
3814 period = AHD_ASYNC_XFER_PERIOD;
3815 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3816 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3817 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3818 ahd->msgout_buf[ahd->msgout_index++] = period;
3819 ahd->msgout_buf[ahd->msgout_index++] = 0;
3820 ahd->msgout_buf[ahd->msgout_index++] = offset;
3821 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3822 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3823 ahd->msgout_len += 8;
3824 if (bootverbose) {
3825 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3826 "offset %x, ppr_options %x\n", ahd_name(ahd),
3827 devinfo->channel, devinfo->target, devinfo->lun,
3828 bus_width, period, offset, ppr_options);
3829 }
3830 }
3831
3832 /*
3833 * Clear any active message state.
3834 */
3835 static void
3836 ahd_clear_msg_state(struct ahd_softc *ahd)
3837 {
3838 ahd_mode_state saved_modes;
3839
3840 saved_modes = ahd_save_modes(ahd);
3841 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3842 ahd->send_msg_perror = 0;
3843 ahd->msg_flags = MSG_FLAG_NONE;
3844 ahd->msgout_len = 0;
3845 ahd->msgin_index = 0;
3846 ahd->msg_type = MSG_TYPE_NONE;
3847 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3848 /*
3849 * The target didn't care to respond to our
3850 * message request, so clear ATN.
3851 */
3852 ahd_outb(ahd, CLRSINT1, CLRATNO);
3853 }
3854 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3855 ahd_outb(ahd, SEQ_FLAGS2,
3856 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3857 ahd_restore_modes(ahd, saved_modes);
3858 }
3859
3860 /*
3861 * Manual message loop handler.
3862 */
3863 static void
3864 ahd_handle_message_phase(struct ahd_softc *ahd)
3865 {
3866 struct ahd_devinfo devinfo;
3867 u_int bus_phase;
3868 int end_session;
3869
3870 ahd_fetch_devinfo(ahd, &devinfo);
3871 end_session = FALSE;
3872 bus_phase = ahd_inb(ahd, LASTPHASE);
3873
3874 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3875 printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3876 ahd_outb(ahd, LQCTL2, LQIRETRY);
3877 }
3878 reswitch:
3879 switch (ahd->msg_type) {
3880 case MSG_TYPE_INITIATOR_MSGOUT:
3881 {
3882 int lastbyte;
3883 int phasemis;
3884 int msgdone;
3885
3886 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3887 panic("HOST_MSG_LOOP interrupt with no active message");
3888
3889 #ifdef AHD_DEBUG
3890 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3891 ahd_print_devinfo(ahd, &devinfo);
3892 printf("INITIATOR_MSG_OUT");
3893 }
3894 #endif
3895 phasemis = bus_phase != P_MESGOUT;
3896 if (phasemis) {
3897 #ifdef AHD_DEBUG
3898 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3899 printf(" PHASEMIS %s\n",
3900 ahd_lookup_phase_entry(bus_phase)
3901 ->phasemsg);
3902 }
3903 #endif
3904 if (bus_phase == P_MESGIN) {
3905 /*
3906 * Change gears and see if
3907 * this messages is of interest to
3908 * us or should be passed back to
3909 * the sequencer.
3910 */
3911 ahd_outb(ahd, CLRSINT1, CLRATNO);
3912 ahd->send_msg_perror = 0;
3913 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3914 ahd->msgin_index = 0;
3915 goto reswitch;
3916 }
3917 end_session = TRUE;
3918 break;
3919 }
3920
3921 if (ahd->send_msg_perror) {
3922 ahd_outb(ahd, CLRSINT1, CLRATNO);
3923 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3924 #ifdef AHD_DEBUG
3925 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3926 printf(" byte 0x%x\n", ahd->send_msg_perror);
3927 #endif
3928 /*
3929 * If we are notifying the target of a CRC error
3930 * during packetized operations, the target is
3931 * within its rights to acknowledge our message
3932 * with a busfree.
3933 */
3934 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3935 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3936 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3937
3938 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3939 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3940 break;
3941 }
3942
3943 msgdone = ahd->msgout_index == ahd->msgout_len;
3944 if (msgdone) {
3945 /*
3946 * The target has requested a retry.
3947 * Re-assert ATN, reset our message index to
3948 * 0, and try again.
3949 */
3950 ahd->msgout_index = 0;
3951 ahd_assert_atn(ahd);
3952 }
3953
3954 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3955 if (lastbyte) {
3956 /* Last byte is signified by dropping ATN */
3957 ahd_outb(ahd, CLRSINT1, CLRATNO);
3958 }
3959
3960 /*
3961 * Clear our interrupt status and present
3962 * the next byte on the bus.
3963 */
3964 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3965 #ifdef AHD_DEBUG
3966 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3967 printf(" byte 0x%x\n",
3968 ahd->msgout_buf[ahd->msgout_index]);
3969 #endif
3970 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3971 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3972 break;
3973 }
3974 case MSG_TYPE_INITIATOR_MSGIN:
3975 {
3976 int phasemis;
3977 int message_done;
3978
3979 #ifdef AHD_DEBUG
3980 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3981 ahd_print_devinfo(ahd, &devinfo);
3982 printf("INITIATOR_MSG_IN");
3983 }
3984 #endif
3985 phasemis = bus_phase != P_MESGIN;
3986 if (phasemis) {
3987 #ifdef AHD_DEBUG
3988 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3989 printf(" PHASEMIS %s\n",
3990 ahd_lookup_phase_entry(bus_phase)
3991 ->phasemsg);
3992 }
3993 #endif
3994 ahd->msgin_index = 0;
3995 if (bus_phase == P_MESGOUT
3996 && (ahd->send_msg_perror != 0
3997 || (ahd->msgout_len != 0
3998 && ahd->msgout_index == 0))) {
3999 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
4000 goto reswitch;
4001 }
4002 end_session = TRUE;
4003 break;
4004 }
4005
4006 /* Pull the byte in without acking it */
4007 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4008 #ifdef AHD_DEBUG
4009 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4010 printf(" byte 0x%x\n",
4011 ahd->msgin_buf[ahd->msgin_index]);
4012 #endif
4013
4014 message_done = ahd_parse_msg(ahd, &devinfo);
4015
4016 if (message_done) {
4017 /*
4018 * Clear our incoming message buffer in case there
4019 * is another message following this one.
4020 */
4021 ahd->msgin_index = 0;
4022
4023 /*
4024 * If this message illicited a response,
4025 * assert ATN so the target takes us to the
4026 * message out phase.
4027 */
4028 if (ahd->msgout_len != 0) {
4029 #ifdef AHD_DEBUG
4030 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4031 ahd_print_devinfo(ahd, &devinfo);
4032 printf("Asserting ATN for response\n");
4033 }
4034 #endif
4035 ahd_assert_atn(ahd);
4036 }
4037 } else
4038 ahd->msgin_index++;
4039
4040 if (message_done == MSGLOOP_TERMINATED) {
4041 end_session = TRUE;
4042 } else {
4043 /* Ack the byte */
4044 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4045 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4046 }
4047 break;
4048 }
4049 case MSG_TYPE_TARGET_MSGIN:
4050 {
4051 int msgdone;
4052 int msgout_request;
4053
4054 /*
4055 * By default, the message loop will continue.
4056 */
4057 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4058
4059 if (ahd->msgout_len == 0)
4060 panic("Target MSGIN with no active message");
4061
4062 /*
4063 * If we interrupted a mesgout session, the initiator
4064 * will not know this until our first REQ. So, we
4065 * only honor mesgout requests after we've sent our
4066 * first byte.
4067 */
4068 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4069 && ahd->msgout_index > 0)
4070 msgout_request = TRUE;
4071 else
4072 msgout_request = FALSE;
4073
4074 if (msgout_request) {
4075
4076 /*
4077 * Change gears and see if
4078 * this messages is of interest to
4079 * us or should be passed back to
4080 * the sequencer.
4081 */
4082 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4083 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4084 ahd->msgin_index = 0;
4085 /* Dummy read to REQ for first byte */
4086 ahd_inb(ahd, SCSIDAT);
4087 ahd_outb(ahd, SXFRCTL0,
4088 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4089 break;
4090 }
4091
4092 msgdone = ahd->msgout_index == ahd->msgout_len;
4093 if (msgdone) {
4094 ahd_outb(ahd, SXFRCTL0,
4095 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4096 end_session = TRUE;
4097 break;
4098 }
4099
4100 /*
4101 * Present the next byte on the bus.
4102 */
4103 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4104 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4105 break;
4106 }
4107 case MSG_TYPE_TARGET_MSGOUT:
4108 {
4109 int lastbyte;
4110 int msgdone;
4111
4112 /*
4113 * By default, the message loop will continue.
4114 */
4115 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4116
4117 /*
4118 * The initiator signals that this is
4119 * the last byte by dropping ATN.
4120 */
4121 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4122
4123 /*
4124 * Read the latched byte, but turn off SPIOEN first
4125 * so that we don't inadvertently cause a REQ for the
4126 * next byte.
4127 */
4128 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4129 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4130 msgdone = ahd_parse_msg(ahd, &devinfo);
4131 if (msgdone == MSGLOOP_TERMINATED) {
4132 /*
4133 * The message is *really* done in that it caused
4134 * us to go to bus free. The sequencer has already
4135 * been reset at this point, so pull the ejection
4136 * handle.
4137 */
4138 return;
4139 }
4140
4141 ahd->msgin_index++;
4142
4143 /*
4144 * XXX Read spec about initiator dropping ATN too soon
4145 * and use msgdone to detect it.
4146 */
4147 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4148 ahd->msgin_index = 0;
4149
4150 /*
4151 * If this message illicited a response, transition
4152 * to the Message in phase and send it.
4153 */
4154 if (ahd->msgout_len != 0) {
4155 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4156 ahd_outb(ahd, SXFRCTL0,
4157 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4158 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4159 ahd->msgin_index = 0;
4160 break;
4161 }
4162 }
4163
4164 if (lastbyte)
4165 end_session = TRUE;
4166 else {
4167 /* Ask for the next byte. */
4168 ahd_outb(ahd, SXFRCTL0,
4169 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4170 }
4171
4172 break;
4173 }
4174 default:
4175 panic("Unknown REQINIT message type");
4176 }
4177
4178 if (end_session) {
4179 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4180 printf("%s: Returning to Idle Loop\n",
4181 ahd_name(ahd));
4182 ahd_clear_msg_state(ahd);
4183
4184 /*
4185 * Perform the equivalent of a clear_target_state.
4186 */
4187 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4188 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4189 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4190 } else {
4191 ahd_clear_msg_state(ahd);
4192 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4193 }
4194 }
4195 }
4196
4197 /*
4198 * See if we sent a particular extended message to the target.
4199 * If "full" is true, return true only if the target saw the full
4200 * message. If "full" is false, return true if the target saw at
4201 * least the first byte of the message.
4202 */
4203 static int
4204 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4205 {
4206 int found;
4207 u_int index;
4208
4209 found = FALSE;
4210 index = 0;
4211
4212 while (index < ahd->msgout_len) {
4213 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4214 u_int end_index;
4215
4216 end_index = index + 1 + ahd->msgout_buf[index + 1];
4217 if (ahd->msgout_buf[index+2] == msgval
4218 && type == AHDMSG_EXT) {
4219
4220 if (full) {
4221 if (ahd->msgout_index > end_index)
4222 found = TRUE;
4223 } else if (ahd->msgout_index > index)
4224 found = TRUE;
4225 }
4226 index = end_index;
4227 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4228 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4229
4230 /* Skip tag type and tag id or residue param*/
4231 index += 2;
4232 } else {
4233 /* Single byte message */
4234 if (type == AHDMSG_1B
4235 && ahd->msgout_index > index
4236 && (ahd->msgout_buf[index] == msgval
4237 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4238 && msgval == MSG_IDENTIFYFLAG)))
4239 found = TRUE;
4240 index++;
4241 }
4242
4243 if (found)
4244 break;
4245 }
4246 return (found);
4247 }
4248
4249 /*
4250 * Wait for a complete incoming message, parse it, and respond accordingly.
4251 */
4252 static int
4253 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4254 {
4255 struct ahd_initiator_tinfo *tinfo;
4256 struct ahd_tmode_tstate *tstate;
4257 int reject;
4258 int done;
4259 int response;
4260
4261 done = MSGLOOP_IN_PROG;
4262 response = FALSE;
4263 reject = FALSE;
4264 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4265 devinfo->target, &tstate);
4266
4267 /*
4268 * Parse as much of the message as is available,
4269 * rejecting it if we don't support it. When
4270 * the entire message is available and has been
4271 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4272 * that we have parsed an entire message.
4273 *
4274 * In the case of extended messages, we accept the length
4275 * byte outright and perform more checking once we know the
4276 * extended message type.
4277 */
4278 switch (ahd->msgin_buf[0]) {
4279 case MSG_DISCONNECT:
4280 case MSG_SAVEDATAPOINTER:
4281 case MSG_CMDCOMPLETE:
4282 case MSG_RESTOREPOINTERS:
4283 case MSG_IGN_WIDE_RESIDUE:
4284 /*
4285 * End our message loop as these are messages
4286 * the sequencer handles on its own.
4287 */
4288 done = MSGLOOP_TERMINATED;
4289 break;
4290 case MSG_MESSAGE_REJECT:
4291 response = ahd_handle_msg_reject(ahd, devinfo);
4292 /* FALLTHROUGH */
4293 case MSG_NOOP:
4294 done = MSGLOOP_MSGCOMPLETE;
4295 break;
4296 case MSG_EXTENDED:
4297 {
4298 /* Wait for enough of the message to begin validation */
4299 if (ahd->msgin_index < 2)
4300 break;
4301 switch (ahd->msgin_buf[2]) {
4302 case MSG_EXT_SDTR:
4303 {
4304 u_int period;
4305 u_int ppr_options;
4306 u_int offset;
4307 u_int saved_offset;
4308
4309 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4310 reject = TRUE;
4311 break;
4312 }
4313
4314 /*
4315 * Wait until we have both args before validating
4316 * and acting on this message.
4317 *
4318 * Add one to MSG_EXT_SDTR_LEN to account for
4319 * the extended message preamble.
4320 */
4321 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4322 break;
4323
4324 period = ahd->msgin_buf[3];
4325 ppr_options = 0;
4326 saved_offset = offset = ahd->msgin_buf[4];
4327 ahd_devlimited_syncrate(ahd, tinfo, &period,
4328 &ppr_options, devinfo->role);
4329 ahd_validate_offset(ahd, tinfo, period, &offset,
4330 tinfo->curr.width, devinfo->role);
4331 if (bootverbose) {
4332 printf("(%s:%c:%d:%d): Received "
4333 "SDTR period %x, offset %x\n\t"
4334 "Filtered to period %x, offset %x\n",
4335 ahd_name(ahd), devinfo->channel,
4336 devinfo->target, devinfo->lun,
4337 ahd->msgin_buf[3], saved_offset,
4338 period, offset);
4339 }
4340 ahd_set_syncrate(ahd, devinfo, period,
4341 offset, ppr_options,
4342 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4343 /*paused*/TRUE);
4344
4345 /*
4346 * See if we initiated Sync Negotiation
4347 * and didn't have to fall down to async
4348 * transfers.
4349 */
4350 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4351 /* We started it */
4352 if (saved_offset != offset) {
4353 /* Went too low - force async */
4354 reject = TRUE;
4355 }
4356 } else {
4357 /*
4358 * Send our own SDTR in reply
4359 */
4360 if (bootverbose
4361 && devinfo->role == ROLE_INITIATOR) {
4362 printf("(%s:%c:%d:%d): Target "
4363 "Initiated SDTR\n",
4364 ahd_name(ahd), devinfo->channel,
4365 devinfo->target, devinfo->lun);
4366 }
4367 ahd->msgout_index = 0;
4368 ahd->msgout_len = 0;
4369 ahd_construct_sdtr(ahd, devinfo,
4370 period, offset);
4371 ahd->msgout_index = 0;
4372 response = TRUE;
4373 }
4374 done = MSGLOOP_MSGCOMPLETE;
4375 break;
4376 }
4377 case MSG_EXT_WDTR:
4378 {
4379 u_int bus_width;
4380 u_int saved_width;
4381 u_int sending_reply;
4382
4383 sending_reply = FALSE;
4384 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4385 reject = TRUE;
4386 break;
4387 }
4388
4389 /*
4390 * Wait until we have our arg before validating
4391 * and acting on this message.
4392 *
4393 * Add one to MSG_EXT_WDTR_LEN to account for
4394 * the extended message preamble.
4395 */
4396 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4397 break;
4398
4399 bus_width = ahd->msgin_buf[3];
4400 saved_width = bus_width;
4401 ahd_validate_width(ahd, tinfo, &bus_width,
4402 devinfo->role);
4403 if (bootverbose) {
4404 printf("(%s:%c:%d:%d): Received WDTR "
4405 "%x filtered to %x\n",
4406 ahd_name(ahd), devinfo->channel,
4407 devinfo->target, devinfo->lun,
4408 saved_width, bus_width);
4409 }
4410
4411 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4412 /*
4413 * Don't send a WDTR back to the
4414 * target, since we asked first.
4415 * If the width went higher than our
4416 * request, reject it.
4417 */
4418 if (saved_width > bus_width) {
4419 reject = TRUE;
4420 printf("(%s:%c:%d:%d): requested %dBit "
4421 "transfers. Rejecting...\n",
4422 ahd_name(ahd), devinfo->channel,
4423 devinfo->target, devinfo->lun,
4424 8 * (0x01 << bus_width));
4425 bus_width = 0;
4426 }
4427 } else {
4428 /*
4429 * Send our own WDTR in reply
4430 */
4431 if (bootverbose
4432 && devinfo->role == ROLE_INITIATOR) {
4433 printf("(%s:%c:%d:%d): Target "
4434 "Initiated WDTR\n",
4435 ahd_name(ahd), devinfo->channel,
4436 devinfo->target, devinfo->lun);
4437 }
4438 ahd->msgout_index = 0;
4439 ahd->msgout_len = 0;
4440 ahd_construct_wdtr(ahd, devinfo, bus_width);
4441 ahd->msgout_index = 0;
4442 response = TRUE;
4443 sending_reply = TRUE;
4444 }
4445 /*
4446 * After a wide message, we are async, but
4447 * some devices don't seem to honor this portion
4448 * of the spec. Force a renegotiation of the
4449 * sync component of our transfer agreement even
4450 * if our goal is async. By updating our width
4451 * after forcing the negotiation, we avoid
4452 * renegotiating for width.
4453 */
4454 ahd_update_neg_request(ahd, devinfo, tstate,
4455 tinfo, AHD_NEG_ALWAYS);
4456 ahd_set_width(ahd, devinfo, bus_width,
4457 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4458 /*paused*/TRUE);
4459 if (sending_reply == FALSE && reject == FALSE) {
4460
4461 /*
4462 * We will always have an SDTR to send.
4463 */
4464 ahd->msgout_index = 0;
4465 ahd->msgout_len = 0;
4466 ahd_build_transfer_msg(ahd, devinfo);
4467 ahd->msgout_index = 0;
4468 response = TRUE;
4469 }
4470 done = MSGLOOP_MSGCOMPLETE;
4471 break;
4472 }
4473 case MSG_EXT_PPR:
4474 {
4475 u_int period;
4476 u_int offset;
4477 u_int bus_width;
4478 u_int ppr_options;
4479 u_int saved_width;
4480 u_int saved_offset;
4481 u_int saved_ppr_options;
4482
4483 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4484 reject = TRUE;
4485 break;
4486 }
4487
4488 /*
4489 * Wait until we have all args before validating
4490 * and acting on this message.
4491 *
4492 * Add one to MSG_EXT_PPR_LEN to account for
4493 * the extended message preamble.
4494 */
4495 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4496 break;
4497
4498 period = ahd->msgin_buf[3];
4499 offset = ahd->msgin_buf[5];
4500 bus_width = ahd->msgin_buf[6];
4501 saved_width = bus_width;
4502 ppr_options = ahd->msgin_buf[7];
4503 /*
4504 * According to the spec, a DT only
4505 * period factor with no DT option
4506 * set implies async.
4507 */
4508 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4509 && period <= 9)
4510 offset = 0;
4511 saved_ppr_options = ppr_options;
4512 saved_offset = offset;
4513
4514 /*
4515 * Transfer options are only available if we
4516 * are negotiating wide.
4517 */
4518 if (bus_width == 0)
4519 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4520
4521 ahd_validate_width(ahd, tinfo, &bus_width,
4522 devinfo->role);
4523 ahd_devlimited_syncrate(ahd, tinfo, &period,
4524 &ppr_options, devinfo->role);
4525 ahd_validate_offset(ahd, tinfo, period, &offset,
4526 bus_width, devinfo->role);
4527
4528 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4529 /*
4530 * If we are unable to do any of the
4531 * requested options (we went too low),
4532 * then we'll have to reject the message.
4533 */
4534 if (saved_width > bus_width
4535 || saved_offset != offset
4536 || saved_ppr_options != ppr_options) {
4537 reject = TRUE;
4538 period = 0;
4539 offset = 0;
4540 bus_width = 0;
4541 ppr_options = 0;
4542 }
4543 } else {
4544 if (devinfo->role != ROLE_TARGET)
4545 printf("(%s:%c:%d:%d): Target "
4546 "Initiated PPR\n",
4547 ahd_name(ahd), devinfo->channel,
4548 devinfo->target, devinfo->lun);
4549 else
4550 printf("(%s:%c:%d:%d): Initiator "
4551 "Initiated PPR\n",
4552 ahd_name(ahd), devinfo->channel,
4553 devinfo->target, devinfo->lun);
4554 ahd->msgout_index = 0;
4555 ahd->msgout_len = 0;
4556 ahd_construct_ppr(ahd, devinfo, period, offset,
4557 bus_width, ppr_options);
4558 ahd->msgout_index = 0;
4559 response = TRUE;
4560 }
4561 if (bootverbose) {
4562 printf("(%s:%c:%d:%d): Received PPR width %x, "
4563 "period %x, offset %x,options %x\n"
4564 "\tFiltered to width %x, period %x, "
4565 "offset %x, options %x\n",
4566 ahd_name(ahd), devinfo->channel,
4567 devinfo->target, devinfo->lun,
4568 saved_width, ahd->msgin_buf[3],
4569 saved_offset, saved_ppr_options,
4570 bus_width, period, offset, ppr_options);
4571 }
4572 ahd_set_width(ahd, devinfo, bus_width,
4573 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4574 /*paused*/TRUE);
4575 ahd_set_syncrate(ahd, devinfo, period,
4576 offset, ppr_options,
4577 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4578 /*paused*/TRUE);
4579
4580 done = MSGLOOP_MSGCOMPLETE;
4581 break;
4582 }
4583 default:
4584 /* Unknown extended message. Reject it. */
4585 reject = TRUE;
4586 break;
4587 }
4588 break;
4589 }
4590 #ifdef AHD_TARGET_MODE
4591 case MSG_BUS_DEV_RESET:
4592 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4593 CAM_BDR_SENT,
4594 "Bus Device Reset Received",
4595 /*verbose_level*/0);
4596 ahd_restart(ahd);
4597 done = MSGLOOP_TERMINATED;
4598 break;
4599 case MSG_ABORT_TAG:
4600 case MSG_ABORT:
4601 case MSG_CLEAR_QUEUE:
4602 {
4603 int tag;
4604
4605 /* Target mode messages */
4606 if (devinfo->role != ROLE_TARGET) {
4607 reject = TRUE;
4608 break;
4609 }
4610 tag = SCB_LIST_NULL;
4611 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4612 tag = ahd_inb(ahd, INITIATOR_TAG);
4613 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4614 devinfo->lun, tag, ROLE_TARGET,
4615 CAM_REQ_ABORTED);
4616
4617 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4618 if (tstate != NULL) {
4619 struct ahd_tmode_lstate* lstate;
4620
4621 lstate = tstate->enabled_luns[devinfo->lun];
4622 if (lstate != NULL) {
4623 ahd_queue_lstate_event(ahd, lstate,
4624 devinfo->our_scsiid,
4625 ahd->msgin_buf[0],
4626 /*arg*/tag);
4627 ahd_send_lstate_events(ahd, lstate);
4628 }
4629 }
4630 ahd_restart(ahd);
4631 done = MSGLOOP_TERMINATED;
4632 break;
4633 }
4634 #endif
4635 case MSG_QAS_REQUEST:
4636 #ifdef AHD_DEBUG
4637 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4638 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4639 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4640 #endif
4641 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4642 /* FALLTHROUGH */
4643 case MSG_TERM_IO_PROC:
4644 default:
4645 reject = TRUE;
4646 break;
4647 }
4648
4649 if (reject) {
4650 /*
4651 * Setup to reject the message.
4652 */
4653 ahd->msgout_index = 0;
4654 ahd->msgout_len = 1;
4655 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4656 done = MSGLOOP_MSGCOMPLETE;
4657 response = TRUE;
4658 }
4659
4660 if (done != MSGLOOP_IN_PROG && !response)
4661 /* Clear the outgoing message buffer */
4662 ahd->msgout_len = 0;
4663
4664 return (done);
4665 }
4666
4667 /*
4668 * Process a message reject message.
4669 */
4670 static int
4671 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4672 {
4673 /*
4674 * What we care about here is if we had an
4675 * outstanding SDTR or WDTR message for this
4676 * target. If we did, this is a signal that
4677 * the target is refusing negotiation.
4678 */
4679 struct scb *scb;
4680 struct ahd_initiator_tinfo *tinfo;
4681 struct ahd_tmode_tstate *tstate;
4682 u_int scb_index;
4683 u_int last_msg;
4684 int response = 0;
4685
4686 scb_index = ahd_get_scbptr(ahd);
4687 scb = ahd_lookup_scb(ahd, scb_index);
4688 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4689 devinfo->our_scsiid,
4690 devinfo->target, &tstate);
4691 /* Might be necessary */
4692 last_msg = ahd_inb(ahd, LAST_MSG);
4693
4694 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4695 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4696 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4697 /*
4698 * Target may not like our SPI-4 PPR Options.
4699 * Attempt to negotiate 80MHz which will turn
4700 * off these options.
4701 */
4702 if (bootverbose) {
4703 printf("(%s:%c:%d:%d): PPR Rejected. "
4704 "Trying simple U160 PPR\n",
4705 ahd_name(ahd), devinfo->channel,
4706 devinfo->target, devinfo->lun);
4707 }
4708 tinfo->goal.period = AHD_SYNCRATE_DT;
4709 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4710 | MSG_EXT_PPR_QAS_REQ
4711 | MSG_EXT_PPR_DT_REQ;
4712 } else {
4713 /*
4714 * Target does not support the PPR message.
4715 * Attempt to negotiate SPI-2 style.
4716 */
4717 if (bootverbose) {
4718 printf("(%s:%c:%d:%d): PPR Rejected. "
4719 "Trying WDTR/SDTR\n",
4720 ahd_name(ahd), devinfo->channel,
4721 devinfo->target, devinfo->lun);
4722 }
4723 tinfo->goal.ppr_options = 0;
4724 tinfo->curr.transport_version = 2;
4725 tinfo->goal.transport_version = 2;
4726 }
4727 ahd->msgout_index = 0;
4728 ahd->msgout_len = 0;
4729 ahd_build_transfer_msg(ahd, devinfo);
4730 ahd->msgout_index = 0;
4731 response = 1;
4732 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4733
4734 /* note 8bit xfers */
4735 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4736 "8bit transfers\n", ahd_name(ahd),
4737 devinfo->channel, devinfo->target, devinfo->lun);
4738 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4739 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4740 /*paused*/TRUE);
4741 /*
4742 * No need to clear the sync rate. If the target
4743 * did not accept the command, our syncrate is
4744 * unaffected. If the target started the negotiation,
4745 * but rejected our response, we already cleared the
4746 * sync rate before sending our WDTR.
4747 */
4748 if (tinfo->goal.offset != tinfo->curr.offset) {
4749
4750 /* Start the sync negotiation */
4751 ahd->msgout_index = 0;
4752 ahd->msgout_len = 0;
4753 ahd_build_transfer_msg(ahd, devinfo);
4754 ahd->msgout_index = 0;
4755 response = 1;
4756 }
4757 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4758 /* note asynch xfers and clear flag */
4759 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4760 /*offset*/0, /*ppr_options*/0,
4761 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4762 /*paused*/TRUE);
4763 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4764 "Using asynchronous transfers\n",
4765 ahd_name(ahd), devinfo->channel,
4766 devinfo->target, devinfo->lun);
4767 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4768 int tag_type;
4769 int mask;
4770
4771 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4772
4773 if (tag_type == MSG_SIMPLE_TASK) {
4774 printf("(%s:%c:%d:%d): refuses tagged commands. "
4775 "Performing non-tagged I/O\n", ahd_name(ahd),
4776 devinfo->channel, devinfo->target, devinfo->lun);
4777 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4778 mask = ~0x23;
4779 } else {
4780 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4781 "Performing simple queue tagged I/O only\n",
4782 ahd_name(ahd), devinfo->channel, devinfo->target,
4783 devinfo->lun, tag_type == MSG_ORDERED_TASK
4784 ? "ordered" : "head of queue");
4785 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4786 mask = ~0x03;
4787 }
4788
4789 /*
4790 * Resend the identify for this CCB as the target
4791 * may believe that the selection is invalid otherwise.
4792 */
4793 ahd_outb(ahd, SCB_CONTROL,
4794 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4795 scb->hscb->control &= mask;
4796 aic_set_transaction_tag(scb, /*enabled*/FALSE,
4797 /*type*/MSG_SIMPLE_TASK);
4798 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4799 ahd_assert_atn(ahd);
4800 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4801 SCB_GET_TAG(scb));
4802
4803 /*
4804 * Requeue all tagged commands for this target
4805 * currently in our posession so they can be
4806 * converted to untagged commands.
4807 */
4808 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4809 SCB_GET_CHANNEL(ahd, scb),
4810 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4811 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4812 SEARCH_COMPLETE);
4813 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4814 /*
4815 * Most likely the device believes that we had
4816 * previously negotiated packetized.
4817 */
4818 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4819 | MSG_FLAG_IU_REQ_CHANGED;
4820
4821 ahd_force_renegotiation(ahd, devinfo);
4822 ahd->msgout_index = 0;
4823 ahd->msgout_len = 0;
4824 ahd_build_transfer_msg(ahd, devinfo);
4825 ahd->msgout_index = 0;
4826 response = 1;
4827 } else {
4828 /*
4829 * Otherwise, we ignore it.
4830 */
4831 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4832 ahd_name(ahd), devinfo->channel, devinfo->target,
4833 last_msg);
4834 }
4835 return (response);
4836 }
4837
4838 /*
4839 * Process an ingnore wide residue message.
4840 */
4841 static void
4842 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4843 {
4844 u_int scb_index;
4845 struct scb *scb;
4846
4847 scb_index = ahd_get_scbptr(ahd);
4848 scb = ahd_lookup_scb(ahd, scb_index);
4849 /*
4850 * XXX Actually check data direction in the sequencer?
4851 * Perhaps add datadir to some spare bits in the hscb?
4852 */
4853 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4854 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
4855 /*
4856 * Ignore the message if we haven't
4857 * seen an appropriate data phase yet.
4858 */
4859 } else {
4860 /*
4861 * If the residual occurred on the last
4862 * transfer and the transfer request was
4863 * expected to end on an odd count, do
4864 * nothing. Otherwise, subtract a byte
4865 * and update the residual count accordingly.
4866 */
4867 uint32_t sgptr;
4868
4869 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4870 if ((sgptr & SG_LIST_NULL) != 0
4871 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4872 & SCB_XFERLEN_ODD) != 0) {
4873 /*
4874 * If the residual occurred on the last
4875 * transfer and the transfer request was
4876 * expected to end on an odd count, do
4877 * nothing.
4878 */
4879 } else {
4880 uint32_t data_cnt;
4881 uint64_t data_addr;
4882 uint32_t sglen;
4883
4884 /* Pull in the rest of the sgptr */
4885 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4886 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4887 if ((sgptr & SG_LIST_NULL) != 0) {
4888 /*
4889 * The residual data count is not updated
4890 * for the command run to completion case.
4891 * Explicitly zero the count.
4892 */
4893 data_cnt &= ~AHD_SG_LEN_MASK;
4894 }
4895 data_addr = ahd_inq(ahd, SHADDR);
4896 data_cnt += 1;
4897 data_addr -= 1;
4898 sgptr &= SG_PTR_MASK;
4899 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4900 struct ahd_dma64_seg *sg;
4901
4902 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4903
4904 /*
4905 * The residual sg ptr points to the next S/G
4906 * to load so we must go back one.
4907 */
4908 sg--;
4909 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4910 if (sg != scb->sg_list
4911 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4912
4913 sg--;
4914 sglen = aic_le32toh(sg->len);
4915 /*
4916 * Preserve High Address and SG_LIST
4917 * bits while setting the count to 1.
4918 */
4919 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4920 data_addr = aic_le64toh(sg->addr)
4921 + (sglen & AHD_SG_LEN_MASK)
4922 - 1;
4923
4924 /*
4925 * Increment sg so it points to the
4926 * "next" sg.
4927 */
4928 sg++;
4929 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4930 sg);
4931 }
4932 } else {
4933 struct ahd_dma_seg *sg;
4934
4935 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4936
4937 /*
4938 * The residual sg ptr points to the next S/G
4939 * to load so we must go back one.
4940 */
4941 sg--;
4942 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4943 if (sg != scb->sg_list
4944 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4945
4946 sg--;
4947 sglen = aic_le32toh(sg->len);
4948 /*
4949 * Preserve High Address and SG_LIST
4950 * bits while setting the count to 1.
4951 */
4952 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4953 data_addr = aic_le32toh(sg->addr)
4954 + (sglen & AHD_SG_LEN_MASK)
4955 - 1;
4956
4957 /*
4958 * Increment sg so it points to the
4959 * "next" sg.
4960 */
4961 sg++;
4962 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4963 sg);
4964 }
4965 }
4966 /*
4967 * Toggle the "oddness" of the transfer length
4968 * to handle this mid-transfer ignore wide
4969 * residue. This ensures that the oddness is
4970 * correct for subsequent data transfers.
4971 */
4972 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4973 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4974 ^ SCB_XFERLEN_ODD);
4975
4976 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4977 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4978 /*
4979 * The FIFO's pointers will be updated if/when the
4980 * sequencer re-enters a data phase.
4981 */
4982 }
4983 }
4984 }
4985
4986
4987 /*
4988 * Reinitialize the data pointers for the active transfer
4989 * based on its current residual.
4990 */
4991 static void
4992 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
4993 {
4994 struct scb *scb;
4995 ahd_mode_state saved_modes;
4996 u_int scb_index;
4997 u_int wait;
4998 uint32_t sgptr;
4999 uint32_t resid;
5000 uint64_t dataptr;
5001
5002 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
5003 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
5004
5005 scb_index = ahd_get_scbptr(ahd);
5006 scb = ahd_lookup_scb(ahd, scb_index);
5007
5008 /*
5009 * Release and reacquire the FIFO so we
5010 * have a clean slate.
5011 */
5012 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5013 wait = 1000;
5014 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5015 aic_delay(100);
5016 if (wait == 0) {
5017 ahd_print_path(ahd, scb);
5018 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5019 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5020 }
5021 saved_modes = ahd_save_modes(ahd);
5022 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5023 ahd_outb(ahd, DFFSTAT,
5024 ahd_inb(ahd, DFFSTAT)
5025 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5026
5027 /*
5028 * Determine initial values for data_addr and data_cnt
5029 * for resuming the data phase.
5030 */
5031 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5032 sgptr &= SG_PTR_MASK;
5033
5034 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5035 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5036 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5037
5038 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5039 struct ahd_dma64_seg *sg;
5040
5041 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5042
5043 /* The residual sg_ptr always points to the next sg */
5044 sg--;
5045
5046 dataptr = aic_le64toh(sg->addr)
5047 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5048 - resid;
5049 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5050 } else {
5051 struct ahd_dma_seg *sg;
5052
5053 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5054
5055 /* The residual sg_ptr always points to the next sg */
5056 sg--;
5057
5058 dataptr = aic_le32toh(sg->addr)
5059 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5060 - resid;
5061 ahd_outb(ahd, HADDR + 4,
5062 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5063 }
5064 ahd_outl(ahd, HADDR, dataptr);
5065 ahd_outb(ahd, HCNT + 2, resid >> 16);
5066 ahd_outb(ahd, HCNT + 1, resid >> 8);
5067 ahd_outb(ahd, HCNT, resid);
5068 }
5069
5070 /*
5071 * Handle the effects of issuing a bus device reset message.
5072 */
5073 static void
5074 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5075 u_int lun, cam_status status, char *message,
5076 int verbose_level)
5077 {
5078 #ifdef AHD_TARGET_MODE
5079 struct ahd_tmode_tstate* tstate;
5080 #endif
5081 int found;
5082
5083 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5084 lun, SCB_LIST_NULL, devinfo->role,
5085 status);
5086
5087 #ifdef AHD_TARGET_MODE
5088 /*
5089 * Send an immediate notify ccb to all target mord peripheral
5090 * drivers affected by this action.
5091 */
5092 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5093 if (tstate != NULL) {
5094 u_int cur_lun;
5095 u_int max_lun;
5096
5097 if (lun != CAM_LUN_WILDCARD) {
5098 cur_lun = 0;
5099 max_lun = AHD_NUM_LUNS - 1;
5100 } else {
5101 cur_lun = lun;
5102 max_lun = lun;
5103 }
5104 for (cur_lun <= max_lun; cur_lun++) {
5105 struct ahd_tmode_lstate* lstate;
5106
5107 lstate = tstate->enabled_luns[cur_lun];
5108 if (lstate == NULL)
5109 continue;
5110
5111 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5112 MSG_BUS_DEV_RESET, /*arg*/0);
5113 ahd_send_lstate_events(ahd, lstate);
5114 }
5115 }
5116 #endif
5117
5118 /*
5119 * Go back to async/narrow transfers and renegotiate.
5120 */
5121 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5122 AHD_TRANS_CUR, /*paused*/TRUE);
5123 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5124 /*ppr_options*/0, AHD_TRANS_CUR,
5125 /*paused*/TRUE);
5126
5127 if (status != CAM_SEL_TIMEOUT)
5128 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5129 lun, AC_SENT_BDR, NULL);
5130
5131 if (message != NULL
5132 && (verbose_level <= bootverbose))
5133 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5134 message, devinfo->channel, devinfo->target, found);
5135 }
5136
5137 #ifdef AHD_TARGET_MODE
5138 static void
5139 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5140 struct scb *scb)
5141 {
5142
5143 /*
5144 * To facilitate adding multiple messages together,
5145 * each routine should increment the index and len
5146 * variables instead of setting them explicitly.
5147 */
5148 ahd->msgout_index = 0;
5149 ahd->msgout_len = 0;
5150
5151 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5152 ahd_build_transfer_msg(ahd, devinfo);
5153 else
5154 panic("ahd_intr: AWAITING target message with no message");
5155
5156 ahd->msgout_index = 0;
5157 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5158 }
5159 #endif
5160 /**************************** Initialization **********************************/
5161 static u_int
5162 ahd_sglist_size(struct ahd_softc *ahd)
5163 {
5164 bus_size_t list_size;
5165
5166 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5167 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5168 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5169 return (list_size);
5170 }
5171
5172 /*
5173 * Calculate the optimum S/G List allocation size. S/G elements used
5174 * for a given transaction must be physically contiguous. Assume the
5175 * OS will allocate full pages to us, so it doesn't make sense to request
5176 * less than a page.
5177 */
5178 static u_int
5179 ahd_sglist_allocsize(struct ahd_softc *ahd)
5180 {
5181 bus_size_t sg_list_increment;
5182 bus_size_t sg_list_size;
5183 bus_size_t max_list_size;
5184 bus_size_t best_list_size;
5185
5186 /* Start out with the minimum required for AHD_NSEG. */
5187 sg_list_increment = ahd_sglist_size(ahd);
5188 sg_list_size = sg_list_increment;
5189
5190 /* Get us as close as possible to a page in size. */
5191 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5192 sg_list_size += sg_list_increment;
5193
5194 /*
5195 * Try to reduce the amount of wastage by allocating
5196 * multiple pages.
5197 */
5198 best_list_size = sg_list_size;
5199 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5200 if (max_list_size < 4 * PAGE_SIZE)
5201 max_list_size = 4 * PAGE_SIZE;
5202 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5203 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5204 while ((sg_list_size + sg_list_increment) <= max_list_size
5205 && (sg_list_size % PAGE_SIZE) != 0) {
5206 bus_size_t new_mod;
5207 bus_size_t best_mod;
5208
5209 sg_list_size += sg_list_increment;
5210 new_mod = sg_list_size % PAGE_SIZE;
5211 best_mod = best_list_size % PAGE_SIZE;
5212 if (new_mod > best_mod || new_mod == 0) {
5213 best_list_size = sg_list_size;
5214 }
5215 }
5216 return (best_list_size);
5217 }
5218
5219 /*
5220 * Allocate a controller structure for a new device
5221 * and perform initial initializion.
5222 */
5223 struct ahd_softc *
5224 ahd_alloc(void *platform_arg, char *name)
5225 {
5226 struct ahd_softc *ahd;
5227
5228 #ifndef __FreeBSD__
5229 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT);
5230 if (!ahd) {
5231 printf("aic7xxx: cannot malloc softc!\n");
5232 free(name, M_DEVBUF);
5233 return NULL;
5234 }
5235 #else
5236 ahd = device_get_softc((device_t)platform_arg);
5237 #endif
5238 memset(ahd, 0, sizeof(*ahd));
5239 ahd->seep_config = malloc(sizeof(*ahd->seep_config),
5240 M_DEVBUF, M_NOWAIT);
5241 if (ahd->seep_config == NULL) {
5242 #ifndef __FreeBSD__
5243 free(ahd, M_DEVBUF);
5244 #endif
5245 free(name, M_DEVBUF);
5246 return (NULL);
5247 }
5248 LIST_INIT(&ahd->pending_scbs);
5249 /* We don't know our unit number until the OSM sets it */
5250 ahd->name = name;
5251 ahd->unit = -1;
5252 ahd->description = NULL;
5253 ahd->bus_description = NULL;
5254 ahd->channel = 'A';
5255 ahd->chip = AHD_NONE;
5256 ahd->features = AHD_FENONE;
5257 ahd->bugs = AHD_BUGNONE;
5258 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5259 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5260 aic_timer_init(&ahd->reset_timer);
5261 aic_timer_init(&ahd->stat_timer);
5262 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5263 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5264 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5265 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5266 ahd->int_coalescing_stop_threshold =
5267 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5268
5269 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5270 ahd_free(ahd);
5271 ahd = NULL;
5272 }
5273 #ifdef AHD_DEBUG
5274 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5275 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5276 ahd_name(ahd), (u_int)sizeof(struct scb),
5277 (u_int)sizeof(struct hardware_scb));
5278 }
5279 #endif
5280 return (ahd);
5281 }
5282
5283 int
5284 ahd_softc_init(struct ahd_softc *ahd)
5285 {
5286
5287 ahd->unpause = 0;
5288 ahd->pause = PAUSE;
5289 return (0);
5290 }
5291
5292 void
5293 ahd_softc_insert(struct ahd_softc *ahd)
5294 {
5295 struct ahd_softc *list_ahd;
5296
5297 #if AIC_PCI_CONFIG > 0
5298 /*
5299 * Second Function PCI devices need to inherit some
5300 * settings from function 0.
5301 */
5302 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5303 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5304 aic_dev_softc_t list_pci;
5305 aic_dev_softc_t pci;
5306
5307 list_pci = list_ahd->dev_softc;
5308 pci = ahd->dev_softc;
5309 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
5310 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
5311 struct ahd_softc *master;
5312 struct ahd_softc *slave;
5313
5314 if (aic_get_pci_function(list_pci) == 0) {
5315 master = list_ahd;
5316 slave = ahd;
5317 } else {
5318 master = ahd;
5319 slave = list_ahd;
5320 }
5321 slave->flags &= ~AHD_BIOS_ENABLED;
5322 slave->flags |=
5323 master->flags & AHD_BIOS_ENABLED;
5324 break;
5325 }
5326 }
5327 }
5328 #endif
5329
5330 /*
5331 * Insertion sort into our list of softcs.
5332 */
5333 list_ahd = TAILQ_FIRST(&ahd_tailq);
5334 while (list_ahd != NULL
5335 && ahd_softc_comp(ahd, list_ahd) <= 0)
5336 list_ahd = TAILQ_NEXT(list_ahd, links);
5337 if (list_ahd != NULL)
5338 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5339 else
5340 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5341 ahd->init_level++;
5342 }
5343
5344 /*
5345 * Verify that the passed in softc pointer is for a
5346 * controller that is still configured.
5347 */
5348 struct ahd_softc *
5349 ahd_find_softc(struct ahd_softc *ahd)
5350 {
5351 struct ahd_softc *list_ahd;
5352
5353 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5354 if (list_ahd == ahd)
5355 return (ahd);
5356 }
5357 return (NULL);
5358 }
5359
5360 void
5361 ahd_set_unit(struct ahd_softc *ahd, int unit)
5362 {
5363 ahd->unit = unit;
5364 }
5365
5366 void
5367 ahd_set_name(struct ahd_softc *ahd, char *name)
5368 {
5369 if (ahd->name != NULL)
5370 free(ahd->name, M_DEVBUF);
5371 ahd->name = name;
5372 }
5373
5374 void
5375 ahd_free(struct ahd_softc *ahd)
5376 {
5377 int i;
5378
5379 ahd_terminate_recovery_thread(ahd);
5380 switch (ahd->init_level) {
5381 default:
5382 case 5:
5383 ahd_shutdown(ahd);
5384 /* FALLTHROUGH */
5385 case 4:
5386 aic_dmamap_unload(ahd, ahd->shared_data_dmat,
5387 ahd->shared_data_map.dmamap);
5388 /* FALLTHROUGH */
5389 case 3:
5390 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5391 ahd->shared_data_map.dmamap);
5392 aic_dmamap_destroy(ahd, ahd->shared_data_dmat,
5393 ahd->shared_data_map.dmamap);
5394 /* FALLTHROUGH */
5395 case 2:
5396 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5397 case 1:
5398 #ifndef __linux__
5399 aic_dma_tag_destroy(ahd, ahd->buffer_dmat);
5400 #endif
5401 break;
5402 case 0:
5403 break;
5404 }
5405
5406 #ifndef __linux__
5407 aic_dma_tag_destroy(ahd, ahd->parent_dmat);
5408 #endif
5409 ahd_platform_free(ahd);
5410 ahd_fini_scbdata(ahd);
5411 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5412 struct ahd_tmode_tstate *tstate;
5413
5414 tstate = ahd->enabled_targets[i];
5415 if (tstate != NULL) {
5416 #if AHD_TARGET_MODE
5417 int j;
5418
5419 for (j = 0; j < AHD_NUM_LUNS; j++) {
5420 struct ahd_tmode_lstate *lstate;
5421
5422 lstate = tstate->enabled_luns[j];
5423 if (lstate != NULL) {
5424 xpt_free_path(lstate->path);
5425 free(lstate, M_DEVBUF);
5426 }
5427 }
5428 #endif
5429 free(tstate, M_DEVBUF);
5430 }
5431 }
5432 #if AHD_TARGET_MODE
5433 if (ahd->black_hole != NULL) {
5434 xpt_free_path(ahd->black_hole->path);
5435 free(ahd->black_hole, M_DEVBUF);
5436 }
5437 #endif
5438 if (ahd->name != NULL)
5439 free(ahd->name, M_DEVBUF);
5440 if (ahd->seep_config != NULL)
5441 free(ahd->seep_config, M_DEVBUF);
5442 if (ahd->saved_stack != NULL)
5443 free(ahd->saved_stack, M_DEVBUF);
5444 #ifndef __FreeBSD__
5445 free(ahd, M_DEVBUF);
5446 #endif
5447 return;
5448 }
5449
5450 void
5451 ahd_shutdown(void *arg)
5452 {
5453 struct ahd_softc *ahd;
5454
5455 ahd = (struct ahd_softc *)arg;
5456
5457 /*
5458 * Stop periodic timer callbacks.
5459 */
5460 aic_timer_stop(&ahd->reset_timer);
5461 aic_timer_stop(&ahd->stat_timer);
5462
5463 /* This will reset most registers to 0, but not all */
5464 ahd_reset(ahd, /*reinit*/FALSE);
5465 }
5466
5467 /*
5468 * Reset the controller and record some information about it
5469 * that is only available just after a reset. If "reinit" is
5470 * non-zero, this reset occured after initial configuration
5471 * and the caller requests that the chip be fully reinitialized
5472 * to a runable state. Chip interrupts are *not* enabled after
5473 * a reinitialization. The caller must enable interrupts via
5474 * ahd_intr_enable().
5475 */
5476 int
5477 ahd_reset(struct ahd_softc *ahd, int reinit)
5478 {
5479 u_int sxfrctl1;
5480 int wait;
5481 uint32_t cmd;
5482
5483 /*
5484 * Preserve the value of the SXFRCTL1 register for all channels.
5485 * It contains settings that affect termination and we don't want
5486 * to disturb the integrity of the bus.
5487 */
5488 ahd_pause(ahd);
5489 ahd_update_modes(ahd);
5490 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5491 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5492
5493 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5494 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5495 uint32_t mod_cmd;
5496
5497 /*
5498 * A4 Razor #632
5499 * During the assertion of CHIPRST, the chip
5500 * does not disable its parity logic prior to
5501 * the start of the reset. This may cause a
5502 * parity error to be detected and thus a
5503 * spurious SERR or PERR assertion. Disble
5504 * PERR and SERR responses during the CHIPRST.
5505 */
5506 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5507 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5508 mod_cmd, /*bytes*/2);
5509 }
5510 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5511
5512 /*
5513 * Ensure that the reset has finished. We delay 1000us
5514 * prior to reading the register to make sure the chip
5515 * has sufficiently completed its reset to handle register
5516 * accesses.
5517 */
5518 wait = 1000;
5519 do {
5520 aic_delay(1000);
5521 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5522
5523 if (wait == 0) {
5524 printf("%s: WARNING - Failed chip reset! "
5525 "Trying to initialize anyway.\n", ahd_name(ahd));
5526 }
5527 ahd_outb(ahd, HCNTRL, ahd->pause);
5528
5529 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5530 /*
5531 * Clear any latched PCI error status and restore
5532 * previous SERR and PERR response enables.
5533 */
5534 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5535 0xFF, /*bytes*/1);
5536 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5537 cmd, /*bytes*/2);
5538 }
5539
5540 /*
5541 * Mode should be SCSI after a chip reset, but lets
5542 * set it just to be safe. We touch the MODE_PTR
5543 * register directly so as to bypass the lazy update
5544 * code in ahd_set_modes().
5545 */
5546 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5547 ahd_outb(ahd, MODE_PTR,
5548 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5549
5550 /*
5551 * Restore SXFRCTL1.
5552 *
5553 * We must always initialize STPWEN to 1 before we
5554 * restore the saved values. STPWEN is initialized
5555 * to a tri-state condition which can only be cleared
5556 * by turning it on.
5557 */
5558 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5559 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5560
5561 /* Determine chip configuration */
5562 ahd->features &= ~AHD_WIDE;
5563 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5564 ahd->features |= AHD_WIDE;
5565
5566 /*
5567 * If a recovery action has forced a chip reset,
5568 * re-initialize the chip to our liking.
5569 */
5570 if (reinit != 0)
5571 ahd_chip_init(ahd);
5572
5573 return (0);
5574 }
5575
5576 /*
5577 * Determine the number of SCBs available on the controller
5578 */
5579 int
5580 ahd_probe_scbs(struct ahd_softc *ahd) {
5581 int i;
5582
5583 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5584 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5585 for (i = 0; i < AHD_SCB_MAX; i++) {
5586 int j;
5587
5588 ahd_set_scbptr(ahd, i);
5589 ahd_outw(ahd, SCB_BASE, i);
5590 for (j = 2; j < 64; j++)
5591 ahd_outb(ahd, SCB_BASE+j, 0);
5592 /* Start out life as unallocated (needing an abort) */
5593 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5594 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5595 break;
5596 ahd_set_scbptr(ahd, 0);
5597 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5598 break;
5599 }
5600 return (i);
5601 }
5602
5603 static void
5604 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5605 {
5606 bus_addr_t *baddr;
5607
5608 baddr = (bus_addr_t *)arg;
5609 *baddr = segs->ds_addr;
5610 }
5611
5612 static void
5613 ahd_initialize_hscbs(struct ahd_softc *ahd)
5614 {
5615 int i;
5616
5617 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5618 ahd_set_scbptr(ahd, i);
5619
5620 /* Clear the control byte. */
5621 ahd_outb(ahd, SCB_CONTROL, 0);
5622
5623 /* Set the next pointer */
5624 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5625 }
5626 }
5627
5628 static int
5629 ahd_init_scbdata(struct ahd_softc *ahd)
5630 {
5631 struct scb_data *scb_data;
5632 int i;
5633
5634 scb_data = &ahd->scb_data;
5635 TAILQ_INIT(&scb_data->free_scbs);
5636 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5637 LIST_INIT(&scb_data->free_scb_lists[i]);
5638 LIST_INIT(&scb_data->any_dev_free_scb_list);
5639 SLIST_INIT(&scb_data->hscb_maps);
5640 SLIST_INIT(&scb_data->sg_maps);
5641 SLIST_INIT(&scb_data->sense_maps);
5642
5643 /* Determine the number of hardware SCBs and initialize them */
5644 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5645 if (scb_data->maxhscbs == 0) {
5646 printf("%s: No SCB space found\n", ahd_name(ahd));
5647 return (ENXIO);
5648 }
5649
5650 ahd_initialize_hscbs(ahd);
5651
5652 /*
5653 * Create our DMA tags. These tags define the kinds of device
5654 * accessible memory allocations and memory mappings we will
5655 * need to perform during normal operation.
5656 *
5657 * Unless we need to further restrict the allocation, we rely
5658 * on the restrictions of the parent dmat, hence the common
5659 * use of MAXADDR and MAXSIZE.
5660 */
5661
5662 /* DMA tag for our hardware scb structures */
5663 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5664 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5665 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5666 /*highaddr*/BUS_SPACE_MAXADDR,
5667 /*filter*/NULL, /*filterarg*/NULL,
5668 PAGE_SIZE, /*nsegments*/1,
5669 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5670 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5671 goto error_exit;
5672 }
5673
5674 scb_data->init_level++;
5675
5676 /* DMA tag for our S/G structures. */
5677 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5678 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5679 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5680 /*highaddr*/BUS_SPACE_MAXADDR,
5681 /*filter*/NULL, /*filterarg*/NULL,
5682 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5683 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5684 /*flags*/0, &scb_data->sg_dmat) != 0) {
5685 goto error_exit;
5686 }
5687 #ifdef AHD_DEBUG
5688 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5689 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5690 ahd_sglist_allocsize(ahd));
5691 #endif
5692
5693 scb_data->init_level++;
5694
5695 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5696 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5697 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5698 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5699 /*highaddr*/BUS_SPACE_MAXADDR,
5700 /*filter*/NULL, /*filterarg*/NULL,
5701 PAGE_SIZE, /*nsegments*/1,
5702 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5703 /*flags*/0, &scb_data->sense_dmat) != 0) {
5704 goto error_exit;
5705 }
5706
5707 scb_data->init_level++;
5708
5709 /* Perform initial CCB allocation */
5710 ahd_alloc_scbs(ahd);
5711
5712 if (scb_data->numscbs == 0) {
5713 printf("%s: ahd_init_scbdata - "
5714 "Unable to allocate initial scbs\n",
5715 ahd_name(ahd));
5716 goto error_exit;
5717 }
5718
5719 /*
5720 * Note that we were successfull
5721 */
5722 return (0);
5723
5724 error_exit:
5725
5726 return (ENOMEM);
5727 }
5728
5729 static struct scb *
5730 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5731 {
5732 struct scb *scb;
5733
5734 /*
5735 * Look on the pending list.
5736 */
5737 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5738 if (SCB_GET_TAG(scb) == tag)
5739 return (scb);
5740 }
5741
5742 /*
5743 * Then on all of the collision free lists.
5744 */
5745 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5746 struct scb *list_scb;
5747
5748 list_scb = scb;
5749 do {
5750 if (SCB_GET_TAG(list_scb) == tag)
5751 return (list_scb);
5752 list_scb = LIST_NEXT(list_scb, collision_links);
5753 } while (list_scb);
5754 }
5755
5756 /*
5757 * And finally on the generic free list.
5758 */
5759 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5760 if (SCB_GET_TAG(scb) == tag)
5761 return (scb);
5762 }
5763
5764 return (NULL);
5765 }
5766
5767 static void
5768 ahd_fini_scbdata(struct ahd_softc *ahd)
5769 {
5770 struct scb_data *scb_data;
5771
5772 scb_data = &ahd->scb_data;
5773 if (scb_data == NULL)
5774 return;
5775
5776 switch (scb_data->init_level) {
5777 default:
5778 case 7:
5779 {
5780 struct map_node *sns_map;
5781
5782 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5783 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5784 aic_dmamap_unload(ahd, scb_data->sense_dmat,
5785 sns_map->dmamap);
5786 aic_dmamem_free(ahd, scb_data->sense_dmat,
5787 sns_map->vaddr, sns_map->dmamap);
5788 free(sns_map, M_DEVBUF);
5789 }
5790 aic_dma_tag_destroy(ahd, scb_data->sense_dmat);
5791 /* FALLTHROUGH */
5792 }
5793 case 6:
5794 {
5795 struct map_node *sg_map;
5796
5797 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5798 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5799 aic_dmamap_unload(ahd, scb_data->sg_dmat,
5800 sg_map->dmamap);
5801 aic_dmamem_free(ahd, scb_data->sg_dmat,
5802 sg_map->vaddr, sg_map->dmamap);
5803 free(sg_map, M_DEVBUF);
5804 }
5805 aic_dma_tag_destroy(ahd, scb_data->sg_dmat);
5806 /* FALLTHROUGH */
5807 }
5808 case 5:
5809 {
5810 struct map_node *hscb_map;
5811
5812 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5813 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5814 aic_dmamap_unload(ahd, scb_data->hscb_dmat,
5815 hscb_map->dmamap);
5816 aic_dmamem_free(ahd, scb_data->hscb_dmat,
5817 hscb_map->vaddr, hscb_map->dmamap);
5818 free(hscb_map, M_DEVBUF);
5819 }
5820 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5821 /* FALLTHROUGH */
5822 }
5823 case 4:
5824 case 3:
5825 case 2:
5826 case 1:
5827 case 0:
5828 break;
5829 }
5830 }
5831
5832 /*
5833 * DSP filter Bypass must be enabled until the first selection
5834 * after a change in bus mode (Razor #491 and #493).
5835 */
5836 static void
5837 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5838 {
5839 ahd_mode_state saved_modes;
5840
5841 saved_modes = ahd_save_modes(ahd);
5842 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5843 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5844 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5845 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5846 #ifdef AHD_DEBUG
5847 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5848 printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5849 #endif
5850 ahd_restore_modes(ahd, saved_modes);
5851 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5852 }
5853
5854 static void
5855 ahd_iocell_first_selection(struct ahd_softc *ahd)
5856 {
5857 ahd_mode_state saved_modes;
5858 u_int sblkctl;
5859
5860 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5861 return;
5862 saved_modes = ahd_save_modes(ahd);
5863 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5864 sblkctl = ahd_inb(ahd, SBLKCTL);
5865 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5866 #ifdef AHD_DEBUG
5867 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5868 printf("%s: iocell first selection\n", ahd_name(ahd));
5869 #endif
5870 if ((sblkctl & ENAB40) != 0) {
5871 ahd_outb(ahd, DSPDATACTL,
5872 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5873 #ifdef AHD_DEBUG
5874 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5875 printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5876 #endif
5877 }
5878 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5879 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5880 ahd_restore_modes(ahd, saved_modes);
5881 ahd->flags |= AHD_HAD_FIRST_SEL;
5882 }
5883
5884 /*************************** SCB Management ***********************************/
5885 static void
5886 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5887 {
5888 struct scb_list *free_list;
5889 struct scb_tailq *free_tailq;
5890 struct scb *first_scb;
5891
5892 scb->flags |= SCB_ON_COL_LIST;
5893 AHD_SET_SCB_COL_IDX(scb, col_idx);
5894 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5895 free_tailq = &ahd->scb_data.free_scbs;
5896 first_scb = LIST_FIRST(free_list);
5897 if (first_scb != NULL) {
5898 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5899 } else {
5900 LIST_INSERT_HEAD(free_list, scb, collision_links);
5901 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5902 }
5903 }
5904
5905 static void
5906 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5907 {
5908 struct scb_list *free_list;
5909 struct scb_tailq *free_tailq;
5910 struct scb *first_scb;
5911 u_int col_idx;
5912
5913 scb->flags &= ~SCB_ON_COL_LIST;
5914 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5915 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5916 free_tailq = &ahd->scb_data.free_scbs;
5917 first_scb = LIST_FIRST(free_list);
5918 if (first_scb == scb) {
5919 struct scb *next_scb;
5920
5921 /*
5922 * Maintain order in the collision free
5923 * lists for fairness if this device has
5924 * other colliding tags active.
5925 */
5926 next_scb = LIST_NEXT(scb, collision_links);
5927 if (next_scb != NULL) {
5928 TAILQ_INSERT_AFTER(free_tailq, scb,
5929 next_scb, links.tqe);
5930 }
5931 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5932 }
5933 LIST_REMOVE(scb, collision_links);
5934 }
5935
5936 /*
5937 * Get a free scb. If there are none, see if we can allocate a new SCB.
5938 */
5939 struct scb *
5940 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5941 {
5942 struct scb *scb;
5943 int tries;
5944
5945 tries = 0;
5946 look_again:
5947 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5948 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5949 ahd_rem_col_list(ahd, scb);
5950 goto found;
5951 }
5952 }
5953 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5954
5955 if (tries++ != 0)
5956 return (NULL);
5957 ahd_alloc_scbs(ahd);
5958 goto look_again;
5959 }
5960 LIST_REMOVE(scb, links.le);
5961 if (col_idx != AHD_NEVER_COL_IDX
5962 && (scb->col_scb != NULL)
5963 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5964 LIST_REMOVE(scb->col_scb, links.le);
5965 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5966 }
5967 found:
5968 scb->flags |= SCB_ACTIVE;
5969 return (scb);
5970 }
5971
5972 /*
5973 * Return an SCB resource to the free list.
5974 */
5975 void
5976 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5977 {
5978
5979 /* Clean up for the next user */
5980 scb->flags = SCB_FLAG_NONE;
5981 scb->hscb->control = 0;
5982 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5983
5984 if (scb->col_scb == NULL) {
5985
5986 /*
5987 * No collision possible. Just free normally.
5988 */
5989 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5990 scb, links.le);
5991 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
5992
5993 /*
5994 * The SCB we might have collided with is on
5995 * a free collision list. Put both SCBs on
5996 * the generic list.
5997 */
5998 ahd_rem_col_list(ahd, scb->col_scb);
5999 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6000 scb, links.le);
6001 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6002 scb->col_scb, links.le);
6003 } else if ((scb->col_scb->flags
6004 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
6005 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
6006
6007 /*
6008 * The SCB we might collide with on the next allocation
6009 * is still active in a non-packetized, tagged, context.
6010 * Put us on the SCB collision list.
6011 */
6012 ahd_add_col_list(ahd, scb,
6013 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
6014 } else {
6015 /*
6016 * The SCB we might collide with on the next allocation
6017 * is either active in a packetized context, or free.
6018 * Since we can't collide, put this SCB on the generic
6019 * free list.
6020 */
6021 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6022 scb, links.le);
6023 }
6024
6025 aic_platform_scb_free(ahd, scb);
6026 }
6027
6028 void
6029 ahd_alloc_scbs(struct ahd_softc *ahd)
6030 {
6031 struct scb_data *scb_data;
6032 struct scb *next_scb;
6033 struct hardware_scb *hscb;
6034 struct map_node *hscb_map;
6035 struct map_node *sg_map;
6036 struct map_node *sense_map;
6037 uint8_t *segs;
6038 uint8_t *sense_data;
6039 bus_addr_t hscb_busaddr;
6040 bus_addr_t sg_busaddr;
6041 bus_addr_t sense_busaddr;
6042 int newcount;
6043 int i;
6044
6045 scb_data = &ahd->scb_data;
6046 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
6047 /* Can't allocate any more */
6048 return;
6049
6050 if (scb_data->scbs_left != 0) {
6051 int offset;
6052
6053 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
6054 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
6055 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
6056 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
6057 } else {
6058 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
6059
6060 if (hscb_map == NULL)
6061 return;
6062
6063 /* Allocate the next batch of hardware SCBs */
6064 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat,
6065 (void **)&hscb_map->vaddr,
6066 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
6067 free(hscb_map, M_DEVBUF);
6068 return;
6069 }
6070
6071 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
6072
6073 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
6074 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6075 &hscb_map->busaddr, /*flags*/0);
6076
6077 hscb = (struct hardware_scb *)hscb_map->vaddr;
6078 hscb_busaddr = hscb_map->busaddr;
6079 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6080 }
6081
6082 if (scb_data->sgs_left != 0) {
6083 int offset;
6084
6085 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6086 - scb_data->sgs_left) * ahd_sglist_size(ahd);
6087 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6088 segs = sg_map->vaddr + offset;
6089 sg_busaddr = sg_map->busaddr + offset;
6090 } else {
6091 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
6092
6093 if (sg_map == NULL)
6094 return;
6095
6096 /* Allocate the next batch of S/G lists */
6097 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat,
6098 (void **)&sg_map->vaddr,
6099 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
6100 free(sg_map, M_DEVBUF);
6101 return;
6102 }
6103
6104 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6105
6106 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6107 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6108 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0);
6109
6110 segs = sg_map->vaddr;
6111 sg_busaddr = sg_map->busaddr;
6112 scb_data->sgs_left =
6113 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6114 #ifdef AHD_DEBUG
6115 if (ahd_debug & AHD_SHOW_MEMORY)
6116 printf("Mapped SG data\n");
6117 #endif
6118 }
6119
6120 if (scb_data->sense_left != 0) {
6121 int offset;
6122
6123 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6124 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6125 sense_data = sense_map->vaddr + offset;
6126 sense_busaddr = sense_map->busaddr + offset;
6127 } else {
6128 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
6129
6130 if (sense_map == NULL)
6131 return;
6132
6133 /* Allocate the next batch of sense buffers */
6134 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat,
6135 (void **)&sense_map->vaddr,
6136 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6137 free(sense_map, M_DEVBUF);
6138 return;
6139 }
6140
6141 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6142
6143 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6144 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6145 &sense_map->busaddr, /*flags*/0);
6146
6147 sense_data = sense_map->vaddr;
6148 sense_busaddr = sense_map->busaddr;
6149 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6150 #ifdef AHD_DEBUG
6151 if (ahd_debug & AHD_SHOW_MEMORY)
6152 printf("Mapped sense data\n");
6153 #endif
6154 }
6155
6156 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6157 newcount = MIN(newcount, scb_data->sgs_left);
6158 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6159 scb_data->sense_left -= newcount;
6160 scb_data->scbs_left -= newcount;
6161 scb_data->sgs_left -= newcount;
6162 for (i = 0; i < newcount; i++) {
6163 struct scb_platform_data *pdata;
6164 u_int col_tag;
6165 #ifndef __linux__
6166 int error;
6167 #endif
6168
6169 next_scb = (struct scb *)malloc(sizeof(*next_scb),
6170 M_DEVBUF, M_NOWAIT);
6171 if (next_scb == NULL)
6172 break;
6173
6174 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
6175 M_DEVBUF, M_NOWAIT);
6176 if (pdata == NULL) {
6177 free(next_scb, M_DEVBUF);
6178 break;
6179 }
6180 next_scb->platform_data = pdata;
6181 next_scb->hscb_map = hscb_map;
6182 next_scb->sg_map = sg_map;
6183 next_scb->sense_map = sense_map;
6184 next_scb->sg_list = segs;
6185 next_scb->sense_data = sense_data;
6186 next_scb->sense_busaddr = sense_busaddr;
6187 memset(hscb, 0, sizeof(*hscb));
6188 next_scb->hscb = hscb;
6189 hscb->hscb_busaddr = aic_htole32(hscb_busaddr);
6190
6191 /*
6192 * The sequencer always starts with the second entry.
6193 * The first entry is embedded in the scb.
6194 */
6195 next_scb->sg_list_busaddr = sg_busaddr;
6196 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6197 next_scb->sg_list_busaddr
6198 += sizeof(struct ahd_dma64_seg);
6199 else
6200 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6201 next_scb->ahd_softc = ahd;
6202 next_scb->flags = SCB_FLAG_NONE;
6203 #ifndef __linux__
6204 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6205 &next_scb->dmamap);
6206 if (error != 0) {
6207 free(next_scb, M_DEVBUF);
6208 free(pdata, M_DEVBUF);
6209 break;
6210 }
6211 #endif
6212 next_scb->hscb->tag = aic_htole16(scb_data->numscbs);
6213 col_tag = scb_data->numscbs ^ 0x100;
6214 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6215 if (next_scb->col_scb != NULL)
6216 next_scb->col_scb->col_scb = next_scb;
6217 ahd_free_scb(ahd, next_scb);
6218 hscb++;
6219 hscb_busaddr += sizeof(*hscb);
6220 segs += ahd_sglist_size(ahd);
6221 sg_busaddr += ahd_sglist_size(ahd);
6222 sense_data += AHD_SENSE_BUFSIZE;
6223 sense_busaddr += AHD_SENSE_BUFSIZE;
6224 scb_data->numscbs++;
6225 }
6226 }
6227
6228 void
6229 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6230 {
6231 const char *speed;
6232 const char *type;
6233 int len;
6234
6235 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6236 buf += len;
6237
6238 speed = "Ultra320 ";
6239 if ((ahd->features & AHD_WIDE) != 0) {
6240 type = "Wide ";
6241 } else {
6242 type = "Single ";
6243 }
6244 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6245 speed, type, ahd->channel, ahd->our_id);
6246 buf += len;
6247
6248 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
6249 ahd->scb_data.maxhscbs);
6250 }
6251
6252 static const char *channel_strings[] = {
6253 "Primary Low",
6254 "Primary High",
6255 "Secondary Low",
6256 "Secondary High"
6257 };
6258
6259 static const char *termstat_strings[] = {
6260 "Terminated Correctly",
6261 "Over Terminated",
6262 "Under Terminated",
6263 "Not Configured"
6264 };
6265
6266 /*
6267 * Start the board, ready for normal operation
6268 */
6269 int
6270 ahd_init(struct ahd_softc *ahd)
6271 {
6272 uint8_t *next_vaddr;
6273 bus_addr_t next_baddr;
6274 size_t driver_data_size;
6275 int i;
6276 int error;
6277 u_int warn_user;
6278 uint8_t current_sensing;
6279 uint8_t fstat;
6280
6281 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6282
6283 ahd->stack_size = ahd_probe_stack_size(ahd);
6284 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t),
6285 M_DEVBUF, M_NOWAIT);
6286 if (ahd->saved_stack == NULL)
6287 return (ENOMEM);
6288
6289 /*
6290 * Verify that the compiler hasn't over-agressively
6291 * padded important structures.
6292 */
6293 if (sizeof(struct hardware_scb) != 64)
6294 panic("Hardware SCB size is incorrect");
6295
6296 #ifdef AHD_DEBUG
6297 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6298 ahd->flags |= AHD_SEQUENCER_DEBUG;
6299 #endif
6300
6301 /*
6302 * Default to allowing initiator operations.
6303 */
6304 ahd->flags |= AHD_INITIATORROLE;
6305
6306 /*
6307 * Only allow target mode features if this unit has them enabled.
6308 */
6309 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6310 ahd->features &= ~AHD_TARGETMODE;
6311
6312 #ifndef __linux__
6313 /* DMA tag for mapping buffers into device visible space. */
6314 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6315 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6316 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6317 ? (bus_addr_t)0x7FFFFFFFFFULL
6318 : BUS_SPACE_MAXADDR_32BIT,
6319 /*highaddr*/BUS_SPACE_MAXADDR,
6320 /*filter*/NULL, /*filterarg*/NULL,
6321 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6322 /*nsegments*/AHD_NSEG,
6323 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6324 /*flags*/BUS_DMA_ALLOCNOW,
6325 &ahd->buffer_dmat) != 0) {
6326 return (ENOMEM);
6327 }
6328 #endif
6329
6330 ahd->init_level++;
6331
6332 /*
6333 * DMA tag for our command fifos and other data in system memory
6334 * the card's sequencer must be able to access. For initiator
6335 * roles, we need to allocate space for the qoutfifo. When providing
6336 * for the target mode role, we must additionally provide space for
6337 * the incoming target command fifo.
6338 */
6339 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6340 + sizeof(struct hardware_scb);
6341 if ((ahd->features & AHD_TARGETMODE) != 0)
6342 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6343 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6344 driver_data_size += PKT_OVERRUN_BUFSIZE;
6345 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6346 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6347 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6348 /*highaddr*/BUS_SPACE_MAXADDR,
6349 /*filter*/NULL, /*filterarg*/NULL,
6350 driver_data_size,
6351 /*nsegments*/1,
6352 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6353 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6354 return (ENOMEM);
6355 }
6356
6357 ahd->init_level++;
6358
6359 /* Allocation of driver data */
6360 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat,
6361 (void **)&ahd->shared_data_map.vaddr,
6362 BUS_DMA_NOWAIT,
6363 &ahd->shared_data_map.dmamap) != 0) {
6364 return (ENOMEM);
6365 }
6366
6367 ahd->init_level++;
6368
6369 /* And permanently map it in */
6370 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6371 ahd->shared_data_map.vaddr, driver_data_size,
6372 ahd_dmamap_cb, &ahd->shared_data_map.busaddr,
6373 /*flags*/0);
6374 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6375 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6376 next_baddr = ahd->shared_data_map.busaddr
6377 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6378 if ((ahd->features & AHD_TARGETMODE) != 0) {
6379 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6380 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6381 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6382 }
6383
6384 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6385 ahd->overrun_buf = next_vaddr;
6386 next_vaddr += PKT_OVERRUN_BUFSIZE;
6387 next_baddr += PKT_OVERRUN_BUFSIZE;
6388 }
6389
6390 /*
6391 * We need one SCB to serve as the "next SCB". Since the
6392 * tag identifier in this SCB will never be used, there is
6393 * no point in using a valid HSCB tag from an SCB pulled from
6394 * the standard free pool. So, we allocate this "sentinel"
6395 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6396 */
6397 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6398 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6399 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr);
6400
6401 ahd->init_level++;
6402
6403 /* Allocate SCB data now that buffer_dmat is initialized */
6404 if (ahd_init_scbdata(ahd) != 0)
6405 return (ENOMEM);
6406
6407 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6408 ahd->flags &= ~AHD_RESET_BUS_A;
6409
6410 /*
6411 * Before committing these settings to the chip, give
6412 * the OSM one last chance to modify our configuration.
6413 */
6414 ahd_platform_init(ahd);
6415
6416 /* Bring up the chip. */
6417 ahd_chip_init(ahd);
6418
6419 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6420
6421 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6422 goto init_done;
6423
6424 /*
6425 * Verify termination based on current draw and
6426 * warn user if the bus is over/under terminated.
6427 */
6428 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6429 CURSENSE_ENB);
6430 if (error != 0) {
6431 printf("%s: current sensing timeout 1\n", ahd_name(ahd));
6432 goto init_done;
6433 }
6434 for (i = 20, fstat = FLX_FSTAT_BUSY;
6435 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6436 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6437 if (error != 0) {
6438 printf("%s: current sensing timeout 2\n",
6439 ahd_name(ahd));
6440 goto init_done;
6441 }
6442 }
6443 if (i == 0) {
6444 printf("%s: Timedout during current-sensing test\n",
6445 ahd_name(ahd));
6446 goto init_done;
6447 }
6448
6449 /* Latch Current Sensing status. */
6450 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing);
6451 if (error != 0) {
6452 printf("%s: current sensing timeout 3\n", ahd_name(ahd));
6453 goto init_done;
6454 }
6455
6456 /* Diable current sensing. */
6457 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6458
6459 #ifdef AHD_DEBUG
6460 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6461 printf("%s: current_sensing == 0x%x\n",
6462 ahd_name(ahd), current_sensing);
6463 }
6464 #endif
6465 warn_user = 0;
6466 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6467 u_int term_stat;
6468
6469 term_stat = (current_sensing & FLX_CSTAT_MASK);
6470 switch (term_stat) {
6471 case FLX_CSTAT_OVER:
6472 case FLX_CSTAT_UNDER:
6473 warn_user++;
6474 case FLX_CSTAT_INVALID:
6475 case FLX_CSTAT_OKAY:
6476 if (warn_user == 0 && bootverbose == 0)
6477 break;
6478 printf("%s: %s Channel %s\n", ahd_name(ahd),
6479 channel_strings[i], termstat_strings[term_stat]);
6480 break;
6481 }
6482 }
6483 if (warn_user) {
6484 printf("%s: WARNING. Termination is not configured correctly.\n"
6485 "%s: WARNING. SCSI bus operations may FAIL.\n",
6486 ahd_name(ahd), ahd_name(ahd));
6487 }
6488 init_done:
6489 ahd_restart(ahd);
6490 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
6491 ahd_stat_timer, ahd);
6492 return (0);
6493 }
6494
6495 /*
6496 * (Re)initialize chip state after a chip reset.
6497 */
6498 static void
6499 ahd_chip_init(struct ahd_softc *ahd)
6500 {
6501 uint32_t busaddr;
6502 u_int sxfrctl1;
6503 u_int scsiseq_template;
6504 u_int wait;
6505 u_int i;
6506 u_int target;
6507
6508 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6509 /*
6510 * Take the LED out of diagnostic mode
6511 */
6512 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6513
6514 /*
6515 * Return HS_MAILBOX to its default value.
6516 */
6517 ahd->hs_mailbox = 0;
6518 ahd_outb(ahd, HS_MAILBOX, 0);
6519
6520 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6521 ahd_outb(ahd, IOWNID, ahd->our_id);
6522 ahd_outb(ahd, TOWNID, ahd->our_id);
6523 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6524 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6525 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6526 && (ahd->seltime != STIMESEL_MIN)) {
6527 /*
6528 * The selection timer duration is twice as long
6529 * as it should be. Halve it by adding "1" to
6530 * the user specified setting.
6531 */
6532 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6533 } else {
6534 sxfrctl1 |= ahd->seltime;
6535 }
6536
6537 ahd_outb(ahd, SXFRCTL0, DFON);
6538 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6539 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6540
6541 /*
6542 * Now that termination is set, wait for up
6543 * to 500ms for our transceivers to settle. If
6544 * the adapter does not have a cable attached,
6545 * the transceivers may never settle, so don't
6546 * complain if we fail here.
6547 */
6548 for (wait = 10000;
6549 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6550 wait--)
6551 aic_delay(100);
6552
6553 /* Clear any false bus resets due to the transceivers settling */
6554 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6555 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6556
6557 /* Initialize mode specific S/G state. */
6558 for (i = 0; i < 2; i++) {
6559 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6560 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6561 ahd_outb(ahd, SG_STATE, 0);
6562 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6563 ahd_outb(ahd, SEQIMODE,
6564 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6565 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6566 }
6567
6568 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6569 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6570 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6571 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6572 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6573 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6574 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6575 } else {
6576 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6577 }
6578 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6579 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6580 /*
6581 * Do not issue a target abort when a split completion
6582 * error occurs. Let our PCIX interrupt handler deal
6583 * with it instead. H2A4 Razor #625
6584 */
6585 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6586
6587 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6588 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6589
6590 /*
6591 * Tweak IOCELL settings.
6592 */
6593 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6594 for (i = 0; i < NUMDSPS; i++) {
6595 ahd_outb(ahd, DSPSELECT, i);
6596 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6597 }
6598 #ifdef AHD_DEBUG
6599 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6600 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6601 WRTBIASCTL_HP_DEFAULT);
6602 #endif
6603 }
6604 ahd_setup_iocell_workaround(ahd);
6605
6606 /*
6607 * Enable LQI Manager interrupts.
6608 */
6609 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6610 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6611 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6612 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6613 /*
6614 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6615 * manually for the command phase at the start of a packetized
6616 * selection case. ENLQOBUSFREE should be made redundant by
6617 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6618 * events fail to assert the BUSFREE interrupt so we must
6619 * also enable LQOBUSFREE interrupts.
6620 */
6621 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6622
6623 /*
6624 * Setup sequencer interrupt handlers.
6625 */
6626 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6627 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6628
6629 /*
6630 * Setup SCB Offset registers.
6631 */
6632 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6633 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6634 pkt_long_lun));
6635 } else {
6636 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6637 }
6638 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6639 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6640 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6641 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6642 shared_data.idata.cdb));
6643 ahd_outb(ahd, QNEXTPTR,
6644 offsetof(struct hardware_scb, next_hscb_busaddr));
6645 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6646 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6647 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6648 ahd_outb(ahd, LUNLEN,
6649 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6650 } else {
6651 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6652 }
6653 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6654 ahd_outb(ahd, MAXCMD, 0xFF);
6655 ahd_outb(ahd, SCBAUTOPTR,
6656 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6657
6658 /* We haven't been enabled for target mode yet. */
6659 ahd_outb(ahd, MULTARGID, 0);
6660 ahd_outb(ahd, MULTARGID + 1, 0);
6661
6662 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6663 /* Initialize the negotiation table. */
6664 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6665 /*
6666 * Clear the spare bytes in the neg table to avoid
6667 * spurious parity errors.
6668 */
6669 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6670 ahd_outb(ahd, NEGOADDR, target);
6671 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6672 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6673 ahd_outb(ahd, ANNEXDAT, 0);
6674 }
6675 }
6676 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6677 struct ahd_devinfo devinfo;
6678 struct ahd_initiator_tinfo *tinfo;
6679 struct ahd_tmode_tstate *tstate;
6680
6681 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6682 target, &tstate);
6683 ahd_compile_devinfo(&devinfo, ahd->our_id,
6684 target, CAM_LUN_WILDCARD,
6685 'A', ROLE_INITIATOR);
6686 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6687 }
6688
6689 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6690 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6691
6692 #if NEEDS_MORE_TESTING
6693 /*
6694 * Always enable abort on incoming L_Qs if this feature is
6695 * supported. We use this to catch invalid SCB references.
6696 */
6697 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6698 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6699 else
6700 #endif
6701 ahd_outb(ahd, LQCTL1, 0);
6702
6703 /* All of our queues are empty */
6704 ahd->qoutfifonext = 0;
6705 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6706 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6707 for (i = 0; i < AHD_QOUT_SIZE; i++)
6708 ahd->qoutfifo[i].valid_tag = 0;
6709 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6710
6711 ahd->qinfifonext = 0;
6712 for (i = 0; i < AHD_QIN_SIZE; i++)
6713 ahd->qinfifo[i] = SCB_LIST_NULL;
6714
6715 if ((ahd->features & AHD_TARGETMODE) != 0) {
6716 /* All target command blocks start out invalid. */
6717 for (i = 0; i < AHD_TMODE_CMDS; i++)
6718 ahd->targetcmds[i].cmd_valid = 0;
6719 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6720 ahd->tqinfifonext = 1;
6721 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6722 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6723 }
6724
6725 /* Initialize Scratch Ram. */
6726 ahd_outb(ahd, SEQ_FLAGS, 0);
6727 ahd_outb(ahd, SEQ_FLAGS2, 0);
6728
6729 /* We don't have any waiting selections */
6730 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6731 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6732 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6733 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6734 for (i = 0; i < AHD_NUM_TARGETS; i++)
6735 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6736
6737 /*
6738 * Nobody is waiting to be DMAed into the QOUTFIFO.
6739 */
6740 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6741 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6742 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6743 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6744 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6745
6746 /*
6747 * The Freeze Count is 0.
6748 */
6749 ahd->qfreeze_cnt = 0;
6750 ahd_outw(ahd, QFREEZE_COUNT, 0);
6751 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6752
6753 /*
6754 * Tell the sequencer where it can find our arrays in memory.
6755 */
6756 busaddr = ahd->shared_data_map.busaddr;
6757 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6758 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6759
6760 /*
6761 * Setup the allowed SCSI Sequences based on operational mode.
6762 * If we are a target, we'll enable select in operations once
6763 * we've had a lun enabled.
6764 */
6765 scsiseq_template = ENAUTOATNP;
6766 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6767 scsiseq_template |= ENRSELI;
6768 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6769
6770 /* There are no busy SCBs yet. */
6771 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6772 int lun;
6773
6774 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6775 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6776 }
6777
6778 /*
6779 * Initialize the group code to command length table.
6780 * Vendor Unique codes are set to 0 so we only capture
6781 * the first byte of the cdb. These can be overridden
6782 * when target mode is enabled.
6783 */
6784 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6785 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6786 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6787 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6788 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6789 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6790 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6791 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6792
6793 /* Tell the sequencer of our initial queue positions */
6794 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6795 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6796 ahd->qinfifonext = 0;
6797 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6798 ahd_set_hescb_qoff(ahd, 0);
6799 ahd_set_snscb_qoff(ahd, 0);
6800 ahd_set_sescb_qoff(ahd, 0);
6801 ahd_set_sdscb_qoff(ahd, 0);
6802
6803 /*
6804 * Tell the sequencer which SCB will be the next one it receives.
6805 */
6806 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6807 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6808
6809 /*
6810 * Default to coalescing disabled.
6811 */
6812 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6813 ahd_outw(ahd, CMDS_PENDING, 0);
6814 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6815 ahd->int_coalescing_maxcmds,
6816 ahd->int_coalescing_mincmds);
6817 ahd_enable_coalescing(ahd, FALSE);
6818
6819 ahd_loadseq(ahd);
6820 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6821 }
6822
6823 /*
6824 * Setup default device and controller settings.
6825 * This should only be called if our probe has
6826 * determined that no configuration data is available.
6827 */
6828 int
6829 ahd_default_config(struct ahd_softc *ahd)
6830 {
6831 int targ;
6832
6833 ahd->our_id = 7;
6834
6835 /*
6836 * Allocate a tstate to house information for our
6837 * initiator presence on the bus as well as the user
6838 * data for any target mode initiator.
6839 */
6840 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6841 printf("%s: unable to allocate ahd_tmode_tstate. "
6842 "Failing attach\n", ahd_name(ahd));
6843 return (ENOMEM);
6844 }
6845
6846 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6847 struct ahd_devinfo devinfo;
6848 struct ahd_initiator_tinfo *tinfo;
6849 struct ahd_tmode_tstate *tstate;
6850 uint16_t target_mask;
6851
6852 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6853 targ, &tstate);
6854 /*
6855 * We support SPC2 and SPI4.
6856 */
6857 tinfo->user.protocol_version = 4;
6858 tinfo->user.transport_version = 4;
6859
6860 target_mask = 0x01 << targ;
6861 ahd->user_discenable |= target_mask;
6862 tstate->discenable |= target_mask;
6863 ahd->user_tagenable |= target_mask;
6864 #ifdef AHD_FORCE_160
6865 tinfo->user.period = AHD_SYNCRATE_DT;
6866 #else
6867 tinfo->user.period = AHD_SYNCRATE_160;
6868 #endif
6869 tinfo->user.offset = MAX_OFFSET;
6870 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6871 | MSG_EXT_PPR_WR_FLOW
6872 | MSG_EXT_PPR_HOLD_MCS
6873 | MSG_EXT_PPR_IU_REQ
6874 | MSG_EXT_PPR_QAS_REQ
6875 | MSG_EXT_PPR_DT_REQ;
6876 if ((ahd->features & AHD_RTI) != 0)
6877 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6878
6879 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6880
6881 /*
6882 * Start out Async/Narrow/Untagged and with
6883 * conservative protocol support.
6884 */
6885 tinfo->goal.protocol_version = 2;
6886 tinfo->goal.transport_version = 2;
6887 tinfo->curr.protocol_version = 2;
6888 tinfo->curr.transport_version = 2;
6889 ahd_compile_devinfo(&devinfo, ahd->our_id,
6890 targ, CAM_LUN_WILDCARD,
6891 'A', ROLE_INITIATOR);
6892 tstate->tagenable &= ~target_mask;
6893 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6894 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6895 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6896 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6897 /*paused*/TRUE);
6898 }
6899 return (0);
6900 }
6901
6902 /*
6903 * Parse device configuration information.
6904 */
6905 int
6906 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6907 {
6908 int targ;
6909 int max_targ;
6910
6911 max_targ = sc->max_targets & CFMAXTARG;
6912 ahd->our_id = sc->brtime_id & CFSCSIID;
6913
6914 /*
6915 * Allocate a tstate to house information for our
6916 * initiator presence on the bus as well as the user
6917 * data for any target mode initiator.
6918 */
6919 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6920 printf("%s: unable to allocate ahd_tmode_tstate. "
6921 "Failing attach\n", ahd_name(ahd));
6922 return (ENOMEM);
6923 }
6924
6925 for (targ = 0; targ < max_targ; targ++) {
6926 struct ahd_devinfo devinfo;
6927 struct ahd_initiator_tinfo *tinfo;
6928 struct ahd_transinfo *user_tinfo;
6929 struct ahd_tmode_tstate *tstate;
6930 uint16_t target_mask;
6931
6932 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6933 targ, &tstate);
6934 user_tinfo = &tinfo->user;
6935
6936 /*
6937 * We support SPC2 and SPI4.
6938 */
6939 tinfo->user.protocol_version = 4;
6940 tinfo->user.transport_version = 4;
6941
6942 target_mask = 0x01 << targ;
6943 ahd->user_discenable &= ~target_mask;
6944 tstate->discenable &= ~target_mask;
6945 ahd->user_tagenable &= ~target_mask;
6946 if (sc->device_flags[targ] & CFDISC) {
6947 tstate->discenable |= target_mask;
6948 ahd->user_discenable |= target_mask;
6949 ahd->user_tagenable |= target_mask;
6950 } else {
6951 /*
6952 * Cannot be packetized without disconnection.
6953 */
6954 sc->device_flags[targ] &= ~CFPACKETIZED;
6955 }
6956
6957 user_tinfo->ppr_options = 0;
6958 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6959 if (user_tinfo->period < CFXFER_ASYNC) {
6960 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6961 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6962 user_tinfo->offset = MAX_OFFSET;
6963 } else {
6964 user_tinfo->offset = 0;
6965 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6966 }
6967 #ifdef AHD_FORCE_160
6968 if (user_tinfo->period <= AHD_SYNCRATE_160)
6969 user_tinfo->period = AHD_SYNCRATE_DT;
6970 #endif
6971
6972 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6973 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6974 | MSG_EXT_PPR_WR_FLOW
6975 | MSG_EXT_PPR_HOLD_MCS
6976 | MSG_EXT_PPR_IU_REQ;
6977 if ((ahd->features & AHD_RTI) != 0)
6978 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6979 }
6980
6981 if ((sc->device_flags[targ] & CFQAS) != 0)
6982 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6983
6984 if ((sc->device_flags[targ] & CFWIDEB) != 0)
6985 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6986 else
6987 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6988 #ifdef AHD_DEBUG
6989 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6990 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6991 user_tinfo->period, user_tinfo->offset,
6992 user_tinfo->ppr_options);
6993 #endif
6994 /*
6995 * Start out Async/Narrow/Untagged and with
6996 * conservative protocol support.
6997 */
6998 tstate->tagenable &= ~target_mask;
6999 tinfo->goal.protocol_version = 2;
7000 tinfo->goal.transport_version = 2;
7001 tinfo->curr.protocol_version = 2;
7002 tinfo->curr.transport_version = 2;
7003 ahd_compile_devinfo(&devinfo, ahd->our_id,
7004 targ, CAM_LUN_WILDCARD,
7005 'A', ROLE_INITIATOR);
7006 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7007 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
7008 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
7009 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
7010 /*paused*/TRUE);
7011 }
7012
7013 ahd->flags &= ~AHD_SPCHK_ENB_A;
7014 if (sc->bios_control & CFSPARITY)
7015 ahd->flags |= AHD_SPCHK_ENB_A;
7016
7017 ahd->flags &= ~AHD_RESET_BUS_A;
7018 if (sc->bios_control & CFRESETB)
7019 ahd->flags |= AHD_RESET_BUS_A;
7020
7021 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
7022 if (sc->bios_control & CFEXTEND)
7023 ahd->flags |= AHD_EXTENDED_TRANS_A;
7024
7025 ahd->flags &= ~AHD_BIOS_ENABLED;
7026 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
7027 ahd->flags |= AHD_BIOS_ENABLED;
7028
7029 ahd->flags &= ~AHD_STPWLEVEL_A;
7030 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
7031 ahd->flags |= AHD_STPWLEVEL_A;
7032
7033 return (0);
7034 }
7035
7036 /*
7037 * Parse device configuration information.
7038 */
7039 int
7040 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
7041 {
7042 int error;
7043
7044 error = ahd_verify_vpd_cksum(vpd);
7045 if (error == 0)
7046 return (EINVAL);
7047 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
7048 ahd->flags |= AHD_BOOT_CHANNEL;
7049 return (0);
7050 }
7051
7052 void
7053 ahd_intr_enable(struct ahd_softc *ahd, int enable)
7054 {
7055 u_int hcntrl;
7056
7057 hcntrl = ahd_inb(ahd, HCNTRL);
7058 hcntrl &= ~INTEN;
7059 ahd->pause &= ~INTEN;
7060 ahd->unpause &= ~INTEN;
7061 if (enable) {
7062 hcntrl |= INTEN;
7063 ahd->pause |= INTEN;
7064 ahd->unpause |= INTEN;
7065 }
7066 ahd_outb(ahd, HCNTRL, hcntrl);
7067 }
7068
7069 void
7070 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
7071 u_int mincmds)
7072 {
7073 if (timer > AHD_TIMER_MAX_US)
7074 timer = AHD_TIMER_MAX_US;
7075 ahd->int_coalescing_timer = timer;
7076
7077 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7078 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7079 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7080 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7081 ahd->int_coalescing_maxcmds = maxcmds;
7082 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7083 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7084 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7085 }
7086
7087 void
7088 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7089 {
7090
7091 ahd->hs_mailbox &= ~ENINT_COALESCE;
7092 if (enable)
7093 ahd->hs_mailbox |= ENINT_COALESCE;
7094 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7095 ahd_flush_device_writes(ahd);
7096 ahd_run_qoutfifo(ahd);
7097 }
7098
7099 /*
7100 * Ensure that the card is paused in a location
7101 * outside of all critical sections and that all
7102 * pending work is completed prior to returning.
7103 * This routine should only be called from outside
7104 * an interrupt context.
7105 */
7106 void
7107 ahd_pause_and_flushwork(struct ahd_softc *ahd)
7108 {
7109 u_int intstat;
7110 u_int maxloops;
7111
7112 maxloops = 1000;
7113 ahd->flags |= AHD_ALL_INTERRUPTS;
7114 ahd_pause(ahd);
7115 /*
7116 * Freeze the outgoing selections. We do this only
7117 * until we are safely paused without further selections
7118 * pending.
7119 */
7120 ahd->qfreeze_cnt--;
7121 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7122 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
7123 do {
7124
7125 ahd_unpause(ahd);
7126 /*
7127 * Give the sequencer some time to service
7128 * any active selections.
7129 */
7130 aic_delay(500);
7131
7132 ahd_intr(ahd);
7133 ahd_pause(ahd);
7134 intstat = ahd_inb(ahd, INTSTAT);
7135 if ((intstat & INT_PEND) == 0) {
7136 ahd_clear_critical_section(ahd);
7137 intstat = ahd_inb(ahd, INTSTAT);
7138 }
7139 } while (--maxloops
7140 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7141 && ((intstat & INT_PEND) != 0
7142 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7143 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7144
7145 if (maxloops == 0) {
7146 printf("Infinite interrupt loop, INTSTAT = %x",
7147 ahd_inb(ahd, INTSTAT));
7148 }
7149 ahd->qfreeze_cnt++;
7150 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7151
7152 ahd_flush_qoutfifo(ahd);
7153
7154 ahd_platform_flushwork(ahd);
7155 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7156 }
7157
7158 int
7159 ahd_suspend(struct ahd_softc *ahd)
7160 {
7161
7162 ahd_pause_and_flushwork(ahd);
7163
7164 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7165 ahd_unpause(ahd);
7166 return (EBUSY);
7167 }
7168 ahd_shutdown(ahd);
7169 return (0);
7170 }
7171
7172 int
7173 ahd_resume(struct ahd_softc *ahd)
7174 {
7175
7176 ahd_reset(ahd, /*reinit*/TRUE);
7177 ahd_intr_enable(ahd, TRUE);
7178 ahd_restart(ahd);
7179 return (0);
7180 }
7181
7182 /************************** Busy Target Table *********************************/
7183 /*
7184 * Set SCBPTR to the SCB that contains the busy
7185 * table entry for TCL. Return the offset into
7186 * the SCB that contains the entry for TCL.
7187 * saved_scbid is dereferenced and set to the
7188 * scbid that should be restored once manipualtion
7189 * of the TCL entry is complete.
7190 */
7191 static __inline u_int
7192 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7193 {
7194 /*
7195 * Index to the SCB that contains the busy entry.
7196 */
7197 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7198 *saved_scbid = ahd_get_scbptr(ahd);
7199 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7200 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7201
7202 /*
7203 * And now calculate the SCB offset to the entry.
7204 * Each entry is 2 bytes wide, hence the
7205 * multiplication by 2.
7206 */
7207 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7208 }
7209
7210 /*
7211 * Return the untagged transaction id for a given target/channel lun.
7212 */
7213 u_int
7214 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7215 {
7216 u_int scbid;
7217 u_int scb_offset;
7218 u_int saved_scbptr;
7219
7220 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7221 scbid = ahd_inw_scbram(ahd, scb_offset);
7222 ahd_set_scbptr(ahd, saved_scbptr);
7223 return (scbid);
7224 }
7225
7226 void
7227 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7228 {
7229 u_int scb_offset;
7230 u_int saved_scbptr;
7231
7232 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7233 ahd_outw(ahd, scb_offset, scbid);
7234 ahd_set_scbptr(ahd, saved_scbptr);
7235 }
7236
7237 /************************** SCB and SCB queue management **********************/
7238 int
7239 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7240 char channel, int lun, u_int tag, role_t role)
7241 {
7242 int targ = SCB_GET_TARGET(ahd, scb);
7243 char chan = SCB_GET_CHANNEL(ahd, scb);
7244 int slun = SCB_GET_LUN(scb);
7245 int match;
7246
7247 match = ((chan == channel) || (channel == ALL_CHANNELS));
7248 if (match != 0)
7249 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7250 if (match != 0)
7251 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7252 if (match != 0) {
7253 #if AHD_TARGET_MODE
7254 int group;
7255
7256 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7257 if (role == ROLE_INITIATOR) {
7258 match = (group != XPT_FC_GROUP_TMODE)
7259 && ((tag == SCB_GET_TAG(scb))
7260 || (tag == SCB_LIST_NULL));
7261 } else if (role == ROLE_TARGET) {
7262 match = (group == XPT_FC_GROUP_TMODE)
7263 && ((tag == scb->io_ctx->csio.tag_id)
7264 || (tag == SCB_LIST_NULL));
7265 }
7266 #else /* !AHD_TARGET_MODE */
7267 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7268 #endif /* AHD_TARGET_MODE */
7269 }
7270
7271 return match;
7272 }
7273
7274 void
7275 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7276 {
7277 int target;
7278 char channel;
7279 int lun;
7280
7281 target = SCB_GET_TARGET(ahd, scb);
7282 lun = SCB_GET_LUN(scb);
7283 channel = SCB_GET_CHANNEL(ahd, scb);
7284
7285 ahd_search_qinfifo(ahd, target, channel, lun,
7286 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7287 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7288
7289 ahd_platform_freeze_devq(ahd, scb);
7290 }
7291
7292 void
7293 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7294 {
7295 struct scb *prev_scb;
7296 ahd_mode_state saved_modes;
7297
7298 saved_modes = ahd_save_modes(ahd);
7299 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7300 prev_scb = NULL;
7301 if (ahd_qinfifo_count(ahd) != 0) {
7302 u_int prev_tag;
7303 u_int prev_pos;
7304
7305 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7306 prev_tag = ahd->qinfifo[prev_pos];
7307 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7308 }
7309 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7310 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7311 ahd_restore_modes(ahd, saved_modes);
7312 }
7313
7314 static void
7315 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7316 struct scb *scb)
7317 {
7318 if (prev_scb == NULL) {
7319 uint32_t busaddr;
7320
7321 busaddr = aic_le32toh(scb->hscb->hscb_busaddr);
7322 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7323 } else {
7324 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7325 ahd_sync_scb(ahd, prev_scb,
7326 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7327 }
7328 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7329 ahd->qinfifonext++;
7330 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7331 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7332 }
7333
7334 static int
7335 ahd_qinfifo_count(struct ahd_softc *ahd)
7336 {
7337 u_int qinpos;
7338 u_int wrap_qinpos;
7339 u_int wrap_qinfifonext;
7340
7341 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7342 qinpos = ahd_get_snscb_qoff(ahd);
7343 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7344 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7345 if (wrap_qinfifonext >= wrap_qinpos)
7346 return (wrap_qinfifonext - wrap_qinpos);
7347 else
7348 return (wrap_qinfifonext
7349 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7350 }
7351
7352 void
7353 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7354 {
7355 struct scb *scb;
7356 ahd_mode_state saved_modes;
7357 u_int pending_cmds;
7358
7359 saved_modes = ahd_save_modes(ahd);
7360 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7361
7362 /*
7363 * Don't count any commands as outstanding that the
7364 * sequencer has already marked for completion.
7365 */
7366 ahd_flush_qoutfifo(ahd);
7367
7368 pending_cmds = 0;
7369 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7370 pending_cmds++;
7371 }
7372 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7373 ahd_restore_modes(ahd, saved_modes);
7374 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7375 }
7376
7377 void
7378 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7379 {
7380 cam_status ostat;
7381 cam_status cstat;
7382
7383 ostat = aic_get_transaction_status(scb);
7384 if (ostat == CAM_REQ_INPROG)
7385 aic_set_transaction_status(scb, status);
7386 cstat = aic_get_transaction_status(scb);
7387 if (cstat != CAM_REQ_CMP)
7388 aic_freeze_scb(scb);
7389 ahd_done(ahd, scb);
7390 }
7391
7392 int
7393 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7394 int lun, u_int tag, role_t role, uint32_t status,
7395 ahd_search_action action)
7396 {
7397 struct scb *scb;
7398 struct scb *mk_msg_scb;
7399 struct scb *prev_scb;
7400 ahd_mode_state saved_modes;
7401 u_int qinstart;
7402 u_int qinpos;
7403 u_int qintail;
7404 u_int tid_next;
7405 u_int tid_prev;
7406 u_int scbid;
7407 u_int seq_flags2;
7408 u_int savedscbptr;
7409 uint32_t busaddr;
7410 int found;
7411 int targets;
7412
7413 /* Must be in CCHAN mode */
7414 saved_modes = ahd_save_modes(ahd);
7415 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7416
7417 /*
7418 * Halt any pending SCB DMA. The sequencer will reinitiate
7419 * this dma if the qinfifo is not empty once we unpause.
7420 */
7421 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7422 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7423 ahd_outb(ahd, CCSCBCTL,
7424 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7425 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7426 ;
7427 }
7428 /* Determine sequencer's position in the qinfifo. */
7429 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7430 qinstart = ahd_get_snscb_qoff(ahd);
7431 qinpos = AHD_QIN_WRAP(qinstart);
7432 found = 0;
7433 prev_scb = NULL;
7434
7435 if (action == SEARCH_PRINT) {
7436 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7437 qinstart, ahd->qinfifonext);
7438 }
7439
7440 /*
7441 * Start with an empty queue. Entries that are not chosen
7442 * for removal will be re-added to the queue as we go.
7443 */
7444 ahd->qinfifonext = qinstart;
7445 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7446 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7447
7448 while (qinpos != qintail) {
7449 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7450 if (scb == NULL) {
7451 printf("qinpos = %d, SCB index = %d\n",
7452 qinpos, ahd->qinfifo[qinpos]);
7453 panic("Loop 1\n");
7454 }
7455
7456 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7457 /*
7458 * We found an scb that needs to be acted on.
7459 */
7460 found++;
7461 switch (action) {
7462 case SEARCH_COMPLETE:
7463 if ((scb->flags & SCB_ACTIVE) == 0)
7464 printf("Inactive SCB in qinfifo\n");
7465 ahd_done_with_status(ahd, scb, status);
7466 /* FALLTHROUGH */
7467 case SEARCH_REMOVE:
7468 break;
7469 case SEARCH_PRINT:
7470 printf(" 0x%x", ahd->qinfifo[qinpos]);
7471 /* FALLTHROUGH */
7472 case SEARCH_COUNT:
7473 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7474 prev_scb = scb;
7475 break;
7476 }
7477 } else {
7478 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7479 prev_scb = scb;
7480 }
7481 qinpos = AHD_QIN_WRAP(qinpos+1);
7482 }
7483
7484 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7485
7486 if (action == SEARCH_PRINT)
7487 printf("\nWAITING_TID_QUEUES:\n");
7488
7489 /*
7490 * Search waiting for selection lists. We traverse the
7491 * list of "their ids" waiting for selection and, if
7492 * appropriate, traverse the SCBs of each "their id"
7493 * looking for matches.
7494 */
7495 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7496 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7497 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7498 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7499 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7500 } else
7501 mk_msg_scb = NULL;
7502 savedscbptr = ahd_get_scbptr(ahd);
7503 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7504 tid_prev = SCB_LIST_NULL;
7505 targets = 0;
7506 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7507 u_int tid_head;
7508 u_int tid_tail;
7509
7510 targets++;
7511 if (targets > AHD_NUM_TARGETS)
7512 panic("TID LIST LOOP");
7513
7514 if (scbid >= ahd->scb_data.numscbs) {
7515 printf("%s: Waiting TID List inconsistency. "
7516 "SCB index == 0x%x, yet numscbs == 0x%x.",
7517 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7518 ahd_dump_card_state(ahd);
7519 panic("for safety");
7520 }
7521 scb = ahd_lookup_scb(ahd, scbid);
7522 if (scb == NULL) {
7523 printf("%s: SCB = 0x%x Not Active!\n",
7524 ahd_name(ahd), scbid);
7525 panic("Waiting TID List traversal\n");
7526 }
7527 ahd_set_scbptr(ahd, scbid);
7528 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7529 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7530 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7531 tid_prev = scbid;
7532 continue;
7533 }
7534
7535 /*
7536 * We found a list of scbs that needs to be searched.
7537 */
7538 if (action == SEARCH_PRINT)
7539 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7540 tid_head = scbid;
7541 found += ahd_search_scb_list(ahd, target, channel,
7542 lun, tag, role, status,
7543 action, &tid_head, &tid_tail,
7544 SCB_GET_TARGET(ahd, scb));
7545 /*
7546 * Check any MK_MESSAGE SCB that is still waiting to
7547 * enter this target's waiting for selection queue.
7548 */
7549 if (mk_msg_scb != NULL
7550 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7551 lun, tag, role)) {
7552
7553 /*
7554 * We found an scb that needs to be acted on.
7555 */
7556 found++;
7557 switch (action) {
7558 case SEARCH_COMPLETE:
7559 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7560 printf("Inactive SCB pending MK_MSG\n");
7561 ahd_done_with_status(ahd, mk_msg_scb, status);
7562 /* FALLTHROUGH */
7563 case SEARCH_REMOVE:
7564 {
7565 u_int tail_offset;
7566
7567 printf("Removing MK_MSG scb\n");
7568
7569 /*
7570 * Reset our tail to the tail of the
7571 * main per-target list.
7572 */
7573 tail_offset = WAITING_SCB_TAILS
7574 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7575 ahd_outw(ahd, tail_offset, tid_tail);
7576
7577 seq_flags2 &= ~PENDING_MK_MESSAGE;
7578 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7579 ahd_outw(ahd, CMDS_PENDING,
7580 ahd_inw(ahd, CMDS_PENDING)-1);
7581 mk_msg_scb = NULL;
7582 break;
7583 }
7584 case SEARCH_PRINT:
7585 printf(" 0x%x", SCB_GET_TAG(scb));
7586 /* FALLTHROUGH */
7587 case SEARCH_COUNT:
7588 break;
7589 }
7590 }
7591
7592 if (mk_msg_scb != NULL
7593 && SCBID_IS_NULL(tid_head)
7594 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7595 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7596
7597 /*
7598 * When removing the last SCB for a target
7599 * queue with a pending MK_MESSAGE scb, we
7600 * must queue the MK_MESSAGE scb.
7601 */
7602 printf("Queueing mk_msg_scb\n");
7603 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7604 seq_flags2 &= ~PENDING_MK_MESSAGE;
7605 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7606 mk_msg_scb = NULL;
7607 }
7608 if (tid_head != scbid)
7609 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7610 if (!SCBID_IS_NULL(tid_head))
7611 tid_prev = tid_head;
7612 if (action == SEARCH_PRINT)
7613 printf(")\n");
7614 }
7615
7616 /* Restore saved state. */
7617 ahd_set_scbptr(ahd, savedscbptr);
7618 ahd_restore_modes(ahd, saved_modes);
7619 return (found);
7620 }
7621
7622 static int
7623 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7624 int lun, u_int tag, role_t role, uint32_t status,
7625 ahd_search_action action, u_int *list_head,
7626 u_int *list_tail, u_int tid)
7627 {
7628 struct scb *scb;
7629 u_int scbid;
7630 u_int next;
7631 u_int prev;
7632 int found;
7633
7634 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7635 found = 0;
7636 prev = SCB_LIST_NULL;
7637 next = *list_head;
7638 *list_tail = SCB_LIST_NULL;
7639 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7640 if (scbid >= ahd->scb_data.numscbs) {
7641 printf("%s:SCB List inconsistency. "
7642 "SCB == 0x%x, yet numscbs == 0x%x.",
7643 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7644 ahd_dump_card_state(ahd);
7645 panic("for safety");
7646 }
7647 scb = ahd_lookup_scb(ahd, scbid);
7648 if (scb == NULL) {
7649 printf("%s: SCB = %d Not Active!\n",
7650 ahd_name(ahd), scbid);
7651 panic("Waiting List traversal\n");
7652 }
7653 ahd_set_scbptr(ahd, scbid);
7654 *list_tail = scbid;
7655 next = ahd_inw_scbram(ahd, SCB_NEXT);
7656 if (ahd_match_scb(ahd, scb, target, channel,
7657 lun, SCB_LIST_NULL, role) == 0) {
7658 prev = scbid;
7659 continue;
7660 }
7661 found++;
7662 switch (action) {
7663 case SEARCH_COMPLETE:
7664 if ((scb->flags & SCB_ACTIVE) == 0)
7665 printf("Inactive SCB in Waiting List\n");
7666 ahd_done_with_status(ahd, scb, status);
7667 /* FALLTHROUGH */
7668 case SEARCH_REMOVE:
7669 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7670 *list_tail = prev;
7671 if (SCBID_IS_NULL(prev))
7672 *list_head = next;
7673 break;
7674 case SEARCH_PRINT:
7675 printf("0x%x ", scbid);
7676 case SEARCH_COUNT:
7677 prev = scbid;
7678 break;
7679 }
7680 if (found > AHD_SCB_MAX)
7681 panic("SCB LIST LOOP");
7682 }
7683 if (action == SEARCH_COMPLETE
7684 || action == SEARCH_REMOVE)
7685 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7686 return (found);
7687 }
7688
7689 static void
7690 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7691 u_int tid_cur, u_int tid_next)
7692 {
7693 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7694
7695 if (SCBID_IS_NULL(tid_cur)) {
7696
7697 /* Bypass current TID list */
7698 if (SCBID_IS_NULL(tid_prev)) {
7699 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7700 } else {
7701 ahd_set_scbptr(ahd, tid_prev);
7702 ahd_outw(ahd, SCB_NEXT2, tid_next);
7703 }
7704 if (SCBID_IS_NULL(tid_next))
7705 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7706 } else {
7707
7708 /* Stitch through tid_cur */
7709 if (SCBID_IS_NULL(tid_prev)) {
7710 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7711 } else {
7712 ahd_set_scbptr(ahd, tid_prev);
7713 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7714 }
7715 ahd_set_scbptr(ahd, tid_cur);
7716 ahd_outw(ahd, SCB_NEXT2, tid_next);
7717
7718 if (SCBID_IS_NULL(tid_next))
7719 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7720 }
7721 }
7722
7723 /*
7724 * Manipulate the waiting for selection list and return the
7725 * scb that follows the one that we remove.
7726 */
7727 static u_int
7728 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7729 u_int prev, u_int next, u_int tid)
7730 {
7731 u_int tail_offset;
7732
7733 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7734 if (!SCBID_IS_NULL(prev)) {
7735 ahd_set_scbptr(ahd, prev);
7736 ahd_outw(ahd, SCB_NEXT, next);
7737 }
7738
7739 /*
7740 * SCBs that have MK_MESSAGE set in them may
7741 * cause the tail pointer to be updated without
7742 * setting the next pointer of the previous tail.
7743 * Only clear the tail if the removed SCB was
7744 * the tail.
7745 */
7746 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7747 if (SCBID_IS_NULL(next)
7748 && ahd_inw(ahd, tail_offset) == scbid)
7749 ahd_outw(ahd, tail_offset, prev);
7750
7751 ahd_add_scb_to_free_list(ahd, scbid);
7752 return (next);
7753 }
7754
7755 /*
7756 * Add the SCB as selected by SCBPTR onto the on chip list of
7757 * free hardware SCBs. This list is empty/unused if we are not
7758 * performing SCB paging.
7759 */
7760 static void
7761 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7762 {
7763 /* XXX Need some other mechanism to designate "free". */
7764 /*
7765 * Invalidate the tag so that our abort
7766 * routines don't think it's active.
7767 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7768 */
7769 }
7770
7771 /******************************** Error Handling ******************************/
7772 /*
7773 * Abort all SCBs that match the given description (target/channel/lun/tag),
7774 * setting their status to the passed in status if the status has not already
7775 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7776 * is paused before it is called.
7777 */
7778 int
7779 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7780 int lun, u_int tag, role_t role, uint32_t status)
7781 {
7782 struct scb *scbp;
7783 struct scb *scbp_next;
7784 u_int i, j;
7785 u_int maxtarget;
7786 u_int minlun;
7787 u_int maxlun;
7788 int found;
7789 ahd_mode_state saved_modes;
7790
7791 /* restore this when we're done */
7792 saved_modes = ahd_save_modes(ahd);
7793 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7794
7795 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7796 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7797
7798 /*
7799 * Clean out the busy target table for any untagged commands.
7800 */
7801 i = 0;
7802 maxtarget = 16;
7803 if (target != CAM_TARGET_WILDCARD) {
7804 i = target;
7805 if (channel == 'B')
7806 i += 8;
7807 maxtarget = i + 1;
7808 }
7809
7810 if (lun == CAM_LUN_WILDCARD) {
7811 minlun = 0;
7812 maxlun = AHD_NUM_LUNS_NONPKT;
7813 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7814 minlun = maxlun = 0;
7815 } else {
7816 minlun = lun;
7817 maxlun = lun + 1;
7818 }
7819
7820 if (role != ROLE_TARGET) {
7821 for (;i < maxtarget; i++) {
7822 for (j = minlun;j < maxlun; j++) {
7823 u_int scbid;
7824 u_int tcl;
7825
7826 tcl = BUILD_TCL_RAW(i, 'A', j);
7827 scbid = ahd_find_busy_tcl(ahd, tcl);
7828 scbp = ahd_lookup_scb(ahd, scbid);
7829 if (scbp == NULL
7830 || ahd_match_scb(ahd, scbp, target, channel,
7831 lun, tag, role) == 0)
7832 continue;
7833 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7834 }
7835 }
7836 }
7837
7838 /*
7839 * Don't abort commands that have already completed,
7840 * but haven't quite made it up to the host yet.
7841 */
7842 ahd_flush_qoutfifo(ahd);
7843
7844 /*
7845 * Go through the pending CCB list and look for
7846 * commands for this target that are still active.
7847 * These are other tagged commands that were
7848 * disconnected when the reset occurred.
7849 */
7850 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7851 while (scbp_next != NULL) {
7852 scbp = scbp_next;
7853 scbp_next = LIST_NEXT(scbp, pending_links);
7854 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7855 cam_status ostat;
7856
7857 ostat = aic_get_transaction_status(scbp);
7858 if (ostat == CAM_REQ_INPROG)
7859 aic_set_transaction_status(scbp, status);
7860 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
7861 aic_freeze_scb(scbp);
7862 if ((scbp->flags & SCB_ACTIVE) == 0)
7863 printf("Inactive SCB on pending list\n");
7864 ahd_done(ahd, scbp);
7865 found++;
7866 }
7867 }
7868 ahd_restore_modes(ahd, saved_modes);
7869 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7870 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7871 return found;
7872 }
7873
7874 static void
7875 ahd_reset_current_bus(struct ahd_softc *ahd)
7876 {
7877 uint8_t scsiseq;
7878
7879 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7880 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7881 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7882 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7883 ahd_flush_device_writes(ahd);
7884 aic_delay(AHD_BUSRESET_DELAY);
7885 /* Turn off the bus reset */
7886 ahd_outb(ahd, SCSISEQ0, scsiseq);
7887 ahd_flush_device_writes(ahd);
7888 aic_delay(AHD_BUSRESET_DELAY);
7889 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7890 /*
7891 * 2A Razor #474
7892 * Certain chip state is not cleared for
7893 * SCSI bus resets that we initiate, so
7894 * we must reset the chip.
7895 */
7896 ahd_reset(ahd, /*reinit*/TRUE);
7897 ahd_intr_enable(ahd, /*enable*/TRUE);
7898 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7899 }
7900
7901 ahd_clear_intstat(ahd);
7902 }
7903
7904 int
7905 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7906 {
7907 struct ahd_devinfo devinfo;
7908 u_int initiator;
7909 u_int target;
7910 u_int max_scsiid;
7911 int found;
7912 u_int fifo;
7913 u_int next_fifo;
7914
7915 ahd->pending_device = NULL;
7916
7917 ahd_compile_devinfo(&devinfo,
7918 CAM_TARGET_WILDCARD,
7919 CAM_TARGET_WILDCARD,
7920 CAM_LUN_WILDCARD,
7921 channel, ROLE_UNKNOWN);
7922 ahd_pause(ahd);
7923
7924 /* Make sure the sequencer is in a safe location. */
7925 ahd_clear_critical_section(ahd);
7926
7927 #if AHD_TARGET_MODE
7928 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7929 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7930 }
7931 #endif
7932 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7933
7934 /*
7935 * Disable selections so no automatic hardware
7936 * functions will modify chip state.
7937 */
7938 ahd_outb(ahd, SCSISEQ0, 0);
7939 ahd_outb(ahd, SCSISEQ1, 0);
7940
7941 /*
7942 * Safely shut down our DMA engines. Always start with
7943 * the FIFO that is not currently active (if any are
7944 * actively connected).
7945 */
7946 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7947 if (next_fifo > CURRFIFO_1)
7948 /* If disconneced, arbitrarily start with FIFO1. */
7949 next_fifo = fifo = 0;
7950 do {
7951 next_fifo ^= CURRFIFO_1;
7952 ahd_set_modes(ahd, next_fifo, next_fifo);
7953 ahd_outb(ahd, DFCNTRL,
7954 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7955 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7956 aic_delay(10);
7957 /*
7958 * Set CURRFIFO to the now inactive channel.
7959 */
7960 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7961 ahd_outb(ahd, DFFSTAT, next_fifo);
7962 } while (next_fifo != fifo);
7963
7964 /*
7965 * Reset the bus if we are initiating this reset
7966 */
7967 ahd_clear_msg_state(ahd);
7968 ahd_outb(ahd, SIMODE1,
7969 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
7970
7971 if (initiate_reset)
7972 ahd_reset_current_bus(ahd);
7973
7974 ahd_clear_intstat(ahd);
7975
7976 /*
7977 * Clean up all the state information for the
7978 * pending transactions on this bus.
7979 */
7980 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7981 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7982 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7983
7984 /*
7985 * Cleanup anything left in the FIFOs.
7986 */
7987 ahd_clear_fifo(ahd, 0);
7988 ahd_clear_fifo(ahd, 1);
7989
7990 /*
7991 * Revert to async/narrow transfers until we renegotiate.
7992 */
7993 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7994 for (target = 0; target <= max_scsiid; target++) {
7995
7996 if (ahd->enabled_targets[target] == NULL)
7997 continue;
7998 for (initiator = 0; initiator <= max_scsiid; initiator++) {
7999 struct ahd_devinfo devinfo;
8000
8001 ahd_compile_devinfo(&devinfo, target, initiator,
8002 CAM_LUN_WILDCARD,
8003 'A', ROLE_UNKNOWN);
8004 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
8005 AHD_TRANS_CUR, /*paused*/TRUE);
8006 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
8007 /*offset*/0, /*ppr_options*/0,
8008 AHD_TRANS_CUR, /*paused*/TRUE);
8009 }
8010 }
8011
8012 #ifdef AHD_TARGET_MODE
8013 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
8014
8015 /*
8016 * Send an immediate notify ccb to all target more peripheral
8017 * drivers affected by this action.
8018 */
8019 for (target = 0; target <= max_scsiid; target++) {
8020 struct ahd_tmode_tstate* tstate;
8021 u_int lun;
8022
8023 tstate = ahd->enabled_targets[target];
8024 if (tstate == NULL)
8025 continue;
8026 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
8027 struct ahd_tmode_lstate* lstate;
8028
8029 lstate = tstate->enabled_luns[lun];
8030 if (lstate == NULL)
8031 continue;
8032
8033 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
8034 EVENT_TYPE_BUS_RESET, /*arg*/0);
8035 ahd_send_lstate_events(ahd, lstate);
8036 }
8037 }
8038 #endif
8039 /* Notify the XPT that a bus reset occurred */
8040 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
8041 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
8042 ahd_restart(ahd);
8043 /*
8044 * Freeze the SIMQ until our poller can determine that
8045 * the bus reset has really gone away. We set the initial
8046 * timer to 0 to have the check performed as soon as possible
8047 * from the timer context.
8048 */
8049 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
8050 ahd->flags |= AHD_RESET_POLL_ACTIVE;
8051 aic_freeze_simq(ahd);
8052 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
8053 }
8054 return (found);
8055 }
8056
8057
8058 #define AHD_RESET_POLL_US 1000
8059 static void
8060 ahd_reset_poll(void *arg)
8061 {
8062 struct ahd_softc *ahd;
8063 u_int scsiseq1;
8064 u_long l;
8065 u_long s;
8066
8067 ahd_list_lock(&l);
8068 ahd = ahd_find_softc((struct ahd_softc *)arg);
8069 if (ahd == NULL) {
8070 printf("ahd_reset_poll: Instance %p no longer exists\n", arg);
8071 ahd_list_unlock(&l);
8072 return;
8073 }
8074 ahd_lock(ahd, &s);
8075 ahd_pause(ahd);
8076 ahd_update_modes(ahd);
8077 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8078 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
8079 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
8080 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US,
8081 ahd_reset_poll, ahd);
8082 ahd_unpause(ahd);
8083 ahd_unlock(ahd, &s);
8084 ahd_list_unlock(&l);
8085 return;
8086 }
8087
8088 /* Reset is now low. Complete chip reinitialization. */
8089 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8090 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8091 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8092 ahd_unpause(ahd);
8093 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8094 ahd_unlock(ahd, &s);
8095 aic_release_simq(ahd);
8096 ahd_list_unlock(&l);
8097 }
8098
8099 /**************************** Statistics Processing ***************************/
8100 static void
8101 ahd_stat_timer(void *arg)
8102 {
8103 struct ahd_softc *ahd;
8104 u_long l;
8105 u_long s;
8106 int enint_coal;
8107
8108 ahd_list_lock(&l);
8109 ahd = ahd_find_softc((struct ahd_softc *)arg);
8110 if (ahd == NULL) {
8111 printf("ahd_stat_timer: Instance %p no longer exists\n", arg);
8112 ahd_list_unlock(&l);
8113 return;
8114 }
8115 ahd_lock(ahd, &s);
8116
8117 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8118 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8119 enint_coal |= ENINT_COALESCE;
8120 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8121 enint_coal &= ~ENINT_COALESCE;
8122
8123 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8124 ahd_enable_coalescing(ahd, enint_coal);
8125 #ifdef AHD_DEBUG
8126 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8127 printf("%s: Interrupt coalescing "
8128 "now %sabled. Cmds %d\n",
8129 ahd_name(ahd),
8130 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8131 ahd->cmdcmplt_total);
8132 #endif
8133 }
8134
8135 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8136 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8137 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8138 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
8139 ahd_stat_timer, ahd);
8140 ahd_unlock(ahd, &s);
8141 ahd_list_unlock(&l);
8142 }
8143
8144 /****************************** Status Processing *****************************/
8145 void
8146 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8147 {
8148 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8149 ahd_handle_scsi_status(ahd, scb);
8150 } else {
8151 ahd_calc_residual(ahd, scb);
8152 ahd_done(ahd, scb);
8153 }
8154 }
8155
8156 void
8157 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8158 {
8159 struct hardware_scb *hscb;
8160 int paused;
8161
8162 /*
8163 * The sequencer freezes its select-out queue
8164 * anytime a SCSI status error occurs. We must
8165 * handle the error and increment our qfreeze count
8166 * to allow the sequencer to continue. We don't
8167 * bother clearing critical sections here since all
8168 * operations are on data structures that the sequencer
8169 * is not touching once the queue is frozen.
8170 */
8171 hscb = scb->hscb;
8172
8173 if (ahd_is_paused(ahd)) {
8174 paused = 1;
8175 } else {
8176 paused = 0;
8177 ahd_pause(ahd);
8178 }
8179
8180 /* Freeze the queue until the client sees the error. */
8181 ahd_freeze_devq(ahd, scb);
8182 aic_freeze_scb(scb);
8183 ahd->qfreeze_cnt++;
8184 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8185
8186 if (paused == 0)
8187 ahd_unpause(ahd);
8188
8189 /* Don't want to clobber the original sense code */
8190 if ((scb->flags & SCB_SENSE) != 0) {
8191 /*
8192 * Clear the SCB_SENSE Flag and perform
8193 * a normal command completion.
8194 */
8195 scb->flags &= ~SCB_SENSE;
8196 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8197 ahd_done(ahd, scb);
8198 return;
8199 }
8200 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8201 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8202 switch (hscb->shared_data.istatus.scsi_status) {
8203 case STATUS_PKT_SENSE:
8204 {
8205 struct scsi_status_iu_header *siu;
8206
8207 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8208 siu = (struct scsi_status_iu_header *)scb->sense_data;
8209 aic_set_scsi_status(scb, siu->status);
8210 #ifdef AHD_DEBUG
8211 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8212 ahd_print_path(ahd, scb);
8213 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8214 SCB_GET_TAG(scb), siu->status);
8215 printf("\tflags = 0x%x, sense len = 0x%x, "
8216 "pktfail = 0x%x\n",
8217 siu->flags, scsi_4btoul(siu->sense_length),
8218 scsi_4btoul(siu->pkt_failures_length));
8219 }
8220 #endif
8221 if ((siu->flags & SIU_RSPVALID) != 0) {
8222 ahd_print_path(ahd, scb);
8223 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8224 printf("Unable to parse pkt_failures\n");
8225 } else {
8226
8227 switch (SIU_PKTFAIL_CODE(siu)) {
8228 case SIU_PFC_NONE:
8229 printf("No packet failure found\n");
8230 break;
8231 case SIU_PFC_CIU_FIELDS_INVALID:
8232 printf("Invalid Command IU Field\n");
8233 break;
8234 case SIU_PFC_TMF_NOT_SUPPORTED:
8235 printf("TMF not supportd\n");
8236 break;
8237 case SIU_PFC_TMF_FAILED:
8238 printf("TMF failed\n");
8239 break;
8240 case SIU_PFC_INVALID_TYPE_CODE:
8241 printf("Invalid L_Q Type code\n");
8242 break;
8243 case SIU_PFC_ILLEGAL_REQUEST:
8244 printf("Illegal request\n");
8245 default:
8246 break;
8247 }
8248 }
8249 if (siu->status == SCSI_STATUS_OK)
8250 aic_set_transaction_status(scb,
8251 CAM_REQ_CMP_ERR);
8252 }
8253 if ((siu->flags & SIU_SNSVALID) != 0) {
8254 scb->flags |= SCB_PKT_SENSE;
8255 #ifdef AHD_DEBUG
8256 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8257 printf("Sense data available\n");
8258 #endif
8259 }
8260 ahd_done(ahd, scb);
8261 break;
8262 }
8263 case SCSI_STATUS_CMD_TERMINATED:
8264 case SCSI_STATUS_CHECK_COND:
8265 {
8266 struct ahd_devinfo devinfo;
8267 struct ahd_dma_seg *sg;
8268 struct scsi_sense *sc;
8269 struct ahd_initiator_tinfo *targ_info;
8270 struct ahd_tmode_tstate *tstate;
8271 struct ahd_transinfo *tinfo;
8272 #ifdef AHD_DEBUG
8273 if (ahd_debug & AHD_SHOW_SENSE) {
8274 ahd_print_path(ahd, scb);
8275 printf("SCB %d: requests Check Status\n",
8276 SCB_GET_TAG(scb));
8277 }
8278 #endif
8279
8280 if (aic_perform_autosense(scb) == 0)
8281 break;
8282
8283 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8284 SCB_GET_TARGET(ahd, scb),
8285 SCB_GET_LUN(scb),
8286 SCB_GET_CHANNEL(ahd, scb),
8287 ROLE_INITIATOR);
8288 targ_info = ahd_fetch_transinfo(ahd,
8289 devinfo.channel,
8290 devinfo.our_scsiid,
8291 devinfo.target,
8292 &tstate);
8293 tinfo = &targ_info->curr;
8294 sg = scb->sg_list;
8295 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8296 /*
8297 * Save off the residual if there is one.
8298 */
8299 ahd_update_residual(ahd, scb);
8300 #ifdef AHD_DEBUG
8301 if (ahd_debug & AHD_SHOW_SENSE) {
8302 ahd_print_path(ahd, scb);
8303 printf("Sending Sense\n");
8304 }
8305 #endif
8306 scb->sg_count = 0;
8307 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8308 aic_get_sense_bufsize(ahd, scb),
8309 /*last*/TRUE);
8310 sc->opcode = REQUEST_SENSE;
8311 sc->byte2 = 0;
8312 if (tinfo->protocol_version <= SCSI_REV_2
8313 && SCB_GET_LUN(scb) < 8)
8314 sc->byte2 = SCB_GET_LUN(scb) << 5;
8315 sc->unused[0] = 0;
8316 sc->unused[1] = 0;
8317 sc->length = aic_get_sense_bufsize(ahd, scb);
8318 sc->control = 0;
8319
8320 /*
8321 * We can't allow the target to disconnect.
8322 * This will be an untagged transaction and
8323 * having the target disconnect will make this
8324 * transaction indestinguishable from outstanding
8325 * tagged transactions.
8326 */
8327 hscb->control = 0;
8328
8329 /*
8330 * This request sense could be because the
8331 * the device lost power or in some other
8332 * way has lost our transfer negotiations.
8333 * Renegotiate if appropriate. Unit attention
8334 * errors will be reported before any data
8335 * phases occur.
8336 */
8337 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) {
8338 ahd_update_neg_request(ahd, &devinfo,
8339 tstate, targ_info,
8340 AHD_NEG_IF_NON_ASYNC);
8341 }
8342 if (tstate->auto_negotiate & devinfo.target_mask) {
8343 hscb->control |= MK_MESSAGE;
8344 scb->flags &=
8345 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8346 scb->flags |= SCB_AUTO_NEGOTIATE;
8347 }
8348 hscb->cdb_len = sizeof(*sc);
8349 ahd_setup_data_scb(ahd, scb);
8350 scb->flags |= SCB_SENSE;
8351 ahd_queue_scb(ahd, scb);
8352 /*
8353 * Ensure we have enough time to actually
8354 * retrieve the sense, but only schedule
8355 * the timer if we are not in recovery or
8356 * this is a recovery SCB that is allowed
8357 * to have an active timer.
8358 */
8359 if (ahd->scb_data.recovery_scbs == 0
8360 || (scb->flags & SCB_RECOVERY_SCB) != 0)
8361 aic_scb_timer_reset(scb, 5 * 1000000);
8362 break;
8363 }
8364 case SCSI_STATUS_OK:
8365 printf("%s: Interrupted for staus of 0???\n",
8366 ahd_name(ahd));
8367 /* FALLTHROUGH */
8368 default:
8369 ahd_done(ahd, scb);
8370 break;
8371 }
8372 }
8373
8374 /*
8375 * Calculate the residual for a just completed SCB.
8376 */
8377 void
8378 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8379 {
8380 struct hardware_scb *hscb;
8381 struct initiator_status *spkt;
8382 uint32_t sgptr;
8383 uint32_t resid_sgptr;
8384 uint32_t resid;
8385
8386 /*
8387 * 5 cases.
8388 * 1) No residual.
8389 * SG_STATUS_VALID clear in sgptr.
8390 * 2) Transferless command
8391 * 3) Never performed any transfers.
8392 * sgptr has SG_FULL_RESID set.
8393 * 4) No residual but target did not
8394 * save data pointers after the
8395 * last transfer, so sgptr was
8396 * never updated.
8397 * 5) We have a partial residual.
8398 * Use residual_sgptr to determine
8399 * where we are.
8400 */
8401
8402 hscb = scb->hscb;
8403 sgptr = aic_le32toh(hscb->sgptr);
8404 if ((sgptr & SG_STATUS_VALID) == 0)
8405 /* Case 1 */
8406 return;
8407 sgptr &= ~SG_STATUS_VALID;
8408
8409 if ((sgptr & SG_LIST_NULL) != 0)
8410 /* Case 2 */
8411 return;
8412
8413 /*
8414 * Residual fields are the same in both
8415 * target and initiator status packets,
8416 * so we can always use the initiator fields
8417 * regardless of the role for this SCB.
8418 */
8419 spkt = &hscb->shared_data.istatus;
8420 resid_sgptr = aic_le32toh(spkt->residual_sgptr);
8421 if ((sgptr & SG_FULL_RESID) != 0) {
8422 /* Case 3 */
8423 resid = aic_get_transfer_length(scb);
8424 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8425 /* Case 4 */
8426 return;
8427 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8428 ahd_print_path(ahd, scb);
8429 printf("data overrun detected Tag == 0x%x.\n",
8430 SCB_GET_TAG(scb));
8431 ahd_freeze_devq(ahd, scb);
8432 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8433 aic_freeze_scb(scb);
8434 return;
8435 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8436 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8437 /* NOTREACHED */
8438 } else {
8439 struct ahd_dma_seg *sg;
8440
8441 /*
8442 * Remainder of the SG where the transfer
8443 * stopped.
8444 */
8445 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8446 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8447
8448 /* The residual sg_ptr always points to the next sg */
8449 sg--;
8450
8451 /*
8452 * Add up the contents of all residual
8453 * SG segments that are after the SG where
8454 * the transfer stopped.
8455 */
8456 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8457 sg++;
8458 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
8459 }
8460 }
8461 if ((scb->flags & SCB_SENSE) == 0)
8462 aic_set_residual(scb, resid);
8463 else
8464 aic_set_sense_residual(scb, resid);
8465
8466 #ifdef AHD_DEBUG
8467 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8468 ahd_print_path(ahd, scb);
8469 printf("Handled %sResidual of %d bytes\n",
8470 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8471 }
8472 #endif
8473 }
8474
8475 /******************************* Target Mode **********************************/
8476 #ifdef AHD_TARGET_MODE
8477 /*
8478 * Add a target mode event to this lun's queue
8479 */
8480 static void
8481 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8482 u_int initiator_id, u_int event_type, u_int event_arg)
8483 {
8484 struct ahd_tmode_event *event;
8485 int pending;
8486
8487 xpt_freeze_devq(lstate->path, /*count*/1);
8488 if (lstate->event_w_idx >= lstate->event_r_idx)
8489 pending = lstate->event_w_idx - lstate->event_r_idx;
8490 else
8491 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8492 - (lstate->event_r_idx - lstate->event_w_idx);
8493
8494 if (event_type == EVENT_TYPE_BUS_RESET
8495 || event_type == MSG_BUS_DEV_RESET) {
8496 /*
8497 * Any earlier events are irrelevant, so reset our buffer.
8498 * This has the effect of allowing us to deal with reset
8499 * floods (an external device holding down the reset line)
8500 * without losing the event that is really interesting.
8501 */
8502 lstate->event_r_idx = 0;
8503 lstate->event_w_idx = 0;
8504 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8505 }
8506
8507 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8508 xpt_print_path(lstate->path);
8509 printf("immediate event %x:%x lost\n",
8510 lstate->event_buffer[lstate->event_r_idx].event_type,
8511 lstate->event_buffer[lstate->event_r_idx].event_arg);
8512 lstate->event_r_idx++;
8513 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8514 lstate->event_r_idx = 0;
8515 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8516 }
8517
8518 event = &lstate->event_buffer[lstate->event_w_idx];
8519 event->initiator_id = initiator_id;
8520 event->event_type = event_type;
8521 event->event_arg = event_arg;
8522 lstate->event_w_idx++;
8523 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8524 lstate->event_w_idx = 0;
8525 }
8526
8527 /*
8528 * Send any target mode events queued up waiting
8529 * for immediate notify resources.
8530 */
8531 void
8532 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8533 {
8534 struct ccb_hdr *ccbh;
8535 struct ccb_immed_notify *inot;
8536
8537 while (lstate->event_r_idx != lstate->event_w_idx
8538 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8539 struct ahd_tmode_event *event;
8540
8541 event = &lstate->event_buffer[lstate->event_r_idx];
8542 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8543 inot = (struct ccb_immed_notify *)ccbh;
8544 switch (event->event_type) {
8545 case EVENT_TYPE_BUS_RESET:
8546 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8547 break;
8548 default:
8549 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8550 inot->message_args[0] = event->event_type;
8551 inot->message_args[1] = event->event_arg;
8552 break;
8553 }
8554 inot->initiator_id = event->initiator_id;
8555 inot->sense_len = 0;
8556 xpt_done((union ccb *)inot);
8557 lstate->event_r_idx++;
8558 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8559 lstate->event_r_idx = 0;
8560 }
8561 }
8562 #endif
8563
8564 /******************** Sequencer Program Patching/Download *********************/
8565
8566 #ifdef AHD_DUMP_SEQ
8567 void
8568 ahd_dumpseq(struct ahd_softc* ahd)
8569 {
8570 int i;
8571 int max_prog;
8572
8573 max_prog = 2048;
8574
8575 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8576 ahd_outw(ahd, PRGMCNT, 0);
8577 for (i = 0; i < max_prog; i++) {
8578 uint8_t ins_bytes[4];
8579
8580 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8581 printf("0x%08x\n", ins_bytes[0] << 24
8582 | ins_bytes[1] << 16
8583 | ins_bytes[2] << 8
8584 | ins_bytes[3]);
8585 }
8586 }
8587 #endif
8588
8589 static void
8590 ahd_loadseq(struct ahd_softc *ahd)
8591 {
8592 struct cs cs_table[num_critical_sections];
8593 u_int begin_set[num_critical_sections];
8594 u_int end_set[num_critical_sections];
8595 struct patch *cur_patch;
8596 u_int cs_count;
8597 u_int cur_cs;
8598 u_int i;
8599 int downloaded;
8600 u_int skip_addr;
8601 u_int sg_prefetch_cnt;
8602 u_int sg_prefetch_cnt_limit;
8603 u_int sg_prefetch_align;
8604 u_int sg_size;
8605 u_int cacheline_mask;
8606 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8607
8608 if (bootverbose)
8609 printf("%s: Downloading Sequencer Program...",
8610 ahd_name(ahd));
8611
8612 #if DOWNLOAD_CONST_COUNT != 8
8613 #error "Download Const Mismatch"
8614 #endif
8615 /*
8616 * Start out with 0 critical sections
8617 * that apply to this firmware load.
8618 */
8619 cs_count = 0;
8620 cur_cs = 0;
8621 memset(begin_set, 0, sizeof(begin_set));
8622 memset(end_set, 0, sizeof(end_set));
8623
8624 /*
8625 * Setup downloadable constant table.
8626 *
8627 * The computation for the S/G prefetch variables is
8628 * a bit complicated. We would like to always fetch
8629 * in terms of cachelined sized increments. However,
8630 * if the cacheline is not an even multiple of the
8631 * SG element size or is larger than our SG RAM, using
8632 * just the cache size might leave us with only a portion
8633 * of an SG element at the tail of a prefetch. If the
8634 * cacheline is larger than our S/G prefetch buffer less
8635 * the size of an SG element, we may round down to a cacheline
8636 * that doesn't contain any or all of the S/G of interest
8637 * within the bounds of our S/G ram. Provide variables to
8638 * the sequencer that will allow it to handle these edge
8639 * cases.
8640 */
8641 /* Start by aligning to the nearest cacheline. */
8642 sg_prefetch_align = ahd->pci_cachesize;
8643 if (sg_prefetch_align == 0)
8644 sg_prefetch_align = 8;
8645 /* Round down to the nearest power of 2. */
8646 while (powerof2(sg_prefetch_align) == 0)
8647 sg_prefetch_align--;
8648
8649 cacheline_mask = sg_prefetch_align - 1;
8650
8651 /*
8652 * If the cacheline boundary is greater than half our prefetch RAM
8653 * we risk not being able to fetch even a single complete S/G
8654 * segment if we align to that boundary.
8655 */
8656 if (sg_prefetch_align > CCSGADDR_MAX/2)
8657 sg_prefetch_align = CCSGADDR_MAX/2;
8658 /* Start by fetching a single cacheline. */
8659 sg_prefetch_cnt = sg_prefetch_align;
8660 /*
8661 * Increment the prefetch count by cachelines until
8662 * at least one S/G element will fit.
8663 */
8664 sg_size = sizeof(struct ahd_dma_seg);
8665 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8666 sg_size = sizeof(struct ahd_dma64_seg);
8667 while (sg_prefetch_cnt < sg_size)
8668 sg_prefetch_cnt += sg_prefetch_align;
8669 /*
8670 * If the cacheline is not an even multiple of
8671 * the S/G size, we may only get a partial S/G when
8672 * we align. Add a cacheline if this is the case.
8673 */
8674 if ((sg_prefetch_align % sg_size) != 0
8675 && (sg_prefetch_cnt < CCSGADDR_MAX))
8676 sg_prefetch_cnt += sg_prefetch_align;
8677 /*
8678 * Lastly, compute a value that the sequencer can use
8679 * to determine if the remainder of the CCSGRAM buffer
8680 * has a full S/G element in it.
8681 */
8682 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8683 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8684 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8685 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8686 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8687 download_consts[SG_SIZEOF] = sg_size;
8688 download_consts[PKT_OVERRUN_BUFOFFSET] =
8689 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8690 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8691 download_consts[CACHELINE_MASK] = cacheline_mask;
8692 cur_patch = patches;
8693 downloaded = 0;
8694 skip_addr = 0;
8695 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8696 ahd_outw(ahd, PRGMCNT, 0);
8697
8698 for (i = 0; i < sizeof(seqprog)/4; i++) {
8699 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8700 /*
8701 * Don't download this instruction as it
8702 * is in a patch that was removed.
8703 */
8704 continue;
8705 }
8706 /*
8707 * Move through the CS table until we find a CS
8708 * that might apply to this instruction.
8709 */
8710 for (; cur_cs < num_critical_sections; cur_cs++) {
8711 if (critical_sections[cur_cs].end <= i) {
8712 if (begin_set[cs_count] == TRUE
8713 && end_set[cs_count] == FALSE) {
8714 cs_table[cs_count].end = downloaded;
8715 end_set[cs_count] = TRUE;
8716 cs_count++;
8717 }
8718 continue;
8719 }
8720 if (critical_sections[cur_cs].begin <= i
8721 && begin_set[cs_count] == FALSE) {
8722 cs_table[cs_count].begin = downloaded;
8723 begin_set[cs_count] = TRUE;
8724 }
8725 break;
8726 }
8727 ahd_download_instr(ahd, i, download_consts);
8728 downloaded++;
8729 }
8730
8731 ahd->num_critical_sections = cs_count;
8732 if (cs_count != 0) {
8733
8734 cs_count *= sizeof(struct cs);
8735 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
8736 if (ahd->critical_sections == NULL)
8737 panic("ahd_loadseq: Could not malloc");
8738 memcpy(ahd->critical_sections, cs_table, cs_count);
8739 }
8740 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8741
8742 if (bootverbose) {
8743 printf(" %d instructions downloaded\n", downloaded);
8744 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8745 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8746 }
8747 }
8748
8749 static int
8750 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8751 u_int start_instr, u_int *skip_addr)
8752 {
8753 struct patch *cur_patch;
8754 struct patch *last_patch;
8755 u_int num_patches;
8756
8757 num_patches = sizeof(patches)/sizeof(struct patch);
8758 last_patch = &patches[num_patches];
8759 cur_patch = *start_patch;
8760
8761 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8762
8763 if (cur_patch->patch_func(ahd) == 0) {
8764
8765 /* Start rejecting code */
8766 *skip_addr = start_instr + cur_patch->skip_instr;
8767 cur_patch += cur_patch->skip_patch;
8768 } else {
8769 /* Accepted this patch. Advance to the next
8770 * one and wait for our intruction pointer to
8771 * hit this point.
8772 */
8773 cur_patch++;
8774 }
8775 }
8776
8777 *start_patch = cur_patch;
8778 if (start_instr < *skip_addr)
8779 /* Still skipping */
8780 return (0);
8781
8782 return (1);
8783 }
8784
8785 static u_int
8786 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8787 {
8788 struct patch *cur_patch;
8789 int address_offset;
8790 u_int skip_addr;
8791 u_int i;
8792
8793 address_offset = 0;
8794 cur_patch = patches;
8795 skip_addr = 0;
8796
8797 for (i = 0; i < address;) {
8798
8799 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8800
8801 if (skip_addr > i) {
8802 int end_addr;
8803
8804 end_addr = MIN(address, skip_addr);
8805 address_offset += end_addr - i;
8806 i = skip_addr;
8807 } else {
8808 i++;
8809 }
8810 }
8811 return (address - address_offset);
8812 }
8813
8814 static void
8815 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8816 {
8817 union ins_formats instr;
8818 struct ins_format1 *fmt1_ins;
8819 struct ins_format3 *fmt3_ins;
8820 u_int opcode;
8821
8822 /*
8823 * The firmware is always compiled into a little endian format.
8824 */
8825 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8826
8827 fmt1_ins = &instr.format1;
8828 fmt3_ins = NULL;
8829
8830 /* Pull the opcode */
8831 opcode = instr.format1.opcode;
8832 switch (opcode) {
8833 case AIC_OP_JMP:
8834 case AIC_OP_JC:
8835 case AIC_OP_JNC:
8836 case AIC_OP_CALL:
8837 case AIC_OP_JNE:
8838 case AIC_OP_JNZ:
8839 case AIC_OP_JE:
8840 case AIC_OP_JZ:
8841 {
8842 fmt3_ins = &instr.format3;
8843 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8844 /* FALLTHROUGH */
8845 }
8846 case AIC_OP_OR:
8847 case AIC_OP_AND:
8848 case AIC_OP_XOR:
8849 case AIC_OP_ADD:
8850 case AIC_OP_ADC:
8851 case AIC_OP_BMOV:
8852 if (fmt1_ins->parity != 0) {
8853 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8854 }
8855 fmt1_ins->parity = 0;
8856 /* FALLTHROUGH */
8857 case AIC_OP_ROL:
8858 {
8859 int i, count;
8860
8861 /* Calculate odd parity for the instruction */
8862 for (i = 0, count = 0; i < 31; i++) {
8863 uint32_t mask;
8864
8865 mask = 0x01 << i;
8866 if ((instr.integer & mask) != 0)
8867 count++;
8868 }
8869 if ((count & 0x01) == 0)
8870 instr.format1.parity = 1;
8871
8872 /* The sequencer is a little endian cpu */
8873 instr.integer = aic_htole32(instr.integer);
8874 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8875 break;
8876 }
8877 default:
8878 panic("Unknown opcode encountered in seq program");
8879 break;
8880 }
8881 }
8882
8883 static int
8884 ahd_probe_stack_size(struct ahd_softc *ahd)
8885 {
8886 int last_probe;
8887
8888 last_probe = 0;
8889 while (1) {
8890 int i;
8891
8892 /*
8893 * We avoid using 0 as a pattern to avoid
8894 * confusion if the stack implementation
8895 * "back-fills" with zeros when "poping'
8896 * entries.
8897 */
8898 for (i = 1; i <= last_probe+1; i++) {
8899 ahd_outb(ahd, STACK, i & 0xFF);
8900 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8901 }
8902
8903 /* Verify */
8904 for (i = last_probe+1; i > 0; i--) {
8905 u_int stack_entry;
8906
8907 stack_entry = ahd_inb(ahd, STACK)
8908 |(ahd_inb(ahd, STACK) << 8);
8909 if (stack_entry != i)
8910 goto sized;
8911 }
8912 last_probe++;
8913 }
8914 sized:
8915 return (last_probe);
8916 }
8917
8918 void
8919 ahd_dump_all_cards_state(void)
8920 {
8921 struct ahd_softc *list_ahd;
8922
8923 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8924 ahd_dump_card_state(list_ahd);
8925 }
8926 }
8927
8928 int
8929 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8930 const char *name, u_int address, u_int value,
8931 u_int *cur_column, u_int wrap_point)
8932 {
8933 int printed;
8934 u_int printed_mask;
8935
8936 if (cur_column != NULL && *cur_column >= wrap_point) {
8937 printf("\n");
8938 *cur_column = 0;
8939 }
8940 printed = printf("%s[0x%x]", name, value);
8941 if (table == NULL) {
8942 printed += printf(" ");
8943 *cur_column += printed;
8944 return (printed);
8945 }
8946 printed_mask = 0;
8947 while (printed_mask != 0xFF) {
8948 int entry;
8949
8950 for (entry = 0; entry < num_entries; entry++) {
8951 if (((value & table[entry].mask)
8952 != table[entry].value)
8953 || ((printed_mask & table[entry].mask)
8954 == table[entry].mask))
8955 continue;
8956
8957 printed += printf("%s%s",
8958 printed_mask == 0 ? ":(" : "|",
8959 table[entry].name);
8960 printed_mask |= table[entry].mask;
8961
8962 break;
8963 }
8964 if (entry >= num_entries)
8965 break;
8966 }
8967 if (printed_mask != 0)
8968 printed += printf(") ");
8969 else
8970 printed += printf(" ");
8971 if (cur_column != NULL)
8972 *cur_column += printed;
8973 return (printed);
8974 }
8975
8976 void
8977 ahd_dump_card_state(struct ahd_softc *ahd)
8978 {
8979 struct scb *scb;
8980 ahd_mode_state saved_modes;
8981 u_int dffstat;
8982 int paused;
8983 u_int scb_index;
8984 u_int saved_scb_index;
8985 u_int cur_col;
8986 int i;
8987
8988 if (ahd_is_paused(ahd)) {
8989 paused = 1;
8990 } else {
8991 paused = 0;
8992 ahd_pause(ahd);
8993 }
8994 saved_modes = ahd_save_modes(ahd);
8995 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8996 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8997 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8998 ahd_name(ahd),
8999 ahd_inw(ahd, CURADDR),
9000 ahd_build_mode_state(ahd, ahd->saved_src_mode,
9001 ahd->saved_dst_mode));
9002 if (paused)
9003 printf("Card was paused\n");
9004
9005 if (ahd_check_cmdcmpltqueues(ahd))
9006 printf("Completions are pending\n");
9007
9008 /*
9009 * Mode independent registers.
9010 */
9011 cur_col = 0;
9012 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
9013 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
9014 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
9015 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
9016 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
9017 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
9018 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
9019 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
9020 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
9021 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
9022 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
9023 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
9024 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
9025 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
9026 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
9027 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
9028 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
9029 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
9030 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
9031 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
9032 &cur_col, 50);
9033 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
9034 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
9035 &cur_col, 50);
9036 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
9037 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
9038 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
9039 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
9040 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
9041 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
9042 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
9043 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
9044 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
9045 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
9046 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
9047 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
9048 printf("\n");
9049 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
9050 "CURRSCB 0x%x NEXTSCB 0x%x\n",
9051 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
9052 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
9053 ahd_inw(ahd, NEXTSCB));
9054 cur_col = 0;
9055 /* QINFIFO */
9056 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
9057 CAM_LUN_WILDCARD, SCB_LIST_NULL,
9058 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
9059 saved_scb_index = ahd_get_scbptr(ahd);
9060 printf("Pending list:");
9061 i = 0;
9062 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9063 if (i++ > AHD_SCB_MAX)
9064 break;
9065 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
9066 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
9067 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9068 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
9069 &cur_col, 60);
9070 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
9071 &cur_col, 60);
9072 }
9073 printf("\nTotal %d\n", i);
9074
9075 printf("Kernel Free SCB list: ");
9076 i = 0;
9077 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
9078 struct scb *list_scb;
9079
9080 list_scb = scb;
9081 do {
9082 printf("%d ", SCB_GET_TAG(list_scb));
9083 list_scb = LIST_NEXT(list_scb, collision_links);
9084 } while (list_scb && i++ < AHD_SCB_MAX);
9085 }
9086
9087 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
9088 if (i++ > AHD_SCB_MAX)
9089 break;
9090 printf("%d ", SCB_GET_TAG(scb));
9091 }
9092 printf("\n");
9093
9094 printf("Sequencer Complete DMA-inprog list: ");
9095 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
9096 i = 0;
9097 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9098 ahd_set_scbptr(ahd, scb_index);
9099 printf("%d ", scb_index);
9100 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9101 }
9102 printf("\n");
9103
9104 printf("Sequencer Complete list: ");
9105 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
9106 i = 0;
9107 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9108 ahd_set_scbptr(ahd, scb_index);
9109 printf("%d ", scb_index);
9110 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9111 }
9112 printf("\n");
9113
9114
9115 printf("Sequencer DMA-Up and Complete list: ");
9116 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9117 i = 0;
9118 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9119 ahd_set_scbptr(ahd, scb_index);
9120 printf("%d ", scb_index);
9121 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9122 }
9123 printf("\n");
9124 printf("Sequencer On QFreeze and Complete list: ");
9125 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9126 i = 0;
9127 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9128 ahd_set_scbptr(ahd, scb_index);
9129 printf("%d ", scb_index);
9130 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9131 }
9132 printf("\n");
9133 ahd_set_scbptr(ahd, saved_scb_index);
9134 dffstat = ahd_inb(ahd, DFFSTAT);
9135 for (i = 0; i < 2; i++) {
9136 #ifdef AHD_DEBUG
9137 struct scb *fifo_scb;
9138 #endif
9139 u_int fifo_scbptr;
9140
9141 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9142 fifo_scbptr = ahd_get_scbptr(ahd);
9143 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9144 ahd_name(ahd), i,
9145 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9146 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9147 cur_col = 0;
9148 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9149 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9150 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9151 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9152 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9153 &cur_col, 50);
9154 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9155 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9156 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9157 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9158 if (cur_col > 50) {
9159 printf("\n");
9160 cur_col = 0;
9161 }
9162 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9163 ahd_inl(ahd, SHADDR+4),
9164 ahd_inl(ahd, SHADDR),
9165 (ahd_inb(ahd, SHCNT)
9166 | (ahd_inb(ahd, SHCNT + 1) << 8)
9167 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9168 if (cur_col > 50) {
9169 printf("\n");
9170 cur_col = 0;
9171 }
9172 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9173 ahd_inl(ahd, HADDR+4),
9174 ahd_inl(ahd, HADDR),
9175 (ahd_inb(ahd, HCNT)
9176 | (ahd_inb(ahd, HCNT + 1) << 8)
9177 | (ahd_inb(ahd, HCNT + 2) << 16)));
9178 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9179 #ifdef AHD_DEBUG
9180 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9181 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9182 if (fifo_scb != NULL)
9183 ahd_dump_sglist(fifo_scb);
9184 }
9185 #endif
9186 }
9187 printf("\nLQIN: ");
9188 for (i = 0; i < 20; i++)
9189 printf("0x%x ", ahd_inb(ahd, LQIN + i));
9190 printf("\n");
9191 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9192 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9193 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9194 ahd_inb(ahd, OPTIONMODE));
9195 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9196 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9197 ahd_inb(ahd, MAXCMDCNT));
9198 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9199 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9200 ahd_inb(ahd, SAVED_LUN));
9201 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9202 printf("\n");
9203 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9204 cur_col = 0;
9205 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9206 printf("\n");
9207 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9208 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9209 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9210 ahd_inw(ahd, DINDEX));
9211 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9212 ahd_name(ahd), ahd_get_scbptr(ahd),
9213 ahd_inw_scbram(ahd, SCB_NEXT),
9214 ahd_inw_scbram(ahd, SCB_NEXT2));
9215 printf("CDB %x %x %x %x %x %x\n",
9216 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9217 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9218 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9219 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9220 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9221 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
9222 printf("STACK:");
9223 for (i = 0; i < ahd->stack_size; i++) {
9224 ahd->saved_stack[i] =
9225 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9226 printf(" 0x%x", ahd->saved_stack[i]);
9227 }
9228 for (i = ahd->stack_size-1; i >= 0; i--) {
9229 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9230 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9231 }
9232 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9233 ahd_platform_dump_card_state(ahd);
9234 ahd_restore_modes(ahd, saved_modes);
9235 if (paused == 0)
9236 ahd_unpause(ahd);
9237 }
9238
9239 void
9240 ahd_dump_scbs(struct ahd_softc *ahd)
9241 {
9242 ahd_mode_state saved_modes;
9243 u_int saved_scb_index;
9244 int i;
9245
9246 saved_modes = ahd_save_modes(ahd);
9247 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9248 saved_scb_index = ahd_get_scbptr(ahd);
9249 for (i = 0; i < AHD_SCB_MAX; i++) {
9250 ahd_set_scbptr(ahd, i);
9251 printf("%3d", i);
9252 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9253 ahd_inb_scbram(ahd, SCB_CONTROL),
9254 ahd_inb_scbram(ahd, SCB_SCSIID),
9255 ahd_inw_scbram(ahd, SCB_NEXT),
9256 ahd_inw_scbram(ahd, SCB_NEXT2),
9257 ahd_inl_scbram(ahd, SCB_SGPTR),
9258 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9259 }
9260 printf("\n");
9261 ahd_set_scbptr(ahd, saved_scb_index);
9262 ahd_restore_modes(ahd, saved_modes);
9263 }
9264
9265
9266 /*************************** Timeout Handling *********************************/
9267 void
9268 ahd_timeout(struct scb *scb)
9269 {
9270 struct ahd_softc *ahd;
9271
9272 ahd = scb->ahd_softc;
9273 if ((scb->flags & SCB_ACTIVE) != 0) {
9274 if ((scb->flags & SCB_TIMEDOUT) == 0) {
9275 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb,
9276 timedout_links);
9277 scb->flags |= SCB_TIMEDOUT;
9278 }
9279 ahd_wakeup_recovery_thread(ahd);
9280 }
9281 }
9282
9283 /*
9284 * ahd_recover_commands determines if any of the commands that have currently
9285 * timedout are the root cause for this timeout. Innocent commands are given
9286 * a new timeout while we wait for the command executing on the bus to timeout.
9287 * This routine is invoked from a thread context so we are allowed to sleep.
9288 * Our lock is not held on entry.
9289 */
9290 void
9291 ahd_recover_commands(struct ahd_softc *ahd)
9292 {
9293 struct scb *scb;
9294 struct scb *active_scb;
9295 long s;
9296 int found;
9297 int was_paused;
9298 u_int active_scbptr;
9299 u_int last_phase;
9300
9301 ahd_lock(ahd, &s);
9302
9303 /*
9304 * Pause the controller and manually flush any
9305 * commands that have just completed but that our
9306 * interrupt handler has yet to see.
9307 */
9308 was_paused = ahd_is_paused(ahd);
9309
9310 printf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd),
9311 was_paused ? "" : "not ");
9312 ahd_dump_card_state(ahd);
9313
9314 ahd_pause_and_flushwork(ahd);
9315
9316 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) {
9317 /*
9318 * The timedout commands have already
9319 * completed. This typically means
9320 * that either the timeout value was on
9321 * the hairy edge of what the device
9322 * requires or - more likely - interrupts
9323 * are not happening.
9324 */
9325 printf("%s: Timedout SCBs already complete. "
9326 "Interrupts may not be functioning.\n", ahd_name(ahd));
9327 ahd_unpause(ahd);
9328 ahd_unlock(ahd, &s);
9329 return;
9330 }
9331
9332 /*
9333 * Determine identity of SCB acting on the bus.
9334 * This test only catches non-packetized transactions.
9335 * Due to the fleeting nature of packetized operations,
9336 * we can't easily determine that a packetized operation
9337 * is on the bus.
9338 */
9339 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9340 last_phase = ahd_inb(ahd, LASTPHASE);
9341 active_scbptr = ahd_get_scbptr(ahd);
9342 active_scb = NULL;
9343 if (last_phase != P_BUSFREE
9344 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)
9345 active_scb = ahd_lookup_scb(ahd, active_scbptr);
9346
9347 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9348 int target;
9349 int lun;
9350 char channel;
9351
9352 target = SCB_GET_TARGET(ahd, scb);
9353 channel = SCB_GET_CHANNEL(ahd, scb);
9354 lun = SCB_GET_LUN(scb);
9355
9356 ahd_print_path(ahd, scb);
9357 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
9358
9359 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
9360 /*
9361 * Been down this road before.
9362 * Do a full bus reset.
9363 */
9364 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
9365 bus_reset:
9366 found = ahd_reset_channel(ahd, channel,
9367 /*Initiate Reset*/TRUE);
9368 printf("%s: Issued Channel %c Bus Reset. "
9369 "%d SCBs aborted\n", ahd_name(ahd), channel,
9370 found);
9371 continue;
9372 }
9373
9374 /*
9375 * Remove the command from the timedout list in
9376 * preparation for requeing it.
9377 */
9378 LIST_REMOVE(scb, timedout_links);
9379 scb->flags &= ~SCB_TIMEDOUT;
9380
9381 if (active_scb != NULL) {
9382
9383 if (active_scb != scb) {
9384
9385 /*
9386 * If the active SCB is not us, assume that
9387 * the active SCB has a longer timeout than
9388 * the timedout SCB, and wait for the active
9389 * SCB to timeout. As a safeguard, only
9390 * allow this deferral to continue if some
9391 * untimed-out command is outstanding.
9392 */
9393 if (ahd_other_scb_timeout(ahd, scb,
9394 active_scb) == 0)
9395 goto bus_reset;
9396 continue;
9397 }
9398
9399 /*
9400 * We're active on the bus, so assert ATN
9401 * and hope that the target responds.
9402 */
9403 ahd_set_recoveryscb(ahd, active_scb);
9404 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
9405 ahd_outb(ahd, MSG_OUT, HOST_MSG);
9406 ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
9407 ahd_print_path(ahd, active_scb);
9408 printf("BDR message in message buffer\n");
9409 aic_scb_timer_reset(scb, 2 * 1000000);
9410 break;
9411 } else if (last_phase != P_BUSFREE
9412 && ahd_inb(ahd, SCSIPHASE) == 0) {
9413 /*
9414 * SCB is not identified, there
9415 * is no pending REQ, and the sequencer
9416 * has not seen a busfree. Looks like
9417 * a stuck connection waiting to
9418 * go busfree. Reset the bus.
9419 */
9420 printf("%s: Connection stuck awaiting busfree or "
9421 "Identify Msg.\n", ahd_name(ahd));
9422 goto bus_reset;
9423 } else if (ahd_search_qinfifo(ahd, target, channel, lun,
9424 scb->hscb->tag, ROLE_INITIATOR,
9425 /*status*/0, SEARCH_COUNT) > 0) {
9426
9427 /*
9428 * We haven't even gone out on the bus
9429 * yet, so the timeout must be due to
9430 * some other command. Reset the timer
9431 * and go on.
9432 */
9433 if (ahd_other_scb_timeout(ahd, scb, NULL) == 0)
9434 goto bus_reset;
9435 } else {
9436 /*
9437 * This SCB is for a disconnected transaction
9438 * and we haven't found a better candidate on
9439 * the bus to explain this timeout.
9440 */
9441 ahd_set_recoveryscb(ahd, scb);
9442
9443 /*
9444 * Actually re-queue this SCB in an attempt
9445 * to select the device before it reconnects.
9446 * In either case (selection or reselection),
9447 * we will now issue a target reset to the
9448 * timed-out device.
9449 */
9450 scb->flags |= SCB_DEVICE_RESET;
9451 scb->hscb->cdb_len = 0;
9452 scb->hscb->task_attribute = 0;
9453 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK;
9454
9455 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9456 if ((scb->flags & SCB_PACKETIZED) != 0) {
9457 /*
9458 * Mark the SCB has having an outstanding
9459 * task management function. Should the command
9460 * complete normally before the task management
9461 * function can be sent, the host will be
9462 * notified to abort our requeued SCB.
9463 */
9464 ahd_outb(ahd, SCB_TASK_MANAGEMENT,
9465 scb->hscb->task_management);
9466 } else {
9467 /*
9468 * If non-packetized, set the MK_MESSAGE control
9469 * bit indicating that we desire to send a
9470 * message. We also set the disconnected flag
9471 * since there is no guarantee that our SCB
9472 * control byte matches the version on the
9473 * card. We don't want the sequencer to abort
9474 * the command thinking an unsolicited
9475 * reselection occurred.
9476 */
9477 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
9478
9479 /*
9480 * The sequencer will never re-reference the
9481 * in-core SCB. To make sure we are notified
9482 * during reslection, set the MK_MESSAGE flag in
9483 * the card's copy of the SCB.
9484 */
9485 ahd_outb(ahd, SCB_CONTROL,
9486 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE);
9487 }
9488
9489 /*
9490 * Clear out any entries in the QINFIFO first
9491 * so we are the next SCB for this target
9492 * to run.
9493 */
9494 ahd_search_qinfifo(ahd, target, channel, lun,
9495 SCB_LIST_NULL, ROLE_INITIATOR,
9496 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
9497 ahd_qinfifo_requeue_tail(ahd, scb);
9498 ahd_set_scbptr(ahd, active_scbptr);
9499 ahd_print_path(ahd, scb);
9500 printf("Queuing a BDR SCB\n");
9501 aic_scb_timer_reset(scb, 2 * 1000000);
9502 break;
9503 }
9504 }
9505
9506 /*
9507 * Any remaining SCBs were not the "culprit", so remove
9508 * them from the timeout list. The timer for these commands
9509 * will be reset once the recovery SCB completes.
9510 */
9511 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9512
9513 LIST_REMOVE(scb, timedout_links);
9514 scb->flags &= ~SCB_TIMEDOUT;
9515 }
9516
9517 ahd_unpause(ahd);
9518 ahd_unlock(ahd, &s);
9519 }
9520
9521 /*
9522 * Re-schedule a timeout for the passed in SCB if we determine that some
9523 * other SCB is in the process of recovery or an SCB with a longer
9524 * timeout is still pending. Limit our search to just "other_scb"
9525 * if it is non-NULL.
9526 */
9527 static int
9528 ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb,
9529 struct scb *other_scb)
9530 {
9531 u_int newtimeout;
9532 int found;
9533
9534 ahd_print_path(ahd, scb);
9535 printf("Other SCB Timeout%s",
9536 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
9537 ? " again\n" : "\n");
9538
9539 newtimeout = aic_get_timeout(scb);
9540 scb->flags |= SCB_OTHERTCL_TIMEOUT;
9541 found = 0;
9542 if (other_scb != NULL) {
9543 if ((other_scb->flags
9544 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9545 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9546 found++;
9547 newtimeout = MAX(aic_get_timeout(other_scb),
9548 newtimeout);
9549 }
9550 } else {
9551 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) {
9552 if ((other_scb->flags
9553 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9554 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9555 found++;
9556 newtimeout = MAX(aic_get_timeout(other_scb),
9557 newtimeout);
9558 }
9559 }
9560 }
9561
9562 if (found != 0)
9563 aic_scb_timer_reset(scb, newtimeout);
9564 else {
9565 ahd_print_path(ahd, scb);
9566 printf("No other SCB worth waiting for...\n");
9567 }
9568
9569 return (found != 0);
9570 }
9571
9572 /**************************** Flexport Logic **********************************/
9573 /*
9574 * Read count 16bit words from 16bit word address start_addr from the
9575 * SEEPROM attached to the controller, into buf, using the controller's
9576 * SEEPROM reading state machine. Optionally treat the data as a byte
9577 * stream in terms of byte order.
9578 */
9579 int
9580 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9581 u_int start_addr, u_int count, int bytestream)
9582 {
9583 u_int cur_addr;
9584 u_int end_addr;
9585 int error;
9586
9587 /*
9588 * If we never make it through the loop even once,
9589 * we were passed invalid arguments.
9590 */
9591 error = EINVAL;
9592 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9593 end_addr = start_addr + count;
9594 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9595
9596 ahd_outb(ahd, SEEADR, cur_addr);
9597 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9598
9599 error = ahd_wait_seeprom(ahd);
9600 if (error)
9601 break;
9602 if (bytestream != 0) {
9603 uint8_t *bytestream_ptr;
9604
9605 bytestream_ptr = (uint8_t *)buf;
9606 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9607 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9608 } else {
9609 /*
9610 * ahd_inw() already handles machine byte order.
9611 */
9612 *buf = ahd_inw(ahd, SEEDAT);
9613 }
9614 buf++;
9615 }
9616 return (error);
9617 }
9618
9619 /*
9620 * Write count 16bit words from buf, into SEEPROM attache to the
9621 * controller starting at 16bit word address start_addr, using the
9622 * controller's SEEPROM writing state machine.
9623 */
9624 int
9625 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9626 u_int start_addr, u_int count)
9627 {
9628 u_int cur_addr;
9629 u_int end_addr;
9630 int error;
9631 int retval;
9632
9633 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9634 error = ENOENT;
9635
9636 /* Place the chip into write-enable mode */
9637 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9638 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9639 error = ahd_wait_seeprom(ahd);
9640 if (error)
9641 return (error);
9642
9643 /*
9644 * Write the data. If we don't get throught the loop at
9645 * least once, the arguments were invalid.
9646 */
9647 retval = EINVAL;
9648 end_addr = start_addr + count;
9649 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9650 ahd_outw(ahd, SEEDAT, *buf++);
9651 ahd_outb(ahd, SEEADR, cur_addr);
9652 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9653
9654 retval = ahd_wait_seeprom(ahd);
9655 if (retval)
9656 break;
9657 }
9658
9659 /*
9660 * Disable writes.
9661 */
9662 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9663 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9664 error = ahd_wait_seeprom(ahd);
9665 if (error)
9666 return (error);
9667 return (retval);
9668 }
9669
9670 /*
9671 * Wait ~100us for the serial eeprom to satisfy our request.
9672 */
9673 int
9674 ahd_wait_seeprom(struct ahd_softc *ahd)
9675 {
9676 int cnt;
9677
9678 cnt = 5000;
9679 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9680 aic_delay(5);
9681
9682 if (cnt == 0)
9683 return (ETIMEDOUT);
9684 return (0);
9685 }
9686
9687 /*
9688 * Validate the two checksums in the per_channel
9689 * vital product data struct.
9690 */
9691 int
9692 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9693 {
9694 int i;
9695 int maxaddr;
9696 uint32_t checksum;
9697 uint8_t *vpdarray;
9698
9699 vpdarray = (uint8_t *)vpd;
9700 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9701 checksum = 0;
9702 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9703 checksum = checksum + vpdarray[i];
9704 if (checksum == 0
9705 || (-checksum & 0xFF) != vpd->vpd_checksum)
9706 return (0);
9707
9708 checksum = 0;
9709 maxaddr = offsetof(struct vpd_config, checksum);
9710 for (i = offsetof(struct vpd_config, default_target_flags);
9711 i < maxaddr; i++)
9712 checksum = checksum + vpdarray[i];
9713 if (checksum == 0
9714 || (-checksum & 0xFF) != vpd->checksum)
9715 return (0);
9716 return (1);
9717 }
9718
9719 int
9720 ahd_verify_cksum(struct seeprom_config *sc)
9721 {
9722 int i;
9723 int maxaddr;
9724 uint32_t checksum;
9725 uint16_t *scarray;
9726
9727 maxaddr = (sizeof(*sc)/2) - 1;
9728 checksum = 0;
9729 scarray = (uint16_t *)sc;
9730
9731 for (i = 0; i < maxaddr; i++)
9732 checksum = checksum + scarray[i];
9733 if (checksum == 0
9734 || (checksum & 0xFFFF) != sc->checksum) {
9735 return (0);
9736 } else {
9737 return (1);
9738 }
9739 }
9740
9741 int
9742 ahd_acquire_seeprom(struct ahd_softc *ahd)
9743 {
9744 /*
9745 * We should be able to determine the SEEPROM type
9746 * from the flexport logic, but unfortunately not
9747 * all implementations have this logic and there is
9748 * no programatic method for determining if the logic
9749 * is present.
9750 */
9751 return (1);
9752 #if 0
9753 uint8_t seetype;
9754 int error;
9755
9756 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9757 if (error != 0
9758 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9759 return (0);
9760 return (1);
9761 #endif
9762 }
9763
9764 void
9765 ahd_release_seeprom(struct ahd_softc *ahd)
9766 {
9767 /* Currently a no-op */
9768 }
9769
9770 int
9771 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9772 {
9773 int error;
9774
9775 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9776 if (addr > 7)
9777 panic("ahd_write_flexport: address out of range");
9778 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9779 error = ahd_wait_flexport(ahd);
9780 if (error != 0)
9781 return (error);
9782 ahd_outb(ahd, BRDDAT, value);
9783 ahd_flush_device_writes(ahd);
9784 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9785 ahd_flush_device_writes(ahd);
9786 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9787 ahd_flush_device_writes(ahd);
9788 ahd_outb(ahd, BRDCTL, 0);
9789 ahd_flush_device_writes(ahd);
9790 return (0);
9791 }
9792
9793 int
9794 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9795 {
9796 int error;
9797
9798 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9799 if (addr > 7)
9800 panic("ahd_read_flexport: address out of range");
9801 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9802 error = ahd_wait_flexport(ahd);
9803 if (error != 0)
9804 return (error);
9805 *value = ahd_inb(ahd, BRDDAT);
9806 ahd_outb(ahd, BRDCTL, 0);
9807 ahd_flush_device_writes(ahd);
9808 return (0);
9809 }
9810
9811 /*
9812 * Wait at most 2 seconds for flexport arbitration to succeed.
9813 */
9814 int
9815 ahd_wait_flexport(struct ahd_softc *ahd)
9816 {
9817 int cnt;
9818
9819 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9820 cnt = 1000000 * 2 / 5;
9821 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9822 aic_delay(5);
9823
9824 if (cnt == 0)
9825 return (ETIMEDOUT);
9826 return (0);
9827 }
9828
9829 /************************* Target Mode ****************************************/
9830 #ifdef AHD_TARGET_MODE
9831 cam_status
9832 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9833 struct ahd_tmode_tstate **tstate,
9834 struct ahd_tmode_lstate **lstate,
9835 int notfound_failure)
9836 {
9837
9838 if ((ahd->features & AHD_TARGETMODE) == 0)
9839 return (CAM_REQ_INVALID);
9840
9841 /*
9842 * Handle the 'black hole' device that sucks up
9843 * requests to unattached luns on enabled targets.
9844 */
9845 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9846 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9847 *tstate = NULL;
9848 *lstate = ahd->black_hole;
9849 } else {
9850 u_int max_id;
9851
9852 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9853 if (ccb->ccb_h.target_id > max_id)
9854 return (CAM_TID_INVALID);
9855
9856 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9857 return (CAM_LUN_INVALID);
9858
9859 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9860 *lstate = NULL;
9861 if (*tstate != NULL)
9862 *lstate =
9863 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9864 }
9865
9866 if (notfound_failure != 0 && *lstate == NULL)
9867 return (CAM_PATH_INVALID);
9868
9869 return (CAM_REQ_CMP);
9870 }
9871
9872 void
9873 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9874 {
9875 #if NOT_YET
9876 struct ahd_tmode_tstate *tstate;
9877 struct ahd_tmode_lstate *lstate;
9878 struct ccb_en_lun *cel;
9879 cam_status status;
9880 u_int target;
9881 u_int lun;
9882 u_int target_mask;
9883 u_long s;
9884 char channel;
9885
9886 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9887 /*notfound_failure*/FALSE);
9888
9889 if (status != CAM_REQ_CMP) {
9890 ccb->ccb_h.status = status;
9891 return;
9892 }
9893
9894 if ((ahd->features & AHD_MULTIROLE) != 0) {
9895 u_int our_id;
9896
9897 our_id = ahd->our_id;
9898 if (ccb->ccb_h.target_id != our_id) {
9899 if ((ahd->features & AHD_MULTI_TID) != 0
9900 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9901 /*
9902 * Only allow additional targets if
9903 * the initiator role is disabled.
9904 * The hardware cannot handle a re-select-in
9905 * on the initiator id during a re-select-out
9906 * on a different target id.
9907 */
9908 status = CAM_TID_INVALID;
9909 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9910 || ahd->enabled_luns > 0) {
9911 /*
9912 * Only allow our target id to change
9913 * if the initiator role is not configured
9914 * and there are no enabled luns which
9915 * are attached to the currently registered
9916 * scsi id.
9917 */
9918 status = CAM_TID_INVALID;
9919 }
9920 }
9921 }
9922
9923 if (status != CAM_REQ_CMP) {
9924 ccb->ccb_h.status = status;
9925 return;
9926 }
9927
9928 /*
9929 * We now have an id that is valid.
9930 * If we aren't in target mode, switch modes.
9931 */
9932 if ((ahd->flags & AHD_TARGETROLE) == 0
9933 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9934 u_long s;
9935
9936 printf("Configuring Target Mode\n");
9937 ahd_lock(ahd, &s);
9938 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9939 ccb->ccb_h.status = CAM_BUSY;
9940 ahd_unlock(ahd, &s);
9941 return;
9942 }
9943 ahd->flags |= AHD_TARGETROLE;
9944 if ((ahd->features & AHD_MULTIROLE) == 0)
9945 ahd->flags &= ~AHD_INITIATORROLE;
9946 ahd_pause(ahd);
9947 ahd_loadseq(ahd);
9948 ahd_restart(ahd);
9949 ahd_unlock(ahd, &s);
9950 }
9951 cel = &ccb->cel;
9952 target = ccb->ccb_h.target_id;
9953 lun = ccb->ccb_h.target_lun;
9954 channel = SIM_CHANNEL(ahd, sim);
9955 target_mask = 0x01 << target;
9956 if (channel == 'B')
9957 target_mask <<= 8;
9958
9959 if (cel->enable != 0) {
9960 u_int scsiseq1;
9961
9962 /* Are we already enabled?? */
9963 if (lstate != NULL) {
9964 xpt_print_path(ccb->ccb_h.path);
9965 printf("Lun already enabled\n");
9966 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9967 return;
9968 }
9969
9970 if (cel->grp6_len != 0
9971 || cel->grp7_len != 0) {
9972 /*
9973 * Don't (yet?) support vendor
9974 * specific commands.
9975 */
9976 ccb->ccb_h.status = CAM_REQ_INVALID;
9977 printf("Non-zero Group Codes\n");
9978 return;
9979 }
9980
9981 /*
9982 * Seems to be okay.
9983 * Setup our data structures.
9984 */
9985 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9986 tstate = ahd_alloc_tstate(ahd, target, channel);
9987 if (tstate == NULL) {
9988 xpt_print_path(ccb->ccb_h.path);
9989 printf("Couldn't allocate tstate\n");
9990 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9991 return;
9992 }
9993 }
9994 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
9995 if (lstate == NULL) {
9996 xpt_print_path(ccb->ccb_h.path);
9997 printf("Couldn't allocate lstate\n");
9998 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9999 return;
10000 }
10001 memset(lstate, 0, sizeof(*lstate));
10002 status = xpt_create_path(&lstate->path, /*periph*/NULL,
10003 xpt_path_path_id(ccb->ccb_h.path),
10004 xpt_path_target_id(ccb->ccb_h.path),
10005 xpt_path_lun_id(ccb->ccb_h.path));
10006 if (status != CAM_REQ_CMP) {
10007 free(lstate, M_DEVBUF);
10008 xpt_print_path(ccb->ccb_h.path);
10009 printf("Couldn't allocate path\n");
10010 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
10011 return;
10012 }
10013 SLIST_INIT(&lstate->accept_tios);
10014 SLIST_INIT(&lstate->immed_notifies);
10015 ahd_lock(ahd, &s);
10016 ahd_pause(ahd);
10017 if (target != CAM_TARGET_WILDCARD) {
10018 tstate->enabled_luns[lun] = lstate;
10019 ahd->enabled_luns++;
10020
10021 if ((ahd->features & AHD_MULTI_TID) != 0) {
10022 u_int targid_mask;
10023
10024 targid_mask = ahd_inw(ahd, TARGID);
10025 targid_mask |= target_mask;
10026 ahd_outw(ahd, TARGID, targid_mask);
10027 ahd_update_scsiid(ahd, targid_mask);
10028 } else {
10029 u_int our_id;
10030 char channel;
10031
10032 channel = SIM_CHANNEL(ahd, sim);
10033 our_id = SIM_SCSI_ID(ahd, sim);
10034
10035 /*
10036 * This can only happen if selections
10037 * are not enabled
10038 */
10039 if (target != our_id) {
10040 u_int sblkctl;
10041 char cur_channel;
10042 int swap;
10043
10044 sblkctl = ahd_inb(ahd, SBLKCTL);
10045 cur_channel = (sblkctl & SELBUSB)
10046 ? 'B' : 'A';
10047 if ((ahd->features & AHD_TWIN) == 0)
10048 cur_channel = 'A';
10049 swap = cur_channel != channel;
10050 ahd->our_id = target;
10051
10052 if (swap)
10053 ahd_outb(ahd, SBLKCTL,
10054 sblkctl ^ SELBUSB);
10055
10056 ahd_outb(ahd, SCSIID, target);
10057
10058 if (swap)
10059 ahd_outb(ahd, SBLKCTL, sblkctl);
10060 }
10061 }
10062 } else
10063 ahd->black_hole = lstate;
10064 /* Allow select-in operations */
10065 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
10066 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10067 scsiseq1 |= ENSELI;
10068 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10069 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10070 scsiseq1 |= ENSELI;
10071 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10072 }
10073 ahd_unpause(ahd);
10074 ahd_unlock(ahd, &s);
10075 ccb->ccb_h.status = CAM_REQ_CMP;
10076 xpt_print_path(ccb->ccb_h.path);
10077 printf("Lun now enabled for target mode\n");
10078 } else {
10079 struct scb *scb;
10080 int i, empty;
10081
10082 if (lstate == NULL) {
10083 ccb->ccb_h.status = CAM_LUN_INVALID;
10084 return;
10085 }
10086
10087 ahd_lock(ahd, &s);
10088
10089 ccb->ccb_h.status = CAM_REQ_CMP;
10090 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
10091 struct ccb_hdr *ccbh;
10092
10093 ccbh = &scb->io_ctx->ccb_h;
10094 if (ccbh->func_code == XPT_CONT_TARGET_IO
10095 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
10096 printf("CTIO pending\n");
10097 ccb->ccb_h.status = CAM_REQ_INVALID;
10098 ahd_unlock(ahd, &s);
10099 return;
10100 }
10101 }
10102
10103 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
10104 printf("ATIOs pending\n");
10105 ccb->ccb_h.status = CAM_REQ_INVALID;
10106 }
10107
10108 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
10109 printf("INOTs pending\n");
10110 ccb->ccb_h.status = CAM_REQ_INVALID;
10111 }
10112
10113 if (ccb->ccb_h.status != CAM_REQ_CMP) {
10114 ahd_unlock(ahd, &s);
10115 return;
10116 }
10117
10118 xpt_print_path(ccb->ccb_h.path);
10119 printf("Target mode disabled\n");
10120 xpt_free_path(lstate->path);
10121 free(lstate, M_DEVBUF);
10122
10123 ahd_pause(ahd);
10124 /* Can we clean up the target too? */
10125 if (target != CAM_TARGET_WILDCARD) {
10126 tstate->enabled_luns[lun] = NULL;
10127 ahd->enabled_luns--;
10128 for (empty = 1, i = 0; i < 8; i++)
10129 if (tstate->enabled_luns[i] != NULL) {
10130 empty = 0;
10131 break;
10132 }
10133
10134 if (empty) {
10135 ahd_free_tstate(ahd, target, channel,
10136 /*force*/FALSE);
10137 if (ahd->features & AHD_MULTI_TID) {
10138 u_int targid_mask;
10139
10140 targid_mask = ahd_inw(ahd, TARGID);
10141 targid_mask &= ~target_mask;
10142 ahd_outw(ahd, TARGID, targid_mask);
10143 ahd_update_scsiid(ahd, targid_mask);
10144 }
10145 }
10146 } else {
10147
10148 ahd->black_hole = NULL;
10149
10150 /*
10151 * We can't allow selections without
10152 * our black hole device.
10153 */
10154 empty = TRUE;
10155 }
10156 if (ahd->enabled_luns == 0) {
10157 /* Disallow select-in */
10158 u_int scsiseq1;
10159
10160 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10161 scsiseq1 &= ~ENSELI;
10162 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10163 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10164 scsiseq1 &= ~ENSELI;
10165 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10166
10167 if ((ahd->features & AHD_MULTIROLE) == 0) {
10168 printf("Configuring Initiator Mode\n");
10169 ahd->flags &= ~AHD_TARGETROLE;
10170 ahd->flags |= AHD_INITIATORROLE;
10171 ahd_pause(ahd);
10172 ahd_loadseq(ahd);
10173 ahd_restart(ahd);
10174 /*
10175 * Unpaused. The extra unpause
10176 * that follows is harmless.
10177 */
10178 }
10179 }
10180 ahd_unpause(ahd);
10181 ahd_unlock(ahd, &s);
10182 }
10183 #endif
10184 }
10185
10186 static void
10187 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
10188 {
10189 #if NOT_YET
10190 u_int scsiid_mask;
10191 u_int scsiid;
10192
10193 if ((ahd->features & AHD_MULTI_TID) == 0)
10194 panic("ahd_update_scsiid called on non-multitid unit\n");
10195
10196 /*
10197 * Since we will rely on the TARGID mask
10198 * for selection enables, ensure that OID
10199 * in SCSIID is not set to some other ID
10200 * that we don't want to allow selections on.
10201 */
10202 if ((ahd->features & AHD_ULTRA2) != 0)
10203 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
10204 else
10205 scsiid = ahd_inb(ahd, SCSIID);
10206 scsiid_mask = 0x1 << (scsiid & OID);
10207 if ((targid_mask & scsiid_mask) == 0) {
10208 u_int our_id;
10209
10210 /* ffs counts from 1 */
10211 our_id = ffs(targid_mask);
10212 if (our_id == 0)
10213 our_id = ahd->our_id;
10214 else
10215 our_id--;
10216 scsiid &= TID;
10217 scsiid |= our_id;
10218 }
10219 if ((ahd->features & AHD_ULTRA2) != 0)
10220 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
10221 else
10222 ahd_outb(ahd, SCSIID, scsiid);
10223 #endif
10224 }
10225
10226 void
10227 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
10228 {
10229 struct target_cmd *cmd;
10230
10231 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
10232 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
10233
10234 /*
10235 * Only advance through the queue if we
10236 * have the resources to process the command.
10237 */
10238 if (ahd_handle_target_cmd(ahd, cmd) != 0)
10239 break;
10240
10241 cmd->cmd_valid = 0;
10242 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
10243 ahd->shared_data_dmamap,
10244 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
10245 sizeof(struct target_cmd),
10246 BUS_DMASYNC_PREREAD);
10247 ahd->tqinfifonext++;
10248
10249 /*
10250 * Lazily update our position in the target mode incoming
10251 * command queue as seen by the sequencer.
10252 */
10253 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
10254 u_int hs_mailbox;
10255
10256 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
10257 hs_mailbox &= ~HOST_TQINPOS;
10258 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
10259 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
10260 }
10261 }
10262 }
10263
10264 static int
10265 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
10266 {
10267 struct ahd_tmode_tstate *tstate;
10268 struct ahd_tmode_lstate *lstate;
10269 struct ccb_accept_tio *atio;
10270 uint8_t *byte;
10271 int initiator;
10272 int target;
10273 int lun;
10274
10275 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
10276 target = SCSIID_OUR_ID(cmd->scsiid);
10277 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
10278
10279 byte = cmd->bytes;
10280 tstate = ahd->enabled_targets[target];
10281 lstate = NULL;
10282 if (tstate != NULL)
10283 lstate = tstate->enabled_luns[lun];
10284
10285 /*
10286 * Commands for disabled luns go to the black hole driver.
10287 */
10288 if (lstate == NULL)
10289 lstate = ahd->black_hole;
10290
10291 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
10292 if (atio == NULL) {
10293 ahd->flags |= AHD_TQINFIFO_BLOCKED;
10294 /*
10295 * Wait for more ATIOs from the peripheral driver for this lun.
10296 */
10297 return (1);
10298 } else
10299 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
10300 #ifdef AHD_DEBUG
10301 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10302 printf("Incoming command from %d for %d:%d%s\n",
10303 initiator, target, lun,
10304 lstate == ahd->black_hole ? "(Black Holed)" : "");
10305 #endif
10306 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
10307
10308 if (lstate == ahd->black_hole) {
10309 /* Fill in the wildcards */
10310 atio->ccb_h.target_id = target;
10311 atio->ccb_h.target_lun = lun;
10312 }
10313
10314 /*
10315 * Package it up and send it off to
10316 * whomever has this lun enabled.
10317 */
10318 atio->sense_len = 0;
10319 atio->init_id = initiator;
10320 if (byte[0] != 0xFF) {
10321 /* Tag was included */
10322 atio->tag_action = *byte++;
10323 atio->tag_id = *byte++;
10324 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
10325 } else {
10326 atio->ccb_h.flags = 0;
10327 }
10328 byte++;
10329
10330 /* Okay. Now determine the cdb size based on the command code */
10331 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
10332 case 0:
10333 atio->cdb_len = 6;
10334 break;
10335 case 1:
10336 case 2:
10337 atio->cdb_len = 10;
10338 break;
10339 case 4:
10340 atio->cdb_len = 16;
10341 break;
10342 case 5:
10343 atio->cdb_len = 12;
10344 break;
10345 case 3:
10346 default:
10347 /* Only copy the opcode. */
10348 atio->cdb_len = 1;
10349 printf("Reserved or VU command code type encountered\n");
10350 break;
10351 }
10352
10353 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
10354
10355 atio->ccb_h.status |= CAM_CDB_RECVD;
10356
10357 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
10358 /*
10359 * We weren't allowed to disconnect.
10360 * We're hanging on the bus until a
10361 * continue target I/O comes in response
10362 * to this accept tio.
10363 */
10364 #ifdef AHD_DEBUG
10365 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10366 printf("Received Immediate Command %d:%d:%d - %p\n",
10367 initiator, target, lun, ahd->pending_device);
10368 #endif
10369 ahd->pending_device = lstate;
10370 ahd_freeze_ccb((union ccb *)atio);
10371 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
10372 }
10373 xpt_done((union ccb*)atio);
10374 return (0);
10375 }
10376
10377 #endif
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