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sys/dev/aic7xxx/aic79xx_pci.c
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1 /*- 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 42 */ 43 44 #ifdef __linux__ 45 #include "aic79xx_osm.h" 46 #include "aic79xx_inline.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD: releng/11.2/sys/dev/aic7xxx/aic79xx_pci.c 331722 2018-03-29 02:50:57Z eadler $"); 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #endif 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 69 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 70 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 72 73 #define ID_AIC7901 0x800F9005FFFF9005ull 74 #define ID_AHA_29320A 0x8000900500609005ull 75 #define ID_AHA_29320ALP 0x8017900500449005ull 76 77 #define ID_AIC7901A 0x801E9005FFFF9005ull 78 #define ID_AHA_29320LP 0x8014900500449005ull 79 80 #define ID_AIC7902 0x801F9005FFFF9005ull 81 #define ID_AIC7902_B 0x801D9005FFFF9005ull 82 #define ID_AHA_39320 0x8010900500409005ull 83 #define ID_AHA_29320 0x8012900500429005ull 84 #define ID_AHA_29320B 0x8013900500439005ull 85 #define ID_AHA_39320_B 0x8015900500409005ull 86 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 87 #define ID_AHA_39320A 0x8016900500409005ull 88 #define ID_AHA_39320D 0x8011900500419005ull 89 #define ID_AHA_39320D_B 0x801C900500419005ull 90 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92 #define ID_AHA_39320LPE 0x8017900500459005ull 93 #define ID_AIC7902_PCI_REV_A4 0x3 94 #define ID_AIC7902_PCI_REV_B0 0x10 95 #define SUBID_HP 0x0E11 96 #define DEVICE8081 0x8081 97 #define DEVICE8088 0x8088 98 #define DEVICE8089 0x8089 99 #define ADAPTECVENDORID 0x9005 100 #define SUBVENDOR9005 0x9005 101 102 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103 104 #define DEVID_9005_TYPE(id) ((id) & 0xF) 105 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 106 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 107 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 108 109 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 110 111 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 112 113 #define SUBID_9005_TYPE(id) ((id) & 0xF) 114 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 115 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 116 117 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 118 119 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 120 121 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 122 #define SUBID_9005_SEEPTYPE_NONE 0x0 123 #define SUBID_9005_SEEPTYPE_4K 0x1 124 125 static ahd_device_setup_t ahd_aic7901_setup; 126 static ahd_device_setup_t ahd_aic7901A_setup; 127 static ahd_device_setup_t ahd_aic7902_setup; 128 static ahd_device_setup_t ahd_aic790X_setup; 129 130 struct ahd_pci_identity ahd_pci_ident_table [] = 131 { 132 /* aic7901 based controllers */ 133 { 134 ID_AHA_29320A, 135 ID_ALL_MASK, 136 "Adaptec 29320A Ultra320 SCSI adapter", 137 ahd_aic7901_setup 138 }, 139 { 140 ID_AHA_29320ALP, 141 ID_ALL_MASK, 142 "Adaptec 29320ALP Ultra320 SCSI adapter", 143 ahd_aic7901_setup 144 }, 145 /* aic7901A based controllers */ 146 { 147 ID_AHA_29320LP, 148 ID_ALL_MASK, 149 "Adaptec 29320LP Ultra320 SCSI adapter", 150 ahd_aic7901A_setup 151 }, 152 /* aic7902 based controllers */ 153 { 154 ID_AHA_29320, 155 ID_ALL_MASK, 156 "Adaptec 29320 Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_29320B, 161 ID_ALL_MASK, 162 "Adaptec 29320B Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320, 167 ID_ALL_MASK, 168 "Adaptec 39320 Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320_B, 173 ID_ALL_MASK, 174 "Adaptec 39320 Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320_B_DELL, 179 ID_ALL_MASK, 180 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320A, 185 ID_ALL_MASK, 186 "Adaptec 39320A Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320D, 191 ID_ALL_MASK, 192 "Adaptec 39320D Ultra320 SCSI adapter", 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320D_HP, 197 ID_ALL_MASK, 198 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 199 ahd_aic7902_setup 200 }, 201 { 202 ID_AHA_39320D_B, 203 ID_ALL_MASK, 204 "Adaptec 39320D Ultra320 SCSI adapter", 205 ahd_aic7902_setup 206 }, 207 { 208 ID_AHA_39320D_B_HP, 209 ID_ALL_MASK, 210 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 211 ahd_aic7902_setup 212 }, 213 { 214 ID_AHA_39320LPE, 215 ID_ALL_MASK, 216 "Adaptec 39320LPE Ultra320 SCSI adapter", 217 ahd_aic7902_setup 218 }, 219 /* Generic chip probes for devices we don't know 'exactly' */ 220 { 221 ID_AIC7901 & ID_9005_GENERIC_MASK, 222 ID_9005_GENERIC_MASK, 223 "Adaptec AIC7901 Ultra320 SCSI adapter", 224 ahd_aic7901_setup 225 }, 226 { 227 ID_AIC7901A & ID_DEV_VENDOR_MASK, 228 ID_DEV_VENDOR_MASK, 229 "Adaptec AIC7901A Ultra320 SCSI adapter", 230 ahd_aic7901A_setup 231 }, 232 { 233 ID_AIC7902 & ID_9005_GENERIC_MASK, 234 ID_9005_GENERIC_MASK, 235 "Adaptec AIC7902 Ultra320 SCSI adapter", 236 ahd_aic7902_setup 237 } 238 }; 239 240 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 241 242 #define DEVCONFIG 0x40 243 #define PCIXINITPAT 0x0000E000ul 244 #define PCIXINIT_PCI33_66 0x0000E000ul 245 #define PCIXINIT_PCIX50_66 0x0000C000ul 246 #define PCIXINIT_PCIX66_100 0x0000A000ul 247 #define PCIXINIT_PCIX100_133 0x00008000ul 248 #define PCI_BUS_MODES_INDEX(devconfig) \ 249 (((devconfig) & PCIXINITPAT) >> 13) 250 static const char *pci_bus_modes[] = 251 { 252 "PCI bus mode unknown", 253 "PCI bus mode unknown", 254 "PCI bus mode unknown", 255 "PCI bus mode unknown", 256 "PCI-X 101-133MHz", 257 "PCI-X 67-100MHz", 258 "PCI-X 50-66MHz", 259 "PCI 33 or 66MHz" 260 }; 261 262 #define TESTMODE 0x00000800ul 263 #define IRDY_RST 0x00000200ul 264 #define FRAME_RST 0x00000100ul 265 #define PCI64BIT 0x00000080ul 266 #define MRDCEN 0x00000040ul 267 #define ENDIANSEL 0x00000020ul 268 #define MIXQWENDIANEN 0x00000008ul 269 #define DACEN 0x00000004ul 270 #define STPWLEVEL 0x00000002ul 271 #define QWENDIANSEL 0x00000001ul 272 273 #define DEVCONFIG1 0x44 274 #define PREQDIS 0x01 275 276 #define CSIZE_LATTIME 0x0c 277 #define CACHESIZE 0x000000fful 278 #define LATTIME 0x0000ff00ul 279 280 static int ahd_check_extport(struct ahd_softc *ahd); 281 static void ahd_configure_termination(struct ahd_softc *ahd, 282 u_int adapter_control); 283 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 284 285 struct ahd_pci_identity * 286 ahd_find_pci_device(aic_dev_softc_t pci) 287 { 288 uint64_t full_id; 289 uint16_t device; 290 uint16_t vendor; 291 uint16_t subdevice; 292 uint16_t subvendor; 293 struct ahd_pci_identity *entry; 294 u_int i; 295 296 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 297 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 298 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 299 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 300 301 if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) { 302 if ((device == DEVICE8081) || (device == DEVICE8088) || 303 (device == DEVICE8089)) { 304 printf("Controller device ID conflict with PMC Adaptec HBA\n"); 305 return (NULL); 306 } 307 } 308 309 full_id = ahd_compose_id(device, 310 vendor, 311 subdevice, 312 subvendor); 313 314 /* 315 * If we are configured to attach to HostRAID 316 * controllers, mask out the IROC/HostRAID bit 317 * in the 318 */ 319 if (ahd_attach_to_HostRAID_controllers) 320 full_id &= ID_ALL_IROC_MASK; 321 322 for (i = 0; i < ahd_num_pci_devs; i++) { 323 entry = &ahd_pci_ident_table[i]; 324 if (entry->full_id == (full_id & entry->id_mask)) { 325 /* Honor exclusion entries. */ 326 if (entry->name == NULL) 327 return (NULL); 328 return (entry); 329 } 330 } 331 return (NULL); 332 } 333 334 int 335 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 336 { 337 u_int command; 338 uint32_t devconfig; 339 uint16_t device; 340 uint16_t subvendor; 341 int error; 342 343 ahd->description = entry->name; 344 /* 345 * Record if this is a HostRAID board. 346 */ 347 device = aic_pci_read_config(ahd->dev_softc, 348 PCIR_DEVICE, /*bytes*/2); 349 if (DEVID_9005_HOSTRAID(device)) 350 ahd->flags |= AHD_HOSTRAID_BOARD; 351 352 /* 353 * Record if this is an HP board. 354 */ 355 subvendor = aic_pci_read_config(ahd->dev_softc, 356 PCIR_SUBVEND_0, /*bytes*/2); 357 if (subvendor == SUBID_HP) 358 ahd->flags |= AHD_HP_BOARD; 359 360 error = entry->setup(ahd); 361 if (error != 0) 362 return (error); 363 364 /* 365 * Find the PCI-X cap pointer. If we don't find it, 366 * pcix_ptr will be 0. 367 */ 368 pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 369 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 370 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 371 ahd->chip |= AHD_PCI; 372 /* Disable PCIX workarounds when running in PCI mode. */ 373 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 374 } else { 375 ahd->chip |= AHD_PCIX; 376 if (ahd->pcix_ptr == 0) 377 return (ENXIO); 378 } 379 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 380 381 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 382 383 error = ahd_pci_map_registers(ahd); 384 if (error != 0) 385 return (error); 386 387 /* 388 * If we need to support high memory, enable dual 389 * address cycles. This bit must be set to enable 390 * high address bit generation even if we are on a 391 * 64bit bus (PCI64BIT set in devconfig). 392 */ 393 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 394 uint32_t devconfig; 395 396 if (bootverbose) 397 printf("%s: Enabling 39Bit Addressing\n", 398 ahd_name(ahd)); 399 devconfig = aic_pci_read_config(ahd->dev_softc, 400 DEVCONFIG, /*bytes*/4); 401 devconfig |= DACEN; 402 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 403 devconfig, /*bytes*/4); 404 } 405 406 /* Ensure busmastering is enabled */ 407 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 408 command |= PCIM_CMD_BUSMASTEREN; 409 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 410 411 error = ahd_softc_init(ahd); 412 if (error != 0) 413 return (error); 414 415 ahd->bus_intr = ahd_pci_intr; 416 417 error = ahd_reset(ahd, /*reinit*/FALSE); 418 if (error != 0) 419 return (ENXIO); 420 421 ahd->pci_cachesize = 422 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 423 /*bytes*/1) & CACHESIZE; 424 ahd->pci_cachesize *= 4; 425 426 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 427 /* See if we have a SEEPROM and perform auto-term */ 428 error = ahd_check_extport(ahd); 429 if (error != 0) 430 return (error); 431 432 /* Core initialization */ 433 error = ahd_init(ahd); 434 if (error != 0) 435 return (error); 436 437 /* 438 * Allow interrupts now that we are completely setup. 439 */ 440 error = ahd_pci_map_int(ahd); 441 if (error != 0) 442 return (error); 443 444 ahd_lock(ahd); 445 /* 446 * Link this softc in with all other ahd instances. 447 */ 448 ahd_softc_insert(ahd); 449 ahd_unlock(ahd); 450 return (0); 451 } 452 453 /* 454 * Perform some simple tests that should catch situations where 455 * our registers are invalidly mapped. 456 */ 457 int 458 ahd_pci_test_register_access(struct ahd_softc *ahd) 459 { 460 uint32_t cmd; 461 u_int targpcistat; 462 u_int pci_status1; 463 int error; 464 uint8_t hcntrl; 465 466 error = EIO; 467 468 /* 469 * Enable PCI error interrupt status, but suppress NMIs 470 * generated by SERR raised due to target aborts. 471 */ 472 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 473 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 474 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 475 476 /* 477 * First a simple test to see if any 478 * registers can be read. Reading 479 * HCNTRL has no side effects and has 480 * at least one bit that is guaranteed to 481 * be zero so it is a good register to 482 * use for this test. 483 */ 484 hcntrl = ahd_inb(ahd, HCNTRL); 485 if (hcntrl == 0xFF) 486 goto fail; 487 488 /* 489 * Next create a situation where write combining 490 * or read prefetching could be initiated by the 491 * CPU or host bridge. Our device does not support 492 * either, so look for data corruption and/or flagged 493 * PCI errors. First pause without causing another 494 * chip reset. 495 */ 496 hcntrl &= ~CHIPRST; 497 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 498 while (ahd_is_paused(ahd) == 0) 499 ; 500 501 /* Clear any PCI errors that occurred before our driver attached. */ 502 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 503 targpcistat = ahd_inb(ahd, TARGPCISTAT); 504 ahd_outb(ahd, TARGPCISTAT, targpcistat); 505 pci_status1 = aic_pci_read_config(ahd->dev_softc, 506 PCIR_STATUS + 1, /*bytes*/1); 507 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 508 pci_status1, /*bytes*/1); 509 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 510 ahd_outb(ahd, CLRINT, CLRPCIINT); 511 512 ahd_outb(ahd, SEQCTL0, PERRORDIS); 513 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 514 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 515 goto fail; 516 517 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 518 u_int targpcistat; 519 520 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 521 targpcistat = ahd_inb(ahd, TARGPCISTAT); 522 if ((targpcistat & STA) != 0) 523 goto fail; 524 } 525 526 error = 0; 527 528 fail: 529 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 530 531 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 532 targpcistat = ahd_inb(ahd, TARGPCISTAT); 533 534 /* Silently clear any latched errors. */ 535 ahd_outb(ahd, TARGPCISTAT, targpcistat); 536 pci_status1 = aic_pci_read_config(ahd->dev_softc, 537 PCIR_STATUS + 1, /*bytes*/1); 538 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 539 pci_status1, /*bytes*/1); 540 ahd_outb(ahd, CLRINT, CLRPCIINT); 541 } 542 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 543 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 544 return (error); 545 } 546 547 /* 548 * Check the external port logic for a serial eeprom 549 * and termination/cable detection contrls. 550 */ 551 static int 552 ahd_check_extport(struct ahd_softc *ahd) 553 { 554 struct vpd_config vpd; 555 struct seeprom_config *sc; 556 u_int adapter_control; 557 int have_seeprom; 558 int error; 559 560 sc = ahd->seep_config; 561 have_seeprom = ahd_acquire_seeprom(ahd); 562 if (have_seeprom) { 563 u_int start_addr; 564 565 /* 566 * Fetch VPD for this function and parse it. 567 */ 568 if (bootverbose) 569 printf("%s: Reading VPD from SEEPROM...", 570 ahd_name(ahd)); 571 572 /* Address is always in units of 16bit words */ 573 start_addr = ((2 * sizeof(*sc)) 574 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 575 576 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 577 start_addr, sizeof(vpd)/2, 578 /*bytestream*/TRUE); 579 if (error == 0) 580 error = ahd_parse_vpddata(ahd, &vpd); 581 if (bootverbose) 582 printf("%s: VPD parsing %s\n", 583 ahd_name(ahd), 584 error == 0 ? "successful" : "failed"); 585 586 if (bootverbose) 587 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 588 589 /* Address is always in units of 16bit words */ 590 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 591 592 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 593 start_addr, sizeof(*sc)/2, 594 /*bytestream*/FALSE); 595 596 if (error != 0) { 597 printf("Unable to read SEEPROM\n"); 598 have_seeprom = 0; 599 } else { 600 have_seeprom = ahd_verify_cksum(sc); 601 602 if (bootverbose) { 603 if (have_seeprom == 0) 604 printf ("checksum error\n"); 605 else 606 printf ("done.\n"); 607 } 608 } 609 ahd_release_seeprom(ahd); 610 } 611 612 if (!have_seeprom) { 613 u_int nvram_scb; 614 615 /* 616 * Pull scratch ram settings and treat them as 617 * if they are the contents of an seeprom if 618 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 619 * in SCB 0xFF. We manually compose the data as 16bit 620 * values to avoid endian issues. 621 */ 622 ahd_set_scbptr(ahd, 0xFF); 623 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 624 if (nvram_scb != 0xFF 625 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 626 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 627 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 628 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 629 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 630 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 631 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 632 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 633 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 634 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 635 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 636 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 637 uint16_t *sc_data; 638 int i; 639 640 ahd_set_scbptr(ahd, nvram_scb); 641 sc_data = (uint16_t *)sc; 642 for (i = 0; i < 64; i += 2) 643 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 644 have_seeprom = ahd_verify_cksum(sc); 645 if (have_seeprom) 646 ahd->flags |= AHD_SCB_CONFIG_USED; 647 } 648 } 649 650 #ifdef AHD_DEBUG 651 if (have_seeprom != 0 652 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 653 uint16_t *sc_data; 654 int i; 655 656 printf("%s: Seeprom Contents:", ahd_name(ahd)); 657 sc_data = (uint16_t *)sc; 658 for (i = 0; i < (sizeof(*sc)); i += 2) 659 printf("\n\t0x%.4x", sc_data[i]); 660 printf("\n"); 661 } 662 #endif 663 664 if (!have_seeprom) { 665 if (bootverbose) 666 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 667 ahd->flags |= AHD_USEDEFAULTS; 668 error = ahd_default_config(ahd); 669 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 670 free(ahd->seep_config, M_DEVBUF); 671 ahd->seep_config = NULL; 672 } else { 673 error = ahd_parse_cfgdata(ahd, sc); 674 adapter_control = sc->adapter_control; 675 } 676 if (error != 0) 677 return (error); 678 679 ahd_configure_termination(ahd, adapter_control); 680 681 return (0); 682 } 683 684 static void 685 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 686 { 687 int error; 688 u_int sxfrctl1; 689 uint8_t termctl; 690 uint32_t devconfig; 691 692 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 693 devconfig &= ~STPWLEVEL; 694 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 695 devconfig |= STPWLEVEL; 696 if (bootverbose) 697 printf("%s: STPWLEVEL is %s\n", 698 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 699 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 700 701 /* Make sure current sensing is off. */ 702 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 703 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 704 } 705 706 /* 707 * Read to sense. Write to set. 708 */ 709 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 710 if ((adapter_control & CFAUTOTERM) == 0) { 711 if (bootverbose) 712 printf("%s: Manual Primary Termination\n", 713 ahd_name(ahd)); 714 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 715 if ((adapter_control & CFSTERM) != 0) 716 termctl |= FLX_TERMCTL_ENPRILOW; 717 if ((adapter_control & CFWSTERM) != 0) 718 termctl |= FLX_TERMCTL_ENPRIHIGH; 719 } else if (error != 0) { 720 printf("%s: Primary Auto-Term Sensing failed! " 721 "Using Defaults.\n", ahd_name(ahd)); 722 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 723 } 724 725 if ((adapter_control & CFSEAUTOTERM) == 0) { 726 if (bootverbose) 727 printf("%s: Manual Secondary Termination\n", 728 ahd_name(ahd)); 729 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 730 if ((adapter_control & CFSELOWTERM) != 0) 731 termctl |= FLX_TERMCTL_ENSECLOW; 732 if ((adapter_control & CFSEHIGHTERM) != 0) 733 termctl |= FLX_TERMCTL_ENSECHIGH; 734 } else if (error != 0) { 735 printf("%s: Secondary Auto-Term Sensing failed! " 736 "Using Defaults.\n", ahd_name(ahd)); 737 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 738 } 739 740 /* 741 * Now set the termination based on what we found. 742 */ 743 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 744 ahd->flags &= ~AHD_TERM_ENB_A; 745 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 746 ahd->flags |= AHD_TERM_ENB_A; 747 sxfrctl1 |= STPWEN; 748 } 749 /* Must set the latch once in order to be effective. */ 750 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 751 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 752 753 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 754 if (error != 0) { 755 printf("%s: Unable to set termination settings!\n", 756 ahd_name(ahd)); 757 } else if (bootverbose) { 758 printf("%s: Primary High byte termination %sabled\n", 759 ahd_name(ahd), 760 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 761 762 printf("%s: Primary Low byte termination %sabled\n", 763 ahd_name(ahd), 764 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 765 766 printf("%s: Secondary High byte termination %sabled\n", 767 ahd_name(ahd), 768 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 769 770 printf("%s: Secondary Low byte termination %sabled\n", 771 ahd_name(ahd), 772 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 773 } 774 return; 775 } 776 777 #define DPE 0x80 778 #define SSE 0x40 779 #define RMA 0x20 780 #define RTA 0x10 781 #define STA 0x08 782 #define DPR 0x01 783 784 static const char *split_status_source[] = 785 { 786 "DFF0", 787 "DFF1", 788 "OVLY", 789 "CMC", 790 }; 791 792 static const char *pci_status_source[] = 793 { 794 "DFF0", 795 "DFF1", 796 "SG", 797 "CMC", 798 "OVLY", 799 "NONE", 800 "MSI", 801 "TARG" 802 }; 803 804 static const char *split_status_strings[] = 805 { 806 "%s: Received split response in %s.\n", 807 "%s: Received split completion error message in %s\n", 808 "%s: Receive overrun in %s\n", 809 "%s: Count not complete in %s\n", 810 "%s: Split completion data bucket in %s\n", 811 "%s: Split completion address error in %s\n", 812 "%s: Split completion byte count error in %s\n", 813 "%s: Signaled Target-abort to early terminate a split in %s\n" 814 }; 815 816 static const char *pci_status_strings[] = 817 { 818 "%s: Data Parity Error has been reported via PERR# in %s\n", 819 "%s: Target initial wait state error in %s\n", 820 "%s: Split completion read data parity error in %s\n", 821 "%s: Split completion address attribute parity error in %s\n", 822 "%s: Received a Target Abort in %s\n", 823 "%s: Received a Master Abort in %s\n", 824 "%s: Signal System Error Detected in %s\n", 825 "%s: Address or Write Phase Parity Error Detected in %s.\n" 826 }; 827 828 void 829 ahd_pci_intr(struct ahd_softc *ahd) 830 { 831 uint8_t pci_status[8]; 832 ahd_mode_state saved_modes; 833 u_int pci_status1; 834 u_int intstat; 835 u_int i; 836 u_int reg; 837 838 intstat = ahd_inb(ahd, INTSTAT); 839 840 if ((intstat & SPLTINT) != 0) 841 ahd_pci_split_intr(ahd, intstat); 842 843 if ((intstat & PCIINT) == 0) 844 return; 845 846 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 847 saved_modes = ahd_save_modes(ahd); 848 ahd_dump_card_state(ahd); 849 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 850 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 851 852 if (i == 5) 853 continue; 854 pci_status[i] = ahd_inb(ahd, reg); 855 /* Clear latched errors. So our interrupt deasserts. */ 856 ahd_outb(ahd, reg, pci_status[i]); 857 } 858 859 for (i = 0; i < 8; i++) { 860 u_int bit; 861 862 if (i == 5) 863 continue; 864 865 for (bit = 0; bit < 8; bit++) { 866 867 if ((pci_status[i] & (0x1 << bit)) != 0) { 868 static const char *s; 869 870 s = pci_status_strings[bit]; 871 if (i == 7/*TARG*/ && bit == 3) 872 s = "%s: Signaled Target Abort\n"; 873 printf(s, ahd_name(ahd), pci_status_source[i]); 874 } 875 } 876 } 877 pci_status1 = aic_pci_read_config(ahd->dev_softc, 878 PCIR_STATUS + 1, /*bytes*/1); 879 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 880 pci_status1, /*bytes*/1); 881 ahd_restore_modes(ahd, saved_modes); 882 ahd_outb(ahd, CLRINT, CLRPCIINT); 883 ahd_unpause(ahd); 884 } 885 886 static void 887 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 888 { 889 uint8_t split_status[4]; 890 uint8_t split_status1[4]; 891 uint8_t sg_split_status[2]; 892 uint8_t sg_split_status1[2]; 893 ahd_mode_state saved_modes; 894 u_int i; 895 uint32_t pcix_status; 896 897 /* 898 * Check for splits in all modes. Modes 0 and 1 899 * additionally have SG engine splits to look at. 900 */ 901 pcix_status = aic_pci_read_config(ahd->dev_softc, 902 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 903 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 904 ahd_name(ahd), pcix_status >> 16); 905 saved_modes = ahd_save_modes(ahd); 906 for (i = 0; i < 4; i++) { 907 ahd_set_modes(ahd, i, i); 908 909 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 910 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 911 /* Clear latched errors. So our interrupt deasserts. */ 912 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 913 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 914 if (i > 1) 915 continue; 916 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 917 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 918 /* Clear latched errors. So our interrupt deasserts. */ 919 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 920 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 921 } 922 923 for (i = 0; i < 4; i++) { 924 u_int bit; 925 926 for (bit = 0; bit < 8; bit++) { 927 928 if ((split_status[i] & (0x1 << bit)) != 0) { 929 static const char *s; 930 931 s = split_status_strings[bit]; 932 printf(s, ahd_name(ahd), 933 split_status_source[i]); 934 } 935 936 if (i > 1) 937 continue; 938 939 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 940 static const char *s; 941 942 s = split_status_strings[bit]; 943 printf(s, ahd_name(ahd), "SG"); 944 } 945 } 946 } 947 /* 948 * Clear PCI-X status bits. 949 */ 950 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 951 pcix_status, /*bytes*/4); 952 ahd_outb(ahd, CLRINT, CLRSPLTINT); 953 ahd_restore_modes(ahd, saved_modes); 954 } 955 956 static int 957 ahd_aic7901_setup(struct ahd_softc *ahd) 958 { 959 960 ahd->chip = AHD_AIC7901; 961 ahd->features = AHD_AIC7901_FE; 962 return (ahd_aic790X_setup(ahd)); 963 } 964 965 static int 966 ahd_aic7901A_setup(struct ahd_softc *ahd) 967 { 968 969 ahd->chip = AHD_AIC7901A; 970 ahd->features = AHD_AIC7901A_FE; 971 return (ahd_aic790X_setup(ahd)); 972 } 973 974 static int 975 ahd_aic7902_setup(struct ahd_softc *ahd) 976 { 977 ahd->chip = AHD_AIC7902; 978 ahd->features = AHD_AIC7902_FE; 979 return (ahd_aic790X_setup(ahd)); 980 } 981 982 static int 983 ahd_aic790X_setup(struct ahd_softc *ahd) 984 { 985 aic_dev_softc_t pci; 986 u_int rev; 987 988 pci = ahd->dev_softc; 989 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 990 if (rev < ID_AIC7902_PCI_REV_A4) { 991 printf("%s: Unable to attach to unsupported chip revision %d\n", 992 ahd_name(ahd), rev); 993 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 994 return (ENXIO); 995 } 996 ahd->channel = aic_get_pci_function(pci) + 'A'; 997 if (rev < ID_AIC7902_PCI_REV_B0) { 998 /* 999 * Enable A series workarounds. 1000 */ 1001 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1002 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1003 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1004 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1005 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1006 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1007 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1008 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1009 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1010 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1011 | AHD_FAINT_LED_BUG; 1012 1013 /* 1014 * IO Cell parameter setup. 1015 */ 1016 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1017 1018 if ((ahd->flags & AHD_HP_BOARD) == 0) 1019 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1020 } else { 1021 u_int devconfig1; 1022 1023 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1024 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1025 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1026 1027 /* 1028 * Some issues have been resolved in the 7901B. 1029 */ 1030 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1031 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1032 | AHD_BUSFREEREV_BUG; 1033 1034 /* 1035 * IO Cell parameter setup. 1036 */ 1037 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1038 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1039 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1040 1041 /* 1042 * Set the PREQDIS bit for H2B which disables some workaround 1043 * that doesn't work on regular PCI busses. 1044 * XXX - Find out exactly what this does from the hardware 1045 * folks! 1046 */ 1047 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1048 aic_pci_write_config(pci, DEVCONFIG1, 1049 devconfig1|PREQDIS, /*bytes*/1); 1050 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1051 } 1052 1053 return (0); 1054 }
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