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sys/dev/aic7xxx/aic79xx_pci.c
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1 /*- 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 42 */ 43 44 #ifdef __linux__ 45 #include "aic79xx_osm.h" 46 #include "aic79xx_inline.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD: releng/8.1/sys/dev/aic7xxx/aic79xx_pci.c 203515 2010-02-05 08:52:51Z gavin $"); 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #endif 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 69 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 70 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 72 73 #define ID_AIC7901 0x800F9005FFFF9005ull 74 #define ID_AHA_29320A 0x8000900500609005ull 75 #define ID_AHA_29320ALP 0x8017900500449005ull 76 77 #define ID_AIC7901A 0x801E9005FFFF9005ull 78 #define ID_AHA_29320LP 0x8014900500449005ull 79 80 #define ID_AIC7902 0x801F9005FFFF9005ull 81 #define ID_AIC7902_B 0x801D9005FFFF9005ull 82 #define ID_AHA_39320 0x8010900500409005ull 83 #define ID_AHA_29320 0x8012900500429005ull 84 #define ID_AHA_29320B 0x8013900500439005ull 85 #define ID_AHA_39320_B 0x8015900500409005ull 86 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 87 #define ID_AHA_39320A 0x8016900500409005ull 88 #define ID_AHA_39320D 0x8011900500419005ull 89 #define ID_AHA_39320D_B 0x801C900500419005ull 90 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92 #define ID_AHA_39320LPE 0x8017900500459005ull 93 #define ID_AIC7902_PCI_REV_A4 0x3 94 #define ID_AIC7902_PCI_REV_B0 0x10 95 #define SUBID_HP 0x0E11 96 97 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 98 99 #define DEVID_9005_TYPE(id) ((id) & 0xF) 100 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 101 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 102 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 103 104 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 105 106 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 107 108 #define SUBID_9005_TYPE(id) ((id) & 0xF) 109 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 110 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 111 112 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 113 114 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 115 116 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 117 #define SUBID_9005_SEEPTYPE_NONE 0x0 118 #define SUBID_9005_SEEPTYPE_4K 0x1 119 120 static ahd_device_setup_t ahd_aic7901_setup; 121 static ahd_device_setup_t ahd_aic7901A_setup; 122 static ahd_device_setup_t ahd_aic7902_setup; 123 static ahd_device_setup_t ahd_aic790X_setup; 124 125 struct ahd_pci_identity ahd_pci_ident_table [] = 126 { 127 /* aic7901 based controllers */ 128 { 129 ID_AHA_29320A, 130 ID_ALL_MASK, 131 "Adaptec 29320A Ultra320 SCSI adapter", 132 ahd_aic7901_setup 133 }, 134 { 135 ID_AHA_29320ALP, 136 ID_ALL_MASK, 137 "Adaptec 29320ALP Ultra320 SCSI adapter", 138 ahd_aic7901_setup 139 }, 140 /* aic7901A based controllers */ 141 { 142 ID_AHA_29320LP, 143 ID_ALL_MASK, 144 "Adaptec 29320LP Ultra320 SCSI adapter", 145 ahd_aic7901A_setup 146 }, 147 /* aic7902 based controllers */ 148 { 149 ID_AHA_29320, 150 ID_ALL_MASK, 151 "Adaptec 29320 Ultra320 SCSI adapter", 152 ahd_aic7902_setup 153 }, 154 { 155 ID_AHA_29320B, 156 ID_ALL_MASK, 157 "Adaptec 29320B Ultra320 SCSI adapter", 158 ahd_aic7902_setup 159 }, 160 { 161 ID_AHA_39320, 162 ID_ALL_MASK, 163 "Adaptec 39320 Ultra320 SCSI adapter", 164 ahd_aic7902_setup 165 }, 166 { 167 ID_AHA_39320_B, 168 ID_ALL_MASK, 169 "Adaptec 39320 Ultra320 SCSI adapter", 170 ahd_aic7902_setup 171 }, 172 { 173 ID_AHA_39320_B_DELL, 174 ID_ALL_MASK, 175 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 176 ahd_aic7902_setup 177 }, 178 { 179 ID_AHA_39320A, 180 ID_ALL_MASK, 181 "Adaptec 39320A Ultra320 SCSI adapter", 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320D, 186 ID_ALL_MASK, 187 "Adaptec 39320D Ultra320 SCSI adapter", 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320D_HP, 192 ID_ALL_MASK, 193 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 }, 196 { 197 ID_AHA_39320D_B, 198 ID_ALL_MASK, 199 "Adaptec 39320D Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 }, 202 { 203 ID_AHA_39320D_B_HP, 204 ID_ALL_MASK, 205 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 206 ahd_aic7902_setup 207 }, 208 { 209 ID_AHA_39320LPE, 210 ID_ALL_MASK, 211 "Adaptec 39320LPE Ultra320 SCSI adapter", 212 ahd_aic7902_setup 213 }, 214 /* Generic chip probes for devices we don't know 'exactly' */ 215 { 216 ID_AIC7901 & ID_9005_GENERIC_MASK, 217 ID_9005_GENERIC_MASK, 218 "Adaptec AIC7901 Ultra320 SCSI adapter", 219 ahd_aic7901_setup 220 }, 221 { 222 ID_AIC7901A & ID_DEV_VENDOR_MASK, 223 ID_DEV_VENDOR_MASK, 224 "Adaptec AIC7901A Ultra320 SCSI adapter", 225 ahd_aic7901A_setup 226 }, 227 { 228 ID_AIC7902 & ID_9005_GENERIC_MASK, 229 ID_9005_GENERIC_MASK, 230 "Adaptec AIC7902 Ultra320 SCSI adapter", 231 ahd_aic7902_setup 232 } 233 }; 234 235 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 236 237 #define DEVCONFIG 0x40 238 #define PCIXINITPAT 0x0000E000ul 239 #define PCIXINIT_PCI33_66 0x0000E000ul 240 #define PCIXINIT_PCIX50_66 0x0000C000ul 241 #define PCIXINIT_PCIX66_100 0x0000A000ul 242 #define PCIXINIT_PCIX100_133 0x00008000ul 243 #define PCI_BUS_MODES_INDEX(devconfig) \ 244 (((devconfig) & PCIXINITPAT) >> 13) 245 static const char *pci_bus_modes[] = 246 { 247 "PCI bus mode unknown", 248 "PCI bus mode unknown", 249 "PCI bus mode unknown", 250 "PCI bus mode unknown", 251 "PCI-X 101-133MHz", 252 "PCI-X 67-100MHz", 253 "PCI-X 50-66MHz", 254 "PCI 33 or 66MHz" 255 }; 256 257 #define TESTMODE 0x00000800ul 258 #define IRDY_RST 0x00000200ul 259 #define FRAME_RST 0x00000100ul 260 #define PCI64BIT 0x00000080ul 261 #define MRDCEN 0x00000040ul 262 #define ENDIANSEL 0x00000020ul 263 #define MIXQWENDIANEN 0x00000008ul 264 #define DACEN 0x00000004ul 265 #define STPWLEVEL 0x00000002ul 266 #define QWENDIANSEL 0x00000001ul 267 268 #define DEVCONFIG1 0x44 269 #define PREQDIS 0x01 270 271 #define CSIZE_LATTIME 0x0c 272 #define CACHESIZE 0x000000fful 273 #define LATTIME 0x0000ff00ul 274 275 static int ahd_check_extport(struct ahd_softc *ahd); 276 static void ahd_configure_termination(struct ahd_softc *ahd, 277 u_int adapter_control); 278 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 279 280 struct ahd_pci_identity * 281 ahd_find_pci_device(aic_dev_softc_t pci) 282 { 283 uint64_t full_id; 284 uint16_t device; 285 uint16_t vendor; 286 uint16_t subdevice; 287 uint16_t subvendor; 288 struct ahd_pci_identity *entry; 289 u_int i; 290 291 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 292 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 293 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 294 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 295 full_id = ahd_compose_id(device, 296 vendor, 297 subdevice, 298 subvendor); 299 300 /* 301 * If we are configured to attach to HostRAID 302 * controllers, mask out the IROC/HostRAID bit 303 * in the 304 */ 305 if (ahd_attach_to_HostRAID_controllers) 306 full_id &= ID_ALL_IROC_MASK; 307 308 for (i = 0; i < ahd_num_pci_devs; i++) { 309 entry = &ahd_pci_ident_table[i]; 310 if (entry->full_id == (full_id & entry->id_mask)) { 311 /* Honor exclusion entries. */ 312 if (entry->name == NULL) 313 return (NULL); 314 return (entry); 315 } 316 } 317 return (NULL); 318 } 319 320 int 321 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 322 { 323 struct scb_data *shared_scb_data; 324 u_int command; 325 uint32_t devconfig; 326 uint16_t device; 327 uint16_t subvendor; 328 int error; 329 330 shared_scb_data = NULL; 331 ahd->description = entry->name; 332 /* 333 * Record if this is a HostRAID board. 334 */ 335 device = aic_pci_read_config(ahd->dev_softc, 336 PCIR_DEVICE, /*bytes*/2); 337 if (DEVID_9005_HOSTRAID(device)) 338 ahd->flags |= AHD_HOSTRAID_BOARD; 339 340 /* 341 * Record if this is an HP board. 342 */ 343 subvendor = aic_pci_read_config(ahd->dev_softc, 344 PCIR_SUBVEND_0, /*bytes*/2); 345 if (subvendor == SUBID_HP) 346 ahd->flags |= AHD_HP_BOARD; 347 348 error = entry->setup(ahd); 349 if (error != 0) 350 return (error); 351 352 /* 353 * Find the PCI-X cap pointer. If we don't find it, 354 * pcix_ptr will be 0. 355 */ 356 pci_find_extcap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 357 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 358 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 359 ahd->chip |= AHD_PCI; 360 /* Disable PCIX workarounds when running in PCI mode. */ 361 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 362 } else { 363 ahd->chip |= AHD_PCIX; 364 if (ahd->pcix_ptr == 0) 365 return (ENXIO); 366 } 367 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 368 369 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 370 371 error = ahd_pci_map_registers(ahd); 372 if (error != 0) 373 return (error); 374 375 /* 376 * If we need to support high memory, enable dual 377 * address cycles. This bit must be set to enable 378 * high address bit generation even if we are on a 379 * 64bit bus (PCI64BIT set in devconfig). 380 */ 381 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 382 uint32_t devconfig; 383 384 if (bootverbose) 385 printf("%s: Enabling 39Bit Addressing\n", 386 ahd_name(ahd)); 387 devconfig = aic_pci_read_config(ahd->dev_softc, 388 DEVCONFIG, /*bytes*/4); 389 devconfig |= DACEN; 390 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 391 devconfig, /*bytes*/4); 392 } 393 394 /* Ensure busmastering is enabled */ 395 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 396 command |= PCIM_CMD_BUSMASTEREN; 397 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 398 399 error = ahd_softc_init(ahd); 400 if (error != 0) 401 return (error); 402 403 ahd->bus_intr = ahd_pci_intr; 404 405 error = ahd_reset(ahd, /*reinit*/FALSE); 406 if (error != 0) 407 return (ENXIO); 408 409 ahd->pci_cachesize = 410 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 411 /*bytes*/1) & CACHESIZE; 412 ahd->pci_cachesize *= 4; 413 414 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 415 /* See if we have a SEEPROM and perform auto-term */ 416 error = ahd_check_extport(ahd); 417 if (error != 0) 418 return (error); 419 420 /* Core initialization */ 421 error = ahd_init(ahd); 422 if (error != 0) 423 return (error); 424 425 /* 426 * Allow interrupts now that we are completely setup. 427 */ 428 error = ahd_pci_map_int(ahd); 429 if (error != 0) 430 return (error); 431 432 ahd_lock(ahd); 433 /* 434 * Link this softc in with all other ahd instances. 435 */ 436 ahd_softc_insert(ahd); 437 ahd_unlock(ahd); 438 return (0); 439 } 440 441 /* 442 * Perform some simple tests that should catch situations where 443 * our registers are invalidly mapped. 444 */ 445 int 446 ahd_pci_test_register_access(struct ahd_softc *ahd) 447 { 448 uint32_t cmd; 449 u_int targpcistat; 450 u_int pci_status1; 451 int error; 452 uint8_t hcntrl; 453 454 error = EIO; 455 456 /* 457 * Enable PCI error interrupt status, but suppress NMIs 458 * generated by SERR raised due to target aborts. 459 */ 460 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 461 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 462 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 463 464 /* 465 * First a simple test to see if any 466 * registers can be read. Reading 467 * HCNTRL has no side effects and has 468 * at least one bit that is guaranteed to 469 * be zero so it is a good register to 470 * use for this test. 471 */ 472 hcntrl = ahd_inb(ahd, HCNTRL); 473 if (hcntrl == 0xFF) 474 goto fail; 475 476 /* 477 * Next create a situation where write combining 478 * or read prefetching could be initiated by the 479 * CPU or host bridge. Our device does not support 480 * either, so look for data corruption and/or flaged 481 * PCI errors. First pause without causing another 482 * chip reset. 483 */ 484 hcntrl &= ~CHIPRST; 485 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 486 while (ahd_is_paused(ahd) == 0) 487 ; 488 489 /* Clear any PCI errors that occurred before our driver attached. */ 490 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 491 targpcistat = ahd_inb(ahd, TARGPCISTAT); 492 ahd_outb(ahd, TARGPCISTAT, targpcistat); 493 pci_status1 = aic_pci_read_config(ahd->dev_softc, 494 PCIR_STATUS + 1, /*bytes*/1); 495 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 496 pci_status1, /*bytes*/1); 497 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 498 ahd_outb(ahd, CLRINT, CLRPCIINT); 499 500 ahd_outb(ahd, SEQCTL0, PERRORDIS); 501 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 502 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 503 goto fail; 504 505 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 506 u_int targpcistat; 507 508 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 509 targpcistat = ahd_inb(ahd, TARGPCISTAT); 510 if ((targpcistat & STA) != 0) 511 goto fail; 512 } 513 514 error = 0; 515 516 fail: 517 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 518 519 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 520 targpcistat = ahd_inb(ahd, TARGPCISTAT); 521 522 /* Silently clear any latched errors. */ 523 ahd_outb(ahd, TARGPCISTAT, targpcistat); 524 pci_status1 = aic_pci_read_config(ahd->dev_softc, 525 PCIR_STATUS + 1, /*bytes*/1); 526 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 527 pci_status1, /*bytes*/1); 528 ahd_outb(ahd, CLRINT, CLRPCIINT); 529 } 530 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 531 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 532 return (error); 533 } 534 535 /* 536 * Check the external port logic for a serial eeprom 537 * and termination/cable detection contrls. 538 */ 539 static int 540 ahd_check_extport(struct ahd_softc *ahd) 541 { 542 struct vpd_config vpd; 543 struct seeprom_config *sc; 544 u_int adapter_control; 545 int have_seeprom; 546 int error; 547 548 sc = ahd->seep_config; 549 have_seeprom = ahd_acquire_seeprom(ahd); 550 if (have_seeprom) { 551 u_int start_addr; 552 553 /* 554 * Fetch VPD for this function and parse it. 555 */ 556 if (bootverbose) 557 printf("%s: Reading VPD from SEEPROM...", 558 ahd_name(ahd)); 559 560 /* Address is always in units of 16bit words */ 561 start_addr = ((2 * sizeof(*sc)) 562 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 563 564 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 565 start_addr, sizeof(vpd)/2, 566 /*bytestream*/TRUE); 567 if (error == 0) 568 error = ahd_parse_vpddata(ahd, &vpd); 569 if (bootverbose) 570 printf("%s: VPD parsing %s\n", 571 ahd_name(ahd), 572 error == 0 ? "successful" : "failed"); 573 574 if (bootverbose) 575 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 576 577 /* Address is always in units of 16bit words */ 578 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 579 580 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 581 start_addr, sizeof(*sc)/2, 582 /*bytestream*/FALSE); 583 584 if (error != 0) { 585 printf("Unable to read SEEPROM\n"); 586 have_seeprom = 0; 587 } else { 588 have_seeprom = ahd_verify_cksum(sc); 589 590 if (bootverbose) { 591 if (have_seeprom == 0) 592 printf ("checksum error\n"); 593 else 594 printf ("done.\n"); 595 } 596 } 597 ahd_release_seeprom(ahd); 598 } 599 600 if (!have_seeprom) { 601 u_int nvram_scb; 602 603 /* 604 * Pull scratch ram settings and treat them as 605 * if they are the contents of an seeprom if 606 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 607 * in SCB 0xFF. We manually compose the data as 16bit 608 * values to avoid endian issues. 609 */ 610 ahd_set_scbptr(ahd, 0xFF); 611 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 612 if (nvram_scb != 0xFF 613 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 614 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 615 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 616 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 617 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 618 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 619 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 620 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 621 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 622 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 623 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 624 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 625 uint16_t *sc_data; 626 int i; 627 628 ahd_set_scbptr(ahd, nvram_scb); 629 sc_data = (uint16_t *)sc; 630 for (i = 0; i < 64; i += 2) 631 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 632 have_seeprom = ahd_verify_cksum(sc); 633 if (have_seeprom) 634 ahd->flags |= AHD_SCB_CONFIG_USED; 635 } 636 } 637 638 #ifdef AHD_DEBUG 639 if (have_seeprom != 0 640 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 641 uint16_t *sc_data; 642 int i; 643 644 printf("%s: Seeprom Contents:", ahd_name(ahd)); 645 sc_data = (uint16_t *)sc; 646 for (i = 0; i < (sizeof(*sc)); i += 2) 647 printf("\n\t0x%.4x", sc_data[i]); 648 printf("\n"); 649 } 650 #endif 651 652 if (!have_seeprom) { 653 if (bootverbose) 654 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 655 ahd->flags |= AHD_USEDEFAULTS; 656 error = ahd_default_config(ahd); 657 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 658 free(ahd->seep_config, M_DEVBUF); 659 ahd->seep_config = NULL; 660 } else { 661 error = ahd_parse_cfgdata(ahd, sc); 662 adapter_control = sc->adapter_control; 663 } 664 if (error != 0) 665 return (error); 666 667 ahd_configure_termination(ahd, adapter_control); 668 669 return (0); 670 } 671 672 static void 673 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 674 { 675 int error; 676 u_int sxfrctl1; 677 uint8_t termctl; 678 uint32_t devconfig; 679 680 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 681 devconfig &= ~STPWLEVEL; 682 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 683 devconfig |= STPWLEVEL; 684 if (bootverbose) 685 printf("%s: STPWLEVEL is %s\n", 686 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 687 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 688 689 /* Make sure current sensing is off. */ 690 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 691 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 692 } 693 694 /* 695 * Read to sense. Write to set. 696 */ 697 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 698 if ((adapter_control & CFAUTOTERM) == 0) { 699 if (bootverbose) 700 printf("%s: Manual Primary Termination\n", 701 ahd_name(ahd)); 702 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 703 if ((adapter_control & CFSTERM) != 0) 704 termctl |= FLX_TERMCTL_ENPRILOW; 705 if ((adapter_control & CFWSTERM) != 0) 706 termctl |= FLX_TERMCTL_ENPRIHIGH; 707 } else if (error != 0) { 708 printf("%s: Primary Auto-Term Sensing failed! " 709 "Using Defaults.\n", ahd_name(ahd)); 710 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 711 } 712 713 if ((adapter_control & CFSEAUTOTERM) == 0) { 714 if (bootverbose) 715 printf("%s: Manual Secondary Termination\n", 716 ahd_name(ahd)); 717 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 718 if ((adapter_control & CFSELOWTERM) != 0) 719 termctl |= FLX_TERMCTL_ENSECLOW; 720 if ((adapter_control & CFSEHIGHTERM) != 0) 721 termctl |= FLX_TERMCTL_ENSECHIGH; 722 } else if (error != 0) { 723 printf("%s: Secondary Auto-Term Sensing failed! " 724 "Using Defaults.\n", ahd_name(ahd)); 725 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 726 } 727 728 /* 729 * Now set the termination based on what we found. 730 */ 731 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 732 ahd->flags &= ~AHD_TERM_ENB_A; 733 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 734 ahd->flags |= AHD_TERM_ENB_A; 735 sxfrctl1 |= STPWEN; 736 } 737 /* Must set the latch once in order to be effective. */ 738 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 739 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 740 741 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 742 if (error != 0) { 743 printf("%s: Unable to set termination settings!\n", 744 ahd_name(ahd)); 745 } else if (bootverbose) { 746 printf("%s: Primary High byte termination %sabled\n", 747 ahd_name(ahd), 748 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 749 750 printf("%s: Primary Low byte termination %sabled\n", 751 ahd_name(ahd), 752 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 753 754 printf("%s: Secondary High byte termination %sabled\n", 755 ahd_name(ahd), 756 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 757 758 printf("%s: Secondary Low byte termination %sabled\n", 759 ahd_name(ahd), 760 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 761 } 762 return; 763 } 764 765 #define DPE 0x80 766 #define SSE 0x40 767 #define RMA 0x20 768 #define RTA 0x10 769 #define STA 0x08 770 #define DPR 0x01 771 772 static const char *split_status_source[] = 773 { 774 "DFF0", 775 "DFF1", 776 "OVLY", 777 "CMC", 778 }; 779 780 static const char *pci_status_source[] = 781 { 782 "DFF0", 783 "DFF1", 784 "SG", 785 "CMC", 786 "OVLY", 787 "NONE", 788 "MSI", 789 "TARG" 790 }; 791 792 static const char *split_status_strings[] = 793 { 794 "%s: Received split response in %s.\n", 795 "%s: Received split completion error message in %s\n", 796 "%s: Receive overrun in %s\n", 797 "%s: Count not complete in %s\n", 798 "%s: Split completion data bucket in %s\n", 799 "%s: Split completion address error in %s\n", 800 "%s: Split completion byte count error in %s\n", 801 "%s: Signaled Target-abort to early terminate a split in %s\n" 802 }; 803 804 static const char *pci_status_strings[] = 805 { 806 "%s: Data Parity Error has been reported via PERR# in %s\n", 807 "%s: Target initial wait state error in %s\n", 808 "%s: Split completion read data parity error in %s\n", 809 "%s: Split completion address attribute parity error in %s\n", 810 "%s: Received a Target Abort in %s\n", 811 "%s: Received a Master Abort in %s\n", 812 "%s: Signal System Error Detected in %s\n", 813 "%s: Address or Write Phase Parity Error Detected in %s.\n" 814 }; 815 816 void 817 ahd_pci_intr(struct ahd_softc *ahd) 818 { 819 uint8_t pci_status[8]; 820 ahd_mode_state saved_modes; 821 u_int pci_status1; 822 u_int intstat; 823 u_int i; 824 u_int reg; 825 826 intstat = ahd_inb(ahd, INTSTAT); 827 828 if ((intstat & SPLTINT) != 0) 829 ahd_pci_split_intr(ahd, intstat); 830 831 if ((intstat & PCIINT) == 0) 832 return; 833 834 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 835 saved_modes = ahd_save_modes(ahd); 836 ahd_dump_card_state(ahd); 837 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 838 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 839 840 if (i == 5) 841 continue; 842 pci_status[i] = ahd_inb(ahd, reg); 843 /* Clear latched errors. So our interrupt deasserts. */ 844 ahd_outb(ahd, reg, pci_status[i]); 845 } 846 847 for (i = 0; i < 8; i++) { 848 u_int bit; 849 850 if (i == 5) 851 continue; 852 853 for (bit = 0; bit < 8; bit++) { 854 855 if ((pci_status[i] & (0x1 << bit)) != 0) { 856 static const char *s; 857 858 s = pci_status_strings[bit]; 859 if (i == 7/*TARG*/ && bit == 3) 860 s = "%s: Signaled Target Abort\n"; 861 printf(s, ahd_name(ahd), pci_status_source[i]); 862 } 863 } 864 } 865 pci_status1 = aic_pci_read_config(ahd->dev_softc, 866 PCIR_STATUS + 1, /*bytes*/1); 867 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 868 pci_status1, /*bytes*/1); 869 ahd_restore_modes(ahd, saved_modes); 870 ahd_outb(ahd, CLRINT, CLRPCIINT); 871 ahd_unpause(ahd); 872 } 873 874 static void 875 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 876 { 877 uint8_t split_status[4]; 878 uint8_t split_status1[4]; 879 uint8_t sg_split_status[2]; 880 uint8_t sg_split_status1[2]; 881 ahd_mode_state saved_modes; 882 u_int i; 883 uint32_t pcix_status; 884 885 /* 886 * Check for splits in all modes. Modes 0 and 1 887 * additionally have SG engine splits to look at. 888 */ 889 pcix_status = aic_pci_read_config(ahd->dev_softc, 890 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 891 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 892 ahd_name(ahd), pcix_status >> 16); 893 saved_modes = ahd_save_modes(ahd); 894 for (i = 0; i < 4; i++) { 895 ahd_set_modes(ahd, i, i); 896 897 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 898 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 899 /* Clear latched errors. So our interrupt deasserts. */ 900 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 901 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 902 if (i > 1) 903 continue; 904 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 905 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 906 /* Clear latched errors. So our interrupt deasserts. */ 907 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 908 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 909 } 910 911 for (i = 0; i < 4; i++) { 912 u_int bit; 913 914 for (bit = 0; bit < 8; bit++) { 915 916 if ((split_status[i] & (0x1 << bit)) != 0) { 917 static const char *s; 918 919 s = split_status_strings[bit]; 920 printf(s, ahd_name(ahd), 921 split_status_source[i]); 922 } 923 924 if (i > 1) 925 continue; 926 927 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 928 static const char *s; 929 930 s = split_status_strings[bit]; 931 printf(s, ahd_name(ahd), "SG"); 932 } 933 } 934 } 935 /* 936 * Clear PCI-X status bits. 937 */ 938 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 939 pcix_status, /*bytes*/4); 940 ahd_outb(ahd, CLRINT, CLRSPLTINT); 941 ahd_restore_modes(ahd, saved_modes); 942 } 943 944 static int 945 ahd_aic7901_setup(struct ahd_softc *ahd) 946 { 947 948 ahd->chip = AHD_AIC7901; 949 ahd->features = AHD_AIC7901_FE; 950 return (ahd_aic790X_setup(ahd)); 951 } 952 953 static int 954 ahd_aic7901A_setup(struct ahd_softc *ahd) 955 { 956 957 ahd->chip = AHD_AIC7901A; 958 ahd->features = AHD_AIC7901A_FE; 959 return (ahd_aic790X_setup(ahd)); 960 } 961 962 static int 963 ahd_aic7902_setup(struct ahd_softc *ahd) 964 { 965 ahd->chip = AHD_AIC7902; 966 ahd->features = AHD_AIC7902_FE; 967 return (ahd_aic790X_setup(ahd)); 968 } 969 970 static int 971 ahd_aic790X_setup(struct ahd_softc *ahd) 972 { 973 aic_dev_softc_t pci; 974 u_int rev; 975 976 pci = ahd->dev_softc; 977 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 978 if (rev < ID_AIC7902_PCI_REV_A4) { 979 printf("%s: Unable to attach to unsupported chip revision %d\n", 980 ahd_name(ahd), rev); 981 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 982 return (ENXIO); 983 } 984 ahd->channel = aic_get_pci_function(pci) + 'A'; 985 if (rev < ID_AIC7902_PCI_REV_B0) { 986 /* 987 * Enable A series workarounds. 988 */ 989 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 990 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 991 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 992 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 993 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 994 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 995 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 996 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 997 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 998 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 999 | AHD_FAINT_LED_BUG; 1000 1001 /* 1002 * IO Cell paramter setup. 1003 */ 1004 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1005 1006 if ((ahd->flags & AHD_HP_BOARD) == 0) 1007 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1008 } else { 1009 u_int devconfig1; 1010 1011 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1012 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1013 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1014 1015 /* 1016 * Some issues have been resolved in the 7901B. 1017 */ 1018 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1019 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1020 | AHD_BUSFREEREV_BUG; 1021 1022 /* 1023 * IO Cell paramter setup. 1024 */ 1025 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1026 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1027 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1028 1029 /* 1030 * Set the PREQDIS bit for H2B which disables some workaround 1031 * that doesn't work on regular PCI busses. 1032 * XXX - Find out exactly what this does from the hardware 1033 * folks! 1034 */ 1035 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1036 aic_pci_write_config(pci, DEVCONFIG1, 1037 devconfig1|PREQDIS, /*bytes*/1); 1038 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1039 } 1040 1041 return (0); 1042 }
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