Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/aic7xxx/aic79xx_reg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $ 7 * 8 * $FreeBSD: releng/11.2/sys/dev/aic7xxx/aic79xx_reg.h 260401 2014-01-07 19:33:17Z scottl $ 9 */ 10 typedef int (ahd_reg_print_t)(u_int, u_int *, u_int); 11 typedef struct ahd_reg_parse_entry { 12 char *name; 13 uint8_t value; 14 uint8_t mask; 15 } ahd_reg_parse_entry_t; 16 17 #if AIC_DEBUG_REGISTERS 18 ahd_reg_print_t ahd_mode_ptr_print; 19 #else 20 #define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ 21 ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap) 22 #endif 23 24 #if AIC_DEBUG_REGISTERS 25 ahd_reg_print_t ahd_intstat_print; 26 #else 27 #define ahd_intstat_print(regvalue, cur_col, wrap) \ 28 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap) 29 #endif 30 31 #if AIC_DEBUG_REGISTERS 32 ahd_reg_print_t ahd_seqintcode_print; 33 #else 34 #define ahd_seqintcode_print(regvalue, cur_col, wrap) \ 35 ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap) 36 #endif 37 38 #if AIC_DEBUG_REGISTERS 39 ahd_reg_print_t ahd_clrint_print; 40 #else 41 #define ahd_clrint_print(regvalue, cur_col, wrap) \ 42 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap) 43 #endif 44 45 #if AIC_DEBUG_REGISTERS 46 ahd_reg_print_t ahd_error_print; 47 #else 48 #define ahd_error_print(regvalue, cur_col, wrap) \ 49 ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap) 50 #endif 51 52 #if AIC_DEBUG_REGISTERS 53 ahd_reg_print_t ahd_clrerr_print; 54 #else 55 #define ahd_clrerr_print(regvalue, cur_col, wrap) \ 56 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap) 57 #endif 58 59 #if AIC_DEBUG_REGISTERS 60 ahd_reg_print_t ahd_hcntrl_print; 61 #else 62 #define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 63 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap) 64 #endif 65 66 #if AIC_DEBUG_REGISTERS 67 ahd_reg_print_t ahd_hnscb_qoff_print; 68 #else 69 #define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \ 70 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap) 71 #endif 72 73 #if AIC_DEBUG_REGISTERS 74 ahd_reg_print_t ahd_hescb_qoff_print; 75 #else 76 #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 77 ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap) 78 #endif 79 80 #if AIC_DEBUG_REGISTERS 81 ahd_reg_print_t ahd_hs_mailbox_print; 82 #else 83 #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \ 84 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap) 85 #endif 86 87 #if AIC_DEBUG_REGISTERS 88 ahd_reg_print_t ahd_seqintstat_print; 89 #else 90 #define ahd_seqintstat_print(regvalue, cur_col, wrap) \ 91 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 92 #endif 93 94 #if AIC_DEBUG_REGISTERS 95 ahd_reg_print_t ahd_clrseqintstat_print; 96 #else 97 #define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \ 98 ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 99 #endif 100 101 #if AIC_DEBUG_REGISTERS 102 ahd_reg_print_t ahd_swtimer_print; 103 #else 104 #define ahd_swtimer_print(regvalue, cur_col, wrap) \ 105 ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap) 106 #endif 107 108 #if AIC_DEBUG_REGISTERS 109 ahd_reg_print_t ahd_snscb_qoff_print; 110 #else 111 #define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \ 112 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap) 113 #endif 114 115 #if AIC_DEBUG_REGISTERS 116 ahd_reg_print_t ahd_sescb_qoff_print; 117 #else 118 #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 119 ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap) 120 #endif 121 122 #if AIC_DEBUG_REGISTERS 123 ahd_reg_print_t ahd_sdscb_qoff_print; 124 #else 125 #define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \ 126 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap) 127 #endif 128 129 #if AIC_DEBUG_REGISTERS 130 ahd_reg_print_t ahd_qoff_ctlsta_print; 131 #else 132 #define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 133 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap) 134 #endif 135 136 #if AIC_DEBUG_REGISTERS 137 ahd_reg_print_t ahd_intctl_print; 138 #else 139 #define ahd_intctl_print(regvalue, cur_col, wrap) \ 140 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap) 141 #endif 142 143 #if AIC_DEBUG_REGISTERS 144 ahd_reg_print_t ahd_dfcntrl_print; 145 #else 146 #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \ 147 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap) 148 #endif 149 150 #if AIC_DEBUG_REGISTERS 151 ahd_reg_print_t ahd_dscommand0_print; 152 #else 153 #define ahd_dscommand0_print(regvalue, cur_col, wrap) \ 154 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap) 155 #endif 156 157 #if AIC_DEBUG_REGISTERS 158 ahd_reg_print_t ahd_dfstatus_print; 159 #else 160 #define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 161 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap) 162 #endif 163 164 #if AIC_DEBUG_REGISTERS 165 ahd_reg_print_t ahd_sg_cache_shadow_print; 166 #else 167 #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 168 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap) 169 #endif 170 171 #if AIC_DEBUG_REGISTERS 172 ahd_reg_print_t ahd_sg_cache_pre_print; 173 #else 174 #define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 175 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap) 176 #endif 177 178 #if AIC_DEBUG_REGISTERS 179 ahd_reg_print_t ahd_arbctl_print; 180 #else 181 #define ahd_arbctl_print(regvalue, cur_col, wrap) \ 182 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap) 183 #endif 184 185 #if AIC_DEBUG_REGISTERS 186 ahd_reg_print_t ahd_lqin_print; 187 #else 188 #define ahd_lqin_print(regvalue, cur_col, wrap) \ 189 ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap) 190 #endif 191 192 #if AIC_DEBUG_REGISTERS 193 ahd_reg_print_t ahd_typeptr_print; 194 #else 195 #define ahd_typeptr_print(regvalue, cur_col, wrap) \ 196 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap) 197 #endif 198 199 #if AIC_DEBUG_REGISTERS 200 ahd_reg_print_t ahd_tagptr_print; 201 #else 202 #define ahd_tagptr_print(regvalue, cur_col, wrap) \ 203 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap) 204 #endif 205 206 #if AIC_DEBUG_REGISTERS 207 ahd_reg_print_t ahd_lunptr_print; 208 #else 209 #define ahd_lunptr_print(regvalue, cur_col, wrap) \ 210 ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap) 211 #endif 212 213 #if AIC_DEBUG_REGISTERS 214 ahd_reg_print_t ahd_datalenptr_print; 215 #else 216 #define ahd_datalenptr_print(regvalue, cur_col, wrap) \ 217 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap) 218 #endif 219 220 #if AIC_DEBUG_REGISTERS 221 ahd_reg_print_t ahd_statlenptr_print; 222 #else 223 #define ahd_statlenptr_print(regvalue, cur_col, wrap) \ 224 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap) 225 #endif 226 227 #if AIC_DEBUG_REGISTERS 228 ahd_reg_print_t ahd_cmdlenptr_print; 229 #else 230 #define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 231 ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap) 232 #endif 233 234 #if AIC_DEBUG_REGISTERS 235 ahd_reg_print_t ahd_attrptr_print; 236 #else 237 #define ahd_attrptr_print(regvalue, cur_col, wrap) \ 238 ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap) 239 #endif 240 241 #if AIC_DEBUG_REGISTERS 242 ahd_reg_print_t ahd_flagptr_print; 243 #else 244 #define ahd_flagptr_print(regvalue, cur_col, wrap) \ 245 ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap) 246 #endif 247 248 #if AIC_DEBUG_REGISTERS 249 ahd_reg_print_t ahd_cmdptr_print; 250 #else 251 #define ahd_cmdptr_print(regvalue, cur_col, wrap) \ 252 ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap) 253 #endif 254 255 #if AIC_DEBUG_REGISTERS 256 ahd_reg_print_t ahd_qnextptr_print; 257 #else 258 #define ahd_qnextptr_print(regvalue, cur_col, wrap) \ 259 ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap) 260 #endif 261 262 #if AIC_DEBUG_REGISTERS 263 ahd_reg_print_t ahd_idptr_print; 264 #else 265 #define ahd_idptr_print(regvalue, cur_col, wrap) \ 266 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap) 267 #endif 268 269 #if AIC_DEBUG_REGISTERS 270 ahd_reg_print_t ahd_abrtbyteptr_print; 271 #else 272 #define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 273 ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap) 274 #endif 275 276 #if AIC_DEBUG_REGISTERS 277 ahd_reg_print_t ahd_abrtbitptr_print; 278 #else 279 #define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \ 280 ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap) 281 #endif 282 283 #if AIC_DEBUG_REGISTERS 284 ahd_reg_print_t ahd_maxcmdbytes_print; 285 #else 286 #define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \ 287 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap) 288 #endif 289 290 #if AIC_DEBUG_REGISTERS 291 ahd_reg_print_t ahd_maxcmd2rcv_print; 292 #else 293 #define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \ 294 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap) 295 #endif 296 297 #if AIC_DEBUG_REGISTERS 298 ahd_reg_print_t ahd_shortthresh_print; 299 #else 300 #define ahd_shortthresh_print(regvalue, cur_col, wrap) \ 301 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap) 302 #endif 303 304 #if AIC_DEBUG_REGISTERS 305 ahd_reg_print_t ahd_lunlen_print; 306 #else 307 #define ahd_lunlen_print(regvalue, cur_col, wrap) \ 308 ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap) 309 #endif 310 311 #if AIC_DEBUG_REGISTERS 312 ahd_reg_print_t ahd_cdblimit_print; 313 #else 314 #define ahd_cdblimit_print(regvalue, cur_col, wrap) \ 315 ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap) 316 #endif 317 318 #if AIC_DEBUG_REGISTERS 319 ahd_reg_print_t ahd_maxcmd_print; 320 #else 321 #define ahd_maxcmd_print(regvalue, cur_col, wrap) \ 322 ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap) 323 #endif 324 325 #if AIC_DEBUG_REGISTERS 326 ahd_reg_print_t ahd_maxcmdcnt_print; 327 #else 328 #define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \ 329 ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap) 330 #endif 331 332 #if AIC_DEBUG_REGISTERS 333 ahd_reg_print_t ahd_lqrsvd01_print; 334 #else 335 #define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \ 336 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap) 337 #endif 338 339 #if AIC_DEBUG_REGISTERS 340 ahd_reg_print_t ahd_lqrsvd16_print; 341 #else 342 #define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \ 343 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap) 344 #endif 345 346 #if AIC_DEBUG_REGISTERS 347 ahd_reg_print_t ahd_lqrsvd17_print; 348 #else 349 #define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \ 350 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap) 351 #endif 352 353 #if AIC_DEBUG_REGISTERS 354 ahd_reg_print_t ahd_cmdrsvd0_print; 355 #else 356 #define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \ 357 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap) 358 #endif 359 360 #if AIC_DEBUG_REGISTERS 361 ahd_reg_print_t ahd_lqctl0_print; 362 #else 363 #define ahd_lqctl0_print(regvalue, cur_col, wrap) \ 364 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap) 365 #endif 366 367 #if AIC_DEBUG_REGISTERS 368 ahd_reg_print_t ahd_lqctl1_print; 369 #else 370 #define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 371 ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap) 372 #endif 373 374 #if AIC_DEBUG_REGISTERS 375 ahd_reg_print_t ahd_lqctl2_print; 376 #else 377 #define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 378 ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap) 379 #endif 380 381 #if AIC_DEBUG_REGISTERS 382 ahd_reg_print_t ahd_scsbist0_print; 383 #else 384 #define ahd_scsbist0_print(regvalue, cur_col, wrap) \ 385 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap) 386 #endif 387 388 #if AIC_DEBUG_REGISTERS 389 ahd_reg_print_t ahd_scsiseq0_print; 390 #else 391 #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 392 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap) 393 #endif 394 395 #if AIC_DEBUG_REGISTERS 396 ahd_reg_print_t ahd_scsbist1_print; 397 #else 398 #define ahd_scsbist1_print(regvalue, cur_col, wrap) \ 399 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap) 400 #endif 401 402 #if AIC_DEBUG_REGISTERS 403 ahd_reg_print_t ahd_scsiseq1_print; 404 #else 405 #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \ 406 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap) 407 #endif 408 409 #if AIC_DEBUG_REGISTERS 410 ahd_reg_print_t ahd_businitid_print; 411 #else 412 #define ahd_businitid_print(regvalue, cur_col, wrap) \ 413 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap) 414 #endif 415 416 #if AIC_DEBUG_REGISTERS 417 ahd_reg_print_t ahd_sxfrctl0_print; 418 #else 419 #define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \ 420 ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap) 421 #endif 422 423 #if AIC_DEBUG_REGISTERS 424 ahd_reg_print_t ahd_dlcount_print; 425 #else 426 #define ahd_dlcount_print(regvalue, cur_col, wrap) \ 427 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap) 428 #endif 429 430 #if AIC_DEBUG_REGISTERS 431 ahd_reg_print_t ahd_sxfrctl1_print; 432 #else 433 #define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 434 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap) 435 #endif 436 437 #if AIC_DEBUG_REGISTERS 438 ahd_reg_print_t ahd_bustargid_print; 439 #else 440 #define ahd_bustargid_print(regvalue, cur_col, wrap) \ 441 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap) 442 #endif 443 444 #if AIC_DEBUG_REGISTERS 445 ahd_reg_print_t ahd_sxfrctl2_print; 446 #else 447 #define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \ 448 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap) 449 #endif 450 451 #if AIC_DEBUG_REGISTERS 452 ahd_reg_print_t ahd_dffstat_print; 453 #else 454 #define ahd_dffstat_print(regvalue, cur_col, wrap) \ 455 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap) 456 #endif 457 458 #if AIC_DEBUG_REGISTERS 459 ahd_reg_print_t ahd_scsisigo_print; 460 #else 461 #define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 462 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 463 #endif 464 465 #if AIC_DEBUG_REGISTERS 466 ahd_reg_print_t ahd_multargid_print; 467 #else 468 #define ahd_multargid_print(regvalue, cur_col, wrap) \ 469 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 470 #endif 471 472 #if AIC_DEBUG_REGISTERS 473 ahd_reg_print_t ahd_scsisigi_print; 474 #else 475 #define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 476 ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap) 477 #endif 478 479 #if AIC_DEBUG_REGISTERS 480 ahd_reg_print_t ahd_scsiphase_print; 481 #else 482 #define ahd_scsiphase_print(regvalue, cur_col, wrap) \ 483 ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap) 484 #endif 485 486 #if AIC_DEBUG_REGISTERS 487 ahd_reg_print_t ahd_scsidat0_img_print; 488 #else 489 #define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \ 490 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap) 491 #endif 492 493 #if AIC_DEBUG_REGISTERS 494 ahd_reg_print_t ahd_scsidat_print; 495 #else 496 #define ahd_scsidat_print(regvalue, cur_col, wrap) \ 497 ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap) 498 #endif 499 500 #if AIC_DEBUG_REGISTERS 501 ahd_reg_print_t ahd_scsibus_print; 502 #else 503 #define ahd_scsibus_print(regvalue, cur_col, wrap) \ 504 ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap) 505 #endif 506 507 #if AIC_DEBUG_REGISTERS 508 ahd_reg_print_t ahd_targidin_print; 509 #else 510 #define ahd_targidin_print(regvalue, cur_col, wrap) \ 511 ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap) 512 #endif 513 514 #if AIC_DEBUG_REGISTERS 515 ahd_reg_print_t ahd_selid_print; 516 #else 517 #define ahd_selid_print(regvalue, cur_col, wrap) \ 518 ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap) 519 #endif 520 521 #if AIC_DEBUG_REGISTERS 522 ahd_reg_print_t ahd_optionmode_print; 523 #else 524 #define ahd_optionmode_print(regvalue, cur_col, wrap) \ 525 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap) 526 #endif 527 528 #if AIC_DEBUG_REGISTERS 529 ahd_reg_print_t ahd_sblkctl_print; 530 #else 531 #define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 532 ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap) 533 #endif 534 535 #if AIC_DEBUG_REGISTERS 536 ahd_reg_print_t ahd_simode0_print; 537 #else 538 #define ahd_simode0_print(regvalue, cur_col, wrap) \ 539 ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap) 540 #endif 541 542 #if AIC_DEBUG_REGISTERS 543 ahd_reg_print_t ahd_sstat0_print; 544 #else 545 #define ahd_sstat0_print(regvalue, cur_col, wrap) \ 546 ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap) 547 #endif 548 549 #if AIC_DEBUG_REGISTERS 550 ahd_reg_print_t ahd_clrsint0_print; 551 #else 552 #define ahd_clrsint0_print(regvalue, cur_col, wrap) \ 553 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap) 554 #endif 555 556 #if AIC_DEBUG_REGISTERS 557 ahd_reg_print_t ahd_sstat1_print; 558 #else 559 #define ahd_sstat1_print(regvalue, cur_col, wrap) \ 560 ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap) 561 #endif 562 563 #if AIC_DEBUG_REGISTERS 564 ahd_reg_print_t ahd_clrsint1_print; 565 #else 566 #define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 567 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 568 #endif 569 570 #if AIC_DEBUG_REGISTERS 571 ahd_reg_print_t ahd_sstat2_print; 572 #else 573 #define ahd_sstat2_print(regvalue, cur_col, wrap) \ 574 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 575 #endif 576 577 #if AIC_DEBUG_REGISTERS 578 ahd_reg_print_t ahd_clrsint2_print; 579 #else 580 #define ahd_clrsint2_print(regvalue, cur_col, wrap) \ 581 ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap) 582 #endif 583 584 #if AIC_DEBUG_REGISTERS 585 ahd_reg_print_t ahd_simode2_print; 586 #else 587 #define ahd_simode2_print(regvalue, cur_col, wrap) \ 588 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 589 #endif 590 591 #if AIC_DEBUG_REGISTERS 592 ahd_reg_print_t ahd_perrdiag_print; 593 #else 594 #define ahd_perrdiag_print(regvalue, cur_col, wrap) \ 595 ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap) 596 #endif 597 598 #if AIC_DEBUG_REGISTERS 599 ahd_reg_print_t ahd_lqistate_print; 600 #else 601 #define ahd_lqistate_print(regvalue, cur_col, wrap) \ 602 ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap) 603 #endif 604 605 #if AIC_DEBUG_REGISTERS 606 ahd_reg_print_t ahd_soffcnt_print; 607 #else 608 #define ahd_soffcnt_print(regvalue, cur_col, wrap) \ 609 ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap) 610 #endif 611 612 #if AIC_DEBUG_REGISTERS 613 ahd_reg_print_t ahd_lqostate_print; 614 #else 615 #define ahd_lqostate_print(regvalue, cur_col, wrap) \ 616 ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap) 617 #endif 618 619 #if AIC_DEBUG_REGISTERS 620 ahd_reg_print_t ahd_lqistat0_print; 621 #else 622 #define ahd_lqistat0_print(regvalue, cur_col, wrap) \ 623 ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap) 624 #endif 625 626 #if AIC_DEBUG_REGISTERS 627 ahd_reg_print_t ahd_clrlqiint0_print; 628 #else 629 #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 630 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 631 #endif 632 633 #if AIC_DEBUG_REGISTERS 634 ahd_reg_print_t ahd_lqimode0_print; 635 #else 636 #define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 637 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 638 #endif 639 640 #if AIC_DEBUG_REGISTERS 641 ahd_reg_print_t ahd_lqistat1_print; 642 #else 643 #define ahd_lqistat1_print(regvalue, cur_col, wrap) \ 644 ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap) 645 #endif 646 647 #if AIC_DEBUG_REGISTERS 648 ahd_reg_print_t ahd_clrlqiint1_print; 649 #else 650 #define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \ 651 ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap) 652 #endif 653 654 #if AIC_DEBUG_REGISTERS 655 ahd_reg_print_t ahd_lqimode1_print; 656 #else 657 #define ahd_lqimode1_print(regvalue, cur_col, wrap) \ 658 ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap) 659 #endif 660 661 #if AIC_DEBUG_REGISTERS 662 ahd_reg_print_t ahd_lqistat2_print; 663 #else 664 #define ahd_lqistat2_print(regvalue, cur_col, wrap) \ 665 ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap) 666 #endif 667 668 #if AIC_DEBUG_REGISTERS 669 ahd_reg_print_t ahd_sstat3_print; 670 #else 671 #define ahd_sstat3_print(regvalue, cur_col, wrap) \ 672 ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap) 673 #endif 674 675 #if AIC_DEBUG_REGISTERS 676 ahd_reg_print_t ahd_clrsint3_print; 677 #else 678 #define ahd_clrsint3_print(regvalue, cur_col, wrap) \ 679 ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap) 680 #endif 681 682 #if AIC_DEBUG_REGISTERS 683 ahd_reg_print_t ahd_simode3_print; 684 #else 685 #define ahd_simode3_print(regvalue, cur_col, wrap) \ 686 ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap) 687 #endif 688 689 #if AIC_DEBUG_REGISTERS 690 ahd_reg_print_t ahd_lqomode0_print; 691 #else 692 #define ahd_lqomode0_print(regvalue, cur_col, wrap) \ 693 ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap) 694 #endif 695 696 #if AIC_DEBUG_REGISTERS 697 ahd_reg_print_t ahd_lqostat0_print; 698 #else 699 #define ahd_lqostat0_print(regvalue, cur_col, wrap) \ 700 ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap) 701 #endif 702 703 #if AIC_DEBUG_REGISTERS 704 ahd_reg_print_t ahd_clrlqoint0_print; 705 #else 706 #define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \ 707 ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap) 708 #endif 709 710 #if AIC_DEBUG_REGISTERS 711 ahd_reg_print_t ahd_lqomode1_print; 712 #else 713 #define ahd_lqomode1_print(regvalue, cur_col, wrap) \ 714 ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap) 715 #endif 716 717 #if AIC_DEBUG_REGISTERS 718 ahd_reg_print_t ahd_lqostat1_print; 719 #else 720 #define ahd_lqostat1_print(regvalue, cur_col, wrap) \ 721 ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap) 722 #endif 723 724 #if AIC_DEBUG_REGISTERS 725 ahd_reg_print_t ahd_clrlqoint1_print; 726 #else 727 #define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \ 728 ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap) 729 #endif 730 731 #if AIC_DEBUG_REGISTERS 732 ahd_reg_print_t ahd_os_space_cnt_print; 733 #else 734 #define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \ 735 ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap) 736 #endif 737 738 #if AIC_DEBUG_REGISTERS 739 ahd_reg_print_t ahd_lqostat2_print; 740 #else 741 #define ahd_lqostat2_print(regvalue, cur_col, wrap) \ 742 ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap) 743 #endif 744 745 #if AIC_DEBUG_REGISTERS 746 ahd_reg_print_t ahd_simode1_print; 747 #else 748 #define ahd_simode1_print(regvalue, cur_col, wrap) \ 749 ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap) 750 #endif 751 752 #if AIC_DEBUG_REGISTERS 753 ahd_reg_print_t ahd_gsfifo_print; 754 #else 755 #define ahd_gsfifo_print(regvalue, cur_col, wrap) \ 756 ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap) 757 #endif 758 759 #if AIC_DEBUG_REGISTERS 760 ahd_reg_print_t ahd_dffsxfrctl_print; 761 #else 762 #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \ 763 ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap) 764 #endif 765 766 #if AIC_DEBUG_REGISTERS 767 ahd_reg_print_t ahd_nextscb_print; 768 #else 769 #define ahd_nextscb_print(regvalue, cur_col, wrap) \ 770 ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap) 771 #endif 772 773 #if AIC_DEBUG_REGISTERS 774 ahd_reg_print_t ahd_lqoscsctl_print; 775 #else 776 #define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \ 777 ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap) 778 #endif 779 780 #if AIC_DEBUG_REGISTERS 781 ahd_reg_print_t ahd_seqintsrc_print; 782 #else 783 #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \ 784 ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap) 785 #endif 786 787 #if AIC_DEBUG_REGISTERS 788 ahd_reg_print_t ahd_clrseqintsrc_print; 789 #else 790 #define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \ 791 ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap) 792 #endif 793 794 #if AIC_DEBUG_REGISTERS 795 ahd_reg_print_t ahd_currscb_print; 796 #else 797 #define ahd_currscb_print(regvalue, cur_col, wrap) \ 798 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 799 #endif 800 801 #if AIC_DEBUG_REGISTERS 802 ahd_reg_print_t ahd_seqimode_print; 803 #else 804 #define ahd_seqimode_print(regvalue, cur_col, wrap) \ 805 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 806 #endif 807 808 #if AIC_DEBUG_REGISTERS 809 ahd_reg_print_t ahd_mdffstat_print; 810 #else 811 #define ahd_mdffstat_print(regvalue, cur_col, wrap) \ 812 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap) 813 #endif 814 815 #if AIC_DEBUG_REGISTERS 816 ahd_reg_print_t ahd_crccontrol_print; 817 #else 818 #define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 819 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 820 #endif 821 822 #if AIC_DEBUG_REGISTERS 823 ahd_reg_print_t ahd_scsitest_print; 824 #else 825 #define ahd_scsitest_print(regvalue, cur_col, wrap) \ 826 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap) 827 #endif 828 829 #if AIC_DEBUG_REGISTERS 830 ahd_reg_print_t ahd_dfftag_print; 831 #else 832 #define ahd_dfftag_print(regvalue, cur_col, wrap) \ 833 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 834 #endif 835 836 #if AIC_DEBUG_REGISTERS 837 ahd_reg_print_t ahd_lastscb_print; 838 #else 839 #define ahd_lastscb_print(regvalue, cur_col, wrap) \ 840 ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap) 841 #endif 842 843 #if AIC_DEBUG_REGISTERS 844 ahd_reg_print_t ahd_iopdnctl_print; 845 #else 846 #define ahd_iopdnctl_print(regvalue, cur_col, wrap) \ 847 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap) 848 #endif 849 850 #if AIC_DEBUG_REGISTERS 851 ahd_reg_print_t ahd_negoaddr_print; 852 #else 853 #define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 854 ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap) 855 #endif 856 857 #if AIC_DEBUG_REGISTERS 858 ahd_reg_print_t ahd_shaddr_print; 859 #else 860 #define ahd_shaddr_print(regvalue, cur_col, wrap) \ 861 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap) 862 #endif 863 864 #if AIC_DEBUG_REGISTERS 865 ahd_reg_print_t ahd_dgrpcrci_print; 866 #else 867 #define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \ 868 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap) 869 #endif 870 871 #if AIC_DEBUG_REGISTERS 872 ahd_reg_print_t ahd_negperiod_print; 873 #else 874 #define ahd_negperiod_print(regvalue, cur_col, wrap) \ 875 ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap) 876 #endif 877 878 #if AIC_DEBUG_REGISTERS 879 ahd_reg_print_t ahd_packcrci_print; 880 #else 881 #define ahd_packcrci_print(regvalue, cur_col, wrap) \ 882 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap) 883 #endif 884 885 #if AIC_DEBUG_REGISTERS 886 ahd_reg_print_t ahd_negoffset_print; 887 #else 888 #define ahd_negoffset_print(regvalue, cur_col, wrap) \ 889 ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap) 890 #endif 891 892 #if AIC_DEBUG_REGISTERS 893 ahd_reg_print_t ahd_negppropts_print; 894 #else 895 #define ahd_negppropts_print(regvalue, cur_col, wrap) \ 896 ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap) 897 #endif 898 899 #if AIC_DEBUG_REGISTERS 900 ahd_reg_print_t ahd_negconopts_print; 901 #else 902 #define ahd_negconopts_print(regvalue, cur_col, wrap) \ 903 ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap) 904 #endif 905 906 #if AIC_DEBUG_REGISTERS 907 ahd_reg_print_t ahd_annexcol_print; 908 #else 909 #define ahd_annexcol_print(regvalue, cur_col, wrap) \ 910 ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap) 911 #endif 912 913 #if AIC_DEBUG_REGISTERS 914 ahd_reg_print_t ahd_annexdat_print; 915 #else 916 #define ahd_annexdat_print(regvalue, cur_col, wrap) \ 917 ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap) 918 #endif 919 920 #if AIC_DEBUG_REGISTERS 921 ahd_reg_print_t ahd_scschkn_print; 922 #else 923 #define ahd_scschkn_print(regvalue, cur_col, wrap) \ 924 ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap) 925 #endif 926 927 #if AIC_DEBUG_REGISTERS 928 ahd_reg_print_t ahd_iownid_print; 929 #else 930 #define ahd_iownid_print(regvalue, cur_col, wrap) \ 931 ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap) 932 #endif 933 934 #if AIC_DEBUG_REGISTERS 935 ahd_reg_print_t ahd_shcnt_print; 936 #else 937 #define ahd_shcnt_print(regvalue, cur_col, wrap) \ 938 ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap) 939 #endif 940 941 #if AIC_DEBUG_REGISTERS 942 ahd_reg_print_t ahd_pll960ctl0_print; 943 #else 944 #define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \ 945 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap) 946 #endif 947 948 #if AIC_DEBUG_REGISTERS 949 ahd_reg_print_t ahd_pll960ctl1_print; 950 #else 951 #define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \ 952 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap) 953 #endif 954 955 #if AIC_DEBUG_REGISTERS 956 ahd_reg_print_t ahd_townid_print; 957 #else 958 #define ahd_townid_print(regvalue, cur_col, wrap) \ 959 ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap) 960 #endif 961 962 #if AIC_DEBUG_REGISTERS 963 ahd_reg_print_t ahd_xsig_print; 964 #else 965 #define ahd_xsig_print(regvalue, cur_col, wrap) \ 966 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap) 967 #endif 968 969 #if AIC_DEBUG_REGISTERS 970 ahd_reg_print_t ahd_pll960cnt0_print; 971 #else 972 #define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \ 973 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap) 974 #endif 975 976 #if AIC_DEBUG_REGISTERS 977 ahd_reg_print_t ahd_seloid_print; 978 #else 979 #define ahd_seloid_print(regvalue, cur_col, wrap) \ 980 ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap) 981 #endif 982 983 #if AIC_DEBUG_REGISTERS 984 ahd_reg_print_t ahd_fairness_print; 985 #else 986 #define ahd_fairness_print(regvalue, cur_col, wrap) \ 987 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap) 988 #endif 989 990 #if AIC_DEBUG_REGISTERS 991 ahd_reg_print_t ahd_pll400ctl0_print; 992 #else 993 #define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \ 994 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap) 995 #endif 996 997 #if AIC_DEBUG_REGISTERS 998 ahd_reg_print_t ahd_pll400ctl1_print; 999 #else 1000 #define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \ 1001 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap) 1002 #endif 1003 1004 #if AIC_DEBUG_REGISTERS 1005 ahd_reg_print_t ahd_pll400cnt0_print; 1006 #else 1007 #define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \ 1008 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap) 1009 #endif 1010 1011 #if AIC_DEBUG_REGISTERS 1012 ahd_reg_print_t ahd_unfairness_print; 1013 #else 1014 #define ahd_unfairness_print(regvalue, cur_col, wrap) \ 1015 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap) 1016 #endif 1017 1018 #if AIC_DEBUG_REGISTERS 1019 ahd_reg_print_t ahd_hodmaadr_print; 1020 #else 1021 #define ahd_hodmaadr_print(regvalue, cur_col, wrap) \ 1022 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap) 1023 #endif 1024 1025 #if AIC_DEBUG_REGISTERS 1026 ahd_reg_print_t ahd_haddr_print; 1027 #else 1028 #define ahd_haddr_print(regvalue, cur_col, wrap) \ 1029 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap) 1030 #endif 1031 1032 #if AIC_DEBUG_REGISTERS 1033 ahd_reg_print_t ahd_plldelay_print; 1034 #else 1035 #define ahd_plldelay_print(regvalue, cur_col, wrap) \ 1036 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap) 1037 #endif 1038 1039 #if AIC_DEBUG_REGISTERS 1040 ahd_reg_print_t ahd_hcnt_print; 1041 #else 1042 #define ahd_hcnt_print(regvalue, cur_col, wrap) \ 1043 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap) 1044 #endif 1045 1046 #if AIC_DEBUG_REGISTERS 1047 ahd_reg_print_t ahd_hodmacnt_print; 1048 #else 1049 #define ahd_hodmacnt_print(regvalue, cur_col, wrap) \ 1050 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap) 1051 #endif 1052 1053 #if AIC_DEBUG_REGISTERS 1054 ahd_reg_print_t ahd_hodmaen_print; 1055 #else 1056 #define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 1057 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 1058 #endif 1059 1060 #if AIC_DEBUG_REGISTERS 1061 ahd_reg_print_t ahd_scbhaddr_print; 1062 #else 1063 #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 1064 ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap) 1065 #endif 1066 1067 #if AIC_DEBUG_REGISTERS 1068 ahd_reg_print_t ahd_sghaddr_print; 1069 #else 1070 #define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 1071 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 1072 #endif 1073 1074 #if AIC_DEBUG_REGISTERS 1075 ahd_reg_print_t ahd_scbhcnt_print; 1076 #else 1077 #define ahd_scbhcnt_print(regvalue, cur_col, wrap) \ 1078 ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap) 1079 #endif 1080 1081 #if AIC_DEBUG_REGISTERS 1082 ahd_reg_print_t ahd_sghcnt_print; 1083 #else 1084 #define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 1085 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 1086 #endif 1087 1088 #if AIC_DEBUG_REGISTERS 1089 ahd_reg_print_t ahd_dff_thrsh_print; 1090 #else 1091 #define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 1092 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 1093 #endif 1094 1095 #if AIC_DEBUG_REGISTERS 1096 ahd_reg_print_t ahd_romaddr_print; 1097 #else 1098 #define ahd_romaddr_print(regvalue, cur_col, wrap) \ 1099 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap) 1100 #endif 1101 1102 #if AIC_DEBUG_REGISTERS 1103 ahd_reg_print_t ahd_romcntrl_print; 1104 #else 1105 #define ahd_romcntrl_print(regvalue, cur_col, wrap) \ 1106 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap) 1107 #endif 1108 1109 #if AIC_DEBUG_REGISTERS 1110 ahd_reg_print_t ahd_romdata_print; 1111 #else 1112 #define ahd_romdata_print(regvalue, cur_col, wrap) \ 1113 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap) 1114 #endif 1115 1116 #if AIC_DEBUG_REGISTERS 1117 ahd_reg_print_t ahd_dchrxmsg0_print; 1118 #else 1119 #define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \ 1120 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap) 1121 #endif 1122 1123 #if AIC_DEBUG_REGISTERS 1124 ahd_reg_print_t ahd_ovlyrxmsg0_print; 1125 #else 1126 #define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \ 1127 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap) 1128 #endif 1129 1130 #if AIC_DEBUG_REGISTERS 1131 ahd_reg_print_t ahd_cmcrxmsg0_print; 1132 #else 1133 #define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \ 1134 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap) 1135 #endif 1136 1137 #if AIC_DEBUG_REGISTERS 1138 ahd_reg_print_t ahd_roenable_print; 1139 #else 1140 #define ahd_roenable_print(regvalue, cur_col, wrap) \ 1141 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap) 1142 #endif 1143 1144 #if AIC_DEBUG_REGISTERS 1145 ahd_reg_print_t ahd_dchrxmsg1_print; 1146 #else 1147 #define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \ 1148 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap) 1149 #endif 1150 1151 #if AIC_DEBUG_REGISTERS 1152 ahd_reg_print_t ahd_ovlyrxmsg1_print; 1153 #else 1154 #define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \ 1155 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap) 1156 #endif 1157 1158 #if AIC_DEBUG_REGISTERS 1159 ahd_reg_print_t ahd_cmcrxmsg1_print; 1160 #else 1161 #define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \ 1162 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap) 1163 #endif 1164 1165 #if AIC_DEBUG_REGISTERS 1166 ahd_reg_print_t ahd_nsenable_print; 1167 #else 1168 #define ahd_nsenable_print(regvalue, cur_col, wrap) \ 1169 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap) 1170 #endif 1171 1172 #if AIC_DEBUG_REGISTERS 1173 ahd_reg_print_t ahd_dchrxmsg2_print; 1174 #else 1175 #define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \ 1176 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap) 1177 #endif 1178 1179 #if AIC_DEBUG_REGISTERS 1180 ahd_reg_print_t ahd_ovlyrxmsg2_print; 1181 #else 1182 #define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \ 1183 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap) 1184 #endif 1185 1186 #if AIC_DEBUG_REGISTERS 1187 ahd_reg_print_t ahd_cmcrxmsg2_print; 1188 #else 1189 #define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \ 1190 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap) 1191 #endif 1192 1193 #if AIC_DEBUG_REGISTERS 1194 ahd_reg_print_t ahd_ost_print; 1195 #else 1196 #define ahd_ost_print(regvalue, cur_col, wrap) \ 1197 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap) 1198 #endif 1199 1200 #if AIC_DEBUG_REGISTERS 1201 ahd_reg_print_t ahd_dchrxmsg3_print; 1202 #else 1203 #define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \ 1204 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap) 1205 #endif 1206 1207 #if AIC_DEBUG_REGISTERS 1208 ahd_reg_print_t ahd_ovlyrxmsg3_print; 1209 #else 1210 #define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \ 1211 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap) 1212 #endif 1213 1214 #if AIC_DEBUG_REGISTERS 1215 ahd_reg_print_t ahd_cmcrxmsg3_print; 1216 #else 1217 #define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \ 1218 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap) 1219 #endif 1220 1221 #if AIC_DEBUG_REGISTERS 1222 ahd_reg_print_t ahd_pcixctl_print; 1223 #else 1224 #define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 1225 ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap) 1226 #endif 1227 1228 #if AIC_DEBUG_REGISTERS 1229 ahd_reg_print_t ahd_cmcseqbcnt_print; 1230 #else 1231 #define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \ 1232 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap) 1233 #endif 1234 1235 #if AIC_DEBUG_REGISTERS 1236 ahd_reg_print_t ahd_dchseqbcnt_print; 1237 #else 1238 #define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \ 1239 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap) 1240 #endif 1241 1242 #if AIC_DEBUG_REGISTERS 1243 ahd_reg_print_t ahd_ovlyseqbcnt_print; 1244 #else 1245 #define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \ 1246 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap) 1247 #endif 1248 1249 #if AIC_DEBUG_REGISTERS 1250 ahd_reg_print_t ahd_cmcspltstat0_print; 1251 #else 1252 #define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \ 1253 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1254 #endif 1255 1256 #if AIC_DEBUG_REGISTERS 1257 ahd_reg_print_t ahd_dchspltstat0_print; 1258 #else 1259 #define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 1260 ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1261 #endif 1262 1263 #if AIC_DEBUG_REGISTERS 1264 ahd_reg_print_t ahd_ovlyspltstat0_print; 1265 #else 1266 #define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \ 1267 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1268 #endif 1269 1270 #if AIC_DEBUG_REGISTERS 1271 ahd_reg_print_t ahd_cmcspltstat1_print; 1272 #else 1273 #define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \ 1274 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1275 #endif 1276 1277 #if AIC_DEBUG_REGISTERS 1278 ahd_reg_print_t ahd_dchspltstat1_print; 1279 #else 1280 #define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 1281 ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1282 #endif 1283 1284 #if AIC_DEBUG_REGISTERS 1285 ahd_reg_print_t ahd_ovlyspltstat1_print; 1286 #else 1287 #define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \ 1288 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1289 #endif 1290 1291 #if AIC_DEBUG_REGISTERS 1292 ahd_reg_print_t ahd_sgrxmsg0_print; 1293 #else 1294 #define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \ 1295 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap) 1296 #endif 1297 1298 #if AIC_DEBUG_REGISTERS 1299 ahd_reg_print_t ahd_slvspltoutadr0_print; 1300 #else 1301 #define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \ 1302 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap) 1303 #endif 1304 1305 #if AIC_DEBUG_REGISTERS 1306 ahd_reg_print_t ahd_sgrxmsg1_print; 1307 #else 1308 #define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \ 1309 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap) 1310 #endif 1311 1312 #if AIC_DEBUG_REGISTERS 1313 ahd_reg_print_t ahd_slvspltoutadr1_print; 1314 #else 1315 #define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \ 1316 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap) 1317 #endif 1318 1319 #if AIC_DEBUG_REGISTERS 1320 ahd_reg_print_t ahd_sgrxmsg2_print; 1321 #else 1322 #define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \ 1323 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap) 1324 #endif 1325 1326 #if AIC_DEBUG_REGISTERS 1327 ahd_reg_print_t ahd_slvspltoutadr2_print; 1328 #else 1329 #define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \ 1330 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap) 1331 #endif 1332 1333 #if AIC_DEBUG_REGISTERS 1334 ahd_reg_print_t ahd_sgrxmsg3_print; 1335 #else 1336 #define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \ 1337 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap) 1338 #endif 1339 1340 #if AIC_DEBUG_REGISTERS 1341 ahd_reg_print_t ahd_slvspltoutadr3_print; 1342 #else 1343 #define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \ 1344 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap) 1345 #endif 1346 1347 #if AIC_DEBUG_REGISTERS 1348 ahd_reg_print_t ahd_slvspltoutattr0_print; 1349 #else 1350 #define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \ 1351 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap) 1352 #endif 1353 1354 #if AIC_DEBUG_REGISTERS 1355 ahd_reg_print_t ahd_sgseqbcnt_print; 1356 #else 1357 #define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \ 1358 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap) 1359 #endif 1360 1361 #if AIC_DEBUG_REGISTERS 1362 ahd_reg_print_t ahd_slvspltoutattr1_print; 1363 #else 1364 #define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \ 1365 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap) 1366 #endif 1367 1368 #if AIC_DEBUG_REGISTERS 1369 ahd_reg_print_t ahd_slvspltoutattr2_print; 1370 #else 1371 #define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \ 1372 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap) 1373 #endif 1374 1375 #if AIC_DEBUG_REGISTERS 1376 ahd_reg_print_t ahd_sgspltstat0_print; 1377 #else 1378 #define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 1379 ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap) 1380 #endif 1381 1382 #if AIC_DEBUG_REGISTERS 1383 ahd_reg_print_t ahd_sfunct_print; 1384 #else 1385 #define ahd_sfunct_print(regvalue, cur_col, wrap) \ 1386 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 1387 #endif 1388 1389 #if AIC_DEBUG_REGISTERS 1390 ahd_reg_print_t ahd_sgspltstat1_print; 1391 #else 1392 #define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \ 1393 ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap) 1394 #endif 1395 1396 #if AIC_DEBUG_REGISTERS 1397 ahd_reg_print_t ahd_df0pcistat_print; 1398 #else 1399 #define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 1400 ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap) 1401 #endif 1402 1403 #if AIC_DEBUG_REGISTERS 1404 ahd_reg_print_t ahd_reg0_print; 1405 #else 1406 #define ahd_reg0_print(regvalue, cur_col, wrap) \ 1407 ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap) 1408 #endif 1409 1410 #if AIC_DEBUG_REGISTERS 1411 ahd_reg_print_t ahd_df1pcistat_print; 1412 #else 1413 #define ahd_df1pcistat_print(regvalue, cur_col, wrap) \ 1414 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap) 1415 #endif 1416 1417 #if AIC_DEBUG_REGISTERS 1418 ahd_reg_print_t ahd_sgpcistat_print; 1419 #else 1420 #define ahd_sgpcistat_print(regvalue, cur_col, wrap) \ 1421 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap) 1422 #endif 1423 1424 #if AIC_DEBUG_REGISTERS 1425 ahd_reg_print_t ahd_reg1_print; 1426 #else 1427 #define ahd_reg1_print(regvalue, cur_col, wrap) \ 1428 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap) 1429 #endif 1430 1431 #if AIC_DEBUG_REGISTERS 1432 ahd_reg_print_t ahd_cmcpcistat_print; 1433 #else 1434 #define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \ 1435 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap) 1436 #endif 1437 1438 #if AIC_DEBUG_REGISTERS 1439 ahd_reg_print_t ahd_ovlypcistat_print; 1440 #else 1441 #define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \ 1442 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap) 1443 #endif 1444 1445 #if AIC_DEBUG_REGISTERS 1446 ahd_reg_print_t ahd_reg_isr_print; 1447 #else 1448 #define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 1449 ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap) 1450 #endif 1451 1452 #if AIC_DEBUG_REGISTERS 1453 ahd_reg_print_t ahd_msipcistat_print; 1454 #else 1455 #define ahd_msipcistat_print(regvalue, cur_col, wrap) \ 1456 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap) 1457 #endif 1458 1459 #if AIC_DEBUG_REGISTERS 1460 ahd_reg_print_t ahd_sg_state_print; 1461 #else 1462 #define ahd_sg_state_print(regvalue, cur_col, wrap) \ 1463 ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap) 1464 #endif 1465 1466 #if AIC_DEBUG_REGISTERS 1467 ahd_reg_print_t ahd_targpcistat_print; 1468 #else 1469 #define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 1470 ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap) 1471 #endif 1472 1473 #if AIC_DEBUG_REGISTERS 1474 ahd_reg_print_t ahd_data_count_odd_print; 1475 #else 1476 #define ahd_data_count_odd_print(regvalue, cur_col, wrap) \ 1477 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap) 1478 #endif 1479 1480 #if AIC_DEBUG_REGISTERS 1481 ahd_reg_print_t ahd_scbptr_print; 1482 #else 1483 #define ahd_scbptr_print(regvalue, cur_col, wrap) \ 1484 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap) 1485 #endif 1486 1487 #if AIC_DEBUG_REGISTERS 1488 ahd_reg_print_t ahd_ccscbacnt_print; 1489 #else 1490 #define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \ 1491 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap) 1492 #endif 1493 1494 #if AIC_DEBUG_REGISTERS 1495 ahd_reg_print_t ahd_scbautoptr_print; 1496 #else 1497 #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 1498 ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap) 1499 #endif 1500 1501 #if AIC_DEBUG_REGISTERS 1502 ahd_reg_print_t ahd_ccscbadr_bk_print; 1503 #else 1504 #define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \ 1505 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap) 1506 #endif 1507 1508 #if AIC_DEBUG_REGISTERS 1509 ahd_reg_print_t ahd_ccsgaddr_print; 1510 #else 1511 #define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \ 1512 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap) 1513 #endif 1514 1515 #if AIC_DEBUG_REGISTERS 1516 ahd_reg_print_t ahd_ccscbaddr_print; 1517 #else 1518 #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 1519 ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap) 1520 #endif 1521 1522 #if AIC_DEBUG_REGISTERS 1523 ahd_reg_print_t ahd_ccscbctl_print; 1524 #else 1525 #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 1526 ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap) 1527 #endif 1528 1529 #if AIC_DEBUG_REGISTERS 1530 ahd_reg_print_t ahd_ccsgctl_print; 1531 #else 1532 #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \ 1533 ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap) 1534 #endif 1535 1536 #if AIC_DEBUG_REGISTERS 1537 ahd_reg_print_t ahd_cmc_rambist_print; 1538 #else 1539 #define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \ 1540 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap) 1541 #endif 1542 1543 #if AIC_DEBUG_REGISTERS 1544 ahd_reg_print_t ahd_ccsgram_print; 1545 #else 1546 #define ahd_ccsgram_print(regvalue, cur_col, wrap) \ 1547 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap) 1548 #endif 1549 1550 #if AIC_DEBUG_REGISTERS 1551 ahd_reg_print_t ahd_ccscbram_print; 1552 #else 1553 #define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 1554 ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap) 1555 #endif 1556 1557 #if AIC_DEBUG_REGISTERS 1558 ahd_reg_print_t ahd_flexadr_print; 1559 #else 1560 #define ahd_flexadr_print(regvalue, cur_col, wrap) \ 1561 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap) 1562 #endif 1563 1564 #if AIC_DEBUG_REGISTERS 1565 ahd_reg_print_t ahd_flexcnt_print; 1566 #else 1567 #define ahd_flexcnt_print(regvalue, cur_col, wrap) \ 1568 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap) 1569 #endif 1570 1571 #if AIC_DEBUG_REGISTERS 1572 ahd_reg_print_t ahd_flexdmastat_print; 1573 #else 1574 #define ahd_flexdmastat_print(regvalue, cur_col, wrap) \ 1575 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap) 1576 #endif 1577 1578 #if AIC_DEBUG_REGISTERS 1579 ahd_reg_print_t ahd_flexdata_print; 1580 #else 1581 #define ahd_flexdata_print(regvalue, cur_col, wrap) \ 1582 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap) 1583 #endif 1584 1585 #if AIC_DEBUG_REGISTERS 1586 ahd_reg_print_t ahd_brddat_print; 1587 #else 1588 #define ahd_brddat_print(regvalue, cur_col, wrap) \ 1589 ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap) 1590 #endif 1591 1592 #if AIC_DEBUG_REGISTERS 1593 ahd_reg_print_t ahd_brdctl_print; 1594 #else 1595 #define ahd_brdctl_print(regvalue, cur_col, wrap) \ 1596 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap) 1597 #endif 1598 1599 #if AIC_DEBUG_REGISTERS 1600 ahd_reg_print_t ahd_seeadr_print; 1601 #else 1602 #define ahd_seeadr_print(regvalue, cur_col, wrap) \ 1603 ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap) 1604 #endif 1605 1606 #if AIC_DEBUG_REGISTERS 1607 ahd_reg_print_t ahd_seedat_print; 1608 #else 1609 #define ahd_seedat_print(regvalue, cur_col, wrap) \ 1610 ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap) 1611 #endif 1612 1613 #if AIC_DEBUG_REGISTERS 1614 ahd_reg_print_t ahd_seectl_print; 1615 #else 1616 #define ahd_seectl_print(regvalue, cur_col, wrap) \ 1617 ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap) 1618 #endif 1619 1620 #if AIC_DEBUG_REGISTERS 1621 ahd_reg_print_t ahd_seestat_print; 1622 #else 1623 #define ahd_seestat_print(regvalue, cur_col, wrap) \ 1624 ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap) 1625 #endif 1626 1627 #if AIC_DEBUG_REGISTERS 1628 ahd_reg_print_t ahd_scbcnt_print; 1629 #else 1630 #define ahd_scbcnt_print(regvalue, cur_col, wrap) \ 1631 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap) 1632 #endif 1633 1634 #if AIC_DEBUG_REGISTERS 1635 ahd_reg_print_t ahd_dspfltrctl_print; 1636 #else 1637 #define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \ 1638 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap) 1639 #endif 1640 1641 #if AIC_DEBUG_REGISTERS 1642 ahd_reg_print_t ahd_dfwaddr_print; 1643 #else 1644 #define ahd_dfwaddr_print(regvalue, cur_col, wrap) \ 1645 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap) 1646 #endif 1647 1648 #if AIC_DEBUG_REGISTERS 1649 ahd_reg_print_t ahd_dspdatactl_print; 1650 #else 1651 #define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 1652 ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap) 1653 #endif 1654 1655 #if AIC_DEBUG_REGISTERS 1656 ahd_reg_print_t ahd_dspreqctl_print; 1657 #else 1658 #define ahd_dspreqctl_print(regvalue, cur_col, wrap) \ 1659 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap) 1660 #endif 1661 1662 #if AIC_DEBUG_REGISTERS 1663 ahd_reg_print_t ahd_dfraddr_print; 1664 #else 1665 #define ahd_dfraddr_print(regvalue, cur_col, wrap) \ 1666 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap) 1667 #endif 1668 1669 #if AIC_DEBUG_REGISTERS 1670 ahd_reg_print_t ahd_dspackctl_print; 1671 #else 1672 #define ahd_dspackctl_print(regvalue, cur_col, wrap) \ 1673 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap) 1674 #endif 1675 1676 #if AIC_DEBUG_REGISTERS 1677 ahd_reg_print_t ahd_dfdat_print; 1678 #else 1679 #define ahd_dfdat_print(regvalue, cur_col, wrap) \ 1680 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap) 1681 #endif 1682 1683 #if AIC_DEBUG_REGISTERS 1684 ahd_reg_print_t ahd_dspselect_print; 1685 #else 1686 #define ahd_dspselect_print(regvalue, cur_col, wrap) \ 1687 ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap) 1688 #endif 1689 1690 #if AIC_DEBUG_REGISTERS 1691 ahd_reg_print_t ahd_wrtbiasctl_print; 1692 #else 1693 #define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \ 1694 ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap) 1695 #endif 1696 1697 #if AIC_DEBUG_REGISTERS 1698 ahd_reg_print_t ahd_rcvrbiosctl_print; 1699 #else 1700 #define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \ 1701 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap) 1702 #endif 1703 1704 #if AIC_DEBUG_REGISTERS 1705 ahd_reg_print_t ahd_wrtbiascalc_print; 1706 #else 1707 #define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \ 1708 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap) 1709 #endif 1710 1711 #if AIC_DEBUG_REGISTERS 1712 ahd_reg_print_t ahd_dfptrs_print; 1713 #else 1714 #define ahd_dfptrs_print(regvalue, cur_col, wrap) \ 1715 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap) 1716 #endif 1717 1718 #if AIC_DEBUG_REGISTERS 1719 ahd_reg_print_t ahd_rcvrbiascalc_print; 1720 #else 1721 #define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \ 1722 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap) 1723 #endif 1724 1725 #if AIC_DEBUG_REGISTERS 1726 ahd_reg_print_t ahd_dfbkptr_print; 1727 #else 1728 #define ahd_dfbkptr_print(regvalue, cur_col, wrap) \ 1729 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap) 1730 #endif 1731 1732 #if AIC_DEBUG_REGISTERS 1733 ahd_reg_print_t ahd_skewcalc_print; 1734 #else 1735 #define ahd_skewcalc_print(regvalue, cur_col, wrap) \ 1736 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap) 1737 #endif 1738 1739 #if AIC_DEBUG_REGISTERS 1740 ahd_reg_print_t ahd_dfdbctl_print; 1741 #else 1742 #define ahd_dfdbctl_print(regvalue, cur_col, wrap) \ 1743 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap) 1744 #endif 1745 1746 #if AIC_DEBUG_REGISTERS 1747 ahd_reg_print_t ahd_dfscnt_print; 1748 #else 1749 #define ahd_dfscnt_print(regvalue, cur_col, wrap) \ 1750 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap) 1751 #endif 1752 1753 #if AIC_DEBUG_REGISTERS 1754 ahd_reg_print_t ahd_dfbcnt_print; 1755 #else 1756 #define ahd_dfbcnt_print(regvalue, cur_col, wrap) \ 1757 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap) 1758 #endif 1759 1760 #if AIC_DEBUG_REGISTERS 1761 ahd_reg_print_t ahd_ovlyaddr_print; 1762 #else 1763 #define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \ 1764 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap) 1765 #endif 1766 1767 #if AIC_DEBUG_REGISTERS 1768 ahd_reg_print_t ahd_seqctl0_print; 1769 #else 1770 #define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 1771 ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap) 1772 #endif 1773 1774 #if AIC_DEBUG_REGISTERS 1775 ahd_reg_print_t ahd_seqctl1_print; 1776 #else 1777 #define ahd_seqctl1_print(regvalue, cur_col, wrap) \ 1778 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap) 1779 #endif 1780 1781 #if AIC_DEBUG_REGISTERS 1782 ahd_reg_print_t ahd_flags_print; 1783 #else 1784 #define ahd_flags_print(regvalue, cur_col, wrap) \ 1785 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap) 1786 #endif 1787 1788 #if AIC_DEBUG_REGISTERS 1789 ahd_reg_print_t ahd_seqintctl_print; 1790 #else 1791 #define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 1792 ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap) 1793 #endif 1794 1795 #if AIC_DEBUG_REGISTERS 1796 ahd_reg_print_t ahd_seqram_print; 1797 #else 1798 #define ahd_seqram_print(regvalue, cur_col, wrap) \ 1799 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap) 1800 #endif 1801 1802 #if AIC_DEBUG_REGISTERS 1803 ahd_reg_print_t ahd_prgmcnt_print; 1804 #else 1805 #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 1806 ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap) 1807 #endif 1808 1809 #if AIC_DEBUG_REGISTERS 1810 ahd_reg_print_t ahd_accum_print; 1811 #else 1812 #define ahd_accum_print(regvalue, cur_col, wrap) \ 1813 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap) 1814 #endif 1815 1816 #if AIC_DEBUG_REGISTERS 1817 ahd_reg_print_t ahd_sindex_print; 1818 #else 1819 #define ahd_sindex_print(regvalue, cur_col, wrap) \ 1820 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap) 1821 #endif 1822 1823 #if AIC_DEBUG_REGISTERS 1824 ahd_reg_print_t ahd_dindex_print; 1825 #else 1826 #define ahd_dindex_print(regvalue, cur_col, wrap) \ 1827 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap) 1828 #endif 1829 1830 #if AIC_DEBUG_REGISTERS 1831 ahd_reg_print_t ahd_brkaddr1_print; 1832 #else 1833 #define ahd_brkaddr1_print(regvalue, cur_col, wrap) \ 1834 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap) 1835 #endif 1836 1837 #if AIC_DEBUG_REGISTERS 1838 ahd_reg_print_t ahd_brkaddr0_print; 1839 #else 1840 #define ahd_brkaddr0_print(regvalue, cur_col, wrap) \ 1841 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap) 1842 #endif 1843 1844 #if AIC_DEBUG_REGISTERS 1845 ahd_reg_print_t ahd_allones_print; 1846 #else 1847 #define ahd_allones_print(regvalue, cur_col, wrap) \ 1848 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap) 1849 #endif 1850 1851 #if AIC_DEBUG_REGISTERS 1852 ahd_reg_print_t ahd_none_print; 1853 #else 1854 #define ahd_none_print(regvalue, cur_col, wrap) \ 1855 ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap) 1856 #endif 1857 1858 #if AIC_DEBUG_REGISTERS 1859 ahd_reg_print_t ahd_allzeros_print; 1860 #else 1861 #define ahd_allzeros_print(regvalue, cur_col, wrap) \ 1862 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap) 1863 #endif 1864 1865 #if AIC_DEBUG_REGISTERS 1866 ahd_reg_print_t ahd_sindir_print; 1867 #else 1868 #define ahd_sindir_print(regvalue, cur_col, wrap) \ 1869 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap) 1870 #endif 1871 1872 #if AIC_DEBUG_REGISTERS 1873 ahd_reg_print_t ahd_dindir_print; 1874 #else 1875 #define ahd_dindir_print(regvalue, cur_col, wrap) \ 1876 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap) 1877 #endif 1878 1879 #if AIC_DEBUG_REGISTERS 1880 ahd_reg_print_t ahd_function1_print; 1881 #else 1882 #define ahd_function1_print(regvalue, cur_col, wrap) \ 1883 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap) 1884 #endif 1885 1886 #if AIC_DEBUG_REGISTERS 1887 ahd_reg_print_t ahd_stack_print; 1888 #else 1889 #define ahd_stack_print(regvalue, cur_col, wrap) \ 1890 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap) 1891 #endif 1892 1893 #if AIC_DEBUG_REGISTERS 1894 ahd_reg_print_t ahd_intvec1_addr_print; 1895 #else 1896 #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 1897 ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap) 1898 #endif 1899 1900 #if AIC_DEBUG_REGISTERS 1901 ahd_reg_print_t ahd_curaddr_print; 1902 #else 1903 #define ahd_curaddr_print(regvalue, cur_col, wrap) \ 1904 ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap) 1905 #endif 1906 1907 #if AIC_DEBUG_REGISTERS 1908 ahd_reg_print_t ahd_intvec2_addr_print; 1909 #else 1910 #define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1911 ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap) 1912 #endif 1913 1914 #if AIC_DEBUG_REGISTERS 1915 ahd_reg_print_t ahd_lastaddr_print; 1916 #else 1917 #define ahd_lastaddr_print(regvalue, cur_col, wrap) \ 1918 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap) 1919 #endif 1920 1921 #if AIC_DEBUG_REGISTERS 1922 ahd_reg_print_t ahd_longjmp_addr_print; 1923 #else 1924 #define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \ 1925 ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap) 1926 #endif 1927 1928 #if AIC_DEBUG_REGISTERS 1929 ahd_reg_print_t ahd_accum_save_print; 1930 #else 1931 #define ahd_accum_save_print(regvalue, cur_col, wrap) \ 1932 ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap) 1933 #endif 1934 1935 #if AIC_DEBUG_REGISTERS 1936 ahd_reg_print_t ahd_sram_base_print; 1937 #else 1938 #define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1939 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1940 #endif 1941 1942 #if AIC_DEBUG_REGISTERS 1943 ahd_reg_print_t ahd_waiting_scb_tails_print; 1944 #else 1945 #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 1946 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 1947 #endif 1948 1949 #if AIC_DEBUG_REGISTERS 1950 ahd_reg_print_t ahd_ahd_pci_config_base_print; 1951 #else 1952 #define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1953 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1954 #endif 1955 1956 #if AIC_DEBUG_REGISTERS 1957 ahd_reg_print_t ahd_waiting_tid_head_print; 1958 #else 1959 #define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \ 1960 ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap) 1961 #endif 1962 1963 #if AIC_DEBUG_REGISTERS 1964 ahd_reg_print_t ahd_waiting_tid_tail_print; 1965 #else 1966 #define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \ 1967 ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap) 1968 #endif 1969 1970 #if AIC_DEBUG_REGISTERS 1971 ahd_reg_print_t ahd_next_queued_scb_addr_print; 1972 #else 1973 #define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \ 1974 ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap) 1975 #endif 1976 1977 #if AIC_DEBUG_REGISTERS 1978 ahd_reg_print_t ahd_complete_scb_head_print; 1979 #else 1980 #define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \ 1981 ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap) 1982 #endif 1983 1984 #if AIC_DEBUG_REGISTERS 1985 ahd_reg_print_t ahd_complete_scb_dmainprog_head_print; 1986 #else 1987 #define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \ 1988 ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap) 1989 #endif 1990 1991 #if AIC_DEBUG_REGISTERS 1992 ahd_reg_print_t ahd_complete_dma_scb_head_print; 1993 #else 1994 #define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \ 1995 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap) 1996 #endif 1997 1998 #if AIC_DEBUG_REGISTERS 1999 ahd_reg_print_t ahd_complete_dma_scb_tail_print; 2000 #else 2001 #define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \ 2002 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap) 2003 #endif 2004 2005 #if AIC_DEBUG_REGISTERS 2006 ahd_reg_print_t ahd_complete_on_qfreeze_head_print; 2007 #else 2008 #define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \ 2009 ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap) 2010 #endif 2011 2012 #if AIC_DEBUG_REGISTERS 2013 ahd_reg_print_t ahd_qfreeze_count_print; 2014 #else 2015 #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \ 2016 ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap) 2017 #endif 2018 2019 #if AIC_DEBUG_REGISTERS 2020 ahd_reg_print_t ahd_kernel_qfreeze_count_print; 2021 #else 2022 #define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \ 2023 ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap) 2024 #endif 2025 2026 #if AIC_DEBUG_REGISTERS 2027 ahd_reg_print_t ahd_saved_mode_print; 2028 #else 2029 #define ahd_saved_mode_print(regvalue, cur_col, wrap) \ 2030 ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap) 2031 #endif 2032 2033 #if AIC_DEBUG_REGISTERS 2034 ahd_reg_print_t ahd_msg_out_print; 2035 #else 2036 #define ahd_msg_out_print(regvalue, cur_col, wrap) \ 2037 ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap) 2038 #endif 2039 2040 #if AIC_DEBUG_REGISTERS 2041 ahd_reg_print_t ahd_dmaparams_print; 2042 #else 2043 #define ahd_dmaparams_print(regvalue, cur_col, wrap) \ 2044 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap) 2045 #endif 2046 2047 #if AIC_DEBUG_REGISTERS 2048 ahd_reg_print_t ahd_seq_flags_print; 2049 #else 2050 #define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 2051 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap) 2052 #endif 2053 2054 #if AIC_DEBUG_REGISTERS 2055 ahd_reg_print_t ahd_saved_scsiid_print; 2056 #else 2057 #define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \ 2058 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap) 2059 #endif 2060 2061 #if AIC_DEBUG_REGISTERS 2062 ahd_reg_print_t ahd_saved_lun_print; 2063 #else 2064 #define ahd_saved_lun_print(regvalue, cur_col, wrap) \ 2065 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap) 2066 #endif 2067 2068 #if AIC_DEBUG_REGISTERS 2069 ahd_reg_print_t ahd_lastphase_print; 2070 #else 2071 #define ahd_lastphase_print(regvalue, cur_col, wrap) \ 2072 ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap) 2073 #endif 2074 2075 #if AIC_DEBUG_REGISTERS 2076 ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print; 2077 #else 2078 #define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \ 2079 ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap) 2080 #endif 2081 2082 #if AIC_DEBUG_REGISTERS 2083 ahd_reg_print_t ahd_kernel_tqinpos_print; 2084 #else 2085 #define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 2086 ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap) 2087 #endif 2088 2089 #if AIC_DEBUG_REGISTERS 2090 ahd_reg_print_t ahd_tqinpos_print; 2091 #else 2092 #define ahd_tqinpos_print(regvalue, cur_col, wrap) \ 2093 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap) 2094 #endif 2095 2096 #if AIC_DEBUG_REGISTERS 2097 ahd_reg_print_t ahd_shared_data_addr_print; 2098 #else 2099 #define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \ 2100 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap) 2101 #endif 2102 2103 #if AIC_DEBUG_REGISTERS 2104 ahd_reg_print_t ahd_qoutfifo_next_addr_print; 2105 #else 2106 #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 2107 ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap) 2108 #endif 2109 2110 #if AIC_DEBUG_REGISTERS 2111 ahd_reg_print_t ahd_arg_1_print; 2112 #else 2113 #define ahd_arg_1_print(regvalue, cur_col, wrap) \ 2114 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap) 2115 #endif 2116 2117 #if AIC_DEBUG_REGISTERS 2118 ahd_reg_print_t ahd_arg_2_print; 2119 #else 2120 #define ahd_arg_2_print(regvalue, cur_col, wrap) \ 2121 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap) 2122 #endif 2123 2124 #if AIC_DEBUG_REGISTERS 2125 ahd_reg_print_t ahd_last_msg_print; 2126 #else 2127 #define ahd_last_msg_print(regvalue, cur_col, wrap) \ 2128 ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap) 2129 #endif 2130 2131 #if AIC_DEBUG_REGISTERS 2132 ahd_reg_print_t ahd_scsiseq_template_print; 2133 #else 2134 #define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \ 2135 ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap) 2136 #endif 2137 2138 #if AIC_DEBUG_REGISTERS 2139 ahd_reg_print_t ahd_initiator_tag_print; 2140 #else 2141 #define ahd_initiator_tag_print(regvalue, cur_col, wrap) \ 2142 ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap) 2143 #endif 2144 2145 #if AIC_DEBUG_REGISTERS 2146 ahd_reg_print_t ahd_seq_flags2_print; 2147 #else 2148 #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \ 2149 ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap) 2150 #endif 2151 2152 #if AIC_DEBUG_REGISTERS 2153 ahd_reg_print_t ahd_allocfifo_scbptr_print; 2154 #else 2155 #define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \ 2156 ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap) 2157 #endif 2158 2159 #if AIC_DEBUG_REGISTERS 2160 ahd_reg_print_t ahd_int_coalescing_timer_print; 2161 #else 2162 #define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \ 2163 ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap) 2164 #endif 2165 2166 #if AIC_DEBUG_REGISTERS 2167 ahd_reg_print_t ahd_int_coalescing_maxcmds_print; 2168 #else 2169 #define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \ 2170 ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap) 2171 #endif 2172 2173 #if AIC_DEBUG_REGISTERS 2174 ahd_reg_print_t ahd_int_coalescing_mincmds_print; 2175 #else 2176 #define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \ 2177 ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap) 2178 #endif 2179 2180 #if AIC_DEBUG_REGISTERS 2181 ahd_reg_print_t ahd_cmds_pending_print; 2182 #else 2183 #define ahd_cmds_pending_print(regvalue, cur_col, wrap) \ 2184 ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap) 2185 #endif 2186 2187 #if AIC_DEBUG_REGISTERS 2188 ahd_reg_print_t ahd_int_coalescing_cmdcount_print; 2189 #else 2190 #define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \ 2191 ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap) 2192 #endif 2193 2194 #if AIC_DEBUG_REGISTERS 2195 ahd_reg_print_t ahd_local_hs_mailbox_print; 2196 #else 2197 #define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \ 2198 ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap) 2199 #endif 2200 2201 #if AIC_DEBUG_REGISTERS 2202 ahd_reg_print_t ahd_cmdsize_table_print; 2203 #else 2204 #define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \ 2205 ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap) 2206 #endif 2207 2208 #if AIC_DEBUG_REGISTERS 2209 ahd_reg_print_t ahd_mk_message_scb_print; 2210 #else 2211 #define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \ 2212 ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap) 2213 #endif 2214 2215 #if AIC_DEBUG_REGISTERS 2216 ahd_reg_print_t ahd_mk_message_scsiid_print; 2217 #else 2218 #define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \ 2219 ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap) 2220 #endif 2221 2222 #if AIC_DEBUG_REGISTERS 2223 ahd_reg_print_t ahd_scb_base_print; 2224 #else 2225 #define ahd_scb_base_print(regvalue, cur_col, wrap) \ 2226 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 2227 #endif 2228 2229 #if AIC_DEBUG_REGISTERS 2230 ahd_reg_print_t ahd_scb_residual_datacnt_print; 2231 #else 2232 #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 2233 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 2234 #endif 2235 2236 #if AIC_DEBUG_REGISTERS 2237 ahd_reg_print_t ahd_scb_residual_sgptr_print; 2238 #else 2239 #define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 2240 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap) 2241 #endif 2242 2243 #if AIC_DEBUG_REGISTERS 2244 ahd_reg_print_t ahd_scb_scsi_status_print; 2245 #else 2246 #define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 2247 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 2248 #endif 2249 2250 #if AIC_DEBUG_REGISTERS 2251 ahd_reg_print_t ahd_scb_target_phases_print; 2252 #else 2253 #define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \ 2254 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap) 2255 #endif 2256 2257 #if AIC_DEBUG_REGISTERS 2258 ahd_reg_print_t ahd_scb_target_data_dir_print; 2259 #else 2260 #define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 2261 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap) 2262 #endif 2263 2264 #if AIC_DEBUG_REGISTERS 2265 ahd_reg_print_t ahd_scb_target_itag_print; 2266 #else 2267 #define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \ 2268 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap) 2269 #endif 2270 2271 #if AIC_DEBUG_REGISTERS 2272 ahd_reg_print_t ahd_scb_sense_busaddr_print; 2273 #else 2274 #define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 2275 ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap) 2276 #endif 2277 2278 #if AIC_DEBUG_REGISTERS 2279 ahd_reg_print_t ahd_scb_tag_print; 2280 #else 2281 #define ahd_scb_tag_print(regvalue, cur_col, wrap) \ 2282 ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap) 2283 #endif 2284 2285 #if AIC_DEBUG_REGISTERS 2286 ahd_reg_print_t ahd_scb_control_print; 2287 #else 2288 #define ahd_scb_control_print(regvalue, cur_col, wrap) \ 2289 ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap) 2290 #endif 2291 2292 #if AIC_DEBUG_REGISTERS 2293 ahd_reg_print_t ahd_scb_scsiid_print; 2294 #else 2295 #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \ 2296 ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap) 2297 #endif 2298 2299 #if AIC_DEBUG_REGISTERS 2300 ahd_reg_print_t ahd_scb_lun_print; 2301 #else 2302 #define ahd_scb_lun_print(regvalue, cur_col, wrap) \ 2303 ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap) 2304 #endif 2305 2306 #if AIC_DEBUG_REGISTERS 2307 ahd_reg_print_t ahd_scb_task_attribute_print; 2308 #else 2309 #define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \ 2310 ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap) 2311 #endif 2312 2313 #if AIC_DEBUG_REGISTERS 2314 ahd_reg_print_t ahd_scb_cdb_len_print; 2315 #else 2316 #define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \ 2317 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap) 2318 #endif 2319 2320 #if AIC_DEBUG_REGISTERS 2321 ahd_reg_print_t ahd_scb_task_management_print; 2322 #else 2323 #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 2324 ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap) 2325 #endif 2326 2327 #if AIC_DEBUG_REGISTERS 2328 ahd_reg_print_t ahd_scb_dataptr_print; 2329 #else 2330 #define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \ 2331 ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap) 2332 #endif 2333 2334 #if AIC_DEBUG_REGISTERS 2335 ahd_reg_print_t ahd_scb_datacnt_print; 2336 #else 2337 #define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \ 2338 ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap) 2339 #endif 2340 2341 #if AIC_DEBUG_REGISTERS 2342 ahd_reg_print_t ahd_scb_sgptr_print; 2343 #else 2344 #define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \ 2345 ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap) 2346 #endif 2347 2348 #if AIC_DEBUG_REGISTERS 2349 ahd_reg_print_t ahd_scb_busaddr_print; 2350 #else 2351 #define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \ 2352 ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap) 2353 #endif 2354 2355 #if AIC_DEBUG_REGISTERS 2356 ahd_reg_print_t ahd_scb_next_print; 2357 #else 2358 #define ahd_scb_next_print(regvalue, cur_col, wrap) \ 2359 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap) 2360 #endif 2361 2362 #if AIC_DEBUG_REGISTERS 2363 ahd_reg_print_t ahd_scb_next2_print; 2364 #else 2365 #define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 2366 ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap) 2367 #endif 2368 2369 #if AIC_DEBUG_REGISTERS 2370 ahd_reg_print_t ahd_scb_spare_print; 2371 #else 2372 #define ahd_scb_spare_print(regvalue, cur_col, wrap) \ 2373 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap) 2374 #endif 2375 2376 #if AIC_DEBUG_REGISTERS 2377 ahd_reg_print_t ahd_scb_disconnected_lists_print; 2378 #else 2379 #define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 2380 ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap) 2381 #endif 2382 2383 2384 #define MODE_PTR 0x00 2385 #define DST_MODE 0x70 2386 #define SRC_MODE 0x07 2387 2388 #define INTSTAT 0x01 2389 #define INT_PEND 0xff 2390 #define HWERRINT 0x80 2391 #define BRKADRINT 0x40 2392 #define SWTMINT 0x20 2393 #define PCIINT 0x10 2394 #define SCSIINT 0x08 2395 #define SEQINT 0x04 2396 #define CMDCMPLT 0x02 2397 #define SPLTINT 0x01 2398 2399 #define SEQINTCODE 0x02 2400 #define BAD_SCB_STATUS 0x1a 2401 #define SAW_HWERR 0x19 2402 #define TRACEPOINT3 0x18 2403 #define TRACEPOINT2 0x17 2404 #define TRACEPOINT1 0x16 2405 #define TRACEPOINT0 0x15 2406 #define TASKMGMT_CMD_CMPLT_OKAY 0x14 2407 #define TASKMGMT_FUNC_COMPLETE 0x13 2408 #define ENTERING_NONPACK 0x12 2409 #define CFG4OVERRUN 0x11 2410 #define STATUS_OVERRUN 0x10 2411 #define CFG4ISTAT_INTR 0x0f 2412 #define INVALID_SEQINT 0x0e 2413 #define ILLEGAL_PHASE 0x0d 2414 #define DUMP_CARD_STATE 0x0c 2415 #define MISSED_BUSFREE 0x0b 2416 #define MKMSG_FAILED 0x0a 2417 #define DATA_OVERRUN 0x09 2418 #define BAD_STATUS 0x08 2419 #define HOST_MSG_LOOP 0x07 2420 #define PDATA_REINIT 0x06 2421 #define IGN_WIDE_RES 0x05 2422 #define NO_MATCH 0x04 2423 #define PROTO_VIOLATION 0x03 2424 #define SEND_REJECT 0x02 2425 #define BAD_PHASE 0x01 2426 #define NO_SEQINT 0x00 2427 2428 #define CLRINT 0x03 2429 #define CLRHWERRINT 0x80 2430 #define CLRBRKADRINT 0x40 2431 #define CLRSWTMINT 0x20 2432 #define CLRPCIINT 0x10 2433 #define CLRSCSIINT 0x08 2434 #define CLRSEQINT 0x04 2435 #define CLRCMDINT 0x02 2436 #define CLRSPLTINT 0x01 2437 2438 #define ERROR 0x04 2439 #define CIOPARERR 0x80 2440 #define CIOACCESFAIL 0x40 2441 #define MPARERR 0x20 2442 #define DPARERR 0x10 2443 #define SQPARERR 0x08 2444 #define ILLOPCODE 0x04 2445 #define DSCTMOUT 0x02 2446 2447 #define CLRERR 0x04 2448 #define CLRCIOPARERR 0x80 2449 #define CLRCIOACCESFAIL 0x40 2450 #define CLRMPARERR 0x20 2451 #define CLRDPARERR 0x10 2452 #define CLRSQPARERR 0x08 2453 #define CLRILLOPCODE 0x04 2454 #define CLRDSCTMOUT 0x02 2455 2456 #define HCNTRL 0x05 2457 #define SEQ_RESET 0x80 2458 #define POWRDN 0x40 2459 #define SWINT 0x10 2460 #define SWTIMER_START_B 0x08 2461 #define PAUSE 0x04 2462 #define INTEN 0x02 2463 #define CHIPRST 0x01 2464 #define CHIPRSTACK 0x01 2465 2466 #define HNSCB_QOFF 0x06 2467 2468 #define HESCB_QOFF 0x08 2469 2470 #define HS_MAILBOX 0x0b 2471 #define HOST_TQINPOS 0x80 2472 #define ENINT_COALESCE 0x40 2473 2474 #define SEQINTSTAT 0x0c 2475 #define SEQ_SWTMRTO 0x10 2476 #define SEQ_SEQINT 0x08 2477 #define SEQ_SCSIINT 0x04 2478 #define SEQ_PCIINT 0x02 2479 #define SEQ_SPLTINT 0x01 2480 2481 #define CLRSEQINTSTAT 0x0c 2482 #define CLRSEQ_SWTMRTO 0x10 2483 #define CLRSEQ_SEQINT 0x08 2484 #define CLRSEQ_SCSIINT 0x04 2485 #define CLRSEQ_PCIINT 0x02 2486 #define CLRSEQ_SPLTINT 0x01 2487 2488 #define SWTIMER 0x0e 2489 2490 #define SNSCB_QOFF 0x10 2491 2492 #define SESCB_QOFF 0x12 2493 2494 #define SDSCB_QOFF 0x14 2495 2496 #define QOFF_CTLSTA 0x16 2497 #define EMPTY_SCB_AVAIL 0x80 2498 #define NEW_SCB_AVAIL 0x40 2499 #define SDSCB_ROLLOVR 0x20 2500 #define HS_MAILBOX_ACT 0x10 2501 #define SCB_QSIZE 0x0f 2502 #define SCB_QSIZE_16384 0x0c 2503 #define SCB_QSIZE_8192 0x0b 2504 #define SCB_QSIZE_4096 0x0a 2505 #define SCB_QSIZE_2048 0x09 2506 #define SCB_QSIZE_1024 0x08 2507 #define SCB_QSIZE_512 0x07 2508 #define SCB_QSIZE_256 0x06 2509 #define SCB_QSIZE_128 0x05 2510 #define SCB_QSIZE_64 0x04 2511 #define SCB_QSIZE_32 0x03 2512 #define SCB_QSIZE_16 0x02 2513 #define SCB_QSIZE_8 0x01 2514 #define SCB_QSIZE_4 0x00 2515 2516 #define INTCTL 0x18 2517 #define SWTMINTMASK 0x80 2518 #define SWTMINTEN 0x40 2519 #define SWTIMER_START 0x20 2520 #define AUTOCLRCMDINT 0x10 2521 #define PCIINTEN 0x08 2522 #define SCSIINTEN 0x04 2523 #define SEQINTEN 0x02 2524 #define SPLTINTEN 0x01 2525 2526 #define DFCNTRL 0x19 2527 #define SCSIENWRDIS 0x40 2528 #define SCSIENACK 0x20 2529 #define DIRECTIONACK 0x04 2530 #define FIFOFLUSHACK 0x02 2531 #define DIRECTIONEN 0x01 2532 2533 #define DSCOMMAND0 0x19 2534 #define CACHETHEN 0x80 2535 #define DPARCKEN 0x40 2536 #define MPARCKEN 0x20 2537 #define EXTREQLCK 0x10 2538 #define DISABLE_TWATE 0x02 2539 #define CIOPARCKEN 0x01 2540 2541 #define DFSTATUS 0x1a 2542 #define PRELOAD_AVAIL 0x80 2543 #define PKT_PRELOAD_AVAIL 0x40 2544 #define MREQPEND 0x10 2545 #define HDONE 0x08 2546 #define DFTHRESH 0x04 2547 #define FIFOFULL 0x02 2548 #define FIFOEMP 0x01 2549 2550 #define SG_CACHE_SHADOW 0x1b 2551 #define ODD_SEG 0x04 2552 #define LAST_SEG 0x02 2553 #define LAST_SEG_DONE 0x01 2554 2555 #define SG_CACHE_PRE 0x1b 2556 2557 #define ARBCTL 0x1b 2558 #define RESET_HARB 0x80 2559 #define RETRY_SWEN 0x08 2560 #define USE_TIME 0x07 2561 2562 #define LQIN 0x20 2563 2564 #define TYPEPTR 0x20 2565 2566 #define TAGPTR 0x21 2567 2568 #define LUNPTR 0x22 2569 2570 #define DATALENPTR 0x23 2571 2572 #define STATLENPTR 0x24 2573 2574 #define CMDLENPTR 0x25 2575 2576 #define ATTRPTR 0x26 2577 2578 #define FLAGPTR 0x27 2579 2580 #define CMDPTR 0x28 2581 2582 #define QNEXTPTR 0x29 2583 2584 #define IDPTR 0x2a 2585 2586 #define ABRTBYTEPTR 0x2b 2587 2588 #define ABRTBITPTR 0x2c 2589 2590 #define MAXCMDBYTES 0x2d 2591 2592 #define MAXCMD2RCV 0x2e 2593 2594 #define SHORTTHRESH 0x2f 2595 2596 #define LUNLEN 0x30 2597 #define TLUNLEN 0xf0 2598 #define ILUNLEN 0x0f 2599 2600 #define CDBLIMIT 0x31 2601 2602 #define MAXCMD 0x32 2603 2604 #define MAXCMDCNT 0x33 2605 2606 #define LQRSVD01 0x34 2607 2608 #define LQRSVD16 0x35 2609 2610 #define LQRSVD17 0x36 2611 2612 #define CMDRSVD0 0x37 2613 2614 #define LQCTL0 0x38 2615 #define LQITARGCLT 0xc0 2616 #define LQIINITGCLT 0x30 2617 #define LQ0TARGCLT 0x0c 2618 #define LQ0INITGCLT 0x03 2619 2620 #define LQCTL1 0x38 2621 #define PCI2PCI 0x04 2622 #define SINGLECMD 0x02 2623 #define ABORTPENDING 0x01 2624 2625 #define LQCTL2 0x39 2626 #define LQIRETRY 0x80 2627 #define LQICONTINUE 0x40 2628 #define LQITOIDLE 0x20 2629 #define LQIPAUSE 0x10 2630 #define LQORETRY 0x08 2631 #define LQOCONTINUE 0x04 2632 #define LQOTOIDLE 0x02 2633 #define LQOPAUSE 0x01 2634 2635 #define SCSBIST0 0x39 2636 #define GSBISTERR 0x40 2637 #define GSBISTDONE 0x20 2638 #define GSBISTRUN 0x10 2639 #define OSBISTERR 0x04 2640 #define OSBISTDONE 0x02 2641 #define OSBISTRUN 0x01 2642 2643 #define SCSISEQ0 0x3a 2644 #define TEMODEO 0x80 2645 #define ENSELO 0x40 2646 #define ENARBO 0x20 2647 #define FORCEBUSFREE 0x10 2648 #define SCSIRSTO 0x01 2649 2650 #define SCSBIST1 0x3a 2651 #define NTBISTERR 0x04 2652 #define NTBISTDONE 0x02 2653 #define NTBISTRUN 0x01 2654 2655 #define SCSISEQ1 0x3b 2656 2657 #define BUSINITID 0x3c 2658 2659 #define SXFRCTL0 0x3c 2660 #define DFON 0x80 2661 #define DFPEXP 0x40 2662 #define BIOSCANCELEN 0x10 2663 #define SPIOEN 0x08 2664 2665 #define DLCOUNT 0x3c 2666 2667 #define SXFRCTL1 0x3d 2668 #define BITBUCKET 0x80 2669 #define ENSACHK 0x40 2670 #define ENSPCHK 0x20 2671 #define STIMESEL 0x18 2672 #define ENSTIMER 0x04 2673 #define ACTNEGEN 0x02 2674 #define STPWEN 0x01 2675 2676 #define BUSTARGID 0x3e 2677 2678 #define SXFRCTL2 0x3e 2679 #define AUTORSTDIS 0x10 2680 #define CMDDMAEN 0x08 2681 #define ASU 0x07 2682 2683 #define DFFSTAT 0x3f 2684 #define CURRFIFO 0x03 2685 #define FIFO1FREE 0x20 2686 #define FIFO0FREE 0x10 2687 #define CURRFIFO_NONE 0x03 2688 #define CURRFIFO_1 0x01 2689 #define CURRFIFO_0 0x00 2690 2691 #define SCSISIGO 0x40 2692 #define CDO 0x80 2693 #define IOO 0x40 2694 #define MSGO 0x20 2695 #define ATNO 0x10 2696 #define SELO 0x08 2697 #define BSYO 0x04 2698 #define REQO 0x02 2699 #define ACKO 0x01 2700 2701 #define MULTARGID 0x40 2702 2703 #define SCSISIGI 0x41 2704 #define ATNI 0x10 2705 #define SELI 0x08 2706 #define BSYI 0x04 2707 #define REQI 0x02 2708 #define ACKI 0x01 2709 2710 #define SCSIPHASE 0x42 2711 #define STATUS_PHASE 0x20 2712 #define COMMAND_PHASE 0x10 2713 #define MSG_IN_PHASE 0x08 2714 #define MSG_OUT_PHASE 0x04 2715 #define DATA_PHASE_MASK 0x03 2716 #define DATA_IN_PHASE 0x02 2717 #define DATA_OUT_PHASE 0x01 2718 2719 #define SCSIDAT0_IMG 0x43 2720 2721 #define SCSIDAT 0x44 2722 2723 #define SCSIBUS 0x46 2724 2725 #define TARGIDIN 0x48 2726 #define CLKOUT 0x80 2727 #define TARGID 0x0f 2728 2729 #define SELID 0x49 2730 #define SELID_MASK 0xf0 2731 #define ONEBIT 0x08 2732 2733 #define OPTIONMODE 0x4a 2734 #define OPTIONMODE_DEFAULTS 0x02 2735 #define BIOSCANCTL 0x80 2736 #define AUTOACKEN 0x40 2737 #define BIASCANCTL 0x20 2738 #define BUSFREEREV 0x10 2739 #define ENDGFORMCHK 0x04 2740 #define AUTO_MSGOUT_DE 0x02 2741 2742 #define SBLKCTL 0x4a 2743 #define DIAGLEDEN 0x80 2744 #define DIAGLEDON 0x40 2745 #define ENAB40 0x08 2746 #define ENAB20 0x04 2747 #define SELWIDE 0x02 2748 2749 #define SIMODE0 0x4b 2750 #define ENSELDO 0x40 2751 #define ENSELDI 0x20 2752 #define ENSELINGO 0x10 2753 #define ENIOERR 0x08 2754 #define ENOVERRUN 0x04 2755 #define ENSPIORDY 0x02 2756 #define ENARBDO 0x01 2757 2758 #define SSTAT0 0x4b 2759 #define TARGET 0x80 2760 #define SELDO 0x40 2761 #define SELDI 0x20 2762 #define SELINGO 0x10 2763 #define IOERR 0x08 2764 #define OVERRUN 0x04 2765 #define SPIORDY 0x02 2766 #define ARBDO 0x01 2767 2768 #define CLRSINT0 0x4b 2769 #define CLRSELDO 0x40 2770 #define CLRSELDI 0x20 2771 #define CLRSELINGO 0x10 2772 #define CLRIOERR 0x08 2773 #define CLROVERRUN 0x04 2774 #define CLRSPIORDY 0x02 2775 #define CLRARBDO 0x01 2776 2777 #define SSTAT1 0x4c 2778 #define SELTO 0x80 2779 #define ATNTARG 0x40 2780 #define SCSIRSTI 0x20 2781 #define PHASEMIS 0x10 2782 #define BUSFREE 0x08 2783 #define SCSIPERR 0x04 2784 #define STRB2FAST 0x02 2785 #define REQINIT 0x01 2786 2787 #define CLRSINT1 0x4c 2788 #define CLRSELTIMEO 0x80 2789 #define CLRATNO 0x40 2790 #define CLRSCSIRSTI 0x20 2791 #define CLRBUSFREE 0x08 2792 #define CLRSCSIPERR 0x04 2793 #define CLRSTRB2FAST 0x02 2794 #define CLRREQINIT 0x01 2795 2796 #define SSTAT2 0x4d 2797 #define BUSFREETIME 0xc0 2798 #define NONPACKREQ 0x20 2799 #define EXP_ACTIVE 0x10 2800 #define BSYX 0x08 2801 #define WIDE_RES 0x04 2802 #define SDONE 0x02 2803 #define DMADONE 0x01 2804 #define BUSFREE_DFF1 0xc0 2805 #define BUSFREE_DFF0 0x80 2806 #define BUSFREE_LQO 0x40 2807 2808 #define CLRSINT2 0x4d 2809 #define CLRNONPACKREQ 0x20 2810 #define CLRWIDE_RES 0x04 2811 #define CLRSDONE 0x02 2812 #define CLRDMADONE 0x01 2813 2814 #define SIMODE2 0x4d 2815 #define ENWIDE_RES 0x04 2816 #define ENSDONE 0x02 2817 #define ENDMADONE 0x01 2818 2819 #define PERRDIAG 0x4e 2820 #define HIZERO 0x80 2821 #define HIPERR 0x40 2822 #define PREVPHASE 0x20 2823 #define PARITYERR 0x10 2824 #define AIPERR 0x08 2825 #define CRCERR 0x04 2826 #define DGFORMERR 0x02 2827 #define DTERR 0x01 2828 2829 #define LQISTATE 0x4e 2830 2831 #define SOFFCNT 0x4f 2832 2833 #define LQOSTATE 0x4f 2834 2835 #define LQISTAT0 0x50 2836 #define LQIATNQAS 0x20 2837 #define LQICRCT1 0x10 2838 #define LQICRCT2 0x08 2839 #define LQIBADLQT 0x04 2840 #define LQIATNLQ 0x02 2841 #define LQIATNCMD 0x01 2842 2843 #define CLRLQIINT0 0x50 2844 #define CLRLQIATNQAS 0x20 2845 #define CLRLQICRCT1 0x10 2846 #define CLRLQICRCT2 0x08 2847 #define CLRLQIBADLQT 0x04 2848 #define CLRLQIATNLQ 0x02 2849 #define CLRLQIATNCMD 0x01 2850 2851 #define LQIMODE0 0x50 2852 #define ENLQIATNQASK 0x20 2853 #define ENLQICRCT1 0x10 2854 #define ENLQICRCT2 0x08 2855 #define ENLQIBADLQT 0x04 2856 #define ENLQIATNLQ 0x02 2857 #define ENLQIATNCMD 0x01 2858 2859 #define LQISTAT1 0x51 2860 #define LQIPHASE_LQ 0x80 2861 #define LQIPHASE_NLQ 0x40 2862 #define LQIABORT 0x20 2863 #define LQICRCI_LQ 0x10 2864 #define LQICRCI_NLQ 0x08 2865 #define LQIBADLQI 0x04 2866 #define LQIOVERI_LQ 0x02 2867 #define LQIOVERI_NLQ 0x01 2868 2869 #define CLRLQIINT1 0x51 2870 #define CLRLQIPHASE_LQ 0x80 2871 #define CLRLQIPHASE_NLQ 0x40 2872 #define CLRLIQABORT 0x20 2873 #define CLRLQICRCI_LQ 0x10 2874 #define CLRLQICRCI_NLQ 0x08 2875 #define CLRLQIBADLQI 0x04 2876 #define CLRLQIOVERI_LQ 0x02 2877 #define CLRLQIOVERI_NLQ 0x01 2878 2879 #define LQIMODE1 0x51 2880 #define ENLQIPHASE_LQ 0x80 2881 #define ENLQIPHASE_NLQ 0x40 2882 #define ENLIQABORT 0x20 2883 #define ENLQICRCI_LQ 0x10 2884 #define ENLQICRCI_NLQ 0x08 2885 #define ENLQIBADLQI 0x04 2886 #define ENLQIOVERI_LQ 0x02 2887 #define ENLQIOVERI_NLQ 0x01 2888 2889 #define LQISTAT2 0x52 2890 #define PACKETIZED 0x80 2891 #define LQIPHASE_OUTPKT 0x40 2892 #define LQIWORKONLQ 0x20 2893 #define LQIWAITFIFO 0x10 2894 #define LQISTOPPKT 0x08 2895 #define LQISTOPLQ 0x04 2896 #define LQISTOPCMD 0x02 2897 #define LQIGSAVAIL 0x01 2898 2899 #define SSTAT3 0x53 2900 #define NTRAMPERR 0x02 2901 #define OSRAMPERR 0x01 2902 2903 #define CLRSINT3 0x53 2904 #define CLRNTRAMPERR 0x02 2905 #define CLROSRAMPERR 0x01 2906 2907 #define SIMODE3 0x53 2908 #define ENNTRAMPERR 0x02 2909 #define ENOSRAMPERR 0x01 2910 2911 #define LQOMODE0 0x54 2912 #define ENLQOTARGSCBPERR 0x10 2913 #define ENLQOSTOPT2 0x08 2914 #define ENLQOATNLQ 0x04 2915 #define ENLQOATNPKT 0x02 2916 #define ENLQOTCRC 0x01 2917 2918 #define LQOSTAT0 0x54 2919 #define LQOTARGSCBPERR 0x10 2920 #define LQOSTOPT2 0x08 2921 #define LQOATNLQ 0x04 2922 #define LQOATNPKT 0x02 2923 #define LQOTCRC 0x01 2924 2925 #define CLRLQOINT0 0x54 2926 #define CLRLQOTARGSCBPERR 0x10 2927 #define CLRLQOSTOPT2 0x08 2928 #define CLRLQOATNLQ 0x04 2929 #define CLRLQOATNPKT 0x02 2930 #define CLRLQOTCRC 0x01 2931 2932 #define LQOMODE1 0x55 2933 #define ENLQOINITSCBPERR 0x10 2934 #define ENLQOSTOPI2 0x08 2935 #define ENLQOBADQAS 0x04 2936 #define ENLQOBUSFREE 0x02 2937 #define ENLQOPHACHGINPKT 0x01 2938 2939 #define LQOSTAT1 0x55 2940 #define LQOINITSCBPERR 0x10 2941 #define LQOSTOPI2 0x08 2942 #define LQOBADQAS 0x04 2943 #define LQOBUSFREE 0x02 2944 #define LQOPHACHGINPKT 0x01 2945 2946 #define CLRLQOINT1 0x55 2947 #define CLRLQOINITSCBPERR 0x10 2948 #define CLRLQOSTOPI2 0x08 2949 #define CLRLQOBADQAS 0x04 2950 #define CLRLQOBUSFREE 0x02 2951 #define CLRLQOPHACHGINPKT 0x01 2952 2953 #define OS_SPACE_CNT 0x56 2954 2955 #define LQOSTAT2 0x56 2956 #define LQOPKT 0xe0 2957 #define LQOWAITFIFO 0x10 2958 #define LQOPHACHGOUTPKT 0x02 2959 #define LQOSTOP0 0x01 2960 2961 #define SIMODE1 0x57 2962 #define ENSELTIMO 0x80 2963 #define ENATNTARG 0x40 2964 #define ENSCSIRST 0x20 2965 #define ENPHASEMIS 0x10 2966 #define ENBUSFREE 0x08 2967 #define ENSCSIPERR 0x04 2968 #define ENSTRB2FAST 0x02 2969 #define ENREQINIT 0x01 2970 2971 #define GSFIFO 0x58 2972 2973 #define DFFSXFRCTL 0x5a 2974 #define DFFBITBUCKET 0x08 2975 #define CLRSHCNT 0x04 2976 #define CLRCHN 0x02 2977 #define RSTCHN 0x01 2978 2979 #define NEXTSCB 0x5a 2980 2981 #define LQOSCSCTL 0x5a 2982 #define LQOH2A_VERSION 0x80 2983 #define LQONOCHKOVER 0x01 2984 2985 #define SEQINTSRC 0x5b 2986 #define CTXTDONE 0x40 2987 #define SAVEPTRS 0x20 2988 #define CFG4DATA 0x10 2989 #define CFG4ISTAT 0x08 2990 #define CFG4TSTAT 0x04 2991 #define CFG4ICMD 0x02 2992 #define CFG4TCMD 0x01 2993 2994 #define CLRSEQINTSRC 0x5b 2995 #define CLRCTXTDONE 0x40 2996 #define CLRSAVEPTRS 0x20 2997 #define CLRCFG4DATA 0x10 2998 #define CLRCFG4ISTAT 0x08 2999 #define CLRCFG4TSTAT 0x04 3000 #define CLRCFG4ICMD 0x02 3001 #define CLRCFG4TCMD 0x01 3002 3003 #define CURRSCB 0x5c 3004 3005 #define SEQIMODE 0x5c 3006 #define ENCTXTDONE 0x40 3007 #define ENSAVEPTRS 0x20 3008 #define ENCFG4DATA 0x10 3009 #define ENCFG4ISTAT 0x08 3010 #define ENCFG4TSTAT 0x04 3011 #define ENCFG4ICMD 0x02 3012 #define ENCFG4TCMD 0x01 3013 3014 #define MDFFSTAT 0x5d 3015 #define SHCNTNEGATIVE 0x40 3016 #define SHCNTMINUS1 0x20 3017 #define LASTSDONE 0x10 3018 #define SHVALID 0x08 3019 #define DLZERO 0x04 3020 #define DATAINFIFO 0x02 3021 #define FIFOFREE 0x01 3022 3023 #define CRCCONTROL 0x5d 3024 #define CRCVALCHKEN 0x40 3025 3026 #define SCSITEST 0x5e 3027 #define CNTRTEST 0x08 3028 #define SEL_TXPLL_DEBUG 0x04 3029 3030 #define DFFTAG 0x5e 3031 3032 #define LASTSCB 0x5e 3033 3034 #define IOPDNCTL 0x5f 3035 #define DISABLE_OE 0x80 3036 #define PDN_IDIST 0x04 3037 #define PDN_DIFFSENSE 0x01 3038 3039 #define NEGOADDR 0x60 3040 3041 #define SHADDR 0x60 3042 3043 #define DGRPCRCI 0x60 3044 3045 #define NEGPERIOD 0x61 3046 3047 #define PACKCRCI 0x62 3048 3049 #define NEGOFFSET 0x62 3050 3051 #define NEGPPROPTS 0x63 3052 #define PPROPT_PACE 0x08 3053 #define PPROPT_QAS 0x04 3054 #define PPROPT_DT 0x02 3055 #define PPROPT_IUT 0x01 3056 3057 #define NEGCONOPTS 0x64 3058 #define ENSNAPSHOT 0x40 3059 #define RTI_WRTDIS 0x20 3060 #define RTI_OVRDTRN 0x10 3061 #define ENSLOWCRC 0x08 3062 #define ENAUTOATNI 0x04 3063 #define ENAUTOATNO 0x02 3064 #define WIDEXFER 0x01 3065 3066 #define ANNEXCOL 0x65 3067 3068 #define ANNEXDAT 0x66 3069 3070 #define SCSCHKN 0x66 3071 #define STSELSKIDDIS 0x40 3072 #define CURRFIFODEF 0x20 3073 #define WIDERESEN 0x10 3074 #define SDONEMSKDIS 0x08 3075 #define DFFACTCLR 0x04 3076 #define SHVALIDSTDIS 0x02 3077 #define LSTSGCLRDIS 0x01 3078 3079 #define IOWNID 0x67 3080 3081 #define SHCNT 0x68 3082 3083 #define PLL960CTL0 0x68 3084 3085 #define PLL960CTL1 0x69 3086 3087 #define TOWNID 0x69 3088 3089 #define XSIG 0x6a 3090 3091 #define PLL960CNT0 0x6a 3092 3093 #define SELOID 0x6b 3094 3095 #define FAIRNESS 0x6c 3096 3097 #define PLL400CTL0 0x6c 3098 #define PLL_VCOSEL 0x80 3099 #define PLL_PWDN 0x40 3100 #define PLL_NS 0x30 3101 #define PLL_ENLUD 0x08 3102 #define PLL_ENLPF 0x04 3103 #define PLL_DLPF 0x02 3104 #define PLL_ENFBM 0x01 3105 3106 #define PLL400CTL1 0x6d 3107 #define PLL_CNTEN 0x80 3108 #define PLL_CNTCLR 0x40 3109 #define PLL_RST 0x01 3110 3111 #define PLL400CNT0 0x6e 3112 3113 #define UNFAIRNESS 0x6e 3114 3115 #define HODMAADR 0x70 3116 3117 #define HADDR 0x70 3118 3119 #define PLLDELAY 0x70 3120 #define SPLIT_DROP_REQ 0x80 3121 3122 #define HCNT 0x78 3123 3124 #define HODMACNT 0x78 3125 3126 #define HODMAEN 0x7a 3127 3128 #define SCBHADDR 0x7c 3129 3130 #define SGHADDR 0x7c 3131 3132 #define SCBHCNT 0x84 3133 3134 #define SGHCNT 0x84 3135 3136 #define DFF_THRSH 0x88 3137 #define WR_DFTHRSH 0x70 3138 #define RD_DFTHRSH 0x07 3139 #define WR_DFTHRSH_MAX 0x70 3140 #define WR_DFTHRSH_90 0x60 3141 #define WR_DFTHRSH_85 0x50 3142 #define WR_DFTHRSH_75 0x40 3143 #define WR_DFTHRSH_63 0x30 3144 #define WR_DFTHRSH_50 0x20 3145 #define WR_DFTHRSH_25 0x10 3146 #define RD_DFTHRSH_MAX 0x07 3147 #define RD_DFTHRSH_90 0x06 3148 #define RD_DFTHRSH_85 0x05 3149 #define RD_DFTHRSH_75 0x04 3150 #define RD_DFTHRSH_63 0x03 3151 #define RD_DFTHRSH_50 0x02 3152 #define RD_DFTHRSH_25 0x01 3153 #define WR_DFTHRSH_MIN 0x00 3154 #define RD_DFTHRSH_MIN 0x00 3155 3156 #define ROMADDR 0x8a 3157 3158 #define ROMCNTRL 0x8d 3159 #define ROMOP 0xe0 3160 #define ROMSPD 0x18 3161 #define REPEAT 0x02 3162 #define RDY 0x01 3163 3164 #define ROMDATA 0x8e 3165 3166 #define DCHRXMSG0 0x90 3167 3168 #define OVLYRXMSG0 0x90 3169 3170 #define CMCRXMSG0 0x90 3171 3172 #define ROENABLE 0x90 3173 #define MSIROEN 0x20 3174 #define OVLYROEN 0x10 3175 #define CMCROEN 0x08 3176 #define SGROEN 0x04 3177 #define DCH1ROEN 0x02 3178 #define DCH0ROEN 0x01 3179 3180 #define DCHRXMSG1 0x91 3181 3182 #define OVLYRXMSG1 0x91 3183 3184 #define CMCRXMSG1 0x91 3185 3186 #define NSENABLE 0x91 3187 #define MSINSEN 0x20 3188 #define OVLYNSEN 0x10 3189 #define CMCNSEN 0x08 3190 #define SGNSEN 0x04 3191 #define DCH1NSEN 0x02 3192 #define DCH0NSEN 0x01 3193 3194 #define DCHRXMSG2 0x92 3195 3196 #define OVLYRXMSG2 0x92 3197 3198 #define CMCRXMSG2 0x92 3199 3200 #define OST 0x92 3201 3202 #define DCHRXMSG3 0x93 3203 3204 #define OVLYRXMSG3 0x93 3205 3206 #define CMCRXMSG3 0x93 3207 3208 #define PCIXCTL 0x93 3209 #define SERRPULSE 0x80 3210 #define UNEXPSCIEN 0x20 3211 #define SPLTSMADIS 0x10 3212 #define SPLTSTADIS 0x08 3213 #define SRSPDPEEN 0x04 3214 #define TSCSERREN 0x02 3215 #define CMPABCDIS 0x01 3216 3217 #define CMCSEQBCNT 0x94 3218 3219 #define DCHSEQBCNT 0x94 3220 3221 #define OVLYSEQBCNT 0x94 3222 3223 #define CMCSPLTSTAT0 0x96 3224 3225 #define DCHSPLTSTAT0 0x96 3226 3227 #define OVLYSPLTSTAT0 0x96 3228 3229 #define CMCSPLTSTAT1 0x97 3230 3231 #define DCHSPLTSTAT1 0x97 3232 3233 #define OVLYSPLTSTAT1 0x97 3234 3235 #define SGRXMSG0 0x98 3236 #define CDNUM 0xf8 3237 #define CFNUM 0x07 3238 3239 #define SLVSPLTOUTADR0 0x98 3240 #define LOWER_ADDR 0x7f 3241 3242 #define SGRXMSG1 0x99 3243 #define CBNUM 0xff 3244 3245 #define SLVSPLTOUTADR1 0x99 3246 #define REQ_DNUM 0xf8 3247 #define REQ_FNUM 0x07 3248 3249 #define SGRXMSG2 0x9a 3250 #define MINDEX 0xff 3251 3252 #define SLVSPLTOUTADR2 0x9a 3253 #define REQ_BNUM 0xff 3254 3255 #define SGRXMSG3 0x9b 3256 #define MCLASS 0x0f 3257 3258 #define SLVSPLTOUTADR3 0x9b 3259 #define TAG_NUM 0x1f 3260 #define RLXORD 0x10 3261 3262 #define SLVSPLTOUTATTR0 0x9c 3263 #define LOWER_BCNT 0xff 3264 3265 #define SGSEQBCNT 0x9c 3266 3267 #define SLVSPLTOUTATTR1 0x9d 3268 #define CMPLT_DNUM 0xf8 3269 #define CMPLT_FNUM 0x07 3270 3271 #define SLVSPLTOUTATTR2 0x9e 3272 #define CMPLT_BNUM 0xff 3273 3274 #define SGSPLTSTAT0 0x9e 3275 #define STAETERM 0x80 3276 #define SCBCERR 0x40 3277 #define SCADERR 0x20 3278 #define SCDATBUCKET 0x10 3279 #define CNTNOTCMPLT 0x08 3280 #define RXOVRUN 0x04 3281 #define RXSCEMSG 0x02 3282 #define RXSPLTRSP 0x01 3283 3284 #define SFUNCT 0x9f 3285 #define TEST_GROUP 0xf0 3286 #define TEST_NUM 0x0f 3287 3288 #define SGSPLTSTAT1 0x9f 3289 #define RXDATABUCKET 0x01 3290 3291 #define DF0PCISTAT 0xa0 3292 3293 #define REG0 0xa0 3294 3295 #define DF1PCISTAT 0xa1 3296 3297 #define SGPCISTAT 0xa2 3298 3299 #define REG1 0xa2 3300 3301 #define CMCPCISTAT 0xa3 3302 3303 #define OVLYPCISTAT 0xa4 3304 #define SCAAPERR 0x08 3305 #define RDPERR 0x04 3306 3307 #define REG_ISR 0xa4 3308 3309 #define MSIPCISTAT 0xa6 3310 #define RMA 0x20 3311 #define RTA 0x10 3312 #define CLRPENDMSI 0x08 3313 #define DPR 0x01 3314 3315 #define SG_STATE 0xa6 3316 #define FETCH_INPROG 0x04 3317 #define LOADING_NEEDED 0x02 3318 #define SEGS_AVAIL 0x01 3319 3320 #define TARGPCISTAT 0xa7 3321 #define DPE 0x80 3322 #define SSE 0x40 3323 #define STA 0x08 3324 #define TWATERR 0x02 3325 3326 #define DATA_COUNT_ODD 0xa7 3327 3328 #define SCBPTR 0xa8 3329 3330 #define CCSCBACNT 0xab 3331 3332 #define SCBAUTOPTR 0xab 3333 #define AUSCBPTR_EN 0x80 3334 #define SCBPTR_ADDR 0x38 3335 #define SCBPTR_OFF 0x07 3336 3337 #define CCSCBADR_BK 0xac 3338 3339 #define CCSGADDR 0xac 3340 3341 #define CCSCBADDR 0xac 3342 3343 #define CCSCBCTL 0xad 3344 #define CCSCBDONE 0x80 3345 #define ARRDONE 0x40 3346 #define CCARREN 0x10 3347 #define CCSCBEN 0x08 3348 #define CCSCBDIR 0x04 3349 #define CCSCBRESET 0x01 3350 3351 #define CCSGCTL 0xad 3352 #define CCSGEN 0x0c 3353 #define CCSGDONE 0x80 3354 #define SG_CACHE_AVAIL 0x10 3355 #define CCSGENACK 0x08 3356 #define SG_FETCH_REQ 0x02 3357 #define CCSGRESET 0x01 3358 3359 #define CMC_RAMBIST 0xad 3360 #define SG_ELEMENT_SIZE 0x80 3361 #define SCBRAMBIST_FAIL 0x40 3362 #define SG_BIST_FAIL 0x20 3363 #define SG_BIST_EN 0x10 3364 #define CMC_BUFFER_BIST_FAIL 0x02 3365 #define CMC_BUFFER_BIST_EN 0x01 3366 3367 #define CCSGRAM 0xb0 3368 3369 #define CCSCBRAM 0xb0 3370 3371 #define FLEXADR 0xb0 3372 3373 #define FLEXCNT 0xb3 3374 3375 #define FLEXDMASTAT 0xb5 3376 #define FLEXDMAERR 0x02 3377 #define FLEXDMADONE 0x01 3378 3379 #define FLEXDATA 0xb6 3380 3381 #define BRDDAT 0xb8 3382 3383 #define BRDCTL 0xb9 3384 #define FLXARBACK 0x80 3385 #define FLXARBREQ 0x40 3386 #define BRDADDR 0x38 3387 #define BRDEN 0x04 3388 #define BRDRW 0x02 3389 #define BRDSTB 0x01 3390 3391 #define SEEADR 0xba 3392 3393 #define SEEDAT 0xbc 3394 3395 #define SEECTL 0xbe 3396 #define SEEOP_EWEN 0x40 3397 #define SEEOP_EWDS 0x40 3398 #define SEEOP_WALL 0x40 3399 #define SEEOPCODE 0x70 3400 #define SEERST 0x02 3401 #define SEESTART 0x01 3402 #define SEEOP_ERASE 0x70 3403 #define SEEOP_READ 0x60 3404 #define SEEOP_WRITE 0x50 3405 #define SEEOP_ERAL 0x40 3406 3407 #define SEESTAT 0xbe 3408 #define INIT_DONE 0x80 3409 #define LDALTID_L 0x08 3410 #define SEEARBACK 0x04 3411 #define SEEBUSY 0x02 3412 3413 #define SCBCNT 0xbf 3414 3415 #define DSPFLTRCTL 0xc0 3416 #define FLTRDISABLE 0x20 3417 #define EDGESENSE 0x10 3418 #define DSPFCNTSEL 0x0f 3419 3420 #define DFWADDR 0xc0 3421 3422 #define DSPDATACTL 0xc1 3423 #define BYPASSENAB 0x80 3424 #define DESQDIS 0x10 3425 #define RCVROFFSTDIS 0x04 3426 #define XMITOFFSTDIS 0x02 3427 3428 #define DSPREQCTL 0xc2 3429 #define MANREQCTL 0xc0 3430 #define MANREQDLY 0x3f 3431 3432 #define DFRADDR 0xc2 3433 3434 #define DSPACKCTL 0xc3 3435 #define MANACKCTL 0xc0 3436 #define MANACKDLY 0x3f 3437 3438 #define DFDAT 0xc4 3439 3440 #define DSPSELECT 0xc4 3441 #define AUTOINCEN 0x80 3442 #define DSPSEL 0x1f 3443 3444 #define WRTBIASCTL 0xc5 3445 #define AUTOXBCDIS 0x80 3446 #define XMITMANVAL 0x3f 3447 3448 #define RCVRBIOSCTL 0xc6 3449 #define AUTORBCDIS 0x80 3450 #define RCVRMANVAL 0x3f 3451 3452 #define WRTBIASCALC 0xc7 3453 3454 #define DFPTRS 0xc8 3455 3456 #define RCVRBIASCALC 0xc8 3457 3458 #define DFBKPTR 0xc9 3459 3460 #define SKEWCALC 0xc9 3461 3462 #define DFDBCTL 0xcb 3463 #define DFF_CIO_WR_RDY 0x20 3464 #define DFF_CIO_RD_RDY 0x10 3465 #define DFF_DIR_ERR 0x08 3466 #define DFF_RAMBIST_FAIL 0x04 3467 #define DFF_RAMBIST_DONE 0x02 3468 #define DFF_RAMBIST_EN 0x01 3469 3470 #define DFSCNT 0xcc 3471 3472 #define DFBCNT 0xce 3473 3474 #define OVLYADDR 0xd4 3475 3476 #define SEQCTL0 0xd6 3477 #define PERRORDIS 0x80 3478 #define PAUSEDIS 0x40 3479 #define FAILDIS 0x20 3480 #define FASTMODE 0x10 3481 #define BRKADRINTEN 0x08 3482 #define STEP 0x04 3483 #define SEQRESET 0x02 3484 #define LOADRAM 0x01 3485 3486 #define SEQCTL1 0xd7 3487 #define OVRLAY_DATA_CHK 0x08 3488 #define RAMBIST_DONE 0x04 3489 #define RAMBIST_FAIL 0x02 3490 #define RAMBIST_EN 0x01 3491 3492 #define FLAGS 0xd8 3493 #define ZERO 0x02 3494 #define CARRY 0x01 3495 3496 #define SEQINTCTL 0xd9 3497 #define INTVEC1DSL 0x80 3498 #define INT1_CONTEXT 0x20 3499 #define SCS_SEQ_INT1M1 0x10 3500 #define SCS_SEQ_INT1M0 0x08 3501 #define INTMASK2 0x04 3502 #define INTMASK1 0x02 3503 #define IRET 0x01 3504 3505 #define SEQRAM 0xda 3506 3507 #define PRGMCNT 0xde 3508 3509 #define ACCUM 0xe0 3510 3511 #define SINDEX 0xe2 3512 3513 #define DINDEX 0xe4 3514 3515 #define BRKADDR1 0xe6 3516 #define BRKDIS 0x80 3517 3518 #define BRKADDR0 0xe6 3519 3520 #define ALLONES 0xe8 3521 3522 #define NONE 0xea 3523 3524 #define ALLZEROS 0xea 3525 3526 #define SINDIR 0xec 3527 3528 #define DINDIR 0xed 3529 3530 #define FUNCTION1 0xf0 3531 3532 #define STACK 0xf2 3533 3534 #define INTVEC1_ADDR 0xf4 3535 3536 #define CURADDR 0xf4 3537 3538 #define INTVEC2_ADDR 0xf6 3539 3540 #define LASTADDR 0xf6 3541 3542 #define LONGJMP_ADDR 0xf8 3543 3544 #define ACCUM_SAVE 0xfa 3545 3546 #define SRAM_BASE 0x100 3547 3548 #define WAITING_SCB_TAILS 0x100 3549 3550 #define AHD_PCI_CONFIG_BASE 0x100 3551 3552 #define WAITING_TID_HEAD 0x120 3553 3554 #define WAITING_TID_TAIL 0x122 3555 3556 #define NEXT_QUEUED_SCB_ADDR 0x124 3557 3558 #define COMPLETE_SCB_HEAD 0x128 3559 3560 #define COMPLETE_SCB_DMAINPROG_HEAD 0x12a 3561 3562 #define COMPLETE_DMA_SCB_HEAD 0x12c 3563 3564 #define COMPLETE_DMA_SCB_TAIL 0x12e 3565 3566 #define COMPLETE_ON_QFREEZE_HEAD 0x130 3567 3568 #define QFREEZE_COUNT 0x132 3569 3570 #define KERNEL_QFREEZE_COUNT 0x134 3571 3572 #define SAVED_MODE 0x136 3573 3574 #define MSG_OUT 0x137 3575 3576 #define DMAPARAMS 0x138 3577 #define PRELOADEN 0x80 3578 #define WIDEODD 0x40 3579 #define SCSIEN 0x20 3580 #define SDMAEN 0x10 3581 #define SDMAENACK 0x10 3582 #define HDMAEN 0x08 3583 #define HDMAENACK 0x08 3584 #define DIRECTION 0x04 3585 #define FIFOFLUSH 0x02 3586 #define FIFORESET 0x01 3587 3588 #define SEQ_FLAGS 0x139 3589 #define NOT_IDENTIFIED 0x80 3590 #define NO_CDB_SENT 0x40 3591 #define TARGET_CMD_IS_TAGGED 0x40 3592 #define DPHASE 0x20 3593 #define TARG_CMD_PENDING 0x10 3594 #define CMDPHASE_PENDING 0x08 3595 #define DPHASE_PENDING 0x04 3596 #define SPHASE_PENDING 0x02 3597 #define NO_DISCONNECT 0x01 3598 3599 #define SAVED_SCSIID 0x13a 3600 3601 #define SAVED_LUN 0x13b 3602 3603 #define LASTPHASE 0x13c 3604 #define PHASE_MASK 0xe0 3605 #define CDI 0x80 3606 #define IOI 0x40 3607 #define MSGI 0x20 3608 #define P_BUSFREE 0x01 3609 #define P_MESGIN 0xe0 3610 #define P_STATUS 0xc0 3611 #define P_MESGOUT 0xa0 3612 #define P_COMMAND 0x80 3613 #define P_DATAIN_DT 0x60 3614 #define P_DATAIN 0x40 3615 #define P_DATAOUT_DT 0x20 3616 #define P_DATAOUT 0x00 3617 3618 #define QOUTFIFO_ENTRY_VALID_TAG 0x13d 3619 3620 #define KERNEL_TQINPOS 0x13e 3621 3622 #define TQINPOS 0x13f 3623 3624 #define SHARED_DATA_ADDR 0x140 3625 3626 #define QOUTFIFO_NEXT_ADDR 0x144 3627 3628 #define ARG_1 0x148 3629 #define RETURN_1 0x148 3630 #define SEND_MSG 0x80 3631 #define SEND_SENSE 0x40 3632 #define SEND_REJ 0x20 3633 #define MSGOUT_PHASEMIS 0x10 3634 #define EXIT_MSG_LOOP 0x08 3635 #define CONT_MSG_LOOP_WRITE 0x04 3636 #define CONT_MSG_LOOP_READ 0x03 3637 #define CONT_MSG_LOOP_TARG 0x02 3638 3639 #define ARG_2 0x149 3640 #define RETURN_2 0x149 3641 3642 #define LAST_MSG 0x14a 3643 3644 #define SCSISEQ_TEMPLATE 0x14b 3645 #define MANUALCTL 0x40 3646 #define ENSELI 0x20 3647 #define ENRSELI 0x10 3648 #define MANUALP 0x0c 3649 #define ENAUTOATNP 0x02 3650 #define ALTSTIM 0x01 3651 3652 #define INITIATOR_TAG 0x14c 3653 3654 #define SEQ_FLAGS2 0x14d 3655 #define SELECTOUT_QFROZEN 0x04 3656 #define TARGET_MSG_PENDING 0x02 3657 #define PENDING_MK_MESSAGE 0x01 3658 3659 #define ALLOCFIFO_SCBPTR 0x14e 3660 3661 #define INT_COALESCING_TIMER 0x150 3662 3663 #define INT_COALESCING_MAXCMDS 0x152 3664 3665 #define INT_COALESCING_MINCMDS 0x153 3666 3667 #define CMDS_PENDING 0x154 3668 3669 #define INT_COALESCING_CMDCOUNT 0x156 3670 3671 #define LOCAL_HS_MAILBOX 0x157 3672 3673 #define CMDSIZE_TABLE 0x158 3674 3675 #define MK_MESSAGE_SCB 0x160 3676 3677 #define MK_MESSAGE_SCSIID 0x162 3678 3679 #define SCB_BASE 0x180 3680 3681 #define SCB_RESIDUAL_DATACNT 0x180 3682 #define SCB_HOST_CDB_PTR 0x180 3683 #define SCB_CDB_STORE 0x180 3684 3685 #define SCB_RESIDUAL_SGPTR 0x184 3686 #define SG_ADDR_MASK 0xf8 3687 #define SG_ADDR_BIT 0x04 3688 #define SG_OVERRUN_RESID 0x02 3689 3690 #define SCB_SCSI_STATUS 0x188 3691 #define SCB_HOST_CDB_LEN 0x188 3692 3693 #define SCB_TARGET_PHASES 0x189 3694 3695 #define SCB_TARGET_DATA_DIR 0x18a 3696 3697 #define SCB_TARGET_ITAG 0x18b 3698 3699 #define SCB_SENSE_BUSADDR 0x18c 3700 #define SCB_NEXT_COMPLETE 0x18c 3701 3702 #define SCB_TAG 0x190 3703 #define SCB_FIFO_USE_COUNT 0x190 3704 3705 #define SCB_CONTROL 0x192 3706 #define TARGET_SCB 0x80 3707 #define DISCENB 0x40 3708 #define TAG_ENB 0x20 3709 #define MK_MESSAGE 0x10 3710 #define STATUS_RCVD 0x08 3711 #define DISCONNECTED 0x04 3712 #define SCB_TAG_TYPE 0x03 3713 3714 #define SCB_SCSIID 0x193 3715 #define TID 0xf0 3716 #define OID 0x0f 3717 3718 #define SCB_LUN 0x194 3719 #define LID 0xff 3720 3721 #define SCB_TASK_ATTRIBUTE 0x195 3722 #define SCB_XFERLEN_ODD 0x01 3723 3724 #define SCB_CDB_LEN 0x196 3725 #define SCB_CDB_LEN_PTR 0x80 3726 3727 #define SCB_TASK_MANAGEMENT 0x197 3728 3729 #define SCB_DATAPTR 0x198 3730 3731 #define SCB_DATACNT 0x1a0 3732 #define SG_LAST_SEG 0x80 3733 #define SG_HIGH_ADDR_BITS 0x7f 3734 3735 #define SCB_SGPTR 0x1a4 3736 #define SG_STATUS_VALID 0x04 3737 #define SG_FULL_RESID 0x02 3738 #define SG_LIST_NULL 0x01 3739 3740 #define SCB_BUSADDR 0x1a8 3741 3742 #define SCB_NEXT 0x1ac 3743 #define SCB_NEXT_SCB_BUSADDR 0x1ac 3744 3745 #define SCB_NEXT2 0x1ae 3746 3747 #define SCB_SPARE 0x1b0 3748 #define SCB_PKT_LUN 0x1b0 3749 3750 #define SCB_DISCONNECTED_LISTS 0x1b8 3751 3752 3753 #define STATUS_QUEUE_FULL 0x28 3754 #define WRTBIASCTL_HP_DEFAULT 0x00 3755 #define NUMDSPS 0x14 3756 #define AHD_NUM_PER_DEV_ANNEXCOLS 0x04 3757 #define AHD_TIMER_MAX_US 0x18ffe7 3758 #define STIMESEL_MIN 0x18 3759 #define TARGET_CMD_CMPLT 0xfe 3760 #define SEEOP_ERAL_ADDR 0x80 3761 #define SRC_MODE_SHIFT 0x00 3762 #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 3763 #define MAX_OFFSET_PACED 0xfe 3764 #define SEEOP_EWDS_ADDR 0x00 3765 #define AHD_ANNEXCOL_AMPLITUDE 0x06 3766 #define AHD_PRECOMP_CUTBACK_29 0x06 3767 #define AHD_ANNEXCOL_PER_DEV0 0x04 3768 #define AHD_TIMER_MAX_TICKS 0xffff 3769 #define STATUS_PKT_SENSE 0xff 3770 #define CMD_GROUP_CODE_SHIFT 0x05 3771 #define BUS_8_BIT 0x00 3772 #define CCSGRAM_MAXSEGS 0x10 3773 #define AHD_AMPLITUDE_DEF 0x07 3774 #define AHD_SLEWRATE_DEF_REVB 0x08 3775 #define AHD_PRECOMP_CUTBACK_37 0x07 3776 #define AHD_PRECOMP_SHIFT 0x00 3777 #define PKT_OVERRUN_BUFSIZE 0x200 3778 #define SCB_TRANSFER_SIZE_FULL_LUN 0x38 3779 #define TARGET_DATA_IN 0x01 3780 #define STATUS_BUSY 0x08 3781 #define BUS_16_BIT 0x01 3782 #define CCSCBADDR_MAX 0x80 3783 #define TID_SHIFT 0x04 3784 #define AHD_AMPLITUDE_SHIFT 0x00 3785 #define AHD_SLEWRATE_DEF_REVA 0x08 3786 #define AHD_SLEWRATE_MASK 0x78 3787 #define MAX_OFFSET_PACED_BUG 0x7f 3788 #define AHD_PRECOMP_CUTBACK_17 0x04 3789 #define AHD_PRECOMP_MASK 0x07 3790 #define AHD_TIMER_US_PER_TICK 0x19 3791 #define HOST_MSG 0xff 3792 #define MAX_OFFSET 0xfe 3793 #define BUS_32_BIT 0x02 3794 #define SEEOP_EWEN_ADDR 0xc0 3795 #define AHD_AMPLITUDE_MASK 0x07 3796 #define LUNLEN_SINGLE_LEVEL_LUN 0x0f 3797 #define DST_MODE_SHIFT 0x04 3798 #define STIMESEL_SHIFT 0x03 3799 #define SEEOP_WRAL_ADDR 0x40 3800 #define AHD_ANNEXCOL_PRECOMP_SLEW 0x04 3801 #define MAX_OFFSET_NON_PACED 0x7f 3802 #define NVRAM_SCB_OFFSET 0x2c 3803 #define AHD_SENSE_BUFSIZE 0x100 3804 #define STIMESEL_BUG_ADJ 0x08 3805 #define INVALID_ADDR 0x80 3806 #define CCSGADDR_MAX 0x80 3807 #define MK_MESSAGE_BIT_OFFSET 0x04 3808 #define AHD_SLEWRATE_SHIFT 0x03 3809 #define B_CURRFIFO_0 0x02 3810 3811 3812 /* Downloaded Constant Definitions */ 3813 #define SG_SIZEOF 0x04 3814 #define CACHELINE_MASK 0x07 3815 #define SG_PREFETCH_ADDR_MASK 0x03 3816 #define SG_PREFETCH_ALIGN_MASK 0x02 3817 #define SCB_TRANSFER_SIZE 0x06 3818 #define SG_PREFETCH_CNT 0x00 3819 #define SG_PREFETCH_CNT_LIMIT 0x01 3820 #define PKT_OVERRUN_BUFOFFSET 0x05 3821 #define DOWNLOAD_CONST_COUNT 0x08 3822 3823 3824 /* Exported Labels */ 3825 #define LABEL_seq_isr 0x28f 3826 #define LABEL_timer_isr 0x28b
Cache object: e25c1300da828191bebce17d802a0dfe
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]