Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/aic7xxx/aic7xxx.c
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1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $ 41 */ 42 43 #ifdef __linux__ 44 #include "aic7xxx_osm.h" 45 #include "aic7xxx_inline.h" 46 #include "aicasm/aicasm_insformat.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD: releng/5.3/sys/dev/aic7xxx/aic7xxx.c 133911 2004-08-17 00:14:31Z gibbs $"); 50 #include <dev/aic7xxx/aic7xxx_osm.h> 51 #include <dev/aic7xxx/aic7xxx_inline.h> 52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53 #endif 54 55 /****************************** Softc Data ************************************/ 56 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 57 58 /***************************** Lookup Tables **********************************/ 59 char *ahc_chip_names[] = 60 { 61 "NONE", 62 "aic7770", 63 "aic7850", 64 "aic7855", 65 "aic7859", 66 "aic7860", 67 "aic7870", 68 "aic7880", 69 "aic7895", 70 "aic7895C", 71 "aic7890/91", 72 "aic7896/97", 73 "aic7892", 74 "aic7899" 75 }; 76 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 77 78 /* 79 * Hardware error codes. 80 */ 81 struct ahc_hard_error_entry { 82 uint8_t errno; 83 char *errmesg; 84 }; 85 86 static struct ahc_hard_error_entry ahc_hard_errors[] = { 87 { ILLHADDR, "Illegal Host Access" }, 88 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 89 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 90 { SQPARERR, "Sequencer Parity Error" }, 91 { DPARERR, "Data-path Parity Error" }, 92 { MPARERR, "Scratch or SCB Memory Parity Error" }, 93 { PCIERRSTAT, "PCI Error detected" }, 94 { CIOPARERR, "CIOBUS Parity Error" }, 95 }; 96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 97 98 static struct ahc_phase_table_entry ahc_phase_table[] = 99 { 100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 104 { P_COMMAND, MSG_NOOP, "in Command phase" }, 105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 108 { P_BUSFREE, MSG_NOOP, "while idle" }, 109 { 0, MSG_NOOP, "in unknown phase" } 110 }; 111 112 /* 113 * In most cases we only wish to itterate over real phases, so 114 * exclude the last element from the count. 115 */ 116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 117 118 /* 119 * Valid SCSIRATE values. (p. 3-17) 120 * Provides a mapping of tranfer periods in ns to the proper value to 121 * stick in the scsixfer reg. 122 */ 123 static struct ahc_syncrate ahc_syncrates[] = 124 { 125 /* ultra2 fast/ultra period rate */ 126 { 0x42, 0x000, 9, "80.0" }, 127 { 0x03, 0x000, 10, "40.0" }, 128 { 0x04, 0x000, 11, "33.0" }, 129 { 0x05, 0x100, 12, "20.0" }, 130 { 0x06, 0x110, 15, "16.0" }, 131 { 0x07, 0x120, 18, "13.4" }, 132 { 0x08, 0x000, 25, "10.0" }, 133 { 0x19, 0x010, 31, "8.0" }, 134 { 0x1a, 0x020, 37, "6.67" }, 135 { 0x1b, 0x030, 43, "5.7" }, 136 { 0x1c, 0x040, 50, "5.0" }, 137 { 0x00, 0x050, 56, "4.4" }, 138 { 0x00, 0x060, 62, "4.0" }, 139 { 0x00, 0x070, 68, "3.6" }, 140 { 0x00, 0x000, 0, NULL } 141 }; 142 143 /* Our Sequencer Program */ 144 #include "aic7xxx_seq.h" 145 146 /**************************** Function Declarations ***************************/ 147 static void ahc_force_renegotiation(struct ahc_softc *ahc, 148 struct ahc_devinfo *devinfo); 149 static struct ahc_tmode_tstate* 150 ahc_alloc_tstate(struct ahc_softc *ahc, 151 u_int scsi_id, char channel); 152 #ifdef AHC_TARGET_MODE 153 static void ahc_free_tstate(struct ahc_softc *ahc, 154 u_int scsi_id, char channel, int force); 155 #endif 156 static struct ahc_syncrate* 157 ahc_devlimited_syncrate(struct ahc_softc *ahc, 158 struct ahc_initiator_tinfo *, 159 u_int *period, 160 u_int *ppr_options, 161 role_t role); 162 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 163 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 164 struct ahc_devinfo *devinfo); 165 static void ahc_scb_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo, 167 struct scb *scb); 168 static void ahc_assert_atn(struct ahc_softc *ahc); 169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 struct scb *scb); 172 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo); 174 static void ahc_construct_sdtr(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo, 176 u_int period, u_int offset); 177 static void ahc_construct_wdtr(struct ahc_softc *ahc, 178 struct ahc_devinfo *devinfo, 179 u_int bus_width); 180 static void ahc_construct_ppr(struct ahc_softc *ahc, 181 struct ahc_devinfo *devinfo, 182 u_int period, u_int offset, 183 u_int bus_width, u_int ppr_options); 184 static void ahc_clear_msg_state(struct ahc_softc *ahc); 185 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 186 static void ahc_handle_message_phase(struct ahc_softc *ahc); 187 typedef enum { 188 AHCMSG_1B, 189 AHCMSG_2B, 190 AHCMSG_EXT 191 } ahc_msgtype; 192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 193 u_int msgval, int full); 194 static int ahc_parse_msg(struct ahc_softc *ahc, 195 struct ahc_devinfo *devinfo); 196 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 201 static void ahc_handle_devreset(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 cam_status status, char *message, 204 int verbose_level); 205 #ifdef AHC_TARGET_MODE 206 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 207 struct ahc_devinfo *devinfo, 208 struct scb *scb); 209 #endif 210 211 static bus_dmamap_callback_t ahc_dmamap_cb; 212 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 213 static int ahc_init_scbdata(struct ahc_softc *ahc); 214 static void ahc_fini_scbdata(struct ahc_softc *ahc); 215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 216 struct scb *prev_scb, 217 struct scb *scb); 218 static int ahc_qinfifo_count(struct ahc_softc *ahc); 219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 220 u_int prev, u_int scbptr); 221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 222 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 223 u_int scbpos, u_int prev); 224 static void ahc_reset_current_bus(struct ahc_softc *ahc); 225 #ifdef AHC_DUMP_SEQ 226 static void ahc_dumpseq(struct ahc_softc *ahc); 227 #endif 228 static int ahc_loadseq(struct ahc_softc *ahc); 229 static int ahc_check_patch(struct ahc_softc *ahc, 230 struct patch **start_patch, 231 u_int start_instr, u_int *skip_addr); 232 static void ahc_download_instr(struct ahc_softc *ahc, 233 u_int instrptr, uint8_t *dconsts); 234 static int ahc_other_scb_timeout(struct ahc_softc *ahc, 235 struct scb *scb, 236 struct scb *other_scb); 237 #ifdef AHC_TARGET_MODE 238 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 239 struct ahc_tmode_lstate *lstate, 240 u_int initiator_id, 241 u_int event_type, 242 u_int event_arg); 243 static void ahc_update_scsiid(struct ahc_softc *ahc, 244 u_int targid_mask); 245 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 246 struct target_cmd *cmd); 247 #endif 248 /************************* Sequencer Execution Control ************************/ 249 /* 250 * Restart the sequencer program from address zero 251 */ 252 void 253 ahc_restart(struct ahc_softc *ahc) 254 { 255 256 ahc_pause(ahc); 257 258 /* No more pending messages. */ 259 ahc_clear_msg_state(ahc); 260 261 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 262 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 263 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 264 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 265 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 266 ahc_outb(ahc, SAVED_LUN, 0xFF); 267 268 /* 269 * Ensure that the sequencer's idea of TQINPOS 270 * matches our own. The sequencer increments TQINPOS 271 * only after it sees a DMA complete and a reset could 272 * occur before the increment leaving the kernel to believe 273 * the command arrived but the sequencer to not. 274 */ 275 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 276 277 /* Always allow reselection */ 278 ahc_outb(ahc, SCSISEQ, 279 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 280 if ((ahc->features & AHC_CMD_CHAN) != 0) { 281 /* Ensure that no DMA operations are in progress */ 282 ahc_outb(ahc, CCSCBCNT, 0); 283 ahc_outb(ahc, CCSGCTL, 0); 284 ahc_outb(ahc, CCSCBCTL, 0); 285 } 286 /* 287 * If we were in the process of DMA'ing SCB data into 288 * an SCB, replace that SCB on the free list. This prevents 289 * an SCB leak. 290 */ 291 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 292 ahc_add_curscb_to_free_list(ahc); 293 ahc_outb(ahc, SEQ_FLAGS2, 294 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 295 } 296 297 /* 298 * Clear any pending sequencer interrupt. It is no 299 * longer relevant since we're resetting the Program 300 * Counter. 301 */ 302 ahc_outb(ahc, CLRINT, CLRSEQINT); 303 304 ahc_outb(ahc, MWI_RESIDUAL, 0); 305 ahc_outb(ahc, SEQCTL, ahc->seqctl); 306 ahc_outb(ahc, SEQADDR0, 0); 307 ahc_outb(ahc, SEQADDR1, 0); 308 309 ahc_unpause(ahc); 310 } 311 312 /************************* Input/Output Queues ********************************/ 313 void 314 ahc_run_qoutfifo(struct ahc_softc *ahc) 315 { 316 struct scb *scb; 317 u_int scb_index; 318 319 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 320 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 321 322 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 323 if ((ahc->qoutfifonext & 0x03) == 0x03) { 324 u_int modnext; 325 326 /* 327 * Clear 32bits of QOUTFIFO at a time 328 * so that we don't clobber an incoming 329 * byte DMA to the array on architectures 330 * that only support 32bit load and store 331 * operations. 332 */ 333 modnext = ahc->qoutfifonext & ~0x3; 334 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 335 aic_dmamap_sync(ahc, ahc->shared_data_dmat, 336 ahc->shared_data_dmamap, 337 /*offset*/modnext, /*len*/4, 338 BUS_DMASYNC_PREREAD); 339 } 340 ahc->qoutfifonext++; 341 342 scb = ahc_lookup_scb(ahc, scb_index); 343 if (scb == NULL) { 344 printf("%s: WARNING no command for scb %d " 345 "(cmdcmplt)\nQOUTPOS = %d\n", 346 ahc_name(ahc), scb_index, 347 (ahc->qoutfifonext - 1) & 0xFF); 348 continue; 349 } 350 351 /* 352 * Save off the residual 353 * if there is one. 354 */ 355 ahc_update_residual(ahc, scb); 356 ahc_done(ahc, scb); 357 } 358 } 359 360 void 361 ahc_run_untagged_queues(struct ahc_softc *ahc) 362 { 363 int i; 364 365 for (i = 0; i < 16; i++) 366 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 367 } 368 369 void 370 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 371 { 372 struct scb *scb; 373 374 if (ahc->untagged_queue_lock != 0) 375 return; 376 377 if ((scb = TAILQ_FIRST(queue)) != NULL 378 && (scb->flags & SCB_ACTIVE) == 0) { 379 scb->flags |= SCB_ACTIVE; 380 /* 381 * Timers are disabled while recovery is in progress. 382 */ 383 aic_scb_timer_start(scb); 384 ahc_queue_scb(ahc, scb); 385 } 386 } 387 388 /************************* Interrupt Handling *********************************/ 389 void 390 ahc_handle_brkadrint(struct ahc_softc *ahc) 391 { 392 /* 393 * We upset the sequencer :-( 394 * Lookup the error message 395 */ 396 int i; 397 int error; 398 399 error = ahc_inb(ahc, ERROR); 400 for (i = 0; error != 1 && i < num_errors; i++) 401 error >>= 1; 402 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 403 ahc_name(ahc), ahc_hard_errors[i].errmesg, 404 ahc_inb(ahc, SEQADDR0) | 405 (ahc_inb(ahc, SEQADDR1) << 8)); 406 407 ahc_dump_card_state(ahc); 408 409 /* Tell everyone that this HBA is no longer available */ 410 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 411 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 412 CAM_NO_HBA); 413 414 /* Disable all interrupt sources by resetting the controller */ 415 ahc_shutdown(ahc); 416 } 417 418 void 419 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 420 { 421 struct scb *scb; 422 struct ahc_devinfo devinfo; 423 424 ahc_fetch_devinfo(ahc, &devinfo); 425 426 /* 427 * Clear the upper byte that holds SEQINT status 428 * codes and clear the SEQINT bit. We will unpause 429 * the sequencer, if appropriate, after servicing 430 * the request. 431 */ 432 ahc_outb(ahc, CLRINT, CLRSEQINT); 433 switch (intstat & SEQINT_MASK) { 434 case BAD_STATUS: 435 { 436 u_int scb_index; 437 struct hardware_scb *hscb; 438 439 /* 440 * Set the default return value to 0 (don't 441 * send sense). The sense code will change 442 * this if needed. 443 */ 444 ahc_outb(ahc, RETURN_1, 0); 445 446 /* 447 * The sequencer will notify us when a command 448 * has an error that would be of interest to 449 * the kernel. This allows us to leave the sequencer 450 * running in the common case of command completes 451 * without error. The sequencer will already have 452 * dma'd the SCB back up to us, so we can reference 453 * the in kernel copy directly. 454 */ 455 scb_index = ahc_inb(ahc, SCB_TAG); 456 scb = ahc_lookup_scb(ahc, scb_index); 457 if (scb == NULL) { 458 ahc_print_devinfo(ahc, &devinfo); 459 printf("ahc_intr - referenced scb " 460 "not valid during seqint 0x%x scb(%d)\n", 461 intstat, scb_index); 462 ahc_dump_card_state(ahc); 463 panic("for safety"); 464 goto unpause; 465 } 466 467 hscb = scb->hscb; 468 469 /* Don't want to clobber the original sense code */ 470 if ((scb->flags & SCB_SENSE) != 0) { 471 /* 472 * Clear the SCB_SENSE Flag and have 473 * the sequencer do a normal command 474 * complete. 475 */ 476 scb->flags &= ~SCB_SENSE; 477 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 478 break; 479 } 480 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 481 /* Freeze the queue until the client sees the error. */ 482 ahc_freeze_devq(ahc, scb); 483 aic_freeze_scb(scb); 484 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 485 switch (hscb->shared_data.status.scsi_status) { 486 case SCSI_STATUS_OK: 487 printf("%s: Interrupted for staus of 0???\n", 488 ahc_name(ahc)); 489 break; 490 case SCSI_STATUS_CMD_TERMINATED: 491 case SCSI_STATUS_CHECK_COND: 492 { 493 struct ahc_dma_seg *sg; 494 struct scsi_sense *sc; 495 struct ahc_initiator_tinfo *targ_info; 496 struct ahc_tmode_tstate *tstate; 497 struct ahc_transinfo *tinfo; 498 #ifdef AHC_DEBUG 499 if (ahc_debug & AHC_SHOW_SENSE) { 500 ahc_print_path(ahc, scb); 501 printf("SCB %d: requests Check Status\n", 502 scb->hscb->tag); 503 } 504 #endif 505 506 if (aic_perform_autosense(scb) == 0) 507 break; 508 509 targ_info = ahc_fetch_transinfo(ahc, 510 devinfo.channel, 511 devinfo.our_scsiid, 512 devinfo.target, 513 &tstate); 514 tinfo = &targ_info->curr; 515 sg = scb->sg_list; 516 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 517 /* 518 * Save off the residual if there is one. 519 */ 520 ahc_update_residual(ahc, scb); 521 #ifdef AHC_DEBUG 522 if (ahc_debug & AHC_SHOW_SENSE) { 523 ahc_print_path(ahc, scb); 524 printf("Sending Sense\n"); 525 } 526 #endif 527 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 528 sg->len = aic_get_sense_bufsize(ahc, scb); 529 sg->len |= AHC_DMA_LAST_SEG; 530 531 /* Fixup byte order */ 532 sg->addr = aic_htole32(sg->addr); 533 sg->len = aic_htole32(sg->len); 534 535 sc->opcode = REQUEST_SENSE; 536 sc->byte2 = 0; 537 if (tinfo->protocol_version <= SCSI_REV_2 538 && SCB_GET_LUN(scb) < 8) 539 sc->byte2 = SCB_GET_LUN(scb) << 5; 540 sc->unused[0] = 0; 541 sc->unused[1] = 0; 542 sc->length = sg->len; 543 sc->control = 0; 544 545 /* 546 * We can't allow the target to disconnect. 547 * This will be an untagged transaction and 548 * having the target disconnect will make this 549 * transaction indestinguishable from outstanding 550 * tagged transactions. 551 */ 552 hscb->control = 0; 553 554 /* 555 * This request sense could be because the 556 * the device lost power or in some other 557 * way has lost our transfer negotiations. 558 * Renegotiate if appropriate. Unit attention 559 * errors will be reported before any data 560 * phases occur. 561 */ 562 if (aic_get_residual(scb) 563 == aic_get_transfer_length(scb)) { 564 ahc_update_neg_request(ahc, &devinfo, 565 tstate, targ_info, 566 AHC_NEG_IF_NON_ASYNC); 567 } 568 if (tstate->auto_negotiate & devinfo.target_mask) { 569 hscb->control |= MK_MESSAGE; 570 scb->flags &= ~SCB_NEGOTIATE; 571 scb->flags |= SCB_AUTO_NEGOTIATE; 572 } 573 hscb->cdb_len = sizeof(*sc); 574 hscb->dataptr = sg->addr; 575 hscb->datacnt = sg->len; 576 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 577 hscb->sgptr = aic_htole32(hscb->sgptr); 578 scb->sg_count = 1; 579 scb->flags |= SCB_SENSE; 580 ahc_qinfifo_requeue_tail(ahc, scb); 581 ahc_outb(ahc, RETURN_1, SEND_SENSE); 582 /* 583 * Ensure we have enough time to actually 584 * retrieve the sense, but only schedule 585 * the timer if we are not in recovery or 586 * this is a recovery SCB that is allowed 587 * to have an active timer. 588 */ 589 if (ahc->scb_data->recovery_scbs == 0 590 || (scb->flags & SCB_RECOVERY_SCB) != 0) 591 aic_scb_timer_reset(scb, 5 * 1000000); 592 break; 593 } 594 default: 595 break; 596 } 597 break; 598 } 599 case NO_MATCH: 600 { 601 /* Ensure we don't leave the selection hardware on */ 602 ahc_outb(ahc, SCSISEQ, 603 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 604 605 printf("%s:%c:%d: no active SCB for reconnecting " 606 "target - issuing BUS DEVICE RESET\n", 607 ahc_name(ahc), devinfo.channel, devinfo.target); 608 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 609 "ARG_1 == 0x%x ACCUM = 0x%x\n", 610 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 611 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 612 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 613 "SINDEX == 0x%x\n", 614 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 615 ahc_index_busy_tcl(ahc, 616 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 617 ahc_inb(ahc, SAVED_LUN))), 618 ahc_inb(ahc, SINDEX)); 619 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 620 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 621 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 622 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 623 ahc_inb(ahc, SCB_CONTROL)); 624 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 625 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 626 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 627 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 628 ahc_dump_card_state(ahc); 629 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 630 ahc->msgout_len = 1; 631 ahc->msgout_index = 0; 632 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 633 ahc_outb(ahc, MSG_OUT, HOST_MSG); 634 ahc_assert_atn(ahc); 635 break; 636 } 637 case SEND_REJECT: 638 { 639 u_int rejbyte = ahc_inb(ahc, ACCUM); 640 printf("%s:%c:%d: Warning - unknown message received from " 641 "target (0x%x). Rejecting\n", 642 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 643 break; 644 } 645 case PROTO_VIOLATION: 646 { 647 ahc_handle_proto_violation(ahc); 648 break; 649 } 650 case IGN_WIDE_RES: 651 ahc_handle_ign_wide_residue(ahc, &devinfo); 652 break; 653 case PDATA_REINIT: 654 ahc_reinitialize_dataptrs(ahc); 655 break; 656 case BAD_PHASE: 657 { 658 u_int lastphase; 659 660 lastphase = ahc_inb(ahc, LASTPHASE); 661 printf("%s:%c:%d: unknown scsi bus phase %x, " 662 "lastphase = 0x%x. Attempting to continue\n", 663 ahc_name(ahc), devinfo.channel, devinfo.target, 664 lastphase, ahc_inb(ahc, SCSISIGI)); 665 break; 666 } 667 case MISSED_BUSFREE: 668 { 669 u_int lastphase; 670 671 lastphase = ahc_inb(ahc, LASTPHASE); 672 printf("%s:%c:%d: Missed busfree. " 673 "Lastphase = 0x%x, Curphase = 0x%x\n", 674 ahc_name(ahc), devinfo.channel, devinfo.target, 675 lastphase, ahc_inb(ahc, SCSISIGI)); 676 ahc_restart(ahc); 677 return; 678 } 679 case HOST_MSG_LOOP: 680 { 681 /* 682 * The sequencer has encountered a message phase 683 * that requires host assistance for completion. 684 * While handling the message phase(s), we will be 685 * notified by the sequencer after each byte is 686 * transfered so we can track bus phase changes. 687 * 688 * If this is the first time we've seen a HOST_MSG_LOOP 689 * interrupt, initialize the state of the host message 690 * loop. 691 */ 692 if (ahc->msg_type == MSG_TYPE_NONE) { 693 struct scb *scb; 694 u_int scb_index; 695 u_int bus_phase; 696 697 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 698 if (bus_phase != P_MESGIN 699 && bus_phase != P_MESGOUT) { 700 printf("ahc_intr: HOST_MSG_LOOP bad " 701 "phase 0x%x\n", 702 bus_phase); 703 /* 704 * Probably transitioned to bus free before 705 * we got here. Just punt the message. 706 */ 707 ahc_clear_intstat(ahc); 708 ahc_restart(ahc); 709 return; 710 } 711 712 scb_index = ahc_inb(ahc, SCB_TAG); 713 scb = ahc_lookup_scb(ahc, scb_index); 714 if (devinfo.role == ROLE_INITIATOR) { 715 if (scb == NULL) 716 panic("HOST_MSG_LOOP with " 717 "invalid SCB %x\n", scb_index); 718 719 if (bus_phase == P_MESGOUT) 720 ahc_setup_initiator_msgout(ahc, 721 &devinfo, 722 scb); 723 else { 724 ahc->msg_type = 725 MSG_TYPE_INITIATOR_MSGIN; 726 ahc->msgin_index = 0; 727 } 728 } 729 #ifdef AHC_TARGET_MODE 730 else { 731 if (bus_phase == P_MESGOUT) { 732 ahc->msg_type = 733 MSG_TYPE_TARGET_MSGOUT; 734 ahc->msgin_index = 0; 735 } 736 else 737 ahc_setup_target_msgin(ahc, 738 &devinfo, 739 scb); 740 } 741 #endif 742 } 743 744 ahc_handle_message_phase(ahc); 745 break; 746 } 747 case PERR_DETECTED: 748 { 749 /* 750 * If we've cleared the parity error interrupt 751 * but the sequencer still believes that SCSIPERR 752 * is true, it must be that the parity error is 753 * for the currently presented byte on the bus, 754 * and we are not in a phase (data-in) where we will 755 * eventually ack this byte. Ack the byte and 756 * throw it away in the hope that the target will 757 * take us to message out to deliver the appropriate 758 * error message. 759 */ 760 if ((intstat & SCSIINT) == 0 761 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 762 763 if ((ahc->features & AHC_DT) == 0) { 764 u_int curphase; 765 766 /* 767 * The hardware will only let you ack bytes 768 * if the expected phase in SCSISIGO matches 769 * the current phase. Make sure this is 770 * currently the case. 771 */ 772 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 773 ahc_outb(ahc, LASTPHASE, curphase); 774 ahc_outb(ahc, SCSISIGO, curphase); 775 } 776 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 777 int wait; 778 779 /* 780 * In a data phase. Faster to bitbucket 781 * the data than to individually ack each 782 * byte. This is also the only strategy 783 * that will work with AUTOACK enabled. 784 */ 785 ahc_outb(ahc, SXFRCTL1, 786 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 787 wait = 5000; 788 while (--wait != 0) { 789 if ((ahc_inb(ahc, SCSISIGI) 790 & (CDI|MSGI)) != 0) 791 break; 792 aic_delay(100); 793 } 794 ahc_outb(ahc, SXFRCTL1, 795 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 796 if (wait == 0) { 797 struct scb *scb; 798 u_int scb_index; 799 800 ahc_print_devinfo(ahc, &devinfo); 801 printf("Unable to clear parity error. " 802 "Resetting bus.\n"); 803 scb_index = ahc_inb(ahc, SCB_TAG); 804 scb = ahc_lookup_scb(ahc, scb_index); 805 if (scb != NULL) 806 aic_set_transaction_status(scb, 807 CAM_UNCOR_PARITY); 808 ahc_reset_channel(ahc, devinfo.channel, 809 /*init reset*/TRUE); 810 } 811 } else { 812 ahc_inb(ahc, SCSIDATL); 813 } 814 } 815 break; 816 } 817 case DATA_OVERRUN: 818 { 819 /* 820 * When the sequencer detects an overrun, it 821 * places the controller in "BITBUCKET" mode 822 * and allows the target to complete its transfer. 823 * Unfortunately, none of the counters get updated 824 * when the controller is in this mode, so we have 825 * no way of knowing how large the overrun was. 826 */ 827 u_int scbindex = ahc_inb(ahc, SCB_TAG); 828 u_int lastphase = ahc_inb(ahc, LASTPHASE); 829 u_int i; 830 831 scb = ahc_lookup_scb(ahc, scbindex); 832 for (i = 0; i < num_phases; i++) { 833 if (lastphase == ahc_phase_table[i].phase) 834 break; 835 } 836 ahc_print_path(ahc, scb); 837 printf("data overrun detected %s." 838 " Tag == 0x%x.\n", 839 ahc_phase_table[i].phasemsg, 840 scb->hscb->tag); 841 ahc_print_path(ahc, scb); 842 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 843 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 844 aic_get_transfer_length(scb), scb->sg_count); 845 if (scb->sg_count > 0) { 846 for (i = 0; i < scb->sg_count; i++) { 847 848 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 849 i, 850 (aic_le32toh(scb->sg_list[i].len) >> 24 851 & SG_HIGH_ADDR_BITS), 852 aic_le32toh(scb->sg_list[i].addr), 853 aic_le32toh(scb->sg_list[i].len) 854 & AHC_SG_LEN_MASK); 855 } 856 } 857 /* 858 * Set this and it will take effect when the 859 * target does a command complete. 860 */ 861 ahc_freeze_devq(ahc, scb); 862 if ((scb->flags & SCB_SENSE) == 0) { 863 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 864 } else { 865 scb->flags &= ~SCB_SENSE; 866 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 867 } 868 aic_freeze_scb(scb); 869 870 if ((ahc->features & AHC_ULTRA2) != 0) { 871 /* 872 * Clear the channel in case we return 873 * to data phase later. 874 */ 875 ahc_outb(ahc, SXFRCTL0, 876 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 877 ahc_outb(ahc, SXFRCTL0, 878 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 879 } 880 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 881 u_int dscommand1; 882 883 /* Ensure HHADDR is 0 for future DMA operations. */ 884 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 885 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 886 ahc_outb(ahc, HADDR, 0); 887 ahc_outb(ahc, DSCOMMAND1, dscommand1); 888 } 889 break; 890 } 891 case MKMSG_FAILED: 892 { 893 u_int scbindex; 894 895 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 896 ahc_name(ahc), devinfo.channel, devinfo.target, 897 devinfo.lun); 898 scbindex = ahc_inb(ahc, SCB_TAG); 899 scb = ahc_lookup_scb(ahc, scbindex); 900 if (scb != NULL 901 && (scb->flags & SCB_RECOVERY_SCB) != 0) 902 /* 903 * Ensure that we didn't put a second instance of this 904 * SCB into the QINFIFO. 905 */ 906 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 907 SCB_GET_CHANNEL(ahc, scb), 908 SCB_GET_LUN(scb), scb->hscb->tag, 909 ROLE_INITIATOR, /*status*/0, 910 SEARCH_REMOVE); 911 break; 912 } 913 case NO_FREE_SCB: 914 { 915 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 916 ahc_dump_card_state(ahc); 917 panic("for safety"); 918 break; 919 } 920 case SCB_MISMATCH: 921 { 922 u_int scbptr; 923 924 scbptr = ahc_inb(ahc, SCBPTR); 925 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 926 scbptr, ahc_inb(ahc, ARG_1), 927 ahc->scb_data->hscbs[scbptr].tag); 928 ahc_dump_card_state(ahc); 929 panic("for saftey"); 930 break; 931 } 932 case OUT_OF_RANGE: 933 { 934 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 935 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 936 "ARG_1 == 0x%x ACCUM = 0x%x\n", 937 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 938 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 939 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 940 "SINDEX == 0x%x\n, A == 0x%x\n", 941 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 942 ahc_index_busy_tcl(ahc, 943 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 944 ahc_inb(ahc, SAVED_LUN))), 945 ahc_inb(ahc, SINDEX), 946 ahc_inb(ahc, ACCUM)); 947 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 948 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 949 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 950 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 951 ahc_inb(ahc, SCB_CONTROL)); 952 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 953 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 954 ahc_dump_card_state(ahc); 955 panic("for safety"); 956 break; 957 } 958 default: 959 printf("ahc_intr: seqint, " 960 "intstat == 0x%x, scsisigi = 0x%x\n", 961 intstat, ahc_inb(ahc, SCSISIGI)); 962 break; 963 } 964 unpause: 965 /* 966 * The sequencer is paused immediately on 967 * a SEQINT, so we should restart it when 968 * we're done. 969 */ 970 ahc_unpause(ahc); 971 } 972 973 void 974 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 975 { 976 u_int scb_index; 977 u_int status0; 978 u_int status; 979 struct scb *scb; 980 char cur_channel; 981 char intr_channel; 982 983 if ((ahc->features & AHC_TWIN) != 0 984 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 985 cur_channel = 'B'; 986 else 987 cur_channel = 'A'; 988 intr_channel = cur_channel; 989 990 if ((ahc->features & AHC_ULTRA2) != 0) 991 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 992 else 993 status0 = 0; 994 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 995 if (status == 0 && status0 == 0) { 996 if ((ahc->features & AHC_TWIN) != 0) { 997 /* Try the other channel */ 998 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 999 status = ahc_inb(ahc, SSTAT1) 1000 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1001 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 1002 } 1003 if (status == 0) { 1004 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1005 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1006 ahc_unpause(ahc); 1007 return; 1008 } 1009 } 1010 1011 /* Make sure the sequencer is in a safe location. */ 1012 ahc_clear_critical_section(ahc); 1013 1014 scb_index = ahc_inb(ahc, SCB_TAG); 1015 scb = ahc_lookup_scb(ahc, scb_index); 1016 if (scb != NULL 1017 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1018 scb = NULL; 1019 1020 if ((ahc->features & AHC_ULTRA2) != 0 1021 && (status0 & IOERR) != 0) { 1022 int now_lvd; 1023 1024 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1025 printf("%s: Transceiver State Has Changed to %s mode\n", 1026 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1027 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1028 /* 1029 * When transitioning to SE mode, the reset line 1030 * glitches, triggering an arbitration bug in some 1031 * Ultra2 controllers. This bug is cleared when we 1032 * assert the reset line. Since a reset glitch has 1033 * already occurred with this transition and a 1034 * transceiver state change is handled just like 1035 * a bus reset anyway, asserting the reset line 1036 * ourselves is safe. 1037 */ 1038 ahc_reset_channel(ahc, intr_channel, 1039 /*Initiate Reset*/now_lvd == 0); 1040 } else if ((status & SCSIRSTI) != 0) { 1041 printf("%s: Someone reset channel %c\n", 1042 ahc_name(ahc), intr_channel); 1043 if (intr_channel != cur_channel) 1044 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1045 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1046 } else if ((status & SCSIPERR) != 0) { 1047 /* 1048 * Determine the bus phase and queue an appropriate message. 1049 * SCSIPERR is latched true as soon as a parity error 1050 * occurs. If the sequencer acked the transfer that 1051 * caused the parity error and the currently presented 1052 * transfer on the bus has correct parity, SCSIPERR will 1053 * be cleared by CLRSCSIPERR. Use this to determine if 1054 * we should look at the last phase the sequencer recorded, 1055 * or the current phase presented on the bus. 1056 */ 1057 struct ahc_devinfo devinfo; 1058 u_int mesg_out; 1059 u_int curphase; 1060 u_int errorphase; 1061 u_int lastphase; 1062 u_int scsirate; 1063 u_int i; 1064 u_int sstat2; 1065 int silent; 1066 1067 lastphase = ahc_inb(ahc, LASTPHASE); 1068 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1069 sstat2 = ahc_inb(ahc, SSTAT2); 1070 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1071 /* 1072 * For all phases save DATA, the sequencer won't 1073 * automatically ack a byte that has a parity error 1074 * in it. So the only way that the current phase 1075 * could be 'data-in' is if the parity error is for 1076 * an already acked byte in the data phase. During 1077 * synchronous data-in transfers, we may actually 1078 * ack bytes before latching the current phase in 1079 * LASTPHASE, leading to the discrepancy between 1080 * curphase and lastphase. 1081 */ 1082 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1083 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1084 errorphase = curphase; 1085 else 1086 errorphase = lastphase; 1087 1088 for (i = 0; i < num_phases; i++) { 1089 if (errorphase == ahc_phase_table[i].phase) 1090 break; 1091 } 1092 mesg_out = ahc_phase_table[i].mesg_out; 1093 silent = FALSE; 1094 if (scb != NULL) { 1095 if (SCB_IS_SILENT(scb)) 1096 silent = TRUE; 1097 else 1098 ahc_print_path(ahc, scb); 1099 scb->flags |= SCB_TRANSMISSION_ERROR; 1100 } else 1101 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1102 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1103 scsirate = ahc_inb(ahc, SCSIRATE); 1104 if (silent == FALSE) { 1105 printf("parity error detected %s. " 1106 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1107 ahc_phase_table[i].phasemsg, 1108 ahc_inw(ahc, SEQADDR0), 1109 scsirate); 1110 if ((ahc->features & AHC_DT) != 0) { 1111 if ((sstat2 & CRCVALERR) != 0) 1112 printf("\tCRC Value Mismatch\n"); 1113 if ((sstat2 & CRCENDERR) != 0) 1114 printf("\tNo terminal CRC packet " 1115 "recevied\n"); 1116 if ((sstat2 & CRCREQERR) != 0) 1117 printf("\tIllegal CRC packet " 1118 "request\n"); 1119 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1120 printf("\tUnexpected %sDT Data Phase\n", 1121 (scsirate & SINGLE_EDGE) 1122 ? "" : "non-"); 1123 } 1124 } 1125 1126 if ((ahc->features & AHC_DT) != 0 1127 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1128 /* 1129 * This error applies regardless of 1130 * data direction, so ignore the value 1131 * in the phase table. 1132 */ 1133 mesg_out = MSG_INITIATOR_DET_ERR; 1134 } 1135 1136 /* 1137 * We've set the hardware to assert ATN if we 1138 * get a parity error on "in" phases, so all we 1139 * need to do is stuff the message buffer with 1140 * the appropriate message. "In" phases have set 1141 * mesg_out to something other than MSG_NOP. 1142 */ 1143 if (mesg_out != MSG_NOOP) { 1144 if (ahc->msg_type != MSG_TYPE_NONE) 1145 ahc->send_msg_perror = TRUE; 1146 else 1147 ahc_outb(ahc, MSG_OUT, mesg_out); 1148 } 1149 /* 1150 * Force a renegotiation with this target just in 1151 * case we are out of sync for some external reason 1152 * unknown (or unreported) by the target. 1153 */ 1154 ahc_fetch_devinfo(ahc, &devinfo); 1155 ahc_force_renegotiation(ahc, &devinfo); 1156 1157 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1158 ahc_unpause(ahc); 1159 } else if ((status & SELTO) != 0) { 1160 u_int scbptr; 1161 1162 /* Stop the selection */ 1163 ahc_outb(ahc, SCSISEQ, 0); 1164 1165 /* No more pending messages */ 1166 ahc_clear_msg_state(ahc); 1167 1168 /* Clear interrupt state */ 1169 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1170 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1171 1172 /* 1173 * Although the driver does not care about the 1174 * 'Selection in Progress' status bit, the busy 1175 * LED does. SELINGO is only cleared by a sucessfull 1176 * selection, so we must manually clear it to insure 1177 * the LED turns off just incase no future successful 1178 * selections occur (e.g. no devices on the bus). 1179 */ 1180 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1181 1182 scbptr = ahc_inb(ahc, WAITING_SCBH); 1183 ahc_outb(ahc, SCBPTR, scbptr); 1184 scb_index = ahc_inb(ahc, SCB_TAG); 1185 1186 scb = ahc_lookup_scb(ahc, scb_index); 1187 if (scb == NULL) { 1188 printf("%s: ahc_intr - referenced scb not " 1189 "valid during SELTO scb(%d, %d)\n", 1190 ahc_name(ahc), scbptr, scb_index); 1191 ahc_dump_card_state(ahc); 1192 } else { 1193 struct ahc_devinfo devinfo; 1194 #ifdef AHC_DEBUG 1195 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1196 ahc_print_path(ahc, scb); 1197 printf("Saw Selection Timeout for SCB 0x%x\n", 1198 scb_index); 1199 } 1200 #endif 1201 ahc_scb_devinfo(ahc, &devinfo, scb); 1202 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1203 ahc_freeze_devq(ahc, scb); 1204 1205 /* 1206 * Cancel any pending transactions on the device 1207 * now that it seems to be missing. This will 1208 * also revert us to async/narrow transfers until 1209 * we can renegotiate with the device. 1210 */ 1211 ahc_handle_devreset(ahc, &devinfo, 1212 CAM_SEL_TIMEOUT, 1213 "Selection Timeout", 1214 /*verbose_level*/1); 1215 } 1216 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1217 ahc_restart(ahc); 1218 } else if ((status & BUSFREE) != 0 1219 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1220 struct ahc_devinfo devinfo; 1221 u_int lastphase; 1222 u_int saved_scsiid; 1223 u_int saved_lun; 1224 u_int target; 1225 u_int initiator_role_id; 1226 char channel; 1227 int printerror; 1228 1229 /* 1230 * Clear our selection hardware as soon as possible. 1231 * We may have an entry in the waiting Q for this target, 1232 * that is affected by this busfree and we don't want to 1233 * go about selecting the target while we handle the event. 1234 */ 1235 ahc_outb(ahc, SCSISEQ, 1236 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1237 1238 /* 1239 * Disable busfree interrupts and clear the busfree 1240 * interrupt status. We do this here so that several 1241 * bus transactions occur prior to clearing the SCSIINT 1242 * latch. It can take a bit for the clearing to take effect. 1243 */ 1244 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1245 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1246 1247 /* 1248 * Look at what phase we were last in. 1249 * If its message out, chances are pretty good 1250 * that the busfree was in response to one of 1251 * our abort requests. 1252 */ 1253 lastphase = ahc_inb(ahc, LASTPHASE); 1254 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1255 saved_lun = ahc_inb(ahc, SAVED_LUN); 1256 target = SCSIID_TARGET(ahc, saved_scsiid); 1257 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1258 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1259 ahc_compile_devinfo(&devinfo, initiator_role_id, 1260 target, saved_lun, channel, ROLE_INITIATOR); 1261 printerror = 1; 1262 1263 if (lastphase == P_MESGOUT) { 1264 u_int tag; 1265 1266 tag = SCB_LIST_NULL; 1267 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1268 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1269 if (ahc->msgout_buf[ahc->msgout_index - 1] 1270 == MSG_ABORT_TAG) 1271 tag = scb->hscb->tag; 1272 ahc_print_path(ahc, scb); 1273 printf("SCB %d - Abort%s Completed.\n", 1274 scb->hscb->tag, tag == SCB_LIST_NULL ? 1275 "" : " Tag"); 1276 ahc_abort_scbs(ahc, target, channel, 1277 saved_lun, tag, 1278 ROLE_INITIATOR, 1279 CAM_REQ_ABORTED); 1280 printerror = 0; 1281 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1282 MSG_BUS_DEV_RESET, TRUE)) { 1283 #ifdef __FreeBSD__ 1284 /* 1285 * Don't mark the user's request for this BDR 1286 * as completing with CAM_BDR_SENT. CAM3 1287 * specifies CAM_REQ_CMP. 1288 */ 1289 if (scb != NULL 1290 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1291 && ahc_match_scb(ahc, scb, target, channel, 1292 CAM_LUN_WILDCARD, 1293 SCB_LIST_NULL, 1294 ROLE_INITIATOR)) { 1295 aic_set_transaction_status(scb, CAM_REQ_CMP); 1296 } 1297 #endif 1298 ahc_compile_devinfo(&devinfo, 1299 initiator_role_id, 1300 target, 1301 CAM_LUN_WILDCARD, 1302 channel, 1303 ROLE_INITIATOR); 1304 ahc_handle_devreset(ahc, &devinfo, 1305 CAM_BDR_SENT, 1306 "Bus Device Reset", 1307 /*verbose_level*/0); 1308 printerror = 0; 1309 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1310 MSG_EXT_PPR, FALSE)) { 1311 struct ahc_initiator_tinfo *tinfo; 1312 struct ahc_tmode_tstate *tstate; 1313 1314 /* 1315 * PPR Rejected. Try non-ppr negotiation 1316 * and retry command. 1317 */ 1318 tinfo = ahc_fetch_transinfo(ahc, 1319 devinfo.channel, 1320 devinfo.our_scsiid, 1321 devinfo.target, 1322 &tstate); 1323 tinfo->curr.transport_version = 2; 1324 tinfo->goal.transport_version = 2; 1325 tinfo->goal.ppr_options = 0; 1326 ahc_qinfifo_requeue_tail(ahc, scb); 1327 printerror = 0; 1328 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1329 MSG_EXT_WDTR, FALSE)) { 1330 /* 1331 * Negotiation Rejected. Go-narrow and 1332 * retry command. 1333 */ 1334 ahc_set_width(ahc, &devinfo, 1335 MSG_EXT_WDTR_BUS_8_BIT, 1336 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1337 /*paused*/TRUE); 1338 ahc_qinfifo_requeue_tail(ahc, scb); 1339 printerror = 0; 1340 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1341 MSG_EXT_SDTR, FALSE)) { 1342 /* 1343 * Negotiation Rejected. Go-async and 1344 * retry command. 1345 */ 1346 ahc_set_syncrate(ahc, &devinfo, 1347 /*syncrate*/NULL, 1348 /*period*/0, /*offset*/0, 1349 /*ppr_options*/0, 1350 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1351 /*paused*/TRUE); 1352 ahc_qinfifo_requeue_tail(ahc, scb); 1353 printerror = 0; 1354 } 1355 } 1356 if (printerror != 0) { 1357 u_int i; 1358 1359 if (scb != NULL) { 1360 u_int tag; 1361 1362 if ((scb->hscb->control & TAG_ENB) != 0) 1363 tag = scb->hscb->tag; 1364 else 1365 tag = SCB_LIST_NULL; 1366 ahc_print_path(ahc, scb); 1367 ahc_abort_scbs(ahc, target, channel, 1368 SCB_GET_LUN(scb), tag, 1369 ROLE_INITIATOR, 1370 CAM_UNEXP_BUSFREE); 1371 } else { 1372 /* 1373 * We had not fully identified this connection, 1374 * so we cannot abort anything. 1375 */ 1376 printf("%s: ", ahc_name(ahc)); 1377 } 1378 for (i = 0; i < num_phases; i++) { 1379 if (lastphase == ahc_phase_table[i].phase) 1380 break; 1381 } 1382 if (lastphase != P_BUSFREE) { 1383 /* 1384 * Renegotiate with this device at the 1385 * next oportunity just in case this busfree 1386 * is due to a negotiation mismatch with the 1387 * device. 1388 */ 1389 ahc_force_renegotiation(ahc, &devinfo); 1390 } 1391 printf("Unexpected busfree %s\n" 1392 "SEQADDR == 0x%x\n", 1393 ahc_phase_table[i].phasemsg, 1394 ahc_inb(ahc, SEQADDR0) 1395 | (ahc_inb(ahc, SEQADDR1) << 8)); 1396 } 1397 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1398 ahc_restart(ahc); 1399 } else { 1400 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1401 ahc_name(ahc), status); 1402 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1403 } 1404 } 1405 1406 /* 1407 * Force renegotiation to occur the next time we initiate 1408 * a command to the current device. 1409 */ 1410 static void 1411 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1412 { 1413 struct ahc_initiator_tinfo *targ_info; 1414 struct ahc_tmode_tstate *tstate; 1415 1416 targ_info = ahc_fetch_transinfo(ahc, 1417 devinfo->channel, 1418 devinfo->our_scsiid, 1419 devinfo->target, 1420 &tstate); 1421 ahc_update_neg_request(ahc, devinfo, tstate, 1422 targ_info, AHC_NEG_IF_NON_ASYNC); 1423 } 1424 1425 #define AHC_MAX_STEPS 2000 1426 void 1427 ahc_clear_critical_section(struct ahc_softc *ahc) 1428 { 1429 int stepping; 1430 int steps; 1431 u_int simode0; 1432 u_int simode1; 1433 1434 if (ahc->num_critical_sections == 0) 1435 return; 1436 1437 stepping = FALSE; 1438 steps = 0; 1439 simode0 = 0; 1440 simode1 = 0; 1441 for (;;) { 1442 struct cs *cs; 1443 u_int seqaddr; 1444 u_int i; 1445 1446 seqaddr = ahc_inb(ahc, SEQADDR0) 1447 | (ahc_inb(ahc, SEQADDR1) << 8); 1448 1449 /* 1450 * Seqaddr represents the next instruction to execute, 1451 * so we are really executing the instruction just 1452 * before it. 1453 */ 1454 cs = ahc->critical_sections; 1455 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1456 1457 if (cs->begin < seqaddr && cs->end >= seqaddr) 1458 break; 1459 } 1460 1461 if (i == ahc->num_critical_sections) 1462 break; 1463 1464 if (steps > AHC_MAX_STEPS) { 1465 printf("%s: Infinite loop in critical section\n", 1466 ahc_name(ahc)); 1467 ahc_dump_card_state(ahc); 1468 panic("critical section loop"); 1469 } 1470 1471 steps++; 1472 if (stepping == FALSE) { 1473 1474 /* 1475 * Disable all interrupt sources so that the 1476 * sequencer will not be stuck by a pausing 1477 * interrupt condition while we attempt to 1478 * leave a critical section. 1479 */ 1480 simode0 = ahc_inb(ahc, SIMODE0); 1481 ahc_outb(ahc, SIMODE0, 0); 1482 simode1 = ahc_inb(ahc, SIMODE1); 1483 if ((ahc->features & AHC_DT) != 0) 1484 /* 1485 * On DT class controllers, we 1486 * use the enhanced busfree logic. 1487 * Unfortunately we cannot re-enable 1488 * busfree detection within the 1489 * current connection, so we must 1490 * leave it on while single stepping. 1491 */ 1492 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 1493 else 1494 ahc_outb(ahc, SIMODE1, 0); 1495 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1496 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1497 stepping = TRUE; 1498 } 1499 if ((ahc->features & AHC_DT) != 0) { 1500 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1501 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1502 } 1503 ahc_outb(ahc, HCNTRL, ahc->unpause); 1504 while (!ahc_is_paused(ahc)) 1505 aic_delay(200); 1506 } 1507 if (stepping) { 1508 ahc_outb(ahc, SIMODE0, simode0); 1509 ahc_outb(ahc, SIMODE1, simode1); 1510 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1511 } 1512 } 1513 1514 /* 1515 * Clear any pending interrupt status. 1516 */ 1517 void 1518 ahc_clear_intstat(struct ahc_softc *ahc) 1519 { 1520 /* Clear any interrupt conditions this may have caused */ 1521 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1522 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1523 CLRREQINIT); 1524 ahc_flush_device_writes(ahc); 1525 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1526 ahc_flush_device_writes(ahc); 1527 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1528 ahc_flush_device_writes(ahc); 1529 } 1530 1531 /**************************** Debugging Routines ******************************/ 1532 #ifdef AHC_DEBUG 1533 uint32_t ahc_debug = AHC_DEBUG_OPTS; 1534 #endif 1535 1536 void 1537 ahc_print_scb(struct scb *scb) 1538 { 1539 int i; 1540 1541 struct hardware_scb *hscb = scb->hscb; 1542 1543 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1544 (void *)scb, 1545 hscb->control, 1546 hscb->scsiid, 1547 hscb->lun, 1548 hscb->cdb_len); 1549 printf("Shared Data: "); 1550 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1551 printf("%#02x", hscb->shared_data.cdb[i]); 1552 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1553 aic_le32toh(hscb->dataptr), 1554 aic_le32toh(hscb->datacnt), 1555 aic_le32toh(hscb->sgptr), 1556 hscb->tag); 1557 if (scb->sg_count > 0) { 1558 for (i = 0; i < scb->sg_count; i++) { 1559 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1560 i, 1561 (aic_le32toh(scb->sg_list[i].len) >> 24 1562 & SG_HIGH_ADDR_BITS), 1563 aic_le32toh(scb->sg_list[i].addr), 1564 aic_le32toh(scb->sg_list[i].len)); 1565 } 1566 } 1567 } 1568 1569 /************************* Transfer Negotiation *******************************/ 1570 /* 1571 * Allocate per target mode instance (ID we respond to as a target) 1572 * transfer negotiation data structures. 1573 */ 1574 static struct ahc_tmode_tstate * 1575 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1576 { 1577 struct ahc_tmode_tstate *master_tstate; 1578 struct ahc_tmode_tstate *tstate; 1579 int i; 1580 1581 master_tstate = ahc->enabled_targets[ahc->our_id]; 1582 if (channel == 'B') { 1583 scsi_id += 8; 1584 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1585 } 1586 if (ahc->enabled_targets[scsi_id] != NULL 1587 && ahc->enabled_targets[scsi_id] != master_tstate) 1588 panic("%s: ahc_alloc_tstate - Target already allocated", 1589 ahc_name(ahc)); 1590 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1591 M_DEVBUF, M_NOWAIT); 1592 if (tstate == NULL) 1593 return (NULL); 1594 1595 /* 1596 * If we have allocated a master tstate, copy user settings from 1597 * the master tstate (taken from SRAM or the EEPROM) for this 1598 * channel, but reset our current and goal settings to async/narrow 1599 * until an initiator talks to us. 1600 */ 1601 if (master_tstate != NULL) { 1602 memcpy(tstate, master_tstate, sizeof(*tstate)); 1603 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1604 tstate->ultraenb = 0; 1605 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1606 memset(&tstate->transinfo[i].curr, 0, 1607 sizeof(tstate->transinfo[i].curr)); 1608 memset(&tstate->transinfo[i].goal, 0, 1609 sizeof(tstate->transinfo[i].goal)); 1610 } 1611 } else 1612 memset(tstate, 0, sizeof(*tstate)); 1613 ahc->enabled_targets[scsi_id] = tstate; 1614 return (tstate); 1615 } 1616 1617 #ifdef AHC_TARGET_MODE 1618 /* 1619 * Free per target mode instance (ID we respond to as a target) 1620 * transfer negotiation data structures. 1621 */ 1622 static void 1623 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1624 { 1625 struct ahc_tmode_tstate *tstate; 1626 1627 /* 1628 * Don't clean up our "master" tstate. 1629 * It has our default user settings. 1630 */ 1631 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1632 || (channel == 'A' && scsi_id == ahc->our_id)) 1633 && force == FALSE) 1634 return; 1635 1636 if (channel == 'B') 1637 scsi_id += 8; 1638 tstate = ahc->enabled_targets[scsi_id]; 1639 if (tstate != NULL) 1640 free(tstate, M_DEVBUF); 1641 ahc->enabled_targets[scsi_id] = NULL; 1642 } 1643 #endif 1644 1645 /* 1646 * Called when we have an active connection to a target on the bus, 1647 * this function finds the nearest syncrate to the input period limited 1648 * by the capabilities of the bus connectivity of and sync settings for 1649 * the target. 1650 */ 1651 struct ahc_syncrate * 1652 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1653 struct ahc_initiator_tinfo *tinfo, 1654 u_int *period, u_int *ppr_options, role_t role) 1655 { 1656 struct ahc_transinfo *transinfo; 1657 u_int maxsync; 1658 1659 if ((ahc->features & AHC_ULTRA2) != 0) { 1660 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1661 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1662 maxsync = AHC_SYNCRATE_DT; 1663 } else { 1664 maxsync = AHC_SYNCRATE_ULTRA; 1665 /* Can't do DT on an SE bus */ 1666 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1667 } 1668 } else if ((ahc->features & AHC_ULTRA) != 0) { 1669 maxsync = AHC_SYNCRATE_ULTRA; 1670 } else { 1671 maxsync = AHC_SYNCRATE_FAST; 1672 } 1673 /* 1674 * Never allow a value higher than our current goal 1675 * period otherwise we may allow a target initiated 1676 * negotiation to go above the limit as set by the 1677 * user. In the case of an initiator initiated 1678 * sync negotiation, we limit based on the user 1679 * setting. This allows the system to still accept 1680 * incoming negotiations even if target initiated 1681 * negotiation is not performed. 1682 */ 1683 if (role == ROLE_TARGET) 1684 transinfo = &tinfo->user; 1685 else 1686 transinfo = &tinfo->goal; 1687 *ppr_options &= transinfo->ppr_options; 1688 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1689 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1690 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1691 } 1692 if (transinfo->period == 0) { 1693 *period = 0; 1694 *ppr_options = 0; 1695 return (NULL); 1696 } 1697 *period = MAX(*period, transinfo->period); 1698 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1699 } 1700 1701 /* 1702 * Look up the valid period to SCSIRATE conversion in our table. 1703 * Return the period and offset that should be sent to the target 1704 * if this was the beginning of an SDTR. 1705 */ 1706 struct ahc_syncrate * 1707 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1708 u_int *ppr_options, u_int maxsync) 1709 { 1710 struct ahc_syncrate *syncrate; 1711 1712 if ((ahc->features & AHC_DT) == 0) 1713 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1714 1715 /* Skip all DT only entries if DT is not available */ 1716 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1717 && maxsync < AHC_SYNCRATE_ULTRA2) 1718 maxsync = AHC_SYNCRATE_ULTRA2; 1719 1720 for (syncrate = &ahc_syncrates[maxsync]; 1721 syncrate->rate != NULL; 1722 syncrate++) { 1723 1724 /* 1725 * The Ultra2 table doesn't go as low 1726 * as for the Fast/Ultra cards. 1727 */ 1728 if ((ahc->features & AHC_ULTRA2) != 0 1729 && (syncrate->sxfr_u2 == 0)) 1730 break; 1731 1732 if (*period <= syncrate->period) { 1733 /* 1734 * When responding to a target that requests 1735 * sync, the requested rate may fall between 1736 * two rates that we can output, but still be 1737 * a rate that we can receive. Because of this, 1738 * we want to respond to the target with 1739 * the same rate that it sent to us even 1740 * if the period we use to send data to it 1741 * is lower. Only lower the response period 1742 * if we must. 1743 */ 1744 if (syncrate == &ahc_syncrates[maxsync]) 1745 *period = syncrate->period; 1746 1747 /* 1748 * At some speeds, we only support 1749 * ST transfers. 1750 */ 1751 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1752 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1753 break; 1754 } 1755 } 1756 1757 if ((*period == 0) 1758 || (syncrate->rate == NULL) 1759 || ((ahc->features & AHC_ULTRA2) != 0 1760 && (syncrate->sxfr_u2 == 0))) { 1761 /* Use asynchronous transfers. */ 1762 *period = 0; 1763 syncrate = NULL; 1764 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1765 } 1766 return (syncrate); 1767 } 1768 1769 /* 1770 * Convert from an entry in our syncrate table to the SCSI equivalent 1771 * sync "period" factor. 1772 */ 1773 u_int 1774 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1775 { 1776 struct ahc_syncrate *syncrate; 1777 1778 if ((ahc->features & AHC_ULTRA2) != 0) 1779 scsirate &= SXFR_ULTRA2; 1780 else 1781 scsirate &= SXFR; 1782 1783 syncrate = &ahc_syncrates[maxsync]; 1784 while (syncrate->rate != NULL) { 1785 1786 if ((ahc->features & AHC_ULTRA2) != 0) { 1787 if (syncrate->sxfr_u2 == 0) 1788 break; 1789 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1790 return (syncrate->period); 1791 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1792 return (syncrate->period); 1793 } 1794 syncrate++; 1795 } 1796 return (0); /* async */ 1797 } 1798 1799 /* 1800 * Truncate the given synchronous offset to a value the 1801 * current adapter type and syncrate are capable of. 1802 */ 1803 void 1804 ahc_validate_offset(struct ahc_softc *ahc, 1805 struct ahc_initiator_tinfo *tinfo, 1806 struct ahc_syncrate *syncrate, 1807 u_int *offset, int wide, role_t role) 1808 { 1809 u_int maxoffset; 1810 1811 /* Limit offset to what we can do */ 1812 if (syncrate == NULL) { 1813 maxoffset = 0; 1814 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1815 maxoffset = MAX_OFFSET_ULTRA2; 1816 } else { 1817 if (wide) 1818 maxoffset = MAX_OFFSET_16BIT; 1819 else 1820 maxoffset = MAX_OFFSET_8BIT; 1821 } 1822 *offset = MIN(*offset, maxoffset); 1823 if (tinfo != NULL) { 1824 if (role == ROLE_TARGET) 1825 *offset = MIN(*offset, tinfo->user.offset); 1826 else 1827 *offset = MIN(*offset, tinfo->goal.offset); 1828 } 1829 } 1830 1831 /* 1832 * Truncate the given transfer width parameter to a value the 1833 * current adapter type is capable of. 1834 */ 1835 void 1836 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1837 u_int *bus_width, role_t role) 1838 { 1839 switch (*bus_width) { 1840 default: 1841 if (ahc->features & AHC_WIDE) { 1842 /* Respond Wide */ 1843 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1844 break; 1845 } 1846 /* FALLTHROUGH */ 1847 case MSG_EXT_WDTR_BUS_8_BIT: 1848 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1849 break; 1850 } 1851 if (tinfo != NULL) { 1852 if (role == ROLE_TARGET) 1853 *bus_width = MIN(tinfo->user.width, *bus_width); 1854 else 1855 *bus_width = MIN(tinfo->goal.width, *bus_width); 1856 } 1857 } 1858 1859 /* 1860 * Update the bitmask of targets for which the controller should 1861 * negotiate with at the next convenient oportunity. This currently 1862 * means the next time we send the initial identify messages for 1863 * a new transaction. 1864 */ 1865 int 1866 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1867 struct ahc_tmode_tstate *tstate, 1868 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1869 { 1870 u_int auto_negotiate_orig; 1871 1872 auto_negotiate_orig = tstate->auto_negotiate; 1873 if (neg_type == AHC_NEG_ALWAYS) { 1874 /* 1875 * Force our "current" settings to be 1876 * unknown so that unless a bus reset 1877 * occurs the need to renegotiate is 1878 * recorded persistently. 1879 */ 1880 if ((ahc->features & AHC_WIDE) != 0) 1881 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1882 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1883 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1884 } 1885 if (tinfo->curr.period != tinfo->goal.period 1886 || tinfo->curr.width != tinfo->goal.width 1887 || tinfo->curr.offset != tinfo->goal.offset 1888 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1889 || (neg_type == AHC_NEG_IF_NON_ASYNC 1890 && (tinfo->goal.offset != 0 1891 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1892 || tinfo->goal.ppr_options != 0))) 1893 tstate->auto_negotiate |= devinfo->target_mask; 1894 else 1895 tstate->auto_negotiate &= ~devinfo->target_mask; 1896 1897 return (auto_negotiate_orig != tstate->auto_negotiate); 1898 } 1899 1900 /* 1901 * Update the user/goal/curr tables of synchronous negotiation 1902 * parameters as well as, in the case of a current or active update, 1903 * any data structures on the host controller. In the case of an 1904 * active update, the specified target is currently talking to us on 1905 * the bus, so the transfer parameter update must take effect 1906 * immediately. 1907 */ 1908 void 1909 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1910 struct ahc_syncrate *syncrate, u_int period, 1911 u_int offset, u_int ppr_options, u_int type, int paused) 1912 { 1913 struct ahc_initiator_tinfo *tinfo; 1914 struct ahc_tmode_tstate *tstate; 1915 u_int old_period; 1916 u_int old_offset; 1917 u_int old_ppr; 1918 int active; 1919 int update_needed; 1920 1921 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1922 update_needed = 0; 1923 1924 if (syncrate == NULL) { 1925 period = 0; 1926 offset = 0; 1927 } 1928 1929 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1930 devinfo->target, &tstate); 1931 1932 if ((type & AHC_TRANS_USER) != 0) { 1933 tinfo->user.period = period; 1934 tinfo->user.offset = offset; 1935 tinfo->user.ppr_options = ppr_options; 1936 } 1937 1938 if ((type & AHC_TRANS_GOAL) != 0) { 1939 tinfo->goal.period = period; 1940 tinfo->goal.offset = offset; 1941 tinfo->goal.ppr_options = ppr_options; 1942 } 1943 1944 old_period = tinfo->curr.period; 1945 old_offset = tinfo->curr.offset; 1946 old_ppr = tinfo->curr.ppr_options; 1947 1948 if ((type & AHC_TRANS_CUR) != 0 1949 && (old_period != period 1950 || old_offset != offset 1951 || old_ppr != ppr_options)) { 1952 u_int scsirate; 1953 1954 update_needed++; 1955 scsirate = tinfo->scsirate; 1956 if ((ahc->features & AHC_ULTRA2) != 0) { 1957 1958 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1959 if (syncrate != NULL) { 1960 scsirate |= syncrate->sxfr_u2; 1961 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1962 scsirate |= ENABLE_CRC; 1963 else 1964 scsirate |= SINGLE_EDGE; 1965 } 1966 } else { 1967 1968 scsirate &= ~(SXFR|SOFS); 1969 /* 1970 * Ensure Ultra mode is set properly for 1971 * this target. 1972 */ 1973 tstate->ultraenb &= ~devinfo->target_mask; 1974 if (syncrate != NULL) { 1975 if (syncrate->sxfr & ULTRA_SXFR) { 1976 tstate->ultraenb |= 1977 devinfo->target_mask; 1978 } 1979 scsirate |= syncrate->sxfr & SXFR; 1980 scsirate |= offset & SOFS; 1981 } 1982 if (active) { 1983 u_int sxfrctl0; 1984 1985 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1986 sxfrctl0 &= ~FAST20; 1987 if (tstate->ultraenb & devinfo->target_mask) 1988 sxfrctl0 |= FAST20; 1989 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1990 } 1991 } 1992 if (active) { 1993 ahc_outb(ahc, SCSIRATE, scsirate); 1994 if ((ahc->features & AHC_ULTRA2) != 0) 1995 ahc_outb(ahc, SCSIOFFSET, offset); 1996 } 1997 1998 tinfo->scsirate = scsirate; 1999 tinfo->curr.period = period; 2000 tinfo->curr.offset = offset; 2001 tinfo->curr.ppr_options = ppr_options; 2002 2003 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2004 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2005 if (bootverbose) { 2006 if (offset != 0) { 2007 printf("%s: target %d synchronous at %sMHz%s, " 2008 "offset = 0x%x\n", ahc_name(ahc), 2009 devinfo->target, syncrate->rate, 2010 (ppr_options & MSG_EXT_PPR_DT_REQ) 2011 ? " DT" : "", offset); 2012 } else { 2013 printf("%s: target %d using " 2014 "asynchronous transfers\n", 2015 ahc_name(ahc), devinfo->target); 2016 } 2017 } 2018 } 2019 2020 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2021 tinfo, AHC_NEG_TO_GOAL); 2022 2023 if (update_needed) 2024 ahc_update_pending_scbs(ahc); 2025 } 2026 2027 /* 2028 * Update the user/goal/curr tables of wide negotiation 2029 * parameters as well as, in the case of a current or active update, 2030 * any data structures on the host controller. In the case of an 2031 * active update, the specified target is currently talking to us on 2032 * the bus, so the transfer parameter update must take effect 2033 * immediately. 2034 */ 2035 void 2036 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2037 u_int width, u_int type, int paused) 2038 { 2039 struct ahc_initiator_tinfo *tinfo; 2040 struct ahc_tmode_tstate *tstate; 2041 u_int oldwidth; 2042 int active; 2043 int update_needed; 2044 2045 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2046 update_needed = 0; 2047 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2048 devinfo->target, &tstate); 2049 2050 if ((type & AHC_TRANS_USER) != 0) 2051 tinfo->user.width = width; 2052 2053 if ((type & AHC_TRANS_GOAL) != 0) 2054 tinfo->goal.width = width; 2055 2056 oldwidth = tinfo->curr.width; 2057 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2058 u_int scsirate; 2059 2060 update_needed++; 2061 scsirate = tinfo->scsirate; 2062 scsirate &= ~WIDEXFER; 2063 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2064 scsirate |= WIDEXFER; 2065 2066 tinfo->scsirate = scsirate; 2067 2068 if (active) 2069 ahc_outb(ahc, SCSIRATE, scsirate); 2070 2071 tinfo->curr.width = width; 2072 2073 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2074 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2075 if (bootverbose) { 2076 printf("%s: target %d using %dbit transfers\n", 2077 ahc_name(ahc), devinfo->target, 2078 8 * (0x01 << width)); 2079 } 2080 } 2081 2082 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2083 tinfo, AHC_NEG_TO_GOAL); 2084 if (update_needed) 2085 ahc_update_pending_scbs(ahc); 2086 } 2087 2088 /* 2089 * Update the current state of tagged queuing for a given target. 2090 */ 2091 void 2092 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2093 ahc_queue_alg alg) 2094 { 2095 ahc_platform_set_tags(ahc, devinfo, alg); 2096 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2097 devinfo->lun, AC_TRANSFER_NEG, &alg); 2098 } 2099 2100 /* 2101 * When the transfer settings for a connection change, update any 2102 * in-transit SCBs to contain the new data so the hardware will 2103 * be set correctly during future (re)selections. 2104 */ 2105 static void 2106 ahc_update_pending_scbs(struct ahc_softc *ahc) 2107 { 2108 struct scb *pending_scb; 2109 int pending_scb_count; 2110 int i; 2111 int paused; 2112 u_int saved_scbptr; 2113 2114 /* 2115 * Traverse the pending SCB list and ensure that all of the 2116 * SCBs there have the proper settings. 2117 */ 2118 pending_scb_count = 0; 2119 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2120 struct ahc_devinfo devinfo; 2121 struct hardware_scb *pending_hscb; 2122 struct ahc_initiator_tinfo *tinfo; 2123 struct ahc_tmode_tstate *tstate; 2124 2125 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2126 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2127 devinfo.our_scsiid, 2128 devinfo.target, &tstate); 2129 pending_hscb = pending_scb->hscb; 2130 pending_hscb->control &= ~ULTRAENB; 2131 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2132 pending_hscb->control |= ULTRAENB; 2133 pending_hscb->scsirate = tinfo->scsirate; 2134 pending_hscb->scsioffset = tinfo->curr.offset; 2135 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2136 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2137 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2138 pending_hscb->control &= ~MK_MESSAGE; 2139 } 2140 ahc_sync_scb(ahc, pending_scb, 2141 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2142 pending_scb_count++; 2143 } 2144 2145 if (pending_scb_count == 0) 2146 return; 2147 2148 if (ahc_is_paused(ahc)) { 2149 paused = 1; 2150 } else { 2151 paused = 0; 2152 ahc_pause(ahc); 2153 } 2154 2155 saved_scbptr = ahc_inb(ahc, SCBPTR); 2156 /* Ensure that the hscbs down on the card match the new information */ 2157 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2158 struct hardware_scb *pending_hscb; 2159 u_int control; 2160 u_int scb_tag; 2161 2162 ahc_outb(ahc, SCBPTR, i); 2163 scb_tag = ahc_inb(ahc, SCB_TAG); 2164 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2165 if (pending_scb == NULL) 2166 continue; 2167 2168 pending_hscb = pending_scb->hscb; 2169 control = ahc_inb(ahc, SCB_CONTROL); 2170 control &= ~(ULTRAENB|MK_MESSAGE); 2171 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2172 ahc_outb(ahc, SCB_CONTROL, control); 2173 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2174 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2175 } 2176 ahc_outb(ahc, SCBPTR, saved_scbptr); 2177 2178 if (paused == 0) 2179 ahc_unpause(ahc); 2180 } 2181 2182 /**************************** Pathing Information *****************************/ 2183 static void 2184 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2185 { 2186 u_int saved_scsiid; 2187 role_t role; 2188 int our_id; 2189 2190 if (ahc_inb(ahc, SSTAT0) & TARGET) 2191 role = ROLE_TARGET; 2192 else 2193 role = ROLE_INITIATOR; 2194 2195 if (role == ROLE_TARGET 2196 && (ahc->features & AHC_MULTI_TID) != 0 2197 && (ahc_inb(ahc, SEQ_FLAGS) 2198 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2199 /* We were selected, so pull our id from TARGIDIN */ 2200 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2201 } else if ((ahc->features & AHC_ULTRA2) != 0) 2202 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2203 else 2204 our_id = ahc_inb(ahc, SCSIID) & OID; 2205 2206 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2207 ahc_compile_devinfo(devinfo, 2208 our_id, 2209 SCSIID_TARGET(ahc, saved_scsiid), 2210 ahc_inb(ahc, SAVED_LUN), 2211 SCSIID_CHANNEL(ahc, saved_scsiid), 2212 role); 2213 } 2214 2215 struct ahc_phase_table_entry* 2216 ahc_lookup_phase_entry(int phase) 2217 { 2218 struct ahc_phase_table_entry *entry; 2219 struct ahc_phase_table_entry *last_entry; 2220 2221 /* 2222 * num_phases doesn't include the default entry which 2223 * will be returned if the phase doesn't match. 2224 */ 2225 last_entry = &ahc_phase_table[num_phases]; 2226 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2227 if (phase == entry->phase) 2228 break; 2229 } 2230 return (entry); 2231 } 2232 2233 void 2234 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2235 u_int lun, char channel, role_t role) 2236 { 2237 devinfo->our_scsiid = our_id; 2238 devinfo->target = target; 2239 devinfo->lun = lun; 2240 devinfo->target_offset = target; 2241 devinfo->channel = channel; 2242 devinfo->role = role; 2243 if (channel == 'B') 2244 devinfo->target_offset += 8; 2245 devinfo->target_mask = (0x01 << devinfo->target_offset); 2246 } 2247 2248 void 2249 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2250 { 2251 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2252 devinfo->target, devinfo->lun); 2253 } 2254 2255 static void 2256 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2257 struct scb *scb) 2258 { 2259 role_t role; 2260 int our_id; 2261 2262 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2263 role = ROLE_INITIATOR; 2264 if ((scb->flags & SCB_TARGET_SCB) != 0) 2265 role = ROLE_TARGET; 2266 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2267 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2268 } 2269 2270 2271 /************************ Message Phase Processing ****************************/ 2272 static void 2273 ahc_assert_atn(struct ahc_softc *ahc) 2274 { 2275 u_int scsisigo; 2276 2277 scsisigo = ATNO; 2278 if ((ahc->features & AHC_DT) == 0) 2279 scsisigo |= ahc_inb(ahc, SCSISIGI); 2280 ahc_outb(ahc, SCSISIGO, scsisigo); 2281 } 2282 2283 /* 2284 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2285 * or enters the initial message out phase, we are interrupted. Fill our 2286 * outgoing message buffer with the appropriate message and beging handing 2287 * the message phase(s) manually. 2288 */ 2289 static void 2290 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2291 struct scb *scb) 2292 { 2293 /* 2294 * To facilitate adding multiple messages together, 2295 * each routine should increment the index and len 2296 * variables instead of setting them explicitly. 2297 */ 2298 ahc->msgout_index = 0; 2299 ahc->msgout_len = 0; 2300 2301 if ((scb->flags & SCB_DEVICE_RESET) == 0 2302 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2303 u_int identify_msg; 2304 2305 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2306 if ((scb->hscb->control & DISCENB) != 0) 2307 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2308 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2309 ahc->msgout_len++; 2310 2311 if ((scb->hscb->control & TAG_ENB) != 0) { 2312 ahc->msgout_buf[ahc->msgout_index++] = 2313 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2314 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2315 ahc->msgout_len += 2; 2316 } 2317 } 2318 2319 if (scb->flags & SCB_DEVICE_RESET) { 2320 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2321 ahc->msgout_len++; 2322 ahc_print_path(ahc, scb); 2323 printf("Bus Device Reset Message Sent\n"); 2324 /* 2325 * Clear our selection hardware in advance of 2326 * the busfree. We may have an entry in the waiting 2327 * Q for this target, and we don't want to go about 2328 * selecting while we handle the busfree and blow it 2329 * away. 2330 */ 2331 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2332 } else if ((scb->flags & SCB_ABORT) != 0) { 2333 if ((scb->hscb->control & TAG_ENB) != 0) 2334 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2335 else 2336 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2337 ahc->msgout_len++; 2338 ahc_print_path(ahc, scb); 2339 printf("Abort%s Message Sent\n", 2340 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2341 /* 2342 * Clear our selection hardware in advance of 2343 * the busfree. We may have an entry in the waiting 2344 * Q for this target, and we don't want to go about 2345 * selecting while we handle the busfree and blow it 2346 * away. 2347 */ 2348 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2349 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2350 ahc_build_transfer_msg(ahc, devinfo); 2351 } else { 2352 printf("ahc_intr: AWAITING_MSG for an SCB that " 2353 "does not have a waiting message\n"); 2354 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2355 devinfo->target_mask); 2356 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2357 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2358 ahc_inb(ahc, MSG_OUT), scb->flags); 2359 } 2360 2361 /* 2362 * Clear the MK_MESSAGE flag from the SCB so we aren't 2363 * asked to send this message again. 2364 */ 2365 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2366 scb->hscb->control &= ~MK_MESSAGE; 2367 ahc->msgout_index = 0; 2368 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2369 } 2370 2371 /* 2372 * Build an appropriate transfer negotiation message for the 2373 * currently active target. 2374 */ 2375 static void 2376 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2377 { 2378 /* 2379 * We need to initiate transfer negotiations. 2380 * If our current and goal settings are identical, 2381 * we want to renegotiate due to a check condition. 2382 */ 2383 struct ahc_initiator_tinfo *tinfo; 2384 struct ahc_tmode_tstate *tstate; 2385 struct ahc_syncrate *rate; 2386 int dowide; 2387 int dosync; 2388 int doppr; 2389 u_int period; 2390 u_int ppr_options; 2391 u_int offset; 2392 2393 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2394 devinfo->target, &tstate); 2395 /* 2396 * Filter our period based on the current connection. 2397 * If we can't perform DT transfers on this segment (not in LVD 2398 * mode for instance), then our decision to issue a PPR message 2399 * may change. 2400 */ 2401 period = tinfo->goal.period; 2402 offset = tinfo->goal.offset; 2403 ppr_options = tinfo->goal.ppr_options; 2404 /* Target initiated PPR is not allowed in the SCSI spec */ 2405 if (devinfo->role == ROLE_TARGET) 2406 ppr_options = 0; 2407 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2408 &ppr_options, devinfo->role); 2409 dowide = tinfo->curr.width != tinfo->goal.width; 2410 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2411 /* 2412 * Only use PPR if we have options that need it, even if the device 2413 * claims to support it. There might be an expander in the way 2414 * that doesn't. 2415 */ 2416 doppr = ppr_options != 0; 2417 2418 if (!dowide && !dosync && !doppr) { 2419 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2420 dosync = tinfo->goal.offset != 0; 2421 } 2422 2423 if (!dowide && !dosync && !doppr) { 2424 /* 2425 * Force async with a WDTR message if we have a wide bus, 2426 * or just issue an SDTR with a 0 offset. 2427 */ 2428 if ((ahc->features & AHC_WIDE) != 0) 2429 dowide = 1; 2430 else 2431 dosync = 1; 2432 2433 if (bootverbose) { 2434 ahc_print_devinfo(ahc, devinfo); 2435 printf("Ensuring async\n"); 2436 } 2437 } 2438 2439 /* Target initiated PPR is not allowed in the SCSI spec */ 2440 if (devinfo->role == ROLE_TARGET) 2441 doppr = 0; 2442 2443 /* 2444 * Both the PPR message and SDTR message require the 2445 * goal syncrate to be limited to what the target device 2446 * is capable of handling (based on whether an LVD->SE 2447 * expander is on the bus), so combine these two cases. 2448 * Regardless, guarantee that if we are using WDTR and SDTR 2449 * messages that WDTR comes first. 2450 */ 2451 if (doppr || (dosync && !dowide)) { 2452 2453 offset = tinfo->goal.offset; 2454 ahc_validate_offset(ahc, tinfo, rate, &offset, 2455 doppr ? tinfo->goal.width 2456 : tinfo->curr.width, 2457 devinfo->role); 2458 if (doppr) { 2459 ahc_construct_ppr(ahc, devinfo, period, offset, 2460 tinfo->goal.width, ppr_options); 2461 } else { 2462 ahc_construct_sdtr(ahc, devinfo, period, offset); 2463 } 2464 } else { 2465 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2466 } 2467 } 2468 2469 /* 2470 * Build a synchronous negotiation message in our message 2471 * buffer based on the input parameters. 2472 */ 2473 static void 2474 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2475 u_int period, u_int offset) 2476 { 2477 if (offset == 0) 2478 period = AHC_ASYNC_XFER_PERIOD; 2479 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2482 ahc->msgout_buf[ahc->msgout_index++] = period; 2483 ahc->msgout_buf[ahc->msgout_index++] = offset; 2484 ahc->msgout_len += 5; 2485 if (bootverbose) { 2486 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2487 ahc_name(ahc), devinfo->channel, devinfo->target, 2488 devinfo->lun, period, offset); 2489 } 2490 } 2491 2492 /* 2493 * Build a wide negotiation message in our message 2494 * buffer based on the input parameters. 2495 */ 2496 static void 2497 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2498 u_int bus_width) 2499 { 2500 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2501 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2502 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2503 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2504 ahc->msgout_len += 4; 2505 if (bootverbose) { 2506 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2507 ahc_name(ahc), devinfo->channel, devinfo->target, 2508 devinfo->lun, bus_width); 2509 } 2510 } 2511 2512 /* 2513 * Build a parallel protocol request message in our message 2514 * buffer based on the input parameters. 2515 */ 2516 static void 2517 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2518 u_int period, u_int offset, u_int bus_width, 2519 u_int ppr_options) 2520 { 2521 if (offset == 0) 2522 period = AHC_ASYNC_XFER_PERIOD; 2523 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2524 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2525 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2526 ahc->msgout_buf[ahc->msgout_index++] = period; 2527 ahc->msgout_buf[ahc->msgout_index++] = 0; 2528 ahc->msgout_buf[ahc->msgout_index++] = offset; 2529 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2530 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2531 ahc->msgout_len += 8; 2532 if (bootverbose) { 2533 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2534 "offset %x, ppr_options %x\n", ahc_name(ahc), 2535 devinfo->channel, devinfo->target, devinfo->lun, 2536 bus_width, period, offset, ppr_options); 2537 } 2538 } 2539 2540 /* 2541 * Clear any active message state. 2542 */ 2543 static void 2544 ahc_clear_msg_state(struct ahc_softc *ahc) 2545 { 2546 ahc->msgout_len = 0; 2547 ahc->msgin_index = 0; 2548 ahc->msg_type = MSG_TYPE_NONE; 2549 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2550 /* 2551 * The target didn't care to respond to our 2552 * message request, so clear ATN. 2553 */ 2554 ahc_outb(ahc, CLRSINT1, CLRATNO); 2555 } 2556 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2557 ahc_outb(ahc, SEQ_FLAGS2, 2558 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2559 } 2560 2561 static void 2562 ahc_handle_proto_violation(struct ahc_softc *ahc) 2563 { 2564 struct ahc_devinfo devinfo; 2565 struct scb *scb; 2566 u_int scbid; 2567 u_int seq_flags; 2568 u_int curphase; 2569 u_int lastphase; 2570 int found; 2571 2572 ahc_fetch_devinfo(ahc, &devinfo); 2573 scbid = ahc_inb(ahc, SCB_TAG); 2574 scb = ahc_lookup_scb(ahc, scbid); 2575 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2576 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2577 lastphase = ahc_inb(ahc, LASTPHASE); 2578 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2579 2580 /* 2581 * The reconnecting target either did not send an 2582 * identify message, or did, but we didn't find an SCB 2583 * to match. 2584 */ 2585 ahc_print_devinfo(ahc, &devinfo); 2586 printf("Target did not send an IDENTIFY message. " 2587 "LASTPHASE = 0x%x.\n", lastphase); 2588 scb = NULL; 2589 } else if (scb == NULL) { 2590 /* 2591 * We don't seem to have an SCB active for this 2592 * transaction. Print an error and reset the bus. 2593 */ 2594 ahc_print_devinfo(ahc, &devinfo); 2595 printf("No SCB found during protocol violation\n"); 2596 goto proto_violation_reset; 2597 } else { 2598 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2599 if ((seq_flags & NO_CDB_SENT) != 0) { 2600 ahc_print_path(ahc, scb); 2601 printf("No or incomplete CDB sent to device.\n"); 2602 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2603 /* 2604 * The target never bothered to provide status to 2605 * us prior to completing the command. Since we don't 2606 * know the disposition of this command, we must attempt 2607 * to abort it. Assert ATN and prepare to send an abort 2608 * message. 2609 */ 2610 ahc_print_path(ahc, scb); 2611 printf("Completed command without status.\n"); 2612 } else { 2613 ahc_print_path(ahc, scb); 2614 printf("Unknown protocol violation.\n"); 2615 ahc_dump_card_state(ahc); 2616 } 2617 } 2618 if ((lastphase & ~P_DATAIN_DT) == 0 2619 || lastphase == P_COMMAND) { 2620 proto_violation_reset: 2621 /* 2622 * Target either went directly to data/command 2623 * phase or didn't respond to our ATN. 2624 * The only safe thing to do is to blow 2625 * it away with a bus reset. 2626 */ 2627 found = ahc_reset_channel(ahc, 'A', TRUE); 2628 printf("%s: Issued Channel %c Bus Reset. " 2629 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2630 } else { 2631 /* 2632 * Leave the selection hardware off in case 2633 * this abort attempt will affect yet to 2634 * be sent commands. 2635 */ 2636 ahc_outb(ahc, SCSISEQ, 2637 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2638 ahc_assert_atn(ahc); 2639 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2640 if (scb == NULL) { 2641 ahc_print_devinfo(ahc, &devinfo); 2642 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2643 ahc->msgout_len = 1; 2644 ahc->msgout_index = 0; 2645 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2646 } else { 2647 ahc_print_path(ahc, scb); 2648 scb->flags |= SCB_ABORT; 2649 } 2650 printf("Protocol violation %s. Attempting to abort.\n", 2651 ahc_lookup_phase_entry(curphase)->phasemsg); 2652 } 2653 } 2654 2655 /* 2656 * Manual message loop handler. 2657 */ 2658 static void 2659 ahc_handle_message_phase(struct ahc_softc *ahc) 2660 { 2661 struct ahc_devinfo devinfo; 2662 u_int bus_phase; 2663 int end_session; 2664 2665 ahc_fetch_devinfo(ahc, &devinfo); 2666 end_session = FALSE; 2667 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2668 2669 reswitch: 2670 switch (ahc->msg_type) { 2671 case MSG_TYPE_INITIATOR_MSGOUT: 2672 { 2673 int lastbyte; 2674 int phasemis; 2675 int msgdone; 2676 2677 if (ahc->msgout_len == 0) 2678 panic("HOST_MSG_LOOP interrupt with no active message"); 2679 2680 #ifdef AHC_DEBUG 2681 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2682 ahc_print_devinfo(ahc, &devinfo); 2683 printf("INITIATOR_MSG_OUT"); 2684 } 2685 #endif 2686 phasemis = bus_phase != P_MESGOUT; 2687 if (phasemis) { 2688 #ifdef AHC_DEBUG 2689 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2690 printf(" PHASEMIS %s\n", 2691 ahc_lookup_phase_entry(bus_phase) 2692 ->phasemsg); 2693 } 2694 #endif 2695 if (bus_phase == P_MESGIN) { 2696 /* 2697 * Change gears and see if 2698 * this messages is of interest to 2699 * us or should be passed back to 2700 * the sequencer. 2701 */ 2702 ahc_outb(ahc, CLRSINT1, CLRATNO); 2703 ahc->send_msg_perror = FALSE; 2704 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2705 ahc->msgin_index = 0; 2706 goto reswitch; 2707 } 2708 end_session = TRUE; 2709 break; 2710 } 2711 2712 if (ahc->send_msg_perror) { 2713 ahc_outb(ahc, CLRSINT1, CLRATNO); 2714 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2715 #ifdef AHC_DEBUG 2716 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2717 printf(" byte 0x%x\n", ahc->send_msg_perror); 2718 #endif 2719 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2720 break; 2721 } 2722 2723 msgdone = ahc->msgout_index == ahc->msgout_len; 2724 if (msgdone) { 2725 /* 2726 * The target has requested a retry. 2727 * Re-assert ATN, reset our message index to 2728 * 0, and try again. 2729 */ 2730 ahc->msgout_index = 0; 2731 ahc_assert_atn(ahc); 2732 } 2733 2734 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2735 if (lastbyte) { 2736 /* Last byte is signified by dropping ATN */ 2737 ahc_outb(ahc, CLRSINT1, CLRATNO); 2738 } 2739 2740 /* 2741 * Clear our interrupt status and present 2742 * the next byte on the bus. 2743 */ 2744 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2745 #ifdef AHC_DEBUG 2746 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2747 printf(" byte 0x%x\n", 2748 ahc->msgout_buf[ahc->msgout_index]); 2749 #endif 2750 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2751 break; 2752 } 2753 case MSG_TYPE_INITIATOR_MSGIN: 2754 { 2755 int phasemis; 2756 int message_done; 2757 2758 #ifdef AHC_DEBUG 2759 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2760 ahc_print_devinfo(ahc, &devinfo); 2761 printf("INITIATOR_MSG_IN"); 2762 } 2763 #endif 2764 phasemis = bus_phase != P_MESGIN; 2765 if (phasemis) { 2766 #ifdef AHC_DEBUG 2767 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2768 printf(" PHASEMIS %s\n", 2769 ahc_lookup_phase_entry(bus_phase) 2770 ->phasemsg); 2771 } 2772 #endif 2773 ahc->msgin_index = 0; 2774 if (bus_phase == P_MESGOUT 2775 && (ahc->send_msg_perror == TRUE 2776 || (ahc->msgout_len != 0 2777 && ahc->msgout_index == 0))) { 2778 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2779 goto reswitch; 2780 } 2781 end_session = TRUE; 2782 break; 2783 } 2784 2785 /* Pull the byte in without acking it */ 2786 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2787 #ifdef AHC_DEBUG 2788 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2789 printf(" byte 0x%x\n", 2790 ahc->msgin_buf[ahc->msgin_index]); 2791 #endif 2792 2793 message_done = ahc_parse_msg(ahc, &devinfo); 2794 2795 if (message_done) { 2796 /* 2797 * Clear our incoming message buffer in case there 2798 * is another message following this one. 2799 */ 2800 ahc->msgin_index = 0; 2801 2802 /* 2803 * If this message illicited a response, 2804 * assert ATN so the target takes us to the 2805 * message out phase. 2806 */ 2807 if (ahc->msgout_len != 0) { 2808 #ifdef AHC_DEBUG 2809 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2810 ahc_print_devinfo(ahc, &devinfo); 2811 printf("Asserting ATN for response\n"); 2812 } 2813 #endif 2814 ahc_assert_atn(ahc); 2815 } 2816 } else 2817 ahc->msgin_index++; 2818 2819 if (message_done == MSGLOOP_TERMINATED) { 2820 end_session = TRUE; 2821 } else { 2822 /* Ack the byte */ 2823 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2824 ahc_inb(ahc, SCSIDATL); 2825 } 2826 break; 2827 } 2828 case MSG_TYPE_TARGET_MSGIN: 2829 { 2830 int msgdone; 2831 int msgout_request; 2832 2833 if (ahc->msgout_len == 0) 2834 panic("Target MSGIN with no active message"); 2835 2836 /* 2837 * If we interrupted a mesgout session, the initiator 2838 * will not know this until our first REQ. So, we 2839 * only honor mesgout requests after we've sent our 2840 * first byte. 2841 */ 2842 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2843 && ahc->msgout_index > 0) 2844 msgout_request = TRUE; 2845 else 2846 msgout_request = FALSE; 2847 2848 if (msgout_request) { 2849 2850 /* 2851 * Change gears and see if 2852 * this messages is of interest to 2853 * us or should be passed back to 2854 * the sequencer. 2855 */ 2856 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2857 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2858 ahc->msgin_index = 0; 2859 /* Dummy read to REQ for first byte */ 2860 ahc_inb(ahc, SCSIDATL); 2861 ahc_outb(ahc, SXFRCTL0, 2862 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2863 break; 2864 } 2865 2866 msgdone = ahc->msgout_index == ahc->msgout_len; 2867 if (msgdone) { 2868 ahc_outb(ahc, SXFRCTL0, 2869 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2870 end_session = TRUE; 2871 break; 2872 } 2873 2874 /* 2875 * Present the next byte on the bus. 2876 */ 2877 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2878 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2879 break; 2880 } 2881 case MSG_TYPE_TARGET_MSGOUT: 2882 { 2883 int lastbyte; 2884 int msgdone; 2885 2886 /* 2887 * The initiator signals that this is 2888 * the last byte by dropping ATN. 2889 */ 2890 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2891 2892 /* 2893 * Read the latched byte, but turn off SPIOEN first 2894 * so that we don't inadvertently cause a REQ for the 2895 * next byte. 2896 */ 2897 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2898 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2899 msgdone = ahc_parse_msg(ahc, &devinfo); 2900 if (msgdone == MSGLOOP_TERMINATED) { 2901 /* 2902 * The message is *really* done in that it caused 2903 * us to go to bus free. The sequencer has already 2904 * been reset at this point, so pull the ejection 2905 * handle. 2906 */ 2907 return; 2908 } 2909 2910 ahc->msgin_index++; 2911 2912 /* 2913 * XXX Read spec about initiator dropping ATN too soon 2914 * and use msgdone to detect it. 2915 */ 2916 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2917 ahc->msgin_index = 0; 2918 2919 /* 2920 * If this message illicited a response, transition 2921 * to the Message in phase and send it. 2922 */ 2923 if (ahc->msgout_len != 0) { 2924 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2925 ahc_outb(ahc, SXFRCTL0, 2926 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2927 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2928 ahc->msgin_index = 0; 2929 break; 2930 } 2931 } 2932 2933 if (lastbyte) 2934 end_session = TRUE; 2935 else { 2936 /* Ask for the next byte. */ 2937 ahc_outb(ahc, SXFRCTL0, 2938 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2939 } 2940 2941 break; 2942 } 2943 default: 2944 panic("Unknown REQINIT message type"); 2945 } 2946 2947 if (end_session) { 2948 ahc_clear_msg_state(ahc); 2949 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2950 } else 2951 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2952 } 2953 2954 /* 2955 * See if we sent a particular extended message to the target. 2956 * If "full" is true, return true only if the target saw the full 2957 * message. If "full" is false, return true if the target saw at 2958 * least the first byte of the message. 2959 */ 2960 static int 2961 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2962 { 2963 int found; 2964 u_int index; 2965 2966 found = FALSE; 2967 index = 0; 2968 2969 while (index < ahc->msgout_len) { 2970 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2971 u_int end_index; 2972 2973 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2974 if (ahc->msgout_buf[index+2] == msgval 2975 && type == AHCMSG_EXT) { 2976 2977 if (full) { 2978 if (ahc->msgout_index > end_index) 2979 found = TRUE; 2980 } else if (ahc->msgout_index > index) 2981 found = TRUE; 2982 } 2983 index = end_index; 2984 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2985 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2986 2987 /* Skip tag type and tag id or residue param*/ 2988 index += 2; 2989 } else { 2990 /* Single byte message */ 2991 if (type == AHCMSG_1B 2992 && ahc->msgout_buf[index] == msgval 2993 && ahc->msgout_index > index) 2994 found = TRUE; 2995 index++; 2996 } 2997 2998 if (found) 2999 break; 3000 } 3001 return (found); 3002 } 3003 3004 /* 3005 * Wait for a complete incoming message, parse it, and respond accordingly. 3006 */ 3007 static int 3008 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3009 { 3010 struct ahc_initiator_tinfo *tinfo; 3011 struct ahc_tmode_tstate *tstate; 3012 int reject; 3013 int done; 3014 int response; 3015 u_int targ_scsirate; 3016 3017 done = MSGLOOP_IN_PROG; 3018 response = FALSE; 3019 reject = FALSE; 3020 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3021 devinfo->target, &tstate); 3022 targ_scsirate = tinfo->scsirate; 3023 3024 /* 3025 * Parse as much of the message as is available, 3026 * rejecting it if we don't support it. When 3027 * the entire message is available and has been 3028 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3029 * that we have parsed an entire message. 3030 * 3031 * In the case of extended messages, we accept the length 3032 * byte outright and perform more checking once we know the 3033 * extended message type. 3034 */ 3035 switch (ahc->msgin_buf[0]) { 3036 case MSG_DISCONNECT: 3037 case MSG_SAVEDATAPOINTER: 3038 case MSG_CMDCOMPLETE: 3039 case MSG_RESTOREPOINTERS: 3040 case MSG_IGN_WIDE_RESIDUE: 3041 /* 3042 * End our message loop as these are messages 3043 * the sequencer handles on its own. 3044 */ 3045 done = MSGLOOP_TERMINATED; 3046 break; 3047 case MSG_MESSAGE_REJECT: 3048 response = ahc_handle_msg_reject(ahc, devinfo); 3049 /* FALLTHROUGH */ 3050 case MSG_NOOP: 3051 done = MSGLOOP_MSGCOMPLETE; 3052 break; 3053 case MSG_EXTENDED: 3054 { 3055 /* Wait for enough of the message to begin validation */ 3056 if (ahc->msgin_index < 2) 3057 break; 3058 switch (ahc->msgin_buf[2]) { 3059 case MSG_EXT_SDTR: 3060 { 3061 struct ahc_syncrate *syncrate; 3062 u_int period; 3063 u_int ppr_options; 3064 u_int offset; 3065 u_int saved_offset; 3066 3067 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3068 reject = TRUE; 3069 break; 3070 } 3071 3072 /* 3073 * Wait until we have both args before validating 3074 * and acting on this message. 3075 * 3076 * Add one to MSG_EXT_SDTR_LEN to account for 3077 * the extended message preamble. 3078 */ 3079 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3080 break; 3081 3082 period = ahc->msgin_buf[3]; 3083 ppr_options = 0; 3084 saved_offset = offset = ahc->msgin_buf[4]; 3085 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3086 &ppr_options, 3087 devinfo->role); 3088 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3089 targ_scsirate & WIDEXFER, 3090 devinfo->role); 3091 if (bootverbose) { 3092 printf("(%s:%c:%d:%d): Received " 3093 "SDTR period %x, offset %x\n\t" 3094 "Filtered to period %x, offset %x\n", 3095 ahc_name(ahc), devinfo->channel, 3096 devinfo->target, devinfo->lun, 3097 ahc->msgin_buf[3], saved_offset, 3098 period, offset); 3099 } 3100 ahc_set_syncrate(ahc, devinfo, 3101 syncrate, period, 3102 offset, ppr_options, 3103 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3104 /*paused*/TRUE); 3105 3106 /* 3107 * See if we initiated Sync Negotiation 3108 * and didn't have to fall down to async 3109 * transfers. 3110 */ 3111 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3112 /* We started it */ 3113 if (saved_offset != offset) { 3114 /* Went too low - force async */ 3115 reject = TRUE; 3116 } 3117 } else { 3118 /* 3119 * Send our own SDTR in reply 3120 */ 3121 if (bootverbose 3122 && devinfo->role == ROLE_INITIATOR) { 3123 printf("(%s:%c:%d:%d): Target " 3124 "Initiated SDTR\n", 3125 ahc_name(ahc), devinfo->channel, 3126 devinfo->target, devinfo->lun); 3127 } 3128 ahc->msgout_index = 0; 3129 ahc->msgout_len = 0; 3130 ahc_construct_sdtr(ahc, devinfo, 3131 period, offset); 3132 ahc->msgout_index = 0; 3133 response = TRUE; 3134 } 3135 done = MSGLOOP_MSGCOMPLETE; 3136 break; 3137 } 3138 case MSG_EXT_WDTR: 3139 { 3140 u_int bus_width; 3141 u_int saved_width; 3142 u_int sending_reply; 3143 3144 sending_reply = FALSE; 3145 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3146 reject = TRUE; 3147 break; 3148 } 3149 3150 /* 3151 * Wait until we have our arg before validating 3152 * and acting on this message. 3153 * 3154 * Add one to MSG_EXT_WDTR_LEN to account for 3155 * the extended message preamble. 3156 */ 3157 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3158 break; 3159 3160 bus_width = ahc->msgin_buf[3]; 3161 saved_width = bus_width; 3162 ahc_validate_width(ahc, tinfo, &bus_width, 3163 devinfo->role); 3164 if (bootverbose) { 3165 printf("(%s:%c:%d:%d): Received WDTR " 3166 "%x filtered to %x\n", 3167 ahc_name(ahc), devinfo->channel, 3168 devinfo->target, devinfo->lun, 3169 saved_width, bus_width); 3170 } 3171 3172 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3173 /* 3174 * Don't send a WDTR back to the 3175 * target, since we asked first. 3176 * If the width went higher than our 3177 * request, reject it. 3178 */ 3179 if (saved_width > bus_width) { 3180 reject = TRUE; 3181 printf("(%s:%c:%d:%d): requested %dBit " 3182 "transfers. Rejecting...\n", 3183 ahc_name(ahc), devinfo->channel, 3184 devinfo->target, devinfo->lun, 3185 8 * (0x01 << bus_width)); 3186 bus_width = 0; 3187 } 3188 } else { 3189 /* 3190 * Send our own WDTR in reply 3191 */ 3192 if (bootverbose 3193 && devinfo->role == ROLE_INITIATOR) { 3194 printf("(%s:%c:%d:%d): Target " 3195 "Initiated WDTR\n", 3196 ahc_name(ahc), devinfo->channel, 3197 devinfo->target, devinfo->lun); 3198 } 3199 ahc->msgout_index = 0; 3200 ahc->msgout_len = 0; 3201 ahc_construct_wdtr(ahc, devinfo, bus_width); 3202 ahc->msgout_index = 0; 3203 response = TRUE; 3204 sending_reply = TRUE; 3205 } 3206 /* 3207 * After a wide message, we are async, but 3208 * some devices don't seem to honor this portion 3209 * of the spec. Force a renegotiation of the 3210 * sync component of our transfer agreement even 3211 * if our goal is async. By updating our width 3212 * after forcing the negotiation, we avoid 3213 * renegotiating for width. 3214 */ 3215 ahc_update_neg_request(ahc, devinfo, tstate, 3216 tinfo, AHC_NEG_ALWAYS); 3217 ahc_set_width(ahc, devinfo, bus_width, 3218 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3219 /*paused*/TRUE); 3220 if (sending_reply == FALSE && reject == FALSE) { 3221 3222 /* 3223 * We will always have an SDTR to send. 3224 */ 3225 ahc->msgout_index = 0; 3226 ahc->msgout_len = 0; 3227 ahc_build_transfer_msg(ahc, devinfo); 3228 ahc->msgout_index = 0; 3229 response = TRUE; 3230 } 3231 done = MSGLOOP_MSGCOMPLETE; 3232 break; 3233 } 3234 case MSG_EXT_PPR: 3235 { 3236 struct ahc_syncrate *syncrate; 3237 u_int period; 3238 u_int offset; 3239 u_int bus_width; 3240 u_int ppr_options; 3241 u_int saved_width; 3242 u_int saved_offset; 3243 u_int saved_ppr_options; 3244 3245 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3246 reject = TRUE; 3247 break; 3248 } 3249 3250 /* 3251 * Wait until we have all args before validating 3252 * and acting on this message. 3253 * 3254 * Add one to MSG_EXT_PPR_LEN to account for 3255 * the extended message preamble. 3256 */ 3257 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3258 break; 3259 3260 period = ahc->msgin_buf[3]; 3261 offset = ahc->msgin_buf[5]; 3262 bus_width = ahc->msgin_buf[6]; 3263 saved_width = bus_width; 3264 ppr_options = ahc->msgin_buf[7]; 3265 /* 3266 * According to the spec, a DT only 3267 * period factor with no DT option 3268 * set implies async. 3269 */ 3270 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3271 && period == 9) 3272 offset = 0; 3273 saved_ppr_options = ppr_options; 3274 saved_offset = offset; 3275 3276 /* 3277 * Mask out any options we don't support 3278 * on any controller. Transfer options are 3279 * only available if we are negotiating wide. 3280 */ 3281 ppr_options &= MSG_EXT_PPR_DT_REQ; 3282 if (bus_width == 0) 3283 ppr_options = 0; 3284 3285 ahc_validate_width(ahc, tinfo, &bus_width, 3286 devinfo->role); 3287 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3288 &ppr_options, 3289 devinfo->role); 3290 ahc_validate_offset(ahc, tinfo, syncrate, 3291 &offset, bus_width, 3292 devinfo->role); 3293 3294 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3295 /* 3296 * If we are unable to do any of the 3297 * requested options (we went too low), 3298 * then we'll have to reject the message. 3299 */ 3300 if (saved_width > bus_width 3301 || saved_offset != offset 3302 || saved_ppr_options != ppr_options) { 3303 reject = TRUE; 3304 period = 0; 3305 offset = 0; 3306 bus_width = 0; 3307 ppr_options = 0; 3308 syncrate = NULL; 3309 } 3310 } else { 3311 if (devinfo->role != ROLE_TARGET) 3312 printf("(%s:%c:%d:%d): Target " 3313 "Initiated PPR\n", 3314 ahc_name(ahc), devinfo->channel, 3315 devinfo->target, devinfo->lun); 3316 else 3317 printf("(%s:%c:%d:%d): Initiator " 3318 "Initiated PPR\n", 3319 ahc_name(ahc), devinfo->channel, 3320 devinfo->target, devinfo->lun); 3321 ahc->msgout_index = 0; 3322 ahc->msgout_len = 0; 3323 ahc_construct_ppr(ahc, devinfo, period, offset, 3324 bus_width, ppr_options); 3325 ahc->msgout_index = 0; 3326 response = TRUE; 3327 } 3328 if (bootverbose) { 3329 printf("(%s:%c:%d:%d): Received PPR width %x, " 3330 "period %x, offset %x,options %x\n" 3331 "\tFiltered to width %x, period %x, " 3332 "offset %x, options %x\n", 3333 ahc_name(ahc), devinfo->channel, 3334 devinfo->target, devinfo->lun, 3335 saved_width, ahc->msgin_buf[3], 3336 saved_offset, saved_ppr_options, 3337 bus_width, period, offset, ppr_options); 3338 } 3339 ahc_set_width(ahc, devinfo, bus_width, 3340 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3341 /*paused*/TRUE); 3342 ahc_set_syncrate(ahc, devinfo, 3343 syncrate, period, 3344 offset, ppr_options, 3345 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3346 /*paused*/TRUE); 3347 done = MSGLOOP_MSGCOMPLETE; 3348 break; 3349 } 3350 default: 3351 /* Unknown extended message. Reject it. */ 3352 reject = TRUE; 3353 break; 3354 } 3355 break; 3356 } 3357 #ifdef AHC_TARGET_MODE 3358 case MSG_BUS_DEV_RESET: 3359 ahc_handle_devreset(ahc, devinfo, 3360 CAM_BDR_SENT, 3361 "Bus Device Reset Received", 3362 /*verbose_level*/0); 3363 ahc_restart(ahc); 3364 done = MSGLOOP_TERMINATED; 3365 break; 3366 case MSG_ABORT_TAG: 3367 case MSG_ABORT: 3368 case MSG_CLEAR_QUEUE: 3369 { 3370 int tag; 3371 3372 /* Target mode messages */ 3373 if (devinfo->role != ROLE_TARGET) { 3374 reject = TRUE; 3375 break; 3376 } 3377 tag = SCB_LIST_NULL; 3378 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3379 tag = ahc_inb(ahc, INITIATOR_TAG); 3380 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3381 devinfo->lun, tag, ROLE_TARGET, 3382 CAM_REQ_ABORTED); 3383 3384 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3385 if (tstate != NULL) { 3386 struct ahc_tmode_lstate* lstate; 3387 3388 lstate = tstate->enabled_luns[devinfo->lun]; 3389 if (lstate != NULL) { 3390 ahc_queue_lstate_event(ahc, lstate, 3391 devinfo->our_scsiid, 3392 ahc->msgin_buf[0], 3393 /*arg*/tag); 3394 ahc_send_lstate_events(ahc, lstate); 3395 } 3396 } 3397 ahc_restart(ahc); 3398 done = MSGLOOP_TERMINATED; 3399 break; 3400 } 3401 #endif 3402 case MSG_TERM_IO_PROC: 3403 default: 3404 reject = TRUE; 3405 break; 3406 } 3407 3408 if (reject) { 3409 /* 3410 * Setup to reject the message. 3411 */ 3412 ahc->msgout_index = 0; 3413 ahc->msgout_len = 1; 3414 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3415 done = MSGLOOP_MSGCOMPLETE; 3416 response = TRUE; 3417 } 3418 3419 if (done != MSGLOOP_IN_PROG && !response) 3420 /* Clear the outgoing message buffer */ 3421 ahc->msgout_len = 0; 3422 3423 return (done); 3424 } 3425 3426 /* 3427 * Process a message reject message. 3428 */ 3429 static int 3430 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3431 { 3432 /* 3433 * What we care about here is if we had an 3434 * outstanding SDTR or WDTR message for this 3435 * target. If we did, this is a signal that 3436 * the target is refusing negotiation. 3437 */ 3438 struct scb *scb; 3439 struct ahc_initiator_tinfo *tinfo; 3440 struct ahc_tmode_tstate *tstate; 3441 u_int scb_index; 3442 u_int last_msg; 3443 int response = 0; 3444 3445 scb_index = ahc_inb(ahc, SCB_TAG); 3446 scb = ahc_lookup_scb(ahc, scb_index); 3447 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3448 devinfo->our_scsiid, 3449 devinfo->target, &tstate); 3450 /* Might be necessary */ 3451 last_msg = ahc_inb(ahc, LAST_MSG); 3452 3453 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3454 /* 3455 * Target does not support the PPR message. 3456 * Attempt to negotiate SPI-2 style. 3457 */ 3458 if (bootverbose) { 3459 printf("(%s:%c:%d:%d): PPR Rejected. " 3460 "Trying WDTR/SDTR\n", 3461 ahc_name(ahc), devinfo->channel, 3462 devinfo->target, devinfo->lun); 3463 } 3464 tinfo->goal.ppr_options = 0; 3465 tinfo->curr.transport_version = 2; 3466 tinfo->goal.transport_version = 2; 3467 ahc->msgout_index = 0; 3468 ahc->msgout_len = 0; 3469 ahc_build_transfer_msg(ahc, devinfo); 3470 ahc->msgout_index = 0; 3471 response = 1; 3472 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3473 3474 /* note 8bit xfers */ 3475 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3476 "8bit transfers\n", ahc_name(ahc), 3477 devinfo->channel, devinfo->target, devinfo->lun); 3478 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3479 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3480 /*paused*/TRUE); 3481 /* 3482 * No need to clear the sync rate. If the target 3483 * did not accept the command, our syncrate is 3484 * unaffected. If the target started the negotiation, 3485 * but rejected our response, we already cleared the 3486 * sync rate before sending our WDTR. 3487 */ 3488 if (tinfo->goal.offset != tinfo->curr.offset) { 3489 3490 /* Start the sync negotiation */ 3491 ahc->msgout_index = 0; 3492 ahc->msgout_len = 0; 3493 ahc_build_transfer_msg(ahc, devinfo); 3494 ahc->msgout_index = 0; 3495 response = 1; 3496 } 3497 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3498 /* note asynch xfers and clear flag */ 3499 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3500 /*offset*/0, /*ppr_options*/0, 3501 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3502 /*paused*/TRUE); 3503 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3504 "Using asynchronous transfers\n", 3505 ahc_name(ahc), devinfo->channel, 3506 devinfo->target, devinfo->lun); 3507 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3508 int tag_type; 3509 int mask; 3510 3511 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3512 3513 if (tag_type == MSG_SIMPLE_TASK) { 3514 printf("(%s:%c:%d:%d): refuses tagged commands. " 3515 "Performing non-tagged I/O\n", ahc_name(ahc), 3516 devinfo->channel, devinfo->target, devinfo->lun); 3517 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3518 mask = ~0x23; 3519 } else { 3520 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3521 "Performing simple queue tagged I/O only\n", 3522 ahc_name(ahc), devinfo->channel, devinfo->target, 3523 devinfo->lun, tag_type == MSG_ORDERED_TASK 3524 ? "ordered" : "head of queue"); 3525 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3526 mask = ~0x03; 3527 } 3528 3529 /* 3530 * Resend the identify for this CCB as the target 3531 * may believe that the selection is invalid otherwise. 3532 */ 3533 ahc_outb(ahc, SCB_CONTROL, 3534 ahc_inb(ahc, SCB_CONTROL) & mask); 3535 scb->hscb->control &= mask; 3536 aic_set_transaction_tag(scb, /*enabled*/FALSE, 3537 /*type*/MSG_SIMPLE_TASK); 3538 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3539 ahc_assert_atn(ahc); 3540 3541 /* 3542 * This transaction is now at the head of 3543 * the untagged queue for this target. 3544 */ 3545 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3546 struct scb_tailq *untagged_q; 3547 3548 untagged_q = 3549 &(ahc->untagged_queues[devinfo->target_offset]); 3550 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3551 scb->flags |= SCB_UNTAGGEDQ; 3552 } 3553 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3554 scb->hscb->tag); 3555 3556 /* 3557 * Requeue all tagged commands for this target 3558 * currently in our posession so they can be 3559 * converted to untagged commands. 3560 */ 3561 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3562 SCB_GET_CHANNEL(ahc, scb), 3563 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3564 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3565 SEARCH_COMPLETE); 3566 } else { 3567 /* 3568 * Otherwise, we ignore it. 3569 */ 3570 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3571 ahc_name(ahc), devinfo->channel, devinfo->target, 3572 last_msg); 3573 } 3574 return (response); 3575 } 3576 3577 /* 3578 * Process an ingnore wide residue message. 3579 */ 3580 static void 3581 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3582 { 3583 u_int scb_index; 3584 struct scb *scb; 3585 3586 scb_index = ahc_inb(ahc, SCB_TAG); 3587 scb = ahc_lookup_scb(ahc, scb_index); 3588 /* 3589 * XXX Actually check data direction in the sequencer? 3590 * Perhaps add datadir to some spare bits in the hscb? 3591 */ 3592 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3593 || aic_get_transfer_dir(scb) != CAM_DIR_IN) { 3594 /* 3595 * Ignore the message if we haven't 3596 * seen an appropriate data phase yet. 3597 */ 3598 } else { 3599 /* 3600 * If the residual occurred on the last 3601 * transfer and the transfer request was 3602 * expected to end on an odd count, do 3603 * nothing. Otherwise, subtract a byte 3604 * and update the residual count accordingly. 3605 */ 3606 uint32_t sgptr; 3607 3608 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3609 if ((sgptr & SG_LIST_NULL) != 0 3610 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3611 /* 3612 * If the residual occurred on the last 3613 * transfer and the transfer request was 3614 * expected to end on an odd count, do 3615 * nothing. 3616 */ 3617 } else { 3618 struct ahc_dma_seg *sg; 3619 uint32_t data_cnt; 3620 uint32_t data_addr; 3621 uint32_t sglen; 3622 3623 /* Pull in all of the sgptr */ 3624 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3625 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3626 3627 if ((sgptr & SG_LIST_NULL) != 0) { 3628 /* 3629 * The residual data count is not updated 3630 * for the command run to completion case. 3631 * Explicitly zero the count. 3632 */ 3633 data_cnt &= ~AHC_SG_LEN_MASK; 3634 } 3635 3636 data_addr = ahc_inl(ahc, SHADDR); 3637 3638 data_cnt += 1; 3639 data_addr -= 1; 3640 sgptr &= SG_PTR_MASK; 3641 3642 sg = ahc_sg_bus_to_virt(scb, sgptr); 3643 3644 /* 3645 * The residual sg ptr points to the next S/G 3646 * to load so we must go back one. 3647 */ 3648 sg--; 3649 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 3650 if (sg != scb->sg_list 3651 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3652 3653 sg--; 3654 sglen = aic_le32toh(sg->len); 3655 /* 3656 * Preserve High Address and SG_LIST bits 3657 * while setting the count to 1. 3658 */ 3659 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3660 data_addr = aic_le32toh(sg->addr) 3661 + (sglen & AHC_SG_LEN_MASK) - 1; 3662 3663 /* 3664 * Increment sg so it points to the 3665 * "next" sg. 3666 */ 3667 sg++; 3668 sgptr = ahc_sg_virt_to_bus(scb, sg); 3669 } 3670 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3671 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3672 /* 3673 * Toggle the "oddness" of the transfer length 3674 * to handle this mid-transfer ignore wide 3675 * residue. This ensures that the oddness is 3676 * correct for subsequent data transfers. 3677 */ 3678 ahc_outb(ahc, SCB_LUN, 3679 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3680 } 3681 } 3682 } 3683 3684 3685 /* 3686 * Reinitialize the data pointers for the active transfer 3687 * based on its current residual. 3688 */ 3689 static void 3690 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3691 { 3692 struct scb *scb; 3693 struct ahc_dma_seg *sg; 3694 u_int scb_index; 3695 uint32_t sgptr; 3696 uint32_t resid; 3697 uint32_t dataptr; 3698 3699 scb_index = ahc_inb(ahc, SCB_TAG); 3700 scb = ahc_lookup_scb(ahc, scb_index); 3701 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3702 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3703 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3704 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3705 3706 sgptr &= SG_PTR_MASK; 3707 sg = ahc_sg_bus_to_virt(scb, sgptr); 3708 3709 /* The residual sg_ptr always points to the next sg */ 3710 sg--; 3711 3712 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3713 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3714 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3715 3716 dataptr = aic_le32toh(sg->addr) 3717 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK) 3718 - resid; 3719 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3720 u_int dscommand1; 3721 3722 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3723 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3724 ahc_outb(ahc, HADDR, 3725 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3726 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3727 } 3728 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3729 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3730 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3731 ahc_outb(ahc, HADDR, dataptr); 3732 ahc_outb(ahc, HCNT + 2, resid >> 16); 3733 ahc_outb(ahc, HCNT + 1, resid >> 8); 3734 ahc_outb(ahc, HCNT, resid); 3735 if ((ahc->features & AHC_ULTRA2) == 0) { 3736 ahc_outb(ahc, STCNT + 2, resid >> 16); 3737 ahc_outb(ahc, STCNT + 1, resid >> 8); 3738 ahc_outb(ahc, STCNT, resid); 3739 } 3740 } 3741 3742 /* 3743 * Handle the effects of issuing a bus device reset message. 3744 */ 3745 static void 3746 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3747 cam_status status, char *message, int verbose_level) 3748 { 3749 #ifdef AHC_TARGET_MODE 3750 struct ahc_tmode_tstate* tstate; 3751 u_int lun; 3752 #endif 3753 int found; 3754 3755 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3756 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3757 status); 3758 3759 #ifdef AHC_TARGET_MODE 3760 /* 3761 * Send an immediate notify ccb to all target mord peripheral 3762 * drivers affected by this action. 3763 */ 3764 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3765 if (tstate != NULL) { 3766 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3767 struct ahc_tmode_lstate* lstate; 3768 3769 lstate = tstate->enabled_luns[lun]; 3770 if (lstate == NULL) 3771 continue; 3772 3773 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3774 MSG_BUS_DEV_RESET, /*arg*/0); 3775 ahc_send_lstate_events(ahc, lstate); 3776 } 3777 } 3778 #endif 3779 3780 /* 3781 * Go back to async/narrow transfers and renegotiate. 3782 */ 3783 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3784 AHC_TRANS_CUR, /*paused*/TRUE); 3785 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3786 /*period*/0, /*offset*/0, /*ppr_options*/0, 3787 AHC_TRANS_CUR, /*paused*/TRUE); 3788 3789 if (status != CAM_SEL_TIMEOUT) 3790 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3791 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3792 3793 if (message != NULL 3794 && (verbose_level <= bootverbose)) 3795 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3796 message, devinfo->channel, devinfo->target, found); 3797 } 3798 3799 #ifdef AHC_TARGET_MODE 3800 static void 3801 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3802 struct scb *scb) 3803 { 3804 3805 /* 3806 * To facilitate adding multiple messages together, 3807 * each routine should increment the index and len 3808 * variables instead of setting them explicitly. 3809 */ 3810 ahc->msgout_index = 0; 3811 ahc->msgout_len = 0; 3812 3813 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3814 ahc_build_transfer_msg(ahc, devinfo); 3815 else 3816 panic("ahc_intr: AWAITING target message with no message"); 3817 3818 ahc->msgout_index = 0; 3819 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3820 } 3821 #endif 3822 /**************************** Initialization **********************************/ 3823 /* 3824 * Allocate a controller structure for a new device 3825 * and perform initial initializion. 3826 */ 3827 struct ahc_softc * 3828 ahc_alloc(void *platform_arg, char *name) 3829 { 3830 struct ahc_softc *ahc; 3831 int i; 3832 3833 #ifndef __FreeBSD__ 3834 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3835 if (!ahc) { 3836 printf("aic7xxx: cannot malloc softc!\n"); 3837 free(name, M_DEVBUF); 3838 return NULL; 3839 } 3840 #else 3841 ahc = device_get_softc((device_t)platform_arg); 3842 #endif 3843 memset(ahc, 0, sizeof(*ahc)); 3844 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3845 M_DEVBUF, M_NOWAIT); 3846 if (ahc->seep_config == NULL) { 3847 #ifndef __FreeBSD__ 3848 free(ahc, M_DEVBUF); 3849 #endif 3850 free(name, M_DEVBUF); 3851 return (NULL); 3852 } 3853 LIST_INIT(&ahc->pending_scbs); 3854 /* We don't know our unit number until the OSM sets it */ 3855 ahc->name = name; 3856 ahc->unit = -1; 3857 ahc->description = NULL; 3858 ahc->channel = 'A'; 3859 ahc->channel_b = 'B'; 3860 ahc->chip = AHC_NONE; 3861 ahc->features = AHC_FENONE; 3862 ahc->bugs = AHC_BUGNONE; 3863 ahc->flags = AHC_FNONE; 3864 /* 3865 * Default to all error reporting enabled with the 3866 * sequencer operating at its fastest speed. 3867 * The bus attach code may modify this. 3868 */ 3869 ahc->seqctl = FASTMODE; 3870 3871 for (i = 0; i < AHC_NUM_TARGETS; i++) 3872 TAILQ_INIT(&ahc->untagged_queues[i]); 3873 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3874 ahc_free(ahc); 3875 ahc = NULL; 3876 } 3877 return (ahc); 3878 } 3879 3880 int 3881 ahc_softc_init(struct ahc_softc *ahc) 3882 { 3883 3884 /* The IRQMS bit is only valid on VL and EISA chips */ 3885 if ((ahc->chip & AHC_PCI) == 0) 3886 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3887 else 3888 ahc->unpause = 0; 3889 ahc->pause = ahc->unpause | PAUSE; 3890 /* XXX The shared scb data stuff should be deprecated */ 3891 if (ahc->scb_data == NULL) { 3892 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3893 M_DEVBUF, M_NOWAIT); 3894 if (ahc->scb_data == NULL) 3895 return (ENOMEM); 3896 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3897 } 3898 3899 return (0); 3900 } 3901 3902 void 3903 ahc_softc_insert(struct ahc_softc *ahc) 3904 { 3905 struct ahc_softc *list_ahc; 3906 3907 #if AIC_PCI_CONFIG > 0 3908 /* 3909 * Second Function PCI devices need to inherit some 3910 * settings from function 0. 3911 */ 3912 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3913 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3914 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3915 aic_dev_softc_t list_pci; 3916 aic_dev_softc_t pci; 3917 3918 list_pci = list_ahc->dev_softc; 3919 pci = ahc->dev_softc; 3920 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci) 3921 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) { 3922 struct ahc_softc *master; 3923 struct ahc_softc *slave; 3924 3925 if (aic_get_pci_function(list_pci) == 0) { 3926 master = list_ahc; 3927 slave = ahc; 3928 } else { 3929 master = ahc; 3930 slave = list_ahc; 3931 } 3932 slave->flags &= ~AHC_BIOS_ENABLED; 3933 slave->flags |= 3934 master->flags & AHC_BIOS_ENABLED; 3935 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3936 slave->flags |= 3937 master->flags & AHC_PRIMARY_CHANNEL; 3938 break; 3939 } 3940 } 3941 } 3942 #endif 3943 3944 /* 3945 * Insertion sort into our list of softcs. 3946 */ 3947 list_ahc = TAILQ_FIRST(&ahc_tailq); 3948 while (list_ahc != NULL 3949 && ahc_softc_comp(ahc, list_ahc) <= 0) 3950 list_ahc = TAILQ_NEXT(list_ahc, links); 3951 if (list_ahc != NULL) 3952 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3953 else 3954 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3955 ahc->init_level++; 3956 } 3957 3958 /* 3959 * Verify that the passed in softc pointer is for a 3960 * controller that is still configured. 3961 */ 3962 struct ahc_softc * 3963 ahc_find_softc(struct ahc_softc *ahc) 3964 { 3965 struct ahc_softc *list_ahc; 3966 3967 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3968 if (list_ahc == ahc) 3969 return (ahc); 3970 } 3971 return (NULL); 3972 } 3973 3974 void 3975 ahc_set_unit(struct ahc_softc *ahc, int unit) 3976 { 3977 ahc->unit = unit; 3978 } 3979 3980 void 3981 ahc_set_name(struct ahc_softc *ahc, char *name) 3982 { 3983 if (ahc->name != NULL) 3984 free(ahc->name, M_DEVBUF); 3985 ahc->name = name; 3986 } 3987 3988 void 3989 ahc_free(struct ahc_softc *ahc) 3990 { 3991 int i; 3992 3993 ahc_terminate_recovery_thread(ahc); 3994 switch (ahc->init_level) { 3995 default: 3996 case 5: 3997 ahc_shutdown(ahc); 3998 /* FALLTHROUGH */ 3999 case 4: 4000 aic_dmamap_unload(ahc, ahc->shared_data_dmat, 4001 ahc->shared_data_dmamap); 4002 /* FALLTHROUGH */ 4003 case 3: 4004 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 4005 ahc->shared_data_dmamap); 4006 aic_dmamap_destroy(ahc, ahc->shared_data_dmat, 4007 ahc->shared_data_dmamap); 4008 /* FALLTHROUGH */ 4009 case 2: 4010 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat); 4011 case 1: 4012 #ifndef __linux__ 4013 aic_dma_tag_destroy(ahc, ahc->buffer_dmat); 4014 #endif 4015 break; 4016 case 0: 4017 break; 4018 } 4019 4020 #ifndef __linux__ 4021 aic_dma_tag_destroy(ahc, ahc->parent_dmat); 4022 #endif 4023 ahc_platform_free(ahc); 4024 ahc_fini_scbdata(ahc); 4025 for (i = 0; i < AHC_NUM_TARGETS; i++) { 4026 struct ahc_tmode_tstate *tstate; 4027 4028 tstate = ahc->enabled_targets[i]; 4029 if (tstate != NULL) { 4030 #ifdef AHC_TARGET_MODE 4031 int j; 4032 4033 for (j = 0; j < AHC_NUM_LUNS; j++) { 4034 struct ahc_tmode_lstate *lstate; 4035 4036 lstate = tstate->enabled_luns[j]; 4037 if (lstate != NULL) { 4038 xpt_free_path(lstate->path); 4039 free(lstate, M_DEVBUF); 4040 } 4041 } 4042 #endif 4043 free(tstate, M_DEVBUF); 4044 } 4045 } 4046 #ifdef AHC_TARGET_MODE 4047 if (ahc->black_hole != NULL) { 4048 xpt_free_path(ahc->black_hole->path); 4049 free(ahc->black_hole, M_DEVBUF); 4050 } 4051 #endif 4052 if (ahc->name != NULL) 4053 free(ahc->name, M_DEVBUF); 4054 if (ahc->seep_config != NULL) 4055 free(ahc->seep_config, M_DEVBUF); 4056 #ifndef __FreeBSD__ 4057 free(ahc, M_DEVBUF); 4058 #endif 4059 return; 4060 } 4061 4062 void 4063 ahc_shutdown(void *arg) 4064 { 4065 struct ahc_softc *ahc; 4066 int i; 4067 4068 ahc = (struct ahc_softc *)arg; 4069 4070 /* This will reset most registers to 0, but not all */ 4071 ahc_reset(ahc, /*reinit*/FALSE); 4072 ahc_outb(ahc, SCSISEQ, 0); 4073 ahc_outb(ahc, SXFRCTL0, 0); 4074 ahc_outb(ahc, DSPCISTATUS, 0); 4075 4076 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4077 ahc_outb(ahc, i, 0); 4078 } 4079 4080 /* 4081 * Reset the controller and record some information about it 4082 * that is only available just after a reset. If "reinit" is 4083 * non-zero, this reset occured after initial configuration 4084 * and the caller requests that the chip be fully reinitialized 4085 * to a runable state. Chip interrupts are *not* enabled after 4086 * a reinitialization. The caller must enable interrupts via 4087 * ahc_intr_enable(). 4088 */ 4089 int 4090 ahc_reset(struct ahc_softc *ahc, int reinit) 4091 { 4092 u_int sblkctl; 4093 u_int sxfrctl1_a, sxfrctl1_b; 4094 int error; 4095 int wait; 4096 4097 /* 4098 * Preserve the value of the SXFRCTL1 register for all channels. 4099 * It contains settings that affect termination and we don't want 4100 * to disturb the integrity of the bus. 4101 */ 4102 ahc_pause(ahc); 4103 sxfrctl1_b = 0; 4104 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4105 u_int sblkctl; 4106 4107 /* 4108 * Save channel B's settings in case this chip 4109 * is setup for TWIN channel operation. 4110 */ 4111 sblkctl = ahc_inb(ahc, SBLKCTL); 4112 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4113 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4114 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4115 } 4116 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4117 4118 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4119 4120 /* 4121 * Ensure that the reset has finished. We delay 1000us 4122 * prior to reading the register to make sure the chip 4123 * has sufficiently completed its reset to handle register 4124 * accesses. 4125 */ 4126 wait = 1000; 4127 do { 4128 aic_delay(1000); 4129 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4130 4131 if (wait == 0) { 4132 printf("%s: WARNING - Failed chip reset! " 4133 "Trying to initialize anyway.\n", ahc_name(ahc)); 4134 } 4135 ahc_outb(ahc, HCNTRL, ahc->pause); 4136 4137 /* Determine channel configuration */ 4138 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4139 /* No Twin Channel PCI cards */ 4140 if ((ahc->chip & AHC_PCI) != 0) 4141 sblkctl &= ~SELBUSB; 4142 switch (sblkctl) { 4143 case 0: 4144 /* Single Narrow Channel */ 4145 break; 4146 case 2: 4147 /* Wide Channel */ 4148 ahc->features |= AHC_WIDE; 4149 break; 4150 case 8: 4151 /* Twin Channel */ 4152 ahc->features |= AHC_TWIN; 4153 break; 4154 default: 4155 printf(" Unsupported adapter type. Ignoring\n"); 4156 return(-1); 4157 } 4158 4159 /* 4160 * Reload sxfrctl1. 4161 * 4162 * We must always initialize STPWEN to 1 before we 4163 * restore the saved values. STPWEN is initialized 4164 * to a tri-state condition which can only be cleared 4165 * by turning it on. 4166 */ 4167 if ((ahc->features & AHC_TWIN) != 0) { 4168 u_int sblkctl; 4169 4170 sblkctl = ahc_inb(ahc, SBLKCTL); 4171 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4172 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4173 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4174 } 4175 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4176 4177 error = 0; 4178 if (reinit != 0) 4179 /* 4180 * If a recovery action has forced a chip reset, 4181 * re-initialize the chip to our liking. 4182 */ 4183 error = ahc->bus_chip_init(ahc); 4184 #ifdef AHC_DUMP_SEQ 4185 else 4186 ahc_dumpseq(ahc); 4187 #endif 4188 4189 return (error); 4190 } 4191 4192 /* 4193 * Determine the number of SCBs available on the controller 4194 */ 4195 int 4196 ahc_probe_scbs(struct ahc_softc *ahc) { 4197 int i; 4198 4199 for (i = 0; i < AHC_SCB_MAX; i++) { 4200 4201 ahc_outb(ahc, SCBPTR, i); 4202 ahc_outb(ahc, SCB_BASE, i); 4203 if (ahc_inb(ahc, SCB_BASE) != i) 4204 break; 4205 ahc_outb(ahc, SCBPTR, 0); 4206 if (ahc_inb(ahc, SCB_BASE) != 0) 4207 break; 4208 } 4209 return (i); 4210 } 4211 4212 static void 4213 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4214 { 4215 bus_addr_t *baddr; 4216 4217 baddr = (bus_addr_t *)arg; 4218 *baddr = segs->ds_addr; 4219 } 4220 4221 static void 4222 ahc_build_free_scb_list(struct ahc_softc *ahc) 4223 { 4224 int scbsize; 4225 int i; 4226 4227 scbsize = 32; 4228 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4229 scbsize = 64; 4230 4231 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4232 int j; 4233 4234 ahc_outb(ahc, SCBPTR, i); 4235 4236 /* 4237 * Touch all SCB bytes to avoid parity errors 4238 * should one of our debugging routines read 4239 * an otherwise uninitiatlized byte. 4240 */ 4241 for (j = 0; j < scbsize; j++) 4242 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4243 4244 /* Clear the control byte. */ 4245 ahc_outb(ahc, SCB_CONTROL, 0); 4246 4247 /* Set the next pointer */ 4248 if ((ahc->flags & AHC_PAGESCBS) != 0) 4249 ahc_outb(ahc, SCB_NEXT, i+1); 4250 else 4251 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4252 4253 /* Make the tag number, SCSIID, and lun invalid */ 4254 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4255 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4256 ahc_outb(ahc, SCB_LUN, 0xFF); 4257 } 4258 4259 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4260 /* SCB 0 heads the free list. */ 4261 ahc_outb(ahc, FREE_SCBH, 0); 4262 } else { 4263 /* No free list. */ 4264 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4265 } 4266 4267 /* Make sure that the last SCB terminates the free list */ 4268 ahc_outb(ahc, SCBPTR, i-1); 4269 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4270 } 4271 4272 static int 4273 ahc_init_scbdata(struct ahc_softc *ahc) 4274 { 4275 struct scb_data *scb_data; 4276 4277 scb_data = ahc->scb_data; 4278 SLIST_INIT(&scb_data->free_scbs); 4279 SLIST_INIT(&scb_data->sg_maps); 4280 4281 /* Allocate SCB resources */ 4282 scb_data->scbarray = 4283 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4284 M_DEVBUF, M_NOWAIT); 4285 if (scb_data->scbarray == NULL) 4286 return (ENOMEM); 4287 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4288 4289 /* Determine the number of hardware SCBs and initialize them */ 4290 4291 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4292 if (ahc->scb_data->maxhscbs == 0) { 4293 printf("%s: No SCB space found\n", ahc_name(ahc)); 4294 return (ENXIO); 4295 } 4296 4297 /* 4298 * Create our DMA tags. These tags define the kinds of device 4299 * accessible memory allocations and memory mappings we will 4300 * need to perform during normal operation. 4301 * 4302 * Unless we need to further restrict the allocation, we rely 4303 * on the restrictions of the parent dmat, hence the common 4304 * use of MAXADDR and MAXSIZE. 4305 */ 4306 4307 /* DMA tag for our hardware scb structures */ 4308 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4309 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4310 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4311 /*highaddr*/BUS_SPACE_MAXADDR, 4312 /*filter*/NULL, /*filterarg*/NULL, 4313 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4314 /*nsegments*/1, 4315 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4316 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4317 goto error_exit; 4318 } 4319 4320 scb_data->init_level++; 4321 4322 /* Allocation for our hscbs */ 4323 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat, 4324 (void **)&scb_data->hscbs, 4325 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4326 goto error_exit; 4327 } 4328 4329 scb_data->init_level++; 4330 4331 /* And permanently map them */ 4332 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4333 scb_data->hscbs, 4334 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4335 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4336 4337 scb_data->init_level++; 4338 4339 /* DMA tag for our sense buffers */ 4340 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4341 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4342 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4343 /*highaddr*/BUS_SPACE_MAXADDR, 4344 /*filter*/NULL, /*filterarg*/NULL, 4345 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4346 /*nsegments*/1, 4347 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4348 /*flags*/0, &scb_data->sense_dmat) != 0) { 4349 goto error_exit; 4350 } 4351 4352 scb_data->init_level++; 4353 4354 /* Allocate them */ 4355 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat, 4356 (void **)&scb_data->sense, 4357 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4358 goto error_exit; 4359 } 4360 4361 scb_data->init_level++; 4362 4363 /* And permanently map them */ 4364 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4365 scb_data->sense, 4366 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4367 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4368 4369 scb_data->init_level++; 4370 4371 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4372 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4373 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4374 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4375 /*highaddr*/BUS_SPACE_MAXADDR, 4376 /*filter*/NULL, /*filterarg*/NULL, 4377 PAGE_SIZE, /*nsegments*/1, 4378 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4379 /*flags*/0, &scb_data->sg_dmat) != 0) { 4380 goto error_exit; 4381 } 4382 4383 scb_data->init_level++; 4384 4385 /* Perform initial CCB allocation */ 4386 memset(scb_data->hscbs, 0, 4387 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4388 ahc_alloc_scbs(ahc); 4389 4390 if (scb_data->numscbs == 0) { 4391 printf("%s: ahc_init_scbdata - " 4392 "Unable to allocate initial scbs\n", 4393 ahc_name(ahc)); 4394 goto error_exit; 4395 } 4396 4397 /* 4398 * Reserve the next queued SCB. 4399 */ 4400 ahc->next_queued_scb = ahc_get_scb(ahc); 4401 4402 /* 4403 * Note that we were successfull 4404 */ 4405 return (0); 4406 4407 error_exit: 4408 4409 return (ENOMEM); 4410 } 4411 4412 static void 4413 ahc_fini_scbdata(struct ahc_softc *ahc) 4414 { 4415 struct scb_data *scb_data; 4416 4417 scb_data = ahc->scb_data; 4418 if (scb_data == NULL) 4419 return; 4420 4421 switch (scb_data->init_level) { 4422 default: 4423 case 7: 4424 { 4425 struct sg_map_node *sg_map; 4426 4427 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4428 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4429 aic_dmamap_unload(ahc, scb_data->sg_dmat, 4430 sg_map->sg_dmamap); 4431 aic_dmamem_free(ahc, scb_data->sg_dmat, 4432 sg_map->sg_vaddr, 4433 sg_map->sg_dmamap); 4434 free(sg_map, M_DEVBUF); 4435 } 4436 aic_dma_tag_destroy(ahc, scb_data->sg_dmat); 4437 } 4438 case 6: 4439 aic_dmamap_unload(ahc, scb_data->sense_dmat, 4440 scb_data->sense_dmamap); 4441 case 5: 4442 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4443 scb_data->sense_dmamap); 4444 aic_dmamap_destroy(ahc, scb_data->sense_dmat, 4445 scb_data->sense_dmamap); 4446 case 4: 4447 aic_dma_tag_destroy(ahc, scb_data->sense_dmat); 4448 case 3: 4449 aic_dmamap_unload(ahc, scb_data->hscb_dmat, 4450 scb_data->hscb_dmamap); 4451 case 2: 4452 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4453 scb_data->hscb_dmamap); 4454 aic_dmamap_destroy(ahc, scb_data->hscb_dmat, 4455 scb_data->hscb_dmamap); 4456 case 1: 4457 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4458 break; 4459 case 0: 4460 break; 4461 } 4462 if (scb_data->scbarray != NULL) 4463 free(scb_data->scbarray, M_DEVBUF); 4464 } 4465 4466 void 4467 ahc_alloc_scbs(struct ahc_softc *ahc) 4468 { 4469 struct scb_data *scb_data; 4470 struct scb *next_scb; 4471 struct sg_map_node *sg_map; 4472 bus_addr_t physaddr; 4473 struct ahc_dma_seg *segs; 4474 int newcount; 4475 int i; 4476 4477 scb_data = ahc->scb_data; 4478 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4479 /* Can't allocate any more */ 4480 return; 4481 4482 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4483 4484 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4485 4486 if (sg_map == NULL) 4487 return; 4488 4489 /* Allocate S/G space for the next batch of SCBS */ 4490 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat, 4491 (void **)&sg_map->sg_vaddr, 4492 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4493 free(sg_map, M_DEVBUF); 4494 return; 4495 } 4496 4497 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4498 4499 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4500 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4501 &sg_map->sg_physaddr, /*flags*/0); 4502 4503 segs = sg_map->sg_vaddr; 4504 physaddr = sg_map->sg_physaddr; 4505 4506 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4507 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4508 for (i = 0; i < newcount; i++) { 4509 struct scb_platform_data *pdata; 4510 #ifndef __linux__ 4511 int error; 4512 #endif 4513 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4514 M_DEVBUF, M_NOWAIT); 4515 if (pdata == NULL) 4516 break; 4517 next_scb->platform_data = pdata; 4518 next_scb->sg_map = sg_map; 4519 next_scb->sg_list = segs; 4520 /* 4521 * The sequencer always starts with the second entry. 4522 * The first entry is embedded in the scb. 4523 */ 4524 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4525 next_scb->ahc_softc = ahc; 4526 next_scb->flags = SCB_FLAG_NONE; 4527 #ifndef __linux__ 4528 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4529 &next_scb->dmamap); 4530 if (error != 0) 4531 break; 4532 #endif 4533 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4534 next_scb->hscb->tag = ahc->scb_data->numscbs; 4535 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4536 next_scb, links.sle); 4537 segs += AHC_NSEG; 4538 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4539 next_scb++; 4540 ahc->scb_data->numscbs++; 4541 } 4542 } 4543 4544 void 4545 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4546 { 4547 int len; 4548 4549 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4550 buf += len; 4551 if ((ahc->features & AHC_TWIN) != 0) 4552 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4553 "B SCSI Id=%d, primary %c, ", 4554 ahc->our_id, ahc->our_id_b, 4555 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4556 else { 4557 const char *speed; 4558 const char *type; 4559 4560 speed = ""; 4561 if ((ahc->features & AHC_ULTRA) != 0) { 4562 speed = "Ultra "; 4563 } else if ((ahc->features & AHC_DT) != 0) { 4564 speed = "Ultra160 "; 4565 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4566 speed = "Ultra2 "; 4567 } 4568 if ((ahc->features & AHC_WIDE) != 0) { 4569 type = "Wide"; 4570 } else { 4571 type = "Single"; 4572 } 4573 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4574 speed, type, ahc->channel, ahc->our_id); 4575 } 4576 buf += len; 4577 4578 if ((ahc->flags & AHC_PAGESCBS) != 0) 4579 sprintf(buf, "%d/%d SCBs", 4580 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4581 else 4582 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4583 } 4584 4585 int 4586 ahc_chip_init(struct ahc_softc *ahc) 4587 { 4588 int term; 4589 int error; 4590 u_int i; 4591 u_int scsi_conf; 4592 u_int scsiseq_template; 4593 uint32_t physaddr; 4594 4595 ahc_outb(ahc, SEQ_FLAGS, 0); 4596 ahc_outb(ahc, SEQ_FLAGS2, 0); 4597 4598 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4599 if (ahc->features & AHC_TWIN) { 4600 4601 /* 4602 * Setup Channel B first. 4603 */ 4604 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4605 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4606 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4607 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4608 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4609 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4610 if ((ahc->features & AHC_ULTRA2) != 0) 4611 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4612 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4613 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4614 4615 /* Select Channel A */ 4616 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4617 } 4618 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4619 if ((ahc->features & AHC_ULTRA2) != 0) 4620 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4621 else 4622 ahc_outb(ahc, SCSIID, ahc->our_id); 4623 scsi_conf = ahc_inb(ahc, SCSICONF); 4624 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4625 |term|ahc->seltime 4626 |ENSTIMER|ACTNEGEN); 4627 if ((ahc->features & AHC_ULTRA2) != 0) 4628 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4629 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4630 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4631 4632 /* There are no untagged SCBs active yet. */ 4633 for (i = 0; i < 16; i++) { 4634 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4635 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4636 int lun; 4637 4638 /* 4639 * The SCB based BTT allows an entry per 4640 * target and lun pair. 4641 */ 4642 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4643 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4644 } 4645 } 4646 4647 /* All of our queues are empty */ 4648 for (i = 0; i < 256; i++) 4649 ahc->qoutfifo[i] = SCB_LIST_NULL; 4650 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4651 4652 for (i = 0; i < 256; i++) 4653 ahc->qinfifo[i] = SCB_LIST_NULL; 4654 4655 if ((ahc->features & AHC_MULTI_TID) != 0) { 4656 ahc_outb(ahc, TARGID, 0); 4657 ahc_outb(ahc, TARGID + 1, 0); 4658 } 4659 4660 /* 4661 * Tell the sequencer where it can find our arrays in memory. 4662 */ 4663 physaddr = ahc->scb_data->hscb_busaddr; 4664 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4665 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4666 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4667 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4668 4669 physaddr = ahc->shared_data_busaddr; 4670 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4671 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4672 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4673 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4674 4675 /* 4676 * Initialize the group code to command length table. 4677 * This overrides the values in TARG_SCSIRATE, so only 4678 * setup the table after we have processed that information. 4679 */ 4680 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4681 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4682 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4683 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4684 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4685 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4686 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4687 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4688 4689 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4690 ahc_outb(ahc, HS_MAILBOX, 0); 4691 4692 /* Tell the sequencer of our initial queue positions */ 4693 if ((ahc->features & AHC_TARGETMODE) != 0) { 4694 ahc->tqinfifonext = 1; 4695 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4696 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4697 } 4698 ahc->qinfifonext = 0; 4699 ahc->qoutfifonext = 0; 4700 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4701 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4702 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4703 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4704 ahc_outb(ahc, SDSCB_QOFF, 0); 4705 } else { 4706 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4707 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4708 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4709 } 4710 4711 /* We don't have any waiting selections */ 4712 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4713 4714 /* Our disconnection list is empty too */ 4715 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4716 4717 /* Message out buffer starts empty */ 4718 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4719 4720 /* 4721 * Setup the allowed SCSI Sequences based on operational mode. 4722 * If we are a target, we'll enalbe select in operations once 4723 * we've had a lun enabled. 4724 */ 4725 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4726 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4727 scsiseq_template |= ENRSELI; 4728 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4729 4730 /* Initialize our list of free SCBs. */ 4731 ahc_build_free_scb_list(ahc); 4732 4733 /* 4734 * Tell the sequencer which SCB will be the next one it receives. 4735 */ 4736 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4737 4738 /* 4739 * Load the Sequencer program and Enable the adapter 4740 * in "fast" mode. 4741 */ 4742 if (bootverbose) 4743 printf("%s: Downloading Sequencer Program...", 4744 ahc_name(ahc)); 4745 4746 error = ahc_loadseq(ahc); 4747 if (error != 0) 4748 return (error); 4749 4750 if ((ahc->features & AHC_ULTRA2) != 0) { 4751 int wait; 4752 4753 /* 4754 * Wait for up to 500ms for our transceivers 4755 * to settle. If the adapter does not have 4756 * a cable attached, the transceivers may 4757 * never settle, so don't complain if we 4758 * fail here. 4759 */ 4760 for (wait = 5000; 4761 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4762 wait--) 4763 aic_delay(100); 4764 } 4765 ahc_restart(ahc); 4766 return (0); 4767 } 4768 4769 /* 4770 * Start the board, ready for normal operation 4771 */ 4772 int 4773 ahc_init(struct ahc_softc *ahc) 4774 { 4775 int max_targ; 4776 int error; 4777 u_int i; 4778 u_int scsi_conf; 4779 u_int ultraenb; 4780 u_int discenable; 4781 u_int tagenable; 4782 size_t driver_data_size; 4783 4784 #ifdef AHC_DEBUG 4785 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4786 ahc->flags |= AHC_SEQUENCER_DEBUG; 4787 #endif 4788 4789 #ifdef AHC_PRINT_SRAM 4790 printf("Scratch Ram:"); 4791 for (i = 0x20; i < 0x5f; i++) { 4792 if (((i % 8) == 0) && (i != 0)) { 4793 printf ("\n "); 4794 } 4795 printf (" 0x%x", ahc_inb(ahc, i)); 4796 } 4797 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4798 for (i = 0x70; i < 0x7f; i++) { 4799 if (((i % 8) == 0) && (i != 0)) { 4800 printf ("\n "); 4801 } 4802 printf (" 0x%x", ahc_inb(ahc, i)); 4803 } 4804 } 4805 printf ("\n"); 4806 /* 4807 * Reading uninitialized scratch ram may 4808 * generate parity errors. 4809 */ 4810 ahc_outb(ahc, CLRINT, CLRPARERR); 4811 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4812 #endif 4813 max_targ = 15; 4814 4815 /* 4816 * Assume we have a board at this stage and it has been reset. 4817 */ 4818 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4819 ahc->our_id = ahc->our_id_b = 7; 4820 4821 /* 4822 * Default to allowing initiator operations. 4823 */ 4824 ahc->flags |= AHC_INITIATORROLE; 4825 4826 /* 4827 * Only allow target mode features if this unit has them enabled. 4828 */ 4829 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4830 ahc->features &= ~AHC_TARGETMODE; 4831 4832 #ifndef __linux__ 4833 /* DMA tag for mapping buffers into device visible space. */ 4834 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4835 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4836 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4837 ? (bus_addr_t)0x7FFFFFFFFFULL 4838 : BUS_SPACE_MAXADDR_32BIT, 4839 /*highaddr*/BUS_SPACE_MAXADDR, 4840 /*filter*/NULL, /*filterarg*/NULL, 4841 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4842 /*nsegments*/AHC_NSEG, 4843 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4844 /*flags*/BUS_DMA_ALLOCNOW, 4845 &ahc->buffer_dmat) != 0) { 4846 return (ENOMEM); 4847 } 4848 #endif 4849 4850 ahc->init_level++; 4851 4852 /* 4853 * DMA tag for our command fifos and other data in system memory 4854 * the card's sequencer must be able to access. For initiator 4855 * roles, we need to allocate space for the qinfifo and qoutfifo. 4856 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4857 * When providing for the target mode role, we must additionally 4858 * provide space for the incoming target command fifo and an extra 4859 * byte to deal with a dma bug in some chip versions. 4860 */ 4861 driver_data_size = 2 * 256 * sizeof(uint8_t); 4862 if ((ahc->features & AHC_TARGETMODE) != 0) 4863 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4864 + /*DMA WideOdd Bug Buffer*/1; 4865 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4866 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4867 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4868 /*highaddr*/BUS_SPACE_MAXADDR, 4869 /*filter*/NULL, /*filterarg*/NULL, 4870 driver_data_size, 4871 /*nsegments*/1, 4872 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4873 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4874 return (ENOMEM); 4875 } 4876 4877 ahc->init_level++; 4878 4879 /* Allocation of driver data */ 4880 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat, 4881 (void **)&ahc->qoutfifo, 4882 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4883 return (ENOMEM); 4884 } 4885 4886 ahc->init_level++; 4887 4888 /* And permanently map it in */ 4889 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4890 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4891 &ahc->shared_data_busaddr, /*flags*/0); 4892 4893 if ((ahc->features & AHC_TARGETMODE) != 0) { 4894 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4895 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4896 ahc->dma_bug_buf = ahc->shared_data_busaddr 4897 + driver_data_size - 1; 4898 /* All target command blocks start out invalid. */ 4899 for (i = 0; i < AHC_TMODE_CMDS; i++) 4900 ahc->targetcmds[i].cmd_valid = 0; 4901 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4902 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4903 } 4904 ahc->qinfifo = &ahc->qoutfifo[256]; 4905 4906 ahc->init_level++; 4907 4908 /* Allocate SCB data now that buffer_dmat is initialized */ 4909 if (ahc->scb_data->maxhscbs == 0) 4910 if (ahc_init_scbdata(ahc) != 0) 4911 return (ENOMEM); 4912 4913 /* 4914 * Allocate a tstate to house information for our 4915 * initiator presence on the bus as well as the user 4916 * data for any target mode initiator. 4917 */ 4918 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4919 printf("%s: unable to allocate ahc_tmode_tstate. " 4920 "Failing attach\n", ahc_name(ahc)); 4921 return (ENOMEM); 4922 } 4923 4924 if ((ahc->features & AHC_TWIN) != 0) { 4925 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4926 printf("%s: unable to allocate ahc_tmode_tstate. " 4927 "Failing attach\n", ahc_name(ahc)); 4928 return (ENOMEM); 4929 } 4930 } 4931 4932 /* 4933 * Fire up a recovery thread for this controller. 4934 */ 4935 error = ahc_spawn_recovery_thread(ahc); 4936 if (error != 0) 4937 return (error); 4938 4939 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4940 ahc->flags |= AHC_PAGESCBS; 4941 } else { 4942 ahc->flags &= ~AHC_PAGESCBS; 4943 } 4944 4945 #ifdef AHC_DEBUG 4946 if (ahc_debug & AHC_SHOW_MISC) { 4947 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4948 "ahc_dma %u bytes\n", 4949 ahc_name(ahc), 4950 (u_int)sizeof(struct hardware_scb), 4951 (u_int)sizeof(struct scb), 4952 (u_int)sizeof(struct ahc_dma_seg)); 4953 } 4954 #endif /* AHC_DEBUG */ 4955 4956 /* 4957 * Look at the information that board initialization or 4958 * the board bios has left us. 4959 */ 4960 if (ahc->features & AHC_TWIN) { 4961 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4962 if ((scsi_conf & RESET_SCSI) != 0 4963 && (ahc->flags & AHC_INITIATORROLE) != 0) 4964 ahc->flags |= AHC_RESET_BUS_B; 4965 } 4966 4967 scsi_conf = ahc_inb(ahc, SCSICONF); 4968 if ((scsi_conf & RESET_SCSI) != 0 4969 && (ahc->flags & AHC_INITIATORROLE) != 0) 4970 ahc->flags |= AHC_RESET_BUS_A; 4971 4972 ultraenb = 0; 4973 tagenable = ALL_TARGETS_MASK; 4974 4975 /* Grab the disconnection disable table and invert it for our needs */ 4976 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4977 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4978 "device parameters\n", ahc_name(ahc)); 4979 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4980 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4981 discenable = ALL_TARGETS_MASK; 4982 if ((ahc->features & AHC_ULTRA) != 0) 4983 ultraenb = ALL_TARGETS_MASK; 4984 } else { 4985 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4986 | ahc_inb(ahc, DISC_DSB)); 4987 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4988 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4989 | ahc_inb(ahc, ULTRA_ENB); 4990 } 4991 4992 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4993 max_targ = 7; 4994 4995 for (i = 0; i <= max_targ; i++) { 4996 struct ahc_initiator_tinfo *tinfo; 4997 struct ahc_tmode_tstate *tstate; 4998 u_int our_id; 4999 u_int target_id; 5000 char channel; 5001 5002 channel = 'A'; 5003 our_id = ahc->our_id; 5004 target_id = i; 5005 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 5006 channel = 'B'; 5007 our_id = ahc->our_id_b; 5008 target_id = i % 8; 5009 } 5010 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 5011 target_id, &tstate); 5012 /* Default to async narrow across the board */ 5013 memset(tinfo, 0, sizeof(*tinfo)); 5014 if (ahc->flags & AHC_USEDEFAULTS) { 5015 if ((ahc->features & AHC_WIDE) != 0) 5016 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5017 5018 /* 5019 * These will be truncated when we determine the 5020 * connection type we have with the target. 5021 */ 5022 tinfo->user.period = ahc_syncrates->period; 5023 tinfo->user.offset = MAX_OFFSET; 5024 } else { 5025 u_int scsirate; 5026 uint16_t mask; 5027 5028 /* Take the settings leftover in scratch RAM. */ 5029 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 5030 mask = (0x01 << i); 5031 if ((ahc->features & AHC_ULTRA2) != 0) { 5032 u_int offset; 5033 u_int maxsync; 5034 5035 if ((scsirate & SOFS) == 0x0F) { 5036 /* 5037 * Haven't negotiated yet, 5038 * so the format is different. 5039 */ 5040 scsirate = (scsirate & SXFR) >> 4 5041 | (ultraenb & mask) 5042 ? 0x08 : 0x0 5043 | (scsirate & WIDEXFER); 5044 offset = MAX_OFFSET_ULTRA2; 5045 } else 5046 offset = ahc_inb(ahc, TARG_OFFSET + i); 5047 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 5048 /* Set to the lowest sync rate, 5MHz */ 5049 scsirate |= 0x1c; 5050 maxsync = AHC_SYNCRATE_ULTRA2; 5051 if ((ahc->features & AHC_DT) != 0) 5052 maxsync = AHC_SYNCRATE_DT; 5053 tinfo->user.period = 5054 ahc_find_period(ahc, scsirate, maxsync); 5055 if (offset == 0) 5056 tinfo->user.period = 0; 5057 else 5058 tinfo->user.offset = MAX_OFFSET; 5059 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 5060 && (ahc->features & AHC_DT) != 0) 5061 tinfo->user.ppr_options = 5062 MSG_EXT_PPR_DT_REQ; 5063 } else if ((scsirate & SOFS) != 0) { 5064 if ((scsirate & SXFR) == 0x40 5065 && (ultraenb & mask) != 0) { 5066 /* Treat 10MHz as a non-ultra speed */ 5067 scsirate &= ~SXFR; 5068 ultraenb &= ~mask; 5069 } 5070 tinfo->user.period = 5071 ahc_find_period(ahc, scsirate, 5072 (ultraenb & mask) 5073 ? AHC_SYNCRATE_ULTRA 5074 : AHC_SYNCRATE_FAST); 5075 if (tinfo->user.period != 0) 5076 tinfo->user.offset = MAX_OFFSET; 5077 } 5078 if (tinfo->user.period == 0) 5079 tinfo->user.offset = 0; 5080 if ((scsirate & WIDEXFER) != 0 5081 && (ahc->features & AHC_WIDE) != 0) 5082 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5083 tinfo->user.protocol_version = 4; 5084 if ((ahc->features & AHC_DT) != 0) 5085 tinfo->user.transport_version = 3; 5086 else 5087 tinfo->user.transport_version = 2; 5088 tinfo->goal.protocol_version = 2; 5089 tinfo->goal.transport_version = 2; 5090 tinfo->curr.protocol_version = 2; 5091 tinfo->curr.transport_version = 2; 5092 } 5093 tstate->ultraenb = 0; 5094 } 5095 ahc->user_discenable = discenable; 5096 ahc->user_tagenable = tagenable; 5097 5098 return (ahc->bus_chip_init(ahc)); 5099 } 5100 5101 void 5102 ahc_intr_enable(struct ahc_softc *ahc, int enable) 5103 { 5104 u_int hcntrl; 5105 5106 hcntrl = ahc_inb(ahc, HCNTRL); 5107 hcntrl &= ~INTEN; 5108 ahc->pause &= ~INTEN; 5109 ahc->unpause &= ~INTEN; 5110 if (enable) { 5111 hcntrl |= INTEN; 5112 ahc->pause |= INTEN; 5113 ahc->unpause |= INTEN; 5114 } 5115 ahc_outb(ahc, HCNTRL, hcntrl); 5116 } 5117 5118 /* 5119 * Ensure that the card is paused in a location 5120 * outside of all critical sections and that all 5121 * pending work is completed prior to returning. 5122 * This routine should only be called from outside 5123 * an interrupt context. 5124 */ 5125 void 5126 ahc_pause_and_flushwork(struct ahc_softc *ahc) 5127 { 5128 int intstat; 5129 int maxloops; 5130 int paused; 5131 5132 maxloops = 1000; 5133 ahc->flags |= AHC_ALL_INTERRUPTS; 5134 paused = FALSE; 5135 do { 5136 if (paused) { 5137 ahc_unpause(ahc); 5138 /* 5139 * Give the sequencer some time to service 5140 * any active selections. 5141 */ 5142 aic_delay(500); 5143 } 5144 ahc_intr(ahc); 5145 ahc_pause(ahc); 5146 paused = TRUE; 5147 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5148 intstat = ahc_inb(ahc, INTSTAT); 5149 if ((intstat & INT_PEND) == 0) { 5150 ahc_clear_critical_section(ahc); 5151 intstat = ahc_inb(ahc, INTSTAT); 5152 } 5153 } while (--maxloops 5154 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5155 && ((intstat & INT_PEND) != 0 5156 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5157 if (maxloops == 0) { 5158 printf("Infinite interrupt loop, INTSTAT = %x", 5159 ahc_inb(ahc, INTSTAT)); 5160 } 5161 ahc_platform_flushwork(ahc); 5162 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5163 } 5164 5165 int 5166 ahc_suspend(struct ahc_softc *ahc) 5167 { 5168 5169 ahc_pause_and_flushwork(ahc); 5170 5171 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5172 ahc_unpause(ahc); 5173 return (EBUSY); 5174 } 5175 5176 #ifdef AHC_TARGET_MODE 5177 /* 5178 * XXX What about ATIOs that have not yet been serviced? 5179 * Perhaps we should just refuse to be suspended if we 5180 * are acting in a target role. 5181 */ 5182 if (ahc->pending_device != NULL) { 5183 ahc_unpause(ahc); 5184 return (EBUSY); 5185 } 5186 #endif 5187 ahc_shutdown(ahc); 5188 return (0); 5189 } 5190 5191 int 5192 ahc_resume(struct ahc_softc *ahc) 5193 { 5194 5195 ahc_reset(ahc, /*reinit*/TRUE); 5196 ahc_intr_enable(ahc, TRUE); 5197 ahc_restart(ahc); 5198 return (0); 5199 } 5200 5201 /************************** Busy Target Table *********************************/ 5202 /* 5203 * Return the untagged transaction id for a given target/channel lun. 5204 * Optionally, clear the entry. 5205 */ 5206 u_int 5207 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5208 { 5209 u_int scbid; 5210 u_int target_offset; 5211 5212 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5213 u_int saved_scbptr; 5214 5215 saved_scbptr = ahc_inb(ahc, SCBPTR); 5216 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5217 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5218 ahc_outb(ahc, SCBPTR, saved_scbptr); 5219 } else { 5220 target_offset = TCL_TARGET_OFFSET(tcl); 5221 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5222 } 5223 5224 return (scbid); 5225 } 5226 5227 void 5228 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5229 { 5230 u_int target_offset; 5231 5232 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5233 u_int saved_scbptr; 5234 5235 saved_scbptr = ahc_inb(ahc, SCBPTR); 5236 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5237 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5238 ahc_outb(ahc, SCBPTR, saved_scbptr); 5239 } else { 5240 target_offset = TCL_TARGET_OFFSET(tcl); 5241 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5242 } 5243 } 5244 5245 void 5246 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5247 { 5248 u_int target_offset; 5249 5250 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5251 u_int saved_scbptr; 5252 5253 saved_scbptr = ahc_inb(ahc, SCBPTR); 5254 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5255 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5256 ahc_outb(ahc, SCBPTR, saved_scbptr); 5257 } else { 5258 target_offset = TCL_TARGET_OFFSET(tcl); 5259 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5260 } 5261 } 5262 5263 /************************** SCB and SCB queue management **********************/ 5264 int 5265 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5266 char channel, int lun, u_int tag, role_t role) 5267 { 5268 int targ = SCB_GET_TARGET(ahc, scb); 5269 char chan = SCB_GET_CHANNEL(ahc, scb); 5270 int slun = SCB_GET_LUN(scb); 5271 int match; 5272 5273 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5274 if (match != 0) 5275 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5276 if (match != 0) 5277 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5278 if (match != 0) { 5279 #ifdef AHC_TARGET_MODE 5280 int group; 5281 5282 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5283 if (role == ROLE_INITIATOR) { 5284 match = (group != XPT_FC_GROUP_TMODE) 5285 && ((tag == scb->hscb->tag) 5286 || (tag == SCB_LIST_NULL)); 5287 } else if (role == ROLE_TARGET) { 5288 match = (group == XPT_FC_GROUP_TMODE) 5289 && ((tag == scb->io_ctx->csio.tag_id) 5290 || (tag == SCB_LIST_NULL)); 5291 } 5292 #else /* !AHC_TARGET_MODE */ 5293 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5294 #endif /* AHC_TARGET_MODE */ 5295 } 5296 5297 return match; 5298 } 5299 5300 void 5301 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5302 { 5303 int target; 5304 char channel; 5305 int lun; 5306 5307 target = SCB_GET_TARGET(ahc, scb); 5308 lun = SCB_GET_LUN(scb); 5309 channel = SCB_GET_CHANNEL(ahc, scb); 5310 5311 ahc_search_qinfifo(ahc, target, channel, lun, 5312 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5313 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5314 5315 ahc_platform_freeze_devq(ahc, scb); 5316 } 5317 5318 void 5319 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5320 { 5321 struct scb *prev_scb; 5322 5323 prev_scb = NULL; 5324 if (ahc_qinfifo_count(ahc) != 0) { 5325 u_int prev_tag; 5326 uint8_t prev_pos; 5327 5328 prev_pos = ahc->qinfifonext - 1; 5329 prev_tag = ahc->qinfifo[prev_pos]; 5330 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5331 } 5332 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5333 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5334 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5335 } else { 5336 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5337 } 5338 } 5339 5340 static void 5341 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5342 struct scb *scb) 5343 { 5344 if (prev_scb == NULL) { 5345 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5346 } else { 5347 prev_scb->hscb->next = scb->hscb->tag; 5348 ahc_sync_scb(ahc, prev_scb, 5349 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5350 } 5351 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5352 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5353 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5354 } 5355 5356 static int 5357 ahc_qinfifo_count(struct ahc_softc *ahc) 5358 { 5359 uint8_t qinpos; 5360 uint8_t diff; 5361 5362 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5363 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5364 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5365 } else 5366 qinpos = ahc_inb(ahc, QINPOS); 5367 diff = ahc->qinfifonext - qinpos; 5368 return (diff); 5369 } 5370 5371 int 5372 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5373 int lun, u_int tag, role_t role, uint32_t status, 5374 ahc_search_action action) 5375 { 5376 struct scb *scb; 5377 struct scb *prev_scb; 5378 uint8_t qinstart; 5379 uint8_t qinpos; 5380 uint8_t qintail; 5381 uint8_t next; 5382 uint8_t prev; 5383 uint8_t curscbptr; 5384 int found; 5385 int have_qregs; 5386 5387 qintail = ahc->qinfifonext; 5388 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5389 if (have_qregs) { 5390 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5391 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5392 } else 5393 qinstart = ahc_inb(ahc, QINPOS); 5394 qinpos = qinstart; 5395 found = 0; 5396 prev_scb = NULL; 5397 5398 if (action == SEARCH_COMPLETE) { 5399 /* 5400 * Don't attempt to run any queued untagged transactions 5401 * until we are done with the abort process. 5402 */ 5403 ahc_freeze_untagged_queues(ahc); 5404 } 5405 5406 /* 5407 * Start with an empty queue. Entries that are not chosen 5408 * for removal will be re-added to the queue as we go. 5409 */ 5410 ahc->qinfifonext = qinpos; 5411 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5412 5413 while (qinpos != qintail) { 5414 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5415 if (scb == NULL) { 5416 printf("qinpos = %d, SCB index = %d\n", 5417 qinpos, ahc->qinfifo[qinpos]); 5418 panic("Loop 1\n"); 5419 } 5420 5421 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5422 /* 5423 * We found an scb that needs to be acted on. 5424 */ 5425 found++; 5426 switch (action) { 5427 case SEARCH_COMPLETE: 5428 { 5429 cam_status ostat; 5430 cam_status cstat; 5431 5432 ostat = aic_get_transaction_status(scb); 5433 if (ostat == CAM_REQ_INPROG) 5434 aic_set_transaction_status(scb, status); 5435 cstat = aic_get_transaction_status(scb); 5436 if (cstat != CAM_REQ_CMP) 5437 aic_freeze_scb(scb); 5438 if ((scb->flags & SCB_ACTIVE) == 0) 5439 printf("Inactive SCB in qinfifo\n"); 5440 ahc_done(ahc, scb); 5441 5442 /* FALLTHROUGH */ 5443 } 5444 case SEARCH_REMOVE: 5445 break; 5446 case SEARCH_COUNT: 5447 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5448 prev_scb = scb; 5449 break; 5450 } 5451 } else { 5452 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5453 prev_scb = scb; 5454 } 5455 qinpos++; 5456 } 5457 5458 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5459 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5460 } else { 5461 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5462 } 5463 5464 if (action != SEARCH_COUNT 5465 && (found != 0) 5466 && (qinstart != ahc->qinfifonext)) { 5467 /* 5468 * The sequencer may be in the process of dmaing 5469 * down the SCB at the beginning of the queue. 5470 * This could be problematic if either the first, 5471 * or the second SCB is removed from the queue 5472 * (the first SCB includes a pointer to the "next" 5473 * SCB to dma). If we have removed any entries, swap 5474 * the first element in the queue with the next HSCB 5475 * so the sequencer will notice that NEXT_QUEUED_SCB 5476 * has changed during its dma attempt and will retry 5477 * the DMA. 5478 */ 5479 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5480 5481 if (scb == NULL) { 5482 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5483 found, qinstart, ahc->qinfifonext); 5484 panic("First/Second Qinfifo fixup\n"); 5485 } 5486 /* 5487 * ahc_swap_with_next_hscb forces our next pointer to 5488 * point to the reserved SCB for future commands. Save 5489 * and restore our original next pointer to maintain 5490 * queue integrity. 5491 */ 5492 next = scb->hscb->next; 5493 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5494 ahc_swap_with_next_hscb(ahc, scb); 5495 scb->hscb->next = next; 5496 ahc->qinfifo[qinstart] = scb->hscb->tag; 5497 5498 /* Tell the card about the new head of the qinfifo. */ 5499 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5500 5501 /* Fixup the tail "next" pointer. */ 5502 qintail = ahc->qinfifonext - 1; 5503 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5504 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5505 } 5506 5507 /* 5508 * Search waiting for selection list. 5509 */ 5510 curscbptr = ahc_inb(ahc, SCBPTR); 5511 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5512 prev = SCB_LIST_NULL; 5513 5514 while (next != SCB_LIST_NULL) { 5515 uint8_t scb_index; 5516 5517 ahc_outb(ahc, SCBPTR, next); 5518 scb_index = ahc_inb(ahc, SCB_TAG); 5519 if (scb_index >= ahc->scb_data->numscbs) { 5520 printf("Waiting List inconsistency. " 5521 "SCB index == %d, yet numscbs == %d.", 5522 scb_index, ahc->scb_data->numscbs); 5523 ahc_dump_card_state(ahc); 5524 panic("for safety"); 5525 } 5526 scb = ahc_lookup_scb(ahc, scb_index); 5527 if (scb == NULL) { 5528 printf("scb_index = %d, next = %d\n", 5529 scb_index, next); 5530 panic("Waiting List traversal\n"); 5531 } 5532 if (ahc_match_scb(ahc, scb, target, channel, 5533 lun, SCB_LIST_NULL, role)) { 5534 /* 5535 * We found an scb that needs to be acted on. 5536 */ 5537 found++; 5538 switch (action) { 5539 case SEARCH_COMPLETE: 5540 { 5541 cam_status ostat; 5542 cam_status cstat; 5543 5544 ostat = aic_get_transaction_status(scb); 5545 if (ostat == CAM_REQ_INPROG) 5546 aic_set_transaction_status(scb, 5547 status); 5548 cstat = aic_get_transaction_status(scb); 5549 if (cstat != CAM_REQ_CMP) 5550 aic_freeze_scb(scb); 5551 if ((scb->flags & SCB_ACTIVE) == 0) 5552 printf("Inactive SCB in Wait List\n"); 5553 ahc_done(ahc, scb); 5554 /* FALLTHROUGH */ 5555 } 5556 case SEARCH_REMOVE: 5557 next = ahc_rem_wscb(ahc, next, prev); 5558 break; 5559 case SEARCH_COUNT: 5560 prev = next; 5561 next = ahc_inb(ahc, SCB_NEXT); 5562 break; 5563 } 5564 } else { 5565 5566 prev = next; 5567 next = ahc_inb(ahc, SCB_NEXT); 5568 } 5569 } 5570 ahc_outb(ahc, SCBPTR, curscbptr); 5571 5572 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target, 5573 channel, lun, status, action); 5574 5575 if (action == SEARCH_COMPLETE) 5576 ahc_release_untagged_queues(ahc); 5577 return (found); 5578 } 5579 5580 int 5581 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx, 5582 int target, char channel, int lun, uint32_t status, 5583 ahc_search_action action) 5584 { 5585 struct scb *scb; 5586 int maxtarget; 5587 int found; 5588 int i; 5589 5590 if (action == SEARCH_COMPLETE) { 5591 /* 5592 * Don't attempt to run any queued untagged transactions 5593 * until we are done with the abort process. 5594 */ 5595 ahc_freeze_untagged_queues(ahc); 5596 } 5597 5598 found = 0; 5599 i = 0; 5600 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5601 5602 maxtarget = 16; 5603 if (target != CAM_TARGET_WILDCARD) { 5604 5605 i = target; 5606 if (channel == 'B') 5607 i += 8; 5608 maxtarget = i + 1; 5609 } 5610 } else { 5611 maxtarget = 0; 5612 } 5613 5614 for (; i < maxtarget; i++) { 5615 struct scb_tailq *untagged_q; 5616 struct scb *next_scb; 5617 5618 untagged_q = &(ahc->untagged_queues[i]); 5619 next_scb = TAILQ_FIRST(untagged_q); 5620 while (next_scb != NULL) { 5621 5622 scb = next_scb; 5623 next_scb = TAILQ_NEXT(scb, links.tqe); 5624 5625 /* 5626 * The head of the list may be the currently 5627 * active untagged command for a device. 5628 * We're only searching for commands that 5629 * have not been started. A transaction 5630 * marked active but still in the qinfifo 5631 * is removed by the qinfifo scanning code 5632 * above. 5633 */ 5634 if ((scb->flags & SCB_ACTIVE) != 0) 5635 continue; 5636 5637 if (ahc_match_scb(ahc, scb, target, channel, lun, 5638 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5639 || (ctx != NULL && ctx != scb->io_ctx)) 5640 continue; 5641 5642 /* 5643 * We found an scb that needs to be acted on. 5644 */ 5645 found++; 5646 switch (action) { 5647 case SEARCH_COMPLETE: 5648 { 5649 cam_status ostat; 5650 cam_status cstat; 5651 5652 ostat = aic_get_transaction_status(scb); 5653 if (ostat == CAM_REQ_INPROG) 5654 aic_set_transaction_status(scb, status); 5655 cstat = aic_get_transaction_status(scb); 5656 if (cstat != CAM_REQ_CMP) 5657 aic_freeze_scb(scb); 5658 ahc_done(ahc, scb); 5659 break; 5660 } 5661 case SEARCH_REMOVE: 5662 scb->flags &= ~SCB_UNTAGGEDQ; 5663 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5664 break; 5665 case SEARCH_COUNT: 5666 break; 5667 } 5668 } 5669 } 5670 5671 if (action == SEARCH_COMPLETE) 5672 ahc_release_untagged_queues(ahc); 5673 return (found); 5674 } 5675 5676 int 5677 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5678 int lun, u_int tag, int stop_on_first, int remove, 5679 int save_state) 5680 { 5681 struct scb *scbp; 5682 u_int next; 5683 u_int prev; 5684 u_int count; 5685 u_int active_scb; 5686 5687 count = 0; 5688 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5689 prev = SCB_LIST_NULL; 5690 5691 if (save_state) { 5692 /* restore this when we're done */ 5693 active_scb = ahc_inb(ahc, SCBPTR); 5694 } else 5695 /* Silence compiler */ 5696 active_scb = SCB_LIST_NULL; 5697 5698 while (next != SCB_LIST_NULL) { 5699 u_int scb_index; 5700 5701 ahc_outb(ahc, SCBPTR, next); 5702 scb_index = ahc_inb(ahc, SCB_TAG); 5703 if (scb_index >= ahc->scb_data->numscbs) { 5704 printf("Disconnected List inconsistency. " 5705 "SCB index == %d, yet numscbs == %d.", 5706 scb_index, ahc->scb_data->numscbs); 5707 ahc_dump_card_state(ahc); 5708 panic("for safety"); 5709 } 5710 5711 if (next == prev) { 5712 panic("Disconnected List Loop. " 5713 "cur SCBPTR == %x, prev SCBPTR == %x.", 5714 next, prev); 5715 } 5716 scbp = ahc_lookup_scb(ahc, scb_index); 5717 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5718 tag, ROLE_INITIATOR)) { 5719 count++; 5720 if (remove) { 5721 next = 5722 ahc_rem_scb_from_disc_list(ahc, prev, next); 5723 } else { 5724 prev = next; 5725 next = ahc_inb(ahc, SCB_NEXT); 5726 } 5727 if (stop_on_first) 5728 break; 5729 } else { 5730 prev = next; 5731 next = ahc_inb(ahc, SCB_NEXT); 5732 } 5733 } 5734 if (save_state) 5735 ahc_outb(ahc, SCBPTR, active_scb); 5736 return (count); 5737 } 5738 5739 /* 5740 * Remove an SCB from the on chip list of disconnected transactions. 5741 * This is empty/unused if we are not performing SCB paging. 5742 */ 5743 static u_int 5744 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5745 { 5746 u_int next; 5747 5748 ahc_outb(ahc, SCBPTR, scbptr); 5749 next = ahc_inb(ahc, SCB_NEXT); 5750 5751 ahc_outb(ahc, SCB_CONTROL, 0); 5752 5753 ahc_add_curscb_to_free_list(ahc); 5754 5755 if (prev != SCB_LIST_NULL) { 5756 ahc_outb(ahc, SCBPTR, prev); 5757 ahc_outb(ahc, SCB_NEXT, next); 5758 } else 5759 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5760 5761 return (next); 5762 } 5763 5764 /* 5765 * Add the SCB as selected by SCBPTR onto the on chip list of 5766 * free hardware SCBs. This list is empty/unused if we are not 5767 * performing SCB paging. 5768 */ 5769 static void 5770 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5771 { 5772 /* 5773 * Invalidate the tag so that our abort 5774 * routines don't think it's active. 5775 */ 5776 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5777 5778 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5779 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5780 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5781 } 5782 } 5783 5784 /* 5785 * Manipulate the waiting for selection list and return the 5786 * scb that follows the one that we remove. 5787 */ 5788 static u_int 5789 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5790 { 5791 u_int curscb, next; 5792 5793 /* 5794 * Select the SCB we want to abort and 5795 * pull the next pointer out of it. 5796 */ 5797 curscb = ahc_inb(ahc, SCBPTR); 5798 ahc_outb(ahc, SCBPTR, scbpos); 5799 next = ahc_inb(ahc, SCB_NEXT); 5800 5801 /* Clear the necessary fields */ 5802 ahc_outb(ahc, SCB_CONTROL, 0); 5803 5804 ahc_add_curscb_to_free_list(ahc); 5805 5806 /* update the waiting list */ 5807 if (prev == SCB_LIST_NULL) { 5808 /* First in the list */ 5809 ahc_outb(ahc, WAITING_SCBH, next); 5810 5811 /* 5812 * Ensure we aren't attempting to perform 5813 * selection for this entry. 5814 */ 5815 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5816 } else { 5817 /* 5818 * Select the scb that pointed to us 5819 * and update its next pointer. 5820 */ 5821 ahc_outb(ahc, SCBPTR, prev); 5822 ahc_outb(ahc, SCB_NEXT, next); 5823 } 5824 5825 /* 5826 * Point us back at the original scb position. 5827 */ 5828 ahc_outb(ahc, SCBPTR, curscb); 5829 return next; 5830 } 5831 5832 /******************************** Error Handling ******************************/ 5833 /* 5834 * Abort all SCBs that match the given description (target/channel/lun/tag), 5835 * setting their status to the passed in status if the status has not already 5836 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5837 * is paused before it is called. 5838 */ 5839 int 5840 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5841 int lun, u_int tag, role_t role, uint32_t status) 5842 { 5843 struct scb *scbp; 5844 struct scb *scbp_next; 5845 u_int active_scb; 5846 int i, j; 5847 int maxtarget; 5848 int minlun; 5849 int maxlun; 5850 5851 int found; 5852 5853 /* 5854 * Don't attempt to run any queued untagged transactions 5855 * until we are done with the abort process. 5856 */ 5857 ahc_freeze_untagged_queues(ahc); 5858 5859 /* restore this when we're done */ 5860 active_scb = ahc_inb(ahc, SCBPTR); 5861 5862 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5863 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5864 5865 /* 5866 * Clean out the busy target table for any untagged commands. 5867 */ 5868 i = 0; 5869 maxtarget = 16; 5870 if (target != CAM_TARGET_WILDCARD) { 5871 i = target; 5872 if (channel == 'B') 5873 i += 8; 5874 maxtarget = i + 1; 5875 } 5876 5877 if (lun == CAM_LUN_WILDCARD) { 5878 5879 /* 5880 * Unless we are using an SCB based 5881 * busy targets table, there is only 5882 * one table entry for all luns of 5883 * a target. 5884 */ 5885 minlun = 0; 5886 maxlun = 1; 5887 if ((ahc->flags & AHC_SCB_BTT) != 0) 5888 maxlun = AHC_NUM_LUNS; 5889 } else { 5890 minlun = lun; 5891 maxlun = lun + 1; 5892 } 5893 5894 if (role != ROLE_TARGET) { 5895 for (;i < maxtarget; i++) { 5896 for (j = minlun;j < maxlun; j++) { 5897 u_int scbid; 5898 u_int tcl; 5899 5900 tcl = BUILD_TCL(i << 4, j); 5901 scbid = ahc_index_busy_tcl(ahc, tcl); 5902 scbp = ahc_lookup_scb(ahc, scbid); 5903 if (scbp == NULL 5904 || ahc_match_scb(ahc, scbp, target, channel, 5905 lun, tag, role) == 0) 5906 continue; 5907 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5908 } 5909 } 5910 5911 /* 5912 * Go through the disconnected list and remove any entries we 5913 * have queued for completion, 0'ing their control byte too. 5914 * We save the active SCB and restore it ourselves, so there 5915 * is no reason for this search to restore it too. 5916 */ 5917 ahc_search_disc_list(ahc, target, channel, lun, tag, 5918 /*stop_on_first*/FALSE, /*remove*/TRUE, 5919 /*save_state*/FALSE); 5920 } 5921 5922 /* 5923 * Go through the hardware SCB array looking for commands that 5924 * were active but not on any list. In some cases, these remnants 5925 * might not still have mappings in the scbindex array (e.g. unexpected 5926 * bus free with the same scb queued for an abort). Don't hold this 5927 * against them. 5928 */ 5929 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5930 u_int scbid; 5931 5932 ahc_outb(ahc, SCBPTR, i); 5933 scbid = ahc_inb(ahc, SCB_TAG); 5934 scbp = ahc_lookup_scb(ahc, scbid); 5935 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5936 || (scbp != NULL 5937 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5938 ahc_add_curscb_to_free_list(ahc); 5939 } 5940 5941 /* 5942 * Go through the pending CCB list and look for 5943 * commands for this target that are still active. 5944 * These are other tagged commands that were 5945 * disconnected when the reset occurred. 5946 */ 5947 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5948 while (scbp_next != NULL) { 5949 scbp = scbp_next; 5950 scbp_next = LIST_NEXT(scbp, pending_links); 5951 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5952 cam_status ostat; 5953 5954 ostat = aic_get_transaction_status(scbp); 5955 if (ostat == CAM_REQ_INPROG) 5956 aic_set_transaction_status(scbp, status); 5957 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP) 5958 aic_freeze_scb(scbp); 5959 if ((scbp->flags & SCB_ACTIVE) == 0) 5960 printf("Inactive SCB on pending list\n"); 5961 ahc_done(ahc, scbp); 5962 found++; 5963 } 5964 } 5965 ahc_outb(ahc, SCBPTR, active_scb); 5966 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5967 ahc_release_untagged_queues(ahc); 5968 return found; 5969 } 5970 5971 static void 5972 ahc_reset_current_bus(struct ahc_softc *ahc) 5973 { 5974 uint8_t scsiseq; 5975 5976 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5977 scsiseq = ahc_inb(ahc, SCSISEQ); 5978 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5979 ahc_flush_device_writes(ahc); 5980 aic_delay(AHC_BUSRESET_DELAY); 5981 /* Turn off the bus reset */ 5982 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5983 5984 ahc_clear_intstat(ahc); 5985 5986 /* Re-enable reset interrupts */ 5987 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5988 } 5989 5990 int 5991 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5992 { 5993 struct ahc_devinfo devinfo; 5994 u_int initiator, target, max_scsiid; 5995 u_int sblkctl; 5996 u_int scsiseq; 5997 u_int simode1; 5998 int found; 5999 int restart_needed; 6000 char cur_channel; 6001 6002 ahc->pending_device = NULL; 6003 6004 ahc_compile_devinfo(&devinfo, 6005 CAM_TARGET_WILDCARD, 6006 CAM_TARGET_WILDCARD, 6007 CAM_LUN_WILDCARD, 6008 channel, ROLE_UNKNOWN); 6009 ahc_pause(ahc); 6010 6011 /* Make sure the sequencer is in a safe location. */ 6012 ahc_clear_critical_section(ahc); 6013 6014 /* 6015 * Run our command complete fifos to ensure that we perform 6016 * completion processing on any commands that 'completed' 6017 * before the reset occurred. 6018 */ 6019 ahc_run_qoutfifo(ahc); 6020 #ifdef AHC_TARGET_MODE 6021 /* 6022 * XXX - In Twin mode, the tqinfifo may have commands 6023 * for an unaffected channel in it. However, if 6024 * we have run out of ATIO resources to drain that 6025 * queue, we may not get them all out here. Further, 6026 * the blocked transactions for the reset channel 6027 * should just be killed off, irrespecitve of whether 6028 * we are blocked on ATIO resources. Write a routine 6029 * to compact the tqinfifo appropriately. 6030 */ 6031 if ((ahc->flags & AHC_TARGETROLE) != 0) { 6032 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 6033 } 6034 #endif 6035 6036 /* 6037 * Reset the bus if we are initiating this reset 6038 */ 6039 sblkctl = ahc_inb(ahc, SBLKCTL); 6040 cur_channel = 'A'; 6041 if ((ahc->features & AHC_TWIN) != 0 6042 && ((sblkctl & SELBUSB) != 0)) 6043 cur_channel = 'B'; 6044 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6045 if (cur_channel != channel) { 6046 /* Case 1: Command for another bus is active 6047 * Stealthily reset the other bus without 6048 * upsetting the current bus. 6049 */ 6050 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 6051 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6052 #ifdef AHC_TARGET_MODE 6053 /* 6054 * Bus resets clear ENSELI, so we cannot 6055 * defer re-enabling bus reset interrupts 6056 * if we are in target mode. 6057 */ 6058 if ((ahc->flags & AHC_TARGETROLE) != 0) 6059 simode1 |= ENSCSIRST; 6060 #endif 6061 ahc_outb(ahc, SIMODE1, simode1); 6062 if (initiate_reset) 6063 ahc_reset_current_bus(ahc); 6064 ahc_clear_intstat(ahc); 6065 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6066 ahc_outb(ahc, SBLKCTL, sblkctl); 6067 restart_needed = FALSE; 6068 } else { 6069 /* Case 2: A command from this bus is active or we're idle */ 6070 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6071 #ifdef AHC_TARGET_MODE 6072 /* 6073 * Bus resets clear ENSELI, so we cannot 6074 * defer re-enabling bus reset interrupts 6075 * if we are in target mode. 6076 */ 6077 if ((ahc->flags & AHC_TARGETROLE) != 0) 6078 simode1 |= ENSCSIRST; 6079 #endif 6080 ahc_outb(ahc, SIMODE1, simode1); 6081 if (initiate_reset) 6082 ahc_reset_current_bus(ahc); 6083 ahc_clear_intstat(ahc); 6084 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6085 restart_needed = TRUE; 6086 } 6087 6088 /* 6089 * Clean up all the state information for the 6090 * pending transactions on this bus. 6091 */ 6092 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6093 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6094 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6095 6096 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6097 6098 #ifdef AHC_TARGET_MODE 6099 /* 6100 * Send an immediate notify ccb to all target more peripheral 6101 * drivers affected by this action. 6102 */ 6103 for (target = 0; target <= max_scsiid; target++) { 6104 struct ahc_tmode_tstate* tstate; 6105 u_int lun; 6106 6107 tstate = ahc->enabled_targets[target]; 6108 if (tstate == NULL) 6109 continue; 6110 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6111 struct ahc_tmode_lstate* lstate; 6112 6113 lstate = tstate->enabled_luns[lun]; 6114 if (lstate == NULL) 6115 continue; 6116 6117 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6118 EVENT_TYPE_BUS_RESET, /*arg*/0); 6119 ahc_send_lstate_events(ahc, lstate); 6120 } 6121 } 6122 #endif 6123 /* Notify the XPT that a bus reset occurred */ 6124 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6125 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 6126 6127 /* 6128 * Revert to async/narrow transfers until we renegotiate. 6129 */ 6130 for (target = 0; target <= max_scsiid; target++) { 6131 6132 if (ahc->enabled_targets[target] == NULL) 6133 continue; 6134 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6135 struct ahc_devinfo devinfo; 6136 6137 ahc_compile_devinfo(&devinfo, target, initiator, 6138 CAM_LUN_WILDCARD, 6139 channel, ROLE_UNKNOWN); 6140 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6141 AHC_TRANS_CUR, /*paused*/TRUE); 6142 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6143 /*period*/0, /*offset*/0, 6144 /*ppr_options*/0, AHC_TRANS_CUR, 6145 /*paused*/TRUE); 6146 } 6147 } 6148 6149 if (restart_needed) 6150 ahc_restart(ahc); 6151 else 6152 ahc_unpause(ahc); 6153 return found; 6154 } 6155 6156 6157 /***************************** Residual Processing ****************************/ 6158 /* 6159 * Calculate the residual for a just completed SCB. 6160 */ 6161 void 6162 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6163 { 6164 struct hardware_scb *hscb; 6165 struct status_pkt *spkt; 6166 uint32_t sgptr; 6167 uint32_t resid_sgptr; 6168 uint32_t resid; 6169 6170 /* 6171 * 5 cases. 6172 * 1) No residual. 6173 * SG_RESID_VALID clear in sgptr. 6174 * 2) Transferless command 6175 * 3) Never performed any transfers. 6176 * sgptr has SG_FULL_RESID set. 6177 * 4) No residual but target did not 6178 * save data pointers after the 6179 * last transfer, so sgptr was 6180 * never updated. 6181 * 5) We have a partial residual. 6182 * Use residual_sgptr to determine 6183 * where we are. 6184 */ 6185 6186 hscb = scb->hscb; 6187 sgptr = aic_le32toh(hscb->sgptr); 6188 if ((sgptr & SG_RESID_VALID) == 0) 6189 /* Case 1 */ 6190 return; 6191 sgptr &= ~SG_RESID_VALID; 6192 6193 if ((sgptr & SG_LIST_NULL) != 0) 6194 /* Case 2 */ 6195 return; 6196 6197 spkt = &hscb->shared_data.status; 6198 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr); 6199 if ((sgptr & SG_FULL_RESID) != 0) { 6200 /* Case 3 */ 6201 resid = aic_get_transfer_length(scb); 6202 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6203 /* Case 4 */ 6204 return; 6205 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6206 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6207 } else { 6208 struct ahc_dma_seg *sg; 6209 6210 /* 6211 * Remainder of the SG where the transfer 6212 * stopped. 6213 */ 6214 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6215 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6216 6217 /* The residual sg_ptr always points to the next sg */ 6218 sg--; 6219 6220 /* 6221 * Add up the contents of all residual 6222 * SG segments that are after the SG where 6223 * the transfer stopped. 6224 */ 6225 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6226 sg++; 6227 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 6228 } 6229 } 6230 if ((scb->flags & SCB_SENSE) == 0) 6231 aic_set_residual(scb, resid); 6232 else 6233 aic_set_sense_residual(scb, resid); 6234 6235 #ifdef AHC_DEBUG 6236 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6237 ahc_print_path(ahc, scb); 6238 printf("Handled %sResidual of %d bytes\n", 6239 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6240 } 6241 #endif 6242 } 6243 6244 /******************************* Target Mode **********************************/ 6245 #ifdef AHC_TARGET_MODE 6246 /* 6247 * Add a target mode event to this lun's queue 6248 */ 6249 static void 6250 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6251 u_int initiator_id, u_int event_type, u_int event_arg) 6252 { 6253 struct ahc_tmode_event *event; 6254 int pending; 6255 6256 xpt_freeze_devq(lstate->path, /*count*/1); 6257 if (lstate->event_w_idx >= lstate->event_r_idx) 6258 pending = lstate->event_w_idx - lstate->event_r_idx; 6259 else 6260 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6261 - (lstate->event_r_idx - lstate->event_w_idx); 6262 6263 if (event_type == EVENT_TYPE_BUS_RESET 6264 || event_type == MSG_BUS_DEV_RESET) { 6265 /* 6266 * Any earlier events are irrelevant, so reset our buffer. 6267 * This has the effect of allowing us to deal with reset 6268 * floods (an external device holding down the reset line) 6269 * without losing the event that is really interesting. 6270 */ 6271 lstate->event_r_idx = 0; 6272 lstate->event_w_idx = 0; 6273 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6274 } 6275 6276 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6277 xpt_print_path(lstate->path); 6278 printf("immediate event %x:%x lost\n", 6279 lstate->event_buffer[lstate->event_r_idx].event_type, 6280 lstate->event_buffer[lstate->event_r_idx].event_arg); 6281 lstate->event_r_idx++; 6282 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6283 lstate->event_r_idx = 0; 6284 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6285 } 6286 6287 event = &lstate->event_buffer[lstate->event_w_idx]; 6288 event->initiator_id = initiator_id; 6289 event->event_type = event_type; 6290 event->event_arg = event_arg; 6291 lstate->event_w_idx++; 6292 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6293 lstate->event_w_idx = 0; 6294 } 6295 6296 /* 6297 * Send any target mode events queued up waiting 6298 * for immediate notify resources. 6299 */ 6300 void 6301 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6302 { 6303 struct ccb_hdr *ccbh; 6304 struct ccb_immed_notify *inot; 6305 6306 while (lstate->event_r_idx != lstate->event_w_idx 6307 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6308 struct ahc_tmode_event *event; 6309 6310 event = &lstate->event_buffer[lstate->event_r_idx]; 6311 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6312 inot = (struct ccb_immed_notify *)ccbh; 6313 switch (event->event_type) { 6314 case EVENT_TYPE_BUS_RESET: 6315 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6316 break; 6317 default: 6318 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6319 inot->message_args[0] = event->event_type; 6320 inot->message_args[1] = event->event_arg; 6321 break; 6322 } 6323 inot->initiator_id = event->initiator_id; 6324 inot->sense_len = 0; 6325 xpt_done((union ccb *)inot); 6326 lstate->event_r_idx++; 6327 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6328 lstate->event_r_idx = 0; 6329 } 6330 } 6331 #endif 6332 6333 /******************** Sequencer Program Patching/Download *********************/ 6334 6335 #ifdef AHC_DUMP_SEQ 6336 void 6337 ahc_dumpseq(struct ahc_softc* ahc) 6338 { 6339 int i; 6340 6341 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6342 ahc_outb(ahc, SEQADDR0, 0); 6343 ahc_outb(ahc, SEQADDR1, 0); 6344 for (i = 0; i < ahc->instruction_ram_size; i++) { 6345 uint8_t ins_bytes[4]; 6346 6347 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6348 printf("0x%08x\n", ins_bytes[0] << 24 6349 | ins_bytes[1] << 16 6350 | ins_bytes[2] << 8 6351 | ins_bytes[3]); 6352 } 6353 } 6354 #endif 6355 6356 static int 6357 ahc_loadseq(struct ahc_softc *ahc) 6358 { 6359 struct cs cs_table[num_critical_sections]; 6360 u_int begin_set[num_critical_sections]; 6361 u_int end_set[num_critical_sections]; 6362 struct patch *cur_patch; 6363 u_int cs_count; 6364 u_int cur_cs; 6365 u_int i; 6366 u_int skip_addr; 6367 u_int sg_prefetch_cnt; 6368 int downloaded; 6369 uint8_t download_consts[7]; 6370 6371 /* 6372 * Start out with 0 critical sections 6373 * that apply to this firmware load. 6374 */ 6375 cs_count = 0; 6376 cur_cs = 0; 6377 memset(begin_set, 0, sizeof(begin_set)); 6378 memset(end_set, 0, sizeof(end_set)); 6379 6380 /* Setup downloadable constant table */ 6381 download_consts[QOUTFIFO_OFFSET] = 0; 6382 if (ahc->targetcmds != NULL) 6383 download_consts[QOUTFIFO_OFFSET] += 32; 6384 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6385 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6386 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6387 sg_prefetch_cnt = ahc->pci_cachesize; 6388 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6389 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6390 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6391 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6392 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6393 6394 cur_patch = patches; 6395 downloaded = 0; 6396 skip_addr = 0; 6397 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6398 ahc_outb(ahc, SEQADDR0, 0); 6399 ahc_outb(ahc, SEQADDR1, 0); 6400 6401 for (i = 0; i < sizeof(seqprog)/4; i++) { 6402 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6403 /* 6404 * Don't download this instruction as it 6405 * is in a patch that was removed. 6406 */ 6407 continue; 6408 } 6409 6410 if (downloaded == ahc->instruction_ram_size) { 6411 /* 6412 * We're about to exceed the instruction 6413 * storage capacity for this chip. Fail 6414 * the load. 6415 */ 6416 printf("\n%s: Program too large for instruction memory " 6417 "size of %d!\n", ahc_name(ahc), 6418 ahc->instruction_ram_size); 6419 return (ENOMEM); 6420 } 6421 6422 /* 6423 * Move through the CS table until we find a CS 6424 * that might apply to this instruction. 6425 */ 6426 for (; cur_cs < num_critical_sections; cur_cs++) { 6427 if (critical_sections[cur_cs].end <= i) { 6428 if (begin_set[cs_count] == TRUE 6429 && end_set[cs_count] == FALSE) { 6430 cs_table[cs_count].end = downloaded; 6431 end_set[cs_count] = TRUE; 6432 cs_count++; 6433 } 6434 continue; 6435 } 6436 if (critical_sections[cur_cs].begin <= i 6437 && begin_set[cs_count] == FALSE) { 6438 cs_table[cs_count].begin = downloaded; 6439 begin_set[cs_count] = TRUE; 6440 } 6441 break; 6442 } 6443 ahc_download_instr(ahc, i, download_consts); 6444 downloaded++; 6445 } 6446 6447 ahc->num_critical_sections = cs_count; 6448 if (cs_count != 0) { 6449 6450 cs_count *= sizeof(struct cs); 6451 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6452 if (ahc->critical_sections == NULL) 6453 panic("ahc_loadseq: Could not malloc"); 6454 memcpy(ahc->critical_sections, cs_table, cs_count); 6455 } 6456 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6457 6458 if (bootverbose) { 6459 printf(" %d instructions downloaded\n", downloaded); 6460 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6461 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6462 } 6463 return (0); 6464 } 6465 6466 static int 6467 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6468 u_int start_instr, u_int *skip_addr) 6469 { 6470 struct patch *cur_patch; 6471 struct patch *last_patch; 6472 u_int num_patches; 6473 6474 num_patches = sizeof(patches)/sizeof(struct patch); 6475 last_patch = &patches[num_patches]; 6476 cur_patch = *start_patch; 6477 6478 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6479 6480 if (cur_patch->patch_func(ahc) == 0) { 6481 6482 /* Start rejecting code */ 6483 *skip_addr = start_instr + cur_patch->skip_instr; 6484 cur_patch += cur_patch->skip_patch; 6485 } else { 6486 /* Accepted this patch. Advance to the next 6487 * one and wait for our intruction pointer to 6488 * hit this point. 6489 */ 6490 cur_patch++; 6491 } 6492 } 6493 6494 *start_patch = cur_patch; 6495 if (start_instr < *skip_addr) 6496 /* Still skipping */ 6497 return (0); 6498 6499 return (1); 6500 } 6501 6502 static void 6503 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6504 { 6505 union ins_formats instr; 6506 struct ins_format1 *fmt1_ins; 6507 struct ins_format3 *fmt3_ins; 6508 u_int opcode; 6509 6510 /* 6511 * The firmware is always compiled into a little endian format. 6512 */ 6513 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6514 6515 fmt1_ins = &instr.format1; 6516 fmt3_ins = NULL; 6517 6518 /* Pull the opcode */ 6519 opcode = instr.format1.opcode; 6520 switch (opcode) { 6521 case AIC_OP_JMP: 6522 case AIC_OP_JC: 6523 case AIC_OP_JNC: 6524 case AIC_OP_CALL: 6525 case AIC_OP_JNE: 6526 case AIC_OP_JNZ: 6527 case AIC_OP_JE: 6528 case AIC_OP_JZ: 6529 { 6530 struct patch *cur_patch; 6531 int address_offset; 6532 u_int address; 6533 u_int skip_addr; 6534 u_int i; 6535 6536 fmt3_ins = &instr.format3; 6537 address_offset = 0; 6538 address = fmt3_ins->address; 6539 cur_patch = patches; 6540 skip_addr = 0; 6541 6542 for (i = 0; i < address;) { 6543 6544 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6545 6546 if (skip_addr > i) { 6547 int end_addr; 6548 6549 end_addr = MIN(address, skip_addr); 6550 address_offset += end_addr - i; 6551 i = skip_addr; 6552 } else { 6553 i++; 6554 } 6555 } 6556 address -= address_offset; 6557 fmt3_ins->address = address; 6558 /* FALLTHROUGH */ 6559 } 6560 case AIC_OP_OR: 6561 case AIC_OP_AND: 6562 case AIC_OP_XOR: 6563 case AIC_OP_ADD: 6564 case AIC_OP_ADC: 6565 case AIC_OP_BMOV: 6566 if (fmt1_ins->parity != 0) { 6567 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6568 } 6569 fmt1_ins->parity = 0; 6570 if ((ahc->features & AHC_CMD_CHAN) == 0 6571 && opcode == AIC_OP_BMOV) { 6572 /* 6573 * Block move was added at the same time 6574 * as the command channel. Verify that 6575 * this is only a move of a single element 6576 * and convert the BMOV to a MOV 6577 * (AND with an immediate of FF). 6578 */ 6579 if (fmt1_ins->immediate != 1) 6580 panic("%s: BMOV not supported\n", 6581 ahc_name(ahc)); 6582 fmt1_ins->opcode = AIC_OP_AND; 6583 fmt1_ins->immediate = 0xff; 6584 } 6585 /* FALLTHROUGH */ 6586 case AIC_OP_ROL: 6587 if ((ahc->features & AHC_ULTRA2) != 0) { 6588 int i, count; 6589 6590 /* Calculate odd parity for the instruction */ 6591 for (i = 0, count = 0; i < 31; i++) { 6592 uint32_t mask; 6593 6594 mask = 0x01 << i; 6595 if ((instr.integer & mask) != 0) 6596 count++; 6597 } 6598 if ((count & 0x01) == 0) 6599 instr.format1.parity = 1; 6600 } else { 6601 /* Compress the instruction for older sequencers */ 6602 if (fmt3_ins != NULL) { 6603 instr.integer = 6604 fmt3_ins->immediate 6605 | (fmt3_ins->source << 8) 6606 | (fmt3_ins->address << 16) 6607 | (fmt3_ins->opcode << 25); 6608 } else { 6609 instr.integer = 6610 fmt1_ins->immediate 6611 | (fmt1_ins->source << 8) 6612 | (fmt1_ins->destination << 16) 6613 | (fmt1_ins->ret << 24) 6614 | (fmt1_ins->opcode << 25); 6615 } 6616 } 6617 /* The sequencer is a little endian cpu */ 6618 instr.integer = aic_htole32(instr.integer); 6619 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6620 break; 6621 default: 6622 panic("Unknown opcode encountered in seq program"); 6623 break; 6624 } 6625 } 6626 6627 int 6628 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6629 const char *name, u_int address, u_int value, 6630 u_int *cur_column, u_int wrap_point) 6631 { 6632 int printed; 6633 u_int printed_mask; 6634 6635 if (cur_column != NULL && *cur_column >= wrap_point) { 6636 printf("\n"); 6637 *cur_column = 0; 6638 } 6639 printed = printf("%s[0x%x]", name, value); 6640 if (table == NULL) { 6641 printed += printf(" "); 6642 *cur_column += printed; 6643 return (printed); 6644 } 6645 printed_mask = 0; 6646 while (printed_mask != 0xFF) { 6647 int entry; 6648 6649 for (entry = 0; entry < num_entries; entry++) { 6650 if (((value & table[entry].mask) 6651 != table[entry].value) 6652 || ((printed_mask & table[entry].mask) 6653 == table[entry].mask)) 6654 continue; 6655 6656 printed += printf("%s%s", 6657 printed_mask == 0 ? ":(" : "|", 6658 table[entry].name); 6659 printed_mask |= table[entry].mask; 6660 6661 break; 6662 } 6663 if (entry >= num_entries) 6664 break; 6665 } 6666 if (printed_mask != 0) 6667 printed += printf(") "); 6668 else 6669 printed += printf(" "); 6670 if (cur_column != NULL) 6671 *cur_column += printed; 6672 return (printed); 6673 } 6674 6675 void 6676 ahc_dump_card_state(struct ahc_softc *ahc) 6677 { 6678 struct scb *scb; 6679 struct scb_tailq *untagged_q; 6680 u_int cur_col; 6681 int paused; 6682 int target; 6683 int maxtarget; 6684 int i; 6685 uint8_t last_phase; 6686 uint8_t qinpos; 6687 uint8_t qintail; 6688 uint8_t qoutpos; 6689 uint8_t scb_index; 6690 uint8_t saved_scbptr; 6691 6692 if (ahc_is_paused(ahc)) { 6693 paused = 1; 6694 } else { 6695 paused = 0; 6696 ahc_pause(ahc); 6697 } 6698 6699 saved_scbptr = ahc_inb(ahc, SCBPTR); 6700 last_phase = ahc_inb(ahc, LASTPHASE); 6701 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6702 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6703 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6704 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6705 if (paused) 6706 printf("Card was paused\n"); 6707 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6708 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6709 ahc_inb(ahc, ARG_2)); 6710 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6711 ahc_inb(ahc, SCBPTR)); 6712 cur_col = 0; 6713 if ((ahc->features & AHC_DT) != 0) 6714 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6715 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6716 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6717 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6718 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6719 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6720 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6721 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6722 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6723 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6724 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6725 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6726 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6727 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6728 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6729 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6730 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6731 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6732 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6733 if (cur_col != 0) 6734 printf("\n"); 6735 printf("STACK:"); 6736 for (i = 0; i < STACK_SIZE; i++) 6737 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6738 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6739 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6740 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6741 /* QINFIFO */ 6742 printf("QINFIFO entries: "); 6743 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6744 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6745 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6746 } else 6747 qinpos = ahc_inb(ahc, QINPOS); 6748 qintail = ahc->qinfifonext; 6749 while (qinpos != qintail) { 6750 printf("%d ", ahc->qinfifo[qinpos]); 6751 qinpos++; 6752 } 6753 printf("\n"); 6754 6755 printf("Waiting Queue entries: "); 6756 scb_index = ahc_inb(ahc, WAITING_SCBH); 6757 i = 0; 6758 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6759 ahc_outb(ahc, SCBPTR, scb_index); 6760 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6761 scb_index = ahc_inb(ahc, SCB_NEXT); 6762 } 6763 printf("\n"); 6764 6765 printf("Disconnected Queue entries: "); 6766 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6767 i = 0; 6768 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6769 ahc_outb(ahc, SCBPTR, scb_index); 6770 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6771 scb_index = ahc_inb(ahc, SCB_NEXT); 6772 } 6773 printf("\n"); 6774 6775 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6776 printf("QOUTFIFO entries: "); 6777 qoutpos = ahc->qoutfifonext; 6778 i = 0; 6779 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6780 printf("%d ", ahc->qoutfifo[qoutpos]); 6781 qoutpos++; 6782 } 6783 printf("\n"); 6784 6785 printf("Sequencer Free SCB List: "); 6786 scb_index = ahc_inb(ahc, FREE_SCBH); 6787 i = 0; 6788 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6789 ahc_outb(ahc, SCBPTR, scb_index); 6790 printf("%d ", scb_index); 6791 scb_index = ahc_inb(ahc, SCB_NEXT); 6792 } 6793 printf("\n"); 6794 6795 printf("Sequencer SCB Info: "); 6796 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6797 ahc_outb(ahc, SCBPTR, i); 6798 cur_col = printf("\n%3d ", i); 6799 6800 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6801 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6802 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6803 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6804 } 6805 printf("\n"); 6806 6807 printf("Pending list: "); 6808 i = 0; 6809 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6810 if (i++ > 256) 6811 break; 6812 cur_col = printf("\n%3d ", scb->hscb->tag); 6813 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6814 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6815 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6816 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6817 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6818 printf("("); 6819 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6820 &cur_col, 60); 6821 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6822 printf(")"); 6823 } 6824 } 6825 printf("\n"); 6826 6827 printf("Kernel Free SCB list: "); 6828 i = 0; 6829 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6830 if (i++ > 256) 6831 break; 6832 printf("%d ", scb->hscb->tag); 6833 } 6834 printf("\n"); 6835 6836 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6837 for (target = 0; target <= maxtarget; target++) { 6838 untagged_q = &ahc->untagged_queues[target]; 6839 if (TAILQ_FIRST(untagged_q) == NULL) 6840 continue; 6841 printf("Untagged Q(%d): ", target); 6842 i = 0; 6843 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6844 if (i++ > 256) 6845 break; 6846 printf("%d ", scb->hscb->tag); 6847 } 6848 printf("\n"); 6849 } 6850 6851 ahc_platform_dump_card_state(ahc); 6852 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6853 ahc_outb(ahc, SCBPTR, saved_scbptr); 6854 if (paused == 0) 6855 ahc_unpause(ahc); 6856 } 6857 6858 /*************************** Timeout Handling *********************************/ 6859 void 6860 ahc_timeout(struct scb *scb) 6861 { 6862 struct ahc_softc *ahc; 6863 6864 ahc = scb->ahc_softc; 6865 if ((scb->flags & SCB_ACTIVE) != 0) { 6866 if ((scb->flags & SCB_TIMEDOUT) == 0) { 6867 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb, 6868 timedout_links); 6869 scb->flags |= SCB_TIMEDOUT; 6870 } 6871 ahc_wakeup_recovery_thread(ahc); 6872 } 6873 } 6874 6875 /* 6876 * Re-schedule a timeout for the passed in SCB if we determine that some 6877 * other SCB is in the process of recovery or an SCB with a longer 6878 * timeout is still pending. Limit our search to just "other_scb" 6879 * if it is non-NULL. 6880 */ 6881 static int 6882 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb, 6883 struct scb *other_scb) 6884 { 6885 u_int newtimeout; 6886 int found; 6887 6888 ahc_print_path(ahc, scb); 6889 printf("Other SCB Timeout%s", 6890 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 6891 ? " again\n" : "\n"); 6892 6893 newtimeout = aic_get_timeout(scb); 6894 scb->flags |= SCB_OTHERTCL_TIMEOUT; 6895 found = 0; 6896 if (other_scb != NULL) { 6897 if ((other_scb->flags 6898 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 6899 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 6900 found++; 6901 newtimeout = MAX(aic_get_timeout(other_scb), 6902 newtimeout); 6903 } 6904 } else { 6905 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) { 6906 if ((other_scb->flags 6907 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 6908 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 6909 found++; 6910 newtimeout = 6911 MAX(aic_get_timeout(other_scb), 6912 newtimeout); 6913 } 6914 } 6915 } 6916 6917 if (found != 0) 6918 aic_scb_timer_reset(scb, newtimeout); 6919 else { 6920 ahc_print_path(ahc, scb); 6921 printf("No other SCB worth waiting for...\n"); 6922 } 6923 6924 return (found != 0); 6925 } 6926 6927 /* 6928 * ahc_recover_commands determines if any of the commands that have currently 6929 * timedout are the root cause for this timeout. Innocent commands are given 6930 * a new timeout while we wait for the command executing on the bus to timeout. 6931 * This routine is invoked from a thread context so we are allowed to sleep. 6932 * Our lock is not held on entry. 6933 */ 6934 void 6935 ahc_recover_commands(struct ahc_softc *ahc) 6936 { 6937 struct scb *scb; 6938 long s; 6939 int found; 6940 int restart_needed; 6941 u_int last_phase; 6942 6943 ahc_lock(ahc, &s); 6944 6945 /* 6946 * Pause the controller and manually flush any 6947 * commands that have just completed but that our 6948 * interrupt handler has yet to see. 6949 */ 6950 ahc_pause_and_flushwork(ahc); 6951 6952 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) { 6953 /* 6954 * The timedout commands have already 6955 * completed. This typically means 6956 * that either the timeout value was on 6957 * the hairy edge of what the device 6958 * requires or - more likely - interrupts 6959 * are not happening. 6960 */ 6961 printf("%s: Timedout SCBs already complete. " 6962 "Interrupts may not be functioning.\n", ahc_name(ahc)); 6963 ahc_unpause(ahc); 6964 ahc_unlock(ahc, &s); 6965 return; 6966 } 6967 6968 restart_needed = 0; 6969 printf("%s: Recovery Initiated\n", ahc_name(ahc)); 6970 ahc_dump_card_state(ahc); 6971 6972 last_phase = ahc_inb(ahc, LASTPHASE); 6973 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) { 6974 u_int active_scb_index; 6975 u_int saved_scbptr; 6976 int target; 6977 int lun; 6978 int i; 6979 char channel; 6980 6981 target = SCB_GET_TARGET(ahc, scb); 6982 channel = SCB_GET_CHANNEL(ahc, scb); 6983 lun = SCB_GET_LUN(scb); 6984 6985 ahc_print_path(ahc, scb); 6986 printf("SCB 0x%x - timed out\n", scb->hscb->tag); 6987 if (scb->sg_count > 0) { 6988 for (i = 0; i < scb->sg_count; i++) { 6989 printf("sg[%d] - Addr 0x%x : Length %d\n", 6990 i, 6991 scb->sg_list[i].addr, 6992 scb->sg_list[i].len & AHC_SG_LEN_MASK); 6993 } 6994 } 6995 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 6996 /* 6997 * Been down this road before. 6998 * Do a full bus reset. 6999 */ 7000 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT); 7001 bus_reset: 7002 found = ahc_reset_channel(ahc, channel, 7003 /*Initiate Reset*/TRUE); 7004 printf("%s: Issued Channel %c Bus Reset. " 7005 "%d SCBs aborted\n", ahc_name(ahc), channel, 7006 found); 7007 continue; 7008 } 7009 7010 /* 7011 * Remove the command from the timedout list in 7012 * preparation for requeing it. 7013 */ 7014 LIST_REMOVE(scb, timedout_links); 7015 scb->flags &= ~SCB_TIMEDOUT; 7016 7017 /* 7018 * If we are a target, transition to bus free and report 7019 * the timeout. 7020 * 7021 * The target/initiator that is holding up the bus may not 7022 * be the same as the one that triggered this timeout 7023 * (different commands have different timeout lengths). 7024 * If the bus is idle and we are actiing as the initiator 7025 * for this request, queue a BDR message to the timed out 7026 * target. Otherwise, if the timed out transaction is 7027 * active: 7028 * Initiator transaction: 7029 * Stuff the message buffer with a BDR message and assert 7030 * ATN in the hopes that the target will let go of the bus 7031 * and go to the mesgout phase. If this fails, we'll 7032 * get another timeout 2 seconds later which will attempt 7033 * a bus reset. 7034 * 7035 * Target transaction: 7036 * Transition to BUS FREE and report the error. 7037 * It's good to be the target! 7038 */ 7039 saved_scbptr = ahc_inb(ahc, SCBPTR); 7040 active_scb_index = ahc_inb(ahc, SCB_TAG); 7041 7042 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0 7043 && (active_scb_index < ahc->scb_data->numscbs)) { 7044 struct scb *active_scb; 7045 7046 /* 7047 * If the active SCB is not us, assume that 7048 * the active SCB has a longer timeout than 7049 * the timedout SCB, and wait for the active 7050 * SCB to timeout. 7051 */ 7052 active_scb = ahc_lookup_scb(ahc, active_scb_index); 7053 if (active_scb != scb) { 7054 if (ahc_other_scb_timeout(ahc, scb, 7055 active_scb) != 0) 7056 goto bus_reset; 7057 continue; 7058 } 7059 7060 /* It's us */ 7061 if ((scb->flags & SCB_TARGET_SCB) != 0) { 7062 7063 /* 7064 * Send back any queued up transactions 7065 * and properly record the error condition. 7066 */ 7067 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb), 7068 SCB_GET_CHANNEL(ahc, scb), 7069 SCB_GET_LUN(scb), 7070 scb->hscb->tag, 7071 ROLE_TARGET, 7072 CAM_CMD_TIMEOUT); 7073 7074 /* Will clear us from the bus */ 7075 restart_needed = 1; 7076 break; 7077 } 7078 7079 ahc_set_recoveryscb(ahc, active_scb); 7080 ahc_outb(ahc, MSG_OUT, HOST_MSG); 7081 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 7082 ahc_print_path(ahc, active_scb); 7083 printf("BDR message in message buffer\n"); 7084 active_scb->flags |= SCB_DEVICE_RESET; 7085 aic_scb_timer_reset(scb, 2 * 1000000); 7086 } else if (last_phase != P_BUSFREE 7087 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) { 7088 /* 7089 * SCB is not identified, there 7090 * is no pending REQ, and the sequencer 7091 * has not seen a busfree. Looks like 7092 * a stuck connection waiting to 7093 * go busfree. Reset the bus. 7094 */ 7095 printf("%s: Connection stuck awaiting busfree or " 7096 "Identify Msg.\n", ahc_name(ahc)); 7097 goto bus_reset; 7098 } else { 7099 int disconnected; 7100 7101 if (last_phase != P_BUSFREE 7102 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 7103 /* Hung target selection. Goto busfree */ 7104 printf("%s: Hung target selection\n", 7105 ahc_name(ahc)); 7106 restart_needed = 1; 7107 break; 7108 } 7109 7110 /* XXX Shouldn't panic. Just punt instead? */ 7111 if ((scb->flags & SCB_TARGET_SCB) != 0) 7112 panic("Timed-out target SCB but bus idle"); 7113 7114 if (ahc_search_qinfifo(ahc, target, channel, lun, 7115 scb->hscb->tag, ROLE_INITIATOR, 7116 /*status*/0, SEARCH_COUNT) > 0) { 7117 disconnected = FALSE; 7118 } else { 7119 disconnected = TRUE; 7120 } 7121 7122 if (disconnected) { 7123 7124 ahc_set_recoveryscb(ahc, scb); 7125 /* 7126 * Actually re-queue this SCB in an attempt 7127 * to select the device before it reconnects. 7128 * In either case (selection or reselection), 7129 * we will now issue a target reset to the 7130 * timed-out device. 7131 * 7132 * Set the MK_MESSAGE control bit indicating 7133 * that we desire to send a message. We 7134 * also set the disconnected flag since 7135 * in the paging case there is no guarantee 7136 * that our SCB control byte matches the 7137 * version on the card. We don't want the 7138 * sequencer to abort the command thinking 7139 * an unsolicited reselection occurred. 7140 */ 7141 scb->hscb->control |= MK_MESSAGE|DISCONNECTED; 7142 scb->flags |= SCB_DEVICE_RESET; 7143 7144 /* 7145 * Remove any cached copy of this SCB in the 7146 * disconnected list in preparation for the 7147 * queuing of our abort SCB. We use the 7148 * same element in the SCB, SCB_NEXT, for 7149 * both the qinfifo and the disconnected list. 7150 */ 7151 ahc_search_disc_list(ahc, target, channel, 7152 lun, scb->hscb->tag, 7153 /*stop_on_first*/TRUE, 7154 /*remove*/TRUE, 7155 /*save_state*/FALSE); 7156 7157 /* 7158 * In the non-paging case, the sequencer will 7159 * never re-reference the in-core SCB. 7160 * To make sure we are notified during 7161 * reslection, set the MK_MESSAGE flag in 7162 * the card's copy of the SCB. 7163 */ 7164 if ((ahc->flags & AHC_PAGESCBS) == 0) { 7165 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 7166 ahc_outb(ahc, SCB_CONTROL, 7167 ahc_inb(ahc, SCB_CONTROL) 7168 | MK_MESSAGE); 7169 } 7170 7171 /* 7172 * Clear out any entries in the QINFIFO first 7173 * so we are the next SCB for this target 7174 * to run. 7175 */ 7176 ahc_search_qinfifo(ahc, 7177 SCB_GET_TARGET(ahc, scb), 7178 channel, SCB_GET_LUN(scb), 7179 SCB_LIST_NULL, 7180 ROLE_INITIATOR, 7181 CAM_REQUEUE_REQ, 7182 SEARCH_COMPLETE); 7183 ahc_print_path(ahc, scb); 7184 printf("Queuing a BDR SCB\n"); 7185 ahc_qinfifo_requeue_tail(ahc, scb); 7186 ahc_outb(ahc, SCBPTR, saved_scbptr); 7187 aic_scb_timer_reset(scb, 2 * 1000000); 7188 } else { 7189 /* Go "immediatly" to the bus reset */ 7190 /* This shouldn't happen */ 7191 ahc_set_recoveryscb(ahc, scb); 7192 ahc_print_path(ahc, scb); 7193 printf("SCB %d: Immediate reset. " 7194 "Flags = 0x%x\n", scb->hscb->tag, 7195 scb->flags); 7196 goto bus_reset; 7197 } 7198 } 7199 break; 7200 } 7201 7202 /* 7203 * Any remaining SCBs were not the "culprit", so remove 7204 * them from the timeout list. The timer for these commands 7205 * will be reset once the recovery SCB completes. 7206 */ 7207 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) { 7208 7209 LIST_REMOVE(scb, timedout_links); 7210 scb->flags &= ~SCB_TIMEDOUT; 7211 } 7212 7213 if (restart_needed) 7214 ahc_restart(ahc); 7215 else 7216 ahc_unpause(ahc); 7217 ahc_unlock(ahc, &s); 7218 } 7219 7220 /************************* Target Mode ****************************************/ 7221 #ifdef AHC_TARGET_MODE 7222 cam_status 7223 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 7224 struct ahc_tmode_tstate **tstate, 7225 struct ahc_tmode_lstate **lstate, 7226 int notfound_failure) 7227 { 7228 7229 if ((ahc->features & AHC_TARGETMODE) == 0) 7230 return (CAM_REQ_INVALID); 7231 7232 /* 7233 * Handle the 'black hole' device that sucks up 7234 * requests to unattached luns on enabled targets. 7235 */ 7236 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 7237 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 7238 *tstate = NULL; 7239 *lstate = ahc->black_hole; 7240 } else { 7241 u_int max_id; 7242 7243 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 7244 if (ccb->ccb_h.target_id > max_id) 7245 return (CAM_TID_INVALID); 7246 7247 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 7248 return (CAM_LUN_INVALID); 7249 7250 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 7251 *lstate = NULL; 7252 if (*tstate != NULL) 7253 *lstate = 7254 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 7255 } 7256 7257 if (notfound_failure != 0 && *lstate == NULL) 7258 return (CAM_PATH_INVALID); 7259 7260 return (CAM_REQ_CMP); 7261 } 7262 7263 void 7264 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 7265 { 7266 struct ahc_tmode_tstate *tstate; 7267 struct ahc_tmode_lstate *lstate; 7268 struct ccb_en_lun *cel; 7269 cam_status status; 7270 u_long s; 7271 u_int target; 7272 u_int lun; 7273 u_int target_mask; 7274 u_int our_id; 7275 int error; 7276 char channel; 7277 7278 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 7279 /*notfound_failure*/FALSE); 7280 7281 if (status != CAM_REQ_CMP) { 7282 ccb->ccb_h.status = status; 7283 return; 7284 } 7285 7286 if (cam_sim_bus(sim) == 0) 7287 our_id = ahc->our_id; 7288 else 7289 our_id = ahc->our_id_b; 7290 7291 if (ccb->ccb_h.target_id != our_id) { 7292 /* 7293 * our_id represents our initiator ID, or 7294 * the ID of the first target to have an 7295 * enabled lun in target mode. There are 7296 * two cases that may preclude enabling a 7297 * target id other than our_id. 7298 * 7299 * o our_id is for an active initiator role. 7300 * Since the hardware does not support 7301 * reselections to the initiator role at 7302 * anything other than our_id, and our_id 7303 * is used by the hardware to indicate the 7304 * ID to use for both select-out and 7305 * reselect-out operations, the only target 7306 * ID we can support in this mode is our_id. 7307 * 7308 * o The MULTARGID feature is not available and 7309 * a previous target mode ID has been enabled. 7310 */ 7311 if ((ahc->features & AHC_MULTIROLE) != 0) { 7312 7313 if ((ahc->features & AHC_MULTI_TID) != 0 7314 && (ahc->flags & AHC_INITIATORROLE) != 0) { 7315 /* 7316 * Only allow additional targets if 7317 * the initiator role is disabled. 7318 * The hardware cannot handle a re-select-in 7319 * on the initiator id during a re-select-out 7320 * on a different target id. 7321 */ 7322 status = CAM_TID_INVALID; 7323 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 7324 || ahc->enabled_luns > 0) { 7325 /* 7326 * Only allow our target id to change 7327 * if the initiator role is not configured 7328 * and there are no enabled luns which 7329 * are attached to the currently registered 7330 * scsi id. 7331 */ 7332 status = CAM_TID_INVALID; 7333 } 7334 } else if ((ahc->features & AHC_MULTI_TID) == 0 7335 && ahc->enabled_luns > 0) { 7336 7337 status = CAM_TID_INVALID; 7338 } 7339 } 7340 7341 if (status != CAM_REQ_CMP) { 7342 ccb->ccb_h.status = status; 7343 return; 7344 } 7345 7346 /* 7347 * We now have an id that is valid. 7348 * If we aren't in target mode, switch modes. 7349 */ 7350 if ((ahc->flags & AHC_TARGETROLE) == 0 7351 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 7352 u_long s; 7353 ahc_flag saved_flags; 7354 7355 printf("Configuring Target Mode\n"); 7356 ahc_lock(ahc, &s); 7357 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 7358 ccb->ccb_h.status = CAM_BUSY; 7359 ahc_unlock(ahc, &s); 7360 return; 7361 } 7362 saved_flags = ahc->flags; 7363 ahc->flags |= AHC_TARGETROLE; 7364 if ((ahc->features & AHC_MULTIROLE) == 0) 7365 ahc->flags &= ~AHC_INITIATORROLE; 7366 ahc_pause(ahc); 7367 error = ahc_loadseq(ahc); 7368 if (error != 0) { 7369 /* 7370 * Restore original configuration and notify 7371 * the caller that we cannot support target mode. 7372 * Since the adapter started out in this 7373 * configuration, the firmware load will succeed, 7374 * so there is no point in checking ahc_loadseq's 7375 * return value. 7376 */ 7377 ahc->flags = saved_flags; 7378 (void)ahc_loadseq(ahc); 7379 ahc_restart(ahc); 7380 ahc_unlock(ahc, &s); 7381 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 7382 return; 7383 } 7384 ahc_restart(ahc); 7385 ahc_unlock(ahc, &s); 7386 } 7387 cel = &ccb->cel; 7388 target = ccb->ccb_h.target_id; 7389 lun = ccb->ccb_h.target_lun; 7390 channel = SIM_CHANNEL(ahc, sim); 7391 target_mask = 0x01 << target; 7392 if (channel == 'B') 7393 target_mask <<= 8; 7394 7395 if (cel->enable != 0) { 7396 u_int scsiseq; 7397 7398 /* Are we already enabled?? */ 7399 if (lstate != NULL) { 7400 xpt_print_path(ccb->ccb_h.path); 7401 printf("Lun already enabled\n"); 7402 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 7403 return; 7404 } 7405 7406 if (cel->grp6_len != 0 7407 || cel->grp7_len != 0) { 7408 /* 7409 * Don't (yet?) support vendor 7410 * specific commands. 7411 */ 7412 ccb->ccb_h.status = CAM_REQ_INVALID; 7413 printf("Non-zero Group Codes\n"); 7414 return; 7415 } 7416 7417 /* 7418 * Seems to be okay. 7419 * Setup our data structures. 7420 */ 7421 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 7422 tstate = ahc_alloc_tstate(ahc, target, channel); 7423 if (tstate == NULL) { 7424 xpt_print_path(ccb->ccb_h.path); 7425 printf("Couldn't allocate tstate\n"); 7426 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7427 return; 7428 } 7429 } 7430 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 7431 if (lstate == NULL) { 7432 xpt_print_path(ccb->ccb_h.path); 7433 printf("Couldn't allocate lstate\n"); 7434 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7435 return; 7436 } 7437 memset(lstate, 0, sizeof(*lstate)); 7438 status = xpt_create_path(&lstate->path, /*periph*/NULL, 7439 xpt_path_path_id(ccb->ccb_h.path), 7440 xpt_path_target_id(ccb->ccb_h.path), 7441 xpt_path_lun_id(ccb->ccb_h.path)); 7442 if (status != CAM_REQ_CMP) { 7443 free(lstate, M_DEVBUF); 7444 xpt_print_path(ccb->ccb_h.path); 7445 printf("Couldn't allocate path\n"); 7446 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7447 return; 7448 } 7449 SLIST_INIT(&lstate->accept_tios); 7450 SLIST_INIT(&lstate->immed_notifies); 7451 ahc_lock(ahc, &s); 7452 ahc_pause(ahc); 7453 if (target != CAM_TARGET_WILDCARD) { 7454 tstate->enabled_luns[lun] = lstate; 7455 ahc->enabled_luns++; 7456 7457 if ((ahc->features & AHC_MULTI_TID) != 0) { 7458 u_int targid_mask; 7459 7460 targid_mask = ahc_inb(ahc, TARGID) 7461 | (ahc_inb(ahc, TARGID + 1) << 8); 7462 7463 targid_mask |= target_mask; 7464 ahc_outb(ahc, TARGID, targid_mask); 7465 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7466 7467 ahc_update_scsiid(ahc, targid_mask); 7468 } else { 7469 u_int our_id; 7470 char channel; 7471 7472 channel = SIM_CHANNEL(ahc, sim); 7473 our_id = SIM_SCSI_ID(ahc, sim); 7474 7475 /* 7476 * This can only happen if selections 7477 * are not enabled 7478 */ 7479 if (target != our_id) { 7480 u_int sblkctl; 7481 char cur_channel; 7482 int swap; 7483 7484 sblkctl = ahc_inb(ahc, SBLKCTL); 7485 cur_channel = (sblkctl & SELBUSB) 7486 ? 'B' : 'A'; 7487 if ((ahc->features & AHC_TWIN) == 0) 7488 cur_channel = 'A'; 7489 swap = cur_channel != channel; 7490 if (channel == 'A') 7491 ahc->our_id = target; 7492 else 7493 ahc->our_id_b = target; 7494 7495 if (swap) 7496 ahc_outb(ahc, SBLKCTL, 7497 sblkctl ^ SELBUSB); 7498 7499 ahc_outb(ahc, SCSIID, target); 7500 7501 if (swap) 7502 ahc_outb(ahc, SBLKCTL, sblkctl); 7503 } 7504 } 7505 } else 7506 ahc->black_hole = lstate; 7507 /* Allow select-in operations */ 7508 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7509 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7510 scsiseq |= ENSELI; 7511 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7512 scsiseq = ahc_inb(ahc, SCSISEQ); 7513 scsiseq |= ENSELI; 7514 ahc_outb(ahc, SCSISEQ, scsiseq); 7515 } 7516 ahc_unpause(ahc); 7517 ahc_unlock(ahc, &s); 7518 ccb->ccb_h.status = CAM_REQ_CMP; 7519 xpt_print_path(ccb->ccb_h.path); 7520 printf("Lun now enabled for target mode\n"); 7521 } else { 7522 struct scb *scb; 7523 int i, empty; 7524 7525 if (lstate == NULL) { 7526 ccb->ccb_h.status = CAM_LUN_INVALID; 7527 return; 7528 } 7529 7530 ahc_lock(ahc, &s); 7531 7532 ccb->ccb_h.status = CAM_REQ_CMP; 7533 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7534 struct ccb_hdr *ccbh; 7535 7536 ccbh = &scb->io_ctx->ccb_h; 7537 if (ccbh->func_code == XPT_CONT_TARGET_IO 7538 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7539 printf("CTIO pending\n"); 7540 ccb->ccb_h.status = CAM_REQ_INVALID; 7541 ahc_unlock(ahc, &s); 7542 return; 7543 } 7544 } 7545 7546 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7547 printf("ATIOs pending\n"); 7548 ccb->ccb_h.status = CAM_REQ_INVALID; 7549 } 7550 7551 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7552 printf("INOTs pending\n"); 7553 ccb->ccb_h.status = CAM_REQ_INVALID; 7554 } 7555 7556 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7557 ahc_unlock(ahc, &s); 7558 return; 7559 } 7560 7561 xpt_print_path(ccb->ccb_h.path); 7562 printf("Target mode disabled\n"); 7563 xpt_free_path(lstate->path); 7564 free(lstate, M_DEVBUF); 7565 7566 ahc_pause(ahc); 7567 /* Can we clean up the target too? */ 7568 if (target != CAM_TARGET_WILDCARD) { 7569 tstate->enabled_luns[lun] = NULL; 7570 ahc->enabled_luns--; 7571 for (empty = 1, i = 0; i < 8; i++) 7572 if (tstate->enabled_luns[i] != NULL) { 7573 empty = 0; 7574 break; 7575 } 7576 7577 if (empty) { 7578 ahc_free_tstate(ahc, target, channel, 7579 /*force*/FALSE); 7580 if (ahc->features & AHC_MULTI_TID) { 7581 u_int targid_mask; 7582 7583 targid_mask = ahc_inb(ahc, TARGID) 7584 | (ahc_inb(ahc, TARGID + 1) 7585 << 8); 7586 7587 targid_mask &= ~target_mask; 7588 ahc_outb(ahc, TARGID, targid_mask); 7589 ahc_outb(ahc, TARGID+1, 7590 (targid_mask >> 8)); 7591 ahc_update_scsiid(ahc, targid_mask); 7592 } 7593 } 7594 } else { 7595 7596 ahc->black_hole = NULL; 7597 7598 /* 7599 * We can't allow selections without 7600 * our black hole device. 7601 */ 7602 empty = TRUE; 7603 } 7604 if (ahc->enabled_luns == 0) { 7605 /* Disallow select-in */ 7606 u_int scsiseq; 7607 7608 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7609 scsiseq &= ~ENSELI; 7610 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7611 scsiseq = ahc_inb(ahc, SCSISEQ); 7612 scsiseq &= ~ENSELI; 7613 ahc_outb(ahc, SCSISEQ, scsiseq); 7614 7615 if ((ahc->features & AHC_MULTIROLE) == 0) { 7616 printf("Configuring Initiator Mode\n"); 7617 ahc->flags &= ~AHC_TARGETROLE; 7618 ahc->flags |= AHC_INITIATORROLE; 7619 /* 7620 * Returning to a configuration that 7621 * fit previously will always succeed. 7622 */ 7623 (void)ahc_loadseq(ahc); 7624 ahc_restart(ahc); 7625 /* 7626 * Unpaused. The extra unpause 7627 * that follows is harmless. 7628 */ 7629 } 7630 } 7631 ahc_unpause(ahc); 7632 ahc_unlock(ahc, &s); 7633 } 7634 } 7635 7636 static void 7637 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7638 { 7639 u_int scsiid_mask; 7640 u_int scsiid; 7641 7642 if ((ahc->features & AHC_MULTI_TID) == 0) 7643 panic("ahc_update_scsiid called on non-multitid unit\n"); 7644 7645 /* 7646 * Since we will rely on the TARGID mask 7647 * for selection enables, ensure that OID 7648 * in SCSIID is not set to some other ID 7649 * that we don't want to allow selections on. 7650 */ 7651 if ((ahc->features & AHC_ULTRA2) != 0) 7652 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7653 else 7654 scsiid = ahc_inb(ahc, SCSIID); 7655 scsiid_mask = 0x1 << (scsiid & OID); 7656 if ((targid_mask & scsiid_mask) == 0) { 7657 u_int our_id; 7658 7659 /* ffs counts from 1 */ 7660 our_id = ffs(targid_mask); 7661 if (our_id == 0) 7662 our_id = ahc->our_id; 7663 else 7664 our_id--; 7665 scsiid &= TID; 7666 scsiid |= our_id; 7667 } 7668 if ((ahc->features & AHC_ULTRA2) != 0) 7669 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7670 else 7671 ahc_outb(ahc, SCSIID, scsiid); 7672 } 7673 7674 void 7675 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7676 { 7677 struct target_cmd *cmd; 7678 7679 /* 7680 * If the card supports auto-access pause, 7681 * we can access the card directly regardless 7682 * of whether it is paused or not. 7683 */ 7684 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7685 paused = TRUE; 7686 7687 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7688 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7689 7690 /* 7691 * Only advance through the queue if we 7692 * have the resources to process the command. 7693 */ 7694 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7695 break; 7696 7697 cmd->cmd_valid = 0; 7698 aic_dmamap_sync(ahc, ahc->shared_data_dmat, 7699 ahc->shared_data_dmamap, 7700 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7701 sizeof(struct target_cmd), 7702 BUS_DMASYNC_PREREAD); 7703 ahc->tqinfifonext++; 7704 7705 /* 7706 * Lazily update our position in the target mode incoming 7707 * command queue as seen by the sequencer. 7708 */ 7709 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7710 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7711 u_int hs_mailbox; 7712 7713 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7714 hs_mailbox &= ~HOST_TQINPOS; 7715 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7716 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7717 } else { 7718 if (!paused) 7719 ahc_pause(ahc); 7720 ahc_outb(ahc, KERNEL_TQINPOS, 7721 ahc->tqinfifonext & HOST_TQINPOS); 7722 if (!paused) 7723 ahc_unpause(ahc); 7724 } 7725 } 7726 } 7727 } 7728 7729 static int 7730 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7731 { 7732 struct ahc_tmode_tstate *tstate; 7733 struct ahc_tmode_lstate *lstate; 7734 struct ccb_accept_tio *atio; 7735 uint8_t *byte; 7736 int initiator; 7737 int target; 7738 int lun; 7739 7740 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7741 target = SCSIID_OUR_ID(cmd->scsiid); 7742 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7743 7744 byte = cmd->bytes; 7745 tstate = ahc->enabled_targets[target]; 7746 lstate = NULL; 7747 if (tstate != NULL) 7748 lstate = tstate->enabled_luns[lun]; 7749 7750 /* 7751 * Commands for disabled luns go to the black hole driver. 7752 */ 7753 if (lstate == NULL) 7754 lstate = ahc->black_hole; 7755 7756 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7757 if (atio == NULL) { 7758 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7759 /* 7760 * Wait for more ATIOs from the peripheral driver for this lun. 7761 */ 7762 if (bootverbose) 7763 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7764 return (1); 7765 } else 7766 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7767 #if 0 7768 printf("Incoming command from %d for %d:%d%s\n", 7769 initiator, target, lun, 7770 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7771 #endif 7772 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7773 7774 if (lstate == ahc->black_hole) { 7775 /* Fill in the wildcards */ 7776 atio->ccb_h.target_id = target; 7777 atio->ccb_h.target_lun = lun; 7778 } 7779 7780 /* 7781 * Package it up and send it off to 7782 * whomever has this lun enabled. 7783 */ 7784 atio->sense_len = 0; 7785 atio->init_id = initiator; 7786 if (byte[0] != 0xFF) { 7787 /* Tag was included */ 7788 atio->tag_action = *byte++; 7789 atio->tag_id = *byte++; 7790 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7791 } else { 7792 atio->ccb_h.flags = 0; 7793 } 7794 byte++; 7795 7796 /* Okay. Now determine the cdb size based on the command code */ 7797 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7798 case 0: 7799 atio->cdb_len = 6; 7800 break; 7801 case 1: 7802 case 2: 7803 atio->cdb_len = 10; 7804 break; 7805 case 4: 7806 atio->cdb_len = 16; 7807 break; 7808 case 5: 7809 atio->cdb_len = 12; 7810 break; 7811 case 3: 7812 default: 7813 /* Only copy the opcode. */ 7814 atio->cdb_len = 1; 7815 printf("Reserved or VU command code type encountered\n"); 7816 break; 7817 } 7818 7819 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7820 7821 atio->ccb_h.status |= CAM_CDB_RECVD; 7822 7823 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7824 /* 7825 * We weren't allowed to disconnect. 7826 * We're hanging on the bus until a 7827 * continue target I/O comes in response 7828 * to this accept tio. 7829 */ 7830 #if 0 7831 printf("Received Immediate Command %d:%d:%d - %p\n", 7832 initiator, target, lun, ahc->pending_device); 7833 #endif 7834 ahc->pending_device = lstate; 7835 aic_freeze_ccb((union ccb *)atio); 7836 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7837 } 7838 xpt_done((union ccb*)atio); 7839 return (0); 7840 } 7841 7842 #endif
Cache object: 5030a17f882f10427fe108ffc0411c0d
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