Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/aic7xxx/aic7xxx.h
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1 /*- 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifndef _AIC7XXX_H_ 48 #define _AIC7XXX_H_ 49 50 /* Register Definitions */ 51 #include "aic7xxx_reg.h" 52 53 /************************* Forward Declarations *******************************/ 54 struct ahc_platform_data; 55 struct scb_platform_data; 56 struct seeprom_descriptor; 57 58 /****************************** Useful Macros *********************************/ 59 #ifndef MAX 60 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 61 #endif 62 63 #ifndef MIN 64 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 65 #endif 66 67 #ifndef TRUE 68 #define TRUE 1 69 #endif 70 #ifndef FALSE 71 #define FALSE 0 72 #endif 73 74 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 75 76 #define ALL_CHANNELS '\0' 77 #define ALL_TARGETS_MASK 0xFFFF 78 #define INITIATOR_WILDCARD (~0) 79 80 #define SCSIID_TARGET(ahc, scsiid) \ 81 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 82 >> TID_SHIFT) 83 #define SCSIID_OUR_ID(scsiid) \ 84 ((scsiid) & OID) 85 #define SCSIID_CHANNEL(ahc, scsiid) \ 86 ((((ahc)->features & AHC_TWIN) != 0) \ 87 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 88 : 'A') 89 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 90 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 91 #define SCB_GET_OUR_ID(scb) \ 92 SCSIID_OUR_ID((scb)->hscb->scsiid) 93 #define SCB_GET_TARGET(ahc, scb) \ 94 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 95 #define SCB_GET_CHANNEL(ahc, scb) \ 96 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 97 #define SCB_GET_LUN(scb) \ 98 ((scb)->hscb->lun & LID) 99 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 100 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 101 #define SCB_GET_TARGET_MASK(ahc, scb) \ 102 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 103 #ifdef AHC_DEBUG 104 #define SCB_IS_SILENT(scb) \ 105 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 106 && (((scb)->flags & SCB_SILENT) != 0)) 107 #else 108 #define SCB_IS_SILENT(scb) \ 109 (((scb)->flags & SCB_SILENT) != 0) 110 #endif 111 #define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113 #define TCL_LUN(tcl) \ 114 (tcl & (AHC_NUM_LUNS - 1)) 115 #define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117 118 #ifndef AHC_TARGET_MODE 119 #undef AHC_TMODE_ENABLE 120 #define AHC_TMODE_ENABLE 0 121 #endif 122 123 /**************************** Driver Constants ********************************/ 124 /* 125 * The maximum number of supported targets. 126 */ 127 #define AHC_NUM_TARGETS 16 128 129 /* 130 * The maximum number of supported luns. 131 * The identify message only supports 64 luns in SPI3. 132 * You can have 2^64 luns when information unit transfers are enabled, 133 * but it is doubtful this driver will ever support IUTs. 134 */ 135 #define AHC_NUM_LUNS 64 136 137 /* 138 * The maximum transfer per S/G segment. 139 */ 140 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 141 142 /* 143 * The maximum amount of SCB storage in hardware on a controller. 144 * This value represents an upper bound. Controllers vary in the number 145 * they actually support. 146 */ 147 #define AHC_SCB_MAX 255 148 149 /* 150 * The maximum number of concurrent transactions supported per driver instance. 151 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 152 * the space for SCBs on the host adapter varies by model, the driver will 153 * page the SCBs between host and controller memory as needed. We are limited 154 * to 253 because: 155 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 156 * 2) We reserve one value, 255, to represent the invalid element. 157 * 3) Our input queue scheme requires one SCB to always be reserved 158 * in advance of queuing any SCBs. This takes us down to 254. 159 * 4) To handle our output queue correctly on machines that only 160 * support 32bit stores, we must clear the array 4 bytes at a 161 * time. To avoid colliding with a DMA write from the sequencer, 162 * we must be sure that 4 slots are empty when we write to clear 163 * the queue. This reduces us to 253 SCBs: 1 that just completed 164 * and the known three additional empty slots in the queue that 165 * precede it. 166 */ 167 #define AHC_MAX_QUEUE 253 168 169 /* 170 * The maximum amount of SCB storage we allocate in host memory. This 171 * number should reflect the 1 additional SCB we require to handle our 172 * qinfifo mechanism. 173 */ 174 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 175 176 /* 177 * Ring Buffer of incoming target commands. 178 * We allocate 256 to simplify the logic in the sequencer 179 * by using the natural wrap point of an 8bit counter. 180 */ 181 #define AHC_TMODE_CMDS 256 182 183 /* Reset line assertion time in us */ 184 #define AHC_BUSRESET_DELAY 25 185 186 /* Phase change constants used in target mode. */ 187 #define AHC_BUSSETTLE_DELAY 400 188 #define AHC_DATARELEASE_DELAY 400 189 190 /******************* Chip Characteristics/Operating Settings *****************/ 191 /* 192 * Chip Type 193 * The chip order is from least sophisticated to most sophisticated. 194 */ 195 typedef enum { 196 AHC_NONE = 0x0000, 197 AHC_CHIPID_MASK = 0x00FF, 198 AHC_AIC7770 = 0x0001, 199 AHC_AIC7850 = 0x0002, 200 AHC_AIC7855 = 0x0003, 201 AHC_AIC7859 = 0x0004, 202 AHC_AIC7860 = 0x0005, 203 AHC_AIC7870 = 0x0006, 204 AHC_AIC7880 = 0x0007, 205 AHC_AIC7895 = 0x0008, 206 AHC_AIC7895C = 0x0009, 207 AHC_AIC7890 = 0x000a, 208 AHC_AIC7896 = 0x000b, 209 AHC_AIC7892 = 0x000c, 210 AHC_AIC7899 = 0x000d, 211 AHC_VL = 0x0100, /* Bus type VL */ 212 AHC_EISA = 0x0200, /* Bus type EISA/ISA */ 213 AHC_PCI = 0x0400, /* Bus type PCI */ 214 AHC_BUS_MASK = 0x0F00 215 } ahc_chip; 216 217 /* 218 * Features available in each chip type. 219 */ 220 typedef enum { 221 AHC_FENONE = 0x00000, 222 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 223 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 224 AHC_WIDE = 0x00004, /* Wide Channel */ 225 AHC_TWIN = 0x00008, /* Twin Channel */ 226 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 227 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 228 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 229 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 230 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 231 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 232 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 233 AHC_DT = 0x00800, /* Double Transition transfers */ 234 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 235 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 236 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 237 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 238 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 239 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 240 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 241 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 242 AHC_AIC7770_FE = AHC_FENONE, 243 /* 244 * The real 7850 does not support Ultra modes, but there are 245 * several cards that use the generic 7850 PCI ID even though 246 * they are using an Ultra capable chip (7859/7860). We start 247 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 248 * register to determine if the capability is really present. 249 */ 250 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 251 AHC_AIC7860_FE = AHC_AIC7850_FE, 252 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 253 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 254 /* 255 * Although we have space for both the initiator and 256 * target roles on ULTRA2 chips, we currently disable 257 * the initiator role to allow multi-scsi-id target mode 258 * configurations. We can only respond on the same SCSI 259 * ID as our initiator role if we allow initiator operation. 260 * At some point, we should add a configuration knob to 261 * allow both roles to be loaded. 262 */ 263 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 264 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 265 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 266 |AHC_TARGETMODE, 267 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 268 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 269 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 270 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 271 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 272 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 273 } ahc_feature; 274 275 /* 276 * Bugs in the silicon that we work around in software. 277 */ 278 typedef enum { 279 AHC_BUGNONE = 0x00, 280 /* 281 * On all chips prior to the U2 product line, 282 * the WIDEODD S/G segment feature does not 283 * work during scsi->HostBus transfers. 284 */ 285 AHC_TMODE_WIDEODD_BUG = 0x01, 286 /* 287 * On the aic7890/91 Rev 0 chips, the autoflush 288 * feature does not work. A manual flush of 289 * the DMA FIFO is required. 290 */ 291 AHC_AUTOFLUSH_BUG = 0x02, 292 /* 293 * On many chips, cacheline streaming does not work. 294 */ 295 AHC_CACHETHEN_BUG = 0x04, 296 /* 297 * On the aic7896/97 chips, cacheline 298 * streaming must be enabled. 299 */ 300 AHC_CACHETHEN_DIS_BUG = 0x08, 301 /* 302 * PCI 2.1 Retry failure on non-empty data fifo. 303 */ 304 AHC_PCI_2_1_RETRY_BUG = 0x10, 305 /* 306 * Controller does not handle cacheline residuals 307 * properly on S/G segments if PCI MWI instructions 308 * are allowed. 309 */ 310 AHC_PCI_MWI_BUG = 0x20, 311 /* 312 * An SCB upload using the SCB channel's 313 * auto array entry copy feature may 314 * corrupt data. This appears to only 315 * occur on 66MHz systems. 316 */ 317 AHC_SCBCHAN_UPLOAD_BUG = 0x40 318 } ahc_bug; 319 320 /* 321 * Configuration specific settings. 322 * The driver determines these settings by probing the 323 * chip/controller's configuration. 324 */ 325 typedef enum { 326 AHC_FNONE = 0x000, 327 AHC_PRIMARY_CHANNEL = 0x003, /* 328 * The channel that should 329 * be probed first. 330 */ 331 AHC_USEDEFAULTS = 0x004, /* 332 * For cards without an seeprom 333 * or a BIOS to initialize the chip's 334 * SRAM, we use the default target 335 * settings. 336 */ 337 AHC_SEQUENCER_DEBUG = 0x008, 338 AHC_SHARED_SRAM = 0x010, 339 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 340 AHC_RESET_BUS_A = 0x040, 341 AHC_RESET_BUS_B = 0x080, 342 AHC_EXTENDED_TRANS_A = 0x100, 343 AHC_EXTENDED_TRANS_B = 0x200, 344 AHC_TERM_ENB_A = 0x400, 345 AHC_TERM_ENB_B = 0x800, 346 AHC_INITIATORROLE = 0x1000, /* 347 * Allow initiator operations on 348 * this controller. 349 */ 350 AHC_TARGETROLE = 0x2000, /* 351 * Allow target operations on this 352 * controller. 353 */ 354 AHC_NEWEEPROM_FMT = 0x4000, 355 AHC_RESOURCE_SHORTAGE = 0x8000, 356 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 357 AHC_INT50_SPEEDFLEX = 0x20000, /* 358 * Internal 50pin connector 359 * sits behind an aic3860 360 */ 361 AHC_SCB_BTT = 0x40000, /* 362 * The busy targets table is 363 * stored in SCB space rather 364 * than SRAM. 365 */ 366 AHC_BIOS_ENABLED = 0x80000, 367 AHC_ALL_INTERRUPTS = 0x100000, 368 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 369 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 370 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 371 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 372 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 373 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 374 AHC_DISABLE_PCI_PERR = 0x10000000, 375 AHC_HAS_TERM_LOGIC = 0x20000000, 376 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */ 377 } ahc_flag; 378 379 /************************* Hardware SCB Definition ***************************/ 380 381 /* 382 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 383 * consists of a "hardware SCB" mirroring the fields available on the card 384 * and additional information the kernel stores for each transaction. 385 * 386 * To minimize space utilization, a portion of the hardware scb stores 387 * different data during different portions of a SCSI transaction. 388 * As initialized by the host driver for the initiator role, this area 389 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 390 * the cdb has been presented to the target, this area serves to store 391 * residual transfer information and the SCSI status byte. 392 * For the target role, the contents of this area do not change, but 393 * still serve a different purpose than for the initiator role. See 394 * struct target_data for details. 395 */ 396 397 /* 398 * Status information embedded in the shared poriton of 399 * an SCB after passing the cdb to the target. The kernel 400 * driver will only read this data for transactions that 401 * complete abnormally (non-zero status byte). 402 */ 403 struct status_pkt { 404 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 405 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 406 uint8_t scsi_status; /* Standard SCSI status byte */ 407 }; 408 409 /* 410 * Target mode version of the shared data SCB segment. 411 */ 412 struct target_data { 413 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 414 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 415 uint8_t scsi_status; /* SCSI status to give to initiator */ 416 uint8_t target_phases; /* Bitmap of phases to execute */ 417 uint8_t data_phase; /* Data-In or Data-Out */ 418 uint8_t initiator_tag; /* Initiator's transaction tag */ 419 }; 420 421 #define MAX_CDB_LEN 16 422 struct hardware_scb { 423 /**/ union { 424 /* 425 * If the cdb is 12 bytes or less, we embed it directly 426 * in the SCB. For longer cdbs, we embed the address 427 * of the cdb payload as seen by the chip and a DMA 428 * is used to pull it in. 429 */ 430 uint8_t cdb[12]; 431 uint32_t cdb_ptr; 432 struct status_pkt status; 433 struct target_data tdata; 434 } shared_data; 435 /* 436 * A word about residuals. 437 * The scb is presented to the sequencer with the dataptr and datacnt 438 * fields initialized to the contents of the first S/G element to 439 * transfer. The sgptr field is initialized to the bus address for 440 * the S/G element that follows the first in the in core S/G array 441 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 442 * S/G entry for this transfer (single S/G element transfer with the 443 * first elements address and length preloaded in the dataptr/datacnt 444 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 445 * The SG_FULL_RESID flag ensures that the residual will be correctly 446 * noted even if no data transfers occur. Once the data phase is entered, 447 * the residual sgptr and datacnt are loaded from the sgptr and the 448 * datacnt fields. After each S/G element's dataptr and length are 449 * loaded into the hardware, the residual sgptr is advanced. After 450 * each S/G element is expired, its datacnt field is checked to see 451 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 452 * residual sg ptr and the transfer is considered complete. If the 453 * sequencer determines that there is a residual in the transfer, it 454 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 455 * host memory. To sumarize: 456 * 457 * Sequencer: 458 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 459 * or residual_sgptr does not have SG_LIST_NULL set. 460 * 461 * o We are transferring the last segment if residual_datacnt has 462 * the SG_LAST_SEG flag set. 463 * 464 * Host: 465 * o A residual has occurred if a completed scb has the 466 * SG_RESID_VALID flag set. 467 * 468 * o residual_sgptr and sgptr refer to the "next" sg entry 469 * and so may point beyond the last valid sg entry for the 470 * transfer. 471 */ 472 /*12*/ uint32_t dataptr; 473 /*16*/ uint32_t datacnt; /* 474 * Byte 3 (numbered from 0) of 475 * the datacnt is really the 476 * 4th byte in that data address. 477 */ 478 /*20*/ uint32_t sgptr; 479 #define SG_PTR_MASK 0xFFFFFFF8 480 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 481 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 482 /*26*/ uint8_t lun; 483 /*27*/ uint8_t tag; /* 484 * Index into our kernel SCB array. 485 * Also used as the tag for tagged I/O 486 */ 487 /*28*/ uint8_t cdb_len; 488 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 489 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 490 /*31*/ uint8_t next; /* 491 * Used for threading SCBs in the 492 * "Waiting for Selection" and 493 * "Disconnected SCB" lists down 494 * in the sequencer. 495 */ 496 /*32*/ uint8_t cdb32[32]; /* 497 * CDB storage for cdbs of size 498 * 13->32. We store them here 499 * because hardware scbs are 500 * allocated from DMA safe 501 * memory so we are guaranteed 502 * the controller can access 503 * this data. 504 */ 505 }; 506 507 /************************ Kernel SCB Definitions ******************************/ 508 /* 509 * Some fields of the SCB are OS dependent. Here we collect the 510 * definitions for elements that all OS platforms need to include 511 * in there SCB definition. 512 */ 513 514 /* 515 * Definition of a scatter/gather element as transferred to the controller. 516 * The aic7xxx chips only support a 24bit length. We use the top byte of 517 * the length to store additional address bits and a flag to indicate 518 * that a given segment terminates the transfer. This gives us an 519 * addressable range of 512GB on machines with 64bit PCI or with chips 520 * that can support dual address cycles on 32bit PCI busses. 521 */ 522 struct ahc_dma_seg { 523 uint32_t addr; 524 uint32_t len; 525 #define AHC_DMA_LAST_SEG 0x80000000 526 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 527 #define AHC_SG_LEN_MASK 0x00FFFFFF 528 }; 529 530 struct sg_map_node { 531 bus_dmamap_t sg_dmamap; 532 bus_addr_t sg_physaddr; 533 struct ahc_dma_seg* sg_vaddr; 534 SLIST_ENTRY(sg_map_node) links; 535 }; 536 537 /* 538 * The current state of this SCB. 539 */ 540 typedef enum { 541 SCB_FLAG_NONE = 0x0000, 542 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 543 * Another device was active 544 * during the first timeout for 545 * this SCB so we gave ourselves 546 * an additional timeout period 547 * in case it was hogging the 548 * bus. 549 */ 550 SCB_DEVICE_RESET = 0x0004, 551 SCB_SENSE = 0x0008, 552 SCB_CDB32_PTR = 0x0010, 553 SCB_RECOVERY_SCB = 0x0020, 554 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 555 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 556 SCB_ABORT = 0x0100, 557 SCB_UNTAGGEDQ = 0x0200, 558 SCB_ACTIVE = 0x0400, 559 SCB_TARGET_IMMEDIATE = 0x0800, 560 SCB_TRANSMISSION_ERROR = 0x1000,/* 561 * We detected a parity or CRC 562 * error that has effected the 563 * payload of the command. This 564 * flag is checked when normal 565 * status is returned to catch 566 * the case of a target not 567 * responding to our attempt 568 * to report the error. 569 */ 570 SCB_TARGET_SCB = 0x2000, 571 SCB_SILENT = 0x4000,/* 572 * Be quiet about transmission type 573 * errors. They are expected and we 574 * don't want to upset the user. This 575 * flag is typically used during DV. 576 */ 577 SCB_TIMEDOUT = 0x8000 /* 578 * SCB has timed out and is on the 579 * timedout list. 580 */ 581 } scb_flag; 582 583 struct scb { 584 struct hardware_scb *hscb; 585 union { 586 SLIST_ENTRY(scb) sle; 587 TAILQ_ENTRY(scb) tqe; 588 } links; 589 LIST_ENTRY(scb) pending_links; 590 LIST_ENTRY(scb) timedout_links; 591 aic_io_ctx_t io_ctx; 592 struct ahc_softc *ahc_softc; 593 scb_flag flags; 594 #ifndef __linux__ 595 bus_dmamap_t dmamap; 596 #endif 597 struct scb_platform_data *platform_data; 598 struct sg_map_node *sg_map; 599 struct ahc_dma_seg *sg_list; 600 bus_addr_t sg_list_phys; 601 u_int sg_count;/* How full ahc_dma_seg is */ 602 aic_timer_t io_timer; 603 }; 604 605 struct scb_data { 606 SLIST_HEAD(, scb) free_scbs; /* 607 * Pool of SCBs ready to be assigned 608 * commands to execute. 609 */ 610 struct scb *scbindex[256]; /* 611 * Mapping from tag to SCB. 612 * As tag identifiers are an 613 * 8bit value, we provide space 614 * for all possible tag values. 615 * Any lookups to entries at or 616 * above AHC_SCB_MAX_ALLOC will 617 * always fail. 618 */ 619 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 620 struct scb *scbarray; /* Array of kernel SCBs */ 621 struct scsi_sense_data *sense; /* Per SCB sense data */ 622 623 u_int recovery_scbs; /* Transactions currently in recovery */ 624 625 /* 626 * "Bus" addresses of our data structures. 627 */ 628 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 629 bus_dmamap_t hscb_dmamap; 630 bus_addr_t hscb_busaddr; 631 bus_dma_tag_t sense_dmat; 632 bus_dmamap_t sense_dmamap; 633 bus_addr_t sense_busaddr; 634 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 635 SLIST_HEAD(, sg_map_node) sg_maps; 636 uint8_t numscbs; 637 uint8_t maxhscbs; /* Number of SCBs on the card */ 638 uint8_t init_level; /* 639 * How far we've initialized 640 * this structure. 641 */ 642 }; 643 644 /************************ Target Mode Definitions *****************************/ 645 646 /* 647 * Connection descriptor for select-in requests in target mode. 648 */ 649 struct target_cmd { 650 uint8_t scsiid; /* Our ID and the initiator's ID */ 651 uint8_t identify; /* Identify message */ 652 uint8_t bytes[22]; /* 653 * Bytes contains any additional message 654 * bytes terminated by 0xFF. The remainder 655 * is the cdb to execute. 656 */ 657 uint8_t cmd_valid; /* 658 * When a command is complete, the firmware 659 * will set cmd_valid to all bits set. 660 * After the host has seen the command, 661 * the bits are cleared. This allows us 662 * to just peek at host memory to determine 663 * if more work is complete. cmd_valid is on 664 * an 8 byte boundary to simplify setting 665 * it on aic7880 hardware which only has 666 * limited direct access to the DMA FIFO. 667 */ 668 uint8_t pad[7]; 669 }; 670 671 /* 672 * Number of events we can buffer up if we run out 673 * of immediate notify ccbs. 674 */ 675 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 676 struct ahc_tmode_event { 677 uint8_t initiator_id; 678 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 679 #define EVENT_TYPE_BUS_RESET 0xFF 680 uint8_t event_arg; 681 }; 682 683 /* 684 * Per enabled lun target mode state. 685 * As this state is directly influenced by the host OS'es target mode 686 * environment, we let the OS module define it. Forward declare the 687 * structure here so we can store arrays of them, etc. in OS neutral 688 * data structures. 689 */ 690 #ifdef AHC_TARGET_MODE 691 struct ahc_tmode_lstate { 692 struct cam_path *path; 693 struct ccb_hdr_slist accept_tios; 694 struct ccb_hdr_slist immed_notifies; 695 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 696 uint8_t event_r_idx; 697 uint8_t event_w_idx; 698 }; 699 #else 700 struct ahc_tmode_lstate; 701 #endif 702 703 /******************** Transfer Negotiation Datastructures *********************/ 704 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 705 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 706 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 707 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 708 709 #define AHC_WIDTH_UNKNOWN 0xFF 710 #define AHC_PERIOD_UNKNOWN 0xFF 711 #define AHC_OFFSET_UNKNOWN 0xFF 712 #define AHC_PPR_OPTS_UNKNOWN 0xFF 713 714 /* 715 * Transfer Negotiation Information. 716 */ 717 struct ahc_transinfo { 718 uint8_t protocol_version; /* SCSI Revision level */ 719 uint8_t transport_version; /* SPI Revision level */ 720 uint8_t width; /* Bus width */ 721 uint8_t period; /* Sync rate factor */ 722 uint8_t offset; /* Sync offset */ 723 uint8_t ppr_options; /* Parallel Protocol Request options */ 724 }; 725 726 /* 727 * Per-initiator current, goal and user transfer negotiation information. */ 728 struct ahc_initiator_tinfo { 729 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 730 struct ahc_transinfo curr; 731 struct ahc_transinfo goal; 732 struct ahc_transinfo user; 733 }; 734 735 /* 736 * Per enabled target ID state. 737 * Pointers to lun target state as well as sync/wide negotiation information 738 * for each initiator<->target mapping. For the initiator role we pretend 739 * that we are the target and the targets are the initiators since the 740 * negotiation is the same regardless of role. 741 */ 742 struct ahc_tmode_tstate { 743 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 744 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 745 746 /* 747 * Per initiator state bitmasks. 748 */ 749 uint16_t auto_negotiate;/* Auto Negotiation Required */ 750 uint16_t ultraenb; /* Using ultra sync rate */ 751 uint16_t discenable; /* Disconnection allowed */ 752 uint16_t tagenable; /* Tagged Queuing allowed */ 753 }; 754 755 /* 756 * Data structure for our table of allowed synchronous transfer rates. 757 */ 758 struct ahc_syncrate { 759 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 760 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 761 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 762 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 763 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 764 uint8_t period; /* Period to send to SCSI target */ 765 char *rate; 766 }; 767 768 /* Safe and valid period for async negotiations. */ 769 #define AHC_ASYNC_XFER_PERIOD 0x45 770 #define AHC_ULTRA2_XFER_PERIOD 0x0a 771 772 /* 773 * Indexes into our table of synchronous transfer rates. 774 */ 775 #define AHC_SYNCRATE_DT 0 776 #define AHC_SYNCRATE_ULTRA2 1 777 #define AHC_SYNCRATE_ULTRA 3 778 #define AHC_SYNCRATE_FAST 6 779 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 780 #define AHC_SYNCRATE_MIN 13 781 782 /***************************** Lookup Tables **********************************/ 783 /* 784 * Phase -> name and message out response 785 * to parity errors in each phase table. 786 */ 787 struct ahc_phase_table_entry { 788 uint8_t phase; 789 uint8_t mesg_out; /* Message response to parity errors */ 790 char *phasemsg; 791 }; 792 793 /************************** Serial EEPROM Format ******************************/ 794 795 struct seeprom_config { 796 /* 797 * Per SCSI ID Configuration Flags 798 */ 799 uint16_t device_flags[16]; /* words 0-15 */ 800 #define CFXFER 0x0007 /* synchronous transfer rate */ 801 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 802 #define CFDISC 0x0010 /* enable disconnection */ 803 #define CFWIDEB 0x0020 /* wide bus device */ 804 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 805 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 806 #define CFSTART 0x0100 /* send start unit SCSI command */ 807 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 808 #define CFRNFOUND 0x0400 /* report even if not found */ 809 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 810 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 811 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 812 813 /* 814 * BIOS Control Bits 815 */ 816 uint16_t bios_control; /* word 16 */ 817 #define CFSUPREM 0x0001 /* support all removeable drives */ 818 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 819 #define CFBIOSEN 0x0004 /* BIOS enabled */ 820 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 821 #define CFSM2DRV 0x0010 /* support more than two drives */ 822 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 823 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 824 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 825 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 826 #define CFEXTEND 0x0080 /* extended translation enabled */ 827 #define CFSCAMEN 0x0100 /* SCAM enable */ 828 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 829 #define CFMSG_VERBOSE 0x0000 830 #define CFMSG_SILENT 0x0200 831 #define CFMSG_DIAG 0x0400 832 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 833 /* UNUSED 0xff00 */ 834 835 /* 836 * Host Adapter Control Bits 837 */ 838 uint16_t adapter_control; /* word 17 */ 839 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 840 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 841 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 842 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 843 #define CFSTERM 0x0004 /* SCSI low byte termination */ 844 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 845 #define CFSPARITY 0x0010 /* SCSI parity */ 846 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 847 #define CFMULTILUN 0x0020 848 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 849 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 850 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 851 #define CFBOOTCHANSHIFT 8 852 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 853 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 854 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 855 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 856 857 /* 858 * Bus Release Time, Host Adapter ID 859 */ 860 uint16_t brtime_id; /* word 18 */ 861 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 862 /* UNUSED 0x00f0 */ 863 #define CFBRTIME 0xff00 /* bus release time */ 864 865 /* 866 * Maximum targets 867 */ 868 uint16_t max_targets; /* word 19 */ 869 #define CFMAXTARG 0x00ff /* maximum targets */ 870 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 871 #define CFBOOTID 0xf000 /* Target to boot from */ 872 uint16_t res_1[10]; /* words 20-29 */ 873 uint16_t signature; /* Signature == 0x250 */ 874 #define CFSIGNATURE 0x250 875 #define CFSIGNATURE2 0x300 876 uint16_t checksum; /* word 31 */ 877 }; 878 879 /**************************** Message Buffer *********************************/ 880 typedef enum { 881 MSG_TYPE_NONE = 0x00, 882 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 883 MSG_TYPE_INITIATOR_MSGIN = 0x02, 884 MSG_TYPE_TARGET_MSGOUT = 0x03, 885 MSG_TYPE_TARGET_MSGIN = 0x04 886 } ahc_msg_type; 887 888 typedef enum { 889 MSGLOOP_IN_PROG, 890 MSGLOOP_MSGCOMPLETE, 891 MSGLOOP_TERMINATED 892 } msg_loop_stat; 893 894 /*********************** Software Configuration Structure *********************/ 895 TAILQ_HEAD(scb_tailq, scb); 896 897 struct ahc_aic7770_softc { 898 /* 899 * Saved register state used for chip_init(). 900 */ 901 uint8_t busspd; 902 uint8_t bustime; 903 }; 904 905 struct ahc_pci_softc { 906 /* 907 * Saved register state used for chip_init(). 908 */ 909 uint32_t devconfig; 910 uint16_t targcrccnt; 911 uint8_t command; 912 uint8_t csize_lattime; 913 uint8_t optionmode; 914 uint8_t crccontrol1; 915 uint8_t dscommand0; 916 uint8_t dspcistatus; 917 uint8_t scbbaddr; 918 uint8_t dff_thrsh; 919 }; 920 921 union ahc_bus_softc { 922 struct ahc_aic7770_softc aic7770_softc; 923 struct ahc_pci_softc pci_softc; 924 }; 925 926 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 927 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 928 typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 929 typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 930 typedef void ahc_callback_t (void *); 931 932 #define AIC_SCB_DATA(softc) ((softc)->scb_data) 933 934 struct ahc_softc { 935 bus_space_tag_t tag; 936 bus_space_handle_t bsh; 937 #ifndef __linux__ 938 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 939 #endif 940 struct scb_data *scb_data; 941 942 struct scb *next_queued_scb; 943 944 /* 945 * SCBs that have been sent to the controller 946 */ 947 LIST_HEAD(, scb) pending_scbs; 948 949 /* 950 * SCBs whose timeout routine has been called. 951 */ 952 LIST_HEAD(, scb) timedout_scbs; 953 954 /* 955 * Counting lock for deferring the release of additional 956 * untagged transactions from the untagged_queues. When 957 * the lock is decremented to 0, all queues in the 958 * untagged_queues array are run. 959 */ 960 u_int untagged_queue_lock; 961 962 /* 963 * Per-target queue of untagged-transactions. The 964 * transaction at the head of the queue is the 965 * currently pending untagged transaction for the 966 * target. The driver only allows a single untagged 967 * transaction per target. 968 */ 969 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 970 971 /* 972 * Bus attachment specific data. 973 */ 974 union ahc_bus_softc bus_softc; 975 976 /* 977 * Platform specific data. 978 */ 979 struct ahc_platform_data *platform_data; 980 981 /* 982 * Platform specific device information. 983 */ 984 aic_dev_softc_t dev_softc; 985 986 /* 987 * Bus specific device information. 988 */ 989 ahc_bus_intr_t bus_intr; 990 991 /* 992 * Bus specific initialization required 993 * after a chip reset. 994 */ 995 ahc_bus_chip_init_t bus_chip_init; 996 997 /* 998 * Bus specific suspend routine. 999 */ 1000 ahc_bus_suspend_t bus_suspend; 1001 1002 /* 1003 * Bus specific resume routine. 1004 */ 1005 ahc_bus_resume_t bus_resume; 1006 1007 /* 1008 * Target mode related state kept on a per enabled lun basis. 1009 * Targets that are not enabled will have null entries. 1010 * As an initiator, we keep one target entry for our initiator 1011 * ID to store our sync/wide transfer settings. 1012 */ 1013 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 1014 1015 /* 1016 * The black hole device responsible for handling requests for 1017 * disabled luns on enabled targets. 1018 */ 1019 struct ahc_tmode_lstate *black_hole; 1020 1021 /* 1022 * Device instance currently on the bus awaiting a continue TIO 1023 * for a command that was not given the disconnect priveledge. 1024 */ 1025 struct ahc_tmode_lstate *pending_device; 1026 1027 /* 1028 * Card characteristics 1029 */ 1030 ahc_chip chip; 1031 ahc_feature features; 1032 ahc_bug bugs; 1033 ahc_flag flags; 1034 struct seeprom_config *seep_config; 1035 1036 /* Values to store in the SEQCTL register for pause and unpause */ 1037 uint8_t unpause; 1038 uint8_t pause; 1039 1040 /* Command Queues */ 1041 uint8_t qoutfifonext; 1042 uint8_t qinfifonext; 1043 uint8_t *qoutfifo; 1044 uint8_t *qinfifo; 1045 1046 /* Critical Section Data */ 1047 struct cs *critical_sections; 1048 u_int num_critical_sections; 1049 1050 /* Links for chaining softcs */ 1051 TAILQ_ENTRY(ahc_softc) links; 1052 1053 /* Channel Names ('A', 'B', etc.) */ 1054 char channel; 1055 char channel_b; 1056 1057 /* Initiator Bus ID */ 1058 uint8_t our_id; 1059 uint8_t our_id_b; 1060 1061 /* 1062 * PCI error detection. 1063 */ 1064 int unsolicited_ints; 1065 1066 /* 1067 * Target incoming command FIFO. 1068 */ 1069 struct target_cmd *targetcmds; 1070 uint8_t tqinfifonext; 1071 1072 /* 1073 * Cached copy of the sequencer control register. 1074 */ 1075 uint8_t seqctl; 1076 1077 /* 1078 * Incoming and outgoing message handling. 1079 */ 1080 uint8_t send_msg_perror; 1081 ahc_msg_type msg_type; 1082 uint8_t msgout_buf[12];/* Message we are sending */ 1083 uint8_t msgin_buf[12];/* Message we are receiving */ 1084 u_int msgout_len; /* Length of message to send */ 1085 u_int msgout_index; /* Current index in msgout */ 1086 u_int msgin_index; /* Current index in msgin */ 1087 1088 /* 1089 * Mapping information for data structures shared 1090 * between the sequencer and kernel. 1091 */ 1092 bus_dma_tag_t parent_dmat; 1093 bus_dma_tag_t shared_data_dmat; 1094 bus_dmamap_t shared_data_dmamap; 1095 bus_addr_t shared_data_busaddr; 1096 1097 /* 1098 * Bus address of the one byte buffer used to 1099 * work-around a DMA bug for chips <= aic7880 1100 * in target mode. 1101 */ 1102 bus_addr_t dma_bug_buf; 1103 1104 /* Number of enabled target mode device on this card */ 1105 u_int enabled_luns; 1106 1107 /* Initialization level of this data structure */ 1108 u_int init_level; 1109 1110 /* PCI cacheline size. */ 1111 u_int pci_cachesize; 1112 1113 /* 1114 * Count of parity errors we have seen as a target. 1115 * We auto-disable parity error checking after seeing 1116 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1117 */ 1118 u_int pci_target_perr_count; 1119 #define AHC_PCI_TARGET_PERR_THRESH 10 1120 1121 /* Maximum number of sequencer instructions supported. */ 1122 u_int instruction_ram_size; 1123 1124 /* Per-Unit descriptive information */ 1125 const char *description; 1126 char *name; 1127 int unit; 1128 1129 /* Selection Timer settings */ 1130 int seltime; 1131 int seltime_b; 1132 1133 uint16_t user_discenable;/* Disconnection allowed */ 1134 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1135 }; 1136 1137 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1138 extern struct ahc_softc_tailq ahc_tailq; 1139 1140 /************************ Active Device Information ***************************/ 1141 typedef enum { 1142 ROLE_UNKNOWN, 1143 ROLE_INITIATOR, 1144 ROLE_TARGET 1145 } role_t; 1146 1147 struct ahc_devinfo { 1148 int our_scsiid; 1149 int target_offset; 1150 uint16_t target_mask; 1151 u_int target; 1152 u_int lun; 1153 char channel; 1154 role_t role; /* 1155 * Only guaranteed to be correct if not 1156 * in the busfree state. 1157 */ 1158 }; 1159 1160 /****************************** PCI Structures ********************************/ 1161 #define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 1162 #define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 1163 1164 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1165 1166 struct ahc_pci_identity { 1167 uint64_t full_id; 1168 uint64_t id_mask; 1169 char *name; 1170 ahc_device_setup_t *setup; 1171 }; 1172 extern struct ahc_pci_identity ahc_pci_ident_table[]; 1173 extern const u_int ahc_num_pci_devs; 1174 1175 /*************************** VL/EISA/ISA Declarations *************************/ 1176 struct aic7770_identity { 1177 uint32_t full_id; 1178 uint32_t id_mask; 1179 const char *name; 1180 ahc_device_setup_t *setup; 1181 }; 1182 extern struct aic7770_identity aic7770_ident_table[]; 1183 extern const int ahc_num_aic7770_devs; 1184 1185 #define AHC_EISA_SLOT_SIZE 0x1000 1186 #define AHC_EISA_SLOT_OFFSET 0xc00 1187 #define AHC_EISA_IOSIZE 0x100 1188 1189 /*************************** Function Declarations ****************************/ 1190 /******************************************************************************/ 1191 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1192 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1193 void ahc_busy_tcl(struct ahc_softc *ahc, 1194 u_int tcl, u_int busyid); 1195 1196 /***************************** PCI Front End *********************************/ 1197 struct ahc_pci_identity *ahc_find_pci_device(aic_dev_softc_t); 1198 int ahc_pci_config(struct ahc_softc *, 1199 struct ahc_pci_identity *); 1200 int ahc_pci_test_register_access(struct ahc_softc *); 1201 1202 /*************************** ISA/EISA/VL Front End ****************************/ 1203 struct aic7770_identity *aic7770_find_device(uint32_t); 1204 int aic7770_config(struct ahc_softc *ahc, 1205 struct aic7770_identity *, 1206 u_int port); 1207 1208 /************************** SCB and SCB queue management **********************/ 1209 int ahc_probe_scbs(struct ahc_softc *); 1210 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1211 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1212 struct scb_tailq *queue); 1213 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1214 struct scb *scb); 1215 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1216 int target, char channel, int lun, 1217 u_int tag, role_t role); 1218 1219 /****************************** Initialization ********************************/ 1220 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1221 int ahc_softc_init(struct ahc_softc *); 1222 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1223 int ahc_chip_init(struct ahc_softc *ahc); 1224 int ahc_init(struct ahc_softc *ahc); 1225 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1226 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1227 int ahc_suspend(struct ahc_softc *ahc); 1228 int ahc_resume(struct ahc_softc *ahc); 1229 void ahc_softc_insert(struct ahc_softc *); 1230 void ahc_set_unit(struct ahc_softc *, int); 1231 void ahc_set_name(struct ahc_softc *, char *); 1232 int ahc_alloc_scbs(struct ahc_softc *ahc); 1233 void ahc_free(struct ahc_softc *ahc); 1234 int ahc_reset(struct ahc_softc *ahc, int reinit); 1235 void ahc_shutdown(void *arg); 1236 1237 /*************************** Interrupt Services *******************************/ 1238 void ahc_clear_intstat(struct ahc_softc *ahc); 1239 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1240 #ifdef AHC_TARGET_MODE 1241 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1242 #endif 1243 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1244 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1245 void ahc_handle_scsiint(struct ahc_softc *ahc, 1246 u_int intstat); 1247 void ahc_clear_critical_section(struct ahc_softc *ahc); 1248 1249 /***************************** Error Recovery *********************************/ 1250 typedef enum { 1251 SEARCH_COMPLETE, 1252 SEARCH_COUNT, 1253 SEARCH_REMOVE 1254 } ahc_search_action; 1255 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1256 char channel, int lun, u_int tag, 1257 role_t role, uint32_t status, 1258 ahc_search_action action); 1259 int ahc_search_untagged_queues(struct ahc_softc *ahc, 1260 aic_io_ctx_t ctx, 1261 int target, char channel, 1262 int lun, uint32_t status, 1263 ahc_search_action action); 1264 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1265 char channel, int lun, u_int tag, 1266 int stop_on_first, int remove, 1267 int save_state); 1268 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1269 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1270 int initiate_reset); 1271 int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1272 char channel, int lun, u_int tag, 1273 role_t role, uint32_t status); 1274 void ahc_restart(struct ahc_softc *ahc); 1275 void ahc_calc_residual(struct ahc_softc *ahc, 1276 struct scb *scb); 1277 void ahc_timeout(struct scb *scb); 1278 void ahc_recover_commands(struct ahc_softc *ahc); 1279 /*************************** Utility Functions ********************************/ 1280 struct ahc_phase_table_entry* 1281 ahc_lookup_phase_entry(int phase); 1282 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1283 u_int our_id, u_int target, 1284 u_int lun, char channel, 1285 role_t role); 1286 /************************** Transfer Negotiation ******************************/ 1287 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1288 u_int *ppr_options, u_int maxsync); 1289 u_int ahc_find_period(struct ahc_softc *ahc, 1290 u_int scsirate, u_int maxsync); 1291 void ahc_validate_offset(struct ahc_softc *ahc, 1292 struct ahc_initiator_tinfo *tinfo, 1293 struct ahc_syncrate *syncrate, 1294 u_int *offset, int wide, 1295 role_t role); 1296 void ahc_validate_width(struct ahc_softc *ahc, 1297 struct ahc_initiator_tinfo *tinfo, 1298 u_int *bus_width, 1299 role_t role); 1300 /* 1301 * Negotiation types. These are used to qualify if we should renegotiate 1302 * even if our goal and current transport parameters are identical. 1303 */ 1304 typedef enum { 1305 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1306 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1307 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1308 } ahc_neg_type; 1309 int ahc_update_neg_request(struct ahc_softc*, 1310 struct ahc_devinfo*, 1311 struct ahc_tmode_tstate*, 1312 struct ahc_initiator_tinfo*, 1313 ahc_neg_type); 1314 void ahc_set_width(struct ahc_softc *ahc, 1315 struct ahc_devinfo *devinfo, 1316 u_int width, u_int type, int paused); 1317 void ahc_set_syncrate(struct ahc_softc *ahc, 1318 struct ahc_devinfo *devinfo, 1319 struct ahc_syncrate *syncrate, 1320 u_int period, u_int offset, 1321 u_int ppr_options, 1322 u_int type, int paused); 1323 typedef enum { 1324 AHC_QUEUE_NONE, 1325 AHC_QUEUE_BASIC, 1326 AHC_QUEUE_TAGGED 1327 } ahc_queue_alg; 1328 1329 void ahc_set_tags(struct ahc_softc *ahc, 1330 struct ahc_devinfo *devinfo, 1331 ahc_queue_alg alg); 1332 1333 /**************************** Target Mode *************************************/ 1334 #ifdef AHC_TARGET_MODE 1335 void ahc_send_lstate_events(struct ahc_softc *, 1336 struct ahc_tmode_lstate *); 1337 void ahc_handle_en_lun(struct ahc_softc *ahc, 1338 struct cam_sim *sim, union ccb *ccb); 1339 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1340 struct cam_sim *sim, union ccb *ccb, 1341 struct ahc_tmode_tstate **tstate, 1342 struct ahc_tmode_lstate **lstate, 1343 int notfound_failure); 1344 #ifndef AHC_TMODE_ENABLE 1345 #define AHC_TMODE_ENABLE 0 1346 #endif 1347 #endif 1348 /******************************* Debug ***************************************/ 1349 #ifdef AHC_DEBUG 1350 extern uint32_t ahc_debug; 1351 #define AHC_SHOW_MISC 0x0001 1352 #define AHC_SHOW_SENSE 0x0002 1353 #define AHC_DUMP_SEEPROM 0x0004 1354 #define AHC_SHOW_TERMCTL 0x0008 1355 #define AHC_SHOW_MEMORY 0x0010 1356 #define AHC_SHOW_MESSAGES 0x0020 1357 #define AHC_SHOW_DV 0x0040 1358 #define AHC_SHOW_SELTO 0x0080 1359 #define AHC_SHOW_QFULL 0x0200 1360 #define AHC_SHOW_QUEUE 0x0400 1361 #define AHC_SHOW_TQIN 0x0800 1362 #define AHC_SHOW_MASKED_ERRORS 0x1000 1363 #define AHC_DEBUG_SEQUENCER 0x2000 1364 #endif 1365 void ahc_print_scb(struct scb *scb); 1366 void ahc_print_devinfo(struct ahc_softc *ahc, 1367 struct ahc_devinfo *dev); 1368 void ahc_dump_card_state(struct ahc_softc *ahc); 1369 int ahc_print_register(ahc_reg_parse_entry_t *table, 1370 u_int num_entries, 1371 const char *name, 1372 u_int address, 1373 u_int value, 1374 u_int *cur_column, 1375 u_int wrap_point); 1376 /******************************* SEEPROM *************************************/ 1377 int ahc_acquire_seeprom(struct ahc_softc *ahc, 1378 struct seeprom_descriptor *sd); 1379 void ahc_release_seeprom(struct seeprom_descriptor *sd); 1380 #endif /* _AIC7XXX_H_ */
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