1 /*-
2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD: releng/8.1/sys/dev/aic7xxx/aic7xxx.seq 165628 2006-12-29 13:08:46Z yar $
41 */
42
43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $"
44 PATCH_ARG_LIST = "struct ahc_softc *ahc"
45 PREFIX = "ahc_"
46
47 #include "aic7xxx.reg"
48 #include "scsi_message.h"
49
50 /*
51 * A few words on the waiting SCB list:
52 * After starting the selection hardware, we check for reconnecting targets
53 * as well as for our selection to complete just in case the reselection wins
54 * bus arbitration. The problem with this is that we must keep track of the
55 * SCB that we've already pulled from the QINFIFO and started the selection
56 * on just in case the reselection wins so that we can retry the selection at
57 * a later time. This problem cannot be resolved by holding a single entry
58 * in scratch ram since a reconnecting target can request sense and this will
59 * create yet another SCB waiting for selection. The solution used here is to
60 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list
61 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
62 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
63 * this list everytime a request sense occurs or after completing a non-tagged
64 * command for which a second SCB has been queued. The sequencer will
65 * automatically consume the entries.
66 */
67
68 bus_free_sel:
69 /*
70 * Turn off the selection hardware. We need to reset the
71 * selection request in order to perform a new selection.
72 */
73 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP;
74 and SIMODE1, ~ENBUSFREE;
75 poll_for_work:
76 call clear_target_state;
77 and SXFRCTL0, ~SPIOEN;
78 if ((ahc->features & AHC_ULTRA2) != 0) {
79 clr SCSIBUSL;
80 }
81 test SCSISEQ, ENSELO jnz poll_for_selection;
82 if ((ahc->features & AHC_TWIN) != 0) {
83 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
84 test SCSISEQ, ENSELO jnz poll_for_selection;
85 }
86 BEGIN_CRITICAL;
87 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
88 END_CRITICAL;
89 poll_for_work_loop:
90 if ((ahc->features & AHC_TWIN) != 0) {
91 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
92 }
93 test SSTAT0, SELDO|SELDI jnz selection;
94 test_queue:
95 /* Has the driver posted any work for us? */
96 BEGIN_CRITICAL;
97 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
98 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
99 } else {
100 mov A, QINPOS;
101 cmp KERNEL_QINPOS, A je poll_for_work_loop;
102 }
103 mov ARG_1, NEXT_QUEUED_SCB;
104
105 /*
106 * We have at least one queued SCB now and we don't have any
107 * SCBs in the list of SCBs awaiting selection. Allocate a
108 * card SCB for the host's SCB and get to work on it.
109 */
110 if ((ahc->flags & AHC_PAGESCBS) != 0) {
111 mov ALLZEROS call get_free_or_disc_scb;
112 } else {
113 /* In the non-paging case, the SCBID == hardware SCB index */
114 mov SCBPTR, ARG_1;
115 }
116 or SEQ_FLAGS2, SCB_DMA;
117 END_CRITICAL;
118 dma_queued_scb:
119 /*
120 * DMA the SCB from host ram into the current SCB location.
121 */
122 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
123 mov ARG_1 call dma_scb;
124 /*
125 * Check one last time to see if this SCB was canceled
126 * before we completed the DMA operation. If it was,
127 * the QINFIFO next pointer will not match our saved
128 * value.
129 */
130 mov A, ARG_1;
131 BEGIN_CRITICAL;
132 cmp NEXT_QUEUED_SCB, A jne abort_qinscb;
133 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
134 cmp SCB_TAG, A je . + 2;
135 mvi SCB_MISMATCH call set_seqint;
136 }
137 mov NEXT_QUEUED_SCB, SCB_NEXT;
138 mov SCB_NEXT,WAITING_SCBH;
139 mov WAITING_SCBH, SCBPTR;
140 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
141 mov NONE, SNSCB_QOFF;
142 } else {
143 inc QINPOS;
144 }
145 and SEQ_FLAGS2, ~SCB_DMA;
146 start_waiting:
147 /*
148 * Start the first entry on the waiting SCB list.
149 */
150 mov SCBPTR, WAITING_SCBH;
151 call start_selection;
152 END_CRITICAL;
153
154 poll_for_selection:
155 /*
156 * Twin channel devices cannot handle things like SELTO
157 * interrupts on the "background" channel. So, while
158 * selecting, keep polling the current channel until
159 * either a selection or reselection occurs.
160 */
161 test SSTAT0, SELDO|SELDI jz poll_for_selection;
162
163 selection:
164 /*
165 * We aren't expecting a bus free, so interrupt
166 * the kernel driver if it happens.
167 */
168 mvi CLRSINT1,CLRBUSFREE;
169 if ((ahc->features & AHC_DT) == 0) {
170 or SIMODE1, ENBUSFREE;
171 }
172
173 /*
174 * Guard against a bus free after (re)selection
175 * but prior to enabling the busfree interrupt. SELDI
176 * and SELDO will be cleared in that case.
177 */
178 test SSTAT0, SELDI|SELDO jz bus_free_sel;
179 test SSTAT0,SELDO jnz select_out;
180 select_in:
181 if ((ahc->flags & AHC_TARGETROLE) != 0) {
182 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
183 test SSTAT0, TARGET jz initiator_reselect;
184 }
185 mvi CLRSINT0, CLRSELDI;
186
187 /*
188 * We've just been selected. Assert BSY and
189 * setup the phase for receiving messages
190 * from the target.
191 */
192 mvi SCSISIGO, P_MESGOUT|BSYO;
193
194 /*
195 * Setup the DMA for sending the identify and
196 * command information.
197 */
198 mvi SEQ_FLAGS, CMDPHASE_PENDING;
199
200 mov A, TQINPOS;
201 if ((ahc->features & AHC_CMD_CHAN) != 0) {
202 mvi DINDEX, CCHADDR;
203 mvi SHARED_DATA_ADDR call set_32byte_addr;
204 mvi CCSCBCTL, CCSCBRESET;
205 } else {
206 mvi DINDEX, HADDR;
207 mvi SHARED_DATA_ADDR call set_32byte_addr;
208 mvi DFCNTRL, FIFORESET;
209 }
210
211 /* Initiator that selected us */
212 and SAVED_SCSIID, SELID_MASK, SELID;
213 /* The Target ID we were selected at */
214 if ((ahc->features & AHC_MULTI_TID) != 0) {
215 and A, OID, TARGIDIN;
216 } else if ((ahc->features & AHC_ULTRA2) != 0) {
217 and A, OID, SCSIID_ULTRA2;
218 } else {
219 and A, OID, SCSIID;
220 }
221 or SAVED_SCSIID, A;
222 if ((ahc->features & AHC_TWIN) != 0) {
223 test SBLKCTL, SELBUSB jz . + 2;
224 or SAVED_SCSIID, TWIN_CHNLB;
225 }
226 if ((ahc->features & AHC_CMD_CHAN) != 0) {
227 mov CCSCBRAM, SAVED_SCSIID;
228 } else {
229 mov DFDAT, SAVED_SCSIID;
230 }
231
232 /*
233 * If ATN isn't asserted, the target isn't interested
234 * in talking to us. Go directly to bus free.
235 * XXX SCSI-1 may require us to assume lun 0 if
236 * ATN is false.
237 */
238 test SCSISIGI, ATNI jz target_busfree;
239
240 /*
241 * Watch ATN closely now as we pull in messages from the
242 * initiator. We follow the guidlines from section 6.5
243 * of the SCSI-2 spec for what messages are allowed when.
244 */
245 call target_inb;
246
247 /*
248 * Our first message must be one of IDENTIFY, ABORT, or
249 * BUS_DEVICE_RESET.
250 */
251 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
252 /* Store for host */
253 if ((ahc->features & AHC_CMD_CHAN) != 0) {
254 mov CCSCBRAM, DINDEX;
255 } else {
256 mov DFDAT, DINDEX;
257 }
258 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
259
260 /* Remember for disconnection decision */
261 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
262 /* XXX Honor per target settings too */
263 or SEQ_FLAGS, NO_DISCONNECT;
264
265 test SCSISIGI, ATNI jz ident_messages_done;
266 call target_inb;
267 /*
268 * If this is a tagged request, the tagged message must
269 * immediately follow the identify. We test for a valid
270 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and
271 * < MSG_IGN_WIDE_RESIDUE.
272 */
273 add A, -MSG_SIMPLE_Q_TAG, DINDEX;
274 jnc ident_messages_done_msg_pending;
275 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
276 jc ident_messages_done_msg_pending;
277
278 /* Store for host */
279 if ((ahc->features & AHC_CMD_CHAN) != 0) {
280 mov CCSCBRAM, DINDEX;
281 } else {
282 mov DFDAT, DINDEX;
283 }
284
285 /*
286 * If the initiator doesn't feel like providing a tag number,
287 * we've got a failed selection and must transition to bus
288 * free.
289 */
290 test SCSISIGI, ATNI jz target_busfree;
291
292 /*
293 * Store the tag for the host.
294 */
295 call target_inb;
296 if ((ahc->features & AHC_CMD_CHAN) != 0) {
297 mov CCSCBRAM, DINDEX;
298 } else {
299 mov DFDAT, DINDEX;
300 }
301 mov INITIATOR_TAG, DINDEX;
302 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
303
304 ident_messages_done:
305 /* Terminate the ident list */
306 if ((ahc->features & AHC_CMD_CHAN) != 0) {
307 mvi CCSCBRAM, SCB_LIST_NULL;
308 } else {
309 mvi DFDAT, SCB_LIST_NULL;
310 }
311 or SEQ_FLAGS, TARG_CMD_PENDING;
312 test SEQ_FLAGS2, TARGET_MSG_PENDING
313 jnz target_mesgout_pending;
314 test SCSISIGI, ATNI jnz target_mesgout_continue;
315 jmp target_ITloop;
316
317
318 ident_messages_done_msg_pending:
319 or SEQ_FLAGS2, TARGET_MSG_PENDING;
320 jmp ident_messages_done;
321
322 /*
323 * Pushed message loop to allow the kernel to
324 * run it's own target mode message state engine.
325 */
326 host_target_message_loop:
327 mvi HOST_MSG_LOOP call set_seqint;
328 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
329 test SSTAT0, SPIORDY jz .;
330 jmp host_target_message_loop;
331 }
332
333 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
334 /*
335 * Reselection has been initiated by a target. Make a note that we've been
336 * reselected, but haven't seen an IDENTIFY message from the target yet.
337 */
338 initiator_reselect:
339 /* XXX test for and handle ONE BIT condition */
340 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
341 and SAVED_SCSIID, SELID_MASK, SELID;
342 if ((ahc->features & AHC_ULTRA2) != 0) {
343 and A, OID, SCSIID_ULTRA2;
344 } else {
345 and A, OID, SCSIID;
346 }
347 or SAVED_SCSIID, A;
348 if ((ahc->features & AHC_TWIN) != 0) {
349 test SBLKCTL, SELBUSB jz . + 2;
350 or SAVED_SCSIID, TWIN_CHNLB;
351 }
352 mvi CLRSINT0, CLRSELDI;
353 jmp ITloop;
354 }
355
356 abort_qinscb:
357 call add_scb_to_free_list;
358 jmp poll_for_work_loop;
359
360 BEGIN_CRITICAL;
361 start_selection:
362 /*
363 * If bus reset interrupts have been disabled (from a previous
364 * reset), re-enable them now. Resets are only of interest
365 * when we have outstanding transactions, so we can safely
366 * defer re-enabling the interrupt until, as an initiator,
367 * we start sending out transactions again.
368 */
369 test SIMODE1, ENSCSIRST jnz . + 3;
370 mvi CLRSINT1, CLRSCSIRSTI;
371 or SIMODE1, ENSCSIRST;
372 if ((ahc->features & AHC_TWIN) != 0) {
373 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
374 test SCB_SCSIID, TWIN_CHNLB jz . + 2;
375 or SINDEX, SELBUSB;
376 mov SBLKCTL,SINDEX; /* select channel */
377 }
378 initialize_scsiid:
379 if ((ahc->features & AHC_ULTRA2) != 0) {
380 mov SCSIID_ULTRA2, SCB_SCSIID;
381 } else if ((ahc->features & AHC_TWIN) != 0) {
382 and SCSIID, TWIN_TID|OID, SCB_SCSIID;
383 } else {
384 mov SCSIID, SCB_SCSIID;
385 }
386 if ((ahc->flags & AHC_TARGETROLE) != 0) {
387 mov SINDEX, SCSISEQ_TEMPLATE;
388 test SCB_CONTROL, TARGET_SCB jz . + 2;
389 or SINDEX, TEMODE;
390 mov SCSISEQ, SINDEX ret;
391 } else {
392 mov SCSISEQ, SCSISEQ_TEMPLATE ret;
393 }
394 END_CRITICAL;
395
396 /*
397 * Initialize transfer settings with SCB provided settings.
398 */
399 set_transfer_settings:
400 if ((ahc->features & AHC_ULTRA) != 0) {
401 test SCB_CONTROL, ULTRAENB jz . + 2;
402 or SXFRCTL0, FAST20;
403 }
404 /*
405 * Initialize SCSIRATE with the appropriate value for this target.
406 */
407 if ((ahc->features & AHC_ULTRA2) != 0) {
408 bmov SCSIRATE, SCB_SCSIRATE, 2 ret;
409 } else {
410 mov SCSIRATE, SCB_SCSIRATE ret;
411 }
412
413 if ((ahc->flags & AHC_TARGETROLE) != 0) {
414 /*
415 * We carefully toggle SPIOEN to allow us to return the
416 * message byte we receive so it can be checked prior to
417 * driving REQ on the bus for the next byte.
418 */
419 target_inb:
420 /*
421 * Drive REQ on the bus by enabling SCSI PIO.
422 */
423 or SXFRCTL0, SPIOEN;
424 /* Wait for the byte */
425 test SSTAT0, SPIORDY jz .;
426 /* Prevent our read from triggering another REQ */
427 and SXFRCTL0, ~SPIOEN;
428 /* Save latched contents */
429 mov DINDEX, SCSIDATL ret;
430 }
431
432 /*
433 * After the selection, remove this SCB from the "waiting SCB"
434 * list. This is achieved by simply moving our "next" pointer into
435 * WAITING_SCBH. Our next pointer will be set to null the next time this
436 * SCB is used, so don't bother with it now.
437 */
438 select_out:
439 /* Turn off the selection hardware */
440 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
441 mov SCBPTR, WAITING_SCBH;
442 mov WAITING_SCBH,SCB_NEXT;
443 mov SAVED_SCSIID, SCB_SCSIID;
444 and SAVED_LUN, LID, SCB_LUN;
445 call set_transfer_settings;
446 if ((ahc->flags & AHC_TARGETROLE) != 0) {
447 test SSTAT0, TARGET jz initiator_select;
448
449 or SXFRCTL0, CLRSTCNT|CLRCHN;
450
451 /*
452 * Put tag in connonical location since not
453 * all connections have an SCB.
454 */
455 mov INITIATOR_TAG, SCB_TARGET_ITAG;
456
457 /*
458 * We've just re-selected an initiator.
459 * Assert BSY and setup the phase for
460 * sending our identify messages.
461 */
462 mvi P_MESGIN|BSYO call change_phase;
463 mvi CLRSINT0, CLRSELDO;
464
465 /*
466 * Start out with a simple identify message.
467 */
468 or SAVED_LUN, MSG_IDENTIFYFLAG call target_outb;
469
470 /*
471 * If we are the result of a tagged command, send
472 * a simple Q tag and the tag id.
473 */
474 test SCB_CONTROL, TAG_ENB jz . + 3;
475 mvi MSG_SIMPLE_Q_TAG call target_outb;
476 mov SCB_TARGET_ITAG call target_outb;
477 target_synccmd:
478 /*
479 * Now determine what phases the host wants us
480 * to go through.
481 */
482 mov SEQ_FLAGS, SCB_TARGET_PHASES;
483
484 test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
485 mvi P_MESGIN|BSYO call change_phase;
486 jmp host_target_message_loop;
487 target_ITloop:
488 /*
489 * Start honoring ATN signals now that
490 * we properly identified ourselves.
491 */
492 test SCSISIGI, ATNI jnz target_mesgout;
493 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
494 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
495 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
496
497 /*
498 * No more work to do. Either disconnect or not depending
499 * on the state of NO_DISCONNECT.
500 */
501 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect;
502 mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL;
503 call complete_target_cmd;
504 if ((ahc->flags & AHC_PAGESCBS) != 0) {
505 mov ALLZEROS call get_free_or_disc_scb;
506 }
507 cmp TARG_IMMEDIATE_SCB, SCB_LIST_NULL je .;
508 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
509 mov TARG_IMMEDIATE_SCB call dma_scb;
510 call set_transfer_settings;
511 or SXFRCTL0, CLRSTCNT|CLRCHN;
512 jmp target_synccmd;
513
514 target_mesgout:
515 mvi SCSISIGO, P_MESGOUT|BSYO;
516 target_mesgout_continue:
517 call target_inb;
518 target_mesgout_pending:
519 and SEQ_FLAGS2, ~TARGET_MSG_PENDING;
520 /* Local Processing goes here... */
521 jmp host_target_message_loop;
522
523 target_disconnect:
524 mvi P_MESGIN|BSYO call change_phase;
525 test SEQ_FLAGS, DPHASE jz . + 2;
526 mvi MSG_SAVEDATAPOINTER call target_outb;
527 mvi MSG_DISCONNECT call target_outb;
528
529 target_busfree_wait:
530 /* Wait for preceding I/O session to complete. */
531 test SCSISIGI, ACKI jnz .;
532 target_busfree:
533 and SIMODE1, ~ENBUSFREE;
534 if ((ahc->features & AHC_ULTRA2) != 0) {
535 clr SCSIBUSL;
536 }
537 clr SCSISIGO;
538 mvi LASTPHASE, P_BUSFREE;
539 call complete_target_cmd;
540 jmp poll_for_work;
541
542 target_cmdphase:
543 /*
544 * The target has dropped ATN (doesn't want to abort or BDR)
545 * and we believe this selection to be valid. If the ring
546 * buffer for new commands is full, return busy or queue full.
547 */
548 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
549 and A, HOST_TQINPOS, HS_MAILBOX;
550 } else {
551 mov A, KERNEL_TQINPOS;
552 }
553 cmp TQINPOS, A jne tqinfifo_has_space;
554 mvi P_STATUS|BSYO call change_phase;
555 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
556 mvi STATUS_QUEUE_FULL call target_outb;
557 jmp target_busfree_wait;
558 mvi STATUS_BUSY call target_outb;
559 jmp target_busfree_wait;
560 tqinfifo_has_space:
561 mvi P_COMMAND|BSYO call change_phase;
562 call target_inb;
563 mov A, DINDEX;
564 /* Store for host */
565 if ((ahc->features & AHC_CMD_CHAN) != 0) {
566 mov CCSCBRAM, A;
567 } else {
568 mov DFDAT, A;
569 }
570
571 /*
572 * Determine the number of bytes to read
573 * based on the command group code via table lookup.
574 * We reuse the first 8 bytes of the TARG_SCSIRATE
575 * BIOS array for this table. Count is one less than
576 * the total for the command since we've already fetched
577 * the first byte.
578 */
579 shr A, CMD_GROUP_CODE_SHIFT;
580 add SINDEX, CMDSIZE_TABLE, A;
581 mov A, SINDIR;
582
583 test A, 0xFF jz command_phase_done;
584 or SXFRCTL0, SPIOEN;
585 command_loop:
586 test SSTAT0, SPIORDY jz .;
587 cmp A, 1 jne . + 2;
588 and SXFRCTL0, ~SPIOEN; /* Last Byte */
589 if ((ahc->features & AHC_CMD_CHAN) != 0) {
590 mov CCSCBRAM, SCSIDATL;
591 } else {
592 mov DFDAT, SCSIDATL;
593 }
594 dec A;
595 test A, 0xFF jnz command_loop;
596
597 command_phase_done:
598 and SEQ_FLAGS, ~CMDPHASE_PENDING;
599 jmp target_ITloop;
600
601 target_dphase:
602 /*
603 * Data phases on the bus are from the
604 * perspective of the initiator. The dma
605 * code looks at LASTPHASE to determine the
606 * data direction of the DMA. Toggle it for
607 * target transfers.
608 */
609 xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
610 or SCB_TARGET_DATA_DIR, BSYO call change_phase;
611 jmp p_data;
612
613 target_sphase:
614 mvi P_STATUS|BSYO call change_phase;
615 mvi LASTPHASE, P_STATUS;
616 mov SCB_SCSI_STATUS call target_outb;
617 /* XXX Watch for ATN or parity errors??? */
618 mvi SCSISIGO, P_MESGIN|BSYO;
619 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
620 mov ALLZEROS call target_outb;
621 jmp target_busfree_wait;
622
623 complete_target_cmd:
624 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2;
625 mov SCB_TAG jmp complete_post;
626 if ((ahc->features & AHC_CMD_CHAN) != 0) {
627 /* Set the valid byte */
628 mvi CCSCBADDR, 24;
629 mov CCSCBRAM, ALLONES;
630 mvi CCHCNT, 28;
631 or CCSCBCTL, CCSCBEN|CCSCBRESET;
632 test CCSCBCTL, CCSCBDONE jz .;
633 clr CCSCBCTL;
634 } else {
635 /* Set the valid byte */
636 or DFCNTRL, FIFORESET;
637 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */
638 mov DFDAT, ALLONES;
639 mvi 28 call set_hcnt;
640 or DFCNTRL, HDMAEN|FIFOFLUSH;
641 call dma_finish;
642 }
643 inc TQINPOS;
644 mvi INTSTAT,CMDCMPLT ret;
645 }
646
647 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
648 initiator_select:
649 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
650 /*
651 * As soon as we get a successful selection, the target
652 * should go into the message out phase since we have ATN
653 * asserted.
654 */
655 mvi MSG_OUT, MSG_IDENTIFYFLAG;
656 mvi SEQ_FLAGS, NO_CDB_SENT;
657 mvi CLRSINT0, CLRSELDO;
658
659 /*
660 * Main loop for information transfer phases. Wait for the
661 * target to assert REQ before checking MSG, C/D and I/O for
662 * the bus phase.
663 */
664 mesgin_phasemis:
665 ITloop:
666 call phase_lock;
667
668 mov A, LASTPHASE;
669
670 test A, ~P_DATAIN jz p_data;
671 cmp A,P_COMMAND je p_command;
672 cmp A,P_MESGOUT je p_mesgout;
673 cmp A,P_STATUS je p_status;
674 cmp A,P_MESGIN je p_mesgin;
675
676 mvi BAD_PHASE call set_seqint;
677 jmp ITloop; /* Try reading the bus again. */
678
679 await_busfree:
680 and SIMODE1, ~ENBUSFREE;
681 mov NONE, SCSIDATL; /* Ack the last byte */
682 if ((ahc->features & AHC_ULTRA2) != 0) {
683 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
684 }
685 and SXFRCTL0, ~SPIOEN;
686 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
687 test SSTAT1,REQINIT|BUSFREE jz .;
688 test SSTAT1, BUSFREE jnz poll_for_work;
689 mvi MISSED_BUSFREE call set_seqint;
690 }
691
692 clear_target_state:
693 /*
694 * We assume that the kernel driver may reset us
695 * at any time, even in the middle of a DMA, so
696 * clear DFCNTRL too.
697 */
698 clr DFCNTRL;
699 or SXFRCTL0, CLRSTCNT|CLRCHN;
700
701 /*
702 * We don't know the target we will connect to,
703 * so default to narrow transfers to avoid
704 * parity problems.
705 */
706 if ((ahc->features & AHC_ULTRA2) != 0) {
707 bmov SCSIRATE, ALLZEROS, 2;
708 } else {
709 clr SCSIRATE;
710 if ((ahc->features & AHC_ULTRA) != 0) {
711 and SXFRCTL0, ~(FAST20);
712 }
713 }
714 mvi LASTPHASE, P_BUSFREE;
715 /* clear target specific flags */
716 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
717
718 sg_advance:
719 clr A; /* add sizeof(struct scatter) */
720 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
721 adc SCB_RESIDUAL_SGPTR[1],A;
722 adc SCB_RESIDUAL_SGPTR[2],A;
723 adc SCB_RESIDUAL_SGPTR[3],A ret;
724
725 if ((ahc->features & AHC_CMD_CHAN) != 0) {
726 disable_ccsgen:
727 test CCSGCTL, CCSGEN jz return;
728 test CCSGCTL, CCSGDONE jz .;
729 disable_ccsgen_fetch_done:
730 clr CCSGCTL;
731 test CCSGCTL, CCSGEN jnz .;
732 ret;
733 idle_loop:
734 /*
735 * Do we need any more segments for this transfer?
736 */
737 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
738
739 /* Did we just finish fetching segs? */
740 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
741
742 /* Are we actively fetching segments? */
743 test CCSGCTL, CCSGEN jnz return;
744
745 /*
746 * Do we have any prefetch left???
747 */
748 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
749
750 /*
751 * Need to fetch segments, but we can only do that
752 * if the command channel is completely idle. Make
753 * sure we don't have an SCB prefetch going on.
754 */
755 test CCSCBCTL, CCSCBEN jnz return;
756
757 /*
758 * We fetch a "cacheline aligned" and sized amount of data
759 * so we don't end up referencing a non-existant page.
760 * Cacheline aligned is in quotes because the kernel will
761 * set the prefetch amount to a reasonable level if the
762 * cacheline size is unknown.
763 */
764 mvi CCHCNT, SG_PREFETCH_CNT;
765 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
766 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
767 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
768 idle_sgfetch_complete:
769 call disable_ccsgen_fetch_done;
770 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
771 idle_sg_avail:
772 if ((ahc->features & AHC_ULTRA2) != 0) {
773 /* Does the hardware have space for another SG entry? */
774 test DFSTATUS, PRELOAD_AVAIL jz return;
775 bmov HADDR, CCSGRAM, 7;
776 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
777 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
778 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
779 }
780 call sg_advance;
781 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
782 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
783 or SINDEX, LAST_SEG;
784 mov SG_CACHE_PRE, SINDEX;
785 /* Load the segment */
786 or DFCNTRL, PRELOADEN;
787 }
788 ret;
789 }
790
791 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
792 /*
793 * Calculate the trailing portion of this S/G segment that cannot
794 * be transferred using memory write and invalidate PCI transactions.
795 * XXX Can we optimize this for PCI writes only???
796 */
797 calc_mwi_residual:
798 /*
799 * If the ending address is on a cacheline boundary,
800 * there is no need for an extra segment.
801 */
802 mov A, HCNT[0];
803 add A, A, HADDR[0];
804 and A, CACHESIZE_MASK;
805 test A, 0xFF jz return;
806
807 /*
808 * If the transfer is less than a cachline,
809 * there is no need for an extra segment.
810 */
811 test HCNT[1], 0xFF jnz calc_mwi_residual_final;
812 test HCNT[2], 0xFF jnz calc_mwi_residual_final;
813 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
814 jnc return;
815
816 calc_mwi_residual_final:
817 mov MWI_RESIDUAL, A;
818 not A;
819 inc A;
820 add HCNT[0], A;
821 adc HCNT[1], -1;
822 adc HCNT[2], -1 ret;
823 }
824
825 p_data:
826 test SEQ_FLAGS,NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
827 mvi PROTO_VIOLATION call set_seqint;
828 p_data_allowed:
829 if ((ahc->features & AHC_ULTRA2) != 0) {
830 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
831 } else {
832 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
833 }
834 test LASTPHASE, IOI jnz . + 2;
835 or DMAPARAMS, DIRECTION;
836 if ((ahc->features & AHC_CMD_CHAN) != 0) {
837 /* We don't have any valid S/G elements */
838 mvi CCSGADDR, SG_PREFETCH_CNT;
839 }
840 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
841
842 /*
843 * If we re-enter the data phase after going through another
844 * phase, our transfer location has almost certainly been
845 * corrupted by the interveining, non-data, transfers. Ask
846 * the host driver to fix us up based on the transfer residual.
847 */
848 mvi PDATA_REINIT call set_seqint;
849 jmp data_phase_loop;
850
851 data_phase_initialize:
852 /* We have seen a data phase for the first time */
853 or SEQ_FLAGS, DPHASE;
854
855 /*
856 * Initialize the DMA address and counter from the SCB.
857 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
858 * flag in the highest byte of the data count. We cannot
859 * modify the saved values in the SCB until we see a save
860 * data pointers message.
861 */
862 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
863 /* The lowest address byte must be loaded last. */
864 mov SCB_DATACNT[3] call set_hhaddr;
865 }
866 if ((ahc->features & AHC_CMD_CHAN) != 0) {
867 bmov HADDR, SCB_DATAPTR, 7;
868 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
869 } else {
870 mvi DINDEX, HADDR;
871 mvi SCB_DATAPTR call bcopy_7;
872 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
873 mvi SCB_DATACNT + 3 call bcopy_5;
874 }
875 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
876 call calc_mwi_residual;
877 }
878 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
879
880 if ((ahc->features & AHC_ULTRA2) == 0) {
881 if ((ahc->features & AHC_CMD_CHAN) != 0) {
882 bmov STCNT, HCNT, 3;
883 } else {
884 call set_stcnt_from_hcnt;
885 }
886 }
887
888 data_phase_loop:
889 /* Guard against overruns */
890 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
891
892 /*
893 * Turn on `Bit Bucket' mode, wait until the target takes
894 * us to another phase, and then notify the host.
895 */
896 and DMAPARAMS, DIRECTION;
897 mov DFCNTRL, DMAPARAMS;
898 or SXFRCTL1,BITBUCKET;
899 if ((ahc->features & AHC_DT) == 0) {
900 test SSTAT1,PHASEMIS jz .;
901 } else {
902 test SCSIPHASE, DATA_PHASE_MASK jnz .;
903 }
904 and SXFRCTL1, ~BITBUCKET;
905 mvi DATA_OVERRUN call set_seqint;
906 jmp ITloop;
907
908 data_phase_inbounds:
909 if ((ahc->features & AHC_ULTRA2) != 0) {
910 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
911 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
912 or SINDEX, LAST_SEG;
913 mov SG_CACHE_PRE, SINDEX;
914 mov DFCNTRL, DMAPARAMS;
915 ultra2_dma_loop:
916 call idle_loop;
917 /*
918 * The transfer is complete if either the last segment
919 * completes or the target changes phase.
920 */
921 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
922 if ((ahc->features & AHC_DT) == 0) {
923 if ((ahc->flags & AHC_TARGETROLE) != 0) {
924 /*
925 * As a target, we control the phases,
926 * so ignore PHASEMIS.
927 */
928 test SSTAT0, TARGET jnz ultra2_dma_loop;
929 }
930 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
931 test SSTAT1,PHASEMIS jz ultra2_dma_loop;
932 }
933 } else {
934 test DFCNTRL, SCSIEN jnz ultra2_dma_loop;
935 }
936
937 ultra2_dmafinish:
938 /*
939 * The transfer has terminated either due to a phase
940 * change, and/or the completion of the last segment.
941 * We have two goals here. Do as much other work
942 * as possible while the data fifo drains on a read
943 * and respond as quickly as possible to the standard
944 * messages (save data pointers/disconnect and command
945 * complete) that usually follow a data phase.
946 */
947 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
948 /*
949 * On chips with broken auto-flush, start
950 * the flushing process now. We'll poke
951 * the chip from time to time to keep the
952 * flush process going as we complete the
953 * data phase.
954 */
955 or DFCNTRL, FIFOFLUSH;
956 }
957 /*
958 * We assume that, even though data may still be
959 * transferring to the host, that the SCSI side of
960 * the DMA engine is now in a static state. This
961 * allows us to update our notion of where we are
962 * in this transfer.
963 *
964 * If, by chance, we stopped before being able
965 * to fetch additional segments for this transfer,
966 * yet the last S/G was completely exhausted,
967 * call our idle loop until it is able to load
968 * another segment. This will allow us to immediately
969 * pickup on the next segment on the next data phase.
970 *
971 * If we happened to stop on the last segment, then
972 * our residual information is still correct from
973 * the idle loop and there is no need to perform
974 * any fixups.
975 */
976 ultra2_ensure_sg:
977 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
978 /* Record if we've consumed all S/G entries */
979 test SSTAT2, SHVALID jnz residuals_correct;
980 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
981 jmp residuals_correct;
982
983 ultra2_shvalid:
984 test SSTAT2, SHVALID jnz sgptr_fixup;
985 call idle_loop;
986 jmp ultra2_ensure_sg;
987
988 sgptr_fixup:
989 /*
990 * Fixup the residual next S/G pointer. The S/G preload
991 * feature of the chip allows us to load two elements
992 * in addition to the currently active element. We
993 * store the bottom byte of the next S/G pointer in
994 * the SG_CACEPTR register so we can restore the
995 * correct value when the DMA completes. If the next
996 * sg ptr value has advanced to the point where higher
997 * bytes in the address have been affected, fix them
998 * too.
999 */
1000 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1001 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1002 add SCB_RESIDUAL_SGPTR[1], -1;
1003 adc SCB_RESIDUAL_SGPTR[2], -1;
1004 adc SCB_RESIDUAL_SGPTR[3], -1;
1005 sgptr_fixup_done:
1006 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1007 /* We are not the last seg */
1008 and SCB_RESIDUAL_DATACNT[3], ~SG_LAST_SEG;
1009 residuals_correct:
1010 /*
1011 * Go ahead and shut down the DMA engine now.
1012 * In the future, we'll want to handle end of
1013 * transfer messages prior to doing this, but this
1014 * requires similar restructuring for pre-ULTRA2
1015 * controllers.
1016 */
1017 test DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
1018 ultra2_fifoflush:
1019 if ((ahc->features & AHC_DT) == 0) {
1020 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
1021 /*
1022 * On Rev A of the aic7890, the autoflush
1023 * feature doesn't function correctly.
1024 * Perform an explicit manual flush. During
1025 * a manual flush, the FIFOEMP bit becomes
1026 * true every time the PCI FIFO empties
1027 * regardless of the state of the SCSI FIFO.
1028 * It can take up to 4 clock cycles for the
1029 * SCSI FIFO to get data into the PCI FIFO
1030 * and for FIFOEMP to de-assert. Here we
1031 * guard against this condition by making
1032 * sure the FIFOEMP bit stays on for 5 full
1033 * clock cycles.
1034 */
1035 or DFCNTRL, FIFOFLUSH;
1036 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1037 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1038 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1039 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1040 }
1041 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1042 } else {
1043 /*
1044 * We enable the auto-ack feature on DT capable
1045 * controllers. This means that the controller may
1046 * have already transferred some overrun bytes into
1047 * the data FIFO and acked them on the bus. The only
1048 * way to detect this situation is to wait for
1049 * LAST_SEG_DONE to come true on a completed transfer
1050 * and then test to see if the data FIFO is non-empty.
1051 */
1052 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL
1053 jz ultra2_wait_fifoemp;
1054 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1055 /*
1056 * FIFOEMP can lag LAST_SEG_DONE. Wait a few
1057 * clocks before calling this an overrun.
1058 */
1059 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1060 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1061 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1062 /* Overrun */
1063 jmp data_phase_loop;
1064 ultra2_wait_fifoemp:
1065 test DFSTATUS, FIFOEMP jz .;
1066 }
1067 ultra2_fifoempty:
1068 /* Don't clobber an inprogress host data transfer */
1069 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1070 ultra2_dmahalt:
1071 and DFCNTRL, ~(SCSIEN|HDMAEN);
1072 test DFCNTRL, SCSIEN|HDMAEN jnz .;
1073 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1074 /*
1075 * Keep HHADDR cleared for future, 32bit addressed
1076 * only, DMA operations.
1077 *
1078 * Due to bayonette style S/G handling, our residual
1079 * data must be "fixed up" once the transfer is halted.
1080 * Here we fixup the HSHADDR stored in the high byte
1081 * of the residual data cnt. By postponing the fixup,
1082 * we can batch the clearing of HADDR with the fixup.
1083 * If we halted on the last segment, the residual is
1084 * already correct. If we are not on the last
1085 * segment, copy the high address directly from HSHADDR.
1086 * We don't need to worry about maintaining the
1087 * SG_LAST_SEG flag as it will always be false in the
1088 * case where an update is required.
1089 */
1090 or DSCOMMAND1, HADDLDSEL0;
1091 test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
1092 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1093 clr HADDR;
1094 and DSCOMMAND1, ~HADDLDSEL0;
1095 }
1096 } else {
1097 /* If we are the last SG block, tell the hardware. */
1098 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1099 && ahc->pci_cachesize != 0) {
1100 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1101 }
1102 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1103 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1104 test SSTAT0, TARGET jz dma_last_sg;
1105 if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0) {
1106 test DMAPARAMS, DIRECTION jz dma_mid_sg;
1107 }
1108 }
1109 dma_last_sg:
1110 and DMAPARAMS, ~WIDEODD;
1111 dma_mid_sg:
1112 /* Start DMA data transfer. */
1113 mov DFCNTRL, DMAPARAMS;
1114 dma_loop:
1115 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1116 call idle_loop;
1117 }
1118 test SSTAT0,DMADONE jnz dma_dmadone;
1119 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
1120 dma_phasemis:
1121 /*
1122 * We will be "done" DMAing when the transfer count goes to
1123 * zero, or the target changes the phase (in light of this,
1124 * it makes sense that the DMA circuitry doesn't ACK when
1125 * PHASEMIS is active). If we are doing a SCSI->Host transfer,
1126 * the data FIFO should be flushed auto-magically on STCNT=0
1127 * or a phase change, so just wait for FIFO empty status.
1128 */
1129 dma_checkfifo:
1130 test DFCNTRL,DIRECTION jnz dma_fifoempty;
1131 dma_fifoflush:
1132 test DFSTATUS,FIFOEMP jz dma_fifoflush;
1133 dma_fifoempty:
1134 /* Don't clobber an inprogress host data transfer */
1135 test DFSTATUS, MREQPEND jnz dma_fifoempty;
1136
1137 /*
1138 * Now shut off the DMA and make sure that the DMA
1139 * hardware has actually stopped. Touching the DMA
1140 * counters, etc. while a DMA is active will result
1141 * in an ILLSADDR exception.
1142 */
1143 dma_dmadone:
1144 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1145 dma_halt:
1146 /*
1147 * Some revisions of the aic78XX have a problem where, if the
1148 * data fifo is full, but the PCI input latch is not empty,
1149 * HDMAEN cannot be cleared. The fix used here is to drain
1150 * the prefetched but unused data from the data fifo until
1151 * there is space for the input latch to drain.
1152 */
1153 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
1154 mov NONE, DFDAT;
1155 }
1156 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
1157
1158 /* See if we have completed this last segment */
1159 test STCNT[0], 0xff jnz data_phase_finish;
1160 test STCNT[1], 0xff jnz data_phase_finish;
1161 test STCNT[2], 0xff jnz data_phase_finish;
1162
1163 /*
1164 * Advance the scatter-gather pointers if needed
1165 */
1166 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1167 && ahc->pci_cachesize != 0) {
1168 test MWI_RESIDUAL, 0xFF jz no_mwi_resid;
1169 /*
1170 * Reload HADDR from SHADDR and setup the
1171 * count to be the size of our residual.
1172 */
1173 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1174 bmov HADDR, SHADDR, 4;
1175 mov HCNT, MWI_RESIDUAL;
1176 bmov HCNT[1], ALLZEROS, 2;
1177 } else {
1178 mvi DINDEX, HADDR;
1179 mvi SHADDR call bcopy_4;
1180 mov MWI_RESIDUAL call set_hcnt;
1181 }
1182 clr MWI_RESIDUAL;
1183 jmp sg_load_done;
1184 no_mwi_resid:
1185 }
1186 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
1187 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
1188 jmp data_phase_finish;
1189 sg_load:
1190 /*
1191 * Load the next SG element's data address and length
1192 * into the DMA engine. If we don't have hardware
1193 * to perform a prefetch, we'll have to fetch the
1194 * segment from host memory first.
1195 */
1196 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1197 /* Wait for the idle loop to complete */
1198 test CCSGCTL, CCSGEN jz . + 3;
1199 call idle_loop;
1200 test CCSGCTL, CCSGEN jnz . - 1;
1201 bmov HADDR, CCSGRAM, 7;
1202 /*
1203 * Workaround for flaky external SCB RAM
1204 * on certain aic7895 setups. It seems
1205 * unable to handle direct transfers from
1206 * S/G ram to certain SCB locations.
1207 */
1208 mov SINDEX, CCSGRAM;
1209 mov SCB_RESIDUAL_DATACNT[3], SINDEX;
1210 } else {
1211 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1212 mov ALLZEROS call set_hhaddr;
1213 }
1214 mvi DINDEX, HADDR;
1215 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1216
1217 mvi SG_SIZEOF call set_hcnt;
1218
1219 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1220
1221 call dma_finish;
1222
1223 mvi DINDEX, HADDR;
1224 call dfdat_in_7;
1225 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1226 }
1227
1228 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1229 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
1230
1231 /*
1232 * The lowest address byte must be loaded
1233 * last as it triggers the computation of
1234 * some items in the PCI block. The ULTRA2
1235 * chips do this on PRELOAD.
1236 */
1237 mov HADDR, HADDR;
1238 }
1239 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1240 && ahc->pci_cachesize != 0) {
1241 call calc_mwi_residual;
1242 }
1243
1244 /* Point to the new next sg in memory */
1245 call sg_advance;
1246
1247 sg_load_done:
1248 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1249 bmov STCNT, HCNT, 3;
1250 } else {
1251 call set_stcnt_from_hcnt;
1252 }
1253
1254 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1255 test SSTAT0, TARGET jnz data_phase_loop;
1256 }
1257 }
1258 data_phase_finish:
1259 /*
1260 * If the target has left us in data phase, loop through
1261 * the dma code again. In the case of ULTRA2 adapters,
1262 * we should only loop if there is a data overrun. For
1263 * all other adapters, we'll loop after each S/G element
1264 * is loaded as well as if there is an overrun.
1265 */
1266 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1267 test SSTAT0, TARGET jnz data_phase_done;
1268 }
1269 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1270 test SSTAT1, REQINIT jz .;
1271 if ((ahc->features & AHC_DT) == 0) {
1272 test SSTAT1,PHASEMIS jz data_phase_loop;
1273 } else {
1274 test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
1275 }
1276 }
1277
1278 data_phase_done:
1279 /*
1280 * After a DMA finishes, save the SG and STCNT residuals back into
1281 * the SCB. We use STCNT instead of HCNT, since it's a reflection
1282 * of how many bytes were transferred on the SCSI (as opposed to the
1283 * host) bus.
1284 */
1285 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1286 /* Kill off any pending prefetch */
1287 call disable_ccsgen;
1288 }
1289
1290 if ((ahc->features & AHC_ULTRA2) == 0) {
1291 /*
1292 * Clear the high address byte so that all other DMA
1293 * operations, which use 32bit addressing, can assume
1294 * HHADDR is 0.
1295 */
1296 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1297 mov ALLZEROS call set_hhaddr;
1298 }
1299 }
1300
1301 /*
1302 * Update our residual information before the information is
1303 * lost by some other type of SCSI I/O (e.g. PIO). If we have
1304 * transferred all data, no update is needed.
1305 *
1306 */
1307 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
1308 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1309 && ahc->pci_cachesize != 0) {
1310 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1311 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1312 }
1313 mov A, MWI_RESIDUAL;
1314 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1315 clr A;
1316 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
1317 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
1318 clr MWI_RESIDUAL;
1319 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1320 jmp . + 2;
1321 bmov_resid:
1322 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1323 }
1324 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1325 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1326 } else {
1327 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1328 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1329 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1330 }
1331 residual_update_done:
1332 /*
1333 * Since we've been through a data phase, the SCB_RESID* fields
1334 * are now initialized. Clear the full residual flag.
1335 */
1336 and SCB_SGPTR[0], ~SG_FULL_RESID;
1337
1338 if ((ahc->features & AHC_ULTRA2) != 0) {
1339 /* Clear the channel in case we return to data phase later */
1340 or SXFRCTL0, CLRSTCNT|CLRCHN;
1341 or SXFRCTL0, CLRSTCNT|CLRCHN;
1342 }
1343
1344 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1345 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1346 and SEQ_FLAGS, ~DPHASE_PENDING;
1347 /*
1348 * For data-in phases, wait for any pending acks from the
1349 * initiator before changing phase. We only need to
1350 * send Ignore Wide Residue messages for data-in phases.
1351 */
1352 test DFCNTRL, DIRECTION jz target_ITloop;
1353 test SSTAT1, REQINIT jnz .;
1354 test SCB_LUN, SCB_XFERLEN_ODD jz target_ITloop;
1355 test SCSIRATE, WIDEXFER jz target_ITloop;
1356 /*
1357 * Issue an Ignore Wide Residue Message.
1358 */
1359 mvi P_MESGIN|BSYO call change_phase;
1360 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1361 mvi 1 call target_outb;
1362 jmp target_ITloop;
1363 } else {
1364 jmp ITloop;
1365 }
1366
1367 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1368 /*
1369 * Command phase. Set up the DMA registers and let 'er rip.
1370 */
1371 p_command:
1372 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
1373 mvi PROTO_VIOLATION call set_seqint;
1374 p_command_okay:
1375
1376 if ((ahc->features & AHC_ULTRA2) != 0) {
1377 bmov HCNT[0], SCB_CDB_LEN, 1;
1378 bmov HCNT[1], ALLZEROS, 2;
1379 mvi SG_CACHE_PRE, LAST_SEG;
1380 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1381 bmov STCNT[0], SCB_CDB_LEN, 1;
1382 bmov STCNT[1], ALLZEROS, 2;
1383 } else {
1384 mov STCNT[0], SCB_CDB_LEN;
1385 clr STCNT[1];
1386 clr STCNT[2];
1387 }
1388 add NONE, -13, SCB_CDB_LEN;
1389 mvi SCB_CDB_STORE jnc p_command_embedded;
1390 p_command_from_host:
1391 if ((ahc->features & AHC_ULTRA2) != 0) {
1392 bmov HADDR[0], SCB_CDB_PTR, 4;
1393 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
1394 } else {
1395 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1396 bmov HADDR[0], SCB_CDB_PTR, 4;
1397 bmov HCNT, STCNT, 3;
1398 } else {
1399 mvi DINDEX, HADDR;
1400 mvi SCB_CDB_PTR call bcopy_4;
1401 mov SCB_CDB_LEN call set_hcnt;
1402 }
1403 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
1404 }
1405 jmp p_command_xfer;
1406 p_command_embedded:
1407 /*
1408 * The data fifo seems to require 4 byte aligned
1409 * transfers from the sequencer. Force this to
1410 * be the case by clearing HADDR[0] even though
1411 * we aren't going to touch host memory.
1412 */
1413 clr HADDR[0];
1414 if ((ahc->features & AHC_ULTRA2) != 0) {
1415 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
1416 bmov DFDAT, SCB_CDB_STORE, 12;
1417 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1418 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1419 /*
1420 * On the 7895 the data FIFO will
1421 * get corrupted if you try to dump
1422 * data from external SCB memory into
1423 * the FIFO while it is enabled. So,
1424 * fill the fifo and then enable SCSI
1425 * transfers.
1426 */
1427 mvi DFCNTRL, (DIRECTION|FIFORESET);
1428 } else {
1429 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1430 }
1431 bmov DFDAT, SCB_CDB_STORE, 12;
1432 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1433 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
1434 } else {
1435 or DFCNTRL, FIFOFLUSH;
1436 }
1437 } else {
1438 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1439 call copy_to_fifo_6;
1440 call copy_to_fifo_6;
1441 or DFCNTRL, FIFOFLUSH;
1442 }
1443 p_command_xfer:
1444 and SEQ_FLAGS, ~NO_CDB_SENT;
1445 if ((ahc->features & AHC_DT) == 0) {
1446 test SSTAT0, SDONE jnz . + 2;
1447 test SSTAT1, PHASEMIS jz . - 1;
1448 /*
1449 * Wait for our ACK to go-away on it's own
1450 * instead of being killed by SCSIEN getting cleared.
1451 */
1452 test SCSISIGI, ACKI jnz .;
1453 } else {
1454 test DFCNTRL, SCSIEN jnz .;
1455 }
1456 test SSTAT0, SDONE jnz p_command_successful;
1457 /*
1458 * Don't allow a data phase if the command
1459 * was not fully transferred.
1460 */
1461 or SEQ_FLAGS, NO_CDB_SENT;
1462 p_command_successful:
1463 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1464 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
1465 jmp ITloop;
1466
1467 /*
1468 * Status phase. Wait for the data byte to appear, then read it
1469 * and store it into the SCB.
1470 */
1471 p_status:
1472 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1473 p_status_okay:
1474 mov SCB_SCSI_STATUS, SCSIDATL;
1475 or SCB_CONTROL, STATUS_RCVD;
1476 jmp ITloop;
1477
1478 /*
1479 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1480 * indentify message sequence and send it to the target. The host may
1481 * override this behavior by setting the MK_MESSAGE bit in the SCB
1482 * control byte. This will cause us to interrupt the host and allow
1483 * it to handle the message phase completely on its own. If the bit
1484 * associated with this target is set, we will also interrupt the host,
1485 * thereby allowing it to send a message on the next selection regardless
1486 * of the transaction being sent.
1487 *
1488 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
1489 * This is done to allow the host to send messages outside of an identify
1490 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
1491 * on an SCB that might not be for the current nexus. (For example, a
1492 * BDR message in responce to a bad reselection would leave us pointed to
1493 * an SCB that doesn't have anything to do with the current target).
1494 *
1495 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
1496 * bus device reset).
1497 *
1498 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
1499 * in case the target decides to put us in this phase for some strange
1500 * reason.
1501 */
1502 p_mesgout_retry:
1503 /* Turn on ATN for the retry */
1504 if ((ahc->features & AHC_DT) == 0) {
1505 or SCSISIGO, ATNO, LASTPHASE;
1506 } else {
1507 mvi SCSISIGO, ATNO;
1508 }
1509 p_mesgout:
1510 mov SINDEX, MSG_OUT;
1511 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
1512 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
1513 p_mesgout_identify:
1514 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SAVED_LUN;
1515 test SCB_CONTROL, DISCENB jnz . + 2;
1516 and SINDEX, ~DISCENB;
1517 /*
1518 * Send a tag message if TAG_ENB is set in the SCB control block.
1519 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
1520 */
1521 p_mesgout_tag:
1522 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
1523 mov SCSIDATL, SINDEX; /* Send the identify message */
1524 call phase_lock;
1525 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1526 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
1527 call phase_lock;
1528 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1529 mov SCB_TAG jmp p_mesgout_onebyte;
1530 /*
1531 * Interrupt the driver, and allow it to handle this message
1532 * phase and any required retries.
1533 */
1534 p_mesgout_from_host:
1535 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
1536 jmp host_message_loop;
1537
1538 p_mesgout_onebyte:
1539 mvi CLRSINT1, CLRATNO;
1540 mov SCSIDATL, SINDEX;
1541
1542 /*
1543 * If the next bus phase after ATN drops is message out, it means
1544 * that the target is requesting that the last message(s) be resent.
1545 */
1546 call phase_lock;
1547 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
1548
1549 p_mesgout_done:
1550 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
1551 mov LAST_MSG, MSG_OUT;
1552 mvi MSG_OUT, MSG_NOOP; /* No message left */
1553 jmp ITloop;
1554
1555 /*
1556 * Message in phase. Bytes are read using Automatic PIO mode.
1557 */
1558 p_mesgin:
1559 mvi ACCUM call inb_first; /* read the 1st message byte */
1560
1561 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
1562 cmp A,MSG_DISCONNECT je mesgin_disconnect;
1563 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
1564 cmp ALLZEROS,A je mesgin_complete;
1565 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
1566 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
1567 cmp A,MSG_NOOP je mesgin_done;
1568
1569 /*
1570 * Pushed message loop to allow the kernel to
1571 * run it's own message state engine. To avoid an
1572 * extra nop instruction after signaling the kernel,
1573 * we perform the phase_lock before checking to see
1574 * if we should exit the loop and skip the phase_lock
1575 * in the ITloop. Performing back to back phase_locks
1576 * shouldn't hurt, but why do it twice...
1577 */
1578 host_message_loop:
1579 mvi HOST_MSG_LOOP call set_seqint;
1580 call phase_lock;
1581 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
1582 jmp host_message_loop;
1583
1584 mesgin_ign_wide_residue:
1585 if ((ahc->features & AHC_WIDE) != 0) {
1586 test SCSIRATE, WIDEXFER jz mesgin_reject;
1587 /* Pull the residue byte */
1588 mvi ARG_1 call inb_next;
1589 cmp ARG_1, 0x01 jne mesgin_reject;
1590 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
1591 test SCB_LUN, SCB_XFERLEN_ODD jnz mesgin_done;
1592 mvi IGN_WIDE_RES call set_seqint;
1593 jmp mesgin_done;
1594 }
1595
1596 mesgin_proto_violation:
1597 mvi PROTO_VIOLATION call set_seqint;
1598 jmp mesgin_done;
1599 mesgin_reject:
1600 mvi MSG_MESSAGE_REJECT call mk_mesg;
1601 mesgin_done:
1602 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1603 jmp ITloop;
1604
1605 /*
1606 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO,
1607 * and trigger a completion interrupt. Before doing so, check to see if there
1608 * is a residual or the status byte is something other than STATUS_GOOD (0).
1609 * In either of these conditions, we upload the SCB back to the host so it can
1610 * process this information. In the case of a non zero status byte, we
1611 * additionally interrupt the kernel driver synchronously, allowing it to
1612 * decide if sense should be retrieved. If the kernel driver wishes to request
1613 * sense, it will fill the kernel SCB with a request sense command, requeue
1614 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
1615 * RETURN_1 to SEND_SENSE.
1616 */
1617 mesgin_complete:
1618
1619 /*
1620 * If ATN is raised, we still want to give the target a message.
1621 * Perhaps there was a parity error on this last message byte.
1622 * Either way, the target should take us to message out phase
1623 * and then attempt to complete the command again. We should use a
1624 * critical section here to guard against a timeout triggering
1625 * for this command and setting ATN while we are still processing
1626 * the completion.
1627 test SCSISIGI, ATNI jnz mesgin_done;
1628 */
1629
1630 /*
1631 * If we are identified and have successfully sent the CDB,
1632 * any status will do. Optimize this fast path.
1633 */
1634 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1635 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1636
1637 /*
1638 * If the target never sent an identify message but instead went
1639 * to mesgin to give an invalid message, let the host abort us.
1640 */
1641 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1642
1643 /*
1644 * If we recevied good status but never successfully sent the
1645 * cdb, abort the command.
1646 */
1647 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1648 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1649
1650 complete_accepted:
1651 /*
1652 * See if we attempted to deliver a message but the target ingnored us.
1653 */
1654 test SCB_CONTROL, MK_MESSAGE jz . + 2;
1655 mvi MKMSG_FAILED call set_seqint;
1656
1657 /*
1658 * Check for residuals
1659 */
1660 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
1661 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1662 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1663 check_status:
1664 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */
1665 upload_scb:
1666 or SCB_SGPTR, SG_RESID_VALID;
1667 mvi DMAPARAMS, FIFORESET;
1668 mov SCB_TAG call dma_scb;
1669 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */
1670 mvi BAD_STATUS call set_seqint; /* let driver know */
1671 cmp RETURN_1, SEND_SENSE jne complete;
1672 call add_scb_to_free_list;
1673 jmp await_busfree;
1674 complete:
1675 mov SCB_TAG call complete_post;
1676 jmp await_busfree;
1677 }
1678
1679 complete_post:
1680 /* Post the SCBID in SINDEX and issue an interrupt */
1681 call add_scb_to_free_list;
1682 mov ARG_1, SINDEX;
1683 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
1684 mov A, SDSCB_QOFF;
1685 } else {
1686 mov A, QOUTPOS;
1687 }
1688 mvi QOUTFIFO_OFFSET call post_byte_setup;
1689 mov ARG_1 call post_byte;
1690 if ((ahc->features & AHC_QUEUE_REGS) == 0) {
1691 inc QOUTPOS;
1692 }
1693 mvi INTSTAT,CMDCMPLT ret;
1694
1695 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1696 /*
1697 * Is it a disconnect message? Set a flag in the SCB to remind us
1698 * and await the bus going free. If this is an untagged transaction
1699 * store the SCB id for it in our untagged target table for lookup on
1700 * a reselction.
1701 */
1702 mesgin_disconnect:
1703 /*
1704 * If ATN is raised, we still want to give the target a message.
1705 * Perhaps there was a parity error on this last message byte
1706 * or we want to abort this command. Either way, the target
1707 * should take us to message out phase and then attempt to
1708 * disconnect again.
1709 * XXX - Wait for more testing.
1710 test SCSISIGI, ATNI jnz mesgin_done;
1711 */
1712 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1713 jnz mesgin_proto_violation;
1714 or SCB_CONTROL,DISCONNECTED;
1715 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1716 call add_scb_to_disc_list;
1717 }
1718 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1719 mov ARG_1, SCB_TAG;
1720 and SAVED_LUN, LID, SCB_LUN;
1721 mov SCB_SCSIID call set_busy_target;
1722 jmp await_busfree;
1723
1724 /*
1725 * Save data pointers message:
1726 * Copying RAM values back to SCB, for Save Data Pointers message, but
1727 * only if we've actually been into a data phase to change them. This
1728 * protects against bogus data in scratch ram and the residual counts
1729 * since they are only initialized when we go into data_in or data_out.
1730 * Ack the message as soon as possible. For chips without S/G pipelining,
1731 * we can only ack the message after SHADDR has been saved. On these
1732 * chips, SHADDR increments with every bus transaction, even PIO.
1733 */
1734 mesgin_sdptrs:
1735 if ((ahc->features & AHC_ULTRA2) != 0) {
1736 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1737 test SEQ_FLAGS, DPHASE jz ITloop;
1738 } else {
1739 test SEQ_FLAGS, DPHASE jz mesgin_done;
1740 }
1741
1742 /*
1743 * If we are asked to save our position at the end of the
1744 * transfer, just mark us at the end rather than perform a
1745 * full save.
1746 */
1747 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
1748 or SCB_SGPTR, SG_LIST_NULL;
1749 if ((ahc->features & AHC_ULTRA2) != 0) {
1750 jmp ITloop;
1751 } else {
1752 jmp mesgin_done;
1753 }
1754
1755 mesgin_sdptrs_full:
1756
1757 /*
1758 * The SCB_SGPTR becomes the next one we'll download,
1759 * and the SCB_DATAPTR becomes the current SHADDR.
1760 * Use the residual number since STCNT is corrupted by
1761 * any message transfer.
1762 */
1763 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1764 bmov SCB_DATAPTR, SHADDR, 4;
1765 if ((ahc->features & AHC_ULTRA2) == 0) {
1766 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1767 }
1768 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8;
1769 } else {
1770 mvi DINDEX, SCB_DATAPTR;
1771 mvi SHADDR call bcopy_4;
1772 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1773 mvi SCB_RESIDUAL_DATACNT call bcopy_8;
1774 }
1775 jmp ITloop;
1776
1777 /*
1778 * Restore pointers message? Data pointers are recopied from the
1779 * SCB anytime we enter a data phase for the first time, so all
1780 * we need to do is clear the DPHASE flag and let the data phase
1781 * code do the rest. We also reset/reallocate the FIFO to make
1782 * sure we have a clean start for the next data or command phase.
1783 */
1784 mesgin_rdptrs:
1785 and SEQ_FLAGS, ~DPHASE; /*
1786 * We'll reload them
1787 * the next time through
1788 * the dataphase.
1789 */
1790 or SXFRCTL0, CLRSTCNT|CLRCHN;
1791 jmp mesgin_done;
1792
1793 /*
1794 * Index into our Busy Target table. SINDEX and DINDEX are modified
1795 * upon return. SCBPTR may be modified by this action.
1796 */
1797 set_busy_target:
1798 shr DINDEX, 4, SINDEX;
1799 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1800 mov SCBPTR, SAVED_LUN;
1801 add DINDEX, SCB_64_BTT;
1802 } else {
1803 add DINDEX, BUSY_TARGETS;
1804 }
1805 mov DINDIR, ARG_1 ret;
1806
1807 /*
1808 * Identify message? For a reconnecting target, this tells us the lun
1809 * that the reconnection is for - find the correct SCB and switch to it,
1810 * clearing the "disconnected" bit so we don't "find" it by accident later.
1811 */
1812 mesgin_identify:
1813 /*
1814 * Determine whether a target is using tagged or non-tagged
1815 * transactions by first looking at the transaction stored in
1816 * the busy target array. If there is no untagged transaction
1817 * for this target or the transaction is for a different lun, then
1818 * this must be a tagged transaction.
1819 */
1820 shr SINDEX, 4, SAVED_SCSIID;
1821 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1822 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1823 add SINDEX, SCB_64_BTT;
1824 mov SCBPTR, SAVED_LUN;
1825 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1826 add NONE, -SCB_64_BTT, SINDEX;
1827 jc . + 2;
1828 mvi INTSTAT, OUT_OF_RANGE;
1829 nop;
1830 add NONE, -(SCB_64_BTT + 16), SINDEX;
1831 jnc . + 2;
1832 mvi INTSTAT, OUT_OF_RANGE;
1833 nop;
1834 }
1835 } else {
1836 add SINDEX, BUSY_TARGETS;
1837 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1838 add NONE, -BUSY_TARGETS, SINDEX;
1839 jc . + 2;
1840 mvi INTSTAT, OUT_OF_RANGE;
1841 nop;
1842 add NONE, -(BUSY_TARGETS + 16), SINDEX;
1843 jnc . + 2;
1844 mvi INTSTAT, OUT_OF_RANGE;
1845 nop;
1846 }
1847 }
1848 mov ARG_1, SINDIR;
1849 cmp ARG_1, SCB_LIST_NULL je snoop_tag;
1850 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1851 mov ARG_1 call findSCB;
1852 } else {
1853 mov SCBPTR, ARG_1;
1854 }
1855 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1856 jmp setup_SCB_id_lun_okay;
1857 } else {
1858 /*
1859 * We only allow one untagged command per-target
1860 * at a time. So, if the lun doesn't match, look
1861 * for a tag message.
1862 */
1863 and A, LID, SCB_LUN;
1864 cmp SAVED_LUN, A je setup_SCB_id_lun_okay;
1865 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1866 /*
1867 * findSCB removes the SCB from the
1868 * disconnected list, so we must replace
1869 * it there should this SCB be for another
1870 * lun.
1871 */
1872 call cleanup_scb;
1873 }
1874 }
1875
1876 /*
1877 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1878 * If we get one, we use the tag returned to find the proper
1879 * SCB. With SCB paging, we must search for non-tagged
1880 * transactions since the SCB may exist in any slot. If we're not
1881 * using SCB paging, we can use the tag as the direct index to the
1882 * SCB.
1883 */
1884 snoop_tag:
1885 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1886 or SEQ_FLAGS, 0x80;
1887 }
1888 mov NONE,SCSIDATL; /* ACK Identify MSG */
1889 call phase_lock;
1890 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1891 or SEQ_FLAGS, 0x1;
1892 }
1893 cmp LASTPHASE, P_MESGIN jne not_found;
1894 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1895 or SEQ_FLAGS, 0x2;
1896 }
1897 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
1898 get_tag:
1899 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1900 mvi ARG_1 call inb_next; /* tag value */
1901 mov ARG_1 call findSCB;
1902 } else {
1903 mvi ARG_1 call inb_next; /* tag value */
1904 mov SCBPTR, ARG_1;
1905 }
1906
1907 /*
1908 * Ensure that the SCB the tag points to is for
1909 * an SCB transaction to the reconnecting target.
1910 */
1911 setup_SCB:
1912 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1913 or SEQ_FLAGS, 0x4;
1914 }
1915 mov A, SCB_SCSIID;
1916 cmp SAVED_SCSIID, A jne not_found_cleanup_scb;
1917 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1918 or SEQ_FLAGS, 0x8;
1919 }
1920 setup_SCB_id_okay:
1921 and A, LID, SCB_LUN;
1922 cmp SAVED_LUN, A jne not_found_cleanup_scb;
1923 setup_SCB_id_lun_okay:
1924 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1925 or SEQ_FLAGS, 0x10;
1926 }
1927 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
1928 and SCB_CONTROL,~DISCONNECTED;
1929 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged;
1930 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1931 mov A, SCBPTR;
1932 }
1933 mvi ARG_1, SCB_LIST_NULL;
1934 mov SAVED_SCSIID call set_busy_target;
1935 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1936 mov SCBPTR, A;
1937 }
1938 setup_SCB_tagged:
1939 clr SEQ_FLAGS; /* make note of IDENTIFY */
1940 call set_transfer_settings;
1941 /* See if the host wants to send a message upon reconnection */
1942 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1943 mvi HOST_MSG call mk_mesg;
1944 jmp mesgin_done;
1945
1946 not_found_cleanup_scb:
1947 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1948 call cleanup_scb;
1949 }
1950 not_found:
1951 mvi NO_MATCH call set_seqint;
1952 jmp mesgin_done;
1953
1954 mk_mesg:
1955 if ((ahc->features & AHC_DT) == 0) {
1956 or SCSISIGO, ATNO, LASTPHASE;
1957 } else {
1958 mvi SCSISIGO, ATNO;
1959 }
1960 mov MSG_OUT,SINDEX ret;
1961
1962 /*
1963 * Functions to read data in Automatic PIO mode.
1964 *
1965 * According to Adaptec's documentation, an ACK is not sent on input from
1966 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1967 * latched (the usual way), then read the data byte directly off the bus
1968 * using SCSIBUSL. When we have pulled the ATN line, or we just want to
1969 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
1970 * spec guarantees that the target will hold the data byte on the bus until
1971 * we send our ACK.
1972 *
1973 * The assumption here is that these are called in a particular sequence,
1974 * and that REQ is already set when inb_first is called. inb_{first,next}
1975 * use the same calling convention as inb.
1976 */
1977 inb_next_wait_perr:
1978 mvi PERR_DETECTED call set_seqint;
1979 jmp inb_next_wait;
1980 inb_next:
1981 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1982 inb_next_wait:
1983 /*
1984 * If there is a parity error, wait for the kernel to
1985 * see the interrupt and prepare our message response
1986 * before continuing.
1987 */
1988 test SSTAT1, REQINIT jz inb_next_wait;
1989 test SSTAT1, SCSIPERR jnz inb_next_wait_perr;
1990 inb_next_check_phase:
1991 and LASTPHASE, PHASE_MASK, SCSISIGI;
1992 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1993 inb_first:
1994 mov DINDEX,SINDEX;
1995 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
1996 inb_last:
1997 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
1998 }
1999
2000 if ((ahc->flags & AHC_TARGETROLE) != 0) {
2001 /*
2002 * Change to a new phase. If we are changing the state of the I/O signal,
2003 * from out to in, wait an additional data release delay before continuing.
2004 */
2005 change_phase:
2006 /* Wait for preceding I/O session to complete. */
2007 test SCSISIGI, ACKI jnz .;
2008
2009 /* Change the phase */
2010 and DINDEX, IOI, SCSISIGI;
2011 mov SCSISIGO, SINDEX;
2012 and A, IOI, SINDEX;
2013
2014 /*
2015 * If the data direction has changed, from
2016 * out (initiator driving) to in (target driving),
2017 * we must wait at least a data release delay plus
2018 * the normal bus settle delay. [SCSI III SPI 10.11.0]
2019 */
2020 cmp DINDEX, A je change_phase_wait;
2021 test SINDEX, IOI jz change_phase_wait;
2022 call change_phase_wait;
2023 change_phase_wait:
2024 nop;
2025 nop;
2026 nop;
2027 nop ret;
2028
2029 /*
2030 * Send a byte to an initiator in Automatic PIO mode.
2031 */
2032 target_outb:
2033 or SXFRCTL0, SPIOEN;
2034 test SSTAT0, SPIORDY jz .;
2035 mov SCSIDATL, SINDEX;
2036 test SSTAT0, SPIORDY jz .;
2037 and SXFRCTL0, ~SPIOEN ret;
2038 }
2039
2040 /*
2041 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
2042 * be set to the position of the SCB. If the SCB cannot be found locally,
2043 * it will be paged in from host memory. RETURN_2 stores the address of the
2044 * preceding SCB in the disconnected list which can be used to speed up
2045 * removal of the found SCB from the disconnected list.
2046 */
2047 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2048 BEGIN_CRITICAL;
2049 findSCB:
2050 mov A, SINDEX; /* Tag passed in SINDEX */
2051 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound;
2052 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */
2053 mvi ARG_2, SCB_LIST_NULL; /* Head of list */
2054 jmp findSCB_loop;
2055 findSCB_next:
2056 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound;
2057 mov ARG_2, SCBPTR;
2058 mov SCBPTR,SCB_NEXT;
2059 findSCB_loop:
2060 cmp SCB_TAG, A jne findSCB_next;
2061 rem_scb_from_disc_list:
2062 cmp ARG_2, SCB_LIST_NULL je rHead;
2063 mov DINDEX, SCB_NEXT;
2064 mov SINDEX, SCBPTR;
2065 mov SCBPTR, ARG_2;
2066 mov SCB_NEXT, DINDEX;
2067 mov SCBPTR, SINDEX ret;
2068 rHead:
2069 mov DISCONNECTED_SCBH,SCB_NEXT ret;
2070 END_CRITICAL;
2071 findSCB_notFound:
2072 /*
2073 * We didn't find it. Page in the SCB.
2074 */
2075 mov ARG_1, A; /* Save tag */
2076 mov ALLZEROS call get_free_or_disc_scb;
2077 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
2078 mov ARG_1 jmp dma_scb;
2079 }
2080
2081 /*
2082 * Prepare the hardware to post a byte to host memory given an
2083 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR.
2084 */
2085 post_byte_setup:
2086 mov ARG_2, SINDEX;
2087 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2088 mvi DINDEX, CCHADDR;
2089 mvi SHARED_DATA_ADDR call set_1byte_addr;
2090 mvi CCHCNT, 1;
2091 mvi CCSCBCTL, CCSCBRESET ret;
2092 } else {
2093 mvi DINDEX, HADDR;
2094 mvi SHARED_DATA_ADDR call set_1byte_addr;
2095 mvi 1 call set_hcnt;
2096 mvi DFCNTRL, FIFORESET ret;
2097 }
2098
2099 post_byte:
2100 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2101 bmov CCSCBRAM, SINDEX, 1;
2102 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2103 test CCSCBCTL, CCSCBDONE jz .;
2104 clr CCSCBCTL ret;
2105 } else {
2106 mov DFDAT, SINDEX;
2107 or DFCNTRL, HDMAEN|FIFOFLUSH;
2108 jmp dma_finish;
2109 }
2110
2111 phase_lock_perr:
2112 mvi PERR_DETECTED call set_seqint;
2113 phase_lock:
2114 /*
2115 * If there is a parity error, wait for the kernel to
2116 * see the interrupt and prepare our message response
2117 * before continuing.
2118 */
2119 test SSTAT1, REQINIT jz phase_lock;
2120 test SSTAT1, SCSIPERR jnz phase_lock_perr;
2121 phase_lock_latch_phase:
2122 if ((ahc->features & AHC_DT) == 0) {
2123 and SCSISIGO, PHASE_MASK, SCSISIGI;
2124 }
2125 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
2126
2127 if ((ahc->features & AHC_CMD_CHAN) == 0) {
2128 set_hcnt:
2129 mov HCNT[0], SINDEX;
2130 clear_hcnt:
2131 clr HCNT[1];
2132 clr HCNT[2] ret;
2133
2134 set_stcnt_from_hcnt:
2135 mov STCNT[0], HCNT[0];
2136 mov STCNT[1], HCNT[1];
2137 mov STCNT[2], HCNT[2] ret;
2138
2139 bcopy_8:
2140 mov DINDIR, SINDIR;
2141 bcopy_7:
2142 mov DINDIR, SINDIR;
2143 mov DINDIR, SINDIR;
2144 bcopy_5:
2145 mov DINDIR, SINDIR;
2146 bcopy_4:
2147 mov DINDIR, SINDIR;
2148 bcopy_3:
2149 mov DINDIR, SINDIR;
2150 mov DINDIR, SINDIR;
2151 mov DINDIR, SINDIR ret;
2152 }
2153
2154 if ((ahc->flags & AHC_TARGETROLE) != 0) {
2155 /*
2156 * Setup addr assuming that A is an index into
2157 * an array of 32byte objects, SINDEX contains
2158 * the base address of that array, and DINDEX
2159 * contains the base address of the location
2160 * to store the indexed address.
2161 */
2162 set_32byte_addr:
2163 shr ARG_2, 3, A;
2164 shl A, 5;
2165 jmp set_1byte_addr;
2166 }
2167
2168 /*
2169 * Setup addr assuming that A is an index into
2170 * an array of 64byte objects, SINDEX contains
2171 * the base address of that array, and DINDEX
2172 * contains the base address of the location
2173 * to store the indexed address.
2174 */
2175 set_64byte_addr:
2176 shr ARG_2, 2, A;
2177 shl A, 6;
2178
2179 /*
2180 * Setup addr assuming that A + (ARG_2 * 256) is an
2181 * index into an array of 1byte objects, SINDEX contains
2182 * the base address of that array, and DINDEX contains
2183 * the base address of the location to store the computed
2184 * address.
2185 */
2186 set_1byte_addr:
2187 add DINDIR, A, SINDIR;
2188 mov A, ARG_2;
2189 adc DINDIR, A, SINDIR;
2190 clr A;
2191 adc DINDIR, A, SINDIR;
2192 adc DINDIR, A, SINDIR ret;
2193
2194 /*
2195 * Either post or fetch an SCB from host memory based on the
2196 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX.
2197 */
2198 dma_scb:
2199 mov A, SINDEX;
2200 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2201 mvi DINDEX, CCHADDR;
2202 mvi HSCB_ADDR call set_64byte_addr;
2203 mov CCSCBPTR, SCBPTR;
2204 test DMAPARAMS, DIRECTION jz dma_scb_tohost;
2205 if ((ahc->flags & AHC_SCB_BTT) != 0) {
2206 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64;
2207 } else {
2208 mvi CCHCNT, SCB_DOWNLOAD_SIZE;
2209 }
2210 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
2211 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
2212 jmp dma_scb_finish;
2213 dma_scb_tohost:
2214 mvi CCHCNT, SCB_UPLOAD_SIZE;
2215 if ((ahc->features & AHC_ULTRA2) == 0) {
2216 mvi CCSCBCTL, CCSCBRESET;
2217 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE;
2218 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2219 test CCSCBCTL, CCSCBDONE jz .;
2220 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
2221 mvi CCSCBCTL, CCARREN|CCSCBRESET;
2222 cmp CCSCBCTL, ARRDONE|CCARREN jne .;
2223 mvi CCHCNT, SCB_UPLOAD_SIZE;
2224 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
2225 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
2226 } else {
2227 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
2228 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
2229 }
2230 dma_scb_finish:
2231 clr CCSCBCTL;
2232 test CCSCBCTL, CCARREN|CCSCBEN jnz .;
2233 ret;
2234 } else {
2235 mvi DINDEX, HADDR;
2236 mvi HSCB_ADDR call set_64byte_addr;
2237 mvi SCB_DOWNLOAD_SIZE call set_hcnt;
2238 mov DFCNTRL, DMAPARAMS;
2239 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost;
2240 /* Fill it with the SCB data */
2241 copy_scb_tofifo:
2242 mvi SINDEX, SCB_BASE;
2243 add A, SCB_DOWNLOAD_SIZE, SINDEX;
2244 copy_scb_tofifo_loop:
2245 call copy_to_fifo_8;
2246 cmp SINDEX, A jne copy_scb_tofifo_loop;
2247 or DFCNTRL, HDMAEN|FIFOFLUSH;
2248 jmp dma_finish;
2249 dma_scb_fromhost:
2250 mvi DINDEX, SCB_BASE;
2251 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
2252 /*
2253 * The PCI module will only issue a PCI
2254 * retry if the data FIFO is empty. If the
2255 * host disconnects in the middle of a
2256 * transfer, we must empty the fifo of all
2257 * available data to force the chip to
2258 * continue the transfer. This does not
2259 * happen for SCSI transfers as the SCSI module
2260 * will drain the FIFO as data are made available.
2261 * When the hang occurs, we know that a multiple
2262 * of 8 bytes is in the FIFO because the PCI
2263 * module has an 8 byte input latch that only
2264 * dumps to the FIFO when HCNT == 0 or the
2265 * latch is full.
2266 */
2267 clr A;
2268 /* Wait for at least 8 bytes of data to arrive. */
2269 dma_scb_hang_fifo:
2270 test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
2271 dma_scb_hang_wait:
2272 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait;
2273 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2274 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2275 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2276 /*
2277 * The PCI module no longer intends to perform
2278 * a PCI transaction. Drain the fifo.
2279 */
2280 dma_scb_hang_dma_drain_fifo:
2281 not A, HCNT;
2282 add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1;
2283 and A, ~0x7;
2284 mov DINDIR,DFDAT;
2285 cmp DINDEX, A jne . - 1;
2286 cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE
2287 je dma_finish_nowait;
2288 /* Restore A as the lines left to transfer. */
2289 add A, -SCB_BASE, DINDEX;
2290 shr A, 3;
2291 jmp dma_scb_hang_fifo;
2292 dma_scb_hang_dma_done:
2293 and DFCNTRL, ~HDMAEN;
2294 test DFCNTRL, HDMAEN jnz .;
2295 add SEQADDR0, A;
2296 } else {
2297 call dma_finish;
2298 }
2299 call dfdat_in_8;
2300 call dfdat_in_8;
2301 call dfdat_in_8;
2302 dfdat_in_8:
2303 mov DINDIR,DFDAT;
2304 dfdat_in_7:
2305 mov DINDIR,DFDAT;
2306 mov DINDIR,DFDAT;
2307 mov DINDIR,DFDAT;
2308 mov DINDIR,DFDAT;
2309 mov DINDIR,DFDAT;
2310 dfdat_in_2:
2311 mov DINDIR,DFDAT;
2312 mov DINDIR,DFDAT ret;
2313 }
2314
2315 copy_to_fifo_8:
2316 mov DFDAT,SINDIR;
2317 mov DFDAT,SINDIR;
2318 copy_to_fifo_6:
2319 mov DFDAT,SINDIR;
2320 copy_to_fifo_5:
2321 mov DFDAT,SINDIR;
2322 copy_to_fifo_4:
2323 mov DFDAT,SINDIR;
2324 mov DFDAT,SINDIR;
2325 mov DFDAT,SINDIR;
2326 mov DFDAT,SINDIR ret;
2327
2328 /*
2329 * Wait for DMA from host memory to data FIFO to complete, then disable
2330 * DMA and wait for it to acknowledge that it's off.
2331 */
2332 dma_finish:
2333 test DFSTATUS,HDONE jz dma_finish;
2334 dma_finish_nowait:
2335 /* Turn off DMA */
2336 and DFCNTRL, ~HDMAEN;
2337 test DFCNTRL, HDMAEN jnz .;
2338 ret;
2339
2340 /*
2341 * Restore an SCB that failed to match an incoming reselection
2342 * to the correct/safe state. If the SCB is for a disconnected
2343 * transaction, it must be returned to the disconnected list.
2344 * If it is not in the disconnected state, it must be free.
2345 */
2346 cleanup_scb:
2347 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2348 test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list;
2349 }
2350 add_scb_to_free_list:
2351 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2352 BEGIN_CRITICAL;
2353 mov SCB_NEXT, FREE_SCBH;
2354 mvi SCB_TAG, SCB_LIST_NULL;
2355 mov FREE_SCBH, SCBPTR ret;
2356 END_CRITICAL;
2357 } else {
2358 mvi SCB_TAG, SCB_LIST_NULL ret;
2359 }
2360
2361 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2362 set_hhaddr:
2363 or DSCOMMAND1, HADDLDSEL0;
2364 and HADDR, SG_HIGH_ADDR_BITS, SINDEX;
2365 and DSCOMMAND1, ~HADDLDSEL0 ret;
2366 }
2367
2368 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2369 get_free_or_disc_scb:
2370 BEGIN_CRITICAL;
2371 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2372 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2373 return_error:
2374 mvi NO_FREE_SCB call set_seqint;
2375 mvi SINDEX, SCB_LIST_NULL ret;
2376 dequeue_disc_scb:
2377 mov SCBPTR, DISCONNECTED_SCBH;
2378 mov DISCONNECTED_SCBH, SCB_NEXT;
2379 END_CRITICAL;
2380 mvi DMAPARAMS, FIFORESET;
2381 mov SCB_TAG jmp dma_scb;
2382 BEGIN_CRITICAL;
2383 dequeue_free_scb:
2384 mov SCBPTR, FREE_SCBH;
2385 mov FREE_SCBH, SCB_NEXT ret;
2386 END_CRITICAL;
2387
2388 add_scb_to_disc_list:
2389 /*
2390 * Link this SCB into the DISCONNECTED list. This list holds the
2391 * candidates for paging out an SCB if one is needed for a new command.
2392 * Modifying the disconnected list is a critical(pause dissabled) section.
2393 */
2394 BEGIN_CRITICAL;
2395 mov SCB_NEXT, DISCONNECTED_SCBH;
2396 mov DISCONNECTED_SCBH, SCBPTR ret;
2397 END_CRITICAL;
2398 }
2399 set_seqint:
2400 mov INTSTAT, SINDEX;
2401 nop;
2402 return:
2403 ret;
Cache object: 3d014918c170e9cc4277d61a5084d630
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