The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/aic7xxx/aic7xxx_93cx6.c

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    1 /*-
    2  * Interface for the 93C66/56/46/26/06 serial eeprom parts.
    3  *
    4  * Copyright (c) 1995, 1996 Daniel M. Eischen
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions, and the following disclaimer,
   12  *    without modification.
   13  * 2. The name of the author may not be used to endorse or promote products
   14  *    derived from this software without specific prior written permission.
   15  *
   16  * Alternatively, this software may be distributed under the terms of the
   17  * GNU General Public License ("GPL").
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
   32  */
   33 
   34 /*
   35  *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
   36  *
   37  *               Start  OP          *
   38  *     Function   Bit  Code  Address**  Data     Description
   39  *     -------------------------------------------------------------------
   40  *     READ        1    10   A5 - A0             Reads data stored in memory,
   41  *                                               starting at specified address
   42  *     EWEN        1    00   11XXXX              Write enable must precede
   43  *                                               all programming modes
   44  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
   45  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
   46  *     ERAL        1    00   10XXXX              Erase all registers
   47  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
   48  *     EWDS        1    00   00XXXX              Disables all programming
   49  *                                               instructions
   50  *     *Note: A value of X for address is a don't care condition.
   51  *    **Note: There are 8 address bits for the 93C56/66 chips unlike
   52  *            the 93C46/26/06 chips which have 6 address bits.
   53  *
   54  *   The 93C46 has a four wire interface: clock, chip select, data in, and
   55  *   data out.  In order to perform one of the above functions, you need
   56  *   to enable the chip select for a clock period (typically a minimum of
   57  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
   58  *   respectively).  While the chip select remains high, you can clock in
   59  *   the instructions (above) starting with the start bit, followed by the
   60  *   OP code, Address, and Data (if needed).  For the READ instruction, the
   61  *   requested 16-bit register contents is read from the data out line but
   62  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
   63  *   first).  The clock cycling from low to high initiates the next data
   64  *   bit to be sent from the chip.
   65  */
   66 
   67 #ifdef __linux__
   68 #include "aic7xxx_osm.h"
   69 #include "aic7xxx_inline.h"
   70 #include "aic7xxx_93cx6.h"
   71 #else
   72 #include <sys/cdefs.h>
   73 __FBSDID("$FreeBSD: releng/11.2/sys/dev/aic7xxx/aic7xxx_93cx6.c 139757 2005-01-06 05:30:44Z scottl $");
   74 #include <dev/aic7xxx/aic7xxx_osm.h>
   75 #include <dev/aic7xxx/aic7xxx_inline.h>
   76 #include <dev/aic7xxx/aic7xxx_93cx6.h>
   77 #endif
   78 
   79 /*
   80  * Right now, we only have to read the SEEPROM.  But we make it easier to
   81  * add other 93Cx6 functions.
   82  */
   83 struct seeprom_cmd {
   84         uint8_t len;
   85         uint8_t bits[11];
   86 };
   87 
   88 /* Short opcodes for the c46 */
   89 static struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
   90 static struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
   91 
   92 /* Long opcodes for the C56/C66 */
   93 static struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
   94 static struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
   95 
   96 /* Common opcodes */
   97 static struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
   98 static struct seeprom_cmd seeprom_read  = {3, {1, 1, 0}};
   99 
  100 /*
  101  * Wait for the SEERDY to go high; about 800 ns.
  102  */
  103 #define CLOCK_PULSE(sd, rdy)                            \
  104         while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) {   \
  105                 ;  /* Do nothing */                     \
  106         }                                               \
  107         (void)SEEPROM_INB(sd);  /* Clear clock */
  108 
  109 /*
  110  * Send a START condition and the given command
  111  */
  112 static void
  113 send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd)
  114 {
  115         uint8_t temp;
  116         int i = 0;
  117 
  118         /* Send chip select for one clock cycle. */
  119         temp = sd->sd_MS ^ sd->sd_CS;
  120         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  121         CLOCK_PULSE(sd, sd->sd_RDY);
  122 
  123         for (i = 0; i < cmd->len; i++) {
  124                 if (cmd->bits[i] != 0)
  125                         temp ^= sd->sd_DO;
  126                 SEEPROM_OUTB(sd, temp);
  127                 CLOCK_PULSE(sd, sd->sd_RDY);
  128                 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  129                 CLOCK_PULSE(sd, sd->sd_RDY);
  130                 if (cmd->bits[i] != 0)
  131                         temp ^= sd->sd_DO;
  132         }
  133 }
  134 
  135 /*
  136  * Clear CS put the chip in the reset state, where it can wait for new commands.
  137  */
  138 static void
  139 reset_seeprom(struct seeprom_descriptor *sd)
  140 {
  141         uint8_t temp;
  142 
  143         temp = sd->sd_MS;
  144         SEEPROM_OUTB(sd, temp);
  145         CLOCK_PULSE(sd, sd->sd_RDY);
  146         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  147         CLOCK_PULSE(sd, sd->sd_RDY);
  148         SEEPROM_OUTB(sd, temp);
  149         CLOCK_PULSE(sd, sd->sd_RDY);
  150 }
  151 
  152 /*
  153  * Read the serial EEPROM and returns 1 if successful and 0 if
  154  * not successful.
  155  */
  156 int
  157 ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
  158                  u_int start_addr, u_int count)
  159 {
  160         int i = 0;
  161         u_int k = 0;
  162         uint16_t v;
  163         uint8_t temp;
  164 
  165         /*
  166          * Read the requested registers of the seeprom.  The loop
  167          * will range from 0 to count-1.
  168          */
  169         for (k = start_addr; k < count + start_addr; k++) {
  170                 /*
  171                  * Now we're ready to send the read command followed by the
  172                  * address of the 16-bit register we want to read.
  173                  */
  174                 send_seeprom_cmd(sd, &seeprom_read);
  175 
  176                 /* Send the 6 or 8 bit address (MSB first, LSB last). */
  177                 temp = sd->sd_MS ^ sd->sd_CS;
  178                 for (i = (sd->sd_chip - 1); i >= 0; i--) {
  179                         if ((k & (1 << i)) != 0)
  180                                 temp ^= sd->sd_DO;
  181                         SEEPROM_OUTB(sd, temp);
  182                         CLOCK_PULSE(sd, sd->sd_RDY);
  183                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  184                         CLOCK_PULSE(sd, sd->sd_RDY);
  185                         if ((k & (1 << i)) != 0)
  186                                 temp ^= sd->sd_DO;
  187                 }
  188 
  189                 /*
  190                  * Now read the 16 bit register.  An initial 0 precedes the
  191                  * register contents which begins with bit 15 (MSB) and ends
  192                  * with bit 0 (LSB).  The initial 0 will be shifted off the
  193                  * top of our word as we let the loop run from 0 to 16.
  194                  */
  195                 v = 0;
  196                 for (i = 16; i >= 0; i--) {
  197                         SEEPROM_OUTB(sd, temp);
  198                         CLOCK_PULSE(sd, sd->sd_RDY);
  199                         v <<= 1;
  200                         if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
  201                                 v |= 1;
  202                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  203                         CLOCK_PULSE(sd, sd->sd_RDY);
  204                 }
  205 
  206                 buf[k - start_addr] = v;
  207 
  208                 /* Reset the chip select for the next command cycle. */
  209                 reset_seeprom(sd);
  210         }
  211 #ifdef AHC_DUMP_EEPROM
  212         printf("\nSerial EEPROM:\n\t");
  213         for (k = 0; k < count; k = k + 1) {
  214                 if (((k % 8) == 0) && (k != 0)) {
  215                         printf ("\n\t");
  216                 }
  217                 printf (" 0x%x", buf[k]);
  218         }
  219         printf ("\n");
  220 #endif
  221         return (1);
  222 }
  223 
  224 /*
  225  * Write the serial EEPROM and return 1 if successful and 0 if
  226  * not successful.
  227  */
  228 int
  229 ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
  230                   u_int start_addr, u_int count)
  231 {
  232         struct seeprom_cmd *ewen, *ewds;
  233         uint16_t v;
  234         uint8_t temp;
  235         int i, k;
  236 
  237         /* Place the chip into write-enable mode */
  238         if (sd->sd_chip == C46) {
  239                 ewen = &seeprom_ewen;
  240                 ewds = &seeprom_ewds;
  241         } else if (sd->sd_chip == C56_66) {
  242                 ewen = &seeprom_long_ewen;
  243                 ewds = &seeprom_long_ewds;
  244         } else {
  245                 printf("ahc_write_seeprom: unsupported seeprom type %d\n",
  246                        sd->sd_chip);
  247                 return (0);
  248         }
  249 
  250         send_seeprom_cmd(sd, ewen);
  251         reset_seeprom(sd);
  252 
  253         /* Write all requested data out to the seeprom. */
  254         temp = sd->sd_MS ^ sd->sd_CS;
  255         for (k = start_addr; k < count + start_addr; k++) {
  256                 /* Send the write command */
  257                 send_seeprom_cmd(sd, &seeprom_write);
  258 
  259                 /* Send the 6 or 8 bit address (MSB first). */
  260                 for (i = (sd->sd_chip - 1); i >= 0; i--) {
  261                         if ((k & (1 << i)) != 0)
  262                                 temp ^= sd->sd_DO;
  263                         SEEPROM_OUTB(sd, temp);
  264                         CLOCK_PULSE(sd, sd->sd_RDY);
  265                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  266                         CLOCK_PULSE(sd, sd->sd_RDY);
  267                         if ((k & (1 << i)) != 0)
  268                                 temp ^= sd->sd_DO;
  269                 }
  270 
  271                 /* Write the 16 bit value, MSB first */
  272                 v = buf[k - start_addr];
  273                 for (i = 15; i >= 0; i--) {
  274                         if ((v & (1 << i)) != 0)
  275                                 temp ^= sd->sd_DO;
  276                         SEEPROM_OUTB(sd, temp);
  277                         CLOCK_PULSE(sd, sd->sd_RDY);
  278                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  279                         CLOCK_PULSE(sd, sd->sd_RDY);
  280                         if ((v & (1 << i)) != 0)
  281                                 temp ^= sd->sd_DO;
  282                 }
  283 
  284                 /* Wait for the chip to complete the write */
  285                 temp = sd->sd_MS;
  286                 SEEPROM_OUTB(sd, temp);
  287                 CLOCK_PULSE(sd, sd->sd_RDY);
  288                 temp = sd->sd_MS ^ sd->sd_CS;
  289                 do {
  290                         SEEPROM_OUTB(sd, temp);
  291                         CLOCK_PULSE(sd, sd->sd_RDY);
  292                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
  293                         CLOCK_PULSE(sd, sd->sd_RDY);
  294                 } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
  295 
  296                 reset_seeprom(sd);
  297         }
  298 
  299         /* Put the chip back into write-protect mode */
  300         send_seeprom_cmd(sd, ewds);
  301         reset_seeprom(sd);
  302 
  303         return (1);
  304 }
  305 
  306 int
  307 ahc_verify_cksum(struct seeprom_config *sc)
  308 {
  309         int i;
  310         int maxaddr;
  311         uint32_t checksum;
  312         uint16_t *scarray;
  313 
  314         maxaddr = (sizeof(*sc)/2) - 1;
  315         checksum = 0;
  316         scarray = (uint16_t *)sc;
  317 
  318         for (i = 0; i < maxaddr; i++)
  319                 checksum = checksum + scarray[i];
  320         if (checksum == 0
  321          || (checksum & 0xFFFF) != sc->checksum) {
  322                 return (0);
  323         } else {
  324                 return(1);
  325         }
  326 }

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