Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/aic7xxx/aic7xxx_pci.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * Copyright (c) 1994-2001 Justin T. Gibbs. 9 * Copyright (c) 2000-2001 Adaptec Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions, and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * substantially similar to the "NO WARRANTY" disclaimer below 20 * ("Disclaimer") and any redistribution must be conditioned upon 21 * including a substantially similar Disclaimer requirement for further 22 * binary redistribution. 23 * 3. Neither the names of the above-listed copyright holders nor the names 24 * of any contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * Alternatively, this software may be distributed under the terms of the 28 * GNU General Public License ("GPL") version 2 as published by the Free 29 * Software Foundation. 30 * 31 * NO WARRANTY 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 * POSSIBILITY OF SUCH DAMAGES. 43 * 44 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <sys/cdefs.h> 53 __FBSDID("$FreeBSD$"); 54 #include <dev/aic7xxx/aic7xxx_osm.h> 55 #include <dev/aic7xxx/aic7xxx_inline.h> 56 #include <dev/aic7xxx/aic7xxx_93cx6.h> 57 #endif 58 59 static __inline uint64_t 60 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 61 { 62 uint64_t id; 63 64 id = subvendor 65 | (subdevice << 16) 66 | ((uint64_t)vendor << 32) 67 | ((uint64_t)device << 48); 68 69 return (id); 70 } 71 72 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 73 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 74 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 75 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 76 #define ID_9005_SISL_ID 0x0005900500000000ull 77 #define ID_AIC7850 0x5078900400000000ull 78 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull 79 #define ID_AIC7855 0x5578900400000000ull 80 #define ID_AIC7859 0x3860900400000000ull 81 #define ID_AHA_2930CU 0x3860900438699004ull 82 #define ID_AIC7860 0x6078900400000000ull 83 #define ID_AIC7860C 0x6078900478609004ull 84 #define ID_AHA_1480A 0x6075900400000000ull 85 #define ID_AHA_2940AU_0 0x6178900400000000ull 86 #define ID_AHA_2940AU_1 0x6178900478619004ull 87 #define ID_AHA_2940AU_CN 0x2178900478219004ull 88 #define ID_AHA_2930C_VAR 0x6038900438689004ull 89 90 #define ID_AIC7870 0x7078900400000000ull 91 #define ID_AHA_2940 0x7178900400000000ull 92 #define ID_AHA_3940 0x7278900400000000ull 93 #define ID_AHA_398X 0x7378900400000000ull 94 #define ID_AHA_2944 0x7478900400000000ull 95 #define ID_AHA_3944 0x7578900400000000ull 96 #define ID_AHA_4944 0x7678900400000000ull 97 98 #define ID_AIC7880 0x8078900400000000ull 99 #define ID_AIC7880_B 0x8078900478809004ull 100 #define ID_AHA_2940U 0x8178900400000000ull 101 #define ID_AHA_3940U 0x8278900400000000ull 102 #define ID_AHA_2944U 0x8478900400000000ull 103 #define ID_AHA_3944U 0x8578900400000000ull 104 #define ID_AHA_398XU 0x8378900400000000ull 105 #define ID_AHA_4944U 0x8678900400000000ull 106 #define ID_AHA_2940UB 0x8178900478819004ull 107 #define ID_AHA_2930U 0x8878900478889004ull 108 #define ID_AHA_2940U_PRO 0x8778900478879004ull 109 #define ID_AHA_2940U_CN 0x0078900478009004ull 110 111 #define ID_AIC7895 0x7895900478959004ull 112 #define ID_AIC7895_ARO 0x7890900478939004ull 113 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 114 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 115 #define ID_AHA_3940AU 0x7895900478929004ull 116 #define ID_AHA_3944AU 0x7895900478949004ull 117 118 #define ID_AIC7890 0x001F9005000F9005ull 119 #define ID_AIC7890_ARO 0x00139005000F9005ull 120 #define ID_AAA_131U2 0x0013900500039005ull 121 #define ID_AHA_2930U2 0x0011900501819005ull 122 #define ID_AHA_2940U2B 0x00109005A1009005ull 123 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 124 #define ID_AHA_2940U2 0x00109005A1809005ull 125 #define ID_AHA_2950U2B 0x00109005E1009005ull 126 127 #define ID_AIC7892 0x008F9005FFFF9005ull 128 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 129 #define ID_AHA_29160 0x00809005E2A09005ull 130 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 131 #define ID_AHA_29160N 0x0080900562A09005ull 132 #define ID_AHA_29160C 0x0080900562209005ull 133 #define ID_AHA_29160B 0x00809005E2209005ull 134 #define ID_AHA_19160B 0x0081900562A19005ull 135 #define ID_AHA_2915_30LP 0x0082900502109005ull 136 137 #define ID_AIC7896 0x005F9005FFFF9005ull 138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 146 #define ID_AHA_3960D 0x00C09005F6209005ull 147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 148 149 #define ID_AIC7810 0x1078900400000000ull 150 #define ID_AIC7815 0x7815900400000000ull 151 152 #define DEVID_9005_TYPE(id) ((id) & 0xF) 153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 157 158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 159 #define DEVID_9005_MAXRATE_U160 0x0 160 #define DEVID_9005_MAXRATE_ULTRA2 0x1 161 #define DEVID_9005_MAXRATE_ULTRA 0x2 162 #define DEVID_9005_MAXRATE_FAST 0x3 163 164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 165 166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 168 169 #define SUBID_9005_TYPE(id) ((id) & 0xF) 170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 174 175 #define SUBID_9005_TYPE_KNOWN(id) \ 176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 180 181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define SUBID_9005_MAXRATE_ULTRA2 0x0 183 #define SUBID_9005_MAXRATE_ULTRA 0x1 184 #define SUBID_9005_MAXRATE_U160 0x2 185 #define SUBID_9005_MAXRATE_RESERVED 0x3 186 187 #define SUBID_9005_SEEPTYPE(id) \ 188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 189 ? ((id) & 0xC0) >> 6 \ 190 : ((id) & 0x300) >> 8) 191 #define SUBID_9005_SEEPTYPE_NONE 0x0 192 #define SUBID_9005_SEEPTYPE_1K 0x1 193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 195 #define SUBID_9005_AUTOTERM(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? (((id) & 0x400) >> 10) == 0 \ 198 : (((id) & 0x40) >> 6) == 0) 199 200 #define SUBID_9005_NUMCHAN(id) \ 201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 202 ? ((id) & 0x300) >> 8 \ 203 : ((id) & 0xC00) >> 10) 204 205 #define SUBID_9005_LEGACYCONN(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? 0 \ 208 : ((id) & 0x80) >> 7) 209 210 #define SUBID_9005_MFUNCENB(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0x800) >> 11 \ 213 : ((id) & 0x1000) >> 12) 214 /* 215 * Informational only. Should use chip register to be 216 * certain, but may be use in identification strings. 217 */ 218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 221 222 static ahc_device_setup_t ahc_aic785X_setup; 223 static ahc_device_setup_t ahc_aic7860_setup; 224 static ahc_device_setup_t ahc_apa1480_setup; 225 static ahc_device_setup_t ahc_aic7870_setup; 226 static ahc_device_setup_t ahc_aha394X_setup; 227 static ahc_device_setup_t ahc_aha494X_setup; 228 static ahc_device_setup_t ahc_aha398X_setup; 229 static ahc_device_setup_t ahc_aic7880_setup; 230 static ahc_device_setup_t ahc_aha2940Pro_setup; 231 static ahc_device_setup_t ahc_aha394XU_setup; 232 static ahc_device_setup_t ahc_aha398XU_setup; 233 static ahc_device_setup_t ahc_aic7890_setup; 234 static ahc_device_setup_t ahc_aic7892_setup; 235 static ahc_device_setup_t ahc_aic7895_setup; 236 static ahc_device_setup_t ahc_aic7896_setup; 237 static ahc_device_setup_t ahc_aic7899_setup; 238 static ahc_device_setup_t ahc_aha29160C_setup; 239 static ahc_device_setup_t ahc_raid_setup; 240 static ahc_device_setup_t ahc_aha394XX_setup; 241 static ahc_device_setup_t ahc_aha494XX_setup; 242 static ahc_device_setup_t ahc_aha398XX_setup; 243 244 struct ahc_pci_identity ahc_pci_ident_table [] = 245 { 246 /* aic7850 based controllers */ 247 { 248 ID_AHA_2902_04_10_15_20C_30C, 249 ID_ALL_MASK, 250 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 251 ahc_aic785X_setup 252 }, 253 /* aic7860 based controllers */ 254 { 255 ID_AHA_2930CU, 256 ID_ALL_MASK, 257 "Adaptec 2930CU SCSI adapter", 258 ahc_aic7860_setup 259 }, 260 { 261 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 1480A Ultra SCSI adapter", 264 ahc_apa1480_setup 265 }, 266 { 267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2940A Ultra SCSI adapter", 270 ahc_aic7860_setup 271 }, 272 { 273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 2940A/CN Ultra SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 2930C Ultra SCSI adapter (VAR)", 282 ahc_aic7860_setup 283 }, 284 /* aic7870 based controllers */ 285 { 286 ID_AHA_2940, 287 ID_ALL_MASK, 288 "Adaptec 2940 SCSI adapter", 289 ahc_aic7870_setup 290 }, 291 { 292 ID_AHA_3940, 293 ID_ALL_MASK, 294 "Adaptec 3940 SCSI adapter", 295 ahc_aha394X_setup 296 }, 297 { 298 ID_AHA_398X, 299 ID_ALL_MASK, 300 "Adaptec 398X SCSI RAID adapter", 301 ahc_aha398X_setup 302 }, 303 { 304 ID_AHA_2944, 305 ID_ALL_MASK, 306 "Adaptec 2944 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3944, 311 ID_ALL_MASK, 312 "Adaptec 3944 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_4944, 317 ID_ALL_MASK, 318 "Adaptec 4944 SCSI adapter", 319 ahc_aha494X_setup 320 }, 321 /* aic7880 based controllers */ 322 { 323 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 324 ID_DEV_VENDOR_MASK, 325 "Adaptec 2940 Ultra SCSI adapter", 326 ahc_aic7880_setup 327 }, 328 { 329 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 330 ID_DEV_VENDOR_MASK, 331 "Adaptec 3940 Ultra SCSI adapter", 332 ahc_aha394XU_setup 333 }, 334 { 335 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 336 ID_DEV_VENDOR_MASK, 337 "Adaptec 2944 Ultra SCSI adapter", 338 ahc_aic7880_setup 339 }, 340 { 341 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 3944 Ultra SCSI adapter", 344 ahc_aha394XU_setup 345 }, 346 { 347 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 398X Ultra SCSI RAID adapter", 350 ahc_aha398XU_setup 351 }, 352 { 353 /* 354 * XXX Don't know the slot numbers 355 * so we can't identify channels 356 */ 357 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec 4944 Ultra SCSI adapter", 360 ahc_aic7880_setup 361 }, 362 { 363 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec 2930 Ultra SCSI adapter", 366 ahc_aic7880_setup 367 }, 368 { 369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec 2940 Pro Ultra SCSI adapter", 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 2940/CN Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 /* Ignore all SISL (AAC on MB) based controllers. */ 381 { 382 ID_9005_SISL_ID, 383 ID_9005_SISL_MASK, 384 NULL, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 "Adaptec 2930 Ultra2 SCSI adapter", 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 "Adaptec 2940B Ultra2 SCSI adapter", 398 ahc_aic7890_setup 399 }, 400 { 401 ID_AHA_2940U2_OEM, 402 ID_ALL_MASK, 403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2940U2, 408 ID_ALL_MASK, 409 "Adaptec 2940 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2950U2B, 414 ID_ALL_MASK, 415 "Adaptec 2950 Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AIC7890_ARO, 420 ID_ALL_MASK, 421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AAA_131U2, 426 ID_ALL_MASK, 427 "Adaptec AAA-131 Ultra2 RAID adapter", 428 ahc_aic7890_setup 429 }, 430 /* aic7892 based controllers */ 431 { 432 ID_AHA_29160, 433 ID_ALL_MASK, 434 "Adaptec 29160 Ultra160 SCSI adapter", 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160_CPQ, 439 ID_ALL_MASK, 440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 441 ahc_aic7892_setup 442 }, 443 { 444 ID_AHA_29160N, 445 ID_ALL_MASK, 446 "Adaptec 29160N Ultra160 SCSI adapter", 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_29160C, 451 ID_ALL_MASK, 452 "Adaptec 29160C Ultra160 SCSI adapter", 453 ahc_aha29160C_setup 454 }, 455 { 456 ID_AHA_29160B, 457 ID_ALL_MASK, 458 "Adaptec 29160B Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_19160B, 463 ID_ALL_MASK, 464 "Adaptec 19160B Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7892_ARO, 469 ID_ALL_MASK, 470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 471 ahc_aic7892_setup 472 }, 473 { 474 ID_AHA_2915_30LP, 475 ID_ALL_MASK, 476 "Adaptec 2915/30LP Ultra160 SCSI adapter", 477 ahc_aic7892_setup 478 }, 479 /* aic7895 based controllers */ 480 { 481 ID_AHA_2940U_DUAL, 482 ID_ALL_MASK, 483 "Adaptec 2940/DUAL Ultra SCSI adapter", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AHA_3940AU, 488 ID_ALL_MASK, 489 "Adaptec 3940A Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AHA_3944AU, 494 ID_ALL_MASK, 495 "Adaptec 3944A Ultra SCSI adapter", 496 ahc_aic7895_setup 497 }, 498 { 499 ID_AIC7895_ARO, 500 ID_AIC7895_ARO_MASK, 501 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 502 ahc_aic7895_setup 503 }, 504 /* aic7896/97 based controllers */ 505 { 506 ID_AHA_3950U2B_0, 507 ID_ALL_MASK, 508 "Adaptec 3950B Ultra2 SCSI adapter", 509 ahc_aic7896_setup 510 }, 511 { 512 ID_AHA_3950U2B_1, 513 ID_ALL_MASK, 514 "Adaptec 3950B Ultra2 SCSI adapter", 515 ahc_aic7896_setup 516 }, 517 { 518 ID_AHA_3950U2D_0, 519 ID_ALL_MASK, 520 "Adaptec 3950D Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AHA_3950U2D_1, 525 ID_ALL_MASK, 526 "Adaptec 3950D Ultra2 SCSI adapter", 527 ahc_aic7896_setup 528 }, 529 { 530 ID_AIC7896_ARO, 531 ID_ALL_MASK, 532 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 533 ahc_aic7896_setup 534 }, 535 /* aic7899 based controllers */ 536 { 537 ID_AHA_3960D, 538 ID_ALL_MASK, 539 "Adaptec 3960D Ultra160 SCSI adapter", 540 ahc_aic7899_setup 541 }, 542 { 543 ID_AHA_3960D_CPQ, 544 ID_ALL_MASK, 545 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 546 ahc_aic7899_setup 547 }, 548 { 549 ID_AIC7899_ARO, 550 ID_ALL_MASK, 551 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 552 ahc_aic7899_setup 553 }, 554 /* Generic chip probes for devices we don't know 'exactly' */ 555 { 556 ID_AIC7850 & ID_DEV_VENDOR_MASK, 557 ID_DEV_VENDOR_MASK, 558 "Adaptec aic7850 SCSI adapter", 559 ahc_aic785X_setup 560 }, 561 { 562 ID_AIC7855 & ID_DEV_VENDOR_MASK, 563 ID_DEV_VENDOR_MASK, 564 "Adaptec aic7855 SCSI adapter", 565 ahc_aic785X_setup 566 }, 567 { 568 ID_AIC7859 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7859 SCSI adapter", 571 ahc_aic7860_setup 572 }, 573 { 574 ID_AIC7860 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7860 Ultra SCSI adapter", 577 ahc_aic7860_setup 578 }, 579 { 580 ID_AIC7870 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7870 SCSI adapter", 583 ahc_aic7870_setup 584 }, 585 { 586 ID_AIC7880 & ID_DEV_VENDOR_MASK, 587 ID_DEV_VENDOR_MASK, 588 "Adaptec aic7880 Ultra SCSI adapter", 589 ahc_aic7880_setup 590 }, 591 { 592 ID_AIC7890 & ID_9005_GENERIC_MASK, 593 ID_9005_GENERIC_MASK, 594 "Adaptec aic7890/91 Ultra2 SCSI adapter", 595 ahc_aic7890_setup 596 }, 597 { 598 ID_AIC7892 & ID_9005_GENERIC_MASK, 599 ID_9005_GENERIC_MASK, 600 "Adaptec aic7892 Ultra160 SCSI adapter", 601 ahc_aic7892_setup 602 }, 603 { 604 ID_AIC7895 & ID_DEV_VENDOR_MASK, 605 ID_DEV_VENDOR_MASK, 606 "Adaptec aic7895 Ultra SCSI adapter", 607 ahc_aic7895_setup 608 }, 609 { 610 ID_AIC7896 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7896/97 Ultra2 SCSI adapter", 613 ahc_aic7896_setup 614 }, 615 { 616 ID_AIC7899 & ID_9005_GENERIC_MASK, 617 ID_9005_GENERIC_MASK, 618 "Adaptec aic7899 Ultra160 SCSI adapter", 619 ahc_aic7899_setup 620 }, 621 { 622 ID_AIC7810 & ID_DEV_VENDOR_MASK, 623 ID_DEV_VENDOR_MASK, 624 "Adaptec aic7810 RAID memory controller", 625 ahc_raid_setup 626 }, 627 { 628 ID_AIC7815 & ID_DEV_VENDOR_MASK, 629 ID_DEV_VENDOR_MASK, 630 "Adaptec aic7815 RAID memory controller", 631 ahc_raid_setup 632 } 633 }; 634 635 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 636 637 #define AHC_394X_SLOT_CHANNEL_A 4 638 #define AHC_394X_SLOT_CHANNEL_B 5 639 640 #define AHC_398X_SLOT_CHANNEL_A 4 641 #define AHC_398X_SLOT_CHANNEL_B 8 642 #define AHC_398X_SLOT_CHANNEL_C 12 643 644 #define AHC_494X_SLOT_CHANNEL_A 4 645 #define AHC_494X_SLOT_CHANNEL_B 5 646 #define AHC_494X_SLOT_CHANNEL_C 6 647 #define AHC_494X_SLOT_CHANNEL_D 7 648 649 #define DEVCONFIG 0x40 650 #define PCIERRGENDIS 0x80000000ul 651 #define SCBSIZE32 0x00010000ul /* aic789X only */ 652 #define REXTVALID 0x00001000ul /* ultra cards only */ 653 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 654 #define RAMPSM 0x00000200ul /* aic7870+ only */ 655 #define VOLSENSE 0x00000100ul 656 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 657 #define SCBRAMSEL 0x00000080ul 658 #define MRDCEN 0x00000040ul 659 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 660 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 661 #define BERREN 0x00000008ul 662 #define DACEN 0x00000004ul 663 #define STPWLEVEL 0x00000002ul 664 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 665 666 #define CSIZE_LATTIME 0x0c 667 #define CACHESIZE 0x0000003ful /* only 5 bits */ 668 #define LATTIME 0x0000ff00ul 669 670 /* PCI STATUS definitions */ 671 #define DPE 0x80 672 #define SSE 0x40 673 #define RMA 0x20 674 #define RTA 0x10 675 #define STA 0x08 676 #define DPR 0x01 677 678 static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 679 uint16_t subdevice, uint16_t subvendor); 680 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 681 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 682 int pcheck, int fast, int large); 683 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 684 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 685 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 686 struct seeprom_config *sc); 687 static void configure_termination(struct ahc_softc *ahc, 688 struct seeprom_descriptor *sd, 689 u_int adapter_control, 690 u_int *sxfrctl1); 691 692 static void ahc_new_term_detect(struct ahc_softc *ahc, 693 int *enableSEC_low, 694 int *enableSEC_high, 695 int *enablePRI_low, 696 int *enablePRI_high, 697 int *eeprom_present); 698 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 699 int *internal68_present, 700 int *externalcable_present, 701 int *eeprom_present); 702 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 703 int *externalcable_present, 704 int *eeprom_present); 705 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 706 static uint8_t read_brdctl(struct ahc_softc *ahc); 707 static void ahc_pci_intr(struct ahc_softc *ahc); 708 static int ahc_pci_chip_init(struct ahc_softc *ahc); 709 static int ahc_pci_suspend(struct ahc_softc *ahc); 710 static int ahc_pci_resume(struct ahc_softc *ahc); 711 712 static int 713 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 714 uint16_t subdevice, uint16_t subvendor) 715 { 716 int result; 717 718 /* Default to invalid. */ 719 result = 0; 720 if (vendor == 0x9005 721 && subvendor == 0x9005 722 && subdevice != device 723 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 724 switch (SUBID_9005_TYPE(subdevice)) { 725 case SUBID_9005_TYPE_MB: 726 break; 727 case SUBID_9005_TYPE_CARD: 728 case SUBID_9005_TYPE_LCCARD: 729 /* 730 * Currently only trust Adaptec cards to 731 * get the sub device info correct. 732 */ 733 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 734 result = 1; 735 break; 736 case SUBID_9005_TYPE_RAID: 737 break; 738 default: 739 break; 740 } 741 } 742 return (result); 743 } 744 745 struct ahc_pci_identity * 746 ahc_find_pci_device(aic_dev_softc_t pci) 747 { 748 uint64_t full_id; 749 uint16_t device; 750 uint16_t vendor; 751 uint16_t subdevice; 752 uint16_t subvendor; 753 struct ahc_pci_identity *entry; 754 u_int i; 755 756 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 757 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 758 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 759 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 760 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 761 762 /* 763 * If the second function is not hooked up, ignore it. 764 * Unfortunately, not all MB vendors implement the 765 * subdevice ID as per the Adaptec spec, so do our best 766 * to sanity check it prior to accepting the subdevice 767 * ID as valid. 768 */ 769 if (aic_get_pci_function(pci) > 0 770 && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor) 771 && SUBID_9005_MFUNCENB(subdevice) == 0) 772 return (NULL); 773 774 for (i = 0; i < ahc_num_pci_devs; i++) { 775 entry = &ahc_pci_ident_table[i]; 776 if (entry->full_id == (full_id & entry->id_mask)) { 777 /* Honor exclusion entries. */ 778 if (entry->name == NULL) 779 return (NULL); 780 return (entry); 781 } 782 } 783 return (NULL); 784 } 785 786 int 787 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 788 { 789 u_int command; 790 u_int our_id; 791 u_int sxfrctl1; 792 u_int scsiseq; 793 u_int dscommand0; 794 uint32_t devconfig; 795 int error; 796 uint8_t sblkctl; 797 798 our_id = 0; 799 error = entry->setup(ahc); 800 if (error != 0) 801 return (error); 802 ahc->chip |= AHC_PCI; 803 ahc->description = entry->name; 804 805 aic_power_state_change(ahc, AIC_POWER_STATE_D0); 806 807 error = ahc_pci_map_registers(ahc); 808 if (error != 0) 809 return (error); 810 811 /* 812 * Before we continue probing the card, ensure that 813 * its interrupts are *disabled*. We don't want 814 * a misstep to hang the machine in an interrupt 815 * storm. 816 */ 817 ahc_intr_enable(ahc, FALSE); 818 819 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 820 821 /* 822 * If we need to support high memory, enable dual 823 * address cycles. This bit must be set to enable 824 * high address bit generation even if we are on a 825 * 64bit bus (PCI64BIT set in devconfig). 826 */ 827 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 828 if (bootverbose) 829 printf("%s: Enabling 39Bit Addressing\n", 830 ahc_name(ahc)); 831 devconfig |= DACEN; 832 } 833 834 /* Ensure that pci error generation, a test feature, is disabled. */ 835 devconfig |= PCIERRGENDIS; 836 837 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 838 839 /* Ensure busmastering is enabled */ 840 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 841 command |= PCIM_CMD_BUSMASTEREN; 842 843 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 844 845 /* On all PCI adapters, we allow SCB paging */ 846 ahc->flags |= AHC_PAGESCBS; 847 848 error = ahc_softc_init(ahc); 849 if (error != 0) 850 return (error); 851 852 /* 853 * Disable PCI parity error checking. Users typically 854 * do this to work around broken PCI chipsets that get 855 * the parity timing wrong and thus generate lots of spurious 856 * errors. The chip only allows us to disable *all* parity 857 * error reporting when doing this, so CIO bus, scb ram, and 858 * scratch ram parity errors will be ignored too. 859 */ 860 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 861 ahc->seqctl |= FAILDIS; 862 863 ahc->bus_intr = ahc_pci_intr; 864 ahc->bus_chip_init = ahc_pci_chip_init; 865 ahc->bus_suspend = ahc_pci_suspend; 866 ahc->bus_resume = ahc_pci_resume; 867 868 /* Remember how the card was setup in case there is no SEEPROM */ 869 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 870 ahc_pause(ahc); 871 if ((ahc->features & AHC_ULTRA2) != 0) 872 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 873 else 874 our_id = ahc_inb(ahc, SCSIID) & OID; 875 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 876 scsiseq = ahc_inb(ahc, SCSISEQ); 877 } else { 878 sxfrctl1 = STPWEN; 879 our_id = 7; 880 scsiseq = 0; 881 } 882 883 error = ahc_reset(ahc, /*reinit*/FALSE); 884 if (error != 0) 885 return (ENXIO); 886 887 if ((ahc->features & AHC_DT) != 0) { 888 u_int sfunct; 889 890 /* Perform ALT-Mode Setup */ 891 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 892 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 893 ahc_outb(ahc, OPTIONMODE, 894 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 895 ahc_outb(ahc, SFUNCT, sfunct); 896 897 /* Normal mode setup */ 898 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 899 |TARGCRCENDEN); 900 } 901 902 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 903 dscommand0 |= MPARCKEN|CACHETHEN; 904 if ((ahc->features & AHC_ULTRA2) != 0) { 905 /* 906 * DPARCKEN doesn't work correctly on 907 * some MBs so don't use it. 908 */ 909 dscommand0 &= ~DPARCKEN; 910 } 911 912 /* 913 * Handle chips that must have cache line 914 * streaming (dis/en)abled. 915 */ 916 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 917 dscommand0 |= CACHETHEN; 918 919 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 920 dscommand0 &= ~CACHETHEN; 921 922 ahc_outb(ahc, DSCOMMAND0, dscommand0); 923 924 ahc->pci_cachesize = 925 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 926 /*bytes*/1) & CACHESIZE; 927 ahc->pci_cachesize *= 4; 928 929 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 930 && ahc->pci_cachesize == 4) { 931 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 932 0, /*bytes*/1); 933 ahc->pci_cachesize = 0; 934 } 935 936 /* 937 * We cannot perform ULTRA speeds without the presence 938 * of the external precision resistor. 939 */ 940 if ((ahc->features & AHC_ULTRA) != 0) { 941 uint32_t devconfig; 942 943 devconfig = aic_pci_read_config(ahc->dev_softc, 944 DEVCONFIG, /*bytes*/4); 945 if ((devconfig & REXTVALID) == 0) 946 ahc->features &= ~AHC_ULTRA; 947 } 948 949 /* See if we have a SEEPROM and perform auto-term */ 950 check_extport(ahc, &sxfrctl1); 951 952 /* 953 * Take the LED out of diagnostic mode 954 */ 955 sblkctl = ahc_inb(ahc, SBLKCTL); 956 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 957 958 if ((ahc->features & AHC_ULTRA2) != 0) { 959 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 960 } else { 961 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 962 } 963 964 if (ahc->flags & AHC_USEDEFAULTS) { 965 /* 966 * PCI Adapter default setup 967 * Should only be used if the adapter does not have 968 * a SEEPROM. 969 */ 970 /* See if someone else set us up already */ 971 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 972 && scsiseq != 0) { 973 printf("%s: Using left over BIOS settings\n", 974 ahc_name(ahc)); 975 ahc->flags &= ~AHC_USEDEFAULTS; 976 ahc->flags |= AHC_BIOS_ENABLED; 977 } else { 978 /* 979 * Assume only one connector and always turn 980 * on termination. 981 */ 982 our_id = 0x07; 983 sxfrctl1 = STPWEN; 984 } 985 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 986 987 ahc->our_id = our_id; 988 } 989 990 /* 991 * Take a look to see if we have external SRAM. 992 * We currently do not attempt to use SRAM that is 993 * shared among multiple controllers. 994 */ 995 ahc_probe_ext_scbram(ahc); 996 997 /* 998 * Record our termination setting for the 999 * generic initialization routine. 1000 */ 1001 if ((sxfrctl1 & STPWEN) != 0) 1002 ahc->flags |= AHC_TERM_ENB_A; 1003 1004 /* 1005 * Save chip register configuration data for chip resets 1006 * that occur during runtime and resume events. 1007 */ 1008 ahc->bus_softc.pci_softc.devconfig = 1009 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1010 ahc->bus_softc.pci_softc.command = 1011 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 1012 ahc->bus_softc.pci_softc.csize_lattime = 1013 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 1014 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1015 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 1016 if ((ahc->features & AHC_DT) != 0) { 1017 u_int sfunct; 1018 1019 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1020 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1021 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 1022 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 1023 ahc_outb(ahc, SFUNCT, sfunct); 1024 ahc->bus_softc.pci_softc.crccontrol1 = 1025 ahc_inb(ahc, CRCCONTROL1); 1026 } 1027 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1028 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 1029 1030 if ((ahc->features & AHC_ULTRA2) != 0) 1031 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 1032 1033 /* Core initialization */ 1034 error = ahc_init(ahc); 1035 if (error != 0) 1036 return (error); 1037 1038 /* 1039 * Allow interrupts now that we are completely setup. 1040 */ 1041 error = ahc_pci_map_int(ahc); 1042 if (error != 0) 1043 return (error); 1044 1045 ahc_lock(ahc); 1046 /* 1047 * Link this softc in with all other ahc instances. 1048 */ 1049 ahc_softc_insert(ahc); 1050 ahc_unlock(ahc); 1051 return (0); 1052 } 1053 1054 /* 1055 * Test for the presence of external sram in an 1056 * "unshared" configuration. 1057 */ 1058 static int 1059 ahc_ext_scbram_present(struct ahc_softc *ahc) 1060 { 1061 u_int chip; 1062 int ramps; 1063 int single_user; 1064 uint32_t devconfig; 1065 1066 chip = ahc->chip & AHC_CHIPID_MASK; 1067 devconfig = aic_pci_read_config(ahc->dev_softc, 1068 DEVCONFIG, /*bytes*/4); 1069 single_user = (devconfig & MPORTMODE) != 0; 1070 1071 if ((ahc->features & AHC_ULTRA2) != 0) 1072 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1073 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1074 /* 1075 * External SCBRAM arbitration is flakey 1076 * on these chips. Unfortunately this means 1077 * we don't use the extra SCB ram space on the 1078 * 3940AUW. 1079 */ 1080 ramps = 0; 1081 else if (chip >= AHC_AIC7870) 1082 ramps = (devconfig & RAMPSM) != 0; 1083 else 1084 ramps = 0; 1085 1086 if (ramps && single_user) 1087 return (1); 1088 return (0); 1089 } 1090 1091 /* 1092 * Enable external scbram. 1093 */ 1094 static void 1095 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1096 int fast, int large) 1097 { 1098 uint32_t devconfig; 1099 1100 if (ahc->features & AHC_MULTI_FUNC) { 1101 /* 1102 * Set the SCB Base addr (highest address bit) 1103 * depending on which channel we are. 1104 */ 1105 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc)); 1106 } 1107 1108 ahc->flags &= ~AHC_LSCBS_ENABLED; 1109 if (large) 1110 ahc->flags |= AHC_LSCBS_ENABLED; 1111 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1112 if ((ahc->features & AHC_ULTRA2) != 0) { 1113 u_int dscommand0; 1114 1115 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1116 if (enable) 1117 dscommand0 &= ~INTSCBRAMSEL; 1118 else 1119 dscommand0 |= INTSCBRAMSEL; 1120 if (large) 1121 dscommand0 &= ~USCBSIZE32; 1122 else 1123 dscommand0 |= USCBSIZE32; 1124 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1125 } else { 1126 if (fast) 1127 devconfig &= ~EXTSCBTIME; 1128 else 1129 devconfig |= EXTSCBTIME; 1130 if (enable) 1131 devconfig &= ~SCBRAMSEL; 1132 else 1133 devconfig |= SCBRAMSEL; 1134 if (large) 1135 devconfig &= ~SCBSIZE32; 1136 else 1137 devconfig |= SCBSIZE32; 1138 } 1139 if (pcheck) 1140 devconfig |= EXTSCBPEN; 1141 else 1142 devconfig &= ~EXTSCBPEN; 1143 1144 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1145 } 1146 1147 /* 1148 * Take a look to see if we have external SRAM. 1149 * We currently do not attempt to use SRAM that is 1150 * shared among multiple controllers. 1151 */ 1152 static void 1153 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1154 { 1155 int num_scbs; 1156 int test_num_scbs; 1157 int enable; 1158 int pcheck; 1159 int fast; 1160 int large; 1161 1162 enable = FALSE; 1163 pcheck = FALSE; 1164 fast = FALSE; 1165 large = FALSE; 1166 num_scbs = 0; 1167 1168 if (ahc_ext_scbram_present(ahc) == 0) 1169 goto done; 1170 1171 /* 1172 * Probe for the best parameters to use. 1173 */ 1174 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1175 num_scbs = ahc_probe_scbs(ahc); 1176 if (num_scbs == 0) { 1177 /* The SRAM wasn't really present. */ 1178 goto done; 1179 } 1180 enable = TRUE; 1181 1182 /* 1183 * Clear any outstanding parity error 1184 * and ensure that parity error reporting 1185 * is enabled. 1186 */ 1187 ahc_outb(ahc, SEQCTL, 0); 1188 ahc_outb(ahc, CLRINT, CLRPARERR); 1189 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1190 1191 /* Now see if we can do parity */ 1192 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1193 num_scbs = ahc_probe_scbs(ahc); 1194 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1195 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1196 pcheck = TRUE; 1197 1198 /* Clear any resulting parity error */ 1199 ahc_outb(ahc, CLRINT, CLRPARERR); 1200 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1201 1202 /* Now see if we can do fast timing */ 1203 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1204 test_num_scbs = ahc_probe_scbs(ahc); 1205 if (test_num_scbs == num_scbs 1206 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1207 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1208 fast = TRUE; 1209 1210 /* 1211 * See if we can use large SCBs and still maintain 1212 * the same overall count of SCBs. 1213 */ 1214 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1215 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1216 test_num_scbs = ahc_probe_scbs(ahc); 1217 if (test_num_scbs >= num_scbs) { 1218 large = TRUE; 1219 num_scbs = test_num_scbs; 1220 if (num_scbs >= 64) { 1221 /* 1222 * We have enough space to move the 1223 * "busy targets table" into SCB space 1224 * and make it qualify all the way to the 1225 * lun level. 1226 */ 1227 ahc->flags |= AHC_SCB_BTT; 1228 } 1229 } 1230 } 1231 done: 1232 /* 1233 * Disable parity error reporting until we 1234 * can load instruction ram. 1235 */ 1236 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1237 /* Clear any latched parity error */ 1238 ahc_outb(ahc, CLRINT, CLRPARERR); 1239 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1240 if (bootverbose && enable) { 1241 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1242 ahc_name(ahc), fast ? "fast" : "slow", 1243 pcheck ? ", parity checking enabled" : "", 1244 large ? 64 : 32); 1245 } 1246 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1247 } 1248 1249 /* 1250 * Perform some simple tests that should catch situations where 1251 * our registers are invalidly mapped. 1252 */ 1253 int 1254 ahc_pci_test_register_access(struct ahc_softc *ahc) 1255 { 1256 int error; 1257 u_int status1; 1258 uint32_t cmd; 1259 uint8_t hcntrl; 1260 1261 error = EIO; 1262 1263 /* 1264 * Enable PCI error interrupt status, but suppress NMIs 1265 * generated by SERR raised due to target aborts. 1266 */ 1267 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1268 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1269 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1270 1271 /* 1272 * First a simple test to see if any 1273 * registers can be read. Reading 1274 * HCNTRL has no side effects and has 1275 * at least one bit that is guaranteed to 1276 * be zero so it is a good register to 1277 * use for this test. 1278 */ 1279 hcntrl = ahc_inb(ahc, HCNTRL); 1280 1281 if (hcntrl == 0xFF) 1282 goto fail; 1283 1284 if ((hcntrl & CHIPRST) != 0) { 1285 /* 1286 * The chip has not been initialized since 1287 * PCI/EISA/VLB bus reset. Don't trust 1288 * "left over BIOS data". 1289 */ 1290 ahc->flags |= AHC_NO_BIOS_INIT; 1291 } 1292 1293 /* 1294 * Next create a situation where write combining 1295 * or read prefetching could be initiated by the 1296 * CPU or host bridge. Our device does not support 1297 * either, so look for data corruption and/or flagged 1298 * PCI errors. First pause without causing another 1299 * chip reset. 1300 */ 1301 hcntrl &= ~CHIPRST; 1302 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1303 while (ahc_is_paused(ahc) == 0) 1304 ; 1305 1306 /* Clear any PCI errors that occurred before our driver attached. */ 1307 status1 = aic_pci_read_config(ahc->dev_softc, 1308 PCIR_STATUS + 1, /*bytes*/1); 1309 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1310 status1, /*bytes*/1); 1311 ahc_outb(ahc, CLRINT, CLRPARERR); 1312 1313 ahc_outb(ahc, SEQCTL, PERRORDIS); 1314 ahc_outb(ahc, SCBPTR, 0); 1315 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1316 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1317 goto fail; 1318 1319 status1 = aic_pci_read_config(ahc->dev_softc, 1320 PCIR_STATUS + 1, /*bytes*/1); 1321 if ((status1 & STA) != 0) 1322 goto fail; 1323 1324 error = 0; 1325 1326 fail: 1327 /* Silently clear any latched errors. */ 1328 status1 = aic_pci_read_config(ahc->dev_softc, 1329 PCIR_STATUS + 1, /*bytes*/1); 1330 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1331 status1, /*bytes*/1); 1332 ahc_outb(ahc, CLRINT, CLRPARERR); 1333 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1334 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1335 return (error); 1336 } 1337 1338 /* 1339 * Check the external port logic for a serial eeprom 1340 * and termination/cable detection contrls. 1341 */ 1342 static void 1343 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1344 { 1345 struct seeprom_descriptor sd; 1346 struct seeprom_config *sc; 1347 int have_seeprom; 1348 int have_autoterm; 1349 1350 sd.sd_ahc = ahc; 1351 sd.sd_control_offset = SEECTL; 1352 sd.sd_status_offset = SEECTL; 1353 sd.sd_dataout_offset = SEECTL; 1354 sc = ahc->seep_config; 1355 1356 /* 1357 * For some multi-channel devices, the c46 is simply too 1358 * small to work. For the other controller types, we can 1359 * get our information from either SEEPROM type. Set the 1360 * type to start our probe with accordingly. 1361 */ 1362 if (ahc->flags & AHC_LARGE_SEEPROM) 1363 sd.sd_chip = C56_66; 1364 else 1365 sd.sd_chip = C46; 1366 1367 sd.sd_MS = SEEMS; 1368 sd.sd_RDY = SEERDY; 1369 sd.sd_CS = SEECS; 1370 sd.sd_CK = SEECK; 1371 sd.sd_DO = SEEDO; 1372 sd.sd_DI = SEEDI; 1373 1374 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1375 if (have_seeprom) { 1376 if (bootverbose) 1377 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1378 1379 for (;;) { 1380 u_int start_addr; 1381 1382 start_addr = 32 * (ahc->channel - 'A'); 1383 1384 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1385 start_addr, 1386 sizeof(*sc)/2); 1387 1388 if (have_seeprom) 1389 have_seeprom = ahc_verify_cksum(sc); 1390 1391 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1392 if (bootverbose) { 1393 if (have_seeprom == 0) 1394 printf ("checksum error\n"); 1395 else 1396 printf ("done.\n"); 1397 } 1398 break; 1399 } 1400 sd.sd_chip = C56_66; 1401 } 1402 ahc_release_seeprom(&sd); 1403 1404 /* Remember the SEEPROM type for later */ 1405 if (sd.sd_chip == C56_66) 1406 ahc->flags |= AHC_LARGE_SEEPROM; 1407 } 1408 1409 if (!have_seeprom) { 1410 /* 1411 * Pull scratch ram settings and treat them as 1412 * if they are the contents of an seeprom if 1413 * the 'ADPT' signature is found in SCB2. 1414 * We manually compose the data as 16bit values 1415 * to avoid endian issues. 1416 */ 1417 ahc_outb(ahc, SCBPTR, 2); 1418 if (ahc_inb(ahc, SCB_BASE) == 'A' 1419 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1420 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1421 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1422 uint16_t *sc_data; 1423 int i; 1424 1425 sc_data = (uint16_t *)sc; 1426 for (i = 0; i < 32; i++, sc_data++) { 1427 int j; 1428 1429 j = i * 2; 1430 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1431 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1432 } 1433 have_seeprom = ahc_verify_cksum(sc); 1434 if (have_seeprom) 1435 ahc->flags |= AHC_SCB_CONFIG_USED; 1436 } 1437 /* 1438 * Clear any SCB parity errors in case this data and 1439 * its associated parity was not initialized by the BIOS 1440 */ 1441 ahc_outb(ahc, CLRINT, CLRPARERR); 1442 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1443 } 1444 1445 if (!have_seeprom) { 1446 if (bootverbose) 1447 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1448 ahc->flags |= AHC_USEDEFAULTS; 1449 free(ahc->seep_config, M_DEVBUF); 1450 ahc->seep_config = NULL; 1451 sc = NULL; 1452 } else { 1453 ahc_parse_pci_eeprom(ahc, sc); 1454 } 1455 1456 /* 1457 * Cards that have the external logic necessary to talk to 1458 * a SEEPROM, are almost certain to have the remaining logic 1459 * necessary for auto-termination control. This assumption 1460 * hasn't failed yet... 1461 */ 1462 have_autoterm = have_seeprom; 1463 1464 /* 1465 * Some low-cost chips have SEEPROM and auto-term control built 1466 * in, instead of using a GAL. They can tell us directly 1467 * if the termination logic is enabled. 1468 */ 1469 if ((ahc->features & AHC_SPIOCAP) != 0) { 1470 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1471 have_autoterm = FALSE; 1472 } 1473 1474 if (have_autoterm) { 1475 ahc->flags |= AHC_HAS_TERM_LOGIC; 1476 ahc_acquire_seeprom(ahc, &sd); 1477 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1478 ahc_release_seeprom(&sd); 1479 } else if (have_seeprom) { 1480 *sxfrctl1 &= ~STPWEN; 1481 if ((sc->adapter_control & CFSTERM) != 0) 1482 *sxfrctl1 |= STPWEN; 1483 if (bootverbose) 1484 printf("%s: Low byte termination %sabled\n", 1485 ahc_name(ahc), 1486 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1487 } 1488 } 1489 1490 static void 1491 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1492 { 1493 /* 1494 * Put the data we've collected down into SRAM 1495 * where ahc_init will find it. 1496 */ 1497 int i; 1498 int max_targ = sc->max_targets & CFMAXTARG; 1499 u_int scsi_conf; 1500 uint16_t discenable; 1501 uint16_t ultraenb; 1502 1503 discenable = 0; 1504 ultraenb = 0; 1505 if ((sc->adapter_control & CFULTRAEN) != 0) { 1506 /* 1507 * Determine if this adapter has a "newstyle" 1508 * SEEPROM format. 1509 */ 1510 for (i = 0; i < max_targ; i++) { 1511 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1512 ahc->flags |= AHC_NEWEEPROM_FMT; 1513 break; 1514 } 1515 } 1516 } 1517 1518 for (i = 0; i < max_targ; i++) { 1519 u_int scsirate; 1520 uint16_t target_mask; 1521 1522 target_mask = 0x01 << i; 1523 if (sc->device_flags[i] & CFDISC) 1524 discenable |= target_mask; 1525 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1526 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1527 ultraenb |= target_mask; 1528 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1529 ultraenb |= target_mask; 1530 } 1531 if ((sc->device_flags[i] & CFXFER) == 0x04 1532 && (ultraenb & target_mask) != 0) { 1533 /* Treat 10MHz as a non-ultra speed */ 1534 sc->device_flags[i] &= ~CFXFER; 1535 ultraenb &= ~target_mask; 1536 } 1537 if ((ahc->features & AHC_ULTRA2) != 0) { 1538 u_int offset; 1539 1540 if (sc->device_flags[i] & CFSYNCH) 1541 offset = MAX_OFFSET_ULTRA2; 1542 else 1543 offset = 0; 1544 ahc_outb(ahc, TARG_OFFSET + i, offset); 1545 1546 /* 1547 * The ultra enable bits contain the 1548 * high bit of the ultra2 sync rate 1549 * field. 1550 */ 1551 scsirate = (sc->device_flags[i] & CFXFER) 1552 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1553 if (sc->device_flags[i] & CFWIDEB) 1554 scsirate |= WIDEXFER; 1555 } else { 1556 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1557 if (sc->device_flags[i] & CFSYNCH) 1558 scsirate |= SOFS; 1559 if (sc->device_flags[i] & CFWIDEB) 1560 scsirate |= WIDEXFER; 1561 } 1562 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1563 } 1564 ahc->our_id = sc->brtime_id & CFSCSIID; 1565 1566 scsi_conf = (ahc->our_id & 0x7); 1567 if (sc->adapter_control & CFSPARITY) 1568 scsi_conf |= ENSPCHK; 1569 if (sc->adapter_control & CFRESETB) 1570 scsi_conf |= RESET_SCSI; 1571 1572 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1573 1574 if (sc->bios_control & CFEXTEND) 1575 ahc->flags |= AHC_EXTENDED_TRANS_A; 1576 1577 if (sc->bios_control & CFBIOSEN) 1578 ahc->flags |= AHC_BIOS_ENABLED; 1579 if (ahc->features & AHC_ULTRA 1580 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1581 /* Should we enable Ultra mode? */ 1582 if (!(sc->adapter_control & CFULTRAEN)) 1583 /* Treat us as a non-ultra card */ 1584 ultraenb = 0; 1585 } 1586 1587 if (sc->signature == CFSIGNATURE 1588 || sc->signature == CFSIGNATURE2) { 1589 uint32_t devconfig; 1590 1591 /* Honor the STPWLEVEL settings */ 1592 devconfig = aic_pci_read_config(ahc->dev_softc, 1593 DEVCONFIG, /*bytes*/4); 1594 devconfig &= ~STPWLEVEL; 1595 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1596 devconfig |= STPWLEVEL; 1597 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, 1598 devconfig, /*bytes*/4); 1599 } 1600 /* Set SCSICONF info */ 1601 ahc_outb(ahc, SCSICONF, scsi_conf); 1602 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1603 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1604 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1605 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1606 } 1607 1608 static void 1609 configure_termination(struct ahc_softc *ahc, 1610 struct seeprom_descriptor *sd, 1611 u_int adapter_control, 1612 u_int *sxfrctl1) 1613 { 1614 uint8_t brddat; 1615 1616 brddat = 0; 1617 1618 /* 1619 * Update the settings in sxfrctl1 to match the 1620 * termination settings 1621 */ 1622 *sxfrctl1 = 0; 1623 1624 /* 1625 * SEECS must be on for the GALS to latch 1626 * the data properly. Be sure to leave MS 1627 * on or we will release the seeprom. 1628 */ 1629 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1630 if ((adapter_control & CFAUTOTERM) != 0 1631 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1632 int internal50_present; 1633 int internal68_present; 1634 int externalcable_present; 1635 int eeprom_present; 1636 int enableSEC_low; 1637 int enableSEC_high; 1638 int enablePRI_low; 1639 int enablePRI_high; 1640 int sum; 1641 1642 enableSEC_low = 0; 1643 enableSEC_high = 0; 1644 enablePRI_low = 0; 1645 enablePRI_high = 0; 1646 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1647 ahc_new_term_detect(ahc, &enableSEC_low, 1648 &enableSEC_high, 1649 &enablePRI_low, 1650 &enablePRI_high, 1651 &eeprom_present); 1652 if ((adapter_control & CFSEAUTOTERM) == 0) { 1653 if (bootverbose) 1654 printf("%s: Manual SE Termination\n", 1655 ahc_name(ahc)); 1656 enableSEC_low = (adapter_control & CFSELOWTERM); 1657 enableSEC_high = 1658 (adapter_control & CFSEHIGHTERM); 1659 } 1660 if ((adapter_control & CFAUTOTERM) == 0) { 1661 if (bootverbose) 1662 printf("%s: Manual LVD Termination\n", 1663 ahc_name(ahc)); 1664 enablePRI_low = (adapter_control & CFSTERM); 1665 enablePRI_high = (adapter_control & CFWSTERM); 1666 } 1667 /* Make the table calculations below happy */ 1668 internal50_present = 0; 1669 internal68_present = 1; 1670 externalcable_present = 1; 1671 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1672 aic785X_cable_detect(ahc, &internal50_present, 1673 &externalcable_present, 1674 &eeprom_present); 1675 /* Can never support a wide connector. */ 1676 internal68_present = 0; 1677 } else { 1678 aic787X_cable_detect(ahc, &internal50_present, 1679 &internal68_present, 1680 &externalcable_present, 1681 &eeprom_present); 1682 } 1683 1684 if ((ahc->features & AHC_WIDE) == 0) 1685 internal68_present = 0; 1686 1687 if (bootverbose 1688 && (ahc->features & AHC_ULTRA2) == 0) { 1689 printf("%s: internal 50 cable %s present", 1690 ahc_name(ahc), 1691 internal50_present ? "is":"not"); 1692 1693 if ((ahc->features & AHC_WIDE) != 0) 1694 printf(", internal 68 cable %s present", 1695 internal68_present ? "is":"not"); 1696 printf("\n%s: external cable %s present\n", 1697 ahc_name(ahc), 1698 externalcable_present ? "is":"not"); 1699 } 1700 if (bootverbose) 1701 printf("%s: BIOS eeprom %s present\n", 1702 ahc_name(ahc), eeprom_present ? "is" : "not"); 1703 1704 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1705 /* 1706 * The 50 pin connector is a separate bus, 1707 * so force it to always be terminated. 1708 * In the future, perform current sensing 1709 * to determine if we are in the middle of 1710 * a properly terminated bus. 1711 */ 1712 internal50_present = 0; 1713 } 1714 1715 /* 1716 * Now set the termination based on what 1717 * we found. 1718 * Flash Enable = BRDDAT7 1719 * Secondary High Term Enable = BRDDAT6 1720 * Secondary Low Term Enable = BRDDAT5 (7890) 1721 * Primary High Term Enable = BRDDAT4 (7890) 1722 */ 1723 if ((ahc->features & AHC_ULTRA2) == 0 1724 && (internal50_present != 0) 1725 && (internal68_present != 0) 1726 && (externalcable_present != 0)) { 1727 printf("%s: Illegal cable configuration!!. " 1728 "Only two connectors on the " 1729 "adapter may be used at a " 1730 "time!\n", ahc_name(ahc)); 1731 1732 /* 1733 * Pretend there are no cables in the hope 1734 * that having all of the termination on 1735 * gives us a more stable bus. 1736 */ 1737 internal50_present = 0; 1738 internal68_present = 0; 1739 externalcable_present = 0; 1740 } 1741 1742 if ((ahc->features & AHC_WIDE) != 0 1743 && ((externalcable_present == 0) 1744 || (internal68_present == 0) 1745 || (enableSEC_high != 0))) { 1746 brddat |= BRDDAT6; 1747 if (bootverbose) { 1748 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1749 printf("%s: 68 pin termination " 1750 "Enabled\n", ahc_name(ahc)); 1751 else 1752 printf("%s: %sHigh byte termination " 1753 "Enabled\n", ahc_name(ahc), 1754 enableSEC_high ? "Secondary " 1755 : ""); 1756 } 1757 } 1758 1759 sum = internal50_present + internal68_present 1760 + externalcable_present; 1761 if (sum < 2 || (enableSEC_low != 0)) { 1762 if ((ahc->features & AHC_ULTRA2) != 0) 1763 brddat |= BRDDAT5; 1764 else 1765 *sxfrctl1 |= STPWEN; 1766 if (bootverbose) { 1767 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1768 printf("%s: 50 pin termination " 1769 "Enabled\n", ahc_name(ahc)); 1770 else 1771 printf("%s: %sLow byte termination " 1772 "Enabled\n", ahc_name(ahc), 1773 enableSEC_low ? "Secondary " 1774 : ""); 1775 } 1776 } 1777 1778 if (enablePRI_low != 0) { 1779 *sxfrctl1 |= STPWEN; 1780 if (bootverbose) 1781 printf("%s: Primary Low Byte termination " 1782 "Enabled\n", ahc_name(ahc)); 1783 } 1784 1785 /* 1786 * Setup STPWEN before setting up the rest of 1787 * the termination per the tech note on the U160 cards. 1788 */ 1789 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1790 1791 if (enablePRI_high != 0) { 1792 brddat |= BRDDAT4; 1793 if (bootverbose) 1794 printf("%s: Primary High Byte " 1795 "termination Enabled\n", 1796 ahc_name(ahc)); 1797 } 1798 1799 write_brdctl(ahc, brddat); 1800 1801 } else { 1802 if ((adapter_control & CFSTERM) != 0) { 1803 *sxfrctl1 |= STPWEN; 1804 1805 if (bootverbose) 1806 printf("%s: %sLow byte termination Enabled\n", 1807 ahc_name(ahc), 1808 (ahc->features & AHC_ULTRA2) ? "Primary " 1809 : ""); 1810 } 1811 1812 if ((adapter_control & CFWSTERM) != 0 1813 && (ahc->features & AHC_WIDE) != 0) { 1814 brddat |= BRDDAT6; 1815 if (bootverbose) 1816 printf("%s: %sHigh byte termination Enabled\n", 1817 ahc_name(ahc), 1818 (ahc->features & AHC_ULTRA2) 1819 ? "Secondary " : ""); 1820 } 1821 1822 /* 1823 * Setup STPWEN before setting up the rest of 1824 * the termination per the tech note on the U160 cards. 1825 */ 1826 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1827 1828 if ((ahc->features & AHC_WIDE) != 0) 1829 write_brdctl(ahc, brddat); 1830 } 1831 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1832 } 1833 1834 static void 1835 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1836 int *enableSEC_high, int *enablePRI_low, 1837 int *enablePRI_high, int *eeprom_present) 1838 { 1839 uint8_t brdctl; 1840 1841 /* 1842 * BRDDAT7 = Eeprom 1843 * BRDDAT6 = Enable Secondary High Byte termination 1844 * BRDDAT5 = Enable Secondary Low Byte termination 1845 * BRDDAT4 = Enable Primary high byte termination 1846 * BRDDAT3 = Enable Primary low byte termination 1847 */ 1848 brdctl = read_brdctl(ahc); 1849 *eeprom_present = brdctl & BRDDAT7; 1850 *enableSEC_high = (brdctl & BRDDAT6); 1851 *enableSEC_low = (brdctl & BRDDAT5); 1852 *enablePRI_high = (brdctl & BRDDAT4); 1853 *enablePRI_low = (brdctl & BRDDAT3); 1854 } 1855 1856 static void 1857 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1858 int *internal68_present, int *externalcable_present, 1859 int *eeprom_present) 1860 { 1861 uint8_t brdctl; 1862 1863 /* 1864 * First read the status of our cables. 1865 * Set the rom bank to 0 since the 1866 * bank setting serves as a multiplexor 1867 * for the cable detection logic. 1868 * BRDDAT5 controls the bank switch. 1869 */ 1870 write_brdctl(ahc, 0); 1871 1872 /* 1873 * Now read the state of the internal 1874 * connectors. BRDDAT6 is INT50 and 1875 * BRDDAT7 is INT68. 1876 */ 1877 brdctl = read_brdctl(ahc); 1878 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1879 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1880 1881 /* 1882 * Set the rom bank to 1 and determine 1883 * the other signals. 1884 */ 1885 write_brdctl(ahc, BRDDAT5); 1886 1887 /* 1888 * Now read the state of the external 1889 * connectors. BRDDAT6 is EXT68 and 1890 * BRDDAT7 is EPROMPS. 1891 */ 1892 brdctl = read_brdctl(ahc); 1893 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1894 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1895 } 1896 1897 static void 1898 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1899 int *externalcable_present, int *eeprom_present) 1900 { 1901 uint8_t brdctl; 1902 uint8_t spiocap; 1903 1904 spiocap = ahc_inb(ahc, SPIOCAP); 1905 spiocap &= ~SOFTCMDEN; 1906 spiocap |= EXT_BRDCTL; 1907 ahc_outb(ahc, SPIOCAP, spiocap); 1908 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1909 ahc_flush_device_writes(ahc); 1910 aic_delay(500); 1911 ahc_outb(ahc, BRDCTL, 0); 1912 ahc_flush_device_writes(ahc); 1913 aic_delay(500); 1914 brdctl = ahc_inb(ahc, BRDCTL); 1915 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1916 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1917 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1918 } 1919 1920 int 1921 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1922 { 1923 int wait; 1924 1925 if ((ahc->features & AHC_SPIOCAP) != 0 1926 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1927 return (0); 1928 1929 /* 1930 * Request access of the memory port. When access is 1931 * granted, SEERDY will go high. We use a 1 second 1932 * timeout which should be near 1 second more than 1933 * is needed. Reason: after the chip reset, there 1934 * should be no contention. 1935 */ 1936 SEEPROM_OUTB(sd, sd->sd_MS); 1937 wait = 1000; /* 1 second timeout in msec */ 1938 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1939 aic_delay(1000); /* delay 1 msec */ 1940 } 1941 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1942 SEEPROM_OUTB(sd, 0); 1943 return (0); 1944 } 1945 return(1); 1946 } 1947 1948 void 1949 ahc_release_seeprom(struct seeprom_descriptor *sd) 1950 { 1951 /* Release access to the memory port and the serial EEPROM. */ 1952 SEEPROM_OUTB(sd, 0); 1953 } 1954 1955 static void 1956 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1957 { 1958 uint8_t brdctl; 1959 1960 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1961 brdctl = BRDSTB; 1962 if (ahc->channel == 'B') 1963 brdctl |= BRDCS; 1964 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1965 brdctl = 0; 1966 } else { 1967 brdctl = BRDSTB|BRDCS; 1968 } 1969 ahc_outb(ahc, BRDCTL, brdctl); 1970 ahc_flush_device_writes(ahc); 1971 brdctl |= value; 1972 ahc_outb(ahc, BRDCTL, brdctl); 1973 ahc_flush_device_writes(ahc); 1974 if ((ahc->features & AHC_ULTRA2) != 0) 1975 brdctl |= BRDSTB_ULTRA2; 1976 else 1977 brdctl &= ~BRDSTB; 1978 ahc_outb(ahc, BRDCTL, brdctl); 1979 ahc_flush_device_writes(ahc); 1980 if ((ahc->features & AHC_ULTRA2) != 0) 1981 brdctl = 0; 1982 else 1983 brdctl &= ~BRDCS; 1984 ahc_outb(ahc, BRDCTL, brdctl); 1985 } 1986 1987 static uint8_t 1988 read_brdctl(struct ahc_softc *ahc) 1989 { 1990 uint8_t brdctl; 1991 uint8_t value; 1992 1993 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1994 brdctl = BRDRW; 1995 if (ahc->channel == 'B') 1996 brdctl |= BRDCS; 1997 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1998 brdctl = BRDRW_ULTRA2; 1999 } else { 2000 brdctl = BRDRW|BRDCS; 2001 } 2002 ahc_outb(ahc, BRDCTL, brdctl); 2003 ahc_flush_device_writes(ahc); 2004 value = ahc_inb(ahc, BRDCTL); 2005 ahc_outb(ahc, BRDCTL, 0); 2006 return (value); 2007 } 2008 2009 static void 2010 ahc_pci_intr(struct ahc_softc *ahc) 2011 { 2012 u_int error; 2013 u_int status1; 2014 2015 error = ahc_inb(ahc, ERROR); 2016 if ((error & PCIERRSTAT) == 0) 2017 return; 2018 2019 status1 = aic_pci_read_config(ahc->dev_softc, 2020 PCIR_STATUS + 1, /*bytes*/1); 2021 2022 if ((status1 & ~DPE) != 0 2023 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) { 2024 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 2025 ahc_name(ahc), 2026 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 2027 } 2028 2029 if (status1 & DPE 2030 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) { 2031 ahc->pci_target_perr_count++; 2032 printf("%s: Data Parity Error Detected during address " 2033 "or write data phase\n", ahc_name(ahc)); 2034 } 2035 if (status1 & SSE) { 2036 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 2037 } 2038 if (status1 & RMA) { 2039 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 2040 } 2041 if (status1 & RTA) { 2042 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 2043 } 2044 if (status1 & STA) { 2045 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 2046 } 2047 if (status1 & DPR) { 2048 printf("%s: Data Parity Error has been reported via PERR#\n", 2049 ahc_name(ahc)); 2050 } 2051 2052 /* Clear latched errors. */ 2053 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 2054 status1, /*bytes*/1); 2055 2056 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 2057 printf("%s: Latched PCIERR interrupt with " 2058 "no status bits set\n", ahc_name(ahc)); 2059 } else { 2060 ahc_outb(ahc, CLRINT, CLRPARERR); 2061 } 2062 2063 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH 2064 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) { 2065 printf( 2066 "%s: WARNING WARNING WARNING WARNING\n" 2067 "%s: Too many PCI parity errors observed as a target.\n" 2068 "%s: Some device on this PCI bus is generating bad parity.\n" 2069 "%s: This is an error *observed by*, not *generated by*, %s.\n" 2070 "%s: PCI parity error checking has been disabled.\n" 2071 "%s: WARNING WARNING WARNING WARNING\n", 2072 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 2073 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 2074 ahc_name(ahc)); 2075 ahc->seqctl |= FAILDIS; 2076 ahc->flags |= AHC_DISABLE_PCI_PERR; 2077 ahc_outb(ahc, SEQCTL, ahc->seqctl); 2078 } 2079 ahc_unpause(ahc); 2080 } 2081 2082 static int 2083 ahc_pci_chip_init(struct ahc_softc *ahc) 2084 { 2085 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 2086 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 2087 if ((ahc->features & AHC_DT) != 0) { 2088 u_int sfunct; 2089 2090 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 2091 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 2092 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 2093 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 2094 ahc_outb(ahc, SFUNCT, sfunct); 2095 ahc_outb(ahc, CRCCONTROL1, 2096 ahc->bus_softc.pci_softc.crccontrol1); 2097 } 2098 if ((ahc->features & AHC_MULTI_FUNC) != 0) 2099 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 2100 2101 if ((ahc->features & AHC_ULTRA2) != 0) 2102 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2103 2104 return (ahc_chip_init(ahc)); 2105 } 2106 2107 static int 2108 ahc_pci_suspend(struct ahc_softc *ahc) 2109 { 2110 return (ahc_suspend(ahc)); 2111 } 2112 2113 static int 2114 ahc_pci_resume(struct ahc_softc *ahc) 2115 { 2116 2117 aic_power_state_change(ahc, AIC_POWER_STATE_D0); 2118 2119 /* 2120 * We assume that the OS has restored our register 2121 * mappings, etc. Just update the config space registers 2122 * that the OS doesn't know about and rely on our chip 2123 * reset handler to handle the rest. 2124 */ 2125 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, 2126 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4); 2127 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 2128 ahc->bus_softc.pci_softc.command, /*bytes*/1); 2129 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 2130 ahc->bus_softc.pci_softc.csize_lattime, 2131 /*bytes*/1); 2132 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2133 struct seeprom_descriptor sd; 2134 u_int sxfrctl1; 2135 2136 sd.sd_ahc = ahc; 2137 sd.sd_control_offset = SEECTL; 2138 sd.sd_status_offset = SEECTL; 2139 sd.sd_dataout_offset = SEECTL; 2140 2141 ahc_acquire_seeprom(ahc, &sd); 2142 configure_termination(ahc, &sd, 2143 ahc->seep_config->adapter_control, 2144 &sxfrctl1); 2145 ahc_release_seeprom(&sd); 2146 } 2147 return (ahc_resume(ahc)); 2148 } 2149 2150 static int 2151 ahc_aic785X_setup(struct ahc_softc *ahc) 2152 { 2153 aic_dev_softc_t pci; 2154 uint8_t rev; 2155 2156 pci = ahc->dev_softc; 2157 ahc->channel = 'A'; 2158 ahc->chip = AHC_AIC7850; 2159 ahc->features = AHC_AIC7850_FE; 2160 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2161 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2162 if (rev >= 1) 2163 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2164 ahc->instruction_ram_size = 512; 2165 return (0); 2166 } 2167 2168 static int 2169 ahc_aic7860_setup(struct ahc_softc *ahc) 2170 { 2171 aic_dev_softc_t pci; 2172 uint8_t rev; 2173 2174 pci = ahc->dev_softc; 2175 ahc->channel = 'A'; 2176 ahc->chip = AHC_AIC7860; 2177 ahc->features = AHC_AIC7860_FE; 2178 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2179 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2180 if (rev >= 1) 2181 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2182 ahc->instruction_ram_size = 512; 2183 return (0); 2184 } 2185 2186 static int 2187 ahc_apa1480_setup(struct ahc_softc *ahc) 2188 { 2189 int error; 2190 2191 error = ahc_aic7860_setup(ahc); 2192 if (error != 0) 2193 return (error); 2194 ahc->features |= AHC_REMOVABLE; 2195 return (0); 2196 } 2197 2198 static int 2199 ahc_aic7870_setup(struct ahc_softc *ahc) 2200 { 2201 2202 ahc->channel = 'A'; 2203 ahc->chip = AHC_AIC7870; 2204 ahc->features = AHC_AIC7870_FE; 2205 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2206 ahc->instruction_ram_size = 512; 2207 return (0); 2208 } 2209 2210 static int 2211 ahc_aha394X_setup(struct ahc_softc *ahc) 2212 { 2213 int error; 2214 2215 error = ahc_aic7870_setup(ahc); 2216 if (error == 0) 2217 error = ahc_aha394XX_setup(ahc); 2218 return (error); 2219 } 2220 2221 static int 2222 ahc_aha398X_setup(struct ahc_softc *ahc) 2223 { 2224 int error; 2225 2226 error = ahc_aic7870_setup(ahc); 2227 if (error == 0) 2228 error = ahc_aha398XX_setup(ahc); 2229 return (error); 2230 } 2231 2232 static int 2233 ahc_aha494X_setup(struct ahc_softc *ahc) 2234 { 2235 int error; 2236 2237 error = ahc_aic7870_setup(ahc); 2238 if (error == 0) 2239 error = ahc_aha494XX_setup(ahc); 2240 return (error); 2241 } 2242 2243 static int 2244 ahc_aic7880_setup(struct ahc_softc *ahc) 2245 { 2246 aic_dev_softc_t pci; 2247 uint8_t rev; 2248 2249 pci = ahc->dev_softc; 2250 ahc->channel = 'A'; 2251 ahc->chip = AHC_AIC7880; 2252 ahc->features = AHC_AIC7880_FE; 2253 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2254 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2255 if (rev >= 1) { 2256 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2257 } else { 2258 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2259 } 2260 ahc->instruction_ram_size = 512; 2261 return (0); 2262 } 2263 2264 static int 2265 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2266 { 2267 2268 ahc->flags |= AHC_INT50_SPEEDFLEX; 2269 return (ahc_aic7880_setup(ahc)); 2270 } 2271 2272 static int 2273 ahc_aha394XU_setup(struct ahc_softc *ahc) 2274 { 2275 int error; 2276 2277 error = ahc_aic7880_setup(ahc); 2278 if (error == 0) 2279 error = ahc_aha394XX_setup(ahc); 2280 return (error); 2281 } 2282 2283 static int 2284 ahc_aha398XU_setup(struct ahc_softc *ahc) 2285 { 2286 int error; 2287 2288 error = ahc_aic7880_setup(ahc); 2289 if (error == 0) 2290 error = ahc_aha398XX_setup(ahc); 2291 return (error); 2292 } 2293 2294 static int 2295 ahc_aic7890_setup(struct ahc_softc *ahc) 2296 { 2297 aic_dev_softc_t pci; 2298 uint8_t rev; 2299 2300 pci = ahc->dev_softc; 2301 ahc->channel = 'A'; 2302 ahc->chip = AHC_AIC7890; 2303 ahc->features = AHC_AIC7890_FE; 2304 ahc->flags |= AHC_NEWEEPROM_FMT; 2305 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2306 if (rev == 0) 2307 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2308 ahc->instruction_ram_size = 768; 2309 return (0); 2310 } 2311 2312 static int 2313 ahc_aic7892_setup(struct ahc_softc *ahc) 2314 { 2315 2316 ahc->channel = 'A'; 2317 ahc->chip = AHC_AIC7892; 2318 ahc->features = AHC_AIC7892_FE; 2319 ahc->flags |= AHC_NEWEEPROM_FMT; 2320 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2321 ahc->instruction_ram_size = 1024; 2322 return (0); 2323 } 2324 2325 static int 2326 ahc_aic7895_setup(struct ahc_softc *ahc) 2327 { 2328 aic_dev_softc_t pci; 2329 uint8_t rev; 2330 2331 pci = ahc->dev_softc; 2332 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A'; 2333 /* 2334 * The 'C' revision of the aic7895 has a few additional features. 2335 */ 2336 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2337 if (rev >= 4) { 2338 ahc->chip = AHC_AIC7895C; 2339 ahc->features = AHC_AIC7895C_FE; 2340 } else { 2341 u_int command; 2342 2343 ahc->chip = AHC_AIC7895; 2344 ahc->features = AHC_AIC7895_FE; 2345 2346 /* 2347 * The BIOS disables the use of MWI transactions 2348 * since it does not have the MWI bug work around 2349 * we have. Disabling MWI reduces performance, so 2350 * turn it on again. 2351 */ 2352 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2353 command |= PCIM_CMD_MWRICEN; 2354 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2355 ahc->bugs |= AHC_PCI_MWI_BUG; 2356 } 2357 /* 2358 * XXX Does CACHETHEN really not work??? What about PCI retry? 2359 * on C level chips. Need to test, but for now, play it safe. 2360 */ 2361 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2362 | AHC_CACHETHEN_BUG; 2363 2364 #if 0 2365 uint32_t devconfig; 2366 2367 /* 2368 * Cachesize must also be zero due to stray DAC 2369 * problem when sitting behind some bridges. 2370 */ 2371 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2372 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2373 devconfig |= MRDCEN; 2374 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2375 #endif 2376 ahc->flags |= AHC_NEWEEPROM_FMT; 2377 ahc->instruction_ram_size = 512; 2378 return (0); 2379 } 2380 2381 static int 2382 ahc_aic7896_setup(struct ahc_softc *ahc) 2383 { 2384 aic_dev_softc_t pci; 2385 2386 pci = ahc->dev_softc; 2387 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A'; 2388 ahc->chip = AHC_AIC7896; 2389 ahc->features = AHC_AIC7896_FE; 2390 ahc->flags |= AHC_NEWEEPROM_FMT; 2391 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2392 ahc->instruction_ram_size = 768; 2393 return (0); 2394 } 2395 2396 static int 2397 ahc_aic7899_setup(struct ahc_softc *ahc) 2398 { 2399 aic_dev_softc_t pci; 2400 2401 pci = ahc->dev_softc; 2402 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A'; 2403 ahc->chip = AHC_AIC7899; 2404 ahc->features = AHC_AIC7899_FE; 2405 ahc->flags |= AHC_NEWEEPROM_FMT; 2406 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2407 ahc->instruction_ram_size = 1024; 2408 return (0); 2409 } 2410 2411 static int 2412 ahc_aha29160C_setup(struct ahc_softc *ahc) 2413 { 2414 int error; 2415 2416 error = ahc_aic7899_setup(ahc); 2417 if (error != 0) 2418 return (error); 2419 ahc->features |= AHC_REMOVABLE; 2420 return (0); 2421 } 2422 2423 static int 2424 ahc_raid_setup(struct ahc_softc *ahc) 2425 { 2426 printf("RAID functionality unsupported\n"); 2427 return (ENXIO); 2428 } 2429 2430 static int 2431 ahc_aha394XX_setup(struct ahc_softc *ahc) 2432 { 2433 aic_dev_softc_t pci; 2434 2435 pci = ahc->dev_softc; 2436 switch (aic_get_pci_slot(pci)) { 2437 case AHC_394X_SLOT_CHANNEL_A: 2438 ahc->channel = 'A'; 2439 break; 2440 case AHC_394X_SLOT_CHANNEL_B: 2441 ahc->channel = 'B'; 2442 break; 2443 default: 2444 printf("adapter at unexpected slot %d\n" 2445 "unable to map to a channel\n", 2446 aic_get_pci_slot(pci)); 2447 ahc->channel = 'A'; 2448 } 2449 return (0); 2450 } 2451 2452 static int 2453 ahc_aha398XX_setup(struct ahc_softc *ahc) 2454 { 2455 aic_dev_softc_t pci; 2456 2457 pci = ahc->dev_softc; 2458 switch (aic_get_pci_slot(pci)) { 2459 case AHC_398X_SLOT_CHANNEL_A: 2460 ahc->channel = 'A'; 2461 break; 2462 case AHC_398X_SLOT_CHANNEL_B: 2463 ahc->channel = 'B'; 2464 break; 2465 case AHC_398X_SLOT_CHANNEL_C: 2466 ahc->channel = 'C'; 2467 break; 2468 default: 2469 printf("adapter at unexpected slot %d\n" 2470 "unable to map to a channel\n", 2471 aic_get_pci_slot(pci)); 2472 ahc->channel = 'A'; 2473 break; 2474 } 2475 ahc->flags |= AHC_LARGE_SEEPROM; 2476 return (0); 2477 } 2478 2479 static int 2480 ahc_aha494XX_setup(struct ahc_softc *ahc) 2481 { 2482 aic_dev_softc_t pci; 2483 2484 pci = ahc->dev_softc; 2485 switch (aic_get_pci_slot(pci)) { 2486 case AHC_494X_SLOT_CHANNEL_A: 2487 ahc->channel = 'A'; 2488 break; 2489 case AHC_494X_SLOT_CHANNEL_B: 2490 ahc->channel = 'B'; 2491 break; 2492 case AHC_494X_SLOT_CHANNEL_C: 2493 ahc->channel = 'C'; 2494 break; 2495 case AHC_494X_SLOT_CHANNEL_D: 2496 ahc->channel = 'D'; 2497 break; 2498 default: 2499 printf("adapter at unexpected slot %d\n" 2500 "unable to map to a channel\n", 2501 aic_get_pci_slot(pci)); 2502 ahc->channel = 'A'; 2503 } 2504 ahc->flags |= AHC_LARGE_SEEPROM; 2505 return (0); 2506 }
Cache object: a7e92ac933a7b91d98975e6ef209d0e7
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]