1 /*-
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
43 */
44
45 #ifdef __linux__
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aic7xxx_93cx6.h"
49 #else
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD: releng/8.0/sys/dev/aic7xxx/aic7xxx_pci.c 168807 2007-04-17 06:26:25Z scottl $");
52 #include <dev/aic7xxx/aic7xxx_osm.h>
53 #include <dev/aic7xxx/aic7xxx_inline.h>
54 #include <dev/aic7xxx/aic7xxx_93cx6.h>
55 #endif
56
57 static __inline uint64_t
58 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
59 {
60 uint64_t id;
61
62 id = subvendor
63 | (subdevice << 16)
64 | ((uint64_t)vendor << 32)
65 | ((uint64_t)device << 48);
66
67 return (id);
68 }
69
70 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
71 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
72 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
73 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
74 #define ID_9005_SISL_ID 0x0005900500000000ull
75 #define ID_AIC7850 0x5078900400000000ull
76 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
77 #define ID_AIC7855 0x5578900400000000ull
78 #define ID_AIC7859 0x3860900400000000ull
79 #define ID_AHA_2930CU 0x3860900438699004ull
80 #define ID_AIC7860 0x6078900400000000ull
81 #define ID_AIC7860C 0x6078900478609004ull
82 #define ID_AHA_1480A 0x6075900400000000ull
83 #define ID_AHA_2940AU_0 0x6178900400000000ull
84 #define ID_AHA_2940AU_1 0x6178900478619004ull
85 #define ID_AHA_2940AU_CN 0x2178900478219004ull
86 #define ID_AHA_2930C_VAR 0x6038900438689004ull
87
88 #define ID_AIC7870 0x7078900400000000ull
89 #define ID_AHA_2940 0x7178900400000000ull
90 #define ID_AHA_3940 0x7278900400000000ull
91 #define ID_AHA_398X 0x7378900400000000ull
92 #define ID_AHA_2944 0x7478900400000000ull
93 #define ID_AHA_3944 0x7578900400000000ull
94 #define ID_AHA_4944 0x7678900400000000ull
95
96 #define ID_AIC7880 0x8078900400000000ull
97 #define ID_AIC7880_B 0x8078900478809004ull
98 #define ID_AHA_2940U 0x8178900400000000ull
99 #define ID_AHA_3940U 0x8278900400000000ull
100 #define ID_AHA_2944U 0x8478900400000000ull
101 #define ID_AHA_3944U 0x8578900400000000ull
102 #define ID_AHA_398XU 0x8378900400000000ull
103 #define ID_AHA_4944U 0x8678900400000000ull
104 #define ID_AHA_2940UB 0x8178900478819004ull
105 #define ID_AHA_2930U 0x8878900478889004ull
106 #define ID_AHA_2940U_PRO 0x8778900478879004ull
107 #define ID_AHA_2940U_CN 0x0078900478009004ull
108
109 #define ID_AIC7895 0x7895900478959004ull
110 #define ID_AIC7895_ARO 0x7890900478939004ull
111 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
112 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
113 #define ID_AHA_3940AU 0x7895900478929004ull
114 #define ID_AHA_3944AU 0x7895900478949004ull
115
116 #define ID_AIC7890 0x001F9005000F9005ull
117 #define ID_AIC7890_ARO 0x00139005000F9005ull
118 #define ID_AAA_131U2 0x0013900500039005ull
119 #define ID_AHA_2930U2 0x0011900501819005ull
120 #define ID_AHA_2940U2B 0x00109005A1009005ull
121 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
122 #define ID_AHA_2940U2 0x00109005A1809005ull
123 #define ID_AHA_2950U2B 0x00109005E1009005ull
124
125 #define ID_AIC7892 0x008F9005FFFF9005ull
126 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
127 #define ID_AHA_29160 0x00809005E2A09005ull
128 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
129 #define ID_AHA_29160N 0x0080900562A09005ull
130 #define ID_AHA_29160C 0x0080900562209005ull
131 #define ID_AHA_29160B 0x00809005E2209005ull
132 #define ID_AHA_19160B 0x0081900562A19005ull
133 #define ID_AHA_2915_30LP 0x0082900502109005ull
134
135 #define ID_AIC7896 0x005F9005FFFF9005ull
136 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
137 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
138 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
139 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
140 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
141
142 #define ID_AIC7899 0x00CF9005FFFF9005ull
143 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
144 #define ID_AHA_3960D 0x00C09005F6209005ull
145 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
146
147 #define ID_AIC7810 0x1078900400000000ull
148 #define ID_AIC7815 0x7815900400000000ull
149
150 #define DEVID_9005_TYPE(id) ((id) & 0xF)
151 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
152 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
153 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
154 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
155
156 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
157 #define DEVID_9005_MAXRATE_U160 0x0
158 #define DEVID_9005_MAXRATE_ULTRA2 0x1
159 #define DEVID_9005_MAXRATE_ULTRA 0x2
160 #define DEVID_9005_MAXRATE_FAST 0x3
161
162 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
163
164 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
165 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
166
167 #define SUBID_9005_TYPE(id) ((id) & 0xF)
168 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
169 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
170 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
171 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
172
173 #define SUBID_9005_TYPE_KNOWN(id) \
174 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
175 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
176 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
178
179 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
180 #define SUBID_9005_MAXRATE_ULTRA2 0x0
181 #define SUBID_9005_MAXRATE_ULTRA 0x1
182 #define SUBID_9005_MAXRATE_U160 0x2
183 #define SUBID_9005_MAXRATE_RESERVED 0x3
184
185 #define SUBID_9005_SEEPTYPE(id) \
186 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
187 ? ((id) & 0xC0) >> 6 \
188 : ((id) & 0x300) >> 8)
189 #define SUBID_9005_SEEPTYPE_NONE 0x0
190 #define SUBID_9005_SEEPTYPE_1K 0x1
191 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
192 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
193 #define SUBID_9005_AUTOTERM(id) \
194 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
195 ? (((id) & 0x400) >> 10) == 0 \
196 : (((id) & 0x40) >> 6) == 0)
197
198 #define SUBID_9005_NUMCHAN(id) \
199 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
200 ? ((id) & 0x300) >> 8 \
201 : ((id) & 0xC00) >> 10)
202
203 #define SUBID_9005_LEGACYCONN(id) \
204 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
205 ? 0 \
206 : ((id) & 0x80) >> 7)
207
208 #define SUBID_9005_MFUNCENB(id) \
209 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
210 ? ((id) & 0x800) >> 11 \
211 : ((id) & 0x1000) >> 12)
212 /*
213 * Informational only. Should use chip register to be
214 * certain, but may be use in identification strings.
215 */
216 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
217 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
218 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
219
220 static ahc_device_setup_t ahc_aic785X_setup;
221 static ahc_device_setup_t ahc_aic7860_setup;
222 static ahc_device_setup_t ahc_apa1480_setup;
223 static ahc_device_setup_t ahc_aic7870_setup;
224 static ahc_device_setup_t ahc_aha394X_setup;
225 static ahc_device_setup_t ahc_aha494X_setup;
226 static ahc_device_setup_t ahc_aha398X_setup;
227 static ahc_device_setup_t ahc_aic7880_setup;
228 static ahc_device_setup_t ahc_aha2940Pro_setup;
229 static ahc_device_setup_t ahc_aha394XU_setup;
230 static ahc_device_setup_t ahc_aha398XU_setup;
231 static ahc_device_setup_t ahc_aic7890_setup;
232 static ahc_device_setup_t ahc_aic7892_setup;
233 static ahc_device_setup_t ahc_aic7895_setup;
234 static ahc_device_setup_t ahc_aic7896_setup;
235 static ahc_device_setup_t ahc_aic7899_setup;
236 static ahc_device_setup_t ahc_aha29160C_setup;
237 static ahc_device_setup_t ahc_raid_setup;
238 static ahc_device_setup_t ahc_aha394XX_setup;
239 static ahc_device_setup_t ahc_aha494XX_setup;
240 static ahc_device_setup_t ahc_aha398XX_setup;
241
242 struct ahc_pci_identity ahc_pci_ident_table [] =
243 {
244 /* aic7850 based controllers */
245 {
246 ID_AHA_2902_04_10_15_20C_30C,
247 ID_ALL_MASK,
248 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
249 ahc_aic785X_setup
250 },
251 /* aic7860 based controllers */
252 {
253 ID_AHA_2930CU,
254 ID_ALL_MASK,
255 "Adaptec 2930CU SCSI adapter",
256 ahc_aic7860_setup
257 },
258 {
259 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
260 ID_DEV_VENDOR_MASK,
261 "Adaptec 1480A Ultra SCSI adapter",
262 ahc_apa1480_setup
263 },
264 {
265 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
266 ID_DEV_VENDOR_MASK,
267 "Adaptec 2940A Ultra SCSI adapter",
268 ahc_aic7860_setup
269 },
270 {
271 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
272 ID_DEV_VENDOR_MASK,
273 "Adaptec 2940A/CN Ultra SCSI adapter",
274 ahc_aic7860_setup
275 },
276 {
277 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
278 ID_DEV_VENDOR_MASK,
279 "Adaptec 2930C Ultra SCSI adapter (VAR)",
280 ahc_aic7860_setup
281 },
282 /* aic7870 based controllers */
283 {
284 ID_AHA_2940,
285 ID_ALL_MASK,
286 "Adaptec 2940 SCSI adapter",
287 ahc_aic7870_setup
288 },
289 {
290 ID_AHA_3940,
291 ID_ALL_MASK,
292 "Adaptec 3940 SCSI adapter",
293 ahc_aha394X_setup
294 },
295 {
296 ID_AHA_398X,
297 ID_ALL_MASK,
298 "Adaptec 398X SCSI RAID adapter",
299 ahc_aha398X_setup
300 },
301 {
302 ID_AHA_2944,
303 ID_ALL_MASK,
304 "Adaptec 2944 SCSI adapter",
305 ahc_aic7870_setup
306 },
307 {
308 ID_AHA_3944,
309 ID_ALL_MASK,
310 "Adaptec 3944 SCSI adapter",
311 ahc_aha394X_setup
312 },
313 {
314 ID_AHA_4944,
315 ID_ALL_MASK,
316 "Adaptec 4944 SCSI adapter",
317 ahc_aha494X_setup
318 },
319 /* aic7880 based controllers */
320 {
321 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
322 ID_DEV_VENDOR_MASK,
323 "Adaptec 2940 Ultra SCSI adapter",
324 ahc_aic7880_setup
325 },
326 {
327 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
328 ID_DEV_VENDOR_MASK,
329 "Adaptec 3940 Ultra SCSI adapter",
330 ahc_aha394XU_setup
331 },
332 {
333 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
334 ID_DEV_VENDOR_MASK,
335 "Adaptec 2944 Ultra SCSI adapter",
336 ahc_aic7880_setup
337 },
338 {
339 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
340 ID_DEV_VENDOR_MASK,
341 "Adaptec 3944 Ultra SCSI adapter",
342 ahc_aha394XU_setup
343 },
344 {
345 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
346 ID_DEV_VENDOR_MASK,
347 "Adaptec 398X Ultra SCSI RAID adapter",
348 ahc_aha398XU_setup
349 },
350 {
351 /*
352 * XXX Don't know the slot numbers
353 * so we can't identify channels
354 */
355 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
356 ID_DEV_VENDOR_MASK,
357 "Adaptec 4944 Ultra SCSI adapter",
358 ahc_aic7880_setup
359 },
360 {
361 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
362 ID_DEV_VENDOR_MASK,
363 "Adaptec 2930 Ultra SCSI adapter",
364 ahc_aic7880_setup
365 },
366 {
367 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
368 ID_DEV_VENDOR_MASK,
369 "Adaptec 2940 Pro Ultra SCSI adapter",
370 ahc_aha2940Pro_setup
371 },
372 {
373 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
374 ID_DEV_VENDOR_MASK,
375 "Adaptec 2940/CN Ultra SCSI adapter",
376 ahc_aic7880_setup
377 },
378 /* Ignore all SISL (AAC on MB) based controllers. */
379 {
380 ID_9005_SISL_ID,
381 ID_9005_SISL_MASK,
382 NULL,
383 NULL
384 },
385 /* aic7890 based controllers */
386 {
387 ID_AHA_2930U2,
388 ID_ALL_MASK,
389 "Adaptec 2930 Ultra2 SCSI adapter",
390 ahc_aic7890_setup
391 },
392 {
393 ID_AHA_2940U2B,
394 ID_ALL_MASK,
395 "Adaptec 2940B Ultra2 SCSI adapter",
396 ahc_aic7890_setup
397 },
398 {
399 ID_AHA_2940U2_OEM,
400 ID_ALL_MASK,
401 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
402 ahc_aic7890_setup
403 },
404 {
405 ID_AHA_2940U2,
406 ID_ALL_MASK,
407 "Adaptec 2940 Ultra2 SCSI adapter",
408 ahc_aic7890_setup
409 },
410 {
411 ID_AHA_2950U2B,
412 ID_ALL_MASK,
413 "Adaptec 2950 Ultra2 SCSI adapter",
414 ahc_aic7890_setup
415 },
416 {
417 ID_AIC7890_ARO,
418 ID_ALL_MASK,
419 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
420 ahc_aic7890_setup
421 },
422 {
423 ID_AAA_131U2,
424 ID_ALL_MASK,
425 "Adaptec AAA-131 Ultra2 RAID adapter",
426 ahc_aic7890_setup
427 },
428 /* aic7892 based controllers */
429 {
430 ID_AHA_29160,
431 ID_ALL_MASK,
432 "Adaptec 29160 Ultra160 SCSI adapter",
433 ahc_aic7892_setup
434 },
435 {
436 ID_AHA_29160_CPQ,
437 ID_ALL_MASK,
438 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
439 ahc_aic7892_setup
440 },
441 {
442 ID_AHA_29160N,
443 ID_ALL_MASK,
444 "Adaptec 29160N Ultra160 SCSI adapter",
445 ahc_aic7892_setup
446 },
447 {
448 ID_AHA_29160C,
449 ID_ALL_MASK,
450 "Adaptec 29160C Ultra160 SCSI adapter",
451 ahc_aha29160C_setup
452 },
453 {
454 ID_AHA_29160B,
455 ID_ALL_MASK,
456 "Adaptec 29160B Ultra160 SCSI adapter",
457 ahc_aic7892_setup
458 },
459 {
460 ID_AHA_19160B,
461 ID_ALL_MASK,
462 "Adaptec 19160B Ultra160 SCSI adapter",
463 ahc_aic7892_setup
464 },
465 {
466 ID_AIC7892_ARO,
467 ID_ALL_MASK,
468 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
469 ahc_aic7892_setup
470 },
471 {
472 ID_AHA_2915_30LP,
473 ID_ALL_MASK,
474 "Adaptec 2915/30LP Ultra160 SCSI adapter",
475 ahc_aic7892_setup
476 },
477 /* aic7895 based controllers */
478 {
479 ID_AHA_2940U_DUAL,
480 ID_ALL_MASK,
481 "Adaptec 2940/DUAL Ultra SCSI adapter",
482 ahc_aic7895_setup
483 },
484 {
485 ID_AHA_3940AU,
486 ID_ALL_MASK,
487 "Adaptec 3940A Ultra SCSI adapter",
488 ahc_aic7895_setup
489 },
490 {
491 ID_AHA_3944AU,
492 ID_ALL_MASK,
493 "Adaptec 3944A Ultra SCSI adapter",
494 ahc_aic7895_setup
495 },
496 {
497 ID_AIC7895_ARO,
498 ID_AIC7895_ARO_MASK,
499 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
500 ahc_aic7895_setup
501 },
502 /* aic7896/97 based controllers */
503 {
504 ID_AHA_3950U2B_0,
505 ID_ALL_MASK,
506 "Adaptec 3950B Ultra2 SCSI adapter",
507 ahc_aic7896_setup
508 },
509 {
510 ID_AHA_3950U2B_1,
511 ID_ALL_MASK,
512 "Adaptec 3950B Ultra2 SCSI adapter",
513 ahc_aic7896_setup
514 },
515 {
516 ID_AHA_3950U2D_0,
517 ID_ALL_MASK,
518 "Adaptec 3950D Ultra2 SCSI adapter",
519 ahc_aic7896_setup
520 },
521 {
522 ID_AHA_3950U2D_1,
523 ID_ALL_MASK,
524 "Adaptec 3950D Ultra2 SCSI adapter",
525 ahc_aic7896_setup
526 },
527 {
528 ID_AIC7896_ARO,
529 ID_ALL_MASK,
530 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
531 ahc_aic7896_setup
532 },
533 /* aic7899 based controllers */
534 {
535 ID_AHA_3960D,
536 ID_ALL_MASK,
537 "Adaptec 3960D Ultra160 SCSI adapter",
538 ahc_aic7899_setup
539 },
540 {
541 ID_AHA_3960D_CPQ,
542 ID_ALL_MASK,
543 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
544 ahc_aic7899_setup
545 },
546 {
547 ID_AIC7899_ARO,
548 ID_ALL_MASK,
549 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
550 ahc_aic7899_setup
551 },
552 /* Generic chip probes for devices we don't know 'exactly' */
553 {
554 ID_AIC7850 & ID_DEV_VENDOR_MASK,
555 ID_DEV_VENDOR_MASK,
556 "Adaptec aic7850 SCSI adapter",
557 ahc_aic785X_setup
558 },
559 {
560 ID_AIC7855 & ID_DEV_VENDOR_MASK,
561 ID_DEV_VENDOR_MASK,
562 "Adaptec aic7855 SCSI adapter",
563 ahc_aic785X_setup
564 },
565 {
566 ID_AIC7859 & ID_DEV_VENDOR_MASK,
567 ID_DEV_VENDOR_MASK,
568 "Adaptec aic7859 SCSI adapter",
569 ahc_aic7860_setup
570 },
571 {
572 ID_AIC7860 & ID_DEV_VENDOR_MASK,
573 ID_DEV_VENDOR_MASK,
574 "Adaptec aic7860 Ultra SCSI adapter",
575 ahc_aic7860_setup
576 },
577 {
578 ID_AIC7870 & ID_DEV_VENDOR_MASK,
579 ID_DEV_VENDOR_MASK,
580 "Adaptec aic7870 SCSI adapter",
581 ahc_aic7870_setup
582 },
583 {
584 ID_AIC7880 & ID_DEV_VENDOR_MASK,
585 ID_DEV_VENDOR_MASK,
586 "Adaptec aic7880 Ultra SCSI adapter",
587 ahc_aic7880_setup
588 },
589 {
590 ID_AIC7890 & ID_9005_GENERIC_MASK,
591 ID_9005_GENERIC_MASK,
592 "Adaptec aic7890/91 Ultra2 SCSI adapter",
593 ahc_aic7890_setup
594 },
595 {
596 ID_AIC7892 & ID_9005_GENERIC_MASK,
597 ID_9005_GENERIC_MASK,
598 "Adaptec aic7892 Ultra160 SCSI adapter",
599 ahc_aic7892_setup
600 },
601 {
602 ID_AIC7895 & ID_DEV_VENDOR_MASK,
603 ID_DEV_VENDOR_MASK,
604 "Adaptec aic7895 Ultra SCSI adapter",
605 ahc_aic7895_setup
606 },
607 {
608 ID_AIC7896 & ID_9005_GENERIC_MASK,
609 ID_9005_GENERIC_MASK,
610 "Adaptec aic7896/97 Ultra2 SCSI adapter",
611 ahc_aic7896_setup
612 },
613 {
614 ID_AIC7899 & ID_9005_GENERIC_MASK,
615 ID_9005_GENERIC_MASK,
616 "Adaptec aic7899 Ultra160 SCSI adapter",
617 ahc_aic7899_setup
618 },
619 {
620 ID_AIC7810 & ID_DEV_VENDOR_MASK,
621 ID_DEV_VENDOR_MASK,
622 "Adaptec aic7810 RAID memory controller",
623 ahc_raid_setup
624 },
625 {
626 ID_AIC7815 & ID_DEV_VENDOR_MASK,
627 ID_DEV_VENDOR_MASK,
628 "Adaptec aic7815 RAID memory controller",
629 ahc_raid_setup
630 }
631 };
632
633 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
634
635 #define AHC_394X_SLOT_CHANNEL_A 4
636 #define AHC_394X_SLOT_CHANNEL_B 5
637
638 #define AHC_398X_SLOT_CHANNEL_A 4
639 #define AHC_398X_SLOT_CHANNEL_B 8
640 #define AHC_398X_SLOT_CHANNEL_C 12
641
642 #define AHC_494X_SLOT_CHANNEL_A 4
643 #define AHC_494X_SLOT_CHANNEL_B 5
644 #define AHC_494X_SLOT_CHANNEL_C 6
645 #define AHC_494X_SLOT_CHANNEL_D 7
646
647 #define DEVCONFIG 0x40
648 #define PCIERRGENDIS 0x80000000ul
649 #define SCBSIZE32 0x00010000ul /* aic789X only */
650 #define REXTVALID 0x00001000ul /* ultra cards only */
651 #define MPORTMODE 0x00000400ul /* aic7870+ only */
652 #define RAMPSM 0x00000200ul /* aic7870+ only */
653 #define VOLSENSE 0x00000100ul
654 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
655 #define SCBRAMSEL 0x00000080ul
656 #define MRDCEN 0x00000040ul
657 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
658 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
659 #define BERREN 0x00000008ul
660 #define DACEN 0x00000004ul
661 #define STPWLEVEL 0x00000002ul
662 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
663
664 #define CSIZE_LATTIME 0x0c
665 #define CACHESIZE 0x0000003ful /* only 5 bits */
666 #define LATTIME 0x0000ff00ul
667
668 /* PCI STATUS definitions */
669 #define DPE 0x80
670 #define SSE 0x40
671 #define RMA 0x20
672 #define RTA 0x10
673 #define STA 0x08
674 #define DPR 0x01
675
676 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
677 uint16_t subvendor, uint16_t subdevice);
678 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
679 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
680 int pcheck, int fast, int large);
681 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
682 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
683 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
684 struct seeprom_config *sc);
685 static void configure_termination(struct ahc_softc *ahc,
686 struct seeprom_descriptor *sd,
687 u_int adapter_control,
688 u_int *sxfrctl1);
689
690 static void ahc_new_term_detect(struct ahc_softc *ahc,
691 int *enableSEC_low,
692 int *enableSEC_high,
693 int *enablePRI_low,
694 int *enablePRI_high,
695 int *eeprom_present);
696 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
697 int *internal68_present,
698 int *externalcable_present,
699 int *eeprom_present);
700 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
701 int *externalcable_present,
702 int *eeprom_present);
703 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
704 static uint8_t read_brdctl(struct ahc_softc *ahc);
705 static void ahc_pci_intr(struct ahc_softc *ahc);
706 static int ahc_pci_chip_init(struct ahc_softc *ahc);
707 static int ahc_pci_suspend(struct ahc_softc *ahc);
708 static int ahc_pci_resume(struct ahc_softc *ahc);
709
710 static int
711 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
712 uint16_t subdevice, uint16_t subvendor)
713 {
714 int result;
715
716 /* Default to invalid. */
717 result = 0;
718 if (vendor == 0x9005
719 && subvendor == 0x9005
720 && subdevice != device
721 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
722
723 switch (SUBID_9005_TYPE(subdevice)) {
724 case SUBID_9005_TYPE_MB:
725 break;
726 case SUBID_9005_TYPE_CARD:
727 case SUBID_9005_TYPE_LCCARD:
728 /*
729 * Currently only trust Adaptec cards to
730 * get the sub device info correct.
731 */
732 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
733 result = 1;
734 break;
735 case SUBID_9005_TYPE_RAID:
736 break;
737 default:
738 break;
739 }
740 }
741 return (result);
742 }
743
744 struct ahc_pci_identity *
745 ahc_find_pci_device(aic_dev_softc_t pci)
746 {
747 uint64_t full_id;
748 uint16_t device;
749 uint16_t vendor;
750 uint16_t subdevice;
751 uint16_t subvendor;
752 struct ahc_pci_identity *entry;
753 u_int i;
754
755 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
756 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
757 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
758 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
759 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
760
761 /*
762 * If the second function is not hooked up, ignore it.
763 * Unfortunately, not all MB vendors implement the
764 * subdevice ID as per the Adaptec spec, so do our best
765 * to sanity check it prior to accepting the subdevice
766 * ID as valid.
767 */
768 if (aic_get_pci_function(pci) > 0
769 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
770 && SUBID_9005_MFUNCENB(subdevice) == 0)
771 return (NULL);
772
773 for (i = 0; i < ahc_num_pci_devs; i++) {
774 entry = &ahc_pci_ident_table[i];
775 if (entry->full_id == (full_id & entry->id_mask)) {
776 /* Honor exclusion entries. */
777 if (entry->name == NULL)
778 return (NULL);
779 return (entry);
780 }
781 }
782 return (NULL);
783 }
784
785 int
786 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
787 {
788 u_int command;
789 u_int our_id;
790 u_int sxfrctl1;
791 u_int scsiseq;
792 u_int dscommand0;
793 uint32_t devconfig;
794 int error;
795 uint8_t sblkctl;
796
797 our_id = 0;
798 error = entry->setup(ahc);
799 if (error != 0)
800 return (error);
801 ahc->chip |= AHC_PCI;
802 ahc->description = entry->name;
803
804 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
805
806 error = ahc_pci_map_registers(ahc);
807 if (error != 0)
808 return (error);
809
810 /*
811 * Before we continue probing the card, ensure that
812 * its interrupts are *disabled*. We don't want
813 * a misstep to hang the machine in an interrupt
814 * storm.
815 */
816 ahc_intr_enable(ahc, FALSE);
817
818 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
819
820 /*
821 * If we need to support high memory, enable dual
822 * address cycles. This bit must be set to enable
823 * high address bit generation even if we are on a
824 * 64bit bus (PCI64BIT set in devconfig).
825 */
826 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
827
828 if (bootverbose)
829 printf("%s: Enabling 39Bit Addressing\n",
830 ahc_name(ahc));
831 devconfig |= DACEN;
832 }
833
834 /* Ensure that pci error generation, a test feature, is disabled. */
835 devconfig |= PCIERRGENDIS;
836
837 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
838
839 /* Ensure busmastering is enabled */
840 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
841 command |= PCIM_CMD_BUSMASTEREN;
842
843 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
844
845 /* On all PCI adapters, we allow SCB paging */
846 ahc->flags |= AHC_PAGESCBS;
847
848 error = ahc_softc_init(ahc);
849 if (error != 0)
850 return (error);
851
852 /*
853 * Disable PCI parity error checking. Users typically
854 * do this to work around broken PCI chipsets that get
855 * the parity timing wrong and thus generate lots of spurious
856 * errors. The chip only allows us to disable *all* parity
857 * error reporting when doing this, so CIO bus, scb ram, and
858 * scratch ram parity errors will be ignored too.
859 */
860 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
861 ahc->seqctl |= FAILDIS;
862
863 ahc->bus_intr = ahc_pci_intr;
864 ahc->bus_chip_init = ahc_pci_chip_init;
865 ahc->bus_suspend = ahc_pci_suspend;
866 ahc->bus_resume = ahc_pci_resume;
867
868 /* Remeber how the card was setup in case there is no SEEPROM */
869 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
870 ahc_pause(ahc);
871 if ((ahc->features & AHC_ULTRA2) != 0)
872 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
873 else
874 our_id = ahc_inb(ahc, SCSIID) & OID;
875 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
876 scsiseq = ahc_inb(ahc, SCSISEQ);
877 } else {
878 sxfrctl1 = STPWEN;
879 our_id = 7;
880 scsiseq = 0;
881 }
882
883 error = ahc_reset(ahc, /*reinit*/FALSE);
884 if (error != 0)
885 return (ENXIO);
886
887 if ((ahc->features & AHC_DT) != 0) {
888 u_int sfunct;
889
890 /* Perform ALT-Mode Setup */
891 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
892 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
893 ahc_outb(ahc, OPTIONMODE,
894 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
895 ahc_outb(ahc, SFUNCT, sfunct);
896
897 /* Normal mode setup */
898 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
899 |TARGCRCENDEN);
900 }
901
902 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
903 dscommand0 |= MPARCKEN|CACHETHEN;
904 if ((ahc->features & AHC_ULTRA2) != 0) {
905
906 /*
907 * DPARCKEN doesn't work correctly on
908 * some MBs so don't use it.
909 */
910 dscommand0 &= ~DPARCKEN;
911 }
912
913 /*
914 * Handle chips that must have cache line
915 * streaming (dis/en)abled.
916 */
917 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
918 dscommand0 |= CACHETHEN;
919
920 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
921 dscommand0 &= ~CACHETHEN;
922
923 ahc_outb(ahc, DSCOMMAND0, dscommand0);
924
925 ahc->pci_cachesize =
926 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
927 /*bytes*/1) & CACHESIZE;
928 ahc->pci_cachesize *= 4;
929
930 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
931 && ahc->pci_cachesize == 4) {
932
933 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
934 0, /*bytes*/1);
935 ahc->pci_cachesize = 0;
936 }
937
938 /*
939 * We cannot perform ULTRA speeds without the presense
940 * of the external precision resistor.
941 */
942 if ((ahc->features & AHC_ULTRA) != 0) {
943 uint32_t devconfig;
944
945 devconfig = aic_pci_read_config(ahc->dev_softc,
946 DEVCONFIG, /*bytes*/4);
947 if ((devconfig & REXTVALID) == 0)
948 ahc->features &= ~AHC_ULTRA;
949 }
950
951 /* See if we have a SEEPROM and perform auto-term */
952 check_extport(ahc, &sxfrctl1);
953
954 /*
955 * Take the LED out of diagnostic mode
956 */
957 sblkctl = ahc_inb(ahc, SBLKCTL);
958 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
959
960 if ((ahc->features & AHC_ULTRA2) != 0) {
961 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
962 } else {
963 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
964 }
965
966 if (ahc->flags & AHC_USEDEFAULTS) {
967 /*
968 * PCI Adapter default setup
969 * Should only be used if the adapter does not have
970 * a SEEPROM.
971 */
972 /* See if someone else set us up already */
973 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
974 && scsiseq != 0) {
975 printf("%s: Using left over BIOS settings\n",
976 ahc_name(ahc));
977 ahc->flags &= ~AHC_USEDEFAULTS;
978 ahc->flags |= AHC_BIOS_ENABLED;
979 } else {
980 /*
981 * Assume only one connector and always turn
982 * on termination.
983 */
984 our_id = 0x07;
985 sxfrctl1 = STPWEN;
986 }
987 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
988
989 ahc->our_id = our_id;
990 }
991
992 /*
993 * Take a look to see if we have external SRAM.
994 * We currently do not attempt to use SRAM that is
995 * shared among multiple controllers.
996 */
997 ahc_probe_ext_scbram(ahc);
998
999 /*
1000 * Record our termination setting for the
1001 * generic initialization routine.
1002 */
1003 if ((sxfrctl1 & STPWEN) != 0)
1004 ahc->flags |= AHC_TERM_ENB_A;
1005
1006 /*
1007 * Save chip register configuration data for chip resets
1008 * that occur during runtime and resume events.
1009 */
1010 ahc->bus_softc.pci_softc.devconfig =
1011 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1012 ahc->bus_softc.pci_softc.command =
1013 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1014 ahc->bus_softc.pci_softc.csize_lattime =
1015 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1016 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1017 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1018 if ((ahc->features & AHC_DT) != 0) {
1019 u_int sfunct;
1020
1021 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1022 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1023 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1024 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1025 ahc_outb(ahc, SFUNCT, sfunct);
1026 ahc->bus_softc.pci_softc.crccontrol1 =
1027 ahc_inb(ahc, CRCCONTROL1);
1028 }
1029 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1030 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1031
1032 if ((ahc->features & AHC_ULTRA2) != 0)
1033 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1034
1035 /* Core initialization */
1036 error = ahc_init(ahc);
1037 if (error != 0)
1038 return (error);
1039
1040 /*
1041 * Allow interrupts now that we are completely setup.
1042 */
1043 error = ahc_pci_map_int(ahc);
1044 if (error != 0)
1045 return (error);
1046
1047 ahc_lock(ahc);
1048 /*
1049 * Link this softc in with all other ahc instances.
1050 */
1051 ahc_softc_insert(ahc);
1052 ahc_unlock(ahc);
1053 return (0);
1054 }
1055
1056 /*
1057 * Test for the presense of external sram in an
1058 * "unshared" configuration.
1059 */
1060 static int
1061 ahc_ext_scbram_present(struct ahc_softc *ahc)
1062 {
1063 u_int chip;
1064 int ramps;
1065 int single_user;
1066 uint32_t devconfig;
1067
1068 chip = ahc->chip & AHC_CHIPID_MASK;
1069 devconfig = aic_pci_read_config(ahc->dev_softc,
1070 DEVCONFIG, /*bytes*/4);
1071 single_user = (devconfig & MPORTMODE) != 0;
1072
1073 if ((ahc->features & AHC_ULTRA2) != 0)
1074 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1075 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1076 /*
1077 * External SCBRAM arbitration is flakey
1078 * on these chips. Unfortunately this means
1079 * we don't use the extra SCB ram space on the
1080 * 3940AUW.
1081 */
1082 ramps = 0;
1083 else if (chip >= AHC_AIC7870)
1084 ramps = (devconfig & RAMPSM) != 0;
1085 else
1086 ramps = 0;
1087
1088 if (ramps && single_user)
1089 return (1);
1090 return (0);
1091 }
1092
1093 /*
1094 * Enable external scbram.
1095 */
1096 static void
1097 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1098 int fast, int large)
1099 {
1100 uint32_t devconfig;
1101
1102 if (ahc->features & AHC_MULTI_FUNC) {
1103 /*
1104 * Set the SCB Base addr (highest address bit)
1105 * depending on which channel we are.
1106 */
1107 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1108 }
1109
1110 ahc->flags &= ~AHC_LSCBS_ENABLED;
1111 if (large)
1112 ahc->flags |= AHC_LSCBS_ENABLED;
1113 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1114 if ((ahc->features & AHC_ULTRA2) != 0) {
1115 u_int dscommand0;
1116
1117 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1118 if (enable)
1119 dscommand0 &= ~INTSCBRAMSEL;
1120 else
1121 dscommand0 |= INTSCBRAMSEL;
1122 if (large)
1123 dscommand0 &= ~USCBSIZE32;
1124 else
1125 dscommand0 |= USCBSIZE32;
1126 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1127 } else {
1128 if (fast)
1129 devconfig &= ~EXTSCBTIME;
1130 else
1131 devconfig |= EXTSCBTIME;
1132 if (enable)
1133 devconfig &= ~SCBRAMSEL;
1134 else
1135 devconfig |= SCBRAMSEL;
1136 if (large)
1137 devconfig &= ~SCBSIZE32;
1138 else
1139 devconfig |= SCBSIZE32;
1140 }
1141 if (pcheck)
1142 devconfig |= EXTSCBPEN;
1143 else
1144 devconfig &= ~EXTSCBPEN;
1145
1146 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1147 }
1148
1149 /*
1150 * Take a look to see if we have external SRAM.
1151 * We currently do not attempt to use SRAM that is
1152 * shared among multiple controllers.
1153 */
1154 static void
1155 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1156 {
1157 int num_scbs;
1158 int test_num_scbs;
1159 int enable;
1160 int pcheck;
1161 int fast;
1162 int large;
1163
1164 enable = FALSE;
1165 pcheck = FALSE;
1166 fast = FALSE;
1167 large = FALSE;
1168 num_scbs = 0;
1169
1170 if (ahc_ext_scbram_present(ahc) == 0)
1171 goto done;
1172
1173 /*
1174 * Probe for the best parameters to use.
1175 */
1176 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1177 num_scbs = ahc_probe_scbs(ahc);
1178 if (num_scbs == 0) {
1179 /* The SRAM wasn't really present. */
1180 goto done;
1181 }
1182 enable = TRUE;
1183
1184 /*
1185 * Clear any outstanding parity error
1186 * and ensure that parity error reporting
1187 * is enabled.
1188 */
1189 ahc_outb(ahc, SEQCTL, 0);
1190 ahc_outb(ahc, CLRINT, CLRPARERR);
1191 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1192
1193 /* Now see if we can do parity */
1194 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1195 num_scbs = ahc_probe_scbs(ahc);
1196 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1197 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1198 pcheck = TRUE;
1199
1200 /* Clear any resulting parity error */
1201 ahc_outb(ahc, CLRINT, CLRPARERR);
1202 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1203
1204 /* Now see if we can do fast timing */
1205 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1206 test_num_scbs = ahc_probe_scbs(ahc);
1207 if (test_num_scbs == num_scbs
1208 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1209 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1210 fast = TRUE;
1211
1212 /*
1213 * See if we can use large SCBs and still maintain
1214 * the same overall count of SCBs.
1215 */
1216 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1217 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1218 test_num_scbs = ahc_probe_scbs(ahc);
1219 if (test_num_scbs >= num_scbs) {
1220 large = TRUE;
1221 num_scbs = test_num_scbs;
1222 if (num_scbs >= 64) {
1223 /*
1224 * We have enough space to move the
1225 * "busy targets table" into SCB space
1226 * and make it qualify all the way to the
1227 * lun level.
1228 */
1229 ahc->flags |= AHC_SCB_BTT;
1230 }
1231 }
1232 }
1233 done:
1234 /*
1235 * Disable parity error reporting until we
1236 * can load instruction ram.
1237 */
1238 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1239 /* Clear any latched parity error */
1240 ahc_outb(ahc, CLRINT, CLRPARERR);
1241 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1242 if (bootverbose && enable) {
1243 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1244 ahc_name(ahc), fast ? "fast" : "slow",
1245 pcheck ? ", parity checking enabled" : "",
1246 large ? 64 : 32);
1247 }
1248 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1249 }
1250
1251 /*
1252 * Perform some simple tests that should catch situations where
1253 * our registers are invalidly mapped.
1254 */
1255 int
1256 ahc_pci_test_register_access(struct ahc_softc *ahc)
1257 {
1258 int error;
1259 u_int status1;
1260 uint32_t cmd;
1261 uint8_t hcntrl;
1262
1263 error = EIO;
1264
1265 /*
1266 * Enable PCI error interrupt status, but suppress NMIs
1267 * generated by SERR raised due to target aborts.
1268 */
1269 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1270 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1271 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1272
1273 /*
1274 * First a simple test to see if any
1275 * registers can be read. Reading
1276 * HCNTRL has no side effects and has
1277 * at least one bit that is guaranteed to
1278 * be zero so it is a good register to
1279 * use for this test.
1280 */
1281 hcntrl = ahc_inb(ahc, HCNTRL);
1282
1283 if (hcntrl == 0xFF)
1284 goto fail;
1285
1286 if ((hcntrl & CHIPRST) != 0) {
1287 /*
1288 * The chip has not been initialized since
1289 * PCI/EISA/VLB bus reset. Don't trust
1290 * "left over BIOS data".
1291 */
1292 ahc->flags |= AHC_NO_BIOS_INIT;
1293 }
1294
1295 /*
1296 * Next create a situation where write combining
1297 * or read prefetching could be initiated by the
1298 * CPU or host bridge. Our device does not support
1299 * either, so look for data corruption and/or flagged
1300 * PCI errors. First pause without causing another
1301 * chip reset.
1302 */
1303 hcntrl &= ~CHIPRST;
1304 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1305 while (ahc_is_paused(ahc) == 0)
1306 ;
1307
1308 /* Clear any PCI errors that occurred before our driver attached. */
1309 status1 = aic_pci_read_config(ahc->dev_softc,
1310 PCIR_STATUS + 1, /*bytes*/1);
1311 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1312 status1, /*bytes*/1);
1313 ahc_outb(ahc, CLRINT, CLRPARERR);
1314
1315 ahc_outb(ahc, SEQCTL, PERRORDIS);
1316 ahc_outb(ahc, SCBPTR, 0);
1317 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1318 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1319 goto fail;
1320
1321 status1 = aic_pci_read_config(ahc->dev_softc,
1322 PCIR_STATUS + 1, /*bytes*/1);
1323 if ((status1 & STA) != 0)
1324 goto fail;
1325
1326 error = 0;
1327
1328 fail:
1329 /* Silently clear any latched errors. */
1330 status1 = aic_pci_read_config(ahc->dev_softc,
1331 PCIR_STATUS + 1, /*bytes*/1);
1332 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1333 status1, /*bytes*/1);
1334 ahc_outb(ahc, CLRINT, CLRPARERR);
1335 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1336 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1337 return (error);
1338 }
1339
1340 /*
1341 * Check the external port logic for a serial eeprom
1342 * and termination/cable detection contrls.
1343 */
1344 static void
1345 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1346 {
1347 struct seeprom_descriptor sd;
1348 struct seeprom_config *sc;
1349 int have_seeprom;
1350 int have_autoterm;
1351
1352 sd.sd_ahc = ahc;
1353 sd.sd_control_offset = SEECTL;
1354 sd.sd_status_offset = SEECTL;
1355 sd.sd_dataout_offset = SEECTL;
1356 sc = ahc->seep_config;
1357
1358 /*
1359 * For some multi-channel devices, the c46 is simply too
1360 * small to work. For the other controller types, we can
1361 * get our information from either SEEPROM type. Set the
1362 * type to start our probe with accordingly.
1363 */
1364 if (ahc->flags & AHC_LARGE_SEEPROM)
1365 sd.sd_chip = C56_66;
1366 else
1367 sd.sd_chip = C46;
1368
1369 sd.sd_MS = SEEMS;
1370 sd.sd_RDY = SEERDY;
1371 sd.sd_CS = SEECS;
1372 sd.sd_CK = SEECK;
1373 sd.sd_DO = SEEDO;
1374 sd.sd_DI = SEEDI;
1375
1376 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1377 if (have_seeprom) {
1378
1379 if (bootverbose)
1380 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1381
1382 for (;;) {
1383 u_int start_addr;
1384
1385 start_addr = 32 * (ahc->channel - 'A');
1386
1387 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1388 start_addr,
1389 sizeof(*sc)/2);
1390
1391 if (have_seeprom)
1392 have_seeprom = ahc_verify_cksum(sc);
1393
1394 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1395 if (bootverbose) {
1396 if (have_seeprom == 0)
1397 printf ("checksum error\n");
1398 else
1399 printf ("done.\n");
1400 }
1401 break;
1402 }
1403 sd.sd_chip = C56_66;
1404 }
1405 ahc_release_seeprom(&sd);
1406
1407 /* Remember the SEEPROM type for later */
1408 if (sd.sd_chip == C56_66)
1409 ahc->flags |= AHC_LARGE_SEEPROM;
1410 }
1411
1412 if (!have_seeprom) {
1413 /*
1414 * Pull scratch ram settings and treat them as
1415 * if they are the contents of an seeprom if
1416 * the 'ADPT' signature is found in SCB2.
1417 * We manually compose the data as 16bit values
1418 * to avoid endian issues.
1419 */
1420 ahc_outb(ahc, SCBPTR, 2);
1421 if (ahc_inb(ahc, SCB_BASE) == 'A'
1422 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1423 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1424 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1425 uint16_t *sc_data;
1426 int i;
1427
1428 sc_data = (uint16_t *)sc;
1429 for (i = 0; i < 32; i++, sc_data++) {
1430 int j;
1431
1432 j = i * 2;
1433 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1434 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1435 }
1436 have_seeprom = ahc_verify_cksum(sc);
1437 if (have_seeprom)
1438 ahc->flags |= AHC_SCB_CONFIG_USED;
1439 }
1440 /*
1441 * Clear any SCB parity errors in case this data and
1442 * its associated parity was not initialized by the BIOS
1443 */
1444 ahc_outb(ahc, CLRINT, CLRPARERR);
1445 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1446 }
1447
1448 if (!have_seeprom) {
1449 if (bootverbose)
1450 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1451 ahc->flags |= AHC_USEDEFAULTS;
1452 free(ahc->seep_config, M_DEVBUF);
1453 ahc->seep_config = NULL;
1454 sc = NULL;
1455 } else {
1456 ahc_parse_pci_eeprom(ahc, sc);
1457 }
1458
1459 /*
1460 * Cards that have the external logic necessary to talk to
1461 * a SEEPROM, are almost certain to have the remaining logic
1462 * necessary for auto-termination control. This assumption
1463 * hasn't failed yet...
1464 */
1465 have_autoterm = have_seeprom;
1466
1467 /*
1468 * Some low-cost chips have SEEPROM and auto-term control built
1469 * in, instead of using a GAL. They can tell us directly
1470 * if the termination logic is enabled.
1471 */
1472 if ((ahc->features & AHC_SPIOCAP) != 0) {
1473 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1474 have_autoterm = FALSE;
1475 }
1476
1477 if (have_autoterm) {
1478 ahc->flags |= AHC_HAS_TERM_LOGIC;
1479 ahc_acquire_seeprom(ahc, &sd);
1480 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1481 ahc_release_seeprom(&sd);
1482 } else if (have_seeprom) {
1483 *sxfrctl1 &= ~STPWEN;
1484 if ((sc->adapter_control & CFSTERM) != 0)
1485 *sxfrctl1 |= STPWEN;
1486 if (bootverbose)
1487 printf("%s: Low byte termination %sabled\n",
1488 ahc_name(ahc),
1489 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1490 }
1491 }
1492
1493 static void
1494 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1495 {
1496 /*
1497 * Put the data we've collected down into SRAM
1498 * where ahc_init will find it.
1499 */
1500 int i;
1501 int max_targ = sc->max_targets & CFMAXTARG;
1502 u_int scsi_conf;
1503 uint16_t discenable;
1504 uint16_t ultraenb;
1505
1506 discenable = 0;
1507 ultraenb = 0;
1508 if ((sc->adapter_control & CFULTRAEN) != 0) {
1509 /*
1510 * Determine if this adapter has a "newstyle"
1511 * SEEPROM format.
1512 */
1513 for (i = 0; i < max_targ; i++) {
1514 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1515 ahc->flags |= AHC_NEWEEPROM_FMT;
1516 break;
1517 }
1518 }
1519 }
1520
1521 for (i = 0; i < max_targ; i++) {
1522 u_int scsirate;
1523 uint16_t target_mask;
1524
1525 target_mask = 0x01 << i;
1526 if (sc->device_flags[i] & CFDISC)
1527 discenable |= target_mask;
1528 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1529 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1530 ultraenb |= target_mask;
1531 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1532 ultraenb |= target_mask;
1533 }
1534 if ((sc->device_flags[i] & CFXFER) == 0x04
1535 && (ultraenb & target_mask) != 0) {
1536 /* Treat 10MHz as a non-ultra speed */
1537 sc->device_flags[i] &= ~CFXFER;
1538 ultraenb &= ~target_mask;
1539 }
1540 if ((ahc->features & AHC_ULTRA2) != 0) {
1541 u_int offset;
1542
1543 if (sc->device_flags[i] & CFSYNCH)
1544 offset = MAX_OFFSET_ULTRA2;
1545 else
1546 offset = 0;
1547 ahc_outb(ahc, TARG_OFFSET + i, offset);
1548
1549 /*
1550 * The ultra enable bits contain the
1551 * high bit of the ultra2 sync rate
1552 * field.
1553 */
1554 scsirate = (sc->device_flags[i] & CFXFER)
1555 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1556 if (sc->device_flags[i] & CFWIDEB)
1557 scsirate |= WIDEXFER;
1558 } else {
1559 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1560 if (sc->device_flags[i] & CFSYNCH)
1561 scsirate |= SOFS;
1562 if (sc->device_flags[i] & CFWIDEB)
1563 scsirate |= WIDEXFER;
1564 }
1565 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1566 }
1567 ahc->our_id = sc->brtime_id & CFSCSIID;
1568
1569 scsi_conf = (ahc->our_id & 0x7);
1570 if (sc->adapter_control & CFSPARITY)
1571 scsi_conf |= ENSPCHK;
1572 if (sc->adapter_control & CFRESETB)
1573 scsi_conf |= RESET_SCSI;
1574
1575 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1576
1577 if (sc->bios_control & CFEXTEND)
1578 ahc->flags |= AHC_EXTENDED_TRANS_A;
1579
1580 if (sc->bios_control & CFBIOSEN)
1581 ahc->flags |= AHC_BIOS_ENABLED;
1582 if (ahc->features & AHC_ULTRA
1583 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1584 /* Should we enable Ultra mode? */
1585 if (!(sc->adapter_control & CFULTRAEN))
1586 /* Treat us as a non-ultra card */
1587 ultraenb = 0;
1588 }
1589
1590 if (sc->signature == CFSIGNATURE
1591 || sc->signature == CFSIGNATURE2) {
1592 uint32_t devconfig;
1593
1594 /* Honor the STPWLEVEL settings */
1595 devconfig = aic_pci_read_config(ahc->dev_softc,
1596 DEVCONFIG, /*bytes*/4);
1597 devconfig &= ~STPWLEVEL;
1598 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1599 devconfig |= STPWLEVEL;
1600 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1601 devconfig, /*bytes*/4);
1602 }
1603 /* Set SCSICONF info */
1604 ahc_outb(ahc, SCSICONF, scsi_conf);
1605 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1606 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1607 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1608 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1609 }
1610
1611 static void
1612 configure_termination(struct ahc_softc *ahc,
1613 struct seeprom_descriptor *sd,
1614 u_int adapter_control,
1615 u_int *sxfrctl1)
1616 {
1617 uint8_t brddat;
1618
1619 brddat = 0;
1620
1621 /*
1622 * Update the settings in sxfrctl1 to match the
1623 * termination settings
1624 */
1625 *sxfrctl1 = 0;
1626
1627 /*
1628 * SEECS must be on for the GALS to latch
1629 * the data properly. Be sure to leave MS
1630 * on or we will release the seeprom.
1631 */
1632 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1633 if ((adapter_control & CFAUTOTERM) != 0
1634 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1635 int internal50_present;
1636 int internal68_present;
1637 int externalcable_present;
1638 int eeprom_present;
1639 int enableSEC_low;
1640 int enableSEC_high;
1641 int enablePRI_low;
1642 int enablePRI_high;
1643 int sum;
1644
1645 enableSEC_low = 0;
1646 enableSEC_high = 0;
1647 enablePRI_low = 0;
1648 enablePRI_high = 0;
1649 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1650 ahc_new_term_detect(ahc, &enableSEC_low,
1651 &enableSEC_high,
1652 &enablePRI_low,
1653 &enablePRI_high,
1654 &eeprom_present);
1655 if ((adapter_control & CFSEAUTOTERM) == 0) {
1656 if (bootverbose)
1657 printf("%s: Manual SE Termination\n",
1658 ahc_name(ahc));
1659 enableSEC_low = (adapter_control & CFSELOWTERM);
1660 enableSEC_high =
1661 (adapter_control & CFSEHIGHTERM);
1662 }
1663 if ((adapter_control & CFAUTOTERM) == 0) {
1664 if (bootverbose)
1665 printf("%s: Manual LVD Termination\n",
1666 ahc_name(ahc));
1667 enablePRI_low = (adapter_control & CFSTERM);
1668 enablePRI_high = (adapter_control & CFWSTERM);
1669 }
1670 /* Make the table calculations below happy */
1671 internal50_present = 0;
1672 internal68_present = 1;
1673 externalcable_present = 1;
1674 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1675 aic785X_cable_detect(ahc, &internal50_present,
1676 &externalcable_present,
1677 &eeprom_present);
1678 /* Can never support a wide connector. */
1679 internal68_present = 0;
1680 } else {
1681 aic787X_cable_detect(ahc, &internal50_present,
1682 &internal68_present,
1683 &externalcable_present,
1684 &eeprom_present);
1685 }
1686
1687 if ((ahc->features & AHC_WIDE) == 0)
1688 internal68_present = 0;
1689
1690 if (bootverbose
1691 && (ahc->features & AHC_ULTRA2) == 0) {
1692 printf("%s: internal 50 cable %s present",
1693 ahc_name(ahc),
1694 internal50_present ? "is":"not");
1695
1696 if ((ahc->features & AHC_WIDE) != 0)
1697 printf(", internal 68 cable %s present",
1698 internal68_present ? "is":"not");
1699 printf("\n%s: external cable %s present\n",
1700 ahc_name(ahc),
1701 externalcable_present ? "is":"not");
1702 }
1703 if (bootverbose)
1704 printf("%s: BIOS eeprom %s present\n",
1705 ahc_name(ahc), eeprom_present ? "is" : "not");
1706
1707 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1708 /*
1709 * The 50 pin connector is a separate bus,
1710 * so force it to always be terminated.
1711 * In the future, perform current sensing
1712 * to determine if we are in the middle of
1713 * a properly terminated bus.
1714 */
1715 internal50_present = 0;
1716 }
1717
1718 /*
1719 * Now set the termination based on what
1720 * we found.
1721 * Flash Enable = BRDDAT7
1722 * Secondary High Term Enable = BRDDAT6
1723 * Secondary Low Term Enable = BRDDAT5 (7890)
1724 * Primary High Term Enable = BRDDAT4 (7890)
1725 */
1726 if ((ahc->features & AHC_ULTRA2) == 0
1727 && (internal50_present != 0)
1728 && (internal68_present != 0)
1729 && (externalcable_present != 0)) {
1730 printf("%s: Illegal cable configuration!!. "
1731 "Only two connectors on the "
1732 "adapter may be used at a "
1733 "time!\n", ahc_name(ahc));
1734
1735 /*
1736 * Pretend there are no cables in the hope
1737 * that having all of the termination on
1738 * gives us a more stable bus.
1739 */
1740 internal50_present = 0;
1741 internal68_present = 0;
1742 externalcable_present = 0;
1743 }
1744
1745 if ((ahc->features & AHC_WIDE) != 0
1746 && ((externalcable_present == 0)
1747 || (internal68_present == 0)
1748 || (enableSEC_high != 0))) {
1749 brddat |= BRDDAT6;
1750 if (bootverbose) {
1751 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1752 printf("%s: 68 pin termination "
1753 "Enabled\n", ahc_name(ahc));
1754 else
1755 printf("%s: %sHigh byte termination "
1756 "Enabled\n", ahc_name(ahc),
1757 enableSEC_high ? "Secondary "
1758 : "");
1759 }
1760 }
1761
1762 sum = internal50_present + internal68_present
1763 + externalcable_present;
1764 if (sum < 2 || (enableSEC_low != 0)) {
1765 if ((ahc->features & AHC_ULTRA2) != 0)
1766 brddat |= BRDDAT5;
1767 else
1768 *sxfrctl1 |= STPWEN;
1769 if (bootverbose) {
1770 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1771 printf("%s: 50 pin termination "
1772 "Enabled\n", ahc_name(ahc));
1773 else
1774 printf("%s: %sLow byte termination "
1775 "Enabled\n", ahc_name(ahc),
1776 enableSEC_low ? "Secondary "
1777 : "");
1778 }
1779 }
1780
1781 if (enablePRI_low != 0) {
1782 *sxfrctl1 |= STPWEN;
1783 if (bootverbose)
1784 printf("%s: Primary Low Byte termination "
1785 "Enabled\n", ahc_name(ahc));
1786 }
1787
1788 /*
1789 * Setup STPWEN before setting up the rest of
1790 * the termination per the tech note on the U160 cards.
1791 */
1792 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1793
1794 if (enablePRI_high != 0) {
1795 brddat |= BRDDAT4;
1796 if (bootverbose)
1797 printf("%s: Primary High Byte "
1798 "termination Enabled\n",
1799 ahc_name(ahc));
1800 }
1801
1802 write_brdctl(ahc, brddat);
1803
1804 } else {
1805 if ((adapter_control & CFSTERM) != 0) {
1806 *sxfrctl1 |= STPWEN;
1807
1808 if (bootverbose)
1809 printf("%s: %sLow byte termination Enabled\n",
1810 ahc_name(ahc),
1811 (ahc->features & AHC_ULTRA2) ? "Primary "
1812 : "");
1813 }
1814
1815 if ((adapter_control & CFWSTERM) != 0
1816 && (ahc->features & AHC_WIDE) != 0) {
1817 brddat |= BRDDAT6;
1818 if (bootverbose)
1819 printf("%s: %sHigh byte termination Enabled\n",
1820 ahc_name(ahc),
1821 (ahc->features & AHC_ULTRA2)
1822 ? "Secondary " : "");
1823 }
1824
1825 /*
1826 * Setup STPWEN before setting up the rest of
1827 * the termination per the tech note on the U160 cards.
1828 */
1829 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1830
1831 if ((ahc->features & AHC_WIDE) != 0)
1832 write_brdctl(ahc, brddat);
1833 }
1834 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1835 }
1836
1837 static void
1838 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1839 int *enableSEC_high, int *enablePRI_low,
1840 int *enablePRI_high, int *eeprom_present)
1841 {
1842 uint8_t brdctl;
1843
1844 /*
1845 * BRDDAT7 = Eeprom
1846 * BRDDAT6 = Enable Secondary High Byte termination
1847 * BRDDAT5 = Enable Secondary Low Byte termination
1848 * BRDDAT4 = Enable Primary high byte termination
1849 * BRDDAT3 = Enable Primary low byte termination
1850 */
1851 brdctl = read_brdctl(ahc);
1852 *eeprom_present = brdctl & BRDDAT7;
1853 *enableSEC_high = (brdctl & BRDDAT6);
1854 *enableSEC_low = (brdctl & BRDDAT5);
1855 *enablePRI_high = (brdctl & BRDDAT4);
1856 *enablePRI_low = (brdctl & BRDDAT3);
1857 }
1858
1859 static void
1860 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1861 int *internal68_present, int *externalcable_present,
1862 int *eeprom_present)
1863 {
1864 uint8_t brdctl;
1865
1866 /*
1867 * First read the status of our cables.
1868 * Set the rom bank to 0 since the
1869 * bank setting serves as a multiplexor
1870 * for the cable detection logic.
1871 * BRDDAT5 controls the bank switch.
1872 */
1873 write_brdctl(ahc, 0);
1874
1875 /*
1876 * Now read the state of the internal
1877 * connectors. BRDDAT6 is INT50 and
1878 * BRDDAT7 is INT68.
1879 */
1880 brdctl = read_brdctl(ahc);
1881 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1882 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1883
1884 /*
1885 * Set the rom bank to 1 and determine
1886 * the other signals.
1887 */
1888 write_brdctl(ahc, BRDDAT5);
1889
1890 /*
1891 * Now read the state of the external
1892 * connectors. BRDDAT6 is EXT68 and
1893 * BRDDAT7 is EPROMPS.
1894 */
1895 brdctl = read_brdctl(ahc);
1896 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1897 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1898 }
1899
1900 static void
1901 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1902 int *externalcable_present, int *eeprom_present)
1903 {
1904 uint8_t brdctl;
1905 uint8_t spiocap;
1906
1907 spiocap = ahc_inb(ahc, SPIOCAP);
1908 spiocap &= ~SOFTCMDEN;
1909 spiocap |= EXT_BRDCTL;
1910 ahc_outb(ahc, SPIOCAP, spiocap);
1911 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1912 ahc_flush_device_writes(ahc);
1913 aic_delay(500);
1914 ahc_outb(ahc, BRDCTL, 0);
1915 ahc_flush_device_writes(ahc);
1916 aic_delay(500);
1917 brdctl = ahc_inb(ahc, BRDCTL);
1918 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1919 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1920 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1921 }
1922
1923 int
1924 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1925 {
1926 int wait;
1927
1928 if ((ahc->features & AHC_SPIOCAP) != 0
1929 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1930 return (0);
1931
1932 /*
1933 * Request access of the memory port. When access is
1934 * granted, SEERDY will go high. We use a 1 second
1935 * timeout which should be near 1 second more than
1936 * is needed. Reason: after the chip reset, there
1937 * should be no contention.
1938 */
1939 SEEPROM_OUTB(sd, sd->sd_MS);
1940 wait = 1000; /* 1 second timeout in msec */
1941 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1942 aic_delay(1000); /* delay 1 msec */
1943 }
1944 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1945 SEEPROM_OUTB(sd, 0);
1946 return (0);
1947 }
1948 return(1);
1949 }
1950
1951 void
1952 ahc_release_seeprom(struct seeprom_descriptor *sd)
1953 {
1954 /* Release access to the memory port and the serial EEPROM. */
1955 SEEPROM_OUTB(sd, 0);
1956 }
1957
1958 static void
1959 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1960 {
1961 uint8_t brdctl;
1962
1963 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1964 brdctl = BRDSTB;
1965 if (ahc->channel == 'B')
1966 brdctl |= BRDCS;
1967 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1968 brdctl = 0;
1969 } else {
1970 brdctl = BRDSTB|BRDCS;
1971 }
1972 ahc_outb(ahc, BRDCTL, brdctl);
1973 ahc_flush_device_writes(ahc);
1974 brdctl |= value;
1975 ahc_outb(ahc, BRDCTL, brdctl);
1976 ahc_flush_device_writes(ahc);
1977 if ((ahc->features & AHC_ULTRA2) != 0)
1978 brdctl |= BRDSTB_ULTRA2;
1979 else
1980 brdctl &= ~BRDSTB;
1981 ahc_outb(ahc, BRDCTL, brdctl);
1982 ahc_flush_device_writes(ahc);
1983 if ((ahc->features & AHC_ULTRA2) != 0)
1984 brdctl = 0;
1985 else
1986 brdctl &= ~BRDCS;
1987 ahc_outb(ahc, BRDCTL, brdctl);
1988 }
1989
1990 static uint8_t
1991 read_brdctl(struct ahc_softc *ahc)
1992 {
1993 uint8_t brdctl;
1994 uint8_t value;
1995
1996 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1997 brdctl = BRDRW;
1998 if (ahc->channel == 'B')
1999 brdctl |= BRDCS;
2000 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2001 brdctl = BRDRW_ULTRA2;
2002 } else {
2003 brdctl = BRDRW|BRDCS;
2004 }
2005 ahc_outb(ahc, BRDCTL, brdctl);
2006 ahc_flush_device_writes(ahc);
2007 value = ahc_inb(ahc, BRDCTL);
2008 ahc_outb(ahc, BRDCTL, 0);
2009 return (value);
2010 }
2011
2012 static void
2013 ahc_pci_intr(struct ahc_softc *ahc)
2014 {
2015 u_int error;
2016 u_int status1;
2017
2018 error = ahc_inb(ahc, ERROR);
2019 if ((error & PCIERRSTAT) == 0)
2020 return;
2021
2022 status1 = aic_pci_read_config(ahc->dev_softc,
2023 PCIR_STATUS + 1, /*bytes*/1);
2024
2025 if ((status1 & ~DPE) != 0
2026 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2027 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2028 ahc_name(ahc),
2029 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2030 }
2031
2032 if (status1 & DPE
2033 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2034 ahc->pci_target_perr_count++;
2035 printf("%s: Data Parity Error Detected during address "
2036 "or write data phase\n", ahc_name(ahc));
2037 }
2038 if (status1 & SSE) {
2039 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2040 }
2041 if (status1 & RMA) {
2042 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2043 }
2044 if (status1 & RTA) {
2045 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2046 }
2047 if (status1 & STA) {
2048 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2049 }
2050 if (status1 & DPR) {
2051 printf("%s: Data Parity Error has been reported via PERR#\n",
2052 ahc_name(ahc));
2053 }
2054
2055 /* Clear latched errors. */
2056 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2057 status1, /*bytes*/1);
2058
2059 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2060 printf("%s: Latched PCIERR interrupt with "
2061 "no status bits set\n", ahc_name(ahc));
2062 } else {
2063 ahc_outb(ahc, CLRINT, CLRPARERR);
2064 }
2065
2066 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2067 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2068 printf(
2069 "%s: WARNING WARNING WARNING WARNING\n"
2070 "%s: Too many PCI parity errors observed as a target.\n"
2071 "%s: Some device on this PCI bus is generating bad parity.\n"
2072 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2073 "%s: PCI parity error checking has been disabled.\n"
2074 "%s: WARNING WARNING WARNING WARNING\n",
2075 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2076 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2077 ahc_name(ahc));
2078 ahc->seqctl |= FAILDIS;
2079 ahc->flags |= AHC_DISABLE_PCI_PERR;
2080 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2081 }
2082 ahc_unpause(ahc);
2083 }
2084
2085 static int
2086 ahc_pci_chip_init(struct ahc_softc *ahc)
2087 {
2088 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2089 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2090 if ((ahc->features & AHC_DT) != 0) {
2091 u_int sfunct;
2092
2093 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2094 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2095 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2096 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2097 ahc_outb(ahc, SFUNCT, sfunct);
2098 ahc_outb(ahc, CRCCONTROL1,
2099 ahc->bus_softc.pci_softc.crccontrol1);
2100 }
2101 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2102 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2103
2104 if ((ahc->features & AHC_ULTRA2) != 0)
2105 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2106
2107 return (ahc_chip_init(ahc));
2108 }
2109
2110 static int
2111 ahc_pci_suspend(struct ahc_softc *ahc)
2112 {
2113 return (ahc_suspend(ahc));
2114 }
2115
2116 static int
2117 ahc_pci_resume(struct ahc_softc *ahc)
2118 {
2119
2120 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2121
2122 /*
2123 * We assume that the OS has restored our register
2124 * mappings, etc. Just update the config space registers
2125 * that the OS doesn't know about and rely on our chip
2126 * reset handler to handle the rest.
2127 */
2128 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2129 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2130 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2131 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2132 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2133 ahc->bus_softc.pci_softc.csize_lattime,
2134 /*bytes*/1);
2135 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2136 struct seeprom_descriptor sd;
2137 u_int sxfrctl1;
2138
2139 sd.sd_ahc = ahc;
2140 sd.sd_control_offset = SEECTL;
2141 sd.sd_status_offset = SEECTL;
2142 sd.sd_dataout_offset = SEECTL;
2143
2144 ahc_acquire_seeprom(ahc, &sd);
2145 configure_termination(ahc, &sd,
2146 ahc->seep_config->adapter_control,
2147 &sxfrctl1);
2148 ahc_release_seeprom(&sd);
2149 }
2150 return (ahc_resume(ahc));
2151 }
2152
2153 static int
2154 ahc_aic785X_setup(struct ahc_softc *ahc)
2155 {
2156 aic_dev_softc_t pci;
2157 uint8_t rev;
2158
2159 pci = ahc->dev_softc;
2160 ahc->channel = 'A';
2161 ahc->chip = AHC_AIC7850;
2162 ahc->features = AHC_AIC7850_FE;
2163 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2164 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2165 if (rev >= 1)
2166 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2167 ahc->instruction_ram_size = 512;
2168 return (0);
2169 }
2170
2171 static int
2172 ahc_aic7860_setup(struct ahc_softc *ahc)
2173 {
2174 aic_dev_softc_t pci;
2175 uint8_t rev;
2176
2177 pci = ahc->dev_softc;
2178 ahc->channel = 'A';
2179 ahc->chip = AHC_AIC7860;
2180 ahc->features = AHC_AIC7860_FE;
2181 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2182 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2183 if (rev >= 1)
2184 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2185 ahc->instruction_ram_size = 512;
2186 return (0);
2187 }
2188
2189 static int
2190 ahc_apa1480_setup(struct ahc_softc *ahc)
2191 {
2192 int error;
2193
2194 error = ahc_aic7860_setup(ahc);
2195 if (error != 0)
2196 return (error);
2197 ahc->features |= AHC_REMOVABLE;
2198 return (0);
2199 }
2200
2201 static int
2202 ahc_aic7870_setup(struct ahc_softc *ahc)
2203 {
2204
2205 ahc->channel = 'A';
2206 ahc->chip = AHC_AIC7870;
2207 ahc->features = AHC_AIC7870_FE;
2208 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2209 ahc->instruction_ram_size = 512;
2210 return (0);
2211 }
2212
2213 static int
2214 ahc_aha394X_setup(struct ahc_softc *ahc)
2215 {
2216 int error;
2217
2218 error = ahc_aic7870_setup(ahc);
2219 if (error == 0)
2220 error = ahc_aha394XX_setup(ahc);
2221 return (error);
2222 }
2223
2224 static int
2225 ahc_aha398X_setup(struct ahc_softc *ahc)
2226 {
2227 int error;
2228
2229 error = ahc_aic7870_setup(ahc);
2230 if (error == 0)
2231 error = ahc_aha398XX_setup(ahc);
2232 return (error);
2233 }
2234
2235 static int
2236 ahc_aha494X_setup(struct ahc_softc *ahc)
2237 {
2238 int error;
2239
2240 error = ahc_aic7870_setup(ahc);
2241 if (error == 0)
2242 error = ahc_aha494XX_setup(ahc);
2243 return (error);
2244 }
2245
2246 static int
2247 ahc_aic7880_setup(struct ahc_softc *ahc)
2248 {
2249 aic_dev_softc_t pci;
2250 uint8_t rev;
2251
2252 pci = ahc->dev_softc;
2253 ahc->channel = 'A';
2254 ahc->chip = AHC_AIC7880;
2255 ahc->features = AHC_AIC7880_FE;
2256 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2257 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2258 if (rev >= 1) {
2259 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2260 } else {
2261 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2262 }
2263 ahc->instruction_ram_size = 512;
2264 return (0);
2265 }
2266
2267 static int
2268 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2269 {
2270
2271 ahc->flags |= AHC_INT50_SPEEDFLEX;
2272 return (ahc_aic7880_setup(ahc));
2273 }
2274
2275 static int
2276 ahc_aha394XU_setup(struct ahc_softc *ahc)
2277 {
2278 int error;
2279
2280 error = ahc_aic7880_setup(ahc);
2281 if (error == 0)
2282 error = ahc_aha394XX_setup(ahc);
2283 return (error);
2284 }
2285
2286 static int
2287 ahc_aha398XU_setup(struct ahc_softc *ahc)
2288 {
2289 int error;
2290
2291 error = ahc_aic7880_setup(ahc);
2292 if (error == 0)
2293 error = ahc_aha398XX_setup(ahc);
2294 return (error);
2295 }
2296
2297 static int
2298 ahc_aic7890_setup(struct ahc_softc *ahc)
2299 {
2300 aic_dev_softc_t pci;
2301 uint8_t rev;
2302
2303 pci = ahc->dev_softc;
2304 ahc->channel = 'A';
2305 ahc->chip = AHC_AIC7890;
2306 ahc->features = AHC_AIC7890_FE;
2307 ahc->flags |= AHC_NEWEEPROM_FMT;
2308 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2309 if (rev == 0)
2310 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2311 ahc->instruction_ram_size = 768;
2312 return (0);
2313 }
2314
2315 static int
2316 ahc_aic7892_setup(struct ahc_softc *ahc)
2317 {
2318
2319 ahc->channel = 'A';
2320 ahc->chip = AHC_AIC7892;
2321 ahc->features = AHC_AIC7892_FE;
2322 ahc->flags |= AHC_NEWEEPROM_FMT;
2323 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2324 ahc->instruction_ram_size = 1024;
2325 return (0);
2326 }
2327
2328 static int
2329 ahc_aic7895_setup(struct ahc_softc *ahc)
2330 {
2331 aic_dev_softc_t pci;
2332 uint8_t rev;
2333
2334 pci = ahc->dev_softc;
2335 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2336 /*
2337 * The 'C' revision of the aic7895 has a few additional features.
2338 */
2339 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2340 if (rev >= 4) {
2341 ahc->chip = AHC_AIC7895C;
2342 ahc->features = AHC_AIC7895C_FE;
2343 } else {
2344 u_int command;
2345
2346 ahc->chip = AHC_AIC7895;
2347 ahc->features = AHC_AIC7895_FE;
2348
2349 /*
2350 * The BIOS disables the use of MWI transactions
2351 * since it does not have the MWI bug work around
2352 * we have. Disabling MWI reduces performance, so
2353 * turn it on again.
2354 */
2355 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2356 command |= PCIM_CMD_MWRICEN;
2357 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2358 ahc->bugs |= AHC_PCI_MWI_BUG;
2359 }
2360 /*
2361 * XXX Does CACHETHEN really not work??? What about PCI retry?
2362 * on C level chips. Need to test, but for now, play it safe.
2363 */
2364 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2365 | AHC_CACHETHEN_BUG;
2366
2367 #if 0
2368 uint32_t devconfig;
2369
2370 /*
2371 * Cachesize must also be zero due to stray DAC
2372 * problem when sitting behind some bridges.
2373 */
2374 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2375 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2376 devconfig |= MRDCEN;
2377 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2378 #endif
2379 ahc->flags |= AHC_NEWEEPROM_FMT;
2380 ahc->instruction_ram_size = 512;
2381 return (0);
2382 }
2383
2384 static int
2385 ahc_aic7896_setup(struct ahc_softc *ahc)
2386 {
2387 aic_dev_softc_t pci;
2388
2389 pci = ahc->dev_softc;
2390 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2391 ahc->chip = AHC_AIC7896;
2392 ahc->features = AHC_AIC7896_FE;
2393 ahc->flags |= AHC_NEWEEPROM_FMT;
2394 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2395 ahc->instruction_ram_size = 768;
2396 return (0);
2397 }
2398
2399 static int
2400 ahc_aic7899_setup(struct ahc_softc *ahc)
2401 {
2402 aic_dev_softc_t pci;
2403
2404 pci = ahc->dev_softc;
2405 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2406 ahc->chip = AHC_AIC7899;
2407 ahc->features = AHC_AIC7899_FE;
2408 ahc->flags |= AHC_NEWEEPROM_FMT;
2409 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2410 ahc->instruction_ram_size = 1024;
2411 return (0);
2412 }
2413
2414 static int
2415 ahc_aha29160C_setup(struct ahc_softc *ahc)
2416 {
2417 int error;
2418
2419 error = ahc_aic7899_setup(ahc);
2420 if (error != 0)
2421 return (error);
2422 ahc->features |= AHC_REMOVABLE;
2423 return (0);
2424 }
2425
2426 static int
2427 ahc_raid_setup(struct ahc_softc *ahc)
2428 {
2429 printf("RAID functionality unsupported\n");
2430 return (ENXIO);
2431 }
2432
2433 static int
2434 ahc_aha394XX_setup(struct ahc_softc *ahc)
2435 {
2436 aic_dev_softc_t pci;
2437
2438 pci = ahc->dev_softc;
2439 switch (aic_get_pci_slot(pci)) {
2440 case AHC_394X_SLOT_CHANNEL_A:
2441 ahc->channel = 'A';
2442 break;
2443 case AHC_394X_SLOT_CHANNEL_B:
2444 ahc->channel = 'B';
2445 break;
2446 default:
2447 printf("adapter at unexpected slot %d\n"
2448 "unable to map to a channel\n",
2449 aic_get_pci_slot(pci));
2450 ahc->channel = 'A';
2451 }
2452 return (0);
2453 }
2454
2455 static int
2456 ahc_aha398XX_setup(struct ahc_softc *ahc)
2457 {
2458 aic_dev_softc_t pci;
2459
2460 pci = ahc->dev_softc;
2461 switch (aic_get_pci_slot(pci)) {
2462 case AHC_398X_SLOT_CHANNEL_A:
2463 ahc->channel = 'A';
2464 break;
2465 case AHC_398X_SLOT_CHANNEL_B:
2466 ahc->channel = 'B';
2467 break;
2468 case AHC_398X_SLOT_CHANNEL_C:
2469 ahc->channel = 'C';
2470 break;
2471 default:
2472 printf("adapter at unexpected slot %d\n"
2473 "unable to map to a channel\n",
2474 aic_get_pci_slot(pci));
2475 ahc->channel = 'A';
2476 break;
2477 }
2478 ahc->flags |= AHC_LARGE_SEEPROM;
2479 return (0);
2480 }
2481
2482 static int
2483 ahc_aha494XX_setup(struct ahc_softc *ahc)
2484 {
2485 aic_dev_softc_t pci;
2486
2487 pci = ahc->dev_softc;
2488 switch (aic_get_pci_slot(pci)) {
2489 case AHC_494X_SLOT_CHANNEL_A:
2490 ahc->channel = 'A';
2491 break;
2492 case AHC_494X_SLOT_CHANNEL_B:
2493 ahc->channel = 'B';
2494 break;
2495 case AHC_494X_SLOT_CHANNEL_C:
2496 ahc->channel = 'C';
2497 break;
2498 case AHC_494X_SLOT_CHANNEL_D:
2499 ahc->channel = 'D';
2500 break;
2501 default:
2502 printf("adapter at unexpected slot %d\n"
2503 "unable to map to a channel\n",
2504 aic_get_pci_slot(pci));
2505 ahc->channel = 'A';
2506 }
2507 ahc->flags |= AHC_LARGE_SEEPROM;
2508 return (0);
2509 }
Cache object: 635b6d7b8f729fe3709cf64bfad894dc
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