Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/alc/if_alc.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/rman.h> 46 #include <sys/queue.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 52 #include <net/bpf.h> 53 #include <net/debugnet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_llc.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <machine/bus.h> 76 #include <machine/in_cksum.h> 77 78 #include <dev/alc/if_alcreg.h> 79 #include <dev/alc/if_alcvar.h> 80 81 /* "device miibus" required. See GENERIC if you get errors here. */ 82 #include "miibus_if.h" 83 #undef ALC_USE_CUSTOM_CSUM 84 85 #ifdef ALC_USE_CUSTOM_CSUM 86 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 87 #else 88 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 89 #endif 90 91 MODULE_DEPEND(alc, pci, 1, 1, 1); 92 MODULE_DEPEND(alc, ether, 1, 1, 1); 93 MODULE_DEPEND(alc, miibus, 1, 1, 1); 94 95 /* Tunables. */ 96 static int msi_disable = 0; 97 static int msix_disable = 0; 98 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 99 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 100 101 /* 102 * Devices supported by this driver. 103 */ 104 static struct alc_ident alc_ident_table[] = { 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 106 "Atheros AR8131 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 108 "Atheros AR8132 PCIe Fast Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 118 "Atheros AR8161 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 120 "Atheros AR8162 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 122 "Atheros AR8171 PCIe Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 124 "Atheros AR8172 PCIe Fast Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 126 "Killer E2200 Gigabit Ethernet" }, 127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 128 "Killer E2400 Gigabit Ethernet" }, 129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 130 "Killer E2500 Gigabit Ethernet" }, 131 { 0, 0, 0, NULL} 132 }; 133 134 static void alc_aspm(struct alc_softc *, int, int); 135 static void alc_aspm_813x(struct alc_softc *, int); 136 static void alc_aspm_816x(struct alc_softc *, int); 137 static int alc_attach(device_t); 138 static int alc_check_boundary(struct alc_softc *); 139 static void alc_config_msi(struct alc_softc *); 140 static int alc_detach(device_t); 141 static void alc_disable_l0s_l1(struct alc_softc *); 142 static int alc_dma_alloc(struct alc_softc *); 143 static void alc_dma_free(struct alc_softc *); 144 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 145 static void alc_dsp_fixup(struct alc_softc *, int); 146 static int alc_encap(struct alc_softc *, struct mbuf **); 147 static struct alc_ident * 148 alc_find_ident(device_t); 149 #ifndef __NO_STRICT_ALIGNMENT 150 static struct mbuf * 151 alc_fixup_rx(struct ifnet *, struct mbuf *); 152 #endif 153 static void alc_get_macaddr(struct alc_softc *); 154 static void alc_get_macaddr_813x(struct alc_softc *); 155 static void alc_get_macaddr_816x(struct alc_softc *); 156 static void alc_get_macaddr_par(struct alc_softc *); 157 static void alc_init(void *); 158 static void alc_init_cmb(struct alc_softc *); 159 static void alc_init_locked(struct alc_softc *); 160 static void alc_init_rr_ring(struct alc_softc *); 161 static int alc_init_rx_ring(struct alc_softc *); 162 static void alc_init_smb(struct alc_softc *); 163 static void alc_init_tx_ring(struct alc_softc *); 164 static void alc_int_task(void *, int); 165 static int alc_intr(void *); 166 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 167 static void alc_mac_config(struct alc_softc *); 168 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 169 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 170 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 171 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 172 static int alc_miibus_readreg(device_t, int, int); 173 static void alc_miibus_statchg(device_t); 174 static int alc_miibus_writereg(device_t, int, int, int); 175 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 176 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 177 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 178 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 179 static int alc_mediachange(struct ifnet *); 180 static int alc_mediachange_locked(struct alc_softc *); 181 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 182 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 183 static void alc_osc_reset(struct alc_softc *); 184 static void alc_phy_down(struct alc_softc *); 185 static void alc_phy_reset(struct alc_softc *); 186 static void alc_phy_reset_813x(struct alc_softc *); 187 static void alc_phy_reset_816x(struct alc_softc *); 188 static int alc_probe(device_t); 189 static void alc_reset(struct alc_softc *); 190 static int alc_resume(device_t); 191 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 192 static int alc_rxintr(struct alc_softc *, int); 193 static void alc_rxfilter(struct alc_softc *); 194 static void alc_rxvlan(struct alc_softc *); 195 static void alc_setlinkspeed(struct alc_softc *); 196 static void alc_setwol(struct alc_softc *); 197 static void alc_setwol_813x(struct alc_softc *); 198 static void alc_setwol_816x(struct alc_softc *); 199 static int alc_shutdown(device_t); 200 static void alc_start(struct ifnet *); 201 static void alc_start_locked(struct ifnet *); 202 static void alc_start_queue(struct alc_softc *); 203 static void alc_start_tx(struct alc_softc *); 204 static void alc_stats_clear(struct alc_softc *); 205 static void alc_stats_update(struct alc_softc *); 206 static void alc_stop(struct alc_softc *); 207 static void alc_stop_mac(struct alc_softc *); 208 static void alc_stop_queue(struct alc_softc *); 209 static int alc_suspend(device_t); 210 static void alc_sysctl_node(struct alc_softc *); 211 static void alc_tick(void *); 212 static void alc_txeof(struct alc_softc *); 213 static void alc_watchdog(struct alc_softc *); 214 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 215 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 216 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 217 218 DEBUGNET_DEFINE(alc); 219 220 static device_method_t alc_methods[] = { 221 /* Device interface. */ 222 DEVMETHOD(device_probe, alc_probe), 223 DEVMETHOD(device_attach, alc_attach), 224 DEVMETHOD(device_detach, alc_detach), 225 DEVMETHOD(device_shutdown, alc_shutdown), 226 DEVMETHOD(device_suspend, alc_suspend), 227 DEVMETHOD(device_resume, alc_resume), 228 229 /* MII interface. */ 230 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 231 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 232 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 233 234 DEVMETHOD_END 235 }; 236 237 static driver_t alc_driver = { 238 "alc", 239 alc_methods, 240 sizeof(struct alc_softc) 241 }; 242 243 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 244 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 245 nitems(alc_ident_table) - 1); 246 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 247 248 static struct resource_spec alc_res_spec_mem[] = { 249 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 250 { -1, 0, 0 } 251 }; 252 253 static struct resource_spec alc_irq_spec_legacy[] = { 254 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 255 { -1, 0, 0 } 256 }; 257 258 static struct resource_spec alc_irq_spec_msi[] = { 259 { SYS_RES_IRQ, 1, RF_ACTIVE }, 260 { -1, 0, 0 } 261 }; 262 263 static struct resource_spec alc_irq_spec_msix[] = { 264 { SYS_RES_IRQ, 1, RF_ACTIVE }, 265 { -1, 0, 0 } 266 }; 267 268 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 269 270 static int 271 alc_miibus_readreg(device_t dev, int phy, int reg) 272 { 273 struct alc_softc *sc; 274 int v; 275 276 sc = device_get_softc(dev); 277 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 278 v = alc_mii_readreg_816x(sc, phy, reg); 279 else 280 v = alc_mii_readreg_813x(sc, phy, reg); 281 return (v); 282 } 283 284 static uint32_t 285 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 286 { 287 uint32_t v; 288 int i; 289 290 /* 291 * For AR8132 fast ethernet controller, do not report 1000baseT 292 * capability to mii(4). Even though AR8132 uses the same 293 * model/revision number of F1 gigabit PHY, the PHY has no 294 * ability to establish 1000baseT link. 295 */ 296 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 297 reg == MII_EXTSR) 298 return (0); 299 300 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 301 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 302 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 303 DELAY(5); 304 v = CSR_READ_4(sc, ALC_MDIO); 305 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 306 break; 307 } 308 309 if (i == 0) { 310 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 311 return (0); 312 } 313 314 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 315 } 316 317 static uint32_t 318 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 319 { 320 uint32_t clk, v; 321 int i; 322 323 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 324 clk = MDIO_CLK_25_128; 325 else 326 clk = MDIO_CLK_25_4; 327 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 328 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 329 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 330 DELAY(5); 331 v = CSR_READ_4(sc, ALC_MDIO); 332 if ((v & MDIO_OP_BUSY) == 0) 333 break; 334 } 335 336 if (i == 0) { 337 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 338 return (0); 339 } 340 341 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 342 } 343 344 static int 345 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 346 { 347 struct alc_softc *sc; 348 int v; 349 350 sc = device_get_softc(dev); 351 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 352 v = alc_mii_writereg_816x(sc, phy, reg, val); 353 else 354 v = alc_mii_writereg_813x(sc, phy, reg, val); 355 return (v); 356 } 357 358 static uint32_t 359 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 360 { 361 uint32_t v; 362 int i; 363 364 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 365 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 366 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 367 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 368 DELAY(5); 369 v = CSR_READ_4(sc, ALC_MDIO); 370 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 371 break; 372 } 373 374 if (i == 0) 375 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 376 377 return (0); 378 } 379 380 static uint32_t 381 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 382 { 383 uint32_t clk, v; 384 int i; 385 386 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 387 clk = MDIO_CLK_25_128; 388 else 389 clk = MDIO_CLK_25_4; 390 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 391 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 392 MDIO_SUP_PREAMBLE | clk); 393 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 394 DELAY(5); 395 v = CSR_READ_4(sc, ALC_MDIO); 396 if ((v & MDIO_OP_BUSY) == 0) 397 break; 398 } 399 400 if (i == 0) 401 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 402 403 return (0); 404 } 405 406 static void 407 alc_miibus_statchg(device_t dev) 408 { 409 struct alc_softc *sc; 410 struct mii_data *mii; 411 struct ifnet *ifp; 412 uint32_t reg; 413 414 sc = device_get_softc(dev); 415 416 mii = device_get_softc(sc->alc_miibus); 417 ifp = sc->alc_ifp; 418 if (mii == NULL || ifp == NULL || 419 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 420 return; 421 422 sc->alc_flags &= ~ALC_FLAG_LINK; 423 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 424 (IFM_ACTIVE | IFM_AVALID)) { 425 switch (IFM_SUBTYPE(mii->mii_media_active)) { 426 case IFM_10_T: 427 case IFM_100_TX: 428 sc->alc_flags |= ALC_FLAG_LINK; 429 break; 430 case IFM_1000_T: 431 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 432 sc->alc_flags |= ALC_FLAG_LINK; 433 break; 434 default: 435 break; 436 } 437 } 438 /* Stop Rx/Tx MACs. */ 439 alc_stop_mac(sc); 440 441 /* Program MACs with resolved speed/duplex/flow-control. */ 442 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 443 alc_start_queue(sc); 444 alc_mac_config(sc); 445 /* Re-enable Tx/Rx MACs. */ 446 reg = CSR_READ_4(sc, ALC_MAC_CFG); 447 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 448 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 449 } 450 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 451 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 452 } 453 454 static uint32_t 455 alc_miidbg_readreg(struct alc_softc *sc, int reg) 456 { 457 458 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 459 reg); 460 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 461 ALC_MII_DBG_DATA)); 462 } 463 464 static uint32_t 465 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 466 { 467 468 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 469 reg); 470 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 471 ALC_MII_DBG_DATA, val)); 472 } 473 474 static uint32_t 475 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 476 { 477 uint32_t clk, v; 478 int i; 479 480 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 481 EXT_MDIO_DEVADDR(devaddr)); 482 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 483 clk = MDIO_CLK_25_128; 484 else 485 clk = MDIO_CLK_25_4; 486 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 487 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 488 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 489 DELAY(5); 490 v = CSR_READ_4(sc, ALC_MDIO); 491 if ((v & MDIO_OP_BUSY) == 0) 492 break; 493 } 494 495 if (i == 0) { 496 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 497 devaddr, reg); 498 return (0); 499 } 500 501 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 502 } 503 504 static uint32_t 505 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 506 { 507 uint32_t clk, v; 508 int i; 509 510 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 511 EXT_MDIO_DEVADDR(devaddr)); 512 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 513 clk = MDIO_CLK_25_128; 514 else 515 clk = MDIO_CLK_25_4; 516 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 517 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 518 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 519 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 520 DELAY(5); 521 v = CSR_READ_4(sc, ALC_MDIO); 522 if ((v & MDIO_OP_BUSY) == 0) 523 break; 524 } 525 526 if (i == 0) 527 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 528 devaddr, reg); 529 530 return (0); 531 } 532 533 static void 534 alc_dsp_fixup(struct alc_softc *sc, int media) 535 { 536 uint16_t agc, len, val; 537 538 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 539 return; 540 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 541 return; 542 543 /* 544 * Vendor PHY magic. 545 * 1000BT/AZ, wrong cable length 546 */ 547 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 548 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 549 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 550 EXT_CLDCTL6_CAB_LEN_MASK; 551 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 552 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 553 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 554 agc > DBG_AGC_LONG1G_LIMT) || 555 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 556 agc > DBG_AGC_LONG1G_LIMT)) { 557 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 558 DBG_AZ_ANADECT_LONG); 559 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 560 MII_EXT_ANEG_AFE); 561 val |= ANEG_AFEE_10BT_100M_TH; 562 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 563 val); 564 } else { 565 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 566 DBG_AZ_ANADECT_DEFAULT); 567 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 568 MII_EXT_ANEG_AFE); 569 val &= ~ANEG_AFEE_10BT_100M_TH; 570 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 571 val); 572 } 573 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 574 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 575 if (media == IFM_1000_T) { 576 /* 577 * Giga link threshold, raise the tolerance of 578 * noise 50%. 579 */ 580 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 581 val &= ~DBG_MSE20DB_TH_MASK; 582 val |= (DBG_MSE20DB_TH_HI << 583 DBG_MSE20DB_TH_SHIFT); 584 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 585 } else if (media == IFM_100_TX) 586 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 587 DBG_MSE16DB_UP); 588 } 589 } else { 590 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 591 val &= ~ANEG_AFEE_10BT_100M_TH; 592 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 593 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 594 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 595 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 596 DBG_MSE16DB_DOWN); 597 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 598 val &= ~DBG_MSE20DB_TH_MASK; 599 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 600 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 601 } 602 } 603 } 604 605 static void 606 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 607 { 608 struct alc_softc *sc; 609 struct mii_data *mii; 610 611 sc = ifp->if_softc; 612 ALC_LOCK(sc); 613 if ((ifp->if_flags & IFF_UP) == 0) { 614 ALC_UNLOCK(sc); 615 return; 616 } 617 mii = device_get_softc(sc->alc_miibus); 618 619 mii_pollstat(mii); 620 ifmr->ifm_status = mii->mii_media_status; 621 ifmr->ifm_active = mii->mii_media_active; 622 ALC_UNLOCK(sc); 623 } 624 625 static int 626 alc_mediachange(struct ifnet *ifp) 627 { 628 struct alc_softc *sc; 629 int error; 630 631 sc = ifp->if_softc; 632 ALC_LOCK(sc); 633 error = alc_mediachange_locked(sc); 634 ALC_UNLOCK(sc); 635 636 return (error); 637 } 638 639 static int 640 alc_mediachange_locked(struct alc_softc *sc) 641 { 642 struct mii_data *mii; 643 struct mii_softc *miisc; 644 int error; 645 646 ALC_LOCK_ASSERT(sc); 647 648 mii = device_get_softc(sc->alc_miibus); 649 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 650 PHY_RESET(miisc); 651 error = mii_mediachg(mii); 652 653 return (error); 654 } 655 656 static struct alc_ident * 657 alc_find_ident(device_t dev) 658 { 659 struct alc_ident *ident; 660 uint16_t vendor, devid; 661 662 vendor = pci_get_vendor(dev); 663 devid = pci_get_device(dev); 664 for (ident = alc_ident_table; ident->name != NULL; ident++) { 665 if (vendor == ident->vendorid && devid == ident->deviceid) 666 return (ident); 667 } 668 669 return (NULL); 670 } 671 672 static int 673 alc_probe(device_t dev) 674 { 675 struct alc_ident *ident; 676 677 ident = alc_find_ident(dev); 678 if (ident != NULL) { 679 device_set_desc(dev, ident->name); 680 return (BUS_PROBE_DEFAULT); 681 } 682 683 return (ENXIO); 684 } 685 686 static void 687 alc_get_macaddr(struct alc_softc *sc) 688 { 689 690 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 691 alc_get_macaddr_816x(sc); 692 else 693 alc_get_macaddr_813x(sc); 694 } 695 696 static void 697 alc_get_macaddr_813x(struct alc_softc *sc) 698 { 699 uint32_t opt; 700 uint16_t val; 701 int eeprom, i; 702 703 eeprom = 0; 704 opt = CSR_READ_4(sc, ALC_OPT_CFG); 705 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 706 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 707 /* 708 * EEPROM found, let TWSI reload EEPROM configuration. 709 * This will set ethernet address of controller. 710 */ 711 eeprom++; 712 switch (sc->alc_ident->deviceid) { 713 case DEVICEID_ATHEROS_AR8131: 714 case DEVICEID_ATHEROS_AR8132: 715 if ((opt & OPT_CFG_CLK_ENB) == 0) { 716 opt |= OPT_CFG_CLK_ENB; 717 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 718 CSR_READ_4(sc, ALC_OPT_CFG); 719 DELAY(1000); 720 } 721 break; 722 case DEVICEID_ATHEROS_AR8151: 723 case DEVICEID_ATHEROS_AR8151_V2: 724 case DEVICEID_ATHEROS_AR8152_B: 725 case DEVICEID_ATHEROS_AR8152_B2: 726 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_ADDR, 0x00); 728 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_DATA); 730 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA, val & 0xFF7F); 732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_ADDR, 0x3B); 734 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 735 ALC_MII_DBG_DATA); 736 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 737 ALC_MII_DBG_DATA, val | 0x0008); 738 DELAY(20); 739 break; 740 } 741 742 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 743 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 744 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 745 CSR_READ_4(sc, ALC_WOL_CFG); 746 747 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 748 TWSI_CFG_SW_LD_START); 749 for (i = 100; i > 0; i--) { 750 DELAY(1000); 751 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 752 TWSI_CFG_SW_LD_START) == 0) 753 break; 754 } 755 if (i == 0) 756 device_printf(sc->alc_dev, 757 "reloading EEPROM timeout!\n"); 758 } else { 759 if (bootverbose) 760 device_printf(sc->alc_dev, "EEPROM not found!\n"); 761 } 762 if (eeprom != 0) { 763 switch (sc->alc_ident->deviceid) { 764 case DEVICEID_ATHEROS_AR8131: 765 case DEVICEID_ATHEROS_AR8132: 766 if ((opt & OPT_CFG_CLK_ENB) != 0) { 767 opt &= ~OPT_CFG_CLK_ENB; 768 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 769 CSR_READ_4(sc, ALC_OPT_CFG); 770 DELAY(1000); 771 } 772 break; 773 case DEVICEID_ATHEROS_AR8151: 774 case DEVICEID_ATHEROS_AR8151_V2: 775 case DEVICEID_ATHEROS_AR8152_B: 776 case DEVICEID_ATHEROS_AR8152_B2: 777 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_ADDR, 0x00); 779 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA); 781 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA, val | 0x0080); 783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_ADDR, 0x3B); 785 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 786 ALC_MII_DBG_DATA); 787 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 788 ALC_MII_DBG_DATA, val & 0xFFF7); 789 DELAY(20); 790 break; 791 } 792 } 793 794 alc_get_macaddr_par(sc); 795 } 796 797 static void 798 alc_get_macaddr_816x(struct alc_softc *sc) 799 { 800 uint32_t reg; 801 int i, reloaded; 802 803 reloaded = 0; 804 /* Try to reload station address via TWSI. */ 805 for (i = 100; i > 0; i--) { 806 reg = CSR_READ_4(sc, ALC_SLD); 807 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 808 break; 809 DELAY(1000); 810 } 811 if (i != 0) { 812 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 813 for (i = 100; i > 0; i--) { 814 DELAY(1000); 815 reg = CSR_READ_4(sc, ALC_SLD); 816 if ((reg & SLD_START) == 0) 817 break; 818 } 819 if (i != 0) 820 reloaded++; 821 else if (bootverbose) 822 device_printf(sc->alc_dev, 823 "reloading station address via TWSI timed out!\n"); 824 } 825 826 /* Try to reload station address from EEPROM or FLASH. */ 827 if (reloaded == 0) { 828 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 829 if ((reg & (EEPROM_LD_EEPROM_EXIST | 830 EEPROM_LD_FLASH_EXIST)) != 0) { 831 for (i = 100; i > 0; i--) { 832 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 833 if ((reg & (EEPROM_LD_PROGRESS | 834 EEPROM_LD_START)) == 0) 835 break; 836 DELAY(1000); 837 } 838 if (i != 0) { 839 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 840 EEPROM_LD_START); 841 for (i = 100; i > 0; i--) { 842 DELAY(1000); 843 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 844 if ((reg & EEPROM_LD_START) == 0) 845 break; 846 } 847 } else if (bootverbose) 848 device_printf(sc->alc_dev, 849 "reloading EEPROM/FLASH timed out!\n"); 850 } 851 } 852 853 alc_get_macaddr_par(sc); 854 } 855 856 static void 857 alc_get_macaddr_par(struct alc_softc *sc) 858 { 859 uint32_t ea[2]; 860 861 ea[0] = CSR_READ_4(sc, ALC_PAR0); 862 ea[1] = CSR_READ_4(sc, ALC_PAR1); 863 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 864 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 865 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 866 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 867 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 868 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 869 } 870 871 static void 872 alc_disable_l0s_l1(struct alc_softc *sc) 873 { 874 uint32_t pmcfg; 875 876 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 877 /* Another magic from vendor. */ 878 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 879 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 880 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 881 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 882 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 883 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 884 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 885 } 886 } 887 888 static void 889 alc_phy_reset(struct alc_softc *sc) 890 { 891 892 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 893 alc_phy_reset_816x(sc); 894 else 895 alc_phy_reset_813x(sc); 896 } 897 898 static void 899 alc_phy_reset_813x(struct alc_softc *sc) 900 { 901 uint16_t data; 902 903 /* Reset magic from Linux. */ 904 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 905 CSR_READ_2(sc, ALC_GPHY_CFG); 906 DELAY(10 * 1000); 907 908 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 909 GPHY_CFG_SEL_ANA_RESET); 910 CSR_READ_2(sc, ALC_GPHY_CFG); 911 DELAY(10 * 1000); 912 913 /* DSP fixup, Vendor magic. */ 914 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 915 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 916 ALC_MII_DBG_ADDR, 0x000A); 917 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_DATA); 919 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_DATA, data & 0xDFFF); 921 } 922 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 923 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 924 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 926 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_ADDR, 0x003B); 928 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_DATA); 930 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 931 ALC_MII_DBG_DATA, data & 0xFFF7); 932 DELAY(20 * 1000); 933 } 934 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 935 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 936 ALC_MII_DBG_ADDR, 0x0029); 937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 938 ALC_MII_DBG_DATA, 0x929D); 939 } 940 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 941 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 942 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 944 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 945 ALC_MII_DBG_ADDR, 0x0029); 946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 947 ALC_MII_DBG_DATA, 0xB6DD); 948 } 949 950 /* Load DSP codes, vendor magic. */ 951 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 952 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 953 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 954 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_DATA, data); 957 958 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 959 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 960 ANA_SERDES_EN_LCKDT; 961 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 962 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 964 ALC_MII_DBG_DATA, data); 965 966 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 967 ANA_LONG_CABLE_TH_100_MASK) | 968 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 969 ANA_SHORT_CABLE_TH_100_SHIFT) | 970 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 971 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 972 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 974 ALC_MII_DBG_DATA, data); 975 976 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 977 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 978 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 979 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 980 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 981 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_DATA, data); 984 985 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 986 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 987 ANA_OEN_125M; 988 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 989 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 991 ALC_MII_DBG_DATA, data); 992 DELAY(1000); 993 994 /* Disable hibernation. */ 995 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 996 0x0029); 997 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 998 ALC_MII_DBG_DATA); 999 data &= ~0x8000; 1000 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1001 data); 1002 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1004 0x000B); 1005 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1006 ALC_MII_DBG_DATA); 1007 data &= ~0x8000; 1008 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1009 data); 1010 } 1011 1012 static void 1013 alc_phy_reset_816x(struct alc_softc *sc) 1014 { 1015 uint32_t val; 1016 1017 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1018 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1019 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1020 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1021 val |= GPHY_CFG_SEL_ANA_RESET; 1022 #ifdef notyet 1023 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1024 #else 1025 /* Disable PHY hibernation. */ 1026 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1027 #endif 1028 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1029 DELAY(10); 1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1031 DELAY(800); 1032 1033 /* Vendor PHY magic. */ 1034 #ifdef notyet 1035 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1036 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1037 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1038 EXT_VDRVBIAS_DEFAULT); 1039 #else 1040 /* Disable PHY hibernation. */ 1041 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1042 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1043 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1044 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1045 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1046 #endif 1047 1048 /* XXX Disable EEE. */ 1049 val = CSR_READ_4(sc, ALC_LPI_CTL); 1050 val &= ~LPI_CTL_ENB; 1051 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1052 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1053 1054 /* PHY power saving. */ 1055 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1056 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1057 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1058 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1059 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1060 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1061 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1062 1063 /* RTL8139C, 120m issue. */ 1064 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1065 ANEG_NLP78_120M_DEFAULT); 1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1067 ANEG_S3DIG10_DEFAULT); 1068 1069 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1070 /* Turn off half amplitude. */ 1071 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1072 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1073 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1074 /* Turn off Green feature. */ 1075 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1076 val |= DBG_GREENCFG2_BP_GREEN; 1077 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1078 /* Turn off half bias. */ 1079 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1080 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1081 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1082 } 1083 } 1084 1085 static void 1086 alc_phy_down(struct alc_softc *sc) 1087 { 1088 uint32_t gphy; 1089 1090 switch (sc->alc_ident->deviceid) { 1091 case DEVICEID_ATHEROS_AR8161: 1092 case DEVICEID_ATHEROS_E2200: 1093 case DEVICEID_ATHEROS_E2400: 1094 case DEVICEID_ATHEROS_E2500: 1095 case DEVICEID_ATHEROS_AR8162: 1096 case DEVICEID_ATHEROS_AR8171: 1097 case DEVICEID_ATHEROS_AR8172: 1098 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1099 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1100 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1101 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1102 GPHY_CFG_SEL_ANA_RESET; 1103 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1104 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1105 break; 1106 case DEVICEID_ATHEROS_AR8151: 1107 case DEVICEID_ATHEROS_AR8151_V2: 1108 case DEVICEID_ATHEROS_AR8152_B: 1109 case DEVICEID_ATHEROS_AR8152_B2: 1110 /* 1111 * GPHY power down caused more problems on AR8151 v2.0. 1112 * When driver is reloaded after GPHY power down, 1113 * accesses to PHY/MAC registers hung the system. Only 1114 * cold boot recovered from it. I'm not sure whether 1115 * AR8151 v1.0 also requires this one though. I don't 1116 * have AR8151 v1.0 controller in hand. 1117 * The only option left is to isolate the PHY and 1118 * initiates power down the PHY which in turn saves 1119 * more power when driver is unloaded. 1120 */ 1121 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1122 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1123 break; 1124 default: 1125 /* Force PHY down. */ 1126 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1127 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1128 GPHY_CFG_PWDOWN_HW); 1129 DELAY(1000); 1130 break; 1131 } 1132 } 1133 1134 static void 1135 alc_aspm(struct alc_softc *sc, int init, int media) 1136 { 1137 1138 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1139 alc_aspm_816x(sc, init); 1140 else 1141 alc_aspm_813x(sc, media); 1142 } 1143 1144 static void 1145 alc_aspm_813x(struct alc_softc *sc, int media) 1146 { 1147 uint32_t pmcfg; 1148 uint16_t linkcfg; 1149 1150 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1151 return; 1152 1153 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1154 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1155 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1156 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1157 PCIER_LINK_CTL); 1158 else 1159 linkcfg = 0; 1160 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1161 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1162 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1163 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1164 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1165 1166 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1167 /* Disable extended sync except AR8152 B v1.0 */ 1168 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1169 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1170 sc->alc_rev == ATHEROS_AR8152_B_V10) 1171 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1173 linkcfg); 1174 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1175 PM_CFG_HOTRST); 1176 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1177 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1178 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1179 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1180 PM_CFG_PM_REQ_TIMER_SHIFT); 1181 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1182 } 1183 1184 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1185 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1186 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1187 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1188 pmcfg |= PM_CFG_ASPM_L1_ENB; 1189 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1190 if (sc->alc_ident->deviceid == 1191 DEVICEID_ATHEROS_AR8152_B) 1192 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1193 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1194 PM_CFG_SERDES_PLL_L1_ENB | 1195 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1196 pmcfg |= PM_CFG_CLK_SWH_L1; 1197 if (media == IFM_100_TX || media == IFM_1000_T) { 1198 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1199 switch (sc->alc_ident->deviceid) { 1200 case DEVICEID_ATHEROS_AR8152_B: 1201 pmcfg |= (7 << 1202 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1203 break; 1204 case DEVICEID_ATHEROS_AR8152_B2: 1205 case DEVICEID_ATHEROS_AR8151_V2: 1206 pmcfg |= (4 << 1207 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1208 break; 1209 default: 1210 pmcfg |= (15 << 1211 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1212 break; 1213 } 1214 } 1215 } else { 1216 pmcfg |= PM_CFG_SERDES_L1_ENB | 1217 PM_CFG_SERDES_PLL_L1_ENB | 1218 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1219 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1220 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1221 } 1222 } else { 1223 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1224 PM_CFG_SERDES_PLL_L1_ENB); 1225 pmcfg |= PM_CFG_CLK_SWH_L1; 1226 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1227 pmcfg |= PM_CFG_ASPM_L1_ENB; 1228 } 1229 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1230 } 1231 1232 static void 1233 alc_aspm_816x(struct alc_softc *sc, int init) 1234 { 1235 uint32_t pmcfg; 1236 1237 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1238 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1239 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1240 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1241 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1242 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1243 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1244 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1245 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1246 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1247 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1248 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1249 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1250 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1251 (sc->alc_rev & 0x01) != 0) 1252 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1253 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1254 /* Link up, enable both L0s, L1s. */ 1255 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1256 PM_CFG_MAC_ASPM_CHK; 1257 } else { 1258 if (init != 0) 1259 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1260 PM_CFG_MAC_ASPM_CHK; 1261 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1262 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1263 } 1264 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1265 } 1266 1267 static void 1268 alc_init_pcie(struct alc_softc *sc) 1269 { 1270 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1271 uint32_t cap, ctl, val; 1272 int state; 1273 1274 /* Clear data link and flow-control protocol error. */ 1275 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1276 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1277 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1278 1279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1280 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1281 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1282 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1283 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1284 PCIE_PHYMISC_FORCE_RCV_DET); 1285 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1286 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1287 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1288 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1289 PCIE_PHYMISC2_SERDES_TH_MASK); 1290 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1291 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1292 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1293 } 1294 /* Disable ASPM L0S and L1. */ 1295 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1296 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1297 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1298 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1299 sc->alc_rcb = DMA_CFG_RCB_128; 1300 if (bootverbose) 1301 device_printf(sc->alc_dev, "RCB %u bytes\n", 1302 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1303 state = ctl & PCIEM_LINK_CTL_ASPMC; 1304 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1305 sc->alc_flags |= ALC_FLAG_L0S; 1306 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1307 sc->alc_flags |= ALC_FLAG_L1S; 1308 if (bootverbose) 1309 device_printf(sc->alc_dev, "ASPM %s %s\n", 1310 aspm_state[state], 1311 state == 0 ? "disabled" : "enabled"); 1312 alc_disable_l0s_l1(sc); 1313 } else { 1314 if (bootverbose) 1315 device_printf(sc->alc_dev, 1316 "no ASPM support\n"); 1317 } 1318 } else { 1319 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1320 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1321 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1322 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1323 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1324 (sc->alc_rev & 0x01) != 0) { 1325 if ((val & MASTER_WAKEN_25M) == 0 || 1326 (val & MASTER_CLK_SEL_DIS) == 0) { 1327 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1328 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1329 } 1330 } else { 1331 if ((val & MASTER_WAKEN_25M) == 0 || 1332 (val & MASTER_CLK_SEL_DIS) != 0) { 1333 val |= MASTER_WAKEN_25M; 1334 val &= ~MASTER_CLK_SEL_DIS; 1335 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1336 } 1337 } 1338 } 1339 alc_aspm(sc, 1, IFM_UNKNOWN); 1340 } 1341 1342 static void 1343 alc_config_msi(struct alc_softc *sc) 1344 { 1345 uint32_t ctl, mod; 1346 1347 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1348 /* 1349 * It seems interrupt moderation is controlled by 1350 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1351 * Driver uses RX interrupt moderation parameter to 1352 * program ALC_MSI_RETRANS_TIMER register. 1353 */ 1354 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1355 ctl &= ~MSI_RETRANS_TIMER_MASK; 1356 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1357 mod = ALC_USECS(sc->alc_int_rx_mod); 1358 if (mod == 0) 1359 mod = 1; 1360 ctl |= mod; 1361 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1362 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1363 MSI_RETRANS_MASK_SEL_STD); 1364 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_LINE); 1367 else 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1369 } 1370 } 1371 1372 static int 1373 alc_attach(device_t dev) 1374 { 1375 struct alc_softc *sc; 1376 struct ifnet *ifp; 1377 int base, error, i, msic, msixc; 1378 uint16_t burst; 1379 1380 error = 0; 1381 sc = device_get_softc(dev); 1382 sc->alc_dev = dev; 1383 sc->alc_rev = pci_get_revid(dev); 1384 1385 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1386 MTX_DEF); 1387 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1388 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1389 sc->alc_ident = alc_find_ident(dev); 1390 1391 /* Map the device. */ 1392 pci_enable_busmaster(dev); 1393 sc->alc_res_spec = alc_res_spec_mem; 1394 sc->alc_irq_spec = alc_irq_spec_legacy; 1395 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1396 if (error != 0) { 1397 device_printf(dev, "cannot allocate memory resources.\n"); 1398 goto fail; 1399 } 1400 1401 /* Set PHY address. */ 1402 sc->alc_phyaddr = ALC_PHY_ADDR; 1403 1404 /* 1405 * One odd thing is AR8132 uses the same PHY hardware(F1 1406 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1407 * the PHY supports 1000Mbps but that's not true. The PHY 1408 * used in AR8132 can't establish gigabit link even if it 1409 * shows the same PHY model/revision number of AR8131. 1410 */ 1411 switch (sc->alc_ident->deviceid) { 1412 case DEVICEID_ATHEROS_E2200: 1413 case DEVICEID_ATHEROS_E2400: 1414 case DEVICEID_ATHEROS_E2500: 1415 sc->alc_flags |= ALC_FLAG_E2X00; 1416 /* FALLTHROUGH */ 1417 case DEVICEID_ATHEROS_AR8161: 1418 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1419 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1420 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1421 /* FALLTHROUGH */ 1422 case DEVICEID_ATHEROS_AR8171: 1423 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1424 break; 1425 case DEVICEID_ATHEROS_AR8162: 1426 case DEVICEID_ATHEROS_AR8172: 1427 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1428 break; 1429 case DEVICEID_ATHEROS_AR8152_B: 1430 case DEVICEID_ATHEROS_AR8152_B2: 1431 sc->alc_flags |= ALC_FLAG_APS; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8132: 1434 sc->alc_flags |= ALC_FLAG_FASTETHER; 1435 break; 1436 case DEVICEID_ATHEROS_AR8151: 1437 case DEVICEID_ATHEROS_AR8151_V2: 1438 sc->alc_flags |= ALC_FLAG_APS; 1439 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1440 sc->alc_flags |= ALC_FLAG_MT; 1441 /* FALLTHROUGH */ 1442 default: 1443 break; 1444 } 1445 sc->alc_flags |= ALC_FLAG_JUMBO; 1446 1447 /* 1448 * It seems that AR813x/AR815x has silicon bug for SMB. In 1449 * addition, Atheros said that enabling SMB wouldn't improve 1450 * performance. However I think it's bad to access lots of 1451 * registers to extract MAC statistics. 1452 */ 1453 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1454 /* 1455 * Don't use Tx CMB. It is known to have silicon bug. 1456 */ 1457 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1458 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1459 MASTER_CHIP_REV_SHIFT; 1460 if (bootverbose) { 1461 device_printf(dev, "PCI device revision : 0x%04x\n", 1462 sc->alc_rev); 1463 device_printf(dev, "Chip id/revision : 0x%04x\n", 1464 sc->alc_chip_rev); 1465 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1466 device_printf(dev, "AR816x revision : 0x%x\n", 1467 AR816X_REV(sc->alc_rev)); 1468 } 1469 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1470 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1471 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1472 1473 /* Initialize DMA parameters. */ 1474 sc->alc_dma_rd_burst = 0; 1475 sc->alc_dma_wr_burst = 0; 1476 sc->alc_rcb = DMA_CFG_RCB_64; 1477 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1478 sc->alc_flags |= ALC_FLAG_PCIE; 1479 sc->alc_expcap = base; 1480 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1481 sc->alc_dma_rd_burst = 1482 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1483 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1484 if (bootverbose) { 1485 device_printf(dev, "Read request size : %u bytes.\n", 1486 alc_dma_burst[sc->alc_dma_rd_burst]); 1487 device_printf(dev, "TLP payload size : %u bytes.\n", 1488 alc_dma_burst[sc->alc_dma_wr_burst]); 1489 } 1490 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1491 sc->alc_dma_rd_burst = 3; 1492 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1493 sc->alc_dma_wr_burst = 3; 1494 /* 1495 * Force maximum payload size to 128 bytes for 1496 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1497 * Otherwise it triggers DMA write error. 1498 */ 1499 if ((sc->alc_flags & 1500 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1501 sc->alc_dma_wr_burst = 0; 1502 alc_init_pcie(sc); 1503 } 1504 1505 /* Reset PHY. */ 1506 alc_phy_reset(sc); 1507 1508 /* Reset the ethernet controller. */ 1509 alc_stop_mac(sc); 1510 alc_reset(sc); 1511 1512 /* Allocate IRQ resources. */ 1513 msixc = pci_msix_count(dev); 1514 msic = pci_msi_count(dev); 1515 if (bootverbose) { 1516 device_printf(dev, "MSIX count : %d\n", msixc); 1517 device_printf(dev, "MSI count : %d\n", msic); 1518 } 1519 if (msixc > 1) 1520 msixc = 1; 1521 if (msic > 1) 1522 msic = 1; 1523 /* 1524 * Prefer MSIX over MSI. 1525 * AR816x controller has a silicon bug that MSI interrupt 1526 * does not assert if PCIM_CMD_INTxDIS bit of command 1527 * register is set. pci(4) was taught to handle that case. 1528 */ 1529 if (msix_disable == 0 || msi_disable == 0) { 1530 if (msix_disable == 0 && msixc > 0 && 1531 pci_alloc_msix(dev, &msixc) == 0) { 1532 if (msic == 1) { 1533 device_printf(dev, 1534 "Using %d MSIX message(s).\n", msixc); 1535 sc->alc_flags |= ALC_FLAG_MSIX; 1536 sc->alc_irq_spec = alc_irq_spec_msix; 1537 } else 1538 pci_release_msi(dev); 1539 } 1540 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1541 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1542 if (msic == 1) { 1543 device_printf(dev, 1544 "Using %d MSI message(s).\n", msic); 1545 sc->alc_flags |= ALC_FLAG_MSI; 1546 sc->alc_irq_spec = alc_irq_spec_msi; 1547 } else 1548 pci_release_msi(dev); 1549 } 1550 } 1551 1552 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1553 if (error != 0) { 1554 device_printf(dev, "cannot allocate IRQ resources.\n"); 1555 goto fail; 1556 } 1557 1558 /* Create device sysctl node. */ 1559 alc_sysctl_node(sc); 1560 1561 if ((error = alc_dma_alloc(sc)) != 0) 1562 goto fail; 1563 1564 /* Load station address. */ 1565 alc_get_macaddr(sc); 1566 1567 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1568 if (ifp == NULL) { 1569 device_printf(dev, "cannot allocate ifnet structure.\n"); 1570 error = ENXIO; 1571 goto fail; 1572 } 1573 1574 ifp->if_softc = sc; 1575 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1576 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1577 ifp->if_ioctl = alc_ioctl; 1578 ifp->if_start = alc_start; 1579 ifp->if_init = alc_init; 1580 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1581 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1582 IFQ_SET_READY(&ifp->if_snd); 1583 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1584 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1585 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1586 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1587 sc->alc_flags |= ALC_FLAG_PM; 1588 sc->alc_pmcap = base; 1589 } 1590 ifp->if_capenable = ifp->if_capabilities; 1591 1592 /* Set up MII bus. */ 1593 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1594 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1595 MIIF_DOPAUSE); 1596 if (error != 0) { 1597 device_printf(dev, "attaching PHYs failed\n"); 1598 goto fail; 1599 } 1600 1601 ether_ifattach(ifp, sc->alc_eaddr); 1602 1603 /* VLAN capability setup. */ 1604 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1605 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1606 ifp->if_capenable = ifp->if_capabilities; 1607 /* 1608 * XXX 1609 * It seems enabling Tx checksum offloading makes more trouble. 1610 * Sometimes the controller does not receive any frames when 1611 * Tx checksum offloading is enabled. I'm not sure whether this 1612 * is a bug in Tx checksum offloading logic or I got broken 1613 * sample boards. To safety, don't enable Tx checksum offloading 1614 * by default but give chance to users to toggle it if they know 1615 * their controllers work without problems. 1616 * Fortunately, Tx checksum offloading for AR816x family 1617 * seems to work. 1618 */ 1619 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1620 ifp->if_capenable &= ~IFCAP_TXCSUM; 1621 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1622 } 1623 1624 /* Tell the upper layer(s) we support long frames. */ 1625 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1626 1627 /* Create local taskq. */ 1628 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1629 taskqueue_thread_enqueue, &sc->alc_tq); 1630 if (sc->alc_tq == NULL) { 1631 device_printf(dev, "could not create taskqueue.\n"); 1632 ether_ifdetach(ifp); 1633 error = ENXIO; 1634 goto fail; 1635 } 1636 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1637 device_get_nameunit(sc->alc_dev)); 1638 1639 alc_config_msi(sc); 1640 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1641 msic = ALC_MSIX_MESSAGES; 1642 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1643 msic = ALC_MSI_MESSAGES; 1644 else 1645 msic = 1; 1646 for (i = 0; i < msic; i++) { 1647 error = bus_setup_intr(dev, sc->alc_irq[i], 1648 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1649 &sc->alc_intrhand[i]); 1650 if (error != 0) 1651 break; 1652 } 1653 if (error != 0) { 1654 device_printf(dev, "could not set up interrupt handler.\n"); 1655 taskqueue_free(sc->alc_tq); 1656 sc->alc_tq = NULL; 1657 ether_ifdetach(ifp); 1658 goto fail; 1659 } 1660 1661 /* Attach driver debugnet methods. */ 1662 DEBUGNET_SET(ifp, alc); 1663 1664 fail: 1665 if (error != 0) 1666 alc_detach(dev); 1667 1668 return (error); 1669 } 1670 1671 static int 1672 alc_detach(device_t dev) 1673 { 1674 struct alc_softc *sc; 1675 struct ifnet *ifp; 1676 int i, msic; 1677 1678 sc = device_get_softc(dev); 1679 1680 ifp = sc->alc_ifp; 1681 if (device_is_attached(dev)) { 1682 ether_ifdetach(ifp); 1683 ALC_LOCK(sc); 1684 alc_stop(sc); 1685 ALC_UNLOCK(sc); 1686 callout_drain(&sc->alc_tick_ch); 1687 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1688 } 1689 1690 if (sc->alc_tq != NULL) { 1691 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1692 taskqueue_free(sc->alc_tq); 1693 sc->alc_tq = NULL; 1694 } 1695 1696 if (sc->alc_miibus != NULL) { 1697 device_delete_child(dev, sc->alc_miibus); 1698 sc->alc_miibus = NULL; 1699 } 1700 bus_generic_detach(dev); 1701 alc_dma_free(sc); 1702 1703 if (ifp != NULL) { 1704 if_free(ifp); 1705 sc->alc_ifp = NULL; 1706 } 1707 1708 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1709 msic = ALC_MSIX_MESSAGES; 1710 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1711 msic = ALC_MSI_MESSAGES; 1712 else 1713 msic = 1; 1714 for (i = 0; i < msic; i++) { 1715 if (sc->alc_intrhand[i] != NULL) { 1716 bus_teardown_intr(dev, sc->alc_irq[i], 1717 sc->alc_intrhand[i]); 1718 sc->alc_intrhand[i] = NULL; 1719 } 1720 } 1721 if (sc->alc_res[0] != NULL) 1722 alc_phy_down(sc); 1723 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1724 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1725 pci_release_msi(dev); 1726 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1727 mtx_destroy(&sc->alc_mtx); 1728 1729 return (0); 1730 } 1731 1732 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1733 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1734 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1735 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1736 1737 static void 1738 alc_sysctl_node(struct alc_softc *sc) 1739 { 1740 struct sysctl_ctx_list *ctx; 1741 struct sysctl_oid_list *child, *parent; 1742 struct sysctl_oid *tree; 1743 struct alc_hw_stats *stats; 1744 int error; 1745 1746 stats = &sc->alc_stats; 1747 ctx = device_get_sysctl_ctx(sc->alc_dev); 1748 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1749 1750 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1751 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1752 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1753 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1754 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1755 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1756 /* Pull in device tunables. */ 1757 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1758 error = resource_int_value(device_get_name(sc->alc_dev), 1759 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1760 if (error == 0) { 1761 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1762 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1763 device_printf(sc->alc_dev, "int_rx_mod value out of " 1764 "range; using default: %d\n", 1765 ALC_IM_RX_TIMER_DEFAULT); 1766 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1767 } 1768 } 1769 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1770 error = resource_int_value(device_get_name(sc->alc_dev), 1771 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1772 if (error == 0) { 1773 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1774 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1775 device_printf(sc->alc_dev, "int_tx_mod value out of " 1776 "range; using default: %d\n", 1777 ALC_IM_TX_TIMER_DEFAULT); 1778 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1779 } 1780 } 1781 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1782 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1783 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1784 "max number of Rx events to process"); 1785 /* Pull in device tunables. */ 1786 sc->alc_process_limit = ALC_PROC_DEFAULT; 1787 error = resource_int_value(device_get_name(sc->alc_dev), 1788 device_get_unit(sc->alc_dev), "process_limit", 1789 &sc->alc_process_limit); 1790 if (error == 0) { 1791 if (sc->alc_process_limit < ALC_PROC_MIN || 1792 sc->alc_process_limit > ALC_PROC_MAX) { 1793 device_printf(sc->alc_dev, 1794 "process_limit value out of range; " 1795 "using default: %d\n", ALC_PROC_DEFAULT); 1796 sc->alc_process_limit = ALC_PROC_DEFAULT; 1797 } 1798 } 1799 1800 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1801 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1802 parent = SYSCTL_CHILDREN(tree); 1803 1804 /* Rx statistics. */ 1805 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1806 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1807 child = SYSCTL_CHILDREN(tree); 1808 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1809 &stats->rx_frames, "Good frames"); 1810 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1811 &stats->rx_bcast_frames, "Good broadcast frames"); 1812 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1813 &stats->rx_mcast_frames, "Good multicast frames"); 1814 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1815 &stats->rx_pause_frames, "Pause control frames"); 1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1817 &stats->rx_control_frames, "Control frames"); 1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1819 &stats->rx_crcerrs, "CRC errors"); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1821 &stats->rx_lenerrs, "Frames with length mismatched"); 1822 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1823 &stats->rx_bytes, "Good octets"); 1824 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1825 &stats->rx_bcast_bytes, "Good broadcast octets"); 1826 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1827 &stats->rx_mcast_bytes, "Good multicast octets"); 1828 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1829 &stats->rx_runts, "Too short frames"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1831 &stats->rx_fragments, "Fragmented frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1833 &stats->rx_pkts_64, "64 bytes frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1835 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1837 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1839 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1841 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1843 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1845 &stats->rx_pkts_1519_max, "1519 to max frames"); 1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1847 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1849 &stats->rx_fifo_oflows, "FIFO overflows"); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1851 &stats->rx_rrs_errs, "Return status write-back errors"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1853 &stats->rx_alignerrs, "Alignment errors"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1855 &stats->rx_pkts_filtered, 1856 "Frames dropped due to address filtering"); 1857 1858 /* Tx statistics. */ 1859 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1860 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1861 child = SYSCTL_CHILDREN(tree); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1863 &stats->tx_frames, "Good frames"); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1865 &stats->tx_bcast_frames, "Good broadcast frames"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1867 &stats->tx_mcast_frames, "Good multicast frames"); 1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1869 &stats->tx_pause_frames, "Pause control frames"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1871 &stats->tx_control_frames, "Control frames"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1873 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1875 &stats->tx_excess_defer, "Frames with derferrals"); 1876 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1877 &stats->tx_bytes, "Good octets"); 1878 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1879 &stats->tx_bcast_bytes, "Good broadcast octets"); 1880 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1881 &stats->tx_mcast_bytes, "Good multicast octets"); 1882 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1883 &stats->tx_pkts_64, "64 bytes frames"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1885 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1887 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1889 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1891 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1893 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1895 &stats->tx_pkts_1519_max, "1519 to max frames"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1897 &stats->tx_single_colls, "Single collisions"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1899 &stats->tx_multi_colls, "Multiple collisions"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1901 &stats->tx_late_colls, "Late collisions"); 1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1903 &stats->tx_excess_colls, "Excessive collisions"); 1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1905 &stats->tx_underrun, "FIFO underruns"); 1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1907 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1908 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1909 &stats->tx_lenerrs, "Frames with length mismatched"); 1910 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1911 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1912 } 1913 1914 #undef ALC_SYSCTL_STAT_ADD32 1915 #undef ALC_SYSCTL_STAT_ADD64 1916 1917 struct alc_dmamap_arg { 1918 bus_addr_t alc_busaddr; 1919 }; 1920 1921 static void 1922 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1923 { 1924 struct alc_dmamap_arg *ctx; 1925 1926 if (error != 0) 1927 return; 1928 1929 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1930 1931 ctx = (struct alc_dmamap_arg *)arg; 1932 ctx->alc_busaddr = segs[0].ds_addr; 1933 } 1934 1935 /* 1936 * Normal and high Tx descriptors shares single Tx high address. 1937 * Four Rx descriptor/return rings and CMB shares the same Rx 1938 * high address. 1939 */ 1940 static int 1941 alc_check_boundary(struct alc_softc *sc) 1942 { 1943 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1944 1945 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1946 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1947 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1948 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1949 1950 /* 4GB boundary crossing is not allowed. */ 1951 if ((ALC_ADDR_HI(rx_ring_end) != 1952 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1953 (ALC_ADDR_HI(rr_ring_end) != 1954 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1955 (ALC_ADDR_HI(cmb_end) != 1956 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1957 (ALC_ADDR_HI(tx_ring_end) != 1958 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1959 return (EFBIG); 1960 /* 1961 * Make sure Rx return descriptor/Rx descriptor/CMB use 1962 * the same high address. 1963 */ 1964 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1965 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1966 return (EFBIG); 1967 1968 return (0); 1969 } 1970 1971 static int 1972 alc_dma_alloc(struct alc_softc *sc) 1973 { 1974 struct alc_txdesc *txd; 1975 struct alc_rxdesc *rxd; 1976 bus_addr_t lowaddr; 1977 struct alc_dmamap_arg ctx; 1978 int error, i; 1979 1980 lowaddr = BUS_SPACE_MAXADDR; 1981 if (sc->alc_flags & ALC_FLAG_MT) 1982 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1983 again: 1984 /* Create parent DMA tag. */ 1985 error = bus_dma_tag_create( 1986 bus_get_dma_tag(sc->alc_dev), /* parent */ 1987 1, 0, /* alignment, boundary */ 1988 lowaddr, /* lowaddr */ 1989 BUS_SPACE_MAXADDR, /* highaddr */ 1990 NULL, NULL, /* filter, filterarg */ 1991 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1992 0, /* nsegments */ 1993 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1994 0, /* flags */ 1995 NULL, NULL, /* lockfunc, lockarg */ 1996 &sc->alc_cdata.alc_parent_tag); 1997 if (error != 0) { 1998 device_printf(sc->alc_dev, 1999 "could not create parent DMA tag.\n"); 2000 goto fail; 2001 } 2002 2003 /* Create DMA tag for Tx descriptor ring. */ 2004 error = bus_dma_tag_create( 2005 sc->alc_cdata.alc_parent_tag, /* parent */ 2006 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2007 BUS_SPACE_MAXADDR, /* lowaddr */ 2008 BUS_SPACE_MAXADDR, /* highaddr */ 2009 NULL, NULL, /* filter, filterarg */ 2010 ALC_TX_RING_SZ, /* maxsize */ 2011 1, /* nsegments */ 2012 ALC_TX_RING_SZ, /* maxsegsize */ 2013 0, /* flags */ 2014 NULL, NULL, /* lockfunc, lockarg */ 2015 &sc->alc_cdata.alc_tx_ring_tag); 2016 if (error != 0) { 2017 device_printf(sc->alc_dev, 2018 "could not create Tx ring DMA tag.\n"); 2019 goto fail; 2020 } 2021 2022 /* Create DMA tag for Rx free descriptor ring. */ 2023 error = bus_dma_tag_create( 2024 sc->alc_cdata.alc_parent_tag, /* parent */ 2025 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2026 BUS_SPACE_MAXADDR, /* lowaddr */ 2027 BUS_SPACE_MAXADDR, /* highaddr */ 2028 NULL, NULL, /* filter, filterarg */ 2029 ALC_RX_RING_SZ, /* maxsize */ 2030 1, /* nsegments */ 2031 ALC_RX_RING_SZ, /* maxsegsize */ 2032 0, /* flags */ 2033 NULL, NULL, /* lockfunc, lockarg */ 2034 &sc->alc_cdata.alc_rx_ring_tag); 2035 if (error != 0) { 2036 device_printf(sc->alc_dev, 2037 "could not create Rx ring DMA tag.\n"); 2038 goto fail; 2039 } 2040 /* Create DMA tag for Rx return descriptor ring. */ 2041 error = bus_dma_tag_create( 2042 sc->alc_cdata.alc_parent_tag, /* parent */ 2043 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2044 BUS_SPACE_MAXADDR, /* lowaddr */ 2045 BUS_SPACE_MAXADDR, /* highaddr */ 2046 NULL, NULL, /* filter, filterarg */ 2047 ALC_RR_RING_SZ, /* maxsize */ 2048 1, /* nsegments */ 2049 ALC_RR_RING_SZ, /* maxsegsize */ 2050 0, /* flags */ 2051 NULL, NULL, /* lockfunc, lockarg */ 2052 &sc->alc_cdata.alc_rr_ring_tag); 2053 if (error != 0) { 2054 device_printf(sc->alc_dev, 2055 "could not create Rx return ring DMA tag.\n"); 2056 goto fail; 2057 } 2058 2059 /* Create DMA tag for coalescing message block. */ 2060 error = bus_dma_tag_create( 2061 sc->alc_cdata.alc_parent_tag, /* parent */ 2062 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2063 BUS_SPACE_MAXADDR, /* lowaddr */ 2064 BUS_SPACE_MAXADDR, /* highaddr */ 2065 NULL, NULL, /* filter, filterarg */ 2066 ALC_CMB_SZ, /* maxsize */ 2067 1, /* nsegments */ 2068 ALC_CMB_SZ, /* maxsegsize */ 2069 0, /* flags */ 2070 NULL, NULL, /* lockfunc, lockarg */ 2071 &sc->alc_cdata.alc_cmb_tag); 2072 if (error != 0) { 2073 device_printf(sc->alc_dev, 2074 "could not create CMB DMA tag.\n"); 2075 goto fail; 2076 } 2077 /* Create DMA tag for status message block. */ 2078 error = bus_dma_tag_create( 2079 sc->alc_cdata.alc_parent_tag, /* parent */ 2080 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2081 BUS_SPACE_MAXADDR, /* lowaddr */ 2082 BUS_SPACE_MAXADDR, /* highaddr */ 2083 NULL, NULL, /* filter, filterarg */ 2084 ALC_SMB_SZ, /* maxsize */ 2085 1, /* nsegments */ 2086 ALC_SMB_SZ, /* maxsegsize */ 2087 0, /* flags */ 2088 NULL, NULL, /* lockfunc, lockarg */ 2089 &sc->alc_cdata.alc_smb_tag); 2090 if (error != 0) { 2091 device_printf(sc->alc_dev, 2092 "could not create SMB DMA tag.\n"); 2093 goto fail; 2094 } 2095 2096 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2097 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2098 (void **)&sc->alc_rdata.alc_tx_ring, 2099 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2100 &sc->alc_cdata.alc_tx_ring_map); 2101 if (error != 0) { 2102 device_printf(sc->alc_dev, 2103 "could not allocate DMA'able memory for Tx ring.\n"); 2104 goto fail; 2105 } 2106 ctx.alc_busaddr = 0; 2107 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2108 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2109 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2110 if (error != 0 || ctx.alc_busaddr == 0) { 2111 device_printf(sc->alc_dev, 2112 "could not load DMA'able memory for Tx ring.\n"); 2113 goto fail; 2114 } 2115 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2116 2117 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2118 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2119 (void **)&sc->alc_rdata.alc_rx_ring, 2120 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2121 &sc->alc_cdata.alc_rx_ring_map); 2122 if (error != 0) { 2123 device_printf(sc->alc_dev, 2124 "could not allocate DMA'able memory for Rx ring.\n"); 2125 goto fail; 2126 } 2127 ctx.alc_busaddr = 0; 2128 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2129 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2130 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2131 if (error != 0 || ctx.alc_busaddr == 0) { 2132 device_printf(sc->alc_dev, 2133 "could not load DMA'able memory for Rx ring.\n"); 2134 goto fail; 2135 } 2136 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2137 2138 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2139 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2140 (void **)&sc->alc_rdata.alc_rr_ring, 2141 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2142 &sc->alc_cdata.alc_rr_ring_map); 2143 if (error != 0) { 2144 device_printf(sc->alc_dev, 2145 "could not allocate DMA'able memory for Rx return ring.\n"); 2146 goto fail; 2147 } 2148 ctx.alc_busaddr = 0; 2149 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2150 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2151 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2152 if (error != 0 || ctx.alc_busaddr == 0) { 2153 device_printf(sc->alc_dev, 2154 "could not load DMA'able memory for Tx ring.\n"); 2155 goto fail; 2156 } 2157 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2158 2159 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2160 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2161 (void **)&sc->alc_rdata.alc_cmb, 2162 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2163 &sc->alc_cdata.alc_cmb_map); 2164 if (error != 0) { 2165 device_printf(sc->alc_dev, 2166 "could not allocate DMA'able memory for CMB.\n"); 2167 goto fail; 2168 } 2169 ctx.alc_busaddr = 0; 2170 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2171 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2172 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2173 if (error != 0 || ctx.alc_busaddr == 0) { 2174 device_printf(sc->alc_dev, 2175 "could not load DMA'able memory for CMB.\n"); 2176 goto fail; 2177 } 2178 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2179 2180 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2181 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2182 (void **)&sc->alc_rdata.alc_smb, 2183 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2184 &sc->alc_cdata.alc_smb_map); 2185 if (error != 0) { 2186 device_printf(sc->alc_dev, 2187 "could not allocate DMA'able memory for SMB.\n"); 2188 goto fail; 2189 } 2190 ctx.alc_busaddr = 0; 2191 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2192 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2193 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2194 if (error != 0 || ctx.alc_busaddr == 0) { 2195 device_printf(sc->alc_dev, 2196 "could not load DMA'able memory for CMB.\n"); 2197 goto fail; 2198 } 2199 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2200 2201 /* Make sure we've not crossed 4GB boundary. */ 2202 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2203 (error = alc_check_boundary(sc)) != 0) { 2204 device_printf(sc->alc_dev, "4GB boundary crossed, " 2205 "switching to 32bit DMA addressing mode.\n"); 2206 alc_dma_free(sc); 2207 /* 2208 * Limit max allowable DMA address space to 32bit 2209 * and try again. 2210 */ 2211 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2212 goto again; 2213 } 2214 2215 /* 2216 * Create Tx buffer parent tag. 2217 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2218 * so it needs separate parent DMA tag as parent DMA address 2219 * space could be restricted to be within 32bit address space 2220 * by 4GB boundary crossing. 2221 */ 2222 error = bus_dma_tag_create( 2223 bus_get_dma_tag(sc->alc_dev), /* parent */ 2224 1, 0, /* alignment, boundary */ 2225 lowaddr, /* lowaddr */ 2226 BUS_SPACE_MAXADDR, /* highaddr */ 2227 NULL, NULL, /* filter, filterarg */ 2228 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2229 0, /* nsegments */ 2230 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2231 0, /* flags */ 2232 NULL, NULL, /* lockfunc, lockarg */ 2233 &sc->alc_cdata.alc_buffer_tag); 2234 if (error != 0) { 2235 device_printf(sc->alc_dev, 2236 "could not create parent buffer DMA tag.\n"); 2237 goto fail; 2238 } 2239 2240 /* Create DMA tag for Tx buffers. */ 2241 error = bus_dma_tag_create( 2242 sc->alc_cdata.alc_buffer_tag, /* parent */ 2243 1, 0, /* alignment, boundary */ 2244 BUS_SPACE_MAXADDR, /* lowaddr */ 2245 BUS_SPACE_MAXADDR, /* highaddr */ 2246 NULL, NULL, /* filter, filterarg */ 2247 ALC_TSO_MAXSIZE, /* maxsize */ 2248 ALC_MAXTXSEGS, /* nsegments */ 2249 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2250 0, /* flags */ 2251 NULL, NULL, /* lockfunc, lockarg */ 2252 &sc->alc_cdata.alc_tx_tag); 2253 if (error != 0) { 2254 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2255 goto fail; 2256 } 2257 2258 /* Create DMA tag for Rx buffers. */ 2259 error = bus_dma_tag_create( 2260 sc->alc_cdata.alc_buffer_tag, /* parent */ 2261 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2262 BUS_SPACE_MAXADDR, /* lowaddr */ 2263 BUS_SPACE_MAXADDR, /* highaddr */ 2264 NULL, NULL, /* filter, filterarg */ 2265 MCLBYTES, /* maxsize */ 2266 1, /* nsegments */ 2267 MCLBYTES, /* maxsegsize */ 2268 0, /* flags */ 2269 NULL, NULL, /* lockfunc, lockarg */ 2270 &sc->alc_cdata.alc_rx_tag); 2271 if (error != 0) { 2272 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2273 goto fail; 2274 } 2275 /* Create DMA maps for Tx buffers. */ 2276 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2277 txd = &sc->alc_cdata.alc_txdesc[i]; 2278 txd->tx_m = NULL; 2279 txd->tx_dmamap = NULL; 2280 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2281 &txd->tx_dmamap); 2282 if (error != 0) { 2283 device_printf(sc->alc_dev, 2284 "could not create Tx dmamap.\n"); 2285 goto fail; 2286 } 2287 } 2288 /* Create DMA maps for Rx buffers. */ 2289 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2290 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2291 device_printf(sc->alc_dev, 2292 "could not create spare Rx dmamap.\n"); 2293 goto fail; 2294 } 2295 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2296 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2297 rxd->rx_m = NULL; 2298 rxd->rx_dmamap = NULL; 2299 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2300 &rxd->rx_dmamap); 2301 if (error != 0) { 2302 device_printf(sc->alc_dev, 2303 "could not create Rx dmamap.\n"); 2304 goto fail; 2305 } 2306 } 2307 2308 fail: 2309 return (error); 2310 } 2311 2312 static void 2313 alc_dma_free(struct alc_softc *sc) 2314 { 2315 struct alc_txdesc *txd; 2316 struct alc_rxdesc *rxd; 2317 int i; 2318 2319 /* Tx buffers. */ 2320 if (sc->alc_cdata.alc_tx_tag != NULL) { 2321 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2322 txd = &sc->alc_cdata.alc_txdesc[i]; 2323 if (txd->tx_dmamap != NULL) { 2324 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2325 txd->tx_dmamap); 2326 txd->tx_dmamap = NULL; 2327 } 2328 } 2329 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2330 sc->alc_cdata.alc_tx_tag = NULL; 2331 } 2332 /* Rx buffers */ 2333 if (sc->alc_cdata.alc_rx_tag != NULL) { 2334 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2335 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2336 if (rxd->rx_dmamap != NULL) { 2337 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2338 rxd->rx_dmamap); 2339 rxd->rx_dmamap = NULL; 2340 } 2341 } 2342 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2343 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2344 sc->alc_cdata.alc_rx_sparemap); 2345 sc->alc_cdata.alc_rx_sparemap = NULL; 2346 } 2347 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2348 sc->alc_cdata.alc_rx_tag = NULL; 2349 } 2350 /* Tx descriptor ring. */ 2351 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2352 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2353 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2354 sc->alc_cdata.alc_tx_ring_map); 2355 if (sc->alc_rdata.alc_tx_ring != NULL) 2356 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2357 sc->alc_rdata.alc_tx_ring, 2358 sc->alc_cdata.alc_tx_ring_map); 2359 sc->alc_rdata.alc_tx_ring_paddr = 0; 2360 sc->alc_rdata.alc_tx_ring = NULL; 2361 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2362 sc->alc_cdata.alc_tx_ring_tag = NULL; 2363 } 2364 /* Rx ring. */ 2365 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2366 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2367 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2368 sc->alc_cdata.alc_rx_ring_map); 2369 if (sc->alc_rdata.alc_rx_ring != NULL) 2370 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2371 sc->alc_rdata.alc_rx_ring, 2372 sc->alc_cdata.alc_rx_ring_map); 2373 sc->alc_rdata.alc_rx_ring_paddr = 0; 2374 sc->alc_rdata.alc_rx_ring = NULL; 2375 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2376 sc->alc_cdata.alc_rx_ring_tag = NULL; 2377 } 2378 /* Rx return ring. */ 2379 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2380 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2381 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2382 sc->alc_cdata.alc_rr_ring_map); 2383 if (sc->alc_rdata.alc_rr_ring != NULL) 2384 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2385 sc->alc_rdata.alc_rr_ring, 2386 sc->alc_cdata.alc_rr_ring_map); 2387 sc->alc_rdata.alc_rr_ring_paddr = 0; 2388 sc->alc_rdata.alc_rr_ring = NULL; 2389 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2390 sc->alc_cdata.alc_rr_ring_tag = NULL; 2391 } 2392 /* CMB block */ 2393 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2394 if (sc->alc_rdata.alc_cmb_paddr != 0) 2395 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2396 sc->alc_cdata.alc_cmb_map); 2397 if (sc->alc_rdata.alc_cmb != NULL) 2398 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2399 sc->alc_rdata.alc_cmb, 2400 sc->alc_cdata.alc_cmb_map); 2401 sc->alc_rdata.alc_cmb_paddr = 0; 2402 sc->alc_rdata.alc_cmb = NULL; 2403 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2404 sc->alc_cdata.alc_cmb_tag = NULL; 2405 } 2406 /* SMB block */ 2407 if (sc->alc_cdata.alc_smb_tag != NULL) { 2408 if (sc->alc_rdata.alc_smb_paddr != 0) 2409 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2410 sc->alc_cdata.alc_smb_map); 2411 if (sc->alc_rdata.alc_smb != NULL) 2412 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2413 sc->alc_rdata.alc_smb, 2414 sc->alc_cdata.alc_smb_map); 2415 sc->alc_rdata.alc_smb_paddr = 0; 2416 sc->alc_rdata.alc_smb = NULL; 2417 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2418 sc->alc_cdata.alc_smb_tag = NULL; 2419 } 2420 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2421 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2422 sc->alc_cdata.alc_buffer_tag = NULL; 2423 } 2424 if (sc->alc_cdata.alc_parent_tag != NULL) { 2425 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2426 sc->alc_cdata.alc_parent_tag = NULL; 2427 } 2428 } 2429 2430 static int 2431 alc_shutdown(device_t dev) 2432 { 2433 2434 return (alc_suspend(dev)); 2435 } 2436 2437 /* 2438 * Note, this driver resets the link speed to 10/100Mbps by 2439 * restarting auto-negotiation in suspend/shutdown phase but we 2440 * don't know whether that auto-negotiation would succeed or not 2441 * as driver has no control after powering off/suspend operation. 2442 * If the renegotiation fail WOL may not work. Running at 1Gbps 2443 * will draw more power than 375mA at 3.3V which is specified in 2444 * PCI specification and that would result in complete 2445 * shutdowning power to ethernet controller. 2446 * 2447 * TODO 2448 * Save current negotiated media speed/duplex/flow-control to 2449 * softc and restore the same link again after resuming. PHY 2450 * handling such as power down/resetting to 100Mbps may be better 2451 * handled in suspend method in phy driver. 2452 */ 2453 static void 2454 alc_setlinkspeed(struct alc_softc *sc) 2455 { 2456 struct mii_data *mii; 2457 int aneg, i; 2458 2459 mii = device_get_softc(sc->alc_miibus); 2460 mii_pollstat(mii); 2461 aneg = 0; 2462 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2463 (IFM_ACTIVE | IFM_AVALID)) { 2464 switch IFM_SUBTYPE(mii->mii_media_active) { 2465 case IFM_10_T: 2466 case IFM_100_TX: 2467 return; 2468 case IFM_1000_T: 2469 aneg++; 2470 break; 2471 default: 2472 break; 2473 } 2474 } 2475 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2476 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2477 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2478 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2479 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2480 DELAY(1000); 2481 if (aneg != 0) { 2482 /* 2483 * Poll link state until alc(4) get a 10/100Mbps link. 2484 */ 2485 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2486 mii_pollstat(mii); 2487 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2488 == (IFM_ACTIVE | IFM_AVALID)) { 2489 switch (IFM_SUBTYPE( 2490 mii->mii_media_active)) { 2491 case IFM_10_T: 2492 case IFM_100_TX: 2493 alc_mac_config(sc); 2494 return; 2495 default: 2496 break; 2497 } 2498 } 2499 ALC_UNLOCK(sc); 2500 pause("alclnk", hz); 2501 ALC_LOCK(sc); 2502 } 2503 if (i == MII_ANEGTICKS_GIGE) 2504 device_printf(sc->alc_dev, 2505 "establishing a link failed, WOL may not work!"); 2506 } 2507 /* 2508 * No link, force MAC to have 100Mbps, full-duplex link. 2509 * This is the last resort and may/may not work. 2510 */ 2511 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2512 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2513 alc_mac_config(sc); 2514 } 2515 2516 static void 2517 alc_setwol(struct alc_softc *sc) 2518 { 2519 2520 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2521 alc_setwol_816x(sc); 2522 else 2523 alc_setwol_813x(sc); 2524 } 2525 2526 static void 2527 alc_setwol_813x(struct alc_softc *sc) 2528 { 2529 struct ifnet *ifp; 2530 uint32_t reg, pmcs; 2531 uint16_t pmstat; 2532 2533 ALC_LOCK_ASSERT(sc); 2534 2535 alc_disable_l0s_l1(sc); 2536 ifp = sc->alc_ifp; 2537 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2538 /* Disable WOL. */ 2539 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2540 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2541 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2542 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2543 /* Force PHY power down. */ 2544 alc_phy_down(sc); 2545 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2546 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2547 return; 2548 } 2549 2550 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2551 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2552 alc_setlinkspeed(sc); 2553 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2554 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2555 } 2556 2557 pmcs = 0; 2558 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2559 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2560 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2561 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2562 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2563 MAC_CFG_BCAST); 2564 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2565 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2566 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2567 reg |= MAC_CFG_RX_ENB; 2568 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2569 2570 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2571 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2572 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2573 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2574 /* WOL disabled, PHY power down. */ 2575 alc_phy_down(sc); 2576 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2577 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2578 } 2579 /* Request PME. */ 2580 pmstat = pci_read_config(sc->alc_dev, 2581 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2582 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2583 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2584 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2585 pci_write_config(sc->alc_dev, 2586 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2587 } 2588 2589 static void 2590 alc_setwol_816x(struct alc_softc *sc) 2591 { 2592 struct ifnet *ifp; 2593 uint32_t gphy, mac, master, pmcs, reg; 2594 uint16_t pmstat; 2595 2596 ALC_LOCK_ASSERT(sc); 2597 2598 ifp = sc->alc_ifp; 2599 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2600 master &= ~MASTER_CLK_SEL_DIS; 2601 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2602 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2603 GPHY_CFG_PHY_PLL_ON); 2604 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2605 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2606 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2607 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2608 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2609 } else { 2610 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2611 gphy |= GPHY_CFG_EXT_RESET; 2612 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2613 alc_setlinkspeed(sc); 2614 } 2615 pmcs = 0; 2616 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2617 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2618 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2619 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2620 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2621 MAC_CFG_BCAST); 2622 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2623 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2624 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2625 mac |= MAC_CFG_RX_ENB; 2626 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2627 ANEG_S3DIG10_SL); 2628 } 2629 2630 /* Enable OSC. */ 2631 reg = CSR_READ_4(sc, ALC_MISC); 2632 reg &= ~MISC_INTNLOSC_OPEN; 2633 CSR_WRITE_4(sc, ALC_MISC, reg); 2634 reg |= MISC_INTNLOSC_OPEN; 2635 CSR_WRITE_4(sc, ALC_MISC, reg); 2636 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2637 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2638 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2639 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2640 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2641 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2642 2643 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2644 /* Request PME. */ 2645 pmstat = pci_read_config(sc->alc_dev, 2646 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2647 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2648 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2649 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2650 pci_write_config(sc->alc_dev, 2651 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2652 } 2653 } 2654 2655 static int 2656 alc_suspend(device_t dev) 2657 { 2658 struct alc_softc *sc; 2659 2660 sc = device_get_softc(dev); 2661 2662 ALC_LOCK(sc); 2663 alc_stop(sc); 2664 alc_setwol(sc); 2665 ALC_UNLOCK(sc); 2666 2667 return (0); 2668 } 2669 2670 static int 2671 alc_resume(device_t dev) 2672 { 2673 struct alc_softc *sc; 2674 struct ifnet *ifp; 2675 uint16_t pmstat; 2676 2677 sc = device_get_softc(dev); 2678 2679 ALC_LOCK(sc); 2680 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2681 /* Disable PME and clear PME status. */ 2682 pmstat = pci_read_config(sc->alc_dev, 2683 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2684 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2685 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2686 pci_write_config(sc->alc_dev, 2687 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2688 } 2689 } 2690 /* Reset PHY. */ 2691 alc_phy_reset(sc); 2692 ifp = sc->alc_ifp; 2693 if ((ifp->if_flags & IFF_UP) != 0) { 2694 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2695 alc_init_locked(sc); 2696 } 2697 ALC_UNLOCK(sc); 2698 2699 return (0); 2700 } 2701 2702 static int 2703 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2704 { 2705 struct alc_txdesc *txd, *txd_last; 2706 struct tx_desc *desc; 2707 struct mbuf *m; 2708 struct ip *ip; 2709 struct tcphdr *tcp; 2710 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2711 bus_dmamap_t map; 2712 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2713 int error, idx, nsegs, prod; 2714 2715 ALC_LOCK_ASSERT(sc); 2716 2717 M_ASSERTPKTHDR((*m_head)); 2718 2719 m = *m_head; 2720 ip = NULL; 2721 tcp = NULL; 2722 ip_off = poff = 0; 2723 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2724 /* 2725 * AR81[3567]x requires offset of TCP/UDP header in its 2726 * Tx descriptor to perform Tx checksum offloading. TSO 2727 * also requires TCP header offset and modification of 2728 * IP/TCP header. This kind of operation takes many CPU 2729 * cycles on FreeBSD so fast host CPU is required to get 2730 * smooth TSO performance. 2731 */ 2732 struct ether_header *eh; 2733 2734 if (M_WRITABLE(m) == 0) { 2735 /* Get a writable copy. */ 2736 m = m_dup(*m_head, M_NOWAIT); 2737 /* Release original mbufs. */ 2738 m_freem(*m_head); 2739 if (m == NULL) { 2740 *m_head = NULL; 2741 return (ENOBUFS); 2742 } 2743 *m_head = m; 2744 } 2745 2746 ip_off = sizeof(struct ether_header); 2747 m = m_pullup(m, ip_off); 2748 if (m == NULL) { 2749 *m_head = NULL; 2750 return (ENOBUFS); 2751 } 2752 eh = mtod(m, struct ether_header *); 2753 /* 2754 * Check if hardware VLAN insertion is off. 2755 * Additional check for LLC/SNAP frame? 2756 */ 2757 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2758 ip_off = sizeof(struct ether_vlan_header); 2759 m = m_pullup(m, ip_off); 2760 if (m == NULL) { 2761 *m_head = NULL; 2762 return (ENOBUFS); 2763 } 2764 } 2765 m = m_pullup(m, ip_off + sizeof(struct ip)); 2766 if (m == NULL) { 2767 *m_head = NULL; 2768 return (ENOBUFS); 2769 } 2770 ip = (struct ip *)(mtod(m, char *) + ip_off); 2771 poff = ip_off + (ip->ip_hl << 2); 2772 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2773 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2774 if (m == NULL) { 2775 *m_head = NULL; 2776 return (ENOBUFS); 2777 } 2778 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2779 m = m_pullup(m, poff + (tcp->th_off << 2)); 2780 if (m == NULL) { 2781 *m_head = NULL; 2782 return (ENOBUFS); 2783 } 2784 /* 2785 * Due to strict adherence of Microsoft NDIS 2786 * Large Send specification, hardware expects 2787 * a pseudo TCP checksum inserted by upper 2788 * stack. Unfortunately the pseudo TCP 2789 * checksum that NDIS refers to does not include 2790 * TCP payload length so driver should recompute 2791 * the pseudo checksum here. Hopefully this 2792 * wouldn't be much burden on modern CPUs. 2793 * 2794 * Reset IP checksum and recompute TCP pseudo 2795 * checksum as NDIS specification said. 2796 */ 2797 ip = (struct ip *)(mtod(m, char *) + ip_off); 2798 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2799 ip->ip_sum = 0; 2800 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2801 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2802 } 2803 *m_head = m; 2804 } 2805 2806 prod = sc->alc_cdata.alc_tx_prod; 2807 txd = &sc->alc_cdata.alc_txdesc[prod]; 2808 txd_last = txd; 2809 map = txd->tx_dmamap; 2810 2811 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2812 *m_head, txsegs, &nsegs, 0); 2813 if (error == EFBIG) { 2814 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2815 if (m == NULL) { 2816 m_freem(*m_head); 2817 *m_head = NULL; 2818 return (ENOMEM); 2819 } 2820 *m_head = m; 2821 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2822 *m_head, txsegs, &nsegs, 0); 2823 if (error != 0) { 2824 m_freem(*m_head); 2825 *m_head = NULL; 2826 return (error); 2827 } 2828 } else if (error != 0) 2829 return (error); 2830 if (nsegs == 0) { 2831 m_freem(*m_head); 2832 *m_head = NULL; 2833 return (EIO); 2834 } 2835 2836 /* Check descriptor overrun. */ 2837 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2838 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2839 return (ENOBUFS); 2840 } 2841 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2842 2843 m = *m_head; 2844 cflags = TD_ETHERNET; 2845 vtag = 0; 2846 desc = NULL; 2847 idx = 0; 2848 /* Configure VLAN hardware tag insertion. */ 2849 if ((m->m_flags & M_VLANTAG) != 0) { 2850 vtag = htons(m->m_pkthdr.ether_vtag); 2851 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2852 cflags |= TD_INS_VLAN_TAG; 2853 } 2854 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2855 /* Request TSO and set MSS. */ 2856 cflags |= TD_TSO | TD_TSO_DESCV1; 2857 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2858 TD_MSS_MASK; 2859 /* Set TCP header offset. */ 2860 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2861 TD_TCPHDR_OFFSET_MASK; 2862 /* 2863 * AR81[3567]x requires the first buffer should 2864 * only hold IP/TCP header data. Payload should 2865 * be handled in other descriptors. 2866 */ 2867 hdrlen = poff + (tcp->th_off << 2); 2868 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2869 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2870 desc->flags = htole32(cflags); 2871 desc->addr = htole64(txsegs[0].ds_addr); 2872 sc->alc_cdata.alc_tx_cnt++; 2873 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2874 if (m->m_len - hdrlen > 0) { 2875 /* Handle remaining payload of the first fragment. */ 2876 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2877 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2878 vtag)); 2879 desc->flags = htole32(cflags); 2880 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2881 sc->alc_cdata.alc_tx_cnt++; 2882 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2883 } 2884 /* Handle remaining fragments. */ 2885 idx = 1; 2886 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2887 /* Configure Tx checksum offload. */ 2888 #ifdef ALC_USE_CUSTOM_CSUM 2889 cflags |= TD_CUSTOM_CSUM; 2890 /* Set checksum start offset. */ 2891 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2892 TD_PLOAD_OFFSET_MASK; 2893 /* Set checksum insertion position of TCP/UDP. */ 2894 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2895 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2896 #else 2897 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2898 cflags |= TD_IPCSUM; 2899 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2900 cflags |= TD_TCPCSUM; 2901 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2902 cflags |= TD_UDPCSUM; 2903 /* Set TCP/UDP header offset. */ 2904 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2905 TD_L4HDR_OFFSET_MASK; 2906 #endif 2907 } 2908 for (; idx < nsegs; idx++) { 2909 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2910 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2911 desc->flags = htole32(cflags); 2912 desc->addr = htole64(txsegs[idx].ds_addr); 2913 sc->alc_cdata.alc_tx_cnt++; 2914 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2915 } 2916 /* Update producer index. */ 2917 sc->alc_cdata.alc_tx_prod = prod; 2918 2919 /* Finally set EOP on the last descriptor. */ 2920 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2921 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2922 desc->flags |= htole32(TD_EOP); 2923 2924 /* Swap dmamap of the first and the last. */ 2925 txd = &sc->alc_cdata.alc_txdesc[prod]; 2926 map = txd_last->tx_dmamap; 2927 txd_last->tx_dmamap = txd->tx_dmamap; 2928 txd->tx_dmamap = map; 2929 txd->tx_m = m; 2930 2931 return (0); 2932 } 2933 2934 static void 2935 alc_start(struct ifnet *ifp) 2936 { 2937 struct alc_softc *sc; 2938 2939 sc = ifp->if_softc; 2940 ALC_LOCK(sc); 2941 alc_start_locked(ifp); 2942 ALC_UNLOCK(sc); 2943 } 2944 2945 static void 2946 alc_start_locked(struct ifnet *ifp) 2947 { 2948 struct alc_softc *sc; 2949 struct mbuf *m_head; 2950 int enq; 2951 2952 sc = ifp->if_softc; 2953 2954 ALC_LOCK_ASSERT(sc); 2955 2956 /* Reclaim transmitted frames. */ 2957 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2958 alc_txeof(sc); 2959 2960 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2961 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2962 return; 2963 2964 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2965 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2966 if (m_head == NULL) 2967 break; 2968 /* 2969 * Pack the data into the transmit ring. If we 2970 * don't have room, set the OACTIVE flag and wait 2971 * for the NIC to drain the ring. 2972 */ 2973 if (alc_encap(sc, &m_head)) { 2974 if (m_head == NULL) 2975 break; 2976 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2977 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2978 break; 2979 } 2980 2981 enq++; 2982 /* 2983 * If there's a BPF listener, bounce a copy of this frame 2984 * to him. 2985 */ 2986 ETHER_BPF_MTAP(ifp, m_head); 2987 } 2988 2989 if (enq > 0) 2990 alc_start_tx(sc); 2991 } 2992 2993 static void 2994 alc_start_tx(struct alc_softc *sc) 2995 { 2996 2997 /* Sync descriptors. */ 2998 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2999 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3000 /* Kick. Assume we're using normal Tx priority queue. */ 3001 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3002 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3003 (uint16_t)sc->alc_cdata.alc_tx_prod); 3004 else 3005 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3006 (sc->alc_cdata.alc_tx_prod << 3007 MBOX_TD_PROD_LO_IDX_SHIFT) & 3008 MBOX_TD_PROD_LO_IDX_MASK); 3009 /* Set a timeout in case the chip goes out to lunch. */ 3010 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3011 } 3012 3013 static void 3014 alc_watchdog(struct alc_softc *sc) 3015 { 3016 struct ifnet *ifp; 3017 3018 ALC_LOCK_ASSERT(sc); 3019 3020 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3021 return; 3022 3023 ifp = sc->alc_ifp; 3024 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3025 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3026 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3027 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3028 alc_init_locked(sc); 3029 return; 3030 } 3031 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3032 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3033 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3034 alc_init_locked(sc); 3035 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3036 alc_start_locked(ifp); 3037 } 3038 3039 static int 3040 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3041 { 3042 struct alc_softc *sc; 3043 struct ifreq *ifr; 3044 struct mii_data *mii; 3045 int error, mask; 3046 3047 sc = ifp->if_softc; 3048 ifr = (struct ifreq *)data; 3049 error = 0; 3050 switch (cmd) { 3051 case SIOCSIFMTU: 3052 if (ifr->ifr_mtu < ETHERMIN || 3053 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3054 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3055 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3056 ifr->ifr_mtu > ETHERMTU)) 3057 error = EINVAL; 3058 else if (ifp->if_mtu != ifr->ifr_mtu) { 3059 ALC_LOCK(sc); 3060 ifp->if_mtu = ifr->ifr_mtu; 3061 /* AR81[3567]x has 13 bits MSS field. */ 3062 if (ifp->if_mtu > ALC_TSO_MTU && 3063 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3064 ifp->if_capenable &= ~IFCAP_TSO4; 3065 ifp->if_hwassist &= ~CSUM_TSO; 3066 VLAN_CAPABILITIES(ifp); 3067 } 3068 ALC_UNLOCK(sc); 3069 } 3070 break; 3071 case SIOCSIFFLAGS: 3072 ALC_LOCK(sc); 3073 if ((ifp->if_flags & IFF_UP) != 0) { 3074 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3075 ((ifp->if_flags ^ sc->alc_if_flags) & 3076 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3077 alc_rxfilter(sc); 3078 else 3079 alc_init_locked(sc); 3080 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3081 alc_stop(sc); 3082 sc->alc_if_flags = ifp->if_flags; 3083 ALC_UNLOCK(sc); 3084 break; 3085 case SIOCADDMULTI: 3086 case SIOCDELMULTI: 3087 ALC_LOCK(sc); 3088 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3089 alc_rxfilter(sc); 3090 ALC_UNLOCK(sc); 3091 break; 3092 case SIOCSIFMEDIA: 3093 case SIOCGIFMEDIA: 3094 mii = device_get_softc(sc->alc_miibus); 3095 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3096 break; 3097 case SIOCSIFCAP: 3098 ALC_LOCK(sc); 3099 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3100 if ((mask & IFCAP_TXCSUM) != 0 && 3101 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3102 ifp->if_capenable ^= IFCAP_TXCSUM; 3103 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3104 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3105 else 3106 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3107 } 3108 if ((mask & IFCAP_TSO4) != 0 && 3109 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3110 ifp->if_capenable ^= IFCAP_TSO4; 3111 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3112 /* AR81[3567]x has 13 bits MSS field. */ 3113 if (ifp->if_mtu > ALC_TSO_MTU) { 3114 ifp->if_capenable &= ~IFCAP_TSO4; 3115 ifp->if_hwassist &= ~CSUM_TSO; 3116 } else 3117 ifp->if_hwassist |= CSUM_TSO; 3118 } else 3119 ifp->if_hwassist &= ~CSUM_TSO; 3120 } 3121 if ((mask & IFCAP_WOL_MCAST) != 0 && 3122 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3123 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3124 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3125 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3126 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3127 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3128 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3129 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3130 alc_rxvlan(sc); 3131 } 3132 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3133 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3134 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3135 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3136 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3137 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3138 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3139 ifp->if_capenable &= 3140 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3141 ALC_UNLOCK(sc); 3142 VLAN_CAPABILITIES(ifp); 3143 break; 3144 default: 3145 error = ether_ioctl(ifp, cmd, data); 3146 break; 3147 } 3148 3149 return (error); 3150 } 3151 3152 static void 3153 alc_mac_config(struct alc_softc *sc) 3154 { 3155 struct mii_data *mii; 3156 uint32_t reg; 3157 3158 ALC_LOCK_ASSERT(sc); 3159 3160 mii = device_get_softc(sc->alc_miibus); 3161 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3162 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3163 MAC_CFG_SPEED_MASK); 3164 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3165 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3166 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3167 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3168 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3169 /* Reprogram MAC with resolved speed/duplex. */ 3170 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3171 case IFM_10_T: 3172 case IFM_100_TX: 3173 reg |= MAC_CFG_SPEED_10_100; 3174 break; 3175 case IFM_1000_T: 3176 reg |= MAC_CFG_SPEED_1000; 3177 break; 3178 } 3179 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3180 reg |= MAC_CFG_FULL_DUPLEX; 3181 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3182 reg |= MAC_CFG_TX_FC; 3183 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3184 reg |= MAC_CFG_RX_FC; 3185 } 3186 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3187 } 3188 3189 static void 3190 alc_stats_clear(struct alc_softc *sc) 3191 { 3192 struct smb sb, *smb; 3193 uint32_t *reg; 3194 int i; 3195 3196 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3197 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3198 sc->alc_cdata.alc_smb_map, 3199 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3200 smb = sc->alc_rdata.alc_smb; 3201 /* Update done, clear. */ 3202 smb->updated = 0; 3203 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3204 sc->alc_cdata.alc_smb_map, 3205 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3206 } else { 3207 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3208 reg++) { 3209 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3210 i += sizeof(uint32_t); 3211 } 3212 /* Read Tx statistics. */ 3213 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3214 reg++) { 3215 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3216 i += sizeof(uint32_t); 3217 } 3218 } 3219 } 3220 3221 static void 3222 alc_stats_update(struct alc_softc *sc) 3223 { 3224 struct alc_hw_stats *stat; 3225 struct smb sb, *smb; 3226 struct ifnet *ifp; 3227 uint32_t *reg; 3228 int i; 3229 3230 ALC_LOCK_ASSERT(sc); 3231 3232 ifp = sc->alc_ifp; 3233 stat = &sc->alc_stats; 3234 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3235 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3236 sc->alc_cdata.alc_smb_map, 3237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3238 smb = sc->alc_rdata.alc_smb; 3239 if (smb->updated == 0) 3240 return; 3241 } else { 3242 smb = &sb; 3243 /* Read Rx statistics. */ 3244 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3245 reg++) { 3246 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3247 i += sizeof(uint32_t); 3248 } 3249 /* Read Tx statistics. */ 3250 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3251 reg++) { 3252 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3253 i += sizeof(uint32_t); 3254 } 3255 } 3256 3257 /* Rx stats. */ 3258 stat->rx_frames += smb->rx_frames; 3259 stat->rx_bcast_frames += smb->rx_bcast_frames; 3260 stat->rx_mcast_frames += smb->rx_mcast_frames; 3261 stat->rx_pause_frames += smb->rx_pause_frames; 3262 stat->rx_control_frames += smb->rx_control_frames; 3263 stat->rx_crcerrs += smb->rx_crcerrs; 3264 stat->rx_lenerrs += smb->rx_lenerrs; 3265 stat->rx_bytes += smb->rx_bytes; 3266 stat->rx_runts += smb->rx_runts; 3267 stat->rx_fragments += smb->rx_fragments; 3268 stat->rx_pkts_64 += smb->rx_pkts_64; 3269 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3270 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3271 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3272 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3273 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3274 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3275 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3276 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3277 stat->rx_rrs_errs += smb->rx_rrs_errs; 3278 stat->rx_alignerrs += smb->rx_alignerrs; 3279 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3280 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3281 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3282 3283 /* Tx stats. */ 3284 stat->tx_frames += smb->tx_frames; 3285 stat->tx_bcast_frames += smb->tx_bcast_frames; 3286 stat->tx_mcast_frames += smb->tx_mcast_frames; 3287 stat->tx_pause_frames += smb->tx_pause_frames; 3288 stat->tx_excess_defer += smb->tx_excess_defer; 3289 stat->tx_control_frames += smb->tx_control_frames; 3290 stat->tx_deferred += smb->tx_deferred; 3291 stat->tx_bytes += smb->tx_bytes; 3292 stat->tx_pkts_64 += smb->tx_pkts_64; 3293 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3294 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3295 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3296 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3297 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3298 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3299 stat->tx_single_colls += smb->tx_single_colls; 3300 stat->tx_multi_colls += smb->tx_multi_colls; 3301 stat->tx_late_colls += smb->tx_late_colls; 3302 stat->tx_excess_colls += smb->tx_excess_colls; 3303 stat->tx_underrun += smb->tx_underrun; 3304 stat->tx_desc_underrun += smb->tx_desc_underrun; 3305 stat->tx_lenerrs += smb->tx_lenerrs; 3306 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3307 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3308 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3309 3310 /* Update counters in ifnet. */ 3311 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3312 3313 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3314 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3315 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3316 3317 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3318 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3319 3320 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3321 3322 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3323 smb->rx_crcerrs + smb->rx_lenerrs + 3324 smb->rx_runts + smb->rx_pkts_truncated + 3325 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3326 smb->rx_alignerrs); 3327 3328 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3329 /* Update done, clear. */ 3330 smb->updated = 0; 3331 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3332 sc->alc_cdata.alc_smb_map, 3333 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3334 } 3335 } 3336 3337 static int 3338 alc_intr(void *arg) 3339 { 3340 struct alc_softc *sc; 3341 uint32_t status; 3342 3343 sc = (struct alc_softc *)arg; 3344 3345 if (sc->alc_flags & ALC_FLAG_MT) { 3346 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3347 return (FILTER_HANDLED); 3348 } 3349 3350 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3351 if ((status & ALC_INTRS) == 0) 3352 return (FILTER_STRAY); 3353 /* Disable interrupts. */ 3354 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3355 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3356 3357 return (FILTER_HANDLED); 3358 } 3359 3360 static void 3361 alc_int_task(void *arg, int pending) 3362 { 3363 struct alc_softc *sc; 3364 struct ifnet *ifp; 3365 uint32_t status; 3366 int more; 3367 3368 sc = (struct alc_softc *)arg; 3369 ifp = sc->alc_ifp; 3370 3371 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3372 ALC_LOCK(sc); 3373 if (sc->alc_morework != 0) { 3374 sc->alc_morework = 0; 3375 status |= INTR_RX_PKT; 3376 } 3377 if ((status & ALC_INTRS) == 0) 3378 goto done; 3379 3380 /* Acknowledge interrupts but still disable interrupts. */ 3381 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3382 3383 more = 0; 3384 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3385 if ((status & INTR_RX_PKT) != 0) { 3386 more = alc_rxintr(sc, sc->alc_process_limit); 3387 if (more == EAGAIN) 3388 sc->alc_morework = 1; 3389 else if (more == EIO) { 3390 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3391 alc_init_locked(sc); 3392 ALC_UNLOCK(sc); 3393 return; 3394 } 3395 } 3396 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3397 INTR_TXQ_TO_RST)) != 0) { 3398 if ((status & INTR_DMA_RD_TO_RST) != 0) 3399 device_printf(sc->alc_dev, 3400 "DMA read error! -- resetting\n"); 3401 if ((status & INTR_DMA_WR_TO_RST) != 0) 3402 device_printf(sc->alc_dev, 3403 "DMA write error! -- resetting\n"); 3404 if ((status & INTR_TXQ_TO_RST) != 0) 3405 device_printf(sc->alc_dev, 3406 "TxQ reset! -- resetting\n"); 3407 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3408 alc_init_locked(sc); 3409 ALC_UNLOCK(sc); 3410 return; 3411 } 3412 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3413 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3414 alc_start_locked(ifp); 3415 } 3416 3417 if (more == EAGAIN || 3418 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3419 ALC_UNLOCK(sc); 3420 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3421 return; 3422 } 3423 3424 done: 3425 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3426 /* Re-enable interrupts if we're running. */ 3427 if (sc->alc_flags & ALC_FLAG_MT) 3428 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3429 else 3430 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3431 } 3432 ALC_UNLOCK(sc); 3433 } 3434 3435 static void 3436 alc_txeof(struct alc_softc *sc) 3437 { 3438 struct ifnet *ifp; 3439 struct alc_txdesc *txd; 3440 uint32_t cons, prod; 3441 3442 ALC_LOCK_ASSERT(sc); 3443 3444 ifp = sc->alc_ifp; 3445 3446 if (sc->alc_cdata.alc_tx_cnt == 0) 3447 return; 3448 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3449 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3450 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3451 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3452 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3453 prod = sc->alc_rdata.alc_cmb->cons; 3454 } else { 3455 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3456 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3457 else { 3458 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3459 /* Assume we're using normal Tx priority queue. */ 3460 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3461 MBOX_TD_CONS_LO_IDX_SHIFT; 3462 } 3463 } 3464 cons = sc->alc_cdata.alc_tx_cons; 3465 /* 3466 * Go through our Tx list and free mbufs for those 3467 * frames which have been transmitted. 3468 */ 3469 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3470 if (sc->alc_cdata.alc_tx_cnt <= 0) 3471 break; 3472 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3473 sc->alc_cdata.alc_tx_cnt--; 3474 txd = &sc->alc_cdata.alc_txdesc[cons]; 3475 if (txd->tx_m != NULL) { 3476 /* Reclaim transmitted mbufs. */ 3477 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3478 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3479 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3480 txd->tx_dmamap); 3481 m_freem(txd->tx_m); 3482 txd->tx_m = NULL; 3483 } 3484 } 3485 3486 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3487 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3488 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3489 sc->alc_cdata.alc_tx_cons = cons; 3490 /* 3491 * Unarm watchdog timer only when there is no pending 3492 * frames in Tx queue. 3493 */ 3494 if (sc->alc_cdata.alc_tx_cnt == 0) 3495 sc->alc_watchdog_timer = 0; 3496 } 3497 3498 static int 3499 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3500 { 3501 struct mbuf *m; 3502 bus_dma_segment_t segs[1]; 3503 bus_dmamap_t map; 3504 int nsegs; 3505 3506 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3507 if (m == NULL) 3508 return (ENOBUFS); 3509 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3510 #ifndef __NO_STRICT_ALIGNMENT 3511 m_adj(m, sizeof(uint64_t)); 3512 #endif 3513 3514 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3515 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3516 m_freem(m); 3517 return (ENOBUFS); 3518 } 3519 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3520 3521 if (rxd->rx_m != NULL) { 3522 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3523 BUS_DMASYNC_POSTREAD); 3524 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3525 } 3526 map = rxd->rx_dmamap; 3527 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3528 sc->alc_cdata.alc_rx_sparemap = map; 3529 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3530 BUS_DMASYNC_PREREAD); 3531 rxd->rx_m = m; 3532 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3533 return (0); 3534 } 3535 3536 static int 3537 alc_rxintr(struct alc_softc *sc, int count) 3538 { 3539 struct ifnet *ifp; 3540 struct rx_rdesc *rrd; 3541 uint32_t nsegs, status; 3542 int rr_cons, prog; 3543 3544 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3545 sc->alc_cdata.alc_rr_ring_map, 3546 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3547 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3548 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3549 rr_cons = sc->alc_cdata.alc_rr_cons; 3550 ifp = sc->alc_ifp; 3551 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3552 if (count-- <= 0) 3553 break; 3554 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3555 status = le32toh(rrd->status); 3556 if ((status & RRD_VALID) == 0) 3557 break; 3558 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3559 if (nsegs == 0) { 3560 /* This should not happen! */ 3561 device_printf(sc->alc_dev, 3562 "unexpected segment count -- resetting\n"); 3563 return (EIO); 3564 } 3565 alc_rxeof(sc, rrd); 3566 /* Clear Rx return status. */ 3567 rrd->status = 0; 3568 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3569 sc->alc_cdata.alc_rx_cons += nsegs; 3570 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3571 prog += nsegs; 3572 } 3573 3574 if (prog > 0) { 3575 /* Update the consumer index. */ 3576 sc->alc_cdata.alc_rr_cons = rr_cons; 3577 /* Sync Rx return descriptors. */ 3578 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3579 sc->alc_cdata.alc_rr_ring_map, 3580 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3581 /* 3582 * Sync updated Rx descriptors such that controller see 3583 * modified buffer addresses. 3584 */ 3585 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3586 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3587 /* 3588 * Let controller know availability of new Rx buffers. 3589 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3590 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3591 * only when Rx buffer pre-fetching is required. In 3592 * addition we already set ALC_RX_RD_FREE_THRESH to 3593 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3594 * it still seems that pre-fetching needs more 3595 * experimentation. 3596 */ 3597 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3598 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3599 (uint16_t)sc->alc_cdata.alc_rx_cons); 3600 else 3601 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3602 sc->alc_cdata.alc_rx_cons); 3603 } 3604 3605 return (count > 0 ? 0 : EAGAIN); 3606 } 3607 3608 #ifndef __NO_STRICT_ALIGNMENT 3609 static struct mbuf * 3610 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3611 { 3612 struct mbuf *n; 3613 int i; 3614 uint16_t *src, *dst; 3615 3616 src = mtod(m, uint16_t *); 3617 dst = src - 3; 3618 3619 if (m->m_next == NULL) { 3620 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3621 *dst++ = *src++; 3622 m->m_data -= 6; 3623 return (m); 3624 } 3625 /* 3626 * Append a new mbuf to received mbuf chain and copy ethernet 3627 * header from the mbuf chain. This can save lots of CPU 3628 * cycles for jumbo frame. 3629 */ 3630 MGETHDR(n, M_NOWAIT, MT_DATA); 3631 if (n == NULL) { 3632 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3633 m_freem(m); 3634 return (NULL); 3635 } 3636 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3637 m->m_data += ETHER_HDR_LEN; 3638 m->m_len -= ETHER_HDR_LEN; 3639 n->m_len = ETHER_HDR_LEN; 3640 M_MOVE_PKTHDR(n, m); 3641 n->m_next = m; 3642 return (n); 3643 } 3644 #endif 3645 3646 /* Receive a frame. */ 3647 static void 3648 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3649 { 3650 struct alc_rxdesc *rxd; 3651 struct ifnet *ifp; 3652 struct mbuf *mp, *m; 3653 uint32_t rdinfo, status, vtag; 3654 int count, nsegs, rx_cons; 3655 3656 ifp = sc->alc_ifp; 3657 status = le32toh(rrd->status); 3658 rdinfo = le32toh(rrd->rdinfo); 3659 rx_cons = RRD_RD_IDX(rdinfo); 3660 nsegs = RRD_RD_CNT(rdinfo); 3661 3662 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3663 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3664 /* 3665 * We want to pass the following frames to upper 3666 * layer regardless of error status of Rx return 3667 * ring. 3668 * 3669 * o IP/TCP/UDP checksum is bad. 3670 * o frame length and protocol specific length 3671 * does not match. 3672 * 3673 * Force network stack compute checksum for 3674 * errored frames. 3675 */ 3676 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3677 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3678 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3679 return; 3680 } 3681 3682 for (count = 0; count < nsegs; count++, 3683 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3684 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3685 mp = rxd->rx_m; 3686 /* Add a new receive buffer to the ring. */ 3687 if (alc_newbuf(sc, rxd) != 0) { 3688 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3689 /* Reuse Rx buffers. */ 3690 if (sc->alc_cdata.alc_rxhead != NULL) 3691 m_freem(sc->alc_cdata.alc_rxhead); 3692 break; 3693 } 3694 3695 /* 3696 * Assume we've received a full sized frame. 3697 * Actual size is fixed when we encounter the end of 3698 * multi-segmented frame. 3699 */ 3700 mp->m_len = sc->alc_buf_size; 3701 3702 /* Chain received mbufs. */ 3703 if (sc->alc_cdata.alc_rxhead == NULL) { 3704 sc->alc_cdata.alc_rxhead = mp; 3705 sc->alc_cdata.alc_rxtail = mp; 3706 } else { 3707 mp->m_flags &= ~M_PKTHDR; 3708 sc->alc_cdata.alc_rxprev_tail = 3709 sc->alc_cdata.alc_rxtail; 3710 sc->alc_cdata.alc_rxtail->m_next = mp; 3711 sc->alc_cdata.alc_rxtail = mp; 3712 } 3713 3714 if (count == nsegs - 1) { 3715 /* Last desc. for this frame. */ 3716 m = sc->alc_cdata.alc_rxhead; 3717 m->m_flags |= M_PKTHDR; 3718 /* 3719 * It seems that L1C/L2C controller has no way 3720 * to tell hardware to strip CRC bytes. 3721 */ 3722 m->m_pkthdr.len = 3723 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3724 if (nsegs > 1) { 3725 /* Set last mbuf size. */ 3726 mp->m_len = sc->alc_cdata.alc_rxlen - 3727 (nsegs - 1) * sc->alc_buf_size; 3728 /* Remove the CRC bytes in chained mbufs. */ 3729 if (mp->m_len <= ETHER_CRC_LEN) { 3730 sc->alc_cdata.alc_rxtail = 3731 sc->alc_cdata.alc_rxprev_tail; 3732 sc->alc_cdata.alc_rxtail->m_len -= 3733 (ETHER_CRC_LEN - mp->m_len); 3734 sc->alc_cdata.alc_rxtail->m_next = NULL; 3735 m_freem(mp); 3736 } else { 3737 mp->m_len -= ETHER_CRC_LEN; 3738 } 3739 } else 3740 m->m_len = m->m_pkthdr.len; 3741 m->m_pkthdr.rcvif = ifp; 3742 /* 3743 * Due to hardware bugs, Rx checksum offloading 3744 * was intentionally disabled. 3745 */ 3746 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3747 (status & RRD_VLAN_TAG) != 0) { 3748 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3749 m->m_pkthdr.ether_vtag = ntohs(vtag); 3750 m->m_flags |= M_VLANTAG; 3751 } 3752 #ifndef __NO_STRICT_ALIGNMENT 3753 m = alc_fixup_rx(ifp, m); 3754 if (m != NULL) 3755 #endif 3756 { 3757 /* Pass it on. */ 3758 ALC_UNLOCK(sc); 3759 (*ifp->if_input)(ifp, m); 3760 ALC_LOCK(sc); 3761 } 3762 } 3763 } 3764 /* Reset mbuf chains. */ 3765 ALC_RXCHAIN_RESET(sc); 3766 } 3767 3768 static void 3769 alc_tick(void *arg) 3770 { 3771 struct alc_softc *sc; 3772 struct mii_data *mii; 3773 3774 sc = (struct alc_softc *)arg; 3775 3776 ALC_LOCK_ASSERT(sc); 3777 3778 mii = device_get_softc(sc->alc_miibus); 3779 mii_tick(mii); 3780 alc_stats_update(sc); 3781 /* 3782 * alc(4) does not rely on Tx completion interrupts to reclaim 3783 * transferred buffers. Instead Tx completion interrupts are 3784 * used to hint for scheduling Tx task. So it's necessary to 3785 * release transmitted buffers by kicking Tx completion 3786 * handler. This limits the maximum reclamation delay to a hz. 3787 */ 3788 alc_txeof(sc); 3789 alc_watchdog(sc); 3790 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3791 } 3792 3793 static void 3794 alc_osc_reset(struct alc_softc *sc) 3795 { 3796 uint32_t reg; 3797 3798 reg = CSR_READ_4(sc, ALC_MISC3); 3799 reg &= ~MISC3_25M_BY_SW; 3800 reg |= MISC3_25M_NOTO_INTNL; 3801 CSR_WRITE_4(sc, ALC_MISC3, reg); 3802 3803 reg = CSR_READ_4(sc, ALC_MISC); 3804 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3805 /* 3806 * Restore over-current protection default value. 3807 * This value could be reset by MAC reset. 3808 */ 3809 reg &= ~MISC_PSW_OCP_MASK; 3810 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3811 reg &= ~MISC_INTNLOSC_OPEN; 3812 CSR_WRITE_4(sc, ALC_MISC, reg); 3813 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3814 reg = CSR_READ_4(sc, ALC_MISC2); 3815 reg &= ~MISC2_CALB_START; 3816 CSR_WRITE_4(sc, ALC_MISC2, reg); 3817 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3818 3819 } else { 3820 reg &= ~MISC_INTNLOSC_OPEN; 3821 /* Disable isolate for revision A devices. */ 3822 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3823 reg &= ~MISC_ISO_ENB; 3824 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3825 CSR_WRITE_4(sc, ALC_MISC, reg); 3826 } 3827 3828 DELAY(20); 3829 } 3830 3831 static void 3832 alc_reset(struct alc_softc *sc) 3833 { 3834 uint32_t pmcfg, reg; 3835 int i; 3836 3837 pmcfg = 0; 3838 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3839 /* Reset workaround. */ 3840 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3841 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3842 (sc->alc_rev & 0x01) != 0) { 3843 /* Disable L0s/L1s before reset. */ 3844 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3845 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3846 != 0) { 3847 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3848 PM_CFG_ASPM_L1_ENB); 3849 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3850 } 3851 } 3852 } 3853 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3854 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3855 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3856 3857 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3858 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3859 DELAY(10); 3860 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3861 break; 3862 } 3863 if (i == 0) 3864 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3865 } 3866 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3867 DELAY(10); 3868 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3869 break; 3870 } 3871 if (i == 0) 3872 device_printf(sc->alc_dev, "master reset timeout!\n"); 3873 3874 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3875 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3876 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3877 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3878 break; 3879 DELAY(10); 3880 } 3881 if (i == 0) 3882 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3883 3884 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3885 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3886 (sc->alc_rev & 0x01) != 0) { 3887 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3888 reg |= MASTER_CLK_SEL_DIS; 3889 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3890 /* Restore L0s/L1s config. */ 3891 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3892 != 0) 3893 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3894 } 3895 3896 alc_osc_reset(sc); 3897 reg = CSR_READ_4(sc, ALC_MISC3); 3898 reg &= ~MISC3_25M_BY_SW; 3899 reg |= MISC3_25M_NOTO_INTNL; 3900 CSR_WRITE_4(sc, ALC_MISC3, reg); 3901 reg = CSR_READ_4(sc, ALC_MISC); 3902 reg &= ~MISC_INTNLOSC_OPEN; 3903 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3904 reg &= ~MISC_ISO_ENB; 3905 CSR_WRITE_4(sc, ALC_MISC, reg); 3906 DELAY(20); 3907 } 3908 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3909 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3910 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3911 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3912 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3913 SERDES_PHY_CLK_SLOWDOWN); 3914 } 3915 3916 static void 3917 alc_init(void *xsc) 3918 { 3919 struct alc_softc *sc; 3920 3921 sc = (struct alc_softc *)xsc; 3922 ALC_LOCK(sc); 3923 alc_init_locked(sc); 3924 ALC_UNLOCK(sc); 3925 } 3926 3927 static void 3928 alc_init_locked(struct alc_softc *sc) 3929 { 3930 struct ifnet *ifp; 3931 uint8_t eaddr[ETHER_ADDR_LEN]; 3932 bus_addr_t paddr; 3933 uint32_t reg, rxf_hi, rxf_lo; 3934 3935 ALC_LOCK_ASSERT(sc); 3936 3937 ifp = sc->alc_ifp; 3938 3939 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3940 return; 3941 /* 3942 * Cancel any pending I/O. 3943 */ 3944 alc_stop(sc); 3945 /* 3946 * Reset the chip to a known state. 3947 */ 3948 alc_reset(sc); 3949 3950 /* Initialize Rx descriptors. */ 3951 if (alc_init_rx_ring(sc) != 0) { 3952 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3953 alc_stop(sc); 3954 return; 3955 } 3956 alc_init_rr_ring(sc); 3957 alc_init_tx_ring(sc); 3958 alc_init_cmb(sc); 3959 alc_init_smb(sc); 3960 3961 /* Enable all clocks. */ 3962 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3963 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3964 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3965 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3966 CLK_GATING_RXMAC_ENB); 3967 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3968 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3969 IDLE_DECISN_TIMER_DEFAULT_1MS); 3970 } else 3971 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3972 3973 /* Reprogram the station address. */ 3974 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3975 CSR_WRITE_4(sc, ALC_PAR0, 3976 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3977 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3978 /* 3979 * Clear WOL status and disable all WOL feature as WOL 3980 * would interfere Rx operation under normal environments. 3981 */ 3982 CSR_READ_4(sc, ALC_WOL_CFG); 3983 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3984 /* Set Tx descriptor base addresses. */ 3985 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3986 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3987 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3988 /* We don't use high priority ring. */ 3989 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3990 /* Set Tx descriptor counter. */ 3991 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3992 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3993 /* Set Rx descriptor base addresses. */ 3994 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3995 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3996 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3997 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3998 /* We use one Rx ring. */ 3999 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 4000 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4001 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4002 } 4003 /* Set Rx descriptor counter. */ 4004 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4005 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4006 4007 /* 4008 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4009 * if it do not fit the buffer size. Rx return descriptor holds 4010 * a counter that indicates how many fragments were made by the 4011 * hardware. The buffer size should be multiple of 8 bytes. 4012 * Since hardware has limit on the size of buffer size, always 4013 * use the maximum value. 4014 * For strict-alignment architectures make sure to reduce buffer 4015 * size by 8 bytes to make room for alignment fixup. 4016 */ 4017 #ifndef __NO_STRICT_ALIGNMENT 4018 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4019 #else 4020 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4021 #endif 4022 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4023 4024 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4025 /* Set Rx return descriptor base addresses. */ 4026 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4027 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4028 /* We use one Rx return ring. */ 4029 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4030 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4031 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4032 } 4033 /* Set Rx return descriptor counter. */ 4034 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4035 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4036 paddr = sc->alc_rdata.alc_cmb_paddr; 4037 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4038 paddr = sc->alc_rdata.alc_smb_paddr; 4039 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4040 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4041 4042 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4043 /* Reconfigure SRAM - Vendor magic. */ 4044 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4045 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4046 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4047 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4048 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4049 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4050 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4051 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4052 } 4053 4054 /* Tell hardware that we're ready to load DMA blocks. */ 4055 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4056 4057 /* Configure interrupt moderation timer. */ 4058 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4059 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4060 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4061 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4062 /* 4063 * We don't want to automatic interrupt clear as task queue 4064 * for the interrupt should know interrupt status. 4065 */ 4066 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4067 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4068 reg |= MASTER_SA_TIMER_ENB; 4069 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4070 reg |= MASTER_IM_RX_TIMER_ENB; 4071 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4072 ALC_USECS(sc->alc_int_tx_mod) != 0) 4073 reg |= MASTER_IM_TX_TIMER_ENB; 4074 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4075 /* 4076 * Disable interrupt re-trigger timer. We don't want automatic 4077 * re-triggering of un-ACKed interrupts. 4078 */ 4079 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4080 /* Configure CMB. */ 4081 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4082 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4083 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4084 ALC_USECS(sc->alc_int_tx_mod)); 4085 } else { 4086 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4087 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4088 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4089 } else 4090 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4091 } 4092 /* 4093 * Hardware can be configured to issue SMB interrupt based 4094 * on programmed interval. Since there is a callout that is 4095 * invoked for every hz in driver we use that instead of 4096 * relying on periodic SMB interrupt. 4097 */ 4098 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4099 /* Clear MAC statistics. */ 4100 alc_stats_clear(sc); 4101 4102 /* 4103 * Always use maximum frame size that controller can support. 4104 * Otherwise received frames that has larger frame length 4105 * than alc(4) MTU would be silently dropped in hardware. This 4106 * would make path-MTU discovery hard as sender wouldn't get 4107 * any responses from receiver. alc(4) supports 4108 * multi-fragmented frames on Rx path so it has no issue on 4109 * assembling fragmented frames. Using maximum frame size also 4110 * removes the need to reinitialize hardware when interface 4111 * MTU configuration was changed. 4112 * 4113 * Be conservative in what you do, be liberal in what you 4114 * accept from others - RFC 793. 4115 */ 4116 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4117 4118 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4119 /* Disable header split(?) */ 4120 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4121 4122 /* Configure IPG/IFG parameters. */ 4123 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4124 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4125 IPG_IFG_IPGT_MASK) | 4126 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4127 IPG_IFG_MIFG_MASK) | 4128 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4129 IPG_IFG_IPG1_MASK) | 4130 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4131 IPG_IFG_IPG2_MASK)); 4132 /* Set parameters for half-duplex media. */ 4133 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4134 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4135 HDPX_CFG_LCOL_MASK) | 4136 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4137 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4138 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4139 HDPX_CFG_ABEBT_MASK) | 4140 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4141 HDPX_CFG_JAMIPG_MASK)); 4142 } 4143 4144 /* 4145 * Set TSO/checksum offload threshold. For frames that is 4146 * larger than this threshold, hardware wouldn't do 4147 * TSO/checksum offloading. 4148 */ 4149 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4150 TSO_OFFLOAD_THRESH_MASK; 4151 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4152 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4153 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4154 /* Configure TxQ. */ 4155 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4156 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4157 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4158 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4159 reg >>= 1; 4160 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4161 TXQ_CFG_TD_BURST_MASK; 4162 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4163 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4164 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4165 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4166 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4167 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4168 HQTD_CFG_BURST_ENB); 4169 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4170 reg = WRR_PRI_RESTRICT_NONE; 4171 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4172 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4173 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4174 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4175 CSR_WRITE_4(sc, ALC_WRR, reg); 4176 } else { 4177 /* Configure Rx free descriptor pre-fetching. */ 4178 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4179 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4180 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4181 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4182 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4183 } 4184 4185 /* 4186 * Configure flow control parameters. 4187 * XON : 80% of Rx FIFO 4188 * XOFF : 30% of Rx FIFO 4189 */ 4190 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4191 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4192 reg &= SRAM_RX_FIFO_LEN_MASK; 4193 reg *= 8; 4194 if (reg > 8 * 1024) 4195 reg -= RX_FIFO_PAUSE_816X_RSVD; 4196 else 4197 reg -= RX_BUF_SIZE_MAX; 4198 reg /= 8; 4199 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4200 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4201 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4202 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4203 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4204 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4205 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4206 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4207 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4208 rxf_hi = (reg * 8) / 10; 4209 rxf_lo = (reg * 3) / 10; 4210 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4211 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4212 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4213 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4214 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4215 } 4216 4217 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4218 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4219 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4220 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4221 } 4222 4223 /* Configure RxQ. */ 4224 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4225 RXQ_CFG_RD_BURST_MASK; 4226 reg |= RXQ_CFG_RSS_MODE_DIS; 4227 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4228 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4229 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4230 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4231 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4232 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4233 } else { 4234 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4235 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4236 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4237 } 4238 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4239 4240 /* Configure DMA parameters. */ 4241 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4242 reg |= sc->alc_rcb; 4243 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4244 reg |= DMA_CFG_CMB_ENB; 4245 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4246 reg |= DMA_CFG_SMB_ENB; 4247 else 4248 reg |= DMA_CFG_SMB_DIS; 4249 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4250 DMA_CFG_RD_BURST_SHIFT; 4251 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4252 DMA_CFG_WR_BURST_SHIFT; 4253 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4254 DMA_CFG_RD_DELAY_CNT_MASK; 4255 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4256 DMA_CFG_WR_DELAY_CNT_MASK; 4257 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4258 switch (AR816X_REV(sc->alc_rev)) { 4259 case AR816X_REV_A0: 4260 case AR816X_REV_A1: 4261 reg |= DMA_CFG_RD_CHNL_SEL_2; 4262 break; 4263 case AR816X_REV_B0: 4264 /* FALLTHROUGH */ 4265 default: 4266 reg |= DMA_CFG_RD_CHNL_SEL_4; 4267 break; 4268 } 4269 } 4270 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4271 4272 /* 4273 * Configure Tx/Rx MACs. 4274 * - Auto-padding for short frames. 4275 * - Enable CRC generation. 4276 * Actual reconfiguration of MAC for resolved speed/duplex 4277 * is followed after detection of link establishment. 4278 * AR813x/AR815x always does checksum computation regardless 4279 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4280 * have bug in protocol field in Rx return structure so 4281 * these controllers can't handle fragmented frames. Disable 4282 * Rx checksum offloading until there is a newer controller 4283 * that has sane implementation. 4284 */ 4285 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4286 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4287 MAC_CFG_PREAMBLE_MASK); 4288 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4289 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4290 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4291 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4292 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4293 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4294 reg |= MAC_CFG_SPEED_10_100; 4295 else 4296 reg |= MAC_CFG_SPEED_1000; 4297 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4298 4299 /* Set up the receive filter. */ 4300 alc_rxfilter(sc); 4301 alc_rxvlan(sc); 4302 4303 /* Acknowledge all pending interrupts and clear it. */ 4304 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4305 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4306 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4307 4308 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4309 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4310 4311 sc->alc_flags &= ~ALC_FLAG_LINK; 4312 /* Switch to the current media. */ 4313 alc_mediachange_locked(sc); 4314 4315 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4316 } 4317 4318 static void 4319 alc_stop(struct alc_softc *sc) 4320 { 4321 struct ifnet *ifp; 4322 struct alc_txdesc *txd; 4323 struct alc_rxdesc *rxd; 4324 uint32_t reg; 4325 int i; 4326 4327 ALC_LOCK_ASSERT(sc); 4328 /* 4329 * Mark the interface down and cancel the watchdog timer. 4330 */ 4331 ifp = sc->alc_ifp; 4332 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4333 sc->alc_flags &= ~ALC_FLAG_LINK; 4334 callout_stop(&sc->alc_tick_ch); 4335 sc->alc_watchdog_timer = 0; 4336 alc_stats_update(sc); 4337 /* Disable interrupts. */ 4338 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4339 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4340 /* Disable DMA. */ 4341 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4342 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4343 reg |= DMA_CFG_SMB_DIS; 4344 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4345 DELAY(1000); 4346 /* Stop Rx/Tx MACs. */ 4347 alc_stop_mac(sc); 4348 /* Disable interrupts which might be touched in taskq handler. */ 4349 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4350 /* Disable L0s/L1s */ 4351 alc_aspm(sc, 0, IFM_UNKNOWN); 4352 /* Reclaim Rx buffers that have been processed. */ 4353 if (sc->alc_cdata.alc_rxhead != NULL) 4354 m_freem(sc->alc_cdata.alc_rxhead); 4355 ALC_RXCHAIN_RESET(sc); 4356 /* 4357 * Free Tx/Rx mbufs still in the queues. 4358 */ 4359 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4360 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4361 if (rxd->rx_m != NULL) { 4362 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4363 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4364 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4365 rxd->rx_dmamap); 4366 m_freem(rxd->rx_m); 4367 rxd->rx_m = NULL; 4368 } 4369 } 4370 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4371 txd = &sc->alc_cdata.alc_txdesc[i]; 4372 if (txd->tx_m != NULL) { 4373 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4374 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4375 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4376 txd->tx_dmamap); 4377 m_freem(txd->tx_m); 4378 txd->tx_m = NULL; 4379 } 4380 } 4381 } 4382 4383 static void 4384 alc_stop_mac(struct alc_softc *sc) 4385 { 4386 uint32_t reg; 4387 int i; 4388 4389 alc_stop_queue(sc); 4390 /* Disable Rx/Tx MAC. */ 4391 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4392 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4393 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4394 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4395 } 4396 for (i = ALC_TIMEOUT; i > 0; i--) { 4397 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4398 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4399 break; 4400 DELAY(10); 4401 } 4402 if (i == 0) 4403 device_printf(sc->alc_dev, 4404 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4405 } 4406 4407 static void 4408 alc_start_queue(struct alc_softc *sc) 4409 { 4410 uint32_t qcfg[] = { 4411 0, 4412 RXQ_CFG_QUEUE0_ENB, 4413 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4414 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4415 RXQ_CFG_ENB 4416 }; 4417 uint32_t cfg; 4418 4419 ALC_LOCK_ASSERT(sc); 4420 4421 /* Enable RxQ. */ 4422 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4423 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4424 cfg &= ~RXQ_CFG_ENB; 4425 cfg |= qcfg[1]; 4426 } else 4427 cfg |= RXQ_CFG_QUEUE0_ENB; 4428 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4429 /* Enable TxQ. */ 4430 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4431 cfg |= TXQ_CFG_ENB; 4432 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4433 } 4434 4435 static void 4436 alc_stop_queue(struct alc_softc *sc) 4437 { 4438 uint32_t reg; 4439 int i; 4440 4441 /* Disable RxQ. */ 4442 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4443 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4444 if ((reg & RXQ_CFG_ENB) != 0) { 4445 reg &= ~RXQ_CFG_ENB; 4446 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4447 } 4448 } else { 4449 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4450 reg &= ~RXQ_CFG_QUEUE0_ENB; 4451 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4452 } 4453 } 4454 /* Disable TxQ. */ 4455 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4456 if ((reg & TXQ_CFG_ENB) != 0) { 4457 reg &= ~TXQ_CFG_ENB; 4458 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4459 } 4460 DELAY(40); 4461 for (i = ALC_TIMEOUT; i > 0; i--) { 4462 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4463 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4464 break; 4465 DELAY(10); 4466 } 4467 if (i == 0) 4468 device_printf(sc->alc_dev, 4469 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4470 } 4471 4472 static void 4473 alc_init_tx_ring(struct alc_softc *sc) 4474 { 4475 struct alc_ring_data *rd; 4476 struct alc_txdesc *txd; 4477 int i; 4478 4479 ALC_LOCK_ASSERT(sc); 4480 4481 sc->alc_cdata.alc_tx_prod = 0; 4482 sc->alc_cdata.alc_tx_cons = 0; 4483 sc->alc_cdata.alc_tx_cnt = 0; 4484 4485 rd = &sc->alc_rdata; 4486 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4487 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4488 txd = &sc->alc_cdata.alc_txdesc[i]; 4489 txd->tx_m = NULL; 4490 } 4491 4492 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4493 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4494 } 4495 4496 static int 4497 alc_init_rx_ring(struct alc_softc *sc) 4498 { 4499 struct alc_ring_data *rd; 4500 struct alc_rxdesc *rxd; 4501 int i; 4502 4503 ALC_LOCK_ASSERT(sc); 4504 4505 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4506 sc->alc_morework = 0; 4507 rd = &sc->alc_rdata; 4508 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4509 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4510 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4511 rxd->rx_m = NULL; 4512 rxd->rx_desc = &rd->alc_rx_ring[i]; 4513 if (alc_newbuf(sc, rxd) != 0) 4514 return (ENOBUFS); 4515 } 4516 4517 /* 4518 * Since controller does not update Rx descriptors, driver 4519 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4520 * is enough to ensure coherence. 4521 */ 4522 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4523 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4524 /* Let controller know availability of new Rx buffers. */ 4525 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4526 4527 return (0); 4528 } 4529 4530 static void 4531 alc_init_rr_ring(struct alc_softc *sc) 4532 { 4533 struct alc_ring_data *rd; 4534 4535 ALC_LOCK_ASSERT(sc); 4536 4537 sc->alc_cdata.alc_rr_cons = 0; 4538 ALC_RXCHAIN_RESET(sc); 4539 4540 rd = &sc->alc_rdata; 4541 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4542 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4543 sc->alc_cdata.alc_rr_ring_map, 4544 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4545 } 4546 4547 static void 4548 alc_init_cmb(struct alc_softc *sc) 4549 { 4550 struct alc_ring_data *rd; 4551 4552 ALC_LOCK_ASSERT(sc); 4553 4554 rd = &sc->alc_rdata; 4555 bzero(rd->alc_cmb, ALC_CMB_SZ); 4556 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4558 } 4559 4560 static void 4561 alc_init_smb(struct alc_softc *sc) 4562 { 4563 struct alc_ring_data *rd; 4564 4565 ALC_LOCK_ASSERT(sc); 4566 4567 rd = &sc->alc_rdata; 4568 bzero(rd->alc_smb, ALC_SMB_SZ); 4569 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4571 } 4572 4573 static void 4574 alc_rxvlan(struct alc_softc *sc) 4575 { 4576 struct ifnet *ifp; 4577 uint32_t reg; 4578 4579 ALC_LOCK_ASSERT(sc); 4580 4581 ifp = sc->alc_ifp; 4582 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4583 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4584 reg |= MAC_CFG_VLAN_TAG_STRIP; 4585 else 4586 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4587 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4588 } 4589 4590 static u_int 4591 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4592 { 4593 uint32_t *mchash = arg; 4594 uint32_t crc; 4595 4596 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4597 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4598 4599 return (1); 4600 } 4601 4602 static void 4603 alc_rxfilter(struct alc_softc *sc) 4604 { 4605 struct ifnet *ifp; 4606 uint32_t mchash[2]; 4607 uint32_t rxcfg; 4608 4609 ALC_LOCK_ASSERT(sc); 4610 4611 ifp = sc->alc_ifp; 4612 4613 bzero(mchash, sizeof(mchash)); 4614 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4615 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4616 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4617 rxcfg |= MAC_CFG_BCAST; 4618 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4619 if ((ifp->if_flags & IFF_PROMISC) != 0) 4620 rxcfg |= MAC_CFG_PROMISC; 4621 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4622 rxcfg |= MAC_CFG_ALLMULTI; 4623 mchash[0] = 0xFFFFFFFF; 4624 mchash[1] = 0xFFFFFFFF; 4625 goto chipit; 4626 } 4627 4628 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4629 4630 chipit: 4631 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4632 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4633 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4634 } 4635 4636 static int 4637 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4638 { 4639 int error, value; 4640 4641 if (arg1 == NULL) 4642 return (EINVAL); 4643 value = *(int *)arg1; 4644 error = sysctl_handle_int(oidp, &value, 0, req); 4645 if (error || req->newptr == NULL) 4646 return (error); 4647 if (value < low || value > high) 4648 return (EINVAL); 4649 *(int *)arg1 = value; 4650 4651 return (0); 4652 } 4653 4654 static int 4655 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4656 { 4657 return (sysctl_int_range(oidp, arg1, arg2, req, 4658 ALC_PROC_MIN, ALC_PROC_MAX)); 4659 } 4660 4661 static int 4662 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4663 { 4664 4665 return (sysctl_int_range(oidp, arg1, arg2, req, 4666 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4667 } 4668 4669 #ifdef DEBUGNET 4670 static void 4671 alc_debugnet_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 4672 { 4673 struct alc_softc *sc __diagused; 4674 4675 sc = if_getsoftc(ifp); 4676 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4677 4678 *nrxr = ALC_RX_RING_CNT; 4679 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4680 *clsize = MCLBYTES; 4681 } 4682 4683 static void 4684 alc_debugnet_event(struct ifnet *ifp __unused, enum debugnet_ev event __unused) 4685 { 4686 } 4687 4688 static int 4689 alc_debugnet_transmit(struct ifnet *ifp, struct mbuf *m) 4690 { 4691 struct alc_softc *sc; 4692 int error; 4693 4694 sc = if_getsoftc(ifp); 4695 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4696 IFF_DRV_RUNNING) 4697 return (EBUSY); 4698 4699 error = alc_encap(sc, &m); 4700 if (error == 0) 4701 alc_start_tx(sc); 4702 return (error); 4703 } 4704 4705 static int 4706 alc_debugnet_poll(struct ifnet *ifp, int count) 4707 { 4708 struct alc_softc *sc; 4709 4710 sc = if_getsoftc(ifp); 4711 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4712 IFF_DRV_RUNNING) 4713 return (EBUSY); 4714 4715 alc_txeof(sc); 4716 return (alc_rxintr(sc, count)); 4717 } 4718 #endif /* DEBUGNET */
Cache object: 03ec04e37394552be12e140ed412b478
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]