Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/alc/if_alc.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/bus.h> 72 #include <machine/in_cksum.h> 73 74 #include <dev/alc/if_alcreg.h> 75 #include <dev/alc/if_alcvar.h> 76 77 /* "device miibus" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 #undef ALC_USE_CUSTOM_CSUM 80 81 #ifdef ALC_USE_CUSTOM_CSUM 82 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 #else 84 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 #endif 86 87 MODULE_DEPEND(alc, pci, 1, 1, 1); 88 MODULE_DEPEND(alc, ether, 1, 1, 1); 89 MODULE_DEPEND(alc, miibus, 1, 1, 1); 90 91 /* Tunables. */ 92 static int msi_disable = 0; 93 static int msix_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 96 97 /* 98 * Devices supported by this driver. 99 */ 100 static struct alc_ident alc_ident_table[] = { 101 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 102 "Atheros AR8131 PCIe Gigabit Ethernet" }, 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 104 "Atheros AR8132 PCIe Fast Ethernet" }, 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 106 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 108 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 110 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 112 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 114 "Atheros AR8161 PCIe Gigabit Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 116 "Atheros AR8162 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 118 "Atheros AR8171 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 120 "Atheros AR8172 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 122 "Killer E2200 Gigabit Ethernet" }, 123 { 0, 0, 0, NULL} 124 }; 125 126 static void alc_aspm(struct alc_softc *, int, int); 127 static void alc_aspm_813x(struct alc_softc *, int); 128 static void alc_aspm_816x(struct alc_softc *, int); 129 static int alc_attach(device_t); 130 static int alc_check_boundary(struct alc_softc *); 131 static void alc_config_msi(struct alc_softc *); 132 static int alc_detach(device_t); 133 static void alc_disable_l0s_l1(struct alc_softc *); 134 static int alc_dma_alloc(struct alc_softc *); 135 static void alc_dma_free(struct alc_softc *); 136 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 137 static void alc_dsp_fixup(struct alc_softc *, int); 138 static int alc_encap(struct alc_softc *, struct mbuf **); 139 static struct alc_ident * 140 alc_find_ident(device_t); 141 #ifndef __NO_STRICT_ALIGNMENT 142 static struct mbuf * 143 alc_fixup_rx(struct ifnet *, struct mbuf *); 144 #endif 145 static void alc_get_macaddr(struct alc_softc *); 146 static void alc_get_macaddr_813x(struct alc_softc *); 147 static void alc_get_macaddr_816x(struct alc_softc *); 148 static void alc_get_macaddr_par(struct alc_softc *); 149 static void alc_init(void *); 150 static void alc_init_cmb(struct alc_softc *); 151 static void alc_init_locked(struct alc_softc *); 152 static void alc_init_rr_ring(struct alc_softc *); 153 static int alc_init_rx_ring(struct alc_softc *); 154 static void alc_init_smb(struct alc_softc *); 155 static void alc_init_tx_ring(struct alc_softc *); 156 static void alc_int_task(void *, int); 157 static int alc_intr(void *); 158 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 159 static void alc_mac_config(struct alc_softc *); 160 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 161 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 162 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 163 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 164 static int alc_miibus_readreg(device_t, int, int); 165 static void alc_miibus_statchg(device_t); 166 static int alc_miibus_writereg(device_t, int, int, int); 167 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 168 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 169 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 170 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 171 static int alc_mediachange(struct ifnet *); 172 static int alc_mediachange_locked(struct alc_softc *); 173 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 174 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 175 static void alc_osc_reset(struct alc_softc *); 176 static void alc_phy_down(struct alc_softc *); 177 static void alc_phy_reset(struct alc_softc *); 178 static void alc_phy_reset_813x(struct alc_softc *); 179 static void alc_phy_reset_816x(struct alc_softc *); 180 static int alc_probe(device_t); 181 static void alc_reset(struct alc_softc *); 182 static int alc_resume(device_t); 183 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 184 static int alc_rxintr(struct alc_softc *, int); 185 static void alc_rxfilter(struct alc_softc *); 186 static void alc_rxvlan(struct alc_softc *); 187 static void alc_setlinkspeed(struct alc_softc *); 188 static void alc_setwol(struct alc_softc *); 189 static void alc_setwol_813x(struct alc_softc *); 190 static void alc_setwol_816x(struct alc_softc *); 191 static int alc_shutdown(device_t); 192 static void alc_start(struct ifnet *); 193 static void alc_start_locked(struct ifnet *); 194 static void alc_start_queue(struct alc_softc *); 195 static void alc_stats_clear(struct alc_softc *); 196 static void alc_stats_update(struct alc_softc *); 197 static void alc_stop(struct alc_softc *); 198 static void alc_stop_mac(struct alc_softc *); 199 static void alc_stop_queue(struct alc_softc *); 200 static int alc_suspend(device_t); 201 static void alc_sysctl_node(struct alc_softc *); 202 static void alc_tick(void *); 203 static void alc_txeof(struct alc_softc *); 204 static void alc_watchdog(struct alc_softc *); 205 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 206 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 207 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 208 209 static device_method_t alc_methods[] = { 210 /* Device interface. */ 211 DEVMETHOD(device_probe, alc_probe), 212 DEVMETHOD(device_attach, alc_attach), 213 DEVMETHOD(device_detach, alc_detach), 214 DEVMETHOD(device_shutdown, alc_shutdown), 215 DEVMETHOD(device_suspend, alc_suspend), 216 DEVMETHOD(device_resume, alc_resume), 217 218 /* MII interface. */ 219 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 220 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 221 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 222 223 { NULL, NULL } 224 }; 225 226 static driver_t alc_driver = { 227 "alc", 228 alc_methods, 229 sizeof(struct alc_softc) 230 }; 231 232 static devclass_t alc_devclass; 233 234 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 235 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 236 237 static struct resource_spec alc_res_spec_mem[] = { 238 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 239 { -1, 0, 0 } 240 }; 241 242 static struct resource_spec alc_irq_spec_legacy[] = { 243 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 244 { -1, 0, 0 } 245 }; 246 247 static struct resource_spec alc_irq_spec_msi[] = { 248 { SYS_RES_IRQ, 1, RF_ACTIVE }, 249 { -1, 0, 0 } 250 }; 251 252 static struct resource_spec alc_irq_spec_msix[] = { 253 { SYS_RES_IRQ, 1, RF_ACTIVE }, 254 { -1, 0, 0 } 255 }; 256 257 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 258 259 static int 260 alc_miibus_readreg(device_t dev, int phy, int reg) 261 { 262 struct alc_softc *sc; 263 int v; 264 265 sc = device_get_softc(dev); 266 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 267 v = alc_mii_readreg_816x(sc, phy, reg); 268 else 269 v = alc_mii_readreg_813x(sc, phy, reg); 270 return (v); 271 } 272 273 static uint32_t 274 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 275 { 276 uint32_t v; 277 int i; 278 279 /* 280 * For AR8132 fast ethernet controller, do not report 1000baseT 281 * capability to mii(4). Even though AR8132 uses the same 282 * model/revision number of F1 gigabit PHY, the PHY has no 283 * ability to establish 1000baseT link. 284 */ 285 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 286 reg == MII_EXTSR) 287 return (0); 288 289 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 290 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 291 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 292 DELAY(5); 293 v = CSR_READ_4(sc, ALC_MDIO); 294 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 295 break; 296 } 297 298 if (i == 0) { 299 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 300 return (0); 301 } 302 303 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 304 } 305 306 static uint32_t 307 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 308 { 309 uint32_t clk, v; 310 int i; 311 312 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 313 clk = MDIO_CLK_25_128; 314 else 315 clk = MDIO_CLK_25_4; 316 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 317 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 318 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 319 DELAY(5); 320 v = CSR_READ_4(sc, ALC_MDIO); 321 if ((v & MDIO_OP_BUSY) == 0) 322 break; 323 } 324 325 if (i == 0) { 326 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 327 return (0); 328 } 329 330 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 331 } 332 333 static int 334 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 335 { 336 struct alc_softc *sc; 337 int v; 338 339 sc = device_get_softc(dev); 340 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 341 v = alc_mii_writereg_816x(sc, phy, reg, val); 342 else 343 v = alc_mii_writereg_813x(sc, phy, reg, val); 344 return (v); 345 } 346 347 static uint32_t 348 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 349 { 350 uint32_t v; 351 int i; 352 353 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 354 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 355 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 356 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 357 DELAY(5); 358 v = CSR_READ_4(sc, ALC_MDIO); 359 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 360 break; 361 } 362 363 if (i == 0) 364 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 365 366 return (0); 367 } 368 369 static uint32_t 370 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 371 { 372 uint32_t clk, v; 373 int i; 374 375 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 376 clk = MDIO_CLK_25_128; 377 else 378 clk = MDIO_CLK_25_4; 379 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 380 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 381 MDIO_SUP_PREAMBLE | clk); 382 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 383 DELAY(5); 384 v = CSR_READ_4(sc, ALC_MDIO); 385 if ((v & MDIO_OP_BUSY) == 0) 386 break; 387 } 388 389 if (i == 0) 390 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 391 392 return (0); 393 } 394 395 static void 396 alc_miibus_statchg(device_t dev) 397 { 398 struct alc_softc *sc; 399 struct mii_data *mii; 400 struct ifnet *ifp; 401 uint32_t reg; 402 403 sc = device_get_softc(dev); 404 405 mii = device_get_softc(sc->alc_miibus); 406 ifp = sc->alc_ifp; 407 if (mii == NULL || ifp == NULL || 408 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 409 return; 410 411 sc->alc_flags &= ~ALC_FLAG_LINK; 412 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 413 (IFM_ACTIVE | IFM_AVALID)) { 414 switch (IFM_SUBTYPE(mii->mii_media_active)) { 415 case IFM_10_T: 416 case IFM_100_TX: 417 sc->alc_flags |= ALC_FLAG_LINK; 418 break; 419 case IFM_1000_T: 420 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 421 sc->alc_flags |= ALC_FLAG_LINK; 422 break; 423 default: 424 break; 425 } 426 } 427 /* Stop Rx/Tx MACs. */ 428 alc_stop_mac(sc); 429 430 /* Program MACs with resolved speed/duplex/flow-control. */ 431 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 432 alc_start_queue(sc); 433 alc_mac_config(sc); 434 /* Re-enable Tx/Rx MACs. */ 435 reg = CSR_READ_4(sc, ALC_MAC_CFG); 436 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 437 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 438 } 439 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 440 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 441 } 442 443 static uint32_t 444 alc_miidbg_readreg(struct alc_softc *sc, int reg) 445 { 446 447 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 448 reg); 449 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 450 ALC_MII_DBG_DATA)); 451 } 452 453 static uint32_t 454 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 455 { 456 457 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 458 reg); 459 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 460 ALC_MII_DBG_DATA, val)); 461 } 462 463 static uint32_t 464 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 465 { 466 uint32_t clk, v; 467 int i; 468 469 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 470 EXT_MDIO_DEVADDR(devaddr)); 471 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 472 clk = MDIO_CLK_25_128; 473 else 474 clk = MDIO_CLK_25_4; 475 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 476 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 477 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 478 DELAY(5); 479 v = CSR_READ_4(sc, ALC_MDIO); 480 if ((v & MDIO_OP_BUSY) == 0) 481 break; 482 } 483 484 if (i == 0) { 485 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 486 devaddr, reg); 487 return (0); 488 } 489 490 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 491 } 492 493 static uint32_t 494 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 495 { 496 uint32_t clk, v; 497 int i; 498 499 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 500 EXT_MDIO_DEVADDR(devaddr)); 501 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 502 clk = MDIO_CLK_25_128; 503 else 504 clk = MDIO_CLK_25_4; 505 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 506 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 507 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 508 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 509 DELAY(5); 510 v = CSR_READ_4(sc, ALC_MDIO); 511 if ((v & MDIO_OP_BUSY) == 0) 512 break; 513 } 514 515 if (i == 0) 516 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 517 devaddr, reg); 518 519 return (0); 520 } 521 522 static void 523 alc_dsp_fixup(struct alc_softc *sc, int media) 524 { 525 uint16_t agc, len, val; 526 527 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 528 return; 529 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 530 return; 531 532 /* 533 * Vendor PHY magic. 534 * 1000BT/AZ, wrong cable length 535 */ 536 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 537 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 538 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 539 EXT_CLDCTL6_CAB_LEN_MASK; 540 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 541 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 542 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 543 agc > DBG_AGC_LONG1G_LIMT) || 544 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 545 agc > DBG_AGC_LONG1G_LIMT)) { 546 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 547 DBG_AZ_ANADECT_LONG); 548 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 549 MII_EXT_ANEG_AFE); 550 val |= ANEG_AFEE_10BT_100M_TH; 551 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 552 val); 553 } else { 554 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 555 DBG_AZ_ANADECT_DEFAULT); 556 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 557 MII_EXT_ANEG_AFE); 558 val &= ~ANEG_AFEE_10BT_100M_TH; 559 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 560 val); 561 } 562 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 563 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 564 if (media == IFM_1000_T) { 565 /* 566 * Giga link threshold, raise the tolerance of 567 * noise 50%. 568 */ 569 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 570 val &= ~DBG_MSE20DB_TH_MASK; 571 val |= (DBG_MSE20DB_TH_HI << 572 DBG_MSE20DB_TH_SHIFT); 573 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 574 } else if (media == IFM_100_TX) 575 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 576 DBG_MSE16DB_UP); 577 } 578 } else { 579 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 580 val &= ~ANEG_AFEE_10BT_100M_TH; 581 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 582 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 583 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 584 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 585 DBG_MSE16DB_DOWN); 586 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 587 val &= ~DBG_MSE20DB_TH_MASK; 588 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 589 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 590 } 591 } 592 } 593 594 static void 595 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 596 { 597 struct alc_softc *sc; 598 struct mii_data *mii; 599 600 sc = ifp->if_softc; 601 ALC_LOCK(sc); 602 if ((ifp->if_flags & IFF_UP) == 0) { 603 ALC_UNLOCK(sc); 604 return; 605 } 606 mii = device_get_softc(sc->alc_miibus); 607 608 mii_pollstat(mii); 609 ifmr->ifm_status = mii->mii_media_status; 610 ifmr->ifm_active = mii->mii_media_active; 611 ALC_UNLOCK(sc); 612 } 613 614 static int 615 alc_mediachange(struct ifnet *ifp) 616 { 617 struct alc_softc *sc; 618 int error; 619 620 sc = ifp->if_softc; 621 ALC_LOCK(sc); 622 error = alc_mediachange_locked(sc); 623 ALC_UNLOCK(sc); 624 625 return (error); 626 } 627 628 static int 629 alc_mediachange_locked(struct alc_softc *sc) 630 { 631 struct mii_data *mii; 632 struct mii_softc *miisc; 633 int error; 634 635 ALC_LOCK_ASSERT(sc); 636 637 mii = device_get_softc(sc->alc_miibus); 638 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 639 PHY_RESET(miisc); 640 error = mii_mediachg(mii); 641 642 return (error); 643 } 644 645 static struct alc_ident * 646 alc_find_ident(device_t dev) 647 { 648 struct alc_ident *ident; 649 uint16_t vendor, devid; 650 651 vendor = pci_get_vendor(dev); 652 devid = pci_get_device(dev); 653 for (ident = alc_ident_table; ident->name != NULL; ident++) { 654 if (vendor == ident->vendorid && devid == ident->deviceid) 655 return (ident); 656 } 657 658 return (NULL); 659 } 660 661 static int 662 alc_probe(device_t dev) 663 { 664 struct alc_ident *ident; 665 666 ident = alc_find_ident(dev); 667 if (ident != NULL) { 668 device_set_desc(dev, ident->name); 669 return (BUS_PROBE_DEFAULT); 670 } 671 672 return (ENXIO); 673 } 674 675 static void 676 alc_get_macaddr(struct alc_softc *sc) 677 { 678 679 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 680 alc_get_macaddr_816x(sc); 681 else 682 alc_get_macaddr_813x(sc); 683 } 684 685 static void 686 alc_get_macaddr_813x(struct alc_softc *sc) 687 { 688 uint32_t opt; 689 uint16_t val; 690 int eeprom, i; 691 692 eeprom = 0; 693 opt = CSR_READ_4(sc, ALC_OPT_CFG); 694 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 695 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 696 /* 697 * EEPROM found, let TWSI reload EEPROM configuration. 698 * This will set ethernet address of controller. 699 */ 700 eeprom++; 701 switch (sc->alc_ident->deviceid) { 702 case DEVICEID_ATHEROS_AR8131: 703 case DEVICEID_ATHEROS_AR8132: 704 if ((opt & OPT_CFG_CLK_ENB) == 0) { 705 opt |= OPT_CFG_CLK_ENB; 706 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 707 CSR_READ_4(sc, ALC_OPT_CFG); 708 DELAY(1000); 709 } 710 break; 711 case DEVICEID_ATHEROS_AR8151: 712 case DEVICEID_ATHEROS_AR8151_V2: 713 case DEVICEID_ATHEROS_AR8152_B: 714 case DEVICEID_ATHEROS_AR8152_B2: 715 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 716 ALC_MII_DBG_ADDR, 0x00); 717 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 718 ALC_MII_DBG_DATA); 719 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 720 ALC_MII_DBG_DATA, val & 0xFF7F); 721 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 722 ALC_MII_DBG_ADDR, 0x3B); 723 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 724 ALC_MII_DBG_DATA); 725 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 726 ALC_MII_DBG_DATA, val | 0x0008); 727 DELAY(20); 728 break; 729 } 730 731 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 732 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 733 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 734 CSR_READ_4(sc, ALC_WOL_CFG); 735 736 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 737 TWSI_CFG_SW_LD_START); 738 for (i = 100; i > 0; i--) { 739 DELAY(1000); 740 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 741 TWSI_CFG_SW_LD_START) == 0) 742 break; 743 } 744 if (i == 0) 745 device_printf(sc->alc_dev, 746 "reloading EEPROM timeout!\n"); 747 } else { 748 if (bootverbose) 749 device_printf(sc->alc_dev, "EEPROM not found!\n"); 750 } 751 if (eeprom != 0) { 752 switch (sc->alc_ident->deviceid) { 753 case DEVICEID_ATHEROS_AR8131: 754 case DEVICEID_ATHEROS_AR8132: 755 if ((opt & OPT_CFG_CLK_ENB) != 0) { 756 opt &= ~OPT_CFG_CLK_ENB; 757 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 758 CSR_READ_4(sc, ALC_OPT_CFG); 759 DELAY(1000); 760 } 761 break; 762 case DEVICEID_ATHEROS_AR8151: 763 case DEVICEID_ATHEROS_AR8151_V2: 764 case DEVICEID_ATHEROS_AR8152_B: 765 case DEVICEID_ATHEROS_AR8152_B2: 766 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 767 ALC_MII_DBG_ADDR, 0x00); 768 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 769 ALC_MII_DBG_DATA); 770 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 771 ALC_MII_DBG_DATA, val | 0x0080); 772 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 773 ALC_MII_DBG_ADDR, 0x3B); 774 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 775 ALC_MII_DBG_DATA); 776 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 777 ALC_MII_DBG_DATA, val & 0xFFF7); 778 DELAY(20); 779 break; 780 } 781 } 782 783 alc_get_macaddr_par(sc); 784 } 785 786 static void 787 alc_get_macaddr_816x(struct alc_softc *sc) 788 { 789 uint32_t reg; 790 int i, reloaded; 791 792 reloaded = 0; 793 /* Try to reload station address via TWSI. */ 794 for (i = 100; i > 0; i--) { 795 reg = CSR_READ_4(sc, ALC_SLD); 796 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 797 break; 798 DELAY(1000); 799 } 800 if (i != 0) { 801 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 802 for (i = 100; i > 0; i--) { 803 DELAY(1000); 804 reg = CSR_READ_4(sc, ALC_SLD); 805 if ((reg & SLD_START) == 0) 806 break; 807 } 808 if (i != 0) 809 reloaded++; 810 else if (bootverbose) 811 device_printf(sc->alc_dev, 812 "reloading station address via TWSI timed out!\n"); 813 } 814 815 /* Try to reload station address from EEPROM or FLASH. */ 816 if (reloaded == 0) { 817 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 818 if ((reg & (EEPROM_LD_EEPROM_EXIST | 819 EEPROM_LD_FLASH_EXIST)) != 0) { 820 for (i = 100; i > 0; i--) { 821 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 822 if ((reg & (EEPROM_LD_PROGRESS | 823 EEPROM_LD_START)) == 0) 824 break; 825 DELAY(1000); 826 } 827 if (i != 0) { 828 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 829 EEPROM_LD_START); 830 for (i = 100; i > 0; i--) { 831 DELAY(1000); 832 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 833 if ((reg & EEPROM_LD_START) == 0) 834 break; 835 } 836 } else if (bootverbose) 837 device_printf(sc->alc_dev, 838 "reloading EEPROM/FLASH timed out!\n"); 839 } 840 } 841 842 alc_get_macaddr_par(sc); 843 } 844 845 static void 846 alc_get_macaddr_par(struct alc_softc *sc) 847 { 848 uint32_t ea[2]; 849 850 ea[0] = CSR_READ_4(sc, ALC_PAR0); 851 ea[1] = CSR_READ_4(sc, ALC_PAR1); 852 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 853 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 854 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 855 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 856 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 857 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 858 } 859 860 static void 861 alc_disable_l0s_l1(struct alc_softc *sc) 862 { 863 uint32_t pmcfg; 864 865 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 866 /* Another magic from vendor. */ 867 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 868 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 869 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 870 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 871 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 872 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 873 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 874 } 875 } 876 877 static void 878 alc_phy_reset(struct alc_softc *sc) 879 { 880 881 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 882 alc_phy_reset_816x(sc); 883 else 884 alc_phy_reset_813x(sc); 885 } 886 887 static void 888 alc_phy_reset_813x(struct alc_softc *sc) 889 { 890 uint16_t data; 891 892 /* Reset magic from Linux. */ 893 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 894 CSR_READ_2(sc, ALC_GPHY_CFG); 895 DELAY(10 * 1000); 896 897 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 898 GPHY_CFG_SEL_ANA_RESET); 899 CSR_READ_2(sc, ALC_GPHY_CFG); 900 DELAY(10 * 1000); 901 902 /* DSP fixup, Vendor magic. */ 903 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 904 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 905 ALC_MII_DBG_ADDR, 0x000A); 906 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 907 ALC_MII_DBG_DATA); 908 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 909 ALC_MII_DBG_DATA, data & 0xDFFF); 910 } 911 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 912 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 913 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 914 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 915 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 916 ALC_MII_DBG_ADDR, 0x003B); 917 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_DATA); 919 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_DATA, data & 0xFFF7); 921 DELAY(20 * 1000); 922 } 923 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 924 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 925 ALC_MII_DBG_ADDR, 0x0029); 926 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_DATA, 0x929D); 928 } 929 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 930 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 931 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 932 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_ADDR, 0x0029); 935 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 936 ALC_MII_DBG_DATA, 0xB6DD); 937 } 938 939 /* Load DSP codes, vendor magic. */ 940 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 941 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 942 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 943 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 944 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 945 ALC_MII_DBG_DATA, data); 946 947 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 948 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 949 ANA_SERDES_EN_LCKDT; 950 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 951 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 952 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 953 ALC_MII_DBG_DATA, data); 954 955 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 956 ANA_LONG_CABLE_TH_100_MASK) | 957 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 958 ANA_SHORT_CABLE_TH_100_SHIFT) | 959 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 960 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 961 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 962 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 963 ALC_MII_DBG_DATA, data); 964 965 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 966 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 967 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 968 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 969 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 970 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 971 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 972 ALC_MII_DBG_DATA, data); 973 974 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 975 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 976 ANA_OEN_125M; 977 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 978 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 979 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 980 ALC_MII_DBG_DATA, data); 981 DELAY(1000); 982 983 /* Disable hibernation. */ 984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 985 0x0029); 986 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 987 ALC_MII_DBG_DATA); 988 data &= ~0x8000; 989 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 990 data); 991 992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 993 0x000B); 994 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 995 ALC_MII_DBG_DATA); 996 data &= ~0x8000; 997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 998 data); 999 } 1000 1001 static void 1002 alc_phy_reset_816x(struct alc_softc *sc) 1003 { 1004 uint32_t val; 1005 1006 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1007 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1008 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1009 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1010 val |= GPHY_CFG_SEL_ANA_RESET; 1011 #ifdef notyet 1012 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1013 #else 1014 /* Disable PHY hibernation. */ 1015 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1016 #endif 1017 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1018 DELAY(10); 1019 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1020 DELAY(800); 1021 1022 /* Vendor PHY magic. */ 1023 #ifdef notyet 1024 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1025 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1026 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1027 EXT_VDRVBIAS_DEFAULT); 1028 #else 1029 /* Disable PHY hibernation. */ 1030 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1031 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1032 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1033 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1034 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1035 #endif 1036 1037 /* XXX Disable EEE. */ 1038 val = CSR_READ_4(sc, ALC_LPI_CTL); 1039 val &= ~LPI_CTL_ENB; 1040 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1041 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1042 1043 /* PHY power saving. */ 1044 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1045 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1046 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1047 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1048 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1049 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1050 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1051 1052 /* RTL8139C, 120m issue. */ 1053 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1054 ANEG_NLP78_120M_DEFAULT); 1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1056 ANEG_S3DIG10_DEFAULT); 1057 1058 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1059 /* Turn off half amplitude. */ 1060 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1061 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1062 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1063 /* Turn off Green feature. */ 1064 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1065 val |= DBG_GREENCFG2_BP_GREEN; 1066 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1067 /* Turn off half bias. */ 1068 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1069 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1070 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1071 } 1072 } 1073 1074 static void 1075 alc_phy_down(struct alc_softc *sc) 1076 { 1077 uint32_t gphy; 1078 1079 switch (sc->alc_ident->deviceid) { 1080 case DEVICEID_ATHEROS_AR8161: 1081 case DEVICEID_ATHEROS_E2200: 1082 case DEVICEID_ATHEROS_AR8162: 1083 case DEVICEID_ATHEROS_AR8171: 1084 case DEVICEID_ATHEROS_AR8172: 1085 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1086 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1087 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1088 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1089 GPHY_CFG_SEL_ANA_RESET; 1090 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1091 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1092 break; 1093 case DEVICEID_ATHEROS_AR8151: 1094 case DEVICEID_ATHEROS_AR8151_V2: 1095 case DEVICEID_ATHEROS_AR8152_B: 1096 case DEVICEID_ATHEROS_AR8152_B2: 1097 /* 1098 * GPHY power down caused more problems on AR8151 v2.0. 1099 * When driver is reloaded after GPHY power down, 1100 * accesses to PHY/MAC registers hung the system. Only 1101 * cold boot recovered from it. I'm not sure whether 1102 * AR8151 v1.0 also requires this one though. I don't 1103 * have AR8151 v1.0 controller in hand. 1104 * The only option left is to isolate the PHY and 1105 * initiates power down the PHY which in turn saves 1106 * more power when driver is unloaded. 1107 */ 1108 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1109 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1110 break; 1111 default: 1112 /* Force PHY down. */ 1113 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1114 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1115 GPHY_CFG_PWDOWN_HW); 1116 DELAY(1000); 1117 break; 1118 } 1119 } 1120 1121 static void 1122 alc_aspm(struct alc_softc *sc, int init, int media) 1123 { 1124 1125 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1126 alc_aspm_816x(sc, init); 1127 else 1128 alc_aspm_813x(sc, media); 1129 } 1130 1131 static void 1132 alc_aspm_813x(struct alc_softc *sc, int media) 1133 { 1134 uint32_t pmcfg; 1135 uint16_t linkcfg; 1136 1137 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1138 return; 1139 1140 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1141 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1142 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1143 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1144 PCIER_LINK_CTL); 1145 else 1146 linkcfg = 0; 1147 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1148 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1149 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1150 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1151 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1152 1153 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1154 /* Disable extended sync except AR8152 B v1.0 */ 1155 linkcfg &= ~0x80; 1156 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1157 sc->alc_rev == ATHEROS_AR8152_B_V10) 1158 linkcfg |= 0x80; 1159 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1160 linkcfg); 1161 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1162 PM_CFG_HOTRST); 1163 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1164 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1165 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1166 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1167 PM_CFG_PM_REQ_TIMER_SHIFT); 1168 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1169 } 1170 1171 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1172 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1173 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1174 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1175 pmcfg |= PM_CFG_ASPM_L1_ENB; 1176 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1177 if (sc->alc_ident->deviceid == 1178 DEVICEID_ATHEROS_AR8152_B) 1179 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1180 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1181 PM_CFG_SERDES_PLL_L1_ENB | 1182 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1183 pmcfg |= PM_CFG_CLK_SWH_L1; 1184 if (media == IFM_100_TX || media == IFM_1000_T) { 1185 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1186 switch (sc->alc_ident->deviceid) { 1187 case DEVICEID_ATHEROS_AR8152_B: 1188 pmcfg |= (7 << 1189 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1190 break; 1191 case DEVICEID_ATHEROS_AR8152_B2: 1192 case DEVICEID_ATHEROS_AR8151_V2: 1193 pmcfg |= (4 << 1194 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1195 break; 1196 default: 1197 pmcfg |= (15 << 1198 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1199 break; 1200 } 1201 } 1202 } else { 1203 pmcfg |= PM_CFG_SERDES_L1_ENB | 1204 PM_CFG_SERDES_PLL_L1_ENB | 1205 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1206 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1207 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1208 } 1209 } else { 1210 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1211 PM_CFG_SERDES_PLL_L1_ENB); 1212 pmcfg |= PM_CFG_CLK_SWH_L1; 1213 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1214 pmcfg |= PM_CFG_ASPM_L1_ENB; 1215 } 1216 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1217 } 1218 1219 static void 1220 alc_aspm_816x(struct alc_softc *sc, int init) 1221 { 1222 uint32_t pmcfg; 1223 1224 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1225 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1226 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1227 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1228 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1229 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1230 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1231 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1232 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1233 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1234 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1235 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1236 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1237 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1238 (sc->alc_rev & 0x01) != 0) 1239 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1240 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1241 /* Link up, enable both L0s, L1s. */ 1242 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1243 PM_CFG_MAC_ASPM_CHK; 1244 } else { 1245 if (init != 0) 1246 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1247 PM_CFG_MAC_ASPM_CHK; 1248 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1249 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1250 } 1251 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1252 } 1253 1254 static void 1255 alc_init_pcie(struct alc_softc *sc) 1256 { 1257 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1258 uint32_t cap, ctl, val; 1259 int state; 1260 1261 /* Clear data link and flow-control protocol error. */ 1262 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1263 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1264 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1265 1266 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1267 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1268 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1269 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1270 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1271 PCIE_PHYMISC_FORCE_RCV_DET); 1272 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1273 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1274 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1275 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1276 PCIE_PHYMISC2_SERDES_TH_MASK); 1277 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1278 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1279 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1280 } 1281 /* Disable ASPM L0S and L1. */ 1282 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1283 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1284 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1285 if ((ctl & 0x08) != 0) 1286 sc->alc_rcb = DMA_CFG_RCB_128; 1287 if (bootverbose) 1288 device_printf(sc->alc_dev, "RCB %u bytes\n", 1289 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1290 state = ctl & 0x03; 1291 if (state & 0x01) 1292 sc->alc_flags |= ALC_FLAG_L0S; 1293 if (state & 0x02) 1294 sc->alc_flags |= ALC_FLAG_L1S; 1295 if (bootverbose) 1296 device_printf(sc->alc_dev, "ASPM %s %s\n", 1297 aspm_state[state], 1298 state == 0 ? "disabled" : "enabled"); 1299 alc_disable_l0s_l1(sc); 1300 } else { 1301 if (bootverbose) 1302 device_printf(sc->alc_dev, 1303 "no ASPM support\n"); 1304 } 1305 } else { 1306 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1307 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1308 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1309 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1310 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1311 (sc->alc_rev & 0x01) != 0) { 1312 if ((val & MASTER_WAKEN_25M) == 0 || 1313 (val & MASTER_CLK_SEL_DIS) == 0) { 1314 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1315 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1316 } 1317 } else { 1318 if ((val & MASTER_WAKEN_25M) == 0 || 1319 (val & MASTER_CLK_SEL_DIS) != 0) { 1320 val |= MASTER_WAKEN_25M; 1321 val &= ~MASTER_CLK_SEL_DIS; 1322 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1323 } 1324 } 1325 } 1326 alc_aspm(sc, 1, IFM_UNKNOWN); 1327 } 1328 1329 static void 1330 alc_config_msi(struct alc_softc *sc) 1331 { 1332 uint32_t ctl, mod; 1333 1334 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1335 /* 1336 * It seems interrupt moderation is controlled by 1337 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1338 * Driver uses RX interrupt moderation parameter to 1339 * program ALC_MSI_RETRANS_TIMER register. 1340 */ 1341 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1342 ctl &= ~MSI_RETRANS_TIMER_MASK; 1343 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1344 mod = ALC_USECS(sc->alc_int_rx_mod); 1345 if (mod == 0) 1346 mod = 1; 1347 ctl |= mod; 1348 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1349 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1350 MSI_RETRANS_MASK_SEL_STD); 1351 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1352 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1353 MSI_RETRANS_MASK_SEL_LINE); 1354 else 1355 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1356 } 1357 } 1358 1359 static int 1360 alc_attach(device_t dev) 1361 { 1362 struct alc_softc *sc; 1363 struct ifnet *ifp; 1364 int base, error, i, msic, msixc; 1365 uint16_t burst; 1366 1367 error = 0; 1368 sc = device_get_softc(dev); 1369 sc->alc_dev = dev; 1370 sc->alc_rev = pci_get_revid(dev); 1371 1372 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1373 MTX_DEF); 1374 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1375 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1376 sc->alc_ident = alc_find_ident(dev); 1377 1378 /* Map the device. */ 1379 pci_enable_busmaster(dev); 1380 sc->alc_res_spec = alc_res_spec_mem; 1381 sc->alc_irq_spec = alc_irq_spec_legacy; 1382 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1383 if (error != 0) { 1384 device_printf(dev, "cannot allocate memory resources.\n"); 1385 goto fail; 1386 } 1387 1388 /* Set PHY address. */ 1389 sc->alc_phyaddr = ALC_PHY_ADDR; 1390 1391 /* 1392 * One odd thing is AR8132 uses the same PHY hardware(F1 1393 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1394 * the PHY supports 1000Mbps but that's not true. The PHY 1395 * used in AR8132 can't establish gigabit link even if it 1396 * shows the same PHY model/revision number of AR8131. 1397 */ 1398 switch (sc->alc_ident->deviceid) { 1399 case DEVICEID_ATHEROS_AR8161: 1400 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1401 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1402 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1403 /* FALLTHROUGH */ 1404 case DEVICEID_ATHEROS_E2200: 1405 case DEVICEID_ATHEROS_AR8171: 1406 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1407 break; 1408 case DEVICEID_ATHEROS_AR8162: 1409 case DEVICEID_ATHEROS_AR8172: 1410 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1411 break; 1412 case DEVICEID_ATHEROS_AR8152_B: 1413 case DEVICEID_ATHEROS_AR8152_B2: 1414 sc->alc_flags |= ALC_FLAG_APS; 1415 /* FALLTHROUGH */ 1416 case DEVICEID_ATHEROS_AR8132: 1417 sc->alc_flags |= ALC_FLAG_FASTETHER; 1418 break; 1419 case DEVICEID_ATHEROS_AR8151: 1420 case DEVICEID_ATHEROS_AR8151_V2: 1421 sc->alc_flags |= ALC_FLAG_APS; 1422 /* FALLTHROUGH */ 1423 default: 1424 break; 1425 } 1426 sc->alc_flags |= ALC_FLAG_JUMBO; 1427 1428 /* 1429 * It seems that AR813x/AR815x has silicon bug for SMB. In 1430 * addition, Atheros said that enabling SMB wouldn't improve 1431 * performance. However I think it's bad to access lots of 1432 * registers to extract MAC statistics. 1433 */ 1434 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1435 /* 1436 * Don't use Tx CMB. It is known to have silicon bug. 1437 */ 1438 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1439 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1440 MASTER_CHIP_REV_SHIFT; 1441 if (bootverbose) { 1442 device_printf(dev, "PCI device revision : 0x%04x\n", 1443 sc->alc_rev); 1444 device_printf(dev, "Chip id/revision : 0x%04x\n", 1445 sc->alc_chip_rev); 1446 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1447 device_printf(dev, "AR816x revision : 0x%x\n", 1448 AR816X_REV(sc->alc_rev)); 1449 } 1450 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1451 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1452 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1453 1454 /* Initialize DMA parameters. */ 1455 sc->alc_dma_rd_burst = 0; 1456 sc->alc_dma_wr_burst = 0; 1457 sc->alc_rcb = DMA_CFG_RCB_64; 1458 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1459 sc->alc_flags |= ALC_FLAG_PCIE; 1460 sc->alc_expcap = base; 1461 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1462 sc->alc_dma_rd_burst = 1463 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1464 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1465 if (bootverbose) { 1466 device_printf(dev, "Read request size : %u bytes.\n", 1467 alc_dma_burst[sc->alc_dma_rd_burst]); 1468 device_printf(dev, "TLP payload size : %u bytes.\n", 1469 alc_dma_burst[sc->alc_dma_wr_burst]); 1470 } 1471 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1472 sc->alc_dma_rd_burst = 3; 1473 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1474 sc->alc_dma_wr_burst = 3; 1475 alc_init_pcie(sc); 1476 } 1477 1478 /* Reset PHY. */ 1479 alc_phy_reset(sc); 1480 1481 /* Reset the ethernet controller. */ 1482 alc_stop_mac(sc); 1483 alc_reset(sc); 1484 1485 /* Allocate IRQ resources. */ 1486 msixc = pci_msix_count(dev); 1487 msic = pci_msi_count(dev); 1488 if (bootverbose) { 1489 device_printf(dev, "MSIX count : %d\n", msixc); 1490 device_printf(dev, "MSI count : %d\n", msic); 1491 } 1492 if (msixc > 1) 1493 msixc = 1; 1494 if (msic > 1) 1495 msic = 1; 1496 /* 1497 * Prefer MSIX over MSI. 1498 * AR816x controller has a silicon bug that MSI interrupt 1499 * does not assert if PCIM_CMD_INTxDIS bit of command 1500 * register is set. pci(4) was taught to handle that case. 1501 */ 1502 if (msix_disable == 0 || msi_disable == 0) { 1503 if (msix_disable == 0 && msixc > 0 && 1504 pci_alloc_msix(dev, &msixc) == 0) { 1505 if (msic == 1) { 1506 device_printf(dev, 1507 "Using %d MSIX message(s).\n", msixc); 1508 sc->alc_flags |= ALC_FLAG_MSIX; 1509 sc->alc_irq_spec = alc_irq_spec_msix; 1510 } else 1511 pci_release_msi(dev); 1512 } 1513 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1514 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1515 if (msic == 1) { 1516 device_printf(dev, 1517 "Using %d MSI message(s).\n", msic); 1518 sc->alc_flags |= ALC_FLAG_MSI; 1519 sc->alc_irq_spec = alc_irq_spec_msi; 1520 } else 1521 pci_release_msi(dev); 1522 } 1523 } 1524 1525 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1526 if (error != 0) { 1527 device_printf(dev, "cannot allocate IRQ resources.\n"); 1528 goto fail; 1529 } 1530 1531 /* Create device sysctl node. */ 1532 alc_sysctl_node(sc); 1533 1534 if ((error = alc_dma_alloc(sc) != 0)) 1535 goto fail; 1536 1537 /* Load station address. */ 1538 alc_get_macaddr(sc); 1539 1540 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1541 if (ifp == NULL) { 1542 device_printf(dev, "cannot allocate ifnet structure.\n"); 1543 error = ENXIO; 1544 goto fail; 1545 } 1546 1547 ifp->if_softc = sc; 1548 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1549 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1550 ifp->if_ioctl = alc_ioctl; 1551 ifp->if_start = alc_start; 1552 ifp->if_init = alc_init; 1553 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1554 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1555 IFQ_SET_READY(&ifp->if_snd); 1556 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1557 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1558 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1559 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1560 sc->alc_flags |= ALC_FLAG_PM; 1561 sc->alc_pmcap = base; 1562 } 1563 ifp->if_capenable = ifp->if_capabilities; 1564 1565 /* Set up MII bus. */ 1566 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1567 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1568 MIIF_DOPAUSE); 1569 if (error != 0) { 1570 device_printf(dev, "attaching PHYs failed\n"); 1571 goto fail; 1572 } 1573 1574 ether_ifattach(ifp, sc->alc_eaddr); 1575 1576 /* VLAN capability setup. */ 1577 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1578 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1579 ifp->if_capenable = ifp->if_capabilities; 1580 /* 1581 * XXX 1582 * It seems enabling Tx checksum offloading makes more trouble. 1583 * Sometimes the controller does not receive any frames when 1584 * Tx checksum offloading is enabled. I'm not sure whether this 1585 * is a bug in Tx checksum offloading logic or I got broken 1586 * sample boards. To safety, don't enable Tx checksum offloading 1587 * by default but give chance to users to toggle it if they know 1588 * their controllers work without problems. 1589 * Fortunately, Tx checksum offloading for AR816x family 1590 * seems to work. 1591 */ 1592 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1593 ifp->if_capenable &= ~IFCAP_TXCSUM; 1594 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1595 } 1596 1597 /* Tell the upper layer(s) we support long frames. */ 1598 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1599 1600 /* Create local taskq. */ 1601 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1602 taskqueue_thread_enqueue, &sc->alc_tq); 1603 if (sc->alc_tq == NULL) { 1604 device_printf(dev, "could not create taskqueue.\n"); 1605 ether_ifdetach(ifp); 1606 error = ENXIO; 1607 goto fail; 1608 } 1609 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1610 device_get_nameunit(sc->alc_dev)); 1611 1612 alc_config_msi(sc); 1613 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1614 msic = ALC_MSIX_MESSAGES; 1615 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1616 msic = ALC_MSI_MESSAGES; 1617 else 1618 msic = 1; 1619 for (i = 0; i < msic; i++) { 1620 error = bus_setup_intr(dev, sc->alc_irq[i], 1621 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1622 &sc->alc_intrhand[i]); 1623 if (error != 0) 1624 break; 1625 } 1626 if (error != 0) { 1627 device_printf(dev, "could not set up interrupt handler.\n"); 1628 taskqueue_free(sc->alc_tq); 1629 sc->alc_tq = NULL; 1630 ether_ifdetach(ifp); 1631 goto fail; 1632 } 1633 1634 fail: 1635 if (error != 0) 1636 alc_detach(dev); 1637 1638 return (error); 1639 } 1640 1641 static int 1642 alc_detach(device_t dev) 1643 { 1644 struct alc_softc *sc; 1645 struct ifnet *ifp; 1646 int i, msic; 1647 1648 sc = device_get_softc(dev); 1649 1650 ifp = sc->alc_ifp; 1651 if (device_is_attached(dev)) { 1652 ether_ifdetach(ifp); 1653 ALC_LOCK(sc); 1654 alc_stop(sc); 1655 ALC_UNLOCK(sc); 1656 callout_drain(&sc->alc_tick_ch); 1657 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1658 } 1659 1660 if (sc->alc_tq != NULL) { 1661 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1662 taskqueue_free(sc->alc_tq); 1663 sc->alc_tq = NULL; 1664 } 1665 1666 if (sc->alc_miibus != NULL) { 1667 device_delete_child(dev, sc->alc_miibus); 1668 sc->alc_miibus = NULL; 1669 } 1670 bus_generic_detach(dev); 1671 alc_dma_free(sc); 1672 1673 if (ifp != NULL) { 1674 if_free(ifp); 1675 sc->alc_ifp = NULL; 1676 } 1677 1678 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1679 msic = ALC_MSIX_MESSAGES; 1680 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1681 msic = ALC_MSI_MESSAGES; 1682 else 1683 msic = 1; 1684 for (i = 0; i < msic; i++) { 1685 if (sc->alc_intrhand[i] != NULL) { 1686 bus_teardown_intr(dev, sc->alc_irq[i], 1687 sc->alc_intrhand[i]); 1688 sc->alc_intrhand[i] = NULL; 1689 } 1690 } 1691 if (sc->alc_res[0] != NULL) 1692 alc_phy_down(sc); 1693 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1694 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1695 pci_release_msi(dev); 1696 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1697 mtx_destroy(&sc->alc_mtx); 1698 1699 return (0); 1700 } 1701 1702 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1703 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1704 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1705 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1706 1707 static void 1708 alc_sysctl_node(struct alc_softc *sc) 1709 { 1710 struct sysctl_ctx_list *ctx; 1711 struct sysctl_oid_list *child, *parent; 1712 struct sysctl_oid *tree; 1713 struct alc_hw_stats *stats; 1714 int error; 1715 1716 stats = &sc->alc_stats; 1717 ctx = device_get_sysctl_ctx(sc->alc_dev); 1718 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1719 1720 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1721 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1722 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1723 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1724 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1725 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1726 /* Pull in device tunables. */ 1727 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1728 error = resource_int_value(device_get_name(sc->alc_dev), 1729 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1730 if (error == 0) { 1731 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1732 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1733 device_printf(sc->alc_dev, "int_rx_mod value out of " 1734 "range; using default: %d\n", 1735 ALC_IM_RX_TIMER_DEFAULT); 1736 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1737 } 1738 } 1739 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1740 error = resource_int_value(device_get_name(sc->alc_dev), 1741 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1742 if (error == 0) { 1743 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1744 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1745 device_printf(sc->alc_dev, "int_tx_mod value out of " 1746 "range; using default: %d\n", 1747 ALC_IM_TX_TIMER_DEFAULT); 1748 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1749 } 1750 } 1751 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1752 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1753 sysctl_hw_alc_proc_limit, "I", 1754 "max number of Rx events to process"); 1755 /* Pull in device tunables. */ 1756 sc->alc_process_limit = ALC_PROC_DEFAULT; 1757 error = resource_int_value(device_get_name(sc->alc_dev), 1758 device_get_unit(sc->alc_dev), "process_limit", 1759 &sc->alc_process_limit); 1760 if (error == 0) { 1761 if (sc->alc_process_limit < ALC_PROC_MIN || 1762 sc->alc_process_limit > ALC_PROC_MAX) { 1763 device_printf(sc->alc_dev, 1764 "process_limit value out of range; " 1765 "using default: %d\n", ALC_PROC_DEFAULT); 1766 sc->alc_process_limit = ALC_PROC_DEFAULT; 1767 } 1768 } 1769 1770 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1771 NULL, "ALC statistics"); 1772 parent = SYSCTL_CHILDREN(tree); 1773 1774 /* Rx statistics. */ 1775 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1776 NULL, "Rx MAC statistics"); 1777 child = SYSCTL_CHILDREN(tree); 1778 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1779 &stats->rx_frames, "Good frames"); 1780 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1781 &stats->rx_bcast_frames, "Good broadcast frames"); 1782 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1783 &stats->rx_mcast_frames, "Good multicast frames"); 1784 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1785 &stats->rx_pause_frames, "Pause control frames"); 1786 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1787 &stats->rx_control_frames, "Control frames"); 1788 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1789 &stats->rx_crcerrs, "CRC errors"); 1790 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1791 &stats->rx_lenerrs, "Frames with length mismatched"); 1792 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1793 &stats->rx_bytes, "Good octets"); 1794 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1795 &stats->rx_bcast_bytes, "Good broadcast octets"); 1796 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1797 &stats->rx_mcast_bytes, "Good multicast octets"); 1798 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1799 &stats->rx_runts, "Too short frames"); 1800 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1801 &stats->rx_fragments, "Fragmented frames"); 1802 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1803 &stats->rx_pkts_64, "64 bytes frames"); 1804 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1805 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1806 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1807 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1808 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1809 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1810 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1811 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1812 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1813 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1814 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1815 &stats->rx_pkts_1519_max, "1519 to max frames"); 1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1817 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1819 &stats->rx_fifo_oflows, "FIFO overflows"); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1821 &stats->rx_rrs_errs, "Return status write-back errors"); 1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1823 &stats->rx_alignerrs, "Alignment errors"); 1824 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1825 &stats->rx_pkts_filtered, 1826 "Frames dropped due to address filtering"); 1827 1828 /* Tx statistics. */ 1829 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1830 NULL, "Tx MAC statistics"); 1831 child = SYSCTL_CHILDREN(tree); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1833 &stats->tx_frames, "Good frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1835 &stats->tx_bcast_frames, "Good broadcast frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1837 &stats->tx_mcast_frames, "Good multicast frames"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1839 &stats->tx_pause_frames, "Pause control frames"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1841 &stats->tx_control_frames, "Control frames"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1843 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1845 &stats->tx_excess_defer, "Frames with derferrals"); 1846 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1847 &stats->tx_bytes, "Good octets"); 1848 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1849 &stats->tx_bcast_bytes, "Good broadcast octets"); 1850 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1851 &stats->tx_mcast_bytes, "Good multicast octets"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1853 &stats->tx_pkts_64, "64 bytes frames"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1855 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1857 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1859 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1861 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1863 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1865 &stats->tx_pkts_1519_max, "1519 to max frames"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1867 &stats->tx_single_colls, "Single collisions"); 1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1869 &stats->tx_multi_colls, "Multiple collisions"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1871 &stats->tx_late_colls, "Late collisions"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1873 &stats->tx_excess_colls, "Excessive collisions"); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1875 &stats->tx_underrun, "FIFO underruns"); 1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1877 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1878 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1879 &stats->tx_lenerrs, "Frames with length mismatched"); 1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1881 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1882 } 1883 1884 #undef ALC_SYSCTL_STAT_ADD32 1885 #undef ALC_SYSCTL_STAT_ADD64 1886 1887 struct alc_dmamap_arg { 1888 bus_addr_t alc_busaddr; 1889 }; 1890 1891 static void 1892 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1893 { 1894 struct alc_dmamap_arg *ctx; 1895 1896 if (error != 0) 1897 return; 1898 1899 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1900 1901 ctx = (struct alc_dmamap_arg *)arg; 1902 ctx->alc_busaddr = segs[0].ds_addr; 1903 } 1904 1905 /* 1906 * Normal and high Tx descriptors shares single Tx high address. 1907 * Four Rx descriptor/return rings and CMB shares the same Rx 1908 * high address. 1909 */ 1910 static int 1911 alc_check_boundary(struct alc_softc *sc) 1912 { 1913 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1914 1915 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1916 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1917 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1918 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1919 1920 /* 4GB boundary crossing is not allowed. */ 1921 if ((ALC_ADDR_HI(rx_ring_end) != 1922 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1923 (ALC_ADDR_HI(rr_ring_end) != 1924 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1925 (ALC_ADDR_HI(cmb_end) != 1926 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1927 (ALC_ADDR_HI(tx_ring_end) != 1928 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1929 return (EFBIG); 1930 /* 1931 * Make sure Rx return descriptor/Rx descriptor/CMB use 1932 * the same high address. 1933 */ 1934 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1935 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1936 return (EFBIG); 1937 1938 return (0); 1939 } 1940 1941 static int 1942 alc_dma_alloc(struct alc_softc *sc) 1943 { 1944 struct alc_txdesc *txd; 1945 struct alc_rxdesc *rxd; 1946 bus_addr_t lowaddr; 1947 struct alc_dmamap_arg ctx; 1948 int error, i; 1949 1950 lowaddr = BUS_SPACE_MAXADDR; 1951 again: 1952 /* Create parent DMA tag. */ 1953 error = bus_dma_tag_create( 1954 bus_get_dma_tag(sc->alc_dev), /* parent */ 1955 1, 0, /* alignment, boundary */ 1956 lowaddr, /* lowaddr */ 1957 BUS_SPACE_MAXADDR, /* highaddr */ 1958 NULL, NULL, /* filter, filterarg */ 1959 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1960 0, /* nsegments */ 1961 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1962 0, /* flags */ 1963 NULL, NULL, /* lockfunc, lockarg */ 1964 &sc->alc_cdata.alc_parent_tag); 1965 if (error != 0) { 1966 device_printf(sc->alc_dev, 1967 "could not create parent DMA tag.\n"); 1968 goto fail; 1969 } 1970 1971 /* Create DMA tag for Tx descriptor ring. */ 1972 error = bus_dma_tag_create( 1973 sc->alc_cdata.alc_parent_tag, /* parent */ 1974 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1975 BUS_SPACE_MAXADDR, /* lowaddr */ 1976 BUS_SPACE_MAXADDR, /* highaddr */ 1977 NULL, NULL, /* filter, filterarg */ 1978 ALC_TX_RING_SZ, /* maxsize */ 1979 1, /* nsegments */ 1980 ALC_TX_RING_SZ, /* maxsegsize */ 1981 0, /* flags */ 1982 NULL, NULL, /* lockfunc, lockarg */ 1983 &sc->alc_cdata.alc_tx_ring_tag); 1984 if (error != 0) { 1985 device_printf(sc->alc_dev, 1986 "could not create Tx ring DMA tag.\n"); 1987 goto fail; 1988 } 1989 1990 /* Create DMA tag for Rx free descriptor ring. */ 1991 error = bus_dma_tag_create( 1992 sc->alc_cdata.alc_parent_tag, /* parent */ 1993 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1994 BUS_SPACE_MAXADDR, /* lowaddr */ 1995 BUS_SPACE_MAXADDR, /* highaddr */ 1996 NULL, NULL, /* filter, filterarg */ 1997 ALC_RX_RING_SZ, /* maxsize */ 1998 1, /* nsegments */ 1999 ALC_RX_RING_SZ, /* maxsegsize */ 2000 0, /* flags */ 2001 NULL, NULL, /* lockfunc, lockarg */ 2002 &sc->alc_cdata.alc_rx_ring_tag); 2003 if (error != 0) { 2004 device_printf(sc->alc_dev, 2005 "could not create Rx ring DMA tag.\n"); 2006 goto fail; 2007 } 2008 /* Create DMA tag for Rx return descriptor ring. */ 2009 error = bus_dma_tag_create( 2010 sc->alc_cdata.alc_parent_tag, /* parent */ 2011 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2012 BUS_SPACE_MAXADDR, /* lowaddr */ 2013 BUS_SPACE_MAXADDR, /* highaddr */ 2014 NULL, NULL, /* filter, filterarg */ 2015 ALC_RR_RING_SZ, /* maxsize */ 2016 1, /* nsegments */ 2017 ALC_RR_RING_SZ, /* maxsegsize */ 2018 0, /* flags */ 2019 NULL, NULL, /* lockfunc, lockarg */ 2020 &sc->alc_cdata.alc_rr_ring_tag); 2021 if (error != 0) { 2022 device_printf(sc->alc_dev, 2023 "could not create Rx return ring DMA tag.\n"); 2024 goto fail; 2025 } 2026 2027 /* Create DMA tag for coalescing message block. */ 2028 error = bus_dma_tag_create( 2029 sc->alc_cdata.alc_parent_tag, /* parent */ 2030 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2031 BUS_SPACE_MAXADDR, /* lowaddr */ 2032 BUS_SPACE_MAXADDR, /* highaddr */ 2033 NULL, NULL, /* filter, filterarg */ 2034 ALC_CMB_SZ, /* maxsize */ 2035 1, /* nsegments */ 2036 ALC_CMB_SZ, /* maxsegsize */ 2037 0, /* flags */ 2038 NULL, NULL, /* lockfunc, lockarg */ 2039 &sc->alc_cdata.alc_cmb_tag); 2040 if (error != 0) { 2041 device_printf(sc->alc_dev, 2042 "could not create CMB DMA tag.\n"); 2043 goto fail; 2044 } 2045 /* Create DMA tag for status message block. */ 2046 error = bus_dma_tag_create( 2047 sc->alc_cdata.alc_parent_tag, /* parent */ 2048 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2049 BUS_SPACE_MAXADDR, /* lowaddr */ 2050 BUS_SPACE_MAXADDR, /* highaddr */ 2051 NULL, NULL, /* filter, filterarg */ 2052 ALC_SMB_SZ, /* maxsize */ 2053 1, /* nsegments */ 2054 ALC_SMB_SZ, /* maxsegsize */ 2055 0, /* flags */ 2056 NULL, NULL, /* lockfunc, lockarg */ 2057 &sc->alc_cdata.alc_smb_tag); 2058 if (error != 0) { 2059 device_printf(sc->alc_dev, 2060 "could not create SMB DMA tag.\n"); 2061 goto fail; 2062 } 2063 2064 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2065 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2066 (void **)&sc->alc_rdata.alc_tx_ring, 2067 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2068 &sc->alc_cdata.alc_tx_ring_map); 2069 if (error != 0) { 2070 device_printf(sc->alc_dev, 2071 "could not allocate DMA'able memory for Tx ring.\n"); 2072 goto fail; 2073 } 2074 ctx.alc_busaddr = 0; 2075 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2076 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2077 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2078 if (error != 0 || ctx.alc_busaddr == 0) { 2079 device_printf(sc->alc_dev, 2080 "could not load DMA'able memory for Tx ring.\n"); 2081 goto fail; 2082 } 2083 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2084 2085 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2086 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2087 (void **)&sc->alc_rdata.alc_rx_ring, 2088 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2089 &sc->alc_cdata.alc_rx_ring_map); 2090 if (error != 0) { 2091 device_printf(sc->alc_dev, 2092 "could not allocate DMA'able memory for Rx ring.\n"); 2093 goto fail; 2094 } 2095 ctx.alc_busaddr = 0; 2096 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2097 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2098 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2099 if (error != 0 || ctx.alc_busaddr == 0) { 2100 device_printf(sc->alc_dev, 2101 "could not load DMA'able memory for Rx ring.\n"); 2102 goto fail; 2103 } 2104 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2105 2106 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2107 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2108 (void **)&sc->alc_rdata.alc_rr_ring, 2109 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2110 &sc->alc_cdata.alc_rr_ring_map); 2111 if (error != 0) { 2112 device_printf(sc->alc_dev, 2113 "could not allocate DMA'able memory for Rx return ring.\n"); 2114 goto fail; 2115 } 2116 ctx.alc_busaddr = 0; 2117 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2118 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2119 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2120 if (error != 0 || ctx.alc_busaddr == 0) { 2121 device_printf(sc->alc_dev, 2122 "could not load DMA'able memory for Tx ring.\n"); 2123 goto fail; 2124 } 2125 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2126 2127 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2128 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2129 (void **)&sc->alc_rdata.alc_cmb, 2130 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2131 &sc->alc_cdata.alc_cmb_map); 2132 if (error != 0) { 2133 device_printf(sc->alc_dev, 2134 "could not allocate DMA'able memory for CMB.\n"); 2135 goto fail; 2136 } 2137 ctx.alc_busaddr = 0; 2138 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2139 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2140 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2141 if (error != 0 || ctx.alc_busaddr == 0) { 2142 device_printf(sc->alc_dev, 2143 "could not load DMA'able memory for CMB.\n"); 2144 goto fail; 2145 } 2146 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2147 2148 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2149 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2150 (void **)&sc->alc_rdata.alc_smb, 2151 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2152 &sc->alc_cdata.alc_smb_map); 2153 if (error != 0) { 2154 device_printf(sc->alc_dev, 2155 "could not allocate DMA'able memory for SMB.\n"); 2156 goto fail; 2157 } 2158 ctx.alc_busaddr = 0; 2159 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2160 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2161 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2162 if (error != 0 || ctx.alc_busaddr == 0) { 2163 device_printf(sc->alc_dev, 2164 "could not load DMA'able memory for CMB.\n"); 2165 goto fail; 2166 } 2167 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2168 2169 /* Make sure we've not crossed 4GB boundary. */ 2170 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2171 (error = alc_check_boundary(sc)) != 0) { 2172 device_printf(sc->alc_dev, "4GB boundary crossed, " 2173 "switching to 32bit DMA addressing mode.\n"); 2174 alc_dma_free(sc); 2175 /* 2176 * Limit max allowable DMA address space to 32bit 2177 * and try again. 2178 */ 2179 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2180 goto again; 2181 } 2182 2183 /* 2184 * Create Tx buffer parent tag. 2185 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2186 * so it needs separate parent DMA tag as parent DMA address 2187 * space could be restricted to be within 32bit address space 2188 * by 4GB boundary crossing. 2189 */ 2190 error = bus_dma_tag_create( 2191 bus_get_dma_tag(sc->alc_dev), /* parent */ 2192 1, 0, /* alignment, boundary */ 2193 BUS_SPACE_MAXADDR, /* lowaddr */ 2194 BUS_SPACE_MAXADDR, /* highaddr */ 2195 NULL, NULL, /* filter, filterarg */ 2196 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2197 0, /* nsegments */ 2198 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2199 0, /* flags */ 2200 NULL, NULL, /* lockfunc, lockarg */ 2201 &sc->alc_cdata.alc_buffer_tag); 2202 if (error != 0) { 2203 device_printf(sc->alc_dev, 2204 "could not create parent buffer DMA tag.\n"); 2205 goto fail; 2206 } 2207 2208 /* Create DMA tag for Tx buffers. */ 2209 error = bus_dma_tag_create( 2210 sc->alc_cdata.alc_buffer_tag, /* parent */ 2211 1, 0, /* alignment, boundary */ 2212 BUS_SPACE_MAXADDR, /* lowaddr */ 2213 BUS_SPACE_MAXADDR, /* highaddr */ 2214 NULL, NULL, /* filter, filterarg */ 2215 ALC_TSO_MAXSIZE, /* maxsize */ 2216 ALC_MAXTXSEGS, /* nsegments */ 2217 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2218 0, /* flags */ 2219 NULL, NULL, /* lockfunc, lockarg */ 2220 &sc->alc_cdata.alc_tx_tag); 2221 if (error != 0) { 2222 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2223 goto fail; 2224 } 2225 2226 /* Create DMA tag for Rx buffers. */ 2227 error = bus_dma_tag_create( 2228 sc->alc_cdata.alc_buffer_tag, /* parent */ 2229 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2230 BUS_SPACE_MAXADDR, /* lowaddr */ 2231 BUS_SPACE_MAXADDR, /* highaddr */ 2232 NULL, NULL, /* filter, filterarg */ 2233 MCLBYTES, /* maxsize */ 2234 1, /* nsegments */ 2235 MCLBYTES, /* maxsegsize */ 2236 0, /* flags */ 2237 NULL, NULL, /* lockfunc, lockarg */ 2238 &sc->alc_cdata.alc_rx_tag); 2239 if (error != 0) { 2240 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2241 goto fail; 2242 } 2243 /* Create DMA maps for Tx buffers. */ 2244 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2245 txd = &sc->alc_cdata.alc_txdesc[i]; 2246 txd->tx_m = NULL; 2247 txd->tx_dmamap = NULL; 2248 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2249 &txd->tx_dmamap); 2250 if (error != 0) { 2251 device_printf(sc->alc_dev, 2252 "could not create Tx dmamap.\n"); 2253 goto fail; 2254 } 2255 } 2256 /* Create DMA maps for Rx buffers. */ 2257 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2258 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2259 device_printf(sc->alc_dev, 2260 "could not create spare Rx dmamap.\n"); 2261 goto fail; 2262 } 2263 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2264 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2265 rxd->rx_m = NULL; 2266 rxd->rx_dmamap = NULL; 2267 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2268 &rxd->rx_dmamap); 2269 if (error != 0) { 2270 device_printf(sc->alc_dev, 2271 "could not create Rx dmamap.\n"); 2272 goto fail; 2273 } 2274 } 2275 2276 fail: 2277 return (error); 2278 } 2279 2280 static void 2281 alc_dma_free(struct alc_softc *sc) 2282 { 2283 struct alc_txdesc *txd; 2284 struct alc_rxdesc *rxd; 2285 int i; 2286 2287 /* Tx buffers. */ 2288 if (sc->alc_cdata.alc_tx_tag != NULL) { 2289 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2290 txd = &sc->alc_cdata.alc_txdesc[i]; 2291 if (txd->tx_dmamap != NULL) { 2292 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2293 txd->tx_dmamap); 2294 txd->tx_dmamap = NULL; 2295 } 2296 } 2297 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2298 sc->alc_cdata.alc_tx_tag = NULL; 2299 } 2300 /* Rx buffers */ 2301 if (sc->alc_cdata.alc_rx_tag != NULL) { 2302 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2303 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2304 if (rxd->rx_dmamap != NULL) { 2305 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2306 rxd->rx_dmamap); 2307 rxd->rx_dmamap = NULL; 2308 } 2309 } 2310 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2311 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2312 sc->alc_cdata.alc_rx_sparemap); 2313 sc->alc_cdata.alc_rx_sparemap = NULL; 2314 } 2315 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2316 sc->alc_cdata.alc_rx_tag = NULL; 2317 } 2318 /* Tx descriptor ring. */ 2319 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2320 if (sc->alc_cdata.alc_tx_ring_map != NULL) 2321 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2322 sc->alc_cdata.alc_tx_ring_map); 2323 if (sc->alc_cdata.alc_tx_ring_map != NULL && 2324 sc->alc_rdata.alc_tx_ring != NULL) 2325 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2326 sc->alc_rdata.alc_tx_ring, 2327 sc->alc_cdata.alc_tx_ring_map); 2328 sc->alc_rdata.alc_tx_ring = NULL; 2329 sc->alc_cdata.alc_tx_ring_map = NULL; 2330 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2331 sc->alc_cdata.alc_tx_ring_tag = NULL; 2332 } 2333 /* Rx ring. */ 2334 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2335 if (sc->alc_cdata.alc_rx_ring_map != NULL) 2336 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2337 sc->alc_cdata.alc_rx_ring_map); 2338 if (sc->alc_cdata.alc_rx_ring_map != NULL && 2339 sc->alc_rdata.alc_rx_ring != NULL) 2340 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2341 sc->alc_rdata.alc_rx_ring, 2342 sc->alc_cdata.alc_rx_ring_map); 2343 sc->alc_rdata.alc_rx_ring = NULL; 2344 sc->alc_cdata.alc_rx_ring_map = NULL; 2345 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2346 sc->alc_cdata.alc_rx_ring_tag = NULL; 2347 } 2348 /* Rx return ring. */ 2349 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2350 if (sc->alc_cdata.alc_rr_ring_map != NULL) 2351 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2352 sc->alc_cdata.alc_rr_ring_map); 2353 if (sc->alc_cdata.alc_rr_ring_map != NULL && 2354 sc->alc_rdata.alc_rr_ring != NULL) 2355 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2356 sc->alc_rdata.alc_rr_ring, 2357 sc->alc_cdata.alc_rr_ring_map); 2358 sc->alc_rdata.alc_rr_ring = NULL; 2359 sc->alc_cdata.alc_rr_ring_map = NULL; 2360 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2361 sc->alc_cdata.alc_rr_ring_tag = NULL; 2362 } 2363 /* CMB block */ 2364 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2365 if (sc->alc_cdata.alc_cmb_map != NULL) 2366 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2367 sc->alc_cdata.alc_cmb_map); 2368 if (sc->alc_cdata.alc_cmb_map != NULL && 2369 sc->alc_rdata.alc_cmb != NULL) 2370 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2371 sc->alc_rdata.alc_cmb, 2372 sc->alc_cdata.alc_cmb_map); 2373 sc->alc_rdata.alc_cmb = NULL; 2374 sc->alc_cdata.alc_cmb_map = NULL; 2375 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2376 sc->alc_cdata.alc_cmb_tag = NULL; 2377 } 2378 /* SMB block */ 2379 if (sc->alc_cdata.alc_smb_tag != NULL) { 2380 if (sc->alc_cdata.alc_smb_map != NULL) 2381 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2382 sc->alc_cdata.alc_smb_map); 2383 if (sc->alc_cdata.alc_smb_map != NULL && 2384 sc->alc_rdata.alc_smb != NULL) 2385 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2386 sc->alc_rdata.alc_smb, 2387 sc->alc_cdata.alc_smb_map); 2388 sc->alc_rdata.alc_smb = NULL; 2389 sc->alc_cdata.alc_smb_map = NULL; 2390 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2391 sc->alc_cdata.alc_smb_tag = NULL; 2392 } 2393 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2394 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2395 sc->alc_cdata.alc_buffer_tag = NULL; 2396 } 2397 if (sc->alc_cdata.alc_parent_tag != NULL) { 2398 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2399 sc->alc_cdata.alc_parent_tag = NULL; 2400 } 2401 } 2402 2403 static int 2404 alc_shutdown(device_t dev) 2405 { 2406 2407 return (alc_suspend(dev)); 2408 } 2409 2410 /* 2411 * Note, this driver resets the link speed to 10/100Mbps by 2412 * restarting auto-negotiation in suspend/shutdown phase but we 2413 * don't know whether that auto-negotiation would succeed or not 2414 * as driver has no control after powering off/suspend operation. 2415 * If the renegotiation fail WOL may not work. Running at 1Gbps 2416 * will draw more power than 375mA at 3.3V which is specified in 2417 * PCI specification and that would result in complete 2418 * shutdowning power to ethernet controller. 2419 * 2420 * TODO 2421 * Save current negotiated media speed/duplex/flow-control to 2422 * softc and restore the same link again after resuming. PHY 2423 * handling such as power down/resetting to 100Mbps may be better 2424 * handled in suspend method in phy driver. 2425 */ 2426 static void 2427 alc_setlinkspeed(struct alc_softc *sc) 2428 { 2429 struct mii_data *mii; 2430 int aneg, i; 2431 2432 mii = device_get_softc(sc->alc_miibus); 2433 mii_pollstat(mii); 2434 aneg = 0; 2435 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2436 (IFM_ACTIVE | IFM_AVALID)) { 2437 switch IFM_SUBTYPE(mii->mii_media_active) { 2438 case IFM_10_T: 2439 case IFM_100_TX: 2440 return; 2441 case IFM_1000_T: 2442 aneg++; 2443 break; 2444 default: 2445 break; 2446 } 2447 } 2448 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2449 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2450 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2451 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2452 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2453 DELAY(1000); 2454 if (aneg != 0) { 2455 /* 2456 * Poll link state until alc(4) get a 10/100Mbps link. 2457 */ 2458 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2459 mii_pollstat(mii); 2460 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2461 == (IFM_ACTIVE | IFM_AVALID)) { 2462 switch (IFM_SUBTYPE( 2463 mii->mii_media_active)) { 2464 case IFM_10_T: 2465 case IFM_100_TX: 2466 alc_mac_config(sc); 2467 return; 2468 default: 2469 break; 2470 } 2471 } 2472 ALC_UNLOCK(sc); 2473 pause("alclnk", hz); 2474 ALC_LOCK(sc); 2475 } 2476 if (i == MII_ANEGTICKS_GIGE) 2477 device_printf(sc->alc_dev, 2478 "establishing a link failed, WOL may not work!"); 2479 } 2480 /* 2481 * No link, force MAC to have 100Mbps, full-duplex link. 2482 * This is the last resort and may/may not work. 2483 */ 2484 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2485 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2486 alc_mac_config(sc); 2487 } 2488 2489 static void 2490 alc_setwol(struct alc_softc *sc) 2491 { 2492 2493 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2494 alc_setwol_816x(sc); 2495 else 2496 alc_setwol_813x(sc); 2497 } 2498 2499 static void 2500 alc_setwol_813x(struct alc_softc *sc) 2501 { 2502 struct ifnet *ifp; 2503 uint32_t reg, pmcs; 2504 uint16_t pmstat; 2505 2506 ALC_LOCK_ASSERT(sc); 2507 2508 alc_disable_l0s_l1(sc); 2509 ifp = sc->alc_ifp; 2510 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2511 /* Disable WOL. */ 2512 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2513 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2514 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2515 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2516 /* Force PHY power down. */ 2517 alc_phy_down(sc); 2518 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2519 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2520 return; 2521 } 2522 2523 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2524 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2525 alc_setlinkspeed(sc); 2526 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2527 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2528 } 2529 2530 pmcs = 0; 2531 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2532 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2533 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2534 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2535 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2536 MAC_CFG_BCAST); 2537 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2538 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2539 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2540 reg |= MAC_CFG_RX_ENB; 2541 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2542 2543 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2544 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2545 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2546 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2547 /* WOL disabled, PHY power down. */ 2548 alc_phy_down(sc); 2549 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2550 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2551 } 2552 /* Request PME. */ 2553 pmstat = pci_read_config(sc->alc_dev, 2554 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2555 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2556 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2557 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2558 pci_write_config(sc->alc_dev, 2559 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2560 } 2561 2562 static void 2563 alc_setwol_816x(struct alc_softc *sc) 2564 { 2565 struct ifnet *ifp; 2566 uint32_t gphy, mac, master, pmcs, reg; 2567 uint16_t pmstat; 2568 2569 ALC_LOCK_ASSERT(sc); 2570 2571 ifp = sc->alc_ifp; 2572 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2573 master &= ~MASTER_CLK_SEL_DIS; 2574 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2575 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2576 GPHY_CFG_PHY_PLL_ON); 2577 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2578 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2579 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2580 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2581 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2582 } else { 2583 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2584 gphy |= GPHY_CFG_EXT_RESET; 2585 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2586 alc_setlinkspeed(sc); 2587 } 2588 pmcs = 0; 2589 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2590 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2591 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2592 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2593 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2594 MAC_CFG_BCAST); 2595 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2596 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2597 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2598 mac |= MAC_CFG_RX_ENB; 2599 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2600 ANEG_S3DIG10_SL); 2601 } 2602 2603 /* Enable OSC. */ 2604 reg = CSR_READ_4(sc, ALC_MISC); 2605 reg &= ~MISC_INTNLOSC_OPEN; 2606 CSR_WRITE_4(sc, ALC_MISC, reg); 2607 reg |= MISC_INTNLOSC_OPEN; 2608 CSR_WRITE_4(sc, ALC_MISC, reg); 2609 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2610 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2611 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2612 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2613 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2614 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2615 2616 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2617 /* Request PME. */ 2618 pmstat = pci_read_config(sc->alc_dev, 2619 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2620 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2621 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2622 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2623 pci_write_config(sc->alc_dev, 2624 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2625 } 2626 } 2627 2628 static int 2629 alc_suspend(device_t dev) 2630 { 2631 struct alc_softc *sc; 2632 2633 sc = device_get_softc(dev); 2634 2635 ALC_LOCK(sc); 2636 alc_stop(sc); 2637 alc_setwol(sc); 2638 ALC_UNLOCK(sc); 2639 2640 return (0); 2641 } 2642 2643 static int 2644 alc_resume(device_t dev) 2645 { 2646 struct alc_softc *sc; 2647 struct ifnet *ifp; 2648 uint16_t pmstat; 2649 2650 sc = device_get_softc(dev); 2651 2652 ALC_LOCK(sc); 2653 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2654 /* Disable PME and clear PME status. */ 2655 pmstat = pci_read_config(sc->alc_dev, 2656 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2657 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2658 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2659 pci_write_config(sc->alc_dev, 2660 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2661 } 2662 } 2663 /* Reset PHY. */ 2664 alc_phy_reset(sc); 2665 ifp = sc->alc_ifp; 2666 if ((ifp->if_flags & IFF_UP) != 0) { 2667 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2668 alc_init_locked(sc); 2669 } 2670 ALC_UNLOCK(sc); 2671 2672 return (0); 2673 } 2674 2675 static int 2676 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2677 { 2678 struct alc_txdesc *txd, *txd_last; 2679 struct tx_desc *desc; 2680 struct mbuf *m; 2681 struct ip *ip; 2682 struct tcphdr *tcp; 2683 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2684 bus_dmamap_t map; 2685 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2686 int error, idx, nsegs, prod; 2687 2688 ALC_LOCK_ASSERT(sc); 2689 2690 M_ASSERTPKTHDR((*m_head)); 2691 2692 m = *m_head; 2693 ip = NULL; 2694 tcp = NULL; 2695 ip_off = poff = 0; 2696 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2697 /* 2698 * AR81[3567]x requires offset of TCP/UDP header in its 2699 * Tx descriptor to perform Tx checksum offloading. TSO 2700 * also requires TCP header offset and modification of 2701 * IP/TCP header. This kind of operation takes many CPU 2702 * cycles on FreeBSD so fast host CPU is required to get 2703 * smooth TSO performance. 2704 */ 2705 struct ether_header *eh; 2706 2707 if (M_WRITABLE(m) == 0) { 2708 /* Get a writable copy. */ 2709 m = m_dup(*m_head, M_NOWAIT); 2710 /* Release original mbufs. */ 2711 m_freem(*m_head); 2712 if (m == NULL) { 2713 *m_head = NULL; 2714 return (ENOBUFS); 2715 } 2716 *m_head = m; 2717 } 2718 2719 ip_off = sizeof(struct ether_header); 2720 m = m_pullup(m, ip_off); 2721 if (m == NULL) { 2722 *m_head = NULL; 2723 return (ENOBUFS); 2724 } 2725 eh = mtod(m, struct ether_header *); 2726 /* 2727 * Check if hardware VLAN insertion is off. 2728 * Additional check for LLC/SNAP frame? 2729 */ 2730 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2731 ip_off = sizeof(struct ether_vlan_header); 2732 m = m_pullup(m, ip_off); 2733 if (m == NULL) { 2734 *m_head = NULL; 2735 return (ENOBUFS); 2736 } 2737 } 2738 m = m_pullup(m, ip_off + sizeof(struct ip)); 2739 if (m == NULL) { 2740 *m_head = NULL; 2741 return (ENOBUFS); 2742 } 2743 ip = (struct ip *)(mtod(m, char *) + ip_off); 2744 poff = ip_off + (ip->ip_hl << 2); 2745 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2746 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2747 if (m == NULL) { 2748 *m_head = NULL; 2749 return (ENOBUFS); 2750 } 2751 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2752 m = m_pullup(m, poff + (tcp->th_off << 2)); 2753 if (m == NULL) { 2754 *m_head = NULL; 2755 return (ENOBUFS); 2756 } 2757 /* 2758 * Due to strict adherence of Microsoft NDIS 2759 * Large Send specification, hardware expects 2760 * a pseudo TCP checksum inserted by upper 2761 * stack. Unfortunately the pseudo TCP 2762 * checksum that NDIS refers to does not include 2763 * TCP payload length so driver should recompute 2764 * the pseudo checksum here. Hopefully this 2765 * wouldn't be much burden on modern CPUs. 2766 * 2767 * Reset IP checksum and recompute TCP pseudo 2768 * checksum as NDIS specification said. 2769 */ 2770 ip = (struct ip *)(mtod(m, char *) + ip_off); 2771 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2772 ip->ip_sum = 0; 2773 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2774 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2775 } 2776 *m_head = m; 2777 } 2778 2779 prod = sc->alc_cdata.alc_tx_prod; 2780 txd = &sc->alc_cdata.alc_txdesc[prod]; 2781 txd_last = txd; 2782 map = txd->tx_dmamap; 2783 2784 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2785 *m_head, txsegs, &nsegs, 0); 2786 if (error == EFBIG) { 2787 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2788 if (m == NULL) { 2789 m_freem(*m_head); 2790 *m_head = NULL; 2791 return (ENOMEM); 2792 } 2793 *m_head = m; 2794 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2795 *m_head, txsegs, &nsegs, 0); 2796 if (error != 0) { 2797 m_freem(*m_head); 2798 *m_head = NULL; 2799 return (error); 2800 } 2801 } else if (error != 0) 2802 return (error); 2803 if (nsegs == 0) { 2804 m_freem(*m_head); 2805 *m_head = NULL; 2806 return (EIO); 2807 } 2808 2809 /* Check descriptor overrun. */ 2810 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2811 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2812 return (ENOBUFS); 2813 } 2814 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2815 2816 m = *m_head; 2817 cflags = TD_ETHERNET; 2818 vtag = 0; 2819 desc = NULL; 2820 idx = 0; 2821 /* Configure VLAN hardware tag insertion. */ 2822 if ((m->m_flags & M_VLANTAG) != 0) { 2823 vtag = htons(m->m_pkthdr.ether_vtag); 2824 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2825 cflags |= TD_INS_VLAN_TAG; 2826 } 2827 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2828 /* Request TSO and set MSS. */ 2829 cflags |= TD_TSO | TD_TSO_DESCV1; 2830 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2831 TD_MSS_MASK; 2832 /* Set TCP header offset. */ 2833 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2834 TD_TCPHDR_OFFSET_MASK; 2835 /* 2836 * AR81[3567]x requires the first buffer should 2837 * only hold IP/TCP header data. Payload should 2838 * be handled in other descriptors. 2839 */ 2840 hdrlen = poff + (tcp->th_off << 2); 2841 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2842 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2843 desc->flags = htole32(cflags); 2844 desc->addr = htole64(txsegs[0].ds_addr); 2845 sc->alc_cdata.alc_tx_cnt++; 2846 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2847 if (m->m_len - hdrlen > 0) { 2848 /* Handle remaining payload of the first fragment. */ 2849 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2850 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2851 vtag)); 2852 desc->flags = htole32(cflags); 2853 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2854 sc->alc_cdata.alc_tx_cnt++; 2855 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2856 } 2857 /* Handle remaining fragments. */ 2858 idx = 1; 2859 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2860 /* Configure Tx checksum offload. */ 2861 #ifdef ALC_USE_CUSTOM_CSUM 2862 cflags |= TD_CUSTOM_CSUM; 2863 /* Set checksum start offset. */ 2864 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2865 TD_PLOAD_OFFSET_MASK; 2866 /* Set checksum insertion position of TCP/UDP. */ 2867 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2868 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2869 #else 2870 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2871 cflags |= TD_IPCSUM; 2872 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2873 cflags |= TD_TCPCSUM; 2874 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2875 cflags |= TD_UDPCSUM; 2876 /* Set TCP/UDP header offset. */ 2877 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2878 TD_L4HDR_OFFSET_MASK; 2879 #endif 2880 } 2881 for (; idx < nsegs; idx++) { 2882 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2883 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2884 desc->flags = htole32(cflags); 2885 desc->addr = htole64(txsegs[idx].ds_addr); 2886 sc->alc_cdata.alc_tx_cnt++; 2887 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2888 } 2889 /* Update producer index. */ 2890 sc->alc_cdata.alc_tx_prod = prod; 2891 2892 /* Finally set EOP on the last descriptor. */ 2893 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2894 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2895 desc->flags |= htole32(TD_EOP); 2896 2897 /* Swap dmamap of the first and the last. */ 2898 txd = &sc->alc_cdata.alc_txdesc[prod]; 2899 map = txd_last->tx_dmamap; 2900 txd_last->tx_dmamap = txd->tx_dmamap; 2901 txd->tx_dmamap = map; 2902 txd->tx_m = m; 2903 2904 return (0); 2905 } 2906 2907 static void 2908 alc_start(struct ifnet *ifp) 2909 { 2910 struct alc_softc *sc; 2911 2912 sc = ifp->if_softc; 2913 ALC_LOCK(sc); 2914 alc_start_locked(ifp); 2915 ALC_UNLOCK(sc); 2916 } 2917 2918 static void 2919 alc_start_locked(struct ifnet *ifp) 2920 { 2921 struct alc_softc *sc; 2922 struct mbuf *m_head; 2923 int enq; 2924 2925 sc = ifp->if_softc; 2926 2927 ALC_LOCK_ASSERT(sc); 2928 2929 /* Reclaim transmitted frames. */ 2930 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2931 alc_txeof(sc); 2932 2933 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2934 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2935 return; 2936 2937 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2938 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2939 if (m_head == NULL) 2940 break; 2941 /* 2942 * Pack the data into the transmit ring. If we 2943 * don't have room, set the OACTIVE flag and wait 2944 * for the NIC to drain the ring. 2945 */ 2946 if (alc_encap(sc, &m_head)) { 2947 if (m_head == NULL) 2948 break; 2949 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2950 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2951 break; 2952 } 2953 2954 enq++; 2955 /* 2956 * If there's a BPF listener, bounce a copy of this frame 2957 * to him. 2958 */ 2959 ETHER_BPF_MTAP(ifp, m_head); 2960 } 2961 2962 if (enq > 0) { 2963 /* Sync descriptors. */ 2964 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2965 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2966 /* Kick. Assume we're using normal Tx priority queue. */ 2967 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2968 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2969 (uint16_t)sc->alc_cdata.alc_tx_prod); 2970 else 2971 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2972 (sc->alc_cdata.alc_tx_prod << 2973 MBOX_TD_PROD_LO_IDX_SHIFT) & 2974 MBOX_TD_PROD_LO_IDX_MASK); 2975 /* Set a timeout in case the chip goes out to lunch. */ 2976 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2977 } 2978 } 2979 2980 static void 2981 alc_watchdog(struct alc_softc *sc) 2982 { 2983 struct ifnet *ifp; 2984 2985 ALC_LOCK_ASSERT(sc); 2986 2987 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2988 return; 2989 2990 ifp = sc->alc_ifp; 2991 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2992 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2993 ifp->if_oerrors++; 2994 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2995 alc_init_locked(sc); 2996 return; 2997 } 2998 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2999 ifp->if_oerrors++; 3000 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3001 alc_init_locked(sc); 3002 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3003 alc_start_locked(ifp); 3004 } 3005 3006 static int 3007 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3008 { 3009 struct alc_softc *sc; 3010 struct ifreq *ifr; 3011 struct mii_data *mii; 3012 int error, mask; 3013 3014 sc = ifp->if_softc; 3015 ifr = (struct ifreq *)data; 3016 error = 0; 3017 switch (cmd) { 3018 case SIOCSIFMTU: 3019 if (ifr->ifr_mtu < ETHERMIN || 3020 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3021 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3022 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3023 ifr->ifr_mtu > ETHERMTU)) 3024 error = EINVAL; 3025 else if (ifp->if_mtu != ifr->ifr_mtu) { 3026 ALC_LOCK(sc); 3027 ifp->if_mtu = ifr->ifr_mtu; 3028 /* AR81[3567]x has 13 bits MSS field. */ 3029 if (ifp->if_mtu > ALC_TSO_MTU && 3030 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3031 ifp->if_capenable &= ~IFCAP_TSO4; 3032 ifp->if_hwassist &= ~CSUM_TSO; 3033 VLAN_CAPABILITIES(ifp); 3034 } 3035 ALC_UNLOCK(sc); 3036 } 3037 break; 3038 case SIOCSIFFLAGS: 3039 ALC_LOCK(sc); 3040 if ((ifp->if_flags & IFF_UP) != 0) { 3041 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3042 ((ifp->if_flags ^ sc->alc_if_flags) & 3043 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3044 alc_rxfilter(sc); 3045 else 3046 alc_init_locked(sc); 3047 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3048 alc_stop(sc); 3049 sc->alc_if_flags = ifp->if_flags; 3050 ALC_UNLOCK(sc); 3051 break; 3052 case SIOCADDMULTI: 3053 case SIOCDELMULTI: 3054 ALC_LOCK(sc); 3055 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3056 alc_rxfilter(sc); 3057 ALC_UNLOCK(sc); 3058 break; 3059 case SIOCSIFMEDIA: 3060 case SIOCGIFMEDIA: 3061 mii = device_get_softc(sc->alc_miibus); 3062 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3063 break; 3064 case SIOCSIFCAP: 3065 ALC_LOCK(sc); 3066 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3067 if ((mask & IFCAP_TXCSUM) != 0 && 3068 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3069 ifp->if_capenable ^= IFCAP_TXCSUM; 3070 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3071 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3072 else 3073 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3074 } 3075 if ((mask & IFCAP_TSO4) != 0 && 3076 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3077 ifp->if_capenable ^= IFCAP_TSO4; 3078 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3079 /* AR81[3567]x has 13 bits MSS field. */ 3080 if (ifp->if_mtu > ALC_TSO_MTU) { 3081 ifp->if_capenable &= ~IFCAP_TSO4; 3082 ifp->if_hwassist &= ~CSUM_TSO; 3083 } else 3084 ifp->if_hwassist |= CSUM_TSO; 3085 } else 3086 ifp->if_hwassist &= ~CSUM_TSO; 3087 } 3088 if ((mask & IFCAP_WOL_MCAST) != 0 && 3089 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3090 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3091 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3092 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3093 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3094 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3095 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3096 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3097 alc_rxvlan(sc); 3098 } 3099 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3100 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3101 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3102 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3103 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3104 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3105 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3106 ifp->if_capenable &= 3107 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3108 ALC_UNLOCK(sc); 3109 VLAN_CAPABILITIES(ifp); 3110 break; 3111 default: 3112 error = ether_ioctl(ifp, cmd, data); 3113 break; 3114 } 3115 3116 return (error); 3117 } 3118 3119 static void 3120 alc_mac_config(struct alc_softc *sc) 3121 { 3122 struct mii_data *mii; 3123 uint32_t reg; 3124 3125 ALC_LOCK_ASSERT(sc); 3126 3127 mii = device_get_softc(sc->alc_miibus); 3128 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3129 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3130 MAC_CFG_SPEED_MASK); 3131 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3132 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3133 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3134 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3135 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3136 /* Reprogram MAC with resolved speed/duplex. */ 3137 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3138 case IFM_10_T: 3139 case IFM_100_TX: 3140 reg |= MAC_CFG_SPEED_10_100; 3141 break; 3142 case IFM_1000_T: 3143 reg |= MAC_CFG_SPEED_1000; 3144 break; 3145 } 3146 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3147 reg |= MAC_CFG_FULL_DUPLEX; 3148 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3149 reg |= MAC_CFG_TX_FC; 3150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3151 reg |= MAC_CFG_RX_FC; 3152 } 3153 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3154 } 3155 3156 static void 3157 alc_stats_clear(struct alc_softc *sc) 3158 { 3159 struct smb sb, *smb; 3160 uint32_t *reg; 3161 int i; 3162 3163 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3164 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3165 sc->alc_cdata.alc_smb_map, 3166 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3167 smb = sc->alc_rdata.alc_smb; 3168 /* Update done, clear. */ 3169 smb->updated = 0; 3170 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3171 sc->alc_cdata.alc_smb_map, 3172 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3173 } else { 3174 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3175 reg++) { 3176 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3177 i += sizeof(uint32_t); 3178 } 3179 /* Read Tx statistics. */ 3180 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3181 reg++) { 3182 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3183 i += sizeof(uint32_t); 3184 } 3185 } 3186 } 3187 3188 static void 3189 alc_stats_update(struct alc_softc *sc) 3190 { 3191 struct alc_hw_stats *stat; 3192 struct smb sb, *smb; 3193 struct ifnet *ifp; 3194 uint32_t *reg; 3195 int i; 3196 3197 ALC_LOCK_ASSERT(sc); 3198 3199 ifp = sc->alc_ifp; 3200 stat = &sc->alc_stats; 3201 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3202 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3203 sc->alc_cdata.alc_smb_map, 3204 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3205 smb = sc->alc_rdata.alc_smb; 3206 if (smb->updated == 0) 3207 return; 3208 } else { 3209 smb = &sb; 3210 /* Read Rx statistics. */ 3211 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3212 reg++) { 3213 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3214 i += sizeof(uint32_t); 3215 } 3216 /* Read Tx statistics. */ 3217 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3218 reg++) { 3219 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3220 i += sizeof(uint32_t); 3221 } 3222 } 3223 3224 /* Rx stats. */ 3225 stat->rx_frames += smb->rx_frames; 3226 stat->rx_bcast_frames += smb->rx_bcast_frames; 3227 stat->rx_mcast_frames += smb->rx_mcast_frames; 3228 stat->rx_pause_frames += smb->rx_pause_frames; 3229 stat->rx_control_frames += smb->rx_control_frames; 3230 stat->rx_crcerrs += smb->rx_crcerrs; 3231 stat->rx_lenerrs += smb->rx_lenerrs; 3232 stat->rx_bytes += smb->rx_bytes; 3233 stat->rx_runts += smb->rx_runts; 3234 stat->rx_fragments += smb->rx_fragments; 3235 stat->rx_pkts_64 += smb->rx_pkts_64; 3236 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3237 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3238 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3239 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3240 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3241 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3242 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3243 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3244 stat->rx_rrs_errs += smb->rx_rrs_errs; 3245 stat->rx_alignerrs += smb->rx_alignerrs; 3246 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3247 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3248 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3249 3250 /* Tx stats. */ 3251 stat->tx_frames += smb->tx_frames; 3252 stat->tx_bcast_frames += smb->tx_bcast_frames; 3253 stat->tx_mcast_frames += smb->tx_mcast_frames; 3254 stat->tx_pause_frames += smb->tx_pause_frames; 3255 stat->tx_excess_defer += smb->tx_excess_defer; 3256 stat->tx_control_frames += smb->tx_control_frames; 3257 stat->tx_deferred += smb->tx_deferred; 3258 stat->tx_bytes += smb->tx_bytes; 3259 stat->tx_pkts_64 += smb->tx_pkts_64; 3260 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3261 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3262 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3263 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3264 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3265 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3266 stat->tx_single_colls += smb->tx_single_colls; 3267 stat->tx_multi_colls += smb->tx_multi_colls; 3268 stat->tx_late_colls += smb->tx_late_colls; 3269 stat->tx_excess_colls += smb->tx_excess_colls; 3270 stat->tx_underrun += smb->tx_underrun; 3271 stat->tx_desc_underrun += smb->tx_desc_underrun; 3272 stat->tx_lenerrs += smb->tx_lenerrs; 3273 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3274 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3275 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3276 3277 /* Update counters in ifnet. */ 3278 ifp->if_opackets += smb->tx_frames; 3279 3280 ifp->if_collisions += smb->tx_single_colls + 3281 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3282 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 3283 3284 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 3285 smb->tx_underrun + smb->tx_pkts_truncated; 3286 3287 ifp->if_ipackets += smb->rx_frames; 3288 3289 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 3290 smb->rx_runts + smb->rx_pkts_truncated + 3291 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3292 smb->rx_alignerrs; 3293 3294 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3295 /* Update done, clear. */ 3296 smb->updated = 0; 3297 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3298 sc->alc_cdata.alc_smb_map, 3299 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3300 } 3301 } 3302 3303 static int 3304 alc_intr(void *arg) 3305 { 3306 struct alc_softc *sc; 3307 uint32_t status; 3308 3309 sc = (struct alc_softc *)arg; 3310 3311 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3312 if ((status & ALC_INTRS) == 0) 3313 return (FILTER_STRAY); 3314 /* Disable interrupts. */ 3315 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3316 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3317 3318 return (FILTER_HANDLED); 3319 } 3320 3321 static void 3322 alc_int_task(void *arg, int pending) 3323 { 3324 struct alc_softc *sc; 3325 struct ifnet *ifp; 3326 uint32_t status; 3327 int more; 3328 3329 sc = (struct alc_softc *)arg; 3330 ifp = sc->alc_ifp; 3331 3332 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3333 ALC_LOCK(sc); 3334 if (sc->alc_morework != 0) { 3335 sc->alc_morework = 0; 3336 status |= INTR_RX_PKT; 3337 } 3338 if ((status & ALC_INTRS) == 0) 3339 goto done; 3340 3341 /* Acknowledge interrupts but still disable interrupts. */ 3342 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3343 3344 more = 0; 3345 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3346 if ((status & INTR_RX_PKT) != 0) { 3347 more = alc_rxintr(sc, sc->alc_process_limit); 3348 if (more == EAGAIN) 3349 sc->alc_morework = 1; 3350 else if (more == EIO) { 3351 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3352 alc_init_locked(sc); 3353 ALC_UNLOCK(sc); 3354 return; 3355 } 3356 } 3357 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3358 INTR_TXQ_TO_RST)) != 0) { 3359 if ((status & INTR_DMA_RD_TO_RST) != 0) 3360 device_printf(sc->alc_dev, 3361 "DMA read error! -- resetting\n"); 3362 if ((status & INTR_DMA_WR_TO_RST) != 0) 3363 device_printf(sc->alc_dev, 3364 "DMA write error! -- resetting\n"); 3365 if ((status & INTR_TXQ_TO_RST) != 0) 3366 device_printf(sc->alc_dev, 3367 "TxQ reset! -- resetting\n"); 3368 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3369 alc_init_locked(sc); 3370 ALC_UNLOCK(sc); 3371 return; 3372 } 3373 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3374 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3375 alc_start_locked(ifp); 3376 } 3377 3378 if (more == EAGAIN || 3379 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3380 ALC_UNLOCK(sc); 3381 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3382 return; 3383 } 3384 3385 done: 3386 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3387 /* Re-enable interrupts if we're running. */ 3388 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3389 } 3390 ALC_UNLOCK(sc); 3391 } 3392 3393 static void 3394 alc_txeof(struct alc_softc *sc) 3395 { 3396 struct ifnet *ifp; 3397 struct alc_txdesc *txd; 3398 uint32_t cons, prod; 3399 int prog; 3400 3401 ALC_LOCK_ASSERT(sc); 3402 3403 ifp = sc->alc_ifp; 3404 3405 if (sc->alc_cdata.alc_tx_cnt == 0) 3406 return; 3407 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3408 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3409 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3410 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3411 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3412 prod = sc->alc_rdata.alc_cmb->cons; 3413 } else { 3414 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3415 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3416 else { 3417 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3418 /* Assume we're using normal Tx priority queue. */ 3419 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3420 MBOX_TD_CONS_LO_IDX_SHIFT; 3421 } 3422 } 3423 cons = sc->alc_cdata.alc_tx_cons; 3424 /* 3425 * Go through our Tx list and free mbufs for those 3426 * frames which have been transmitted. 3427 */ 3428 for (prog = 0; cons != prod; prog++, 3429 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3430 if (sc->alc_cdata.alc_tx_cnt <= 0) 3431 break; 3432 prog++; 3433 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3434 sc->alc_cdata.alc_tx_cnt--; 3435 txd = &sc->alc_cdata.alc_txdesc[cons]; 3436 if (txd->tx_m != NULL) { 3437 /* Reclaim transmitted mbufs. */ 3438 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3439 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3440 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3441 txd->tx_dmamap); 3442 m_freem(txd->tx_m); 3443 txd->tx_m = NULL; 3444 } 3445 } 3446 3447 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3448 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3449 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3450 sc->alc_cdata.alc_tx_cons = cons; 3451 /* 3452 * Unarm watchdog timer only when there is no pending 3453 * frames in Tx queue. 3454 */ 3455 if (sc->alc_cdata.alc_tx_cnt == 0) 3456 sc->alc_watchdog_timer = 0; 3457 } 3458 3459 static int 3460 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3461 { 3462 struct mbuf *m; 3463 bus_dma_segment_t segs[1]; 3464 bus_dmamap_t map; 3465 int nsegs; 3466 3467 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3468 if (m == NULL) 3469 return (ENOBUFS); 3470 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3471 #ifndef __NO_STRICT_ALIGNMENT 3472 m_adj(m, sizeof(uint64_t)); 3473 #endif 3474 3475 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3476 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3477 m_freem(m); 3478 return (ENOBUFS); 3479 } 3480 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3481 3482 if (rxd->rx_m != NULL) { 3483 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3484 BUS_DMASYNC_POSTREAD); 3485 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3486 } 3487 map = rxd->rx_dmamap; 3488 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3489 sc->alc_cdata.alc_rx_sparemap = map; 3490 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3491 BUS_DMASYNC_PREREAD); 3492 rxd->rx_m = m; 3493 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3494 return (0); 3495 } 3496 3497 static int 3498 alc_rxintr(struct alc_softc *sc, int count) 3499 { 3500 struct ifnet *ifp; 3501 struct rx_rdesc *rrd; 3502 uint32_t nsegs, status; 3503 int rr_cons, prog; 3504 3505 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3506 sc->alc_cdata.alc_rr_ring_map, 3507 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3508 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3509 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3510 rr_cons = sc->alc_cdata.alc_rr_cons; 3511 ifp = sc->alc_ifp; 3512 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3513 if (count-- <= 0) 3514 break; 3515 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3516 status = le32toh(rrd->status); 3517 if ((status & RRD_VALID) == 0) 3518 break; 3519 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3520 if (nsegs == 0) { 3521 /* This should not happen! */ 3522 device_printf(sc->alc_dev, 3523 "unexpected segment count -- resetting\n"); 3524 return (EIO); 3525 } 3526 alc_rxeof(sc, rrd); 3527 /* Clear Rx return status. */ 3528 rrd->status = 0; 3529 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3530 sc->alc_cdata.alc_rx_cons += nsegs; 3531 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3532 prog += nsegs; 3533 } 3534 3535 if (prog > 0) { 3536 /* Update the consumer index. */ 3537 sc->alc_cdata.alc_rr_cons = rr_cons; 3538 /* Sync Rx return descriptors. */ 3539 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3540 sc->alc_cdata.alc_rr_ring_map, 3541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3542 /* 3543 * Sync updated Rx descriptors such that controller see 3544 * modified buffer addresses. 3545 */ 3546 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3547 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3548 /* 3549 * Let controller know availability of new Rx buffers. 3550 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3551 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3552 * only when Rx buffer pre-fetching is required. In 3553 * addition we already set ALC_RX_RD_FREE_THRESH to 3554 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3555 * it still seems that pre-fetching needs more 3556 * experimentation. 3557 */ 3558 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3559 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3560 (uint16_t)sc->alc_cdata.alc_rx_cons); 3561 else 3562 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3563 sc->alc_cdata.alc_rx_cons); 3564 } 3565 3566 return (count > 0 ? 0 : EAGAIN); 3567 } 3568 3569 #ifndef __NO_STRICT_ALIGNMENT 3570 static struct mbuf * 3571 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3572 { 3573 struct mbuf *n; 3574 int i; 3575 uint16_t *src, *dst; 3576 3577 src = mtod(m, uint16_t *); 3578 dst = src - 3; 3579 3580 if (m->m_next == NULL) { 3581 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3582 *dst++ = *src++; 3583 m->m_data -= 6; 3584 return (m); 3585 } 3586 /* 3587 * Append a new mbuf to received mbuf chain and copy ethernet 3588 * header from the mbuf chain. This can save lots of CPU 3589 * cycles for jumbo frame. 3590 */ 3591 MGETHDR(n, M_NOWAIT, MT_DATA); 3592 if (n == NULL) { 3593 ifp->if_iqdrops++; 3594 m_freem(m); 3595 return (NULL); 3596 } 3597 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3598 m->m_data += ETHER_HDR_LEN; 3599 m->m_len -= ETHER_HDR_LEN; 3600 n->m_len = ETHER_HDR_LEN; 3601 M_MOVE_PKTHDR(n, m); 3602 n->m_next = m; 3603 return (n); 3604 } 3605 #endif 3606 3607 /* Receive a frame. */ 3608 static void 3609 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3610 { 3611 struct alc_rxdesc *rxd; 3612 struct ifnet *ifp; 3613 struct mbuf *mp, *m; 3614 uint32_t rdinfo, status, vtag; 3615 int count, nsegs, rx_cons; 3616 3617 ifp = sc->alc_ifp; 3618 status = le32toh(rrd->status); 3619 rdinfo = le32toh(rrd->rdinfo); 3620 rx_cons = RRD_RD_IDX(rdinfo); 3621 nsegs = RRD_RD_CNT(rdinfo); 3622 3623 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3624 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3625 /* 3626 * We want to pass the following frames to upper 3627 * layer regardless of error status of Rx return 3628 * ring. 3629 * 3630 * o IP/TCP/UDP checksum is bad. 3631 * o frame length and protocol specific length 3632 * does not match. 3633 * 3634 * Force network stack compute checksum for 3635 * errored frames. 3636 */ 3637 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3638 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3639 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3640 return; 3641 } 3642 3643 for (count = 0; count < nsegs; count++, 3644 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3645 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3646 mp = rxd->rx_m; 3647 /* Add a new receive buffer to the ring. */ 3648 if (alc_newbuf(sc, rxd) != 0) { 3649 ifp->if_iqdrops++; 3650 /* Reuse Rx buffers. */ 3651 if (sc->alc_cdata.alc_rxhead != NULL) 3652 m_freem(sc->alc_cdata.alc_rxhead); 3653 break; 3654 } 3655 3656 /* 3657 * Assume we've received a full sized frame. 3658 * Actual size is fixed when we encounter the end of 3659 * multi-segmented frame. 3660 */ 3661 mp->m_len = sc->alc_buf_size; 3662 3663 /* Chain received mbufs. */ 3664 if (sc->alc_cdata.alc_rxhead == NULL) { 3665 sc->alc_cdata.alc_rxhead = mp; 3666 sc->alc_cdata.alc_rxtail = mp; 3667 } else { 3668 mp->m_flags &= ~M_PKTHDR; 3669 sc->alc_cdata.alc_rxprev_tail = 3670 sc->alc_cdata.alc_rxtail; 3671 sc->alc_cdata.alc_rxtail->m_next = mp; 3672 sc->alc_cdata.alc_rxtail = mp; 3673 } 3674 3675 if (count == nsegs - 1) { 3676 /* Last desc. for this frame. */ 3677 m = sc->alc_cdata.alc_rxhead; 3678 m->m_flags |= M_PKTHDR; 3679 /* 3680 * It seems that L1C/L2C controller has no way 3681 * to tell hardware to strip CRC bytes. 3682 */ 3683 m->m_pkthdr.len = 3684 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3685 if (nsegs > 1) { 3686 /* Set last mbuf size. */ 3687 mp->m_len = sc->alc_cdata.alc_rxlen - 3688 (nsegs - 1) * sc->alc_buf_size; 3689 /* Remove the CRC bytes in chained mbufs. */ 3690 if (mp->m_len <= ETHER_CRC_LEN) { 3691 sc->alc_cdata.alc_rxtail = 3692 sc->alc_cdata.alc_rxprev_tail; 3693 sc->alc_cdata.alc_rxtail->m_len -= 3694 (ETHER_CRC_LEN - mp->m_len); 3695 sc->alc_cdata.alc_rxtail->m_next = NULL; 3696 m_freem(mp); 3697 } else { 3698 mp->m_len -= ETHER_CRC_LEN; 3699 } 3700 } else 3701 m->m_len = m->m_pkthdr.len; 3702 m->m_pkthdr.rcvif = ifp; 3703 /* 3704 * Due to hardware bugs, Rx checksum offloading 3705 * was intentionally disabled. 3706 */ 3707 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3708 (status & RRD_VLAN_TAG) != 0) { 3709 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3710 m->m_pkthdr.ether_vtag = ntohs(vtag); 3711 m->m_flags |= M_VLANTAG; 3712 } 3713 #ifndef __NO_STRICT_ALIGNMENT 3714 m = alc_fixup_rx(ifp, m); 3715 if (m != NULL) 3716 #endif 3717 { 3718 /* Pass it on. */ 3719 ALC_UNLOCK(sc); 3720 (*ifp->if_input)(ifp, m); 3721 ALC_LOCK(sc); 3722 } 3723 } 3724 } 3725 /* Reset mbuf chains. */ 3726 ALC_RXCHAIN_RESET(sc); 3727 } 3728 3729 static void 3730 alc_tick(void *arg) 3731 { 3732 struct alc_softc *sc; 3733 struct mii_data *mii; 3734 3735 sc = (struct alc_softc *)arg; 3736 3737 ALC_LOCK_ASSERT(sc); 3738 3739 mii = device_get_softc(sc->alc_miibus); 3740 mii_tick(mii); 3741 alc_stats_update(sc); 3742 /* 3743 * alc(4) does not rely on Tx completion interrupts to reclaim 3744 * transferred buffers. Instead Tx completion interrupts are 3745 * used to hint for scheduling Tx task. So it's necessary to 3746 * release transmitted buffers by kicking Tx completion 3747 * handler. This limits the maximum reclamation delay to a hz. 3748 */ 3749 alc_txeof(sc); 3750 alc_watchdog(sc); 3751 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3752 } 3753 3754 static void 3755 alc_osc_reset(struct alc_softc *sc) 3756 { 3757 uint32_t reg; 3758 3759 reg = CSR_READ_4(sc, ALC_MISC3); 3760 reg &= ~MISC3_25M_BY_SW; 3761 reg |= MISC3_25M_NOTO_INTNL; 3762 CSR_WRITE_4(sc, ALC_MISC3, reg); 3763 3764 reg = CSR_READ_4(sc, ALC_MISC); 3765 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3766 /* 3767 * Restore over-current protection default value. 3768 * This value could be reset by MAC reset. 3769 */ 3770 reg &= ~MISC_PSW_OCP_MASK; 3771 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3772 reg &= ~MISC_INTNLOSC_OPEN; 3773 CSR_WRITE_4(sc, ALC_MISC, reg); 3774 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3775 reg = CSR_READ_4(sc, ALC_MISC2); 3776 reg &= ~MISC2_CALB_START; 3777 CSR_WRITE_4(sc, ALC_MISC2, reg); 3778 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3779 3780 } else { 3781 reg &= ~MISC_INTNLOSC_OPEN; 3782 /* Disable isolate for revision A devices. */ 3783 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3784 reg &= ~MISC_ISO_ENB; 3785 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3786 CSR_WRITE_4(sc, ALC_MISC, reg); 3787 } 3788 3789 DELAY(20); 3790 } 3791 3792 static void 3793 alc_reset(struct alc_softc *sc) 3794 { 3795 uint32_t pmcfg, reg; 3796 int i; 3797 3798 pmcfg = 0; 3799 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3800 /* Reset workaround. */ 3801 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3802 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3803 (sc->alc_rev & 0x01) != 0) { 3804 /* Disable L0s/L1s before reset. */ 3805 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3806 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3807 != 0) { 3808 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3809 PM_CFG_ASPM_L1_ENB); 3810 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3811 } 3812 } 3813 } 3814 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3815 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3816 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3817 3818 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3819 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3820 DELAY(10); 3821 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3822 break; 3823 } 3824 if (i == 0) 3825 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3826 } 3827 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3828 DELAY(10); 3829 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3830 break; 3831 } 3832 if (i == 0) 3833 device_printf(sc->alc_dev, "master reset timeout!\n"); 3834 3835 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3836 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3837 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3838 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3839 break; 3840 DELAY(10); 3841 } 3842 if (i == 0) 3843 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3844 3845 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3846 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3847 (sc->alc_rev & 0x01) != 0) { 3848 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3849 reg |= MASTER_CLK_SEL_DIS; 3850 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3851 /* Restore L0s/L1s config. */ 3852 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3853 != 0) 3854 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3855 } 3856 3857 alc_osc_reset(sc); 3858 reg = CSR_READ_4(sc, ALC_MISC3); 3859 reg &= ~MISC3_25M_BY_SW; 3860 reg |= MISC3_25M_NOTO_INTNL; 3861 CSR_WRITE_4(sc, ALC_MISC3, reg); 3862 reg = CSR_READ_4(sc, ALC_MISC); 3863 reg &= ~MISC_INTNLOSC_OPEN; 3864 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3865 reg &= ~MISC_ISO_ENB; 3866 CSR_WRITE_4(sc, ALC_MISC, reg); 3867 DELAY(20); 3868 } 3869 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3870 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3871 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3872 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3873 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3874 SERDES_PHY_CLK_SLOWDOWN); 3875 } 3876 3877 static void 3878 alc_init(void *xsc) 3879 { 3880 struct alc_softc *sc; 3881 3882 sc = (struct alc_softc *)xsc; 3883 ALC_LOCK(sc); 3884 alc_init_locked(sc); 3885 ALC_UNLOCK(sc); 3886 } 3887 3888 static void 3889 alc_init_locked(struct alc_softc *sc) 3890 { 3891 struct ifnet *ifp; 3892 struct mii_data *mii; 3893 uint8_t eaddr[ETHER_ADDR_LEN]; 3894 bus_addr_t paddr; 3895 uint32_t reg, rxf_hi, rxf_lo; 3896 3897 ALC_LOCK_ASSERT(sc); 3898 3899 ifp = sc->alc_ifp; 3900 mii = device_get_softc(sc->alc_miibus); 3901 3902 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3903 return; 3904 /* 3905 * Cancel any pending I/O. 3906 */ 3907 alc_stop(sc); 3908 /* 3909 * Reset the chip to a known state. 3910 */ 3911 alc_reset(sc); 3912 3913 /* Initialize Rx descriptors. */ 3914 if (alc_init_rx_ring(sc) != 0) { 3915 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3916 alc_stop(sc); 3917 return; 3918 } 3919 alc_init_rr_ring(sc); 3920 alc_init_tx_ring(sc); 3921 alc_init_cmb(sc); 3922 alc_init_smb(sc); 3923 3924 /* Enable all clocks. */ 3925 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3926 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3927 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3928 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3929 CLK_GATING_RXMAC_ENB); 3930 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3931 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3932 IDLE_DECISN_TIMER_DEFAULT_1MS); 3933 } else 3934 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3935 3936 /* Reprogram the station address. */ 3937 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3938 CSR_WRITE_4(sc, ALC_PAR0, 3939 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3940 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3941 /* 3942 * Clear WOL status and disable all WOL feature as WOL 3943 * would interfere Rx operation under normal environments. 3944 */ 3945 CSR_READ_4(sc, ALC_WOL_CFG); 3946 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3947 /* Set Tx descriptor base addresses. */ 3948 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3949 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3950 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3951 /* We don't use high priority ring. */ 3952 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3953 /* Set Tx descriptor counter. */ 3954 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3955 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3956 /* Set Rx descriptor base addresses. */ 3957 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3958 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3959 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3960 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3961 /* We use one Rx ring. */ 3962 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3963 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3964 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3965 } 3966 /* Set Rx descriptor counter. */ 3967 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3968 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3969 3970 /* 3971 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3972 * if it do not fit the buffer size. Rx return descriptor holds 3973 * a counter that indicates how many fragments were made by the 3974 * hardware. The buffer size should be multiple of 8 bytes. 3975 * Since hardware has limit on the size of buffer size, always 3976 * use the maximum value. 3977 * For strict-alignment architectures make sure to reduce buffer 3978 * size by 8 bytes to make room for alignment fixup. 3979 */ 3980 #ifndef __NO_STRICT_ALIGNMENT 3981 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3982 #else 3983 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3984 #endif 3985 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3986 3987 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3988 /* Set Rx return descriptor base addresses. */ 3989 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3990 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3991 /* We use one Rx return ring. */ 3992 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3993 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3994 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3995 } 3996 /* Set Rx return descriptor counter. */ 3997 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3998 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3999 paddr = sc->alc_rdata.alc_cmb_paddr; 4000 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4001 paddr = sc->alc_rdata.alc_smb_paddr; 4002 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4003 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4004 4005 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4006 /* Reconfigure SRAM - Vendor magic. */ 4007 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4008 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4009 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4010 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4011 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4012 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4013 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4014 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4015 } 4016 4017 /* Tell hardware that we're ready to load DMA blocks. */ 4018 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4019 4020 /* Configure interrupt moderation timer. */ 4021 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4022 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4023 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4024 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4025 /* 4026 * We don't want to automatic interrupt clear as task queue 4027 * for the interrupt should know interrupt status. 4028 */ 4029 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4030 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4031 reg |= MASTER_SA_TIMER_ENB; 4032 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4033 reg |= MASTER_IM_RX_TIMER_ENB; 4034 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4035 ALC_USECS(sc->alc_int_tx_mod) != 0) 4036 reg |= MASTER_IM_TX_TIMER_ENB; 4037 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4038 /* 4039 * Disable interrupt re-trigger timer. We don't want automatic 4040 * re-triggering of un-ACKed interrupts. 4041 */ 4042 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4043 /* Configure CMB. */ 4044 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4045 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4046 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4047 ALC_USECS(sc->alc_int_tx_mod)); 4048 } else { 4049 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4050 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4051 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4052 } else 4053 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4054 } 4055 /* 4056 * Hardware can be configured to issue SMB interrupt based 4057 * on programmed interval. Since there is a callout that is 4058 * invoked for every hz in driver we use that instead of 4059 * relying on periodic SMB interrupt. 4060 */ 4061 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4062 /* Clear MAC statistics. */ 4063 alc_stats_clear(sc); 4064 4065 /* 4066 * Always use maximum frame size that controller can support. 4067 * Otherwise received frames that has larger frame length 4068 * than alc(4) MTU would be silently dropped in hardware. This 4069 * would make path-MTU discovery hard as sender wouldn't get 4070 * any responses from receiver. alc(4) supports 4071 * multi-fragmented frames on Rx path so it has no issue on 4072 * assembling fragmented frames. Using maximum frame size also 4073 * removes the need to reinitialize hardware when interface 4074 * MTU configuration was changed. 4075 * 4076 * Be conservative in what you do, be liberal in what you 4077 * accept from others - RFC 793. 4078 */ 4079 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4080 4081 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4082 /* Disable header split(?) */ 4083 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4084 4085 /* Configure IPG/IFG parameters. */ 4086 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4087 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4088 IPG_IFG_IPGT_MASK) | 4089 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4090 IPG_IFG_MIFG_MASK) | 4091 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4092 IPG_IFG_IPG1_MASK) | 4093 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4094 IPG_IFG_IPG2_MASK)); 4095 /* Set parameters for half-duplex media. */ 4096 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4097 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4098 HDPX_CFG_LCOL_MASK) | 4099 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4100 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4101 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4102 HDPX_CFG_ABEBT_MASK) | 4103 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4104 HDPX_CFG_JAMIPG_MASK)); 4105 } 4106 4107 /* 4108 * Set TSO/checksum offload threshold. For frames that is 4109 * larger than this threshold, hardware wouldn't do 4110 * TSO/checksum offloading. 4111 */ 4112 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4113 TSO_OFFLOAD_THRESH_MASK; 4114 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4115 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4116 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4117 /* Configure TxQ. */ 4118 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4119 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4120 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4121 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4122 reg >>= 1; 4123 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4124 TXQ_CFG_TD_BURST_MASK; 4125 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4126 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4127 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4128 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4129 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4130 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4131 HQTD_CFG_BURST_ENB); 4132 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4133 reg = WRR_PRI_RESTRICT_NONE; 4134 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4135 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4136 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4137 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4138 CSR_WRITE_4(sc, ALC_WRR, reg); 4139 } else { 4140 /* Configure Rx free descriptor pre-fetching. */ 4141 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4142 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4143 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4144 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4145 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4146 } 4147 4148 /* 4149 * Configure flow control parameters. 4150 * XON : 80% of Rx FIFO 4151 * XOFF : 30% of Rx FIFO 4152 */ 4153 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4154 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4155 reg &= SRAM_RX_FIFO_LEN_MASK; 4156 reg *= 8; 4157 if (reg > 8 * 1024) 4158 reg -= RX_FIFO_PAUSE_816X_RSVD; 4159 else 4160 reg -= RX_BUF_SIZE_MAX; 4161 reg /= 8; 4162 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4163 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4164 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4165 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4166 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4167 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4168 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4169 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4170 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4171 rxf_hi = (reg * 8) / 10; 4172 rxf_lo = (reg * 3) / 10; 4173 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4174 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4175 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4176 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4177 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4178 } 4179 4180 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4181 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4182 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4183 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4184 } 4185 4186 /* Configure RxQ. */ 4187 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4188 RXQ_CFG_RD_BURST_MASK; 4189 reg |= RXQ_CFG_RSS_MODE_DIS; 4190 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4191 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4192 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4193 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4194 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4195 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4196 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 4197 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4198 4199 /* Configure DMA parameters. */ 4200 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4201 reg |= sc->alc_rcb; 4202 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4203 reg |= DMA_CFG_CMB_ENB; 4204 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4205 reg |= DMA_CFG_SMB_ENB; 4206 else 4207 reg |= DMA_CFG_SMB_DIS; 4208 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4209 DMA_CFG_RD_BURST_SHIFT; 4210 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4211 DMA_CFG_WR_BURST_SHIFT; 4212 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4213 DMA_CFG_RD_DELAY_CNT_MASK; 4214 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4215 DMA_CFG_WR_DELAY_CNT_MASK; 4216 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4217 switch (AR816X_REV(sc->alc_rev)) { 4218 case AR816X_REV_A0: 4219 case AR816X_REV_A1: 4220 reg |= DMA_CFG_RD_CHNL_SEL_1; 4221 break; 4222 case AR816X_REV_B0: 4223 /* FALLTHROUGH */ 4224 default: 4225 reg |= DMA_CFG_RD_CHNL_SEL_3; 4226 break; 4227 } 4228 } 4229 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4230 4231 /* 4232 * Configure Tx/Rx MACs. 4233 * - Auto-padding for short frames. 4234 * - Enable CRC generation. 4235 * Actual reconfiguration of MAC for resolved speed/duplex 4236 * is followed after detection of link establishment. 4237 * AR813x/AR815x always does checksum computation regardless 4238 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4239 * have bug in protocol field in Rx return structure so 4240 * these controllers can't handle fragmented frames. Disable 4241 * Rx checksum offloading until there is a newer controller 4242 * that has sane implementation. 4243 */ 4244 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4245 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4246 MAC_CFG_PREAMBLE_MASK); 4247 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4248 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4249 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4250 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4251 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4252 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4253 reg |= MAC_CFG_SPEED_10_100; 4254 else 4255 reg |= MAC_CFG_SPEED_1000; 4256 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4257 4258 /* Set up the receive filter. */ 4259 alc_rxfilter(sc); 4260 alc_rxvlan(sc); 4261 4262 /* Acknowledge all pending interrupts and clear it. */ 4263 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4264 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4265 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4266 4267 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4268 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4269 4270 sc->alc_flags &= ~ALC_FLAG_LINK; 4271 /* Switch to the current media. */ 4272 alc_mediachange_locked(sc); 4273 4274 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4275 } 4276 4277 static void 4278 alc_stop(struct alc_softc *sc) 4279 { 4280 struct ifnet *ifp; 4281 struct alc_txdesc *txd; 4282 struct alc_rxdesc *rxd; 4283 uint32_t reg; 4284 int i; 4285 4286 ALC_LOCK_ASSERT(sc); 4287 /* 4288 * Mark the interface down and cancel the watchdog timer. 4289 */ 4290 ifp = sc->alc_ifp; 4291 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4292 sc->alc_flags &= ~ALC_FLAG_LINK; 4293 callout_stop(&sc->alc_tick_ch); 4294 sc->alc_watchdog_timer = 0; 4295 alc_stats_update(sc); 4296 /* Disable interrupts. */ 4297 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4298 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4299 /* Disable DMA. */ 4300 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4301 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4302 reg |= DMA_CFG_SMB_DIS; 4303 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4304 DELAY(1000); 4305 /* Stop Rx/Tx MACs. */ 4306 alc_stop_mac(sc); 4307 /* Disable interrupts which might be touched in taskq handler. */ 4308 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4309 /* Disable L0s/L1s */ 4310 alc_aspm(sc, 0, IFM_UNKNOWN); 4311 /* Reclaim Rx buffers that have been processed. */ 4312 if (sc->alc_cdata.alc_rxhead != NULL) 4313 m_freem(sc->alc_cdata.alc_rxhead); 4314 ALC_RXCHAIN_RESET(sc); 4315 /* 4316 * Free Tx/Rx mbufs still in the queues. 4317 */ 4318 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4319 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4320 if (rxd->rx_m != NULL) { 4321 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4322 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4323 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4324 rxd->rx_dmamap); 4325 m_freem(rxd->rx_m); 4326 rxd->rx_m = NULL; 4327 } 4328 } 4329 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4330 txd = &sc->alc_cdata.alc_txdesc[i]; 4331 if (txd->tx_m != NULL) { 4332 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4333 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4334 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4335 txd->tx_dmamap); 4336 m_freem(txd->tx_m); 4337 txd->tx_m = NULL; 4338 } 4339 } 4340 } 4341 4342 static void 4343 alc_stop_mac(struct alc_softc *sc) 4344 { 4345 uint32_t reg; 4346 int i; 4347 4348 alc_stop_queue(sc); 4349 /* Disable Rx/Tx MAC. */ 4350 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4351 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4352 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4353 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4354 } 4355 for (i = ALC_TIMEOUT; i > 0; i--) { 4356 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4357 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4358 break; 4359 DELAY(10); 4360 } 4361 if (i == 0) 4362 device_printf(sc->alc_dev, 4363 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4364 } 4365 4366 static void 4367 alc_start_queue(struct alc_softc *sc) 4368 { 4369 uint32_t qcfg[] = { 4370 0, 4371 RXQ_CFG_QUEUE0_ENB, 4372 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4373 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4374 RXQ_CFG_ENB 4375 }; 4376 uint32_t cfg; 4377 4378 ALC_LOCK_ASSERT(sc); 4379 4380 /* Enable RxQ. */ 4381 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4382 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4383 cfg &= ~RXQ_CFG_ENB; 4384 cfg |= qcfg[1]; 4385 } else 4386 cfg |= RXQ_CFG_QUEUE0_ENB; 4387 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4388 /* Enable TxQ. */ 4389 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4390 cfg |= TXQ_CFG_ENB; 4391 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4392 } 4393 4394 static void 4395 alc_stop_queue(struct alc_softc *sc) 4396 { 4397 uint32_t reg; 4398 int i; 4399 4400 /* Disable RxQ. */ 4401 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4402 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4403 if ((reg & RXQ_CFG_ENB) != 0) { 4404 reg &= ~RXQ_CFG_ENB; 4405 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4406 } 4407 } else { 4408 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4409 reg &= ~RXQ_CFG_QUEUE0_ENB; 4410 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4411 } 4412 } 4413 /* Disable TxQ. */ 4414 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4415 if ((reg & TXQ_CFG_ENB) != 0) { 4416 reg &= ~TXQ_CFG_ENB; 4417 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4418 } 4419 DELAY(40); 4420 for (i = ALC_TIMEOUT; i > 0; i--) { 4421 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4422 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4423 break; 4424 DELAY(10); 4425 } 4426 if (i == 0) 4427 device_printf(sc->alc_dev, 4428 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4429 } 4430 4431 static void 4432 alc_init_tx_ring(struct alc_softc *sc) 4433 { 4434 struct alc_ring_data *rd; 4435 struct alc_txdesc *txd; 4436 int i; 4437 4438 ALC_LOCK_ASSERT(sc); 4439 4440 sc->alc_cdata.alc_tx_prod = 0; 4441 sc->alc_cdata.alc_tx_cons = 0; 4442 sc->alc_cdata.alc_tx_cnt = 0; 4443 4444 rd = &sc->alc_rdata; 4445 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4446 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4447 txd = &sc->alc_cdata.alc_txdesc[i]; 4448 txd->tx_m = NULL; 4449 } 4450 4451 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4452 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4453 } 4454 4455 static int 4456 alc_init_rx_ring(struct alc_softc *sc) 4457 { 4458 struct alc_ring_data *rd; 4459 struct alc_rxdesc *rxd; 4460 int i; 4461 4462 ALC_LOCK_ASSERT(sc); 4463 4464 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4465 sc->alc_morework = 0; 4466 rd = &sc->alc_rdata; 4467 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4468 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4469 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4470 rxd->rx_m = NULL; 4471 rxd->rx_desc = &rd->alc_rx_ring[i]; 4472 if (alc_newbuf(sc, rxd) != 0) 4473 return (ENOBUFS); 4474 } 4475 4476 /* 4477 * Since controller does not update Rx descriptors, driver 4478 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4479 * is enough to ensure coherence. 4480 */ 4481 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4482 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4483 /* Let controller know availability of new Rx buffers. */ 4484 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4485 4486 return (0); 4487 } 4488 4489 static void 4490 alc_init_rr_ring(struct alc_softc *sc) 4491 { 4492 struct alc_ring_data *rd; 4493 4494 ALC_LOCK_ASSERT(sc); 4495 4496 sc->alc_cdata.alc_rr_cons = 0; 4497 ALC_RXCHAIN_RESET(sc); 4498 4499 rd = &sc->alc_rdata; 4500 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4501 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4502 sc->alc_cdata.alc_rr_ring_map, 4503 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4504 } 4505 4506 static void 4507 alc_init_cmb(struct alc_softc *sc) 4508 { 4509 struct alc_ring_data *rd; 4510 4511 ALC_LOCK_ASSERT(sc); 4512 4513 rd = &sc->alc_rdata; 4514 bzero(rd->alc_cmb, ALC_CMB_SZ); 4515 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4517 } 4518 4519 static void 4520 alc_init_smb(struct alc_softc *sc) 4521 { 4522 struct alc_ring_data *rd; 4523 4524 ALC_LOCK_ASSERT(sc); 4525 4526 rd = &sc->alc_rdata; 4527 bzero(rd->alc_smb, ALC_SMB_SZ); 4528 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4530 } 4531 4532 static void 4533 alc_rxvlan(struct alc_softc *sc) 4534 { 4535 struct ifnet *ifp; 4536 uint32_t reg; 4537 4538 ALC_LOCK_ASSERT(sc); 4539 4540 ifp = sc->alc_ifp; 4541 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4542 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4543 reg |= MAC_CFG_VLAN_TAG_STRIP; 4544 else 4545 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4546 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4547 } 4548 4549 static void 4550 alc_rxfilter(struct alc_softc *sc) 4551 { 4552 struct ifnet *ifp; 4553 struct ifmultiaddr *ifma; 4554 uint32_t crc; 4555 uint32_t mchash[2]; 4556 uint32_t rxcfg; 4557 4558 ALC_LOCK_ASSERT(sc); 4559 4560 ifp = sc->alc_ifp; 4561 4562 bzero(mchash, sizeof(mchash)); 4563 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4564 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4565 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4566 rxcfg |= MAC_CFG_BCAST; 4567 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4568 if ((ifp->if_flags & IFF_PROMISC) != 0) 4569 rxcfg |= MAC_CFG_PROMISC; 4570 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4571 rxcfg |= MAC_CFG_ALLMULTI; 4572 mchash[0] = 0xFFFFFFFF; 4573 mchash[1] = 0xFFFFFFFF; 4574 goto chipit; 4575 } 4576 4577 if_maddr_rlock(ifp); 4578 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4579 if (ifma->ifma_addr->sa_family != AF_LINK) 4580 continue; 4581 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4582 ifma->ifma_addr), ETHER_ADDR_LEN); 4583 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4584 } 4585 if_maddr_runlock(ifp); 4586 4587 chipit: 4588 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4589 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4590 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4591 } 4592 4593 static int 4594 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4595 { 4596 int error, value; 4597 4598 if (arg1 == NULL) 4599 return (EINVAL); 4600 value = *(int *)arg1; 4601 error = sysctl_handle_int(oidp, &value, 0, req); 4602 if (error || req->newptr == NULL) 4603 return (error); 4604 if (value < low || value > high) 4605 return (EINVAL); 4606 *(int *)arg1 = value; 4607 4608 return (0); 4609 } 4610 4611 static int 4612 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4613 { 4614 return (sysctl_int_range(oidp, arg1, arg2, req, 4615 ALC_PROC_MIN, ALC_PROC_MAX)); 4616 } 4617 4618 static int 4619 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4620 { 4621 4622 return (sysctl_int_range(oidp, arg1, arg2, req, 4623 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4624 }
Cache object: 71d0fa8b3d3340fb7565784373c26be4
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]