Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/alc/if_alcreg.h
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1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/8.4/sys/dev/alc/if_alcreg.h 222374 2011-05-27 19:03:42Z yongari $ 28 */ 29 30 #ifndef _IF_ALCREG_H 31 #define _IF_ALCREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR813x/AR815x device ID 40 */ 41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 47 48 #define ATHEROS_AR8152_B_V10 0xC0 49 #define ATHEROS_AR8152_B_V11 0xC1 50 51 /* 0x0000 - 0x02FF : PCIe configuration space */ 52 53 #define ALC_PEX_UNC_ERR_SEV 0x10C 54 #define PEX_UNC_ERR_SEV_TRN 0x00000001 55 #define PEX_UNC_ERR_SEV_DLP 0x00000010 56 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 57 #define PEX_UNC_ERR_SEV_FCP 0x00002000 58 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 59 #define PEX_UNC_ERR_SEV_CA 0x00008000 60 #define PEX_UNC_ERR_SEV_UC 0x00010000 61 #define PEX_UNC_ERR_SEV_ROV 0x00020000 62 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 63 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 64 #define PEX_UNC_ERR_SEV_UR 0x00100000 65 66 #define ALC_TWSI_CFG 0x218 67 #define TWSI_CFG_SW_LD_START 0x00000800 68 #define TWSI_CFG_HW_LD_START 0x00001000 69 #define TWSI_CFG_LD_EXIST 0x00400000 70 71 #define ALC_PCIE_PHYMISC 0x1000 72 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 73 74 #define ALC_PCIE_PHYMISC2 0x1004 75 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 76 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 77 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 78 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 79 80 #define ALC_TWSI_DEBUG 0x1108 81 #define TWSI_DEBUG_DEV_EXIST 0x20000000 82 83 #define ALC_EEPROM_CFG 0x12C0 84 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 85 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 86 #define EEPROM_CFG_ACK 0x40000000 87 #define EEPROM_CFG_RW 0x80000000 88 #define EEPROM_CFG_DATA_HI_SHIFT 0 89 #define EEPROM_CFG_ADDR_SHIFT 16 90 91 #define ALC_EEPROM_DATA_LO 0x12C4 92 93 #define ALC_OPT_CFG 0x12F0 94 #define OPT_CFG_CLK_ENB 0x00000002 95 96 #define ALC_PM_CFG 0x12F8 97 #define PM_CFG_SERDES_ENB 0x00000001 98 #define PM_CFG_RBER_ENB 0x00000002 99 #define PM_CFG_CLK_REQ_ENB 0x00000004 100 #define PM_CFG_ASPM_L1_ENB 0x00000008 101 #define PM_CFG_SERDES_L1_ENB 0x00000010 102 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 103 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 104 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 105 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 106 #define PM_CFG_ASPM_L0S_ENB 0x00001000 107 #define PM_CFG_CLK_SWH_L1 0x00002000 108 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 109 #define PM_CFG_PCIE_RECV 0x00008000 110 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 111 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 112 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 113 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 114 #define PM_CFG_SA_DLY_ENB 0x20000000 115 #define PM_CFG_MAC_ASPM_CHK 0x40000000 116 #define PM_CFG_HOTRST 0x80000000 117 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 118 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 119 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 120 #define PM_CFG_LCKDET_TIMER_SHIFT 24 121 122 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 123 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 124 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 125 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 126 127 #define ALC_LTSSM_ID_CFG 0x12FC 128 #define LTSSM_ID_WRO_ENB 0x00001000 129 130 #define ALC_MASTER_CFG 0x1400 131 #define MASTER_RESET 0x00000001 132 #define MASTER_TEST_MODE_MASK 0x0000000C 133 #define MASTER_BERT_START 0x00000010 134 #define MASTER_OOB_DIS_OFF 0x00000040 135 #define MASTER_SA_TIMER_ENB 0x00000080 136 #define MASTER_MTIMER_ENB 0x00000100 137 #define MASTER_MANUAL_INTR_ENB 0x00000200 138 #define MASTER_IM_TX_TIMER_ENB 0x00000400 139 #define MASTER_IM_RX_TIMER_ENB 0x00000800 140 #define MASTER_CLK_SEL_DIS 0x00001000 141 #define MASTER_CLK_SWH_MODE 0x00002000 142 #define MASTER_INTR_RD_CLR 0x00004000 143 #define MASTER_CHIP_REV_MASK 0x00FF0000 144 #define MASTER_CHIP_ID_MASK 0x7F000000 145 #define MASTER_OTP_SEL 0x80000000 146 #define MASTER_TEST_MODE_SHIFT 2 147 #define MASTER_CHIP_REV_SHIFT 16 148 #define MASTER_CHIP_ID_SHIFT 24 149 150 /* Number of ticks per usec for AR813x/AR815x. */ 151 #define ALC_TICK_USECS 2 152 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 153 154 #define ALC_MANUAL_TIMER 0x1404 155 156 #define ALC_IM_TIMER 0x1408 157 #define IM_TIMER_TX_MASK 0x0000FFFF 158 #define IM_TIMER_RX_MASK 0xFFFF0000 159 #define IM_TIMER_TX_SHIFT 0 160 #define IM_TIMER_RX_SHIFT 16 161 #define ALC_IM_TIMER_MIN 0 162 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 163 /* 164 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 165 * interrupts in a second. 166 */ 167 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 168 /* 169 * alc(4) does not rely on Tx completion interrupts, so set it 170 * somewhat large value to reduce Tx completion interrupts. 171 */ 172 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 173 174 #define ALC_GPHY_CFG 0x140C /* 16bits */ 175 #define GPHY_CFG_EXT_RESET 0x0001 176 #define GPHY_CFG_RTL_MODE 0x0002 177 #define GPHY_CFG_LED_MODE 0x0004 178 #define GPHY_CFG_ANEG_NOW 0x0008 179 #define GPHY_CFG_RECV_ANEG 0x0010 180 #define GPHY_CFG_GATE_25M_ENB 0x0020 181 #define GPHY_CFG_LPW_EXIT 0x0040 182 #define GPHY_CFG_PHY_IDDQ 0x0080 183 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 184 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 185 #define GPHY_CFG_HIB_EN 0x0400 186 #define GPHY_CFG_HIB_PULSE 0x0800 187 #define GPHY_CFG_SEL_ANA_RESET 0x1000 188 #define GPHY_CFG_PHY_PLL_ON 0x2000 189 #define GPHY_CFG_PWDOWN_HW 0x4000 190 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 191 192 #define ALC_IDLE_STATUS 0x1410 193 #define IDLE_STATUS_RXMAC 0x00000001 194 #define IDLE_STATUS_TXMAC 0x00000002 195 #define IDLE_STATUS_RXQ 0x00000004 196 #define IDLE_STATUS_TXQ 0x00000008 197 #define IDLE_STATUS_DMARD 0x00000010 198 #define IDLE_STATUS_DMAWR 0x00000020 199 #define IDLE_STATUS_SMB 0x00000040 200 #define IDLE_STATUS_CMB 0x00000080 201 202 #define ALC_MDIO 0x1414 203 #define MDIO_DATA_MASK 0x0000FFFF 204 #define MDIO_REG_ADDR_MASK 0x001F0000 205 #define MDIO_OP_READ 0x00200000 206 #define MDIO_OP_WRITE 0x00000000 207 #define MDIO_SUP_PREAMBLE 0x00400000 208 #define MDIO_OP_EXECUTE 0x00800000 209 #define MDIO_CLK_25_4 0x00000000 210 #define MDIO_CLK_25_6 0x02000000 211 #define MDIO_CLK_25_8 0x03000000 212 #define MDIO_CLK_25_10 0x04000000 213 #define MDIO_CLK_25_14 0x05000000 214 #define MDIO_CLK_25_20 0x06000000 215 #define MDIO_CLK_25_28 0x07000000 216 #define MDIO_OP_BUSY 0x08000000 217 #define MDIO_AP_ENB 0x10000000 218 #define MDIO_DATA_SHIFT 0 219 #define MDIO_REG_ADDR_SHIFT 16 220 221 #define MDIO_REG_ADDR(x) \ 222 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 223 /* Default PHY address. */ 224 #define ALC_PHY_ADDR 0 225 226 #define ALC_PHY_STATUS 0x1418 227 #define PHY_STATUS_RECV_ENB 0x00000001 228 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 229 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 230 #define PHY_STATUS_LPW_STATE 0x80000000 231 #define PHY_STATIS_OE_PWSP_SHIFT 16 232 233 /* Packet memory BIST. */ 234 #define ALC_BIST0 0x141C 235 #define BIST0_ENB 0x00000001 236 #define BIST0_SRAM_FAIL 0x00000002 237 #define BIST0_FUSE_FLAG 0x00000004 238 239 /* PCIe retry buffer BIST. */ 240 #define ALC_BIST1 0x1420 241 #define BIST1_ENB 0x00000001 242 #define BIST1_SRAM_FAIL 0x00000002 243 #define BIST1_FUSE_FLAG 0x00000004 244 245 #define ALC_SERDES_LOCK 0x1424 246 #define SERDES_LOCK_DET 0x00000001 247 #define SERDES_LOCK_DET_ENB 0x00000002 248 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 249 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 250 251 #define ALC_MAC_CFG 0x1480 252 #define MAC_CFG_TX_ENB 0x00000001 253 #define MAC_CFG_RX_ENB 0x00000002 254 #define MAC_CFG_TX_FC 0x00000004 255 #define MAC_CFG_RX_FC 0x00000008 256 #define MAC_CFG_LOOP 0x00000010 257 #define MAC_CFG_FULL_DUPLEX 0x00000020 258 #define MAC_CFG_TX_CRC_ENB 0x00000040 259 #define MAC_CFG_TX_AUTO_PAD 0x00000080 260 #define MAC_CFG_TX_LENCHK 0x00000100 261 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 262 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 263 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 264 #define MAC_CFG_PROMISC 0x00008000 265 #define MAC_CFG_TX_PAUSE 0x00010000 266 #define MAC_CFG_SCNT 0x00020000 267 #define MAC_CFG_SYNC_RST_TX 0x00040000 268 #define MAC_CFG_SIM_RST_TX 0x00080000 269 #define MAC_CFG_SPEED_MASK 0x00300000 270 #define MAC_CFG_SPEED_10_100 0x00100000 271 #define MAC_CFG_SPEED_1000 0x00200000 272 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 273 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 274 #define MAC_CFG_RXCSUM_ENB 0x01000000 275 #define MAC_CFG_ALLMULTI 0x02000000 276 #define MAC_CFG_BCAST 0x04000000 277 #define MAC_CFG_DBG 0x08000000 278 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 279 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 280 #define MAC_CFG_SPEED_MODE_SW 0x40000000 281 #define MAC_CFG_PREAMBLE_SHIFT 10 282 #define MAC_CFG_PREAMBLE_DEFAULT 7 283 284 #define ALC_IPG_IFG_CFG 0x1484 285 #define IPG_IFG_IPGT_MASK 0x0000007F 286 #define IPG_IFG_MIFG_MASK 0x0000FF00 287 #define IPG_IFG_IPG1_MASK 0x007F0000 288 #define IPG_IFG_IPG2_MASK 0x7F000000 289 #define IPG_IFG_IPGT_SHIFT 0 290 #define IPG_IFG_IPGT_DEFAULT 0x60 291 #define IPG_IFG_MIFG_SHIFT 8 292 #define IPG_IFG_MIFG_DEFAULT 0x50 293 #define IPG_IFG_IPG1_SHIFT 16 294 #define IPG_IFG_IPG1_DEFAULT 0x40 295 #define IPG_IFG_IPG2_SHIFT 24 296 #define IPG_IFG_IPG2_DEFAULT 0x60 297 298 /* Station address. */ 299 #define ALC_PAR0 0x1488 300 #define ALC_PAR1 0x148C 301 302 /* 64bit multicast hash register. */ 303 #define ALC_MAR0 0x1490 304 #define ALC_MAR1 0x1494 305 306 /* half-duplex parameter configuration. */ 307 #define ALC_HDPX_CFG 0x1498 308 #define HDPX_CFG_LCOL_MASK 0x000003FF 309 #define HDPX_CFG_RETRY_MASK 0x0000F000 310 #define HDPX_CFG_EXC_DEF_EN 0x00010000 311 #define HDPX_CFG_NO_BACK_C 0x00020000 312 #define HDPX_CFG_NO_BACK_P 0x00040000 313 #define HDPX_CFG_ABEBE 0x00080000 314 #define HDPX_CFG_ABEBT_MASK 0x00F00000 315 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 316 #define HDPX_CFG_LCOL_SHIFT 0 317 #define HDPX_CFG_LCOL_DEFAULT 0x37 318 #define HDPX_CFG_RETRY_SHIFT 12 319 #define HDPX_CFG_RETRY_DEFAULT 0x0F 320 #define HDPX_CFG_ABEBT_SHIFT 20 321 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 322 #define HDPX_CFG_JAMIPG_SHIFT 24 323 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 324 325 #define ALC_FRAME_SIZE 0x149C 326 327 #define ALC_WOL_CFG 0x14A0 328 #define WOL_CFG_PATTERN 0x00000001 329 #define WOL_CFG_PATTERN_ENB 0x00000002 330 #define WOL_CFG_MAGIC 0x00000004 331 #define WOL_CFG_MAGIC_ENB 0x00000008 332 #define WOL_CFG_LINK_CHG 0x00000010 333 #define WOL_CFG_LINK_CHG_ENB 0x00000020 334 #define WOL_CFG_PATTERN_DET 0x00000100 335 #define WOL_CFG_MAGIC_DET 0x00000200 336 #define WOL_CFG_LINK_CHG_DET 0x00000400 337 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 338 #define WOL_CFG_PATTERN0 0x00010000 339 #define WOL_CFG_PATTERN1 0x00020000 340 #define WOL_CFG_PATTERN2 0x00040000 341 #define WOL_CFG_PATTERN3 0x00080000 342 #define WOL_CFG_PATTERN4 0x00100000 343 #define WOL_CFG_PATTERN5 0x00200000 344 #define WOL_CFG_PATTERN6 0x00400000 345 346 /* WOL pattern length. */ 347 #define ALC_PATTERN_CFG0 0x14A4 348 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 349 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 350 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 351 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 352 353 #define ALC_PATTERN_CFG1 0x14A8 354 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 355 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 356 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 357 358 /* RSS */ 359 #define ALC_RSS_KEY0 0x14B0 360 361 #define ALC_RSS_KEY1 0x14B4 362 363 #define ALC_RSS_KEY2 0x14B8 364 365 #define ALC_RSS_KEY3 0x14BC 366 367 #define ALC_RSS_KEY4 0x14C0 368 369 #define ALC_RSS_KEY5 0x14C4 370 371 #define ALC_RSS_KEY6 0x14C8 372 373 #define ALC_RSS_KEY7 0x14CC 374 375 #define ALC_RSS_KEY8 0x14D0 376 377 #define ALC_RSS_KEY9 0x14D4 378 379 #define ALC_RSS_IDT_TABLE0 0x14E0 380 381 #define ALC_RSS_IDT_TABLE1 0x14E4 382 383 #define ALC_RSS_IDT_TABLE2 0x14E8 384 385 #define ALC_RSS_IDT_TABLE3 0x14EC 386 387 #define ALC_RSS_IDT_TABLE4 0x14F0 388 389 #define ALC_RSS_IDT_TABLE5 0x14F4 390 391 #define ALC_RSS_IDT_TABLE6 0x14F8 392 393 #define ALC_RSS_IDT_TABLE7 0x14FC 394 395 #define ALC_SRAM_RD0_ADDR 0x1500 396 397 #define ALC_SRAM_RD1_ADDR 0x1504 398 399 #define ALC_SRAM_RD2_ADDR 0x1508 400 401 #define ALC_SRAM_RD3_ADDR 0x150C 402 403 #define RD_HEAD_ADDR_MASK 0x000003FF 404 #define RD_TAIL_ADDR_MASK 0x03FF0000 405 #define RD_HEAD_ADDR_SHIFT 0 406 #define RD_TAIL_ADDR_SHIFT 16 407 408 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 409 #define RD_NIC_LEN_MASK 0x000003FF 410 411 #define ALC_RD_NIC_LEN1 0x1514 412 413 #define ALC_SRAM_TD_ADDR 0x1518 414 #define TD_HEAD_ADDR_MASK 0x000003FF 415 #define TD_TAIL_ADDR_MASK 0x03FF0000 416 #define TD_HEAD_ADDR_SHIFT 0 417 #define TD_TAIL_ADDR_SHIFT 16 418 419 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 420 #define SRAM_TD_LEN_MASK 0x000003FF 421 422 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 423 424 #define ALC_SRAM_RX_FIFO_LEN 0x1524 425 426 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 427 428 #define ALC_SRAM_TX_FIFO_LEN 0x152C 429 430 #define ALC_SRAM_TCPH_ADDR 0x1530 431 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 432 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 433 #define SRAM_TCPH_ADDR_SHIFT 0 434 #define SRAM_PKTH_ADDR_SHIFT 16 435 436 #define ALC_DMA_BLOCK 0x1534 437 #define DMA_BLOCK_LOAD 0x00000001 438 439 #define ALC_RX_BASE_ADDR_HI 0x1540 440 441 #define ALC_TX_BASE_ADDR_HI 0x1544 442 443 #define ALC_SMB_BASE_ADDR_HI 0x1548 444 445 #define ALC_SMB_BASE_ADDR_LO 0x154C 446 447 #define ALC_RD0_HEAD_ADDR_LO 0x1550 448 449 #define ALC_RD1_HEAD_ADDR_LO 0x1554 450 451 #define ALC_RD2_HEAD_ADDR_LO 0x1558 452 453 #define ALC_RD3_HEAD_ADDR_LO 0x155C 454 455 #define ALC_RD_RING_CNT 0x1560 456 #define RD_RING_CNT_MASK 0x00000FFF 457 #define RD_RING_CNT_SHIFT 0 458 459 #define ALC_RX_BUF_SIZE 0x1564 460 #define RX_BUF_SIZE_MASK 0x0000FFFF 461 /* 462 * If larger buffer size than 1536 is specified the controller 463 * will be locked up. This is hardware limitation. 464 */ 465 #define RX_BUF_SIZE_MAX 1536 466 467 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 468 469 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 470 471 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 472 473 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 474 475 #define ALC_RRD_RING_CNT 0x1578 476 #define RRD_RING_CNT_MASK 0x00000FFF 477 #define RRD_RING_CNT_SHIFT 0 478 479 #define ALC_TDH_HEAD_ADDR_LO 0x157C 480 481 #define ALC_TDL_HEAD_ADDR_LO 0x1580 482 483 #define ALC_TD_RING_CNT 0x1584 484 #define TD_RING_CNT_MASK 0x0000FFFF 485 #define TD_RING_CNT_SHIFT 0 486 487 #define ALC_CMB_BASE_ADDR_LO 0x1588 488 489 #define ALC_TXQ_CFG 0x1590 490 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 491 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 492 #define TXQ_CFG_ENB 0x00000020 493 #define TXQ_CFG_ENHANCED_MODE 0x00000040 494 #define TXQ_CFG_8023_ENB 0x00000080 495 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 496 #define TXQ_CFG_TD_BURST_SHIFT 0 497 #define TXQ_CFG_TD_BURST_DEFAULT 5 498 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 499 500 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 501 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 502 #define TSO_OFFLOAD_THRESH_SHIFT 0 503 #define TSO_OFFLOAD_THRESH_UNIT 8 504 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 505 506 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 507 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 508 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 509 #define TXF_WATER_MARK_BURST_ENB 0x80000000 510 #define TXF_WATER_MARK_LO_SHIFT 0 511 #define TXF_WATER_MARK_HI_SHIFT 16 512 513 #define ALC_THROUGHPUT_MON 0x159C 514 #define THROUGHPUT_MON_RATE_MASK 0x00000003 515 #define THROUGHPUT_MON_ENB 0x00000080 516 #define THROUGHPUT_MON_RATE_SHIFT 0 517 518 #define ALC_RXQ_CFG 0x15A0 519 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 520 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 521 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 522 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 523 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 524 #define RXQ_CFG_QUEUE1_ENB 0x00000010 525 #define RXQ_CFG_QUEUE2_ENB 0x00000020 526 #define RXQ_CFG_QUEUE3_ENB 0x00000040 527 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 528 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 529 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 530 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 531 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 532 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 533 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 534 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 535 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 536 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 537 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 538 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 539 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 540 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 541 #define RXQ_CFG_QUEUE0_ENB 0x80000000 542 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 543 #define RXQ_CFG_RD_BURST_DEFAULT 8 544 #define RXQ_CFG_RD_BURST_SHIFT 20 545 #define RXQ_CFG_ENB \ 546 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 547 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 548 549 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 550 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 551 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 552 #define RX_RD_FREE_THRESH_HI_SHIFT 0 553 #define RX_RD_FREE_THRESH_LO_SHIFT 6 554 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 555 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 556 557 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 558 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 559 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 560 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 561 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 562 563 #define ALC_RD_DMA_CFG 0x15AC 564 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 565 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 566 #define RD_DMA_CFG_THRESH_SHIFT 0 567 #define RD_DMA_CFG_TIMER_SHIFT 16 568 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 569 #define RD_DMA_CFG_TIMER_DEFAULT 0 570 #define RD_DMA_CFG_TICK_USECS 8 571 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 572 573 #define ALC_RSS_HASH_VALUE 0x15B0 574 575 #define ALC_RSS_HASH_FLAG 0x15B4 576 577 #define ALC_RSS_CPU 0x15B8 578 579 #define ALC_DMA_CFG 0x15C0 580 #define DMA_CFG_IN_ORDER 0x00000001 581 #define DMA_CFG_ENH_ORDER 0x00000002 582 #define DMA_CFG_OUT_ORDER 0x00000004 583 #define DMA_CFG_RCB_64 0x00000000 584 #define DMA_CFG_RCB_128 0x00000008 585 #define DMA_CFG_RD_BURST_128 0x00000000 586 #define DMA_CFG_RD_BURST_256 0x00000010 587 #define DMA_CFG_RD_BURST_512 0x00000020 588 #define DMA_CFG_RD_BURST_1024 0x00000030 589 #define DMA_CFG_RD_BURST_2048 0x00000040 590 #define DMA_CFG_RD_BURST_4096 0x00000050 591 #define DMA_CFG_WR_BURST_128 0x00000000 592 #define DMA_CFG_WR_BURST_256 0x00000080 593 #define DMA_CFG_WR_BURST_512 0x00000100 594 #define DMA_CFG_WR_BURST_1024 0x00000180 595 #define DMA_CFG_WR_BURST_2048 0x00000200 596 #define DMA_CFG_WR_BURST_4096 0x00000280 597 #define DMA_CFG_RD_REQ_PRI 0x00000400 598 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 599 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 600 #define DMA_CFG_CMB_ENB 0x00100000 601 #define DMA_CFG_SMB_ENB 0x00200000 602 #define DMA_CFG_CMB_NOW 0x00400000 603 #define DMA_CFG_SMB_DIS 0x01000000 604 #define DMA_CFG_SMB_NOW 0x80000000 605 #define DMA_CFG_RD_BURST_MASK 0x07 606 #define DMA_CFG_RD_BURST_SHIFT 4 607 #define DMA_CFG_WR_BURST_MASK 0x07 608 #define DMA_CFG_WR_BURST_SHIFT 7 609 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 610 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 611 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 612 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 613 614 #define ALC_SMB_STAT_TIMER 0x15C4 615 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 616 #define SMB_STAT_TIMER_SHIFT 0 617 618 #define ALC_CMB_TD_THRESH 0x15C8 619 #define CMB_TD_THRESH_MASK 0x0000FFFF 620 #define CMB_TD_THRESH_SHIFT 0 621 622 #define ALC_CMB_TX_TIMER 0x15CC 623 #define CMB_TX_TIMER_MASK 0x0000FFFF 624 #define CMB_TX_TIMER_SHIFT 0 625 626 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 627 628 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 629 630 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 631 632 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 633 634 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 635 #define MBOX_RD_PROD_SHIFT 0 636 637 #define ALC_MBOX_TD_PROD_IDX 0x15F0 638 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 639 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 640 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 641 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 642 643 #define ALC_MBOX_TD_CONS_IDX 0x15F4 644 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 645 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 646 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 647 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 648 649 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 650 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 651 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 652 #define MBOX_RD0_CONS_IDX_SHIFT 0 653 #define MBOX_RD1_CONS_IDX_SHIFT 16 654 655 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 656 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 657 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 658 #define MBOX_RD2_CONS_IDX_SHIFT 0 659 #define MBOX_RD3_CONS_IDX_SHIFT 16 660 661 #define ALC_INTR_STATUS 0x1600 662 #define INTR_SMB 0x00000001 663 #define INTR_TIMER 0x00000002 664 #define INTR_MANUAL_TIMER 0x00000004 665 #define INTR_RX_FIFO_OFLOW 0x00000008 666 #define INTR_RD0_UNDERRUN 0x00000010 667 #define INTR_RD1_UNDERRUN 0x00000020 668 #define INTR_RD2_UNDERRUN 0x00000040 669 #define INTR_RD3_UNDERRUN 0x00000080 670 #define INTR_TX_FIFO_UNDERRUN 0x00000100 671 #define INTR_DMA_RD_TO_RST 0x00000200 672 #define INTR_DMA_WR_TO_RST 0x00000400 673 #define INTR_TX_CREDIT 0x00000800 674 #define INTR_GPHY 0x00001000 675 #define INTR_GPHY_LOW_PW 0x00002000 676 #define INTR_TXQ_TO_RST 0x00004000 677 #define INTR_TX_PKT 0x00008000 678 #define INTR_RX_PKT0 0x00010000 679 #define INTR_RX_PKT1 0x00020000 680 #define INTR_RX_PKT2 0x00040000 681 #define INTR_RX_PKT3 0x00080000 682 #define INTR_MAC_RX 0x00100000 683 #define INTR_MAC_TX 0x00200000 684 #define INTR_UNDERRUN 0x00400000 685 #define INTR_FRAME_ERROR 0x00800000 686 #define INTR_FRAME_OK 0x01000000 687 #define INTR_CSUM_ERROR 0x02000000 688 #define INTR_PHY_LINK_DOWN 0x04000000 689 #define INTR_DIS_INT 0x80000000 690 691 /* Interrupt Mask Register */ 692 #define ALC_INTR_MASK 0x1604 693 694 #ifdef notyet 695 #define INTR_RX_PKT \ 696 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 697 INTR_RX_PKT3) 698 #define INTR_RD_UNDERRUN \ 699 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 700 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 701 #else 702 #define INTR_RX_PKT INTR_RX_PKT0 703 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 704 #endif 705 706 #define ALC_INTRS \ 707 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 708 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 709 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 710 INTR_TX_FIFO_UNDERRUN) 711 712 #define ALC_INTR_RETRIG_TIMER 0x1608 713 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 714 #define INTR_RETRIG_TIMER_SHIFT 0 715 716 #define ALC_HDS_CFG 0x160C 717 #define HDS_CFG_ENB 0x00000001 718 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 719 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 720 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 721 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 722 723 /* AR813x/AR815x registers for MAC statistics */ 724 #define ALC_RX_MIB_BASE 0x1700 725 726 #define ALC_TX_MIB_BASE 0x1760 727 728 #define ALC_CLK_GATING_CFG 0x1814 729 #define CLK_GATING_DMAW_ENB 0x0001 730 #define CLK_GATING_DMAR_ENB 0x0002 731 #define CLK_GATING_TXQ_ENB 0x0004 732 #define CLK_GATING_RXQ_ENB 0x0008 733 #define CLK_GATING_TXMAC_ENB 0x0010 734 #define CLK_GATING_RXMAC_ENB 0x0020 735 736 #define ALC_DEBUG_DATA0 0x1900 737 738 #define ALC_DEBUG_DATA1 0x1904 739 740 #define ALC_MII_DBG_ADDR 0x1D 741 #define ALC_MII_DBG_DATA 0x1E 742 743 #define MII_ANA_CFG0 0x00 744 #define ANA_RESTART_CAL 0x0001 745 #define ANA_MANUL_SWICH_ON_MASK 0x001E 746 #define ANA_MAN_ENABLE 0x0020 747 #define ANA_SEL_HSP 0x0040 748 #define ANA_EN_HB 0x0080 749 #define ANA_EN_HBIAS 0x0100 750 #define ANA_OEN_125M 0x0200 751 #define ANA_EN_LCKDT 0x0400 752 #define ANA_LCKDT_PHY 0x0800 753 #define ANA_AFE_MODE 0x1000 754 #define ANA_VCO_SLOW 0x2000 755 #define ANA_VCO_FAST 0x4000 756 #define ANA_SEL_CLK125M_DSP 0x8000 757 #define ANA_MANUL_SWICH_ON_SHIFT 1 758 759 #define MII_ANA_CFG4 0x04 760 #define ANA_IECHO_ADJ_MASK 0x0F 761 #define ANA_IECHO_ADJ_3_MASK 0x000F 762 #define ANA_IECHO_ADJ_2_MASK 0x00F0 763 #define ANA_IECHO_ADJ_1_MASK 0x0F00 764 #define ANA_IECHO_ADJ_0_MASK 0xF000 765 #define ANA_IECHO_ADJ_3_SHIFT 0 766 #define ANA_IECHO_ADJ_2_SHIFT 4 767 #define ANA_IECHO_ADJ_1_SHIFT 8 768 #define ANA_IECHO_ADJ_0_SHIFT 12 769 770 #define MII_ANA_CFG5 0x05 771 #define ANA_SERDES_CDR_BW_MASK 0x0003 772 #define ANA_MS_PAD_DBG 0x0004 773 #define ANA_SPEEDUP_DBG 0x0008 774 #define ANA_SERDES_TH_LOS_MASK 0x0030 775 #define ANA_SERDES_EN_DEEM 0x0040 776 #define ANA_SERDES_TXELECIDLE 0x0080 777 #define ANA_SERDES_BEACON 0x0100 778 #define ANA_SERDES_HALFTXDR 0x0200 779 #define ANA_SERDES_SEL_HSP 0x0400 780 #define ANA_SERDES_EN_PLL 0x0800 781 #define ANA_SERDES_EN 0x1000 782 #define ANA_SERDES_EN_LCKDT 0x2000 783 #define ANA_SERDES_CDR_BW_SHIFT 0 784 #define ANA_SERDES_TH_LOS_SHIFT 4 785 786 #define MII_ANA_CFG11 0x0B 787 #define ANA_PS_HIB_EN 0x8000 788 789 #define MII_ANA_CFG18 0x12 790 #define ANA_TEST_MODE_10BT_01MASK 0x0003 791 #define ANA_LOOP_SEL_10BT 0x0004 792 #define ANA_RGMII_MODE_SW 0x0008 793 #define ANA_EN_LONGECABLE 0x0010 794 #define ANA_TEST_MODE_10BT_2 0x0020 795 #define ANA_EN_10BT_IDLE 0x0400 796 #define ANA_EN_MASK_TB 0x0800 797 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 798 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 799 #define ANA_TEST_MODE_10BT_01SHIFT 0 800 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 801 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 802 803 #define MII_ANA_CFG41 0x29 804 #define ANA_TOP_PS_EN 0x8000 805 806 #define MII_ANA_CFG54 0x36 807 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 808 #define ANA_DESERVED 0x0040 809 #define ANA_EN_LIT_CH 0x0080 810 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 811 #define ANA_BP_BAD_LINK_ACCUM 0x4000 812 #define ANA_BP_SMALL_BW 0x8000 813 #define ANA_LONG_CABLE_TH_100_SHIFT 0 814 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 815 816 /* Statistics counters collected by the MAC. */ 817 struct smb { 818 /* Rx stats. */ 819 uint32_t rx_frames; 820 uint32_t rx_bcast_frames; 821 uint32_t rx_mcast_frames; 822 uint32_t rx_pause_frames; 823 uint32_t rx_control_frames; 824 uint32_t rx_crcerrs; 825 uint32_t rx_lenerrs; 826 uint32_t rx_bytes; 827 uint32_t rx_runts; 828 uint32_t rx_fragments; 829 uint32_t rx_pkts_64; 830 uint32_t rx_pkts_65_127; 831 uint32_t rx_pkts_128_255; 832 uint32_t rx_pkts_256_511; 833 uint32_t rx_pkts_512_1023; 834 uint32_t rx_pkts_1024_1518; 835 uint32_t rx_pkts_1519_max; 836 uint32_t rx_pkts_truncated; 837 uint32_t rx_fifo_oflows; 838 uint32_t rx_rrs_errs; 839 uint32_t rx_alignerrs; 840 uint32_t rx_bcast_bytes; 841 uint32_t rx_mcast_bytes; 842 uint32_t rx_pkts_filtered; 843 /* Tx stats. */ 844 uint32_t tx_frames; 845 uint32_t tx_bcast_frames; 846 uint32_t tx_mcast_frames; 847 uint32_t tx_pause_frames; 848 uint32_t tx_excess_defer; 849 uint32_t tx_control_frames; 850 uint32_t tx_deferred; 851 uint32_t tx_bytes; 852 uint32_t tx_pkts_64; 853 uint32_t tx_pkts_65_127; 854 uint32_t tx_pkts_128_255; 855 uint32_t tx_pkts_256_511; 856 uint32_t tx_pkts_512_1023; 857 uint32_t tx_pkts_1024_1518; 858 uint32_t tx_pkts_1519_max; 859 uint32_t tx_single_colls; 860 uint32_t tx_multi_colls; 861 uint32_t tx_late_colls; 862 uint32_t tx_excess_colls; 863 uint32_t tx_abort; 864 uint32_t tx_underrun; 865 uint32_t tx_desc_underrun; 866 uint32_t tx_lenerrs; 867 uint32_t tx_pkts_truncated; 868 uint32_t tx_bcast_bytes; 869 uint32_t tx_mcast_bytes; 870 uint32_t updated; 871 }; 872 873 /* CMB(Coalesing message block) */ 874 struct cmb { 875 uint32_t cons; 876 }; 877 878 /* Rx free descriptor */ 879 struct rx_desc { 880 uint64_t addr; 881 }; 882 883 /* Rx return descriptor */ 884 struct rx_rdesc { 885 uint32_t rdinfo; 886 #define RRD_CSUM_MASK 0x0000FFFF 887 #define RRD_RD_CNT_MASK 0x000F0000 888 #define RRD_RD_IDX_MASK 0xFFF00000 889 #define RRD_CSUM_SHIFT 0 890 #define RRD_RD_CNT_SHIFT 16 891 #define RRD_RD_IDX_SHIFT 20 892 #define RRD_CSUM(x) \ 893 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 894 #define RRD_RD_CNT(x) \ 895 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 896 #define RRD_RD_IDX(x) \ 897 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 898 uint32_t rss; 899 uint32_t vtag; 900 #define RRD_VLAN_MASK 0x0000FFFF 901 #define RRD_HEAD_LEN_MASK 0x00FF0000 902 #define RRD_HDS_MASK 0x03000000 903 #define RRD_HDS_NONE 0x00000000 904 #define RRD_HDS_HEAD 0x01000000 905 #define RRD_HDS_DATA 0x02000000 906 #define RRD_CPU_MASK 0x0C000000 907 #define RRD_HASH_FLAG_MASK 0xF0000000 908 #define RRD_VLAN_SHIFT 0 909 #define RRD_HEAD_LEN_SHIFT 16 910 #define RRD_HDS_SHIFT 24 911 #define RRD_CPU_SHIFT 26 912 #define RRD_HASH_FLAG_SHIFT 28 913 #define RRD_VLAN(x) \ 914 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 915 #define RRD_HEAD_LEN(x) \ 916 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 917 #define RRD_CPU(x) \ 918 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 919 uint32_t status; 920 #define RRD_LEN_MASK 0x00003FFF 921 #define RRD_LEN_SHIFT 0 922 #define RRD_TCP_UDPCSUM_NOK 0x00004000 923 #define RRD_IPCSUM_NOK 0x00008000 924 #define RRD_VLAN_TAG 0x00010000 925 #define RRD_PROTO_MASK 0x000E0000 926 #define RRD_PROTO_IPV4 0x00020000 927 #define RRD_PROTO_IPV6 0x000C0000 928 #define RRD_ERR_SUM 0x00100000 929 #define RRD_ERR_CRC 0x00200000 930 #define RRD_ERR_ALIGN 0x00400000 931 #define RRD_ERR_TRUNC 0x00800000 932 #define RRD_ERR_RUNT 0x01000000 933 #define RRD_ERR_ICMP 0x02000000 934 #define RRD_BCAST 0x04000000 935 #define RRD_MCAST 0x08000000 936 #define RRD_SNAP_LLC 0x10000000 937 #define RRD_ETHER 0x00000000 938 #define RRD_FIFO_FULL 0x20000000 939 #define RRD_ERR_LENGTH 0x40000000 940 #define RRD_VALID 0x80000000 941 #define RRD_BYTES(x) \ 942 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 943 #define RRD_IPV4(x) \ 944 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 945 }; 946 947 /* Tx descriptor */ 948 struct tx_desc { 949 uint32_t len; 950 #define TD_BUFLEN_MASK 0x00003FFF 951 #define TD_VLAN_MASK 0xFFFF0000 952 #define TD_BUFLEN_SHIFT 0 953 #define TX_BYTES(x) \ 954 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 955 #define TD_VLAN_SHIFT 16 956 uint32_t flags; 957 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 958 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 959 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 960 #define TD_CUSTOM_CSUM 0x00000100 961 #define TD_IPCSUM 0x00000200 962 #define TD_TCPCSUM 0x00000400 963 #define TD_UDPCSUM 0x00000800 964 #define TD_TSO 0x00001000 965 #define TD_TSO_DESCV1 0x00000000 966 #define TD_TSO_DESCV2 0x00002000 967 #define TD_CON_VLAN_TAG 0x00004000 968 #define TD_INS_VLAN_TAG 0x00008000 969 #define TD_IPV4_DESCV2 0x00010000 970 #define TD_LLC_SNAP 0x00020000 971 #define TD_ETHERNET 0x00000000 972 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 973 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 974 #define TD_MSS_MASK 0x7FFC0000 975 #define TD_EOP 0x80000000 976 #define TD_L4HDR_OFFSET_SHIFT 0 977 #define TD_TCPHDR_OFFSET_SHIFT 0 978 #define TD_PLOAD_OFFSET_SHIFT 0 979 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 980 #define TD_MSS_SHIFT 18 981 uint64_t addr; 982 }; 983 984 #endif /* _IF_ALCREG_H */
Cache object: 127e8babc0ee9450327003ddceea3ecf
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