1 /*-
2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #ifndef _IF_ALCREG_H
31 #define _IF_ALCREG_H
32
33 /*
34 * Atheros Communucations, Inc. PCI vendor ID
35 */
36 #define VENDORID_ATHEROS 0x1969
37
38 /*
39 * Atheros AR813x/AR815x device ID
40 */
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_E2200 0xE091
49 #define DEVICEID_ATHEROS_AR8162 0x1090
50 #define DEVICEID_ATHEROS_AR8171 0x10A1
51 #define DEVICEID_ATHEROS_AR8172 0x10A0
52
53 #define ATHEROS_AR8152_B_V10 0xC0
54 #define ATHEROS_AR8152_B_V11 0xC1
55
56 /*
57 * Atheros AR816x/AR817x revisions
58 */
59 #define AR816X_REV_A0 0
60 #define AR816X_REV_A1 1
61 #define AR816X_REV_B0 2
62 #define AR816X_REV_C0 3
63
64 #define AR816X_REV_SHIFT 3
65 #define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT)
66
67 /* 0x0000 - 0x02FF : PCIe configuration space */
68
69 #define ALC_PEX_UNC_ERR_SEV 0x10C
70 #define PEX_UNC_ERR_SEV_TRN 0x00000001
71 #define PEX_UNC_ERR_SEV_DLP 0x00000010
72 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
73 #define PEX_UNC_ERR_SEV_FCP 0x00002000
74 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
75 #define PEX_UNC_ERR_SEV_CA 0x00008000
76 #define PEX_UNC_ERR_SEV_UC 0x00010000
77 #define PEX_UNC_ERR_SEV_ROV 0x00020000
78 #define PEX_UNC_ERR_SEV_MLFP 0x00040000
79 #define PEX_UNC_ERR_SEV_ECRC 0x00080000
80 #define PEX_UNC_ERR_SEV_UR 0x00100000
81
82 #define ALC_EEPROM_LD 0x204 /* AR816x */
83 #define EEPROM_LD_START 0x00000001
84 #define EEPROM_LD_IDLE 0x00000010
85 #define EEPROM_LD_DONE 0x00000000
86 #define EEPROM_LD_PROGRESS 0x00000020
87 #define EEPROM_LD_EXIST 0x00000100
88 #define EEPROM_LD_EEPROM_EXIST 0x00000200
89 #define EEPROM_LD_FLASH_EXIST 0x00000400
90 #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000
91 #define EEPROM_LD_FLASH_END_ADDR_SHIFT 16
92
93 #define ALC_TWSI_CFG 0x218
94 #define TWSI_CFG_SW_LD_START 0x00000800
95 #define TWSI_CFG_HW_LD_START 0x00001000
96 #define TWSI_CFG_LD_EXIST 0x00400000
97
98 #define ALC_SLD 0x218 /* AR816x */
99 #define SLD_START 0x00000800
100 #define SLD_PROGRESS 0x00001000
101 #define SLD_IDLE 0x00002000
102 #define SLD_SLVADDR_MASK 0x007F0000
103 #define SLD_EXIST 0x00800000
104 #define SLD_FREQ_MASK 0x03000000
105 #define SLD_FREQ_100K 0x00000000
106 #define SLD_FREQ_200K 0x01000000
107 #define SLD_FREQ_300K 0x02000000
108 #define SLD_FREQ_400K 0x03000000
109
110 #define ALC_PCIE_PHYMISC 0x1000
111 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
112
113 #define ALC_PCIE_PHYMISC2 0x1004
114 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
115 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
116 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
117 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
118
119 #define ALC_PDLL_TRNS1 0x1104
120 #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800
121
122 #define ALC_TWSI_DEBUG 0x1108
123 #define TWSI_DEBUG_DEV_EXIST 0x20000000
124
125 #define ALC_EEPROM_CFG 0x12C0
126 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF
127 #define EEPROM_CFG_ADDR_MASK 0x03FF0000
128 #define EEPROM_CFG_ACK 0x40000000
129 #define EEPROM_CFG_RW 0x80000000
130 #define EEPROM_CFG_DATA_HI_SHIFT 0
131 #define EEPROM_CFG_ADDR_SHIFT 16
132
133 #define ALC_EEPROM_DATA_LO 0x12C4
134
135 #define ALC_OPT_CFG 0x12F0
136 #define OPT_CFG_CLK_ENB 0x00000002
137
138 #define ALC_PM_CFG 0x12F8
139 #define PM_CFG_SERDES_ENB 0x00000001
140 #define PM_CFG_RBER_ENB 0x00000002
141 #define PM_CFG_CLK_REQ_ENB 0x00000004
142 #define PM_CFG_ASPM_L1_ENB 0x00000008
143 #define PM_CFG_SERDES_L1_ENB 0x00000010
144 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020
145 #define PM_CFG_SERDES_PD_EX_L1 0x00000040
146 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
147 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
148 #define PM_CFG_RX_L1_AFTER_L0S 0x00000800
149 #define PM_CFG_ASPM_L0S_ENB 0x00001000
150 #define PM_CFG_CLK_SWH_L1 0x00002000
151 #define PM_CFG_CLK_PWM_VER1_1 0x00004000
152 #define PM_CFG_PCIE_RECV 0x00008000
153 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
154 #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000
155 #define PM_CFG_TX_L1_AFTER_L0S 0x00080000
156 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
157 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
158 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000
159 #define PM_CFG_SA_DLY_ENB 0x20000000
160 #define PM_CFG_MAC_ASPM_CHK 0x40000000
161 #define PM_CFG_HOTRST 0x80000000
162 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
163 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16
164 #define PM_CFG_PM_REQ_TIMER_SHIFT 20
165 #define PM_CFG_LCKDET_TIMER_SHIFT 24
166
167 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
168 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
169 #define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4
170 #define PM_CFG_LCKDET_TIMER_DEFAULT 12
171 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12
172 #define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15
173
174 #define ALC_LTSSM_ID_CFG 0x12FC
175 #define LTSSM_ID_WRO_ENB 0x00001000
176
177 #define ALC_MASTER_CFG 0x1400
178 #define MASTER_RESET 0x00000001
179 #define MASTER_TEST_MODE_MASK 0x0000000C
180 #define MASTER_BERT_START 0x00000010
181 #define MASTER_WAKEN_25M 0x00000020
182 #define MASTER_OOB_DIS_OFF 0x00000040
183 #define MASTER_SA_TIMER_ENB 0x00000080
184 #define MASTER_MTIMER_ENB 0x00000100
185 #define MASTER_MANUAL_INTR_ENB 0x00000200
186 #define MASTER_IM_TX_TIMER_ENB 0x00000400
187 #define MASTER_IM_RX_TIMER_ENB 0x00000800
188 #define MASTER_CLK_SEL_DIS 0x00001000
189 #define MASTER_CLK_SWH_MODE 0x00002000
190 #define MASTER_INTR_RD_CLR 0x00004000
191 #define MASTER_CHIP_REV_MASK 0x00FF0000
192 #define MASTER_CHIP_ID_MASK 0x7F000000
193 #define MASTER_OTP_SEL 0x80000000
194 #define MASTER_TEST_MODE_SHIFT 2
195 #define MASTER_CHIP_REV_SHIFT 16
196 #define MASTER_CHIP_ID_SHIFT 24
197
198 /* Number of ticks per usec for AR813x/AR815x. */
199 #define ALC_TICK_USECS 2
200 #define ALC_USECS(x) ((x) / ALC_TICK_USECS)
201
202 #define ALC_MANUAL_TIMER 0x1404
203
204 #define ALC_IM_TIMER 0x1408
205 #define IM_TIMER_TX_MASK 0x0000FFFF
206 #define IM_TIMER_RX_MASK 0xFFFF0000
207 #define IM_TIMER_TX_SHIFT 0
208 #define IM_TIMER_RX_SHIFT 16
209 #define ALC_IM_TIMER_MIN 0
210 #define ALC_IM_TIMER_MAX 130000 /* 130ms */
211 /*
212 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx
213 * interrupts in a second.
214 */
215 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */
216 /*
217 * alc(4) does not rely on Tx completion interrupts, so set it
218 * somewhat large value to reduce Tx completion interrupts.
219 */
220 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
221
222 #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */
223 #define GPHY_CFG_EXT_RESET 0x0001
224 #define GPHY_CFG_RTL_MODE 0x0002
225 #define GPHY_CFG_LED_MODE 0x0004
226 #define GPHY_CFG_ANEG_NOW 0x0008
227 #define GPHY_CFG_RECV_ANEG 0x0010
228 #define GPHY_CFG_GATE_25M_ENB 0x0020
229 #define GPHY_CFG_LPW_EXIT 0x0040
230 #define GPHY_CFG_PHY_IDDQ 0x0080
231 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100
232 #define GPHY_CFG_PCLK_SEL_DIS 0x0200
233 #define GPHY_CFG_HIB_EN 0x0400
234 #define GPHY_CFG_HIB_PULSE 0x0800
235 #define GPHY_CFG_SEL_ANA_RESET 0x1000
236 #define GPHY_CFG_PHY_PLL_ON 0x2000
237 #define GPHY_CFG_PWDOWN_HW 0x4000
238 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000
239 #define GPHY_CFG_100AB_ENB 0x00020000
240
241 #define ALC_IDLE_STATUS 0x1410
242 #define IDLE_STATUS_RXMAC 0x00000001
243 #define IDLE_STATUS_TXMAC 0x00000002
244 #define IDLE_STATUS_RXQ 0x00000004
245 #define IDLE_STATUS_TXQ 0x00000008
246 #define IDLE_STATUS_DMARD 0x00000010
247 #define IDLE_STATUS_DMAWR 0x00000020
248 #define IDLE_STATUS_SMB 0x00000040
249 #define IDLE_STATUS_CMB 0x00000080
250
251 #define ALC_MDIO 0x1414
252 #define MDIO_DATA_MASK 0x0000FFFF
253 #define MDIO_REG_ADDR_MASK 0x001F0000
254 #define MDIO_OP_READ 0x00200000
255 #define MDIO_OP_WRITE 0x00000000
256 #define MDIO_SUP_PREAMBLE 0x00400000
257 #define MDIO_OP_EXECUTE 0x00800000
258 #define MDIO_CLK_25_4 0x00000000
259 #define MDIO_CLK_25_6 0x02000000
260 #define MDIO_CLK_25_8 0x03000000
261 #define MDIO_CLK_25_10 0x04000000
262 #define MDIO_CLK_25_14 0x05000000
263 #define MDIO_CLK_25_20 0x06000000
264 #define MDIO_CLK_25_128 0x07000000
265 #define MDIO_OP_BUSY 0x08000000
266 #define MDIO_AP_ENB 0x10000000
267 #define MDIO_MODE_EXT 0x40000000
268 #define MDIO_DATA_SHIFT 0
269 #define MDIO_REG_ADDR_SHIFT 16
270
271 #define MDIO_REG_ADDR(x) \
272 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
273 /* Default PHY address. */
274 #define ALC_PHY_ADDR 0
275
276 #define ALC_PHY_STATUS 0x1418
277 #define PHY_STATUS_RECV_ENB 0x00000001
278 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF
279 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000
280 #define PHY_STATUS_LPW_STATE 0x80000000
281 #define PHY_STATIS_OE_PWSP_SHIFT 16
282
283 /* Packet memory BIST. */
284 #define ALC_BIST0 0x141C
285 #define BIST0_ENB 0x00000001
286 #define BIST0_SRAM_FAIL 0x00000002
287 #define BIST0_FUSE_FLAG 0x00000004
288
289 /* PCIe retry buffer BIST. */
290 #define ALC_BIST1 0x1420
291 #define BIST1_ENB 0x00000001
292 #define BIST1_SRAM_FAIL 0x00000002
293 #define BIST1_FUSE_FLAG 0x00000004
294
295 #define ALC_SERDES_LOCK 0x1424
296 #define SERDES_LOCK_DET 0x00000001
297 #define SERDES_LOCK_DET_ENB 0x00000002
298 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000
299 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000
300
301 #define ALC_LPI_CTL 0x1440
302 #define LPI_CTL_ENB 0x00000001
303
304 #define ALC_EXT_MDIO 0x1448
305 #define EXT_MDIO_REG_MASK 0x0000FFFF
306 #define EXT_MDIO_DEVADDR_MASK 0x001F0000
307 #define EXT_MDIO_REG_SHIFT 0
308 #define EXT_MDIO_DEVADDR_SHIFT 16
309
310 #define EXT_MDIO_REG(x) \
311 (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK)
312 #define EXT_MDIO_DEVADDR(x) \
313 (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK)
314
315 #define ALC_IDLE_DECISN_TIMER 0x1474
316 #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400
317
318 #define ALC_MAC_CFG 0x1480
319 #define MAC_CFG_TX_ENB 0x00000001
320 #define MAC_CFG_RX_ENB 0x00000002
321 #define MAC_CFG_TX_FC 0x00000004
322 #define MAC_CFG_RX_FC 0x00000008
323 #define MAC_CFG_LOOP 0x00000010
324 #define MAC_CFG_FULL_DUPLEX 0x00000020
325 #define MAC_CFG_TX_CRC_ENB 0x00000040
326 #define MAC_CFG_TX_AUTO_PAD 0x00000080
327 #define MAC_CFG_TX_LENCHK 0x00000100
328 #define MAC_CFG_RX_JUMBO_ENB 0x00000200
329 #define MAC_CFG_PREAMBLE_MASK 0x00003C00
330 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000
331 #define MAC_CFG_PROMISC 0x00008000
332 #define MAC_CFG_TX_PAUSE 0x00010000
333 #define MAC_CFG_SCNT 0x00020000
334 #define MAC_CFG_SYNC_RST_TX 0x00040000
335 #define MAC_CFG_SIM_RST_TX 0x00080000
336 #define MAC_CFG_SPEED_MASK 0x00300000
337 #define MAC_CFG_SPEED_10_100 0x00100000
338 #define MAC_CFG_SPEED_1000 0x00200000
339 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000
340 #define MAC_CFG_TX_JUMBO_ENB 0x00800000
341 #define MAC_CFG_RXCSUM_ENB 0x01000000
342 #define MAC_CFG_ALLMULTI 0x02000000
343 #define MAC_CFG_BCAST 0x04000000
344 #define MAC_CFG_DBG 0x08000000
345 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
346 #define MAC_CFG_HASH_ALG_CRC32 0x20000000
347 #define MAC_CFG_SPEED_MODE_SW 0x40000000
348 #define MAC_CFG_FAST_PAUSE 0x80000000
349 #define MAC_CFG_PREAMBLE_SHIFT 10
350 #define MAC_CFG_PREAMBLE_DEFAULT 7
351
352 #define ALC_IPG_IFG_CFG 0x1484
353 #define IPG_IFG_IPGT_MASK 0x0000007F
354 #define IPG_IFG_MIFG_MASK 0x0000FF00
355 #define IPG_IFG_IPG1_MASK 0x007F0000
356 #define IPG_IFG_IPG2_MASK 0x7F000000
357 #define IPG_IFG_IPGT_SHIFT 0
358 #define IPG_IFG_IPGT_DEFAULT 0x60
359 #define IPG_IFG_MIFG_SHIFT 8
360 #define IPG_IFG_MIFG_DEFAULT 0x50
361 #define IPG_IFG_IPG1_SHIFT 16
362 #define IPG_IFG_IPG1_DEFAULT 0x40
363 #define IPG_IFG_IPG2_SHIFT 24
364 #define IPG_IFG_IPG2_DEFAULT 0x60
365
366 /* Station address. */
367 #define ALC_PAR0 0x1488
368 #define ALC_PAR1 0x148C
369
370 /* 64bit multicast hash register. */
371 #define ALC_MAR0 0x1490
372 #define ALC_MAR1 0x1494
373
374 /* half-duplex parameter configuration. */
375 #define ALC_HDPX_CFG 0x1498
376 #define HDPX_CFG_LCOL_MASK 0x000003FF
377 #define HDPX_CFG_RETRY_MASK 0x0000F000
378 #define HDPX_CFG_EXC_DEF_EN 0x00010000
379 #define HDPX_CFG_NO_BACK_C 0x00020000
380 #define HDPX_CFG_NO_BACK_P 0x00040000
381 #define HDPX_CFG_ABEBE 0x00080000
382 #define HDPX_CFG_ABEBT_MASK 0x00F00000
383 #define HDPX_CFG_JAMIPG_MASK 0x0F000000
384 #define HDPX_CFG_LCOL_SHIFT 0
385 #define HDPX_CFG_LCOL_DEFAULT 0x37
386 #define HDPX_CFG_RETRY_SHIFT 12
387 #define HDPX_CFG_RETRY_DEFAULT 0x0F
388 #define HDPX_CFG_ABEBT_SHIFT 20
389 #define HDPX_CFG_ABEBT_DEFAULT 0x0A
390 #define HDPX_CFG_JAMIPG_SHIFT 24
391 #define HDPX_CFG_JAMIPG_DEFAULT 0x07
392
393 #define ALC_FRAME_SIZE 0x149C
394
395 #define ALC_WOL_CFG 0x14A0
396 #define WOL_CFG_PATTERN 0x00000001
397 #define WOL_CFG_PATTERN_ENB 0x00000002
398 #define WOL_CFG_MAGIC 0x00000004
399 #define WOL_CFG_MAGIC_ENB 0x00000008
400 #define WOL_CFG_LINK_CHG 0x00000010
401 #define WOL_CFG_LINK_CHG_ENB 0x00000020
402 #define WOL_CFG_PATTERN_DET 0x00000100
403 #define WOL_CFG_MAGIC_DET 0x00000200
404 #define WOL_CFG_LINK_CHG_DET 0x00000400
405 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000
406 #define WOL_CFG_PATTERN0 0x00010000
407 #define WOL_CFG_PATTERN1 0x00020000
408 #define WOL_CFG_PATTERN2 0x00040000
409 #define WOL_CFG_PATTERN3 0x00080000
410 #define WOL_CFG_PATTERN4 0x00100000
411 #define WOL_CFG_PATTERN5 0x00200000
412 #define WOL_CFG_PATTERN6 0x00400000
413
414 /* WOL pattern length. */
415 #define ALC_PATTERN_CFG0 0x14A4
416 #define PATTERN_CFG_0_LEN_MASK 0x0000007F
417 #define PATTERN_CFG_1_LEN_MASK 0x00007F00
418 #define PATTERN_CFG_2_LEN_MASK 0x007F0000
419 #define PATTERN_CFG_3_LEN_MASK 0x7F000000
420
421 #define ALC_PATTERN_CFG1 0x14A8
422 #define PATTERN_CFG_4_LEN_MASK 0x0000007F
423 #define PATTERN_CFG_5_LEN_MASK 0x00007F00
424 #define PATTERN_CFG_6_LEN_MASK 0x007F0000
425
426 /* RSS */
427 #define ALC_RSS_KEY0 0x14B0
428
429 #define ALC_RSS_KEY1 0x14B4
430
431 #define ALC_RSS_KEY2 0x14B8
432
433 #define ALC_RSS_KEY3 0x14BC
434
435 #define ALC_RSS_KEY4 0x14C0
436
437 #define ALC_RSS_KEY5 0x14C4
438
439 #define ALC_RSS_KEY6 0x14C8
440
441 #define ALC_RSS_KEY7 0x14CC
442
443 #define ALC_RSS_KEY8 0x14D0
444
445 #define ALC_RSS_KEY9 0x14D4
446
447 #define ALC_RSS_IDT_TABLE0 0x14E0
448
449 #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */
450
451 #define ALC_RSS_IDT_TABLE1 0x14E4
452
453 #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */
454
455 #define ALC_RSS_IDT_TABLE2 0x14E8
456
457 #define ALC_RSS_IDT_TABLE3 0x14EC
458
459 #define ALC_RSS_IDT_TABLE4 0x14F0
460
461 #define ALC_RSS_IDT_TABLE5 0x14F4
462
463 #define ALC_RSS_IDT_TABLE6 0x14F8
464
465 #define ALC_RSS_IDT_TABLE7 0x14FC
466
467 #define ALC_SRAM_RD0_ADDR 0x1500
468
469 #define ALC_SRAM_RD1_ADDR 0x1504
470
471 #define ALC_SRAM_RD2_ADDR 0x1508
472
473 #define ALC_SRAM_RD3_ADDR 0x150C
474
475 #define RD_HEAD_ADDR_MASK 0x000003FF
476 #define RD_TAIL_ADDR_MASK 0x03FF0000
477 #define RD_HEAD_ADDR_SHIFT 0
478 #define RD_TAIL_ADDR_SHIFT 16
479
480 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */
481 #define RD_NIC_LEN_MASK 0x000003FF
482
483 #define ALC_RD_NIC_LEN1 0x1514
484
485 #define ALC_SRAM_TD_ADDR 0x1518
486 #define TD_HEAD_ADDR_MASK 0x000003FF
487 #define TD_TAIL_ADDR_MASK 0x03FF0000
488 #define TD_HEAD_ADDR_SHIFT 0
489 #define TD_TAIL_ADDR_SHIFT 16
490
491 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */
492 #define SRAM_TD_LEN_MASK 0x000003FF
493
494 #define ALC_SRAM_RX_FIFO_ADDR 0x1520
495
496 #define ALC_SRAM_RX_FIFO_LEN 0x1524
497 #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF
498 #define SRAM_RX_FIFO_LEN_SHIFT 0
499
500 #define ALC_SRAM_TX_FIFO_ADDR 0x1528
501
502 #define ALC_SRAM_TX_FIFO_LEN 0x152C
503
504 #define ALC_SRAM_TCPH_ADDR 0x1530
505 #define SRAM_TCPH_ADDR_MASK 0x00000FFF
506 #define SRAM_PATH_ADDR_MASK 0x0FFF0000
507 #define SRAM_TCPH_ADDR_SHIFT 0
508 #define SRAM_PKTH_ADDR_SHIFT 16
509
510 #define ALC_DMA_BLOCK 0x1534
511 #define DMA_BLOCK_LOAD 0x00000001
512
513 #define ALC_RX_BASE_ADDR_HI 0x1540
514
515 #define ALC_TX_BASE_ADDR_HI 0x1544
516
517 #define ALC_SMB_BASE_ADDR_HI 0x1548
518
519 #define ALC_SMB_BASE_ADDR_LO 0x154C
520
521 #define ALC_RD0_HEAD_ADDR_LO 0x1550
522
523 #define ALC_RD1_HEAD_ADDR_LO 0x1554
524
525 #define ALC_RD2_HEAD_ADDR_LO 0x1558
526
527 #define ALC_RD3_HEAD_ADDR_LO 0x155C
528
529 #define ALC_RD_RING_CNT 0x1560
530 #define RD_RING_CNT_MASK 0x00000FFF
531 #define RD_RING_CNT_SHIFT 0
532
533 #define ALC_RX_BUF_SIZE 0x1564
534 #define RX_BUF_SIZE_MASK 0x0000FFFF
535 /*
536 * If larger buffer size than 1536 is specified the controller
537 * will be locked up. This is hardware limitation.
538 */
539 #define RX_BUF_SIZE_MAX 1536
540
541 #define ALC_RRD0_HEAD_ADDR_LO 0x1568
542
543 #define ALC_RRD1_HEAD_ADDR_LO 0x156C
544
545 #define ALC_RRD2_HEAD_ADDR_LO 0x1570
546
547 #define ALC_RRD3_HEAD_ADDR_LO 0x1574
548
549 #define ALC_RRD_RING_CNT 0x1578
550 #define RRD_RING_CNT_MASK 0x00000FFF
551 #define RRD_RING_CNT_SHIFT 0
552
553 #define ALC_TDH_HEAD_ADDR_LO 0x157C
554
555 #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */
556
557 #define ALC_TDL_HEAD_ADDR_LO 0x1580
558
559 #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */
560
561 #define ALC_TD_RING_CNT 0x1584
562 #define TD_RING_CNT_MASK 0x0000FFFF
563 #define TD_RING_CNT_SHIFT 0
564
565 #define ALC_CMB_BASE_ADDR_LO 0x1588
566
567 #define ALC_TXQ_CFG 0x1590
568 #define TXQ_CFG_TD_BURST_MASK 0x0000000F
569 #define TXQ_CFG_IP_OPTION_ENB 0x00000010
570 #define TXQ_CFG_ENB 0x00000020
571 #define TXQ_CFG_ENHANCED_MODE 0x00000040
572 #define TXQ_CFG_8023_ENB 0x00000080
573 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
574 #define TXQ_CFG_TD_BURST_SHIFT 0
575 #define TXQ_CFG_TD_BURST_DEFAULT 5
576 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
577
578 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
579 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF
580 #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800
581 #define TSO_OFFLOAD_THRESH_SHIFT 0
582 #define TSO_OFFLOAD_THRESH_UNIT 8
583 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3
584
585 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */
586 #define TXF_WATER_MARK_HI_MASK 0x00000FFF
587 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000
588 #define TXF_WATER_MARK_BURST_ENB 0x80000000
589 #define TXF_WATER_MARK_LO_SHIFT 0
590 #define TXF_WATER_MARK_HI_SHIFT 16
591
592 #define ALC_THROUGHPUT_MON 0x159C
593 #define THROUGHPUT_MON_RATE_MASK 0x00000003
594 #define THROUGHPUT_MON_ENB 0x00000080
595 #define THROUGHPUT_MON_RATE_SHIFT 0
596
597 #define ALC_RXQ_CFG 0x15A0
598 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003
599 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000
600 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001
601 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002
602 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003
603 #define RXQ_CFG_QUEUE1_ENB 0x00000010
604 #define RXQ_CFG_QUEUE2_ENB 0x00000020
605 #define RXQ_CFG_QUEUE3_ENB 0x00000040
606 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080
607 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00
608 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000
609 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000
610 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000
611 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000
612 #define RXQ_CFG_RD_BURST_MASK 0x03F00000
613 #define RXQ_CFG_RSS_MODE_DIS 0x00000000
614 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000
615 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000
616 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000
617 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000
618 #define RXQ_CFG_RSS_HASH_ENB 0x20000000
619 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
620 #define RXQ_CFG_QUEUE0_ENB 0x80000000
621 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8
622 #define RXQ_CFG_RD_BURST_DEFAULT 8
623 #define RXQ_CFG_RD_BURST_SHIFT 20
624 #define RXQ_CFG_ENB \
625 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \
626 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
627
628 /* AR816x specific bits */
629 #define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004
630 #define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008
631 #define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010
632 #define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020
633 #define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C
634 #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080
635 #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00
636 #define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8
637 #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100
638
639 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
640 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
641 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
642 #define RX_RD_FREE_THRESH_HI_SHIFT 0
643 #define RX_RD_FREE_THRESH_LO_SHIFT 6
644 #define RX_RD_FREE_THRESH_HI_DEFAULT 16
645 #define RX_RD_FREE_THRESH_LO_DEFAULT 8
646
647 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8
648 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
649 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
650 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
651 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16
652 /*
653 * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
654 * rx-packet(1522) + delay-of-link(64)
655 * = 3212.
656 */
657 #define RX_FIFO_PAUSE_816X_RSVD 3212
658
659 #define ALC_RD_DMA_CFG 0x15AC
660 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
661 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000
662 #define RD_DMA_CFG_THRESH_SHIFT 0
663 #define RD_DMA_CFG_TIMER_SHIFT 16
664 #define RD_DMA_CFG_THRESH_DEFAULT 0x100
665 #define RD_DMA_CFG_TIMER_DEFAULT 0
666 #define RD_DMA_CFG_TICK_USECS 8
667 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS)
668
669 #define ALC_RSS_HASH_VALUE 0x15B0
670
671 #define ALC_RSS_HASH_FLAG 0x15B4
672
673 #define ALC_RSS_CPU 0x15B8
674
675 #define ALC_DMA_CFG 0x15C0
676 #define DMA_CFG_IN_ORDER 0x00000001
677 #define DMA_CFG_ENH_ORDER 0x00000002
678 #define DMA_CFG_OUT_ORDER 0x00000004
679 #define DMA_CFG_RCB_64 0x00000000
680 #define DMA_CFG_RCB_128 0x00000008
681 #define DMA_CFG_PEND_AUTO_RST 0x00000008
682 #define DMA_CFG_RD_BURST_128 0x00000000
683 #define DMA_CFG_RD_BURST_256 0x00000010
684 #define DMA_CFG_RD_BURST_512 0x00000020
685 #define DMA_CFG_RD_BURST_1024 0x00000030
686 #define DMA_CFG_RD_BURST_2048 0x00000040
687 #define DMA_CFG_RD_BURST_4096 0x00000050
688 #define DMA_CFG_WR_BURST_128 0x00000000
689 #define DMA_CFG_WR_BURST_256 0x00000080
690 #define DMA_CFG_WR_BURST_512 0x00000100
691 #define DMA_CFG_WR_BURST_1024 0x00000180
692 #define DMA_CFG_WR_BURST_2048 0x00000200
693 #define DMA_CFG_WR_BURST_4096 0x00000280
694 #define DMA_CFG_RD_REQ_PRI 0x00000400
695 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
696 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
697 #define DMA_CFG_CMB_ENB 0x00100000
698 #define DMA_CFG_SMB_ENB 0x00200000
699 #define DMA_CFG_CMB_NOW 0x00400000
700 #define DMA_CFG_SMB_DIS 0x01000000
701 #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000
702 #define DMA_CFG_RD_CHNL_SEL_1 0x00000000
703 #define DMA_CFG_RD_CHNL_SEL_2 0x04000000
704 #define DMA_CFG_RD_CHNL_SEL_3 0x08000000
705 #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000
706 #define DMA_CFG_WSRAM_RDCTL 0x10000000
707 #define DMA_CFG_RD_PEND_CLR 0x20000000
708 #define DMA_CFG_WR_PEND_CLR 0x40000000
709 #define DMA_CFG_SMB_NOW 0x80000000
710 #define DMA_CFG_RD_BURST_MASK 0x07
711 #define DMA_CFG_RD_BURST_SHIFT 4
712 #define DMA_CFG_WR_BURST_MASK 0x07
713 #define DMA_CFG_WR_BURST_SHIFT 7
714 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11
715 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16
716 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
717 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
718
719 #define ALC_SMB_STAT_TIMER 0x15C4
720 #define SMB_STAT_TIMER_MASK 0x00FFFFFF
721 #define SMB_STAT_TIMER_SHIFT 0
722
723 #define ALC_CMB_TD_THRESH 0x15C8
724 #define CMB_TD_THRESH_MASK 0x0000FFFF
725 #define CMB_TD_THRESH_SHIFT 0
726
727 #define ALC_CMB_TX_TIMER 0x15CC
728 #define CMB_TX_TIMER_MASK 0x0000FFFF
729 #define CMB_TX_TIMER_SHIFT 0
730
731 #define ALC_MSI_MAP_TBL1 0x15D0
732
733 #define ALC_MSI_ID_MAP 0x15D4
734
735 #define ALC_MSI_MAP_TBL2 0x15D8
736
737 #define ALC_MBOX_RD0_PROD_IDX 0x15E0
738
739 #define ALC_MBOX_RD1_PROD_IDX 0x15E4
740
741 #define ALC_MBOX_RD2_PROD_IDX 0x15E8
742
743 #define ALC_MBOX_RD3_PROD_IDX 0x15EC
744
745 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF
746 #define MBOX_RD_PROD_SHIFT 0
747
748 #define ALC_MBOX_TD_PROD_IDX 0x15F0
749 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
750 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
751 #define MBOX_TD_PROD_HI_IDX_SHIFT 0
752 #define MBOX_TD_PROD_LO_IDX_SHIFT 16
753
754 #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */
755
756 #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */
757
758 #define ALC_MBOX_TD_CONS_IDX 0x15F4
759 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
760 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
761 #define MBOX_TD_CONS_HI_IDX_SHIFT 0
762 #define MBOX_TD_CONS_LO_IDX_SHIFT 16
763
764 #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */
765
766 #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */
767
768 #define ALC_MBOX_RD01_CONS_IDX 0x15F8
769 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
770 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
771 #define MBOX_RD0_CONS_IDX_SHIFT 0
772 #define MBOX_RD1_CONS_IDX_SHIFT 16
773
774 #define ALC_MBOX_RD23_CONS_IDX 0x15FC
775 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
776 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
777 #define MBOX_RD2_CONS_IDX_SHIFT 0
778 #define MBOX_RD3_CONS_IDX_SHIFT 16
779
780 #define ALC_INTR_STATUS 0x1600
781 #define INTR_SMB 0x00000001
782 #define INTR_TIMER 0x00000002
783 #define INTR_MANUAL_TIMER 0x00000004
784 #define INTR_RX_FIFO_OFLOW 0x00000008
785 #define INTR_RD0_UNDERRUN 0x00000010
786 #define INTR_RD1_UNDERRUN 0x00000020
787 #define INTR_RD2_UNDERRUN 0x00000040
788 #define INTR_RD3_UNDERRUN 0x00000080
789 #define INTR_TX_FIFO_UNDERRUN 0x00000100
790 #define INTR_DMA_RD_TO_RST 0x00000200
791 #define INTR_DMA_WR_TO_RST 0x00000400
792 #define INTR_TX_CREDIT 0x00000800
793 #define INTR_GPHY 0x00001000
794 #define INTR_GPHY_LOW_PW 0x00002000
795 #define INTR_TXQ_TO_RST 0x00004000
796 #define INTR_TX_PKT0 0x00008000
797 #define INTR_RX_PKT0 0x00010000
798 #define INTR_RX_PKT1 0x00020000
799 #define INTR_RX_PKT2 0x00040000
800 #define INTR_RX_PKT3 0x00080000
801 #define INTR_MAC_RX 0x00100000
802 #define INTR_MAC_TX 0x00200000
803 #define INTR_UNDERRUN 0x00400000
804 #define INTR_FRAME_ERROR 0x00800000
805 #define INTR_FRAME_OK 0x01000000
806 #define INTR_CSUM_ERROR 0x02000000
807 #define INTR_PHY_LINK_DOWN 0x04000000
808 #define INTR_DIS_INT 0x80000000
809
810 /* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */
811 #define INTR_TX_PKT1 0x00000020
812 #define INTR_TX_PKT2 0x00000040
813 #define INTR_TX_PKT3 0x00000080
814 #define INTR_RX_PKT4 0x08000000
815 #define INTR_RX_PKT5 0x10000000
816 #define INTR_RX_PKT6 0x20000000
817 #define INTR_RX_PKT7 0x40000000
818
819 /* Interrupt Mask Register */
820 #define ALC_INTR_MASK 0x1604
821
822 #ifdef notyet
823 #define INTR_RX_PKT \
824 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \
825 INTR_RX_PKT3)
826 #define INTR_RD_UNDERRUN \
827 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \
828 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
829 #else
830 #define INTR_TX_PKT INTR_TX_PKT0
831 #define INTR_RX_PKT INTR_RX_PKT0
832 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN
833 #endif
834
835 #define ALC_INTRS \
836 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
837 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \
838 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \
839 INTR_TX_FIFO_UNDERRUN)
840
841 #define ALC_INTR_RETRIG_TIMER 0x1608
842 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF
843 #define INTR_RETRIG_TIMER_SHIFT 0
844
845 #define ALC_HDS_CFG 0x160C
846 #define HDS_CFG_ENB 0x00000001
847 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
848 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
849 #define HDS_CFG_BACKFILLSIZE_SHIFT 8
850 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
851
852 #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */
853
854 #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */
855
856 #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */
857
858 #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */
859
860 /* AR813x/AR815x registers for MAC statistics */
861 #define ALC_RX_MIB_BASE 0x1700
862
863 #define ALC_TX_MIB_BASE 0x1760
864
865 #define ALC_DRV 0x1804 /* AR816x */
866 #define DRV_ASPM_SPD10LMT_1M 0x00000000
867 #define DRV_ASPM_SPD10LMT_10M 0x00000001
868 #define DRV_ASPM_SPD10LMT_100M 0x00000002
869 #define DRV_ASPM_SPD10LMT_NO 0x00000003
870 #define DRV_ASPM_SPD10LMT_MASK 0x00000003
871 #define DRV_ASPM_SPD100LMT_1M 0x00000000
872 #define DRV_ASPM_SPD100LMT_10M 0x00000004
873 #define DRV_ASPM_SPD100LMT_100M 0x00000008
874 #define DRV_ASPM_SPD100LMT_NO 0x0000000C
875 #define DRV_ASPM_SPD100LMT_MASK 0x0000000C
876 #define DRV_ASPM_SPD1000LMT_100M 0x00000000
877 #define DRV_ASPM_SPD1000LMT_NO 0x00000010
878 #define DRV_ASPM_SPD1000LMT_1M 0x00000020
879 #define DRV_ASPM_SPD1000LMT_10M 0x00000030
880 #define DRV_ASPM_SPD1000LMT_MASK 0x00000000
881 #define DRV_WOLCAP_BIOS_EN 0x00000100
882 #define DRV_WOLMAGIC_EN 0x00000200
883 #define DRV_WOLLINKUP_EN 0x00000400
884 #define DRV_WOLPATTERN_EN 0x00000800
885 #define DRV_AZ_EN 0x00001000
886 #define DRV_WOLS5_BIOS_EN 0x00010000
887 #define DRV_WOLS5_EN 0x00020000
888 #define DRV_DISABLE 0x00040000
889 #define DRV_PHY_MASK 0x1FE00000
890 #define DRV_PHY_EEE 0x00200000
891 #define DRV_PHY_APAUSE 0x00400000
892 #define DRV_PHY_PAUSE 0x00800000
893 #define DRV_PHY_DUPLEX 0x01000000
894 #define DRV_PHY_10 0x02000000
895 #define DRV_PHY_100 0x04000000
896 #define DRV_PHY_1000 0x08000000
897 #define DRV_PHY_AUTO 0x10000000
898 #define DRV_PHY_SHIFT 21
899
900 #define ALC_CLK_GATING_CFG 0x1814
901 #define CLK_GATING_DMAW_ENB 0x0001
902 #define CLK_GATING_DMAR_ENB 0x0002
903 #define CLK_GATING_TXQ_ENB 0x0004
904 #define CLK_GATING_RXQ_ENB 0x0008
905 #define CLK_GATING_TXMAC_ENB 0x0010
906 #define CLK_GATING_RXMAC_ENB 0x0020
907
908 #define ALC_DEBUG_DATA0 0x1900
909
910 #define ALC_DEBUG_DATA1 0x1904
911
912 #define ALC_MSI_RETRANS_TIMER 0x1920
913 #define MSI_RETRANS_TIMER_MASK 0x0000FFFF
914 #define MSI_RETRANS_MASK_SEL_STD 0x00000000
915 #define MSI_RETRANS_MASK_SEL_LINE 0x00010000
916 #define MSI_RETRANS_TIMER_SHIFT 0
917
918 #define ALC_WRR 0x1938
919 #define WRR_PRI0_MASK 0x0000001F
920 #define WRR_PRI1_MASK 0x00001F00
921 #define WRR_PRI2_MASK 0x001F0000
922 #define WRR_PRI3_MASK 0x1F000000
923 #define WRR_PRI_RESTRICT_MASK 0x60000000
924 #define WRR_PRI_RESTRICT_ALL 0x00000000
925 #define WRR_PRI_RESTRICT_HI 0x20000000
926 #define WRR_PRI_RESTRICT_HI2 0x40000000
927 #define WRR_PRI_RESTRICT_NONE 0x60000000
928 #define WRR_PRI0_SHIFT 0
929 #define WRR_PRI1_SHIFT 8
930 #define WRR_PRI2_SHIFT 16
931 #define WRR_PRI3_SHIFT 24
932 #define WRR_PRI_DEFAULT 4
933 #define WRR_PRI_RESTRICT_SHIFT 29
934
935 #define ALC_HQTD_CFG 0x193C
936 #define HQTD_CFG_Q1_BURST_MASK 0x0000000F
937 #define HQTD_CFG_Q2_BURST_MASK 0x000000F0
938 #define HQTD_CFG_Q3_BURST_MASK 0x00000F00
939 #define HQTD_CFG_BURST_ENB 0x80000000
940 #define HQTD_CFG_Q1_BURST_SHIFT 0
941 #define HQTD_CFG_Q2_BURST_SHIFT 4
942 #define HQTD_CFG_Q3_BURST_SHIFT 8
943
944 #define ALC_MISC 0x19C0
945 #define MISC_INTNLOSC_OPEN 0x00000008
946 #define MISC_ISO_ENB 0x00001000
947 #define MISC_PSW_OCP_MASK 0x00E00000
948 #define MISC_PSW_OCP_SHIFT 21
949 #define MISC_PSW_OCP_DEFAULT 7
950
951 #define ALC_MISC2 0x19C8
952 #define MISC2_CALB_START 0x00000001
953
954 #define ALC_MISC3 0x19CC
955 #define MISC3_25M_NOTO_INTNL 0x00000001
956 #define MISC3_25M_BY_SW 0x00000002
957
958 #define ALC_MII_DBG_ADDR 0x1D
959 #define ALC_MII_DBG_DATA 0x1E
960
961 #define MII_ANA_CFG0 0x00
962 #define ANA_RESTART_CAL 0x0001
963 #define ANA_MANUL_SWICH_ON_MASK 0x001E
964 #define ANA_MAN_ENABLE 0x0020
965 #define ANA_SEL_HSP 0x0040
966 #define ANA_EN_HB 0x0080
967 #define ANA_EN_HBIAS 0x0100
968 #define ANA_OEN_125M 0x0200
969 #define ANA_EN_LCKDT 0x0400
970 #define ANA_LCKDT_PHY 0x0800
971 #define ANA_AFE_MODE 0x1000
972 #define ANA_VCO_SLOW 0x2000
973 #define ANA_VCO_FAST 0x4000
974 #define ANA_SEL_CLK125M_DSP 0x8000
975 #define ANA_MANUL_SWICH_ON_SHIFT 1
976
977 #define MII_DBG_ANACTL 0x00
978 #define DBG_ANACTL_DEFAULT 0x02EF
979
980 #define MII_ANA_CFG4 0x04
981 #define ANA_IECHO_ADJ_MASK 0x0F
982 #define ANA_IECHO_ADJ_3_MASK 0x000F
983 #define ANA_IECHO_ADJ_2_MASK 0x00F0
984 #define ANA_IECHO_ADJ_1_MASK 0x0F00
985 #define ANA_IECHO_ADJ_0_MASK 0xF000
986 #define ANA_IECHO_ADJ_3_SHIFT 0
987 #define ANA_IECHO_ADJ_2_SHIFT 4
988 #define ANA_IECHO_ADJ_1_SHIFT 8
989 #define ANA_IECHO_ADJ_0_SHIFT 12
990
991 #define MII_DBG_SYSMODCTL 0x04
992 #define DBG_SYSMODCTL_DEFAULT 0xBB8B
993
994 #define MII_ANA_CFG5 0x05
995 #define ANA_SERDES_CDR_BW_MASK 0x0003
996 #define ANA_MS_PAD_DBG 0x0004
997 #define ANA_SPEEDUP_DBG 0x0008
998 #define ANA_SERDES_TH_LOS_MASK 0x0030
999 #define ANA_SERDES_EN_DEEM 0x0040
1000 #define ANA_SERDES_TXELECIDLE 0x0080
1001 #define ANA_SERDES_BEACON 0x0100
1002 #define ANA_SERDES_HALFTXDR 0x0200
1003 #define ANA_SERDES_SEL_HSP 0x0400
1004 #define ANA_SERDES_EN_PLL 0x0800
1005 #define ANA_SERDES_EN 0x1000
1006 #define ANA_SERDES_EN_LCKDT 0x2000
1007 #define ANA_SERDES_CDR_BW_SHIFT 0
1008 #define ANA_SERDES_TH_LOS_SHIFT 4
1009
1010 #define MII_DBG_SRDSYSMOD 0x05
1011 #define DBG_SRDSYSMOD_DEFAULT 0x2C46
1012
1013 #define MII_ANA_CFG11 0x0B
1014 #define ANA_PS_HIB_EN 0x8000
1015
1016 #define MII_DBG_HIBNEG 0x0B
1017 #define DBG_HIBNEG_HIB_PULSE 0x1000
1018 #define DBG_HIBNEG_PSHIB_EN 0x8000
1019 #define DBG_HIBNEG_DEFAULT 0xBC40
1020
1021 #define MII_ANA_CFG18 0x12
1022 #define ANA_TEST_MODE_10BT_01MASK 0x0003
1023 #define ANA_LOOP_SEL_10BT 0x0004
1024 #define ANA_RGMII_MODE_SW 0x0008
1025 #define ANA_EN_LONGECABLE 0x0010
1026 #define ANA_TEST_MODE_10BT_2 0x0020
1027 #define ANA_EN_10BT_IDLE 0x0400
1028 #define ANA_EN_MASK_TB 0x0800
1029 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
1030 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
1031 #define ANA_TEST_MODE_10BT_01SHIFT 0
1032 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12
1033 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14
1034
1035 #define MII_DBG_TST10BTCFG 0x12
1036 #define DBG_TST10BTCFG_DEFAULT 0x4C04
1037
1038 #define MII_DBG_AZ_ANADECT 0x15
1039 #define DBG_AZ_ANADECT_DEFAULT 0x3220
1040 #define DBG_AZ_ANADECT_LONG 0x3210
1041
1042 #define MII_DBG_MSE16DB 0x18
1043 #define DBG_MSE16DB_UP 0x05EA
1044 #define DBG_MSE16DB_DOWN 0x02EA
1045
1046 #define MII_DBG_MSE20DB 0x1C
1047 #define DBG_MSE20DB_TH_MASK 0x01FC
1048 #define DBG_MSE20DB_TH_DEFAULT 0x2E
1049 #define DBG_MSE20DB_TH_HI 0x54
1050 #define DBG_MSE20DB_TH_SHIFT 2
1051
1052 #define MII_DBG_AGC 0x23
1053 #define DBG_AGC_2_VGA_MASK 0x3F00
1054 #define DBG_AGC_2_VGA_SHIFT 8
1055 #define DBG_AGC_LONG1G_LIMT 40
1056 #define DBG_AGC_LONG100M_LIMT 44
1057
1058 #define MII_ANA_CFG41 0x29
1059 #define ANA_TOP_PS_EN 0x8000
1060
1061 #define MII_DBG_LEGCYPS 0x29
1062 #define DBG_LEGCYPS_ENB 0x8000
1063 #define DBG_LEGCYPS_DEFAULT 0x129D
1064
1065 #define MII_ANA_CFG54 0x36
1066 #define ANA_LONG_CABLE_TH_100_MASK 0x003F
1067 #define ANA_DESERVED 0x0040
1068 #define ANA_EN_LIT_CH 0x0080
1069 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
1070 #define ANA_BP_BAD_LINK_ACCUM 0x4000
1071 #define ANA_BP_SMALL_BW 0x8000
1072 #define ANA_LONG_CABLE_TH_100_SHIFT 0
1073 #define ANA_SHORT_CABLE_TH_100_SHIFT 8
1074
1075 #define MII_DBG_TST100BTCFG 0x36
1076 #define DBG_TST100BTCFG_DEFAULT 0xE12C
1077
1078 #define MII_DBG_GREENCFG 0x3B
1079 #define DBG_GREENCFG_DEFAULT 0x7078
1080
1081 #define MII_DBG_GREENCFG2 0x3D
1082 #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080
1083 #define DBG_GREENCFG2_BP_GREEN 0x8000
1084
1085 /* Device addr 3 */
1086 #define MII_EXT_PCS 3
1087
1088 #define MII_EXT_CLDCTL3 0x8003
1089 #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000
1090
1091 #define MII_EXT_CLDCTL5 0x8005
1092 #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000
1093
1094 #define MII_EXT_CLDCTL6 0x8006
1095 #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF
1096 #define EXT_CLDCTL6_CAB_LEN_SHIFT 0
1097 #define EXT_CLDCTL6_CAB_LEN_SHORT1G 116
1098 #define EXT_CLDCTL6_CAB_LEN_SHORT100M 152
1099
1100 #define MII_EXT_VDRVBIAS 0x8062
1101 #define EXT_VDRVBIAS_DEFAULT 3
1102
1103 /* Device addr 7 */
1104 #define MII_EXT_ANEG 7
1105
1106 #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C
1107 #define ANEG_LOCA_EEEADV_100BT 0x0002
1108 #define ANEG_LOCA_EEEADV_1000BT 0x0004
1109
1110 #define MII_EXT_ANEG_AFE 0x801A
1111 #define ANEG_AFEE_10BT_100M_TH 0x0040
1112
1113 #define MII_EXT_ANEG_S3DIG10 0x8023
1114 #define ANEG_S3DIG10_SL 0x0001
1115 #define ANEG_S3DIG10_DEFAULT 0
1116
1117 #define MII_EXT_ANEG_NLP78 0x8027
1118 #define ANEG_NLP78_120M_DEFAULT 0x8A05
1119
1120 /* Statistics counters collected by the MAC. */
1121 struct smb {
1122 /* Rx stats. */
1123 uint32_t rx_frames;
1124 uint32_t rx_bcast_frames;
1125 uint32_t rx_mcast_frames;
1126 uint32_t rx_pause_frames;
1127 uint32_t rx_control_frames;
1128 uint32_t rx_crcerrs;
1129 uint32_t rx_lenerrs;
1130 uint32_t rx_bytes;
1131 uint32_t rx_runts;
1132 uint32_t rx_fragments;
1133 uint32_t rx_pkts_64;
1134 uint32_t rx_pkts_65_127;
1135 uint32_t rx_pkts_128_255;
1136 uint32_t rx_pkts_256_511;
1137 uint32_t rx_pkts_512_1023;
1138 uint32_t rx_pkts_1024_1518;
1139 uint32_t rx_pkts_1519_max;
1140 uint32_t rx_pkts_truncated;
1141 uint32_t rx_fifo_oflows;
1142 uint32_t rx_rrs_errs;
1143 uint32_t rx_alignerrs;
1144 uint32_t rx_bcast_bytes;
1145 uint32_t rx_mcast_bytes;
1146 uint32_t rx_pkts_filtered;
1147 /* Tx stats. */
1148 uint32_t tx_frames;
1149 uint32_t tx_bcast_frames;
1150 uint32_t tx_mcast_frames;
1151 uint32_t tx_pause_frames;
1152 uint32_t tx_excess_defer;
1153 uint32_t tx_control_frames;
1154 uint32_t tx_deferred;
1155 uint32_t tx_bytes;
1156 uint32_t tx_pkts_64;
1157 uint32_t tx_pkts_65_127;
1158 uint32_t tx_pkts_128_255;
1159 uint32_t tx_pkts_256_511;
1160 uint32_t tx_pkts_512_1023;
1161 uint32_t tx_pkts_1024_1518;
1162 uint32_t tx_pkts_1519_max;
1163 uint32_t tx_single_colls;
1164 uint32_t tx_multi_colls;
1165 uint32_t tx_late_colls;
1166 uint32_t tx_excess_colls;
1167 uint32_t tx_underrun;
1168 uint32_t tx_desc_underrun;
1169 uint32_t tx_lenerrs;
1170 uint32_t tx_pkts_truncated;
1171 uint32_t tx_bcast_bytes;
1172 uint32_t tx_mcast_bytes;
1173 uint32_t updated;
1174 };
1175
1176 /* CMB(Coalesing message block) */
1177 struct cmb {
1178 uint32_t cons;
1179 };
1180
1181 /* Rx free descriptor */
1182 struct rx_desc {
1183 uint64_t addr;
1184 };
1185
1186 /* Rx return descriptor */
1187 struct rx_rdesc {
1188 uint32_t rdinfo;
1189 #define RRD_CSUM_MASK 0x0000FFFF
1190 #define RRD_RD_CNT_MASK 0x000F0000
1191 #define RRD_RD_IDX_MASK 0xFFF00000
1192 #define RRD_CSUM_SHIFT 0
1193 #define RRD_RD_CNT_SHIFT 16
1194 #define RRD_RD_IDX_SHIFT 20
1195 #define RRD_CSUM(x) \
1196 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT)
1197 #define RRD_RD_CNT(x) \
1198 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT)
1199 #define RRD_RD_IDX(x) \
1200 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT)
1201 uint32_t rss;
1202 uint32_t vtag;
1203 #define RRD_VLAN_MASK 0x0000FFFF
1204 #define RRD_HEAD_LEN_MASK 0x00FF0000
1205 #define RRD_HDS_MASK 0x03000000
1206 #define RRD_HDS_NONE 0x00000000
1207 #define RRD_HDS_HEAD 0x01000000
1208 #define RRD_HDS_DATA 0x02000000
1209 #define RRD_CPU_MASK 0x0C000000
1210 #define RRD_HASH_FLAG_MASK 0xF0000000
1211 #define RRD_VLAN_SHIFT 0
1212 #define RRD_HEAD_LEN_SHIFT 16
1213 #define RRD_HDS_SHIFT 24
1214 #define RRD_CPU_SHIFT 26
1215 #define RRD_HASH_FLAG_SHIFT 28
1216 #define RRD_VLAN(x) \
1217 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT)
1218 #define RRD_HEAD_LEN(x) \
1219 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT)
1220 #define RRD_CPU(x) \
1221 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT)
1222 uint32_t status;
1223 #define RRD_LEN_MASK 0x00003FFF
1224 #define RRD_LEN_SHIFT 0
1225 #define RRD_TCP_UDPCSUM_NOK 0x00004000
1226 #define RRD_IPCSUM_NOK 0x00008000
1227 #define RRD_VLAN_TAG 0x00010000
1228 #define RRD_PROTO_MASK 0x000E0000
1229 #define RRD_PROTO_IPV4 0x00020000
1230 #define RRD_PROTO_IPV6 0x000C0000
1231 #define RRD_ERR_SUM 0x00100000
1232 #define RRD_ERR_CRC 0x00200000
1233 #define RRD_ERR_ALIGN 0x00400000
1234 #define RRD_ERR_TRUNC 0x00800000
1235 #define RRD_ERR_RUNT 0x01000000
1236 #define RRD_ERR_ICMP 0x02000000
1237 #define RRD_BCAST 0x04000000
1238 #define RRD_MCAST 0x08000000
1239 #define RRD_SNAP_LLC 0x10000000
1240 #define RRD_ETHER 0x00000000
1241 #define RRD_FIFO_FULL 0x20000000
1242 #define RRD_ERR_LENGTH 0x40000000
1243 #define RRD_VALID 0x80000000
1244 #define RRD_BYTES(x) \
1245 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT)
1246 #define RRD_IPV4(x) \
1247 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4)
1248 };
1249
1250 /* Tx descriptor */
1251 struct tx_desc {
1252 uint32_t len;
1253 #define TD_BUFLEN_MASK 0x00003FFF
1254 #define TD_VLAN_MASK 0xFFFF0000
1255 #define TD_BUFLEN_SHIFT 0
1256 #define TX_BYTES(x) \
1257 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK)
1258 #define TD_VLAN_SHIFT 16
1259 uint32_t flags;
1260 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */
1261 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */
1262 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */
1263 #define TD_CUSTOM_CSUM 0x00000100
1264 #define TD_IPCSUM 0x00000200
1265 #define TD_TCPCSUM 0x00000400
1266 #define TD_UDPCSUM 0x00000800
1267 #define TD_TSO 0x00001000
1268 #define TD_TSO_DESCV1 0x00000000
1269 #define TD_TSO_DESCV2 0x00002000
1270 #define TD_CON_VLAN_TAG 0x00004000
1271 #define TD_INS_VLAN_TAG 0x00008000
1272 #define TD_IPV4_DESCV2 0x00010000
1273 #define TD_LLC_SNAP 0x00020000
1274 #define TD_ETHERNET 0x00000000
1275 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */
1276 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000
1277 #define TD_MSS_MASK 0x7FFC0000
1278 #define TD_EOP 0x80000000
1279 #define TD_L4HDR_OFFSET_SHIFT 0
1280 #define TD_TCPHDR_OFFSET_SHIFT 0
1281 #define TD_PLOAD_OFFSET_SHIFT 0
1282 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18
1283 #define TD_MSS_SHIFT 18
1284 uint64_t addr;
1285 };
1286
1287 #endif /* _IF_ALCREG_H */
Cache object: 22de7486c069c15304cbd9979ee83c83
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