FreeBSD/Linux Kernel Cross Reference
sys/dev/ale/if_ale.c
1 /*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/mbuf.h>
40 #include <sys/module.h>
41 #include <sys/rman.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
47
48 #include <net/bpf.h>
49 #include <net/if.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
62
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
71
72 #include <dev/ale/if_alereg.h>
73 #include <dev/ale/if_alevar.h>
74
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
77
78 /* For more information about Tx checksum offload issues see ale_encap(). */
79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
80
81 MODULE_DEPEND(ale, pci, 1, 1, 1);
82 MODULE_DEPEND(ale, ether, 1, 1, 1);
83 MODULE_DEPEND(ale, miibus, 1, 1, 1);
84
85 /* Tunables. */
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
90
91 /*
92 * Devices supported by this driver.
93 */
94 static const struct ale_dev {
95 uint16_t ale_vendorid;
96 uint16_t ale_deviceid;
97 const char *ale_name;
98 } ale_devs[] = {
99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
101 };
102
103 static int ale_attach(device_t);
104 static int ale_check_boundary(struct ale_softc *);
105 static int ale_detach(device_t);
106 static int ale_dma_alloc(struct ale_softc *);
107 static void ale_dma_free(struct ale_softc *);
108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
109 static int ale_encap(struct ale_softc *, struct mbuf **);
110 static void ale_get_macaddr(struct ale_softc *);
111 static void ale_init(void *);
112 static void ale_init_locked(struct ale_softc *);
113 static void ale_init_rx_pages(struct ale_softc *);
114 static void ale_init_tx_ring(struct ale_softc *);
115 static void ale_int_task(void *, int);
116 static int ale_intr(void *);
117 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
118 static void ale_mac_config(struct ale_softc *);
119 static int ale_miibus_readreg(device_t, int, int);
120 static void ale_miibus_statchg(device_t);
121 static int ale_miibus_writereg(device_t, int, int, int);
122 static int ale_mediachange(struct ifnet *);
123 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
124 static void ale_phy_reset(struct ale_softc *);
125 static int ale_probe(device_t);
126 static void ale_reset(struct ale_softc *);
127 static int ale_resume(device_t);
128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
129 uint32_t, uint32_t *);
130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
131 static int ale_rxeof(struct ale_softc *sc, int);
132 static void ale_rxfilter(struct ale_softc *);
133 static void ale_rxvlan(struct ale_softc *);
134 static void ale_setlinkspeed(struct ale_softc *);
135 static void ale_setwol(struct ale_softc *);
136 static int ale_shutdown(device_t);
137 static void ale_start(struct ifnet *);
138 static void ale_start_locked(struct ifnet *);
139 static void ale_stats_clear(struct ale_softc *);
140 static void ale_stats_update(struct ale_softc *);
141 static void ale_stop(struct ale_softc *);
142 static void ale_stop_mac(struct ale_softc *);
143 static int ale_suspend(device_t);
144 static void ale_sysctl_node(struct ale_softc *);
145 static void ale_tick(void *);
146 static void ale_txeof(struct ale_softc *);
147 static void ale_watchdog(struct ale_softc *);
148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
151
152 static device_method_t ale_methods[] = {
153 /* Device interface. */
154 DEVMETHOD(device_probe, ale_probe),
155 DEVMETHOD(device_attach, ale_attach),
156 DEVMETHOD(device_detach, ale_detach),
157 DEVMETHOD(device_shutdown, ale_shutdown),
158 DEVMETHOD(device_suspend, ale_suspend),
159 DEVMETHOD(device_resume, ale_resume),
160
161 /* MII interface. */
162 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
163 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
164 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
165
166 DEVMETHOD_END
167 };
168
169 static driver_t ale_driver = {
170 "ale",
171 ale_methods,
172 sizeof(struct ale_softc)
173 };
174
175 static devclass_t ale_devclass;
176
177 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL);
178 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL);
179
180 static struct resource_spec ale_res_spec_mem[] = {
181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
182 { -1, 0, 0 }
183 };
184
185 static struct resource_spec ale_irq_spec_legacy[] = {
186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
187 { -1, 0, 0 }
188 };
189
190 static struct resource_spec ale_irq_spec_msi[] = {
191 { SYS_RES_IRQ, 1, RF_ACTIVE },
192 { -1, 0, 0 }
193 };
194
195 static struct resource_spec ale_irq_spec_msix[] = {
196 { SYS_RES_IRQ, 1, RF_ACTIVE },
197 { -1, 0, 0 }
198 };
199
200 static int
201 ale_miibus_readreg(device_t dev, int phy, int reg)
202 {
203 struct ale_softc *sc;
204 uint32_t v;
205 int i;
206
207 sc = device_get_softc(dev);
208
209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
212 DELAY(5);
213 v = CSR_READ_4(sc, ALE_MDIO);
214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
215 break;
216 }
217
218 if (i == 0) {
219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
220 return (0);
221 }
222
223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
224 }
225
226 static int
227 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
228 {
229 struct ale_softc *sc;
230 uint32_t v;
231 int i;
232
233 sc = device_get_softc(dev);
234
235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
239 DELAY(5);
240 v = CSR_READ_4(sc, ALE_MDIO);
241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
242 break;
243 }
244
245 if (i == 0)
246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
247
248 return (0);
249 }
250
251 static void
252 ale_miibus_statchg(device_t dev)
253 {
254 struct ale_softc *sc;
255 struct mii_data *mii;
256 struct ifnet *ifp;
257 uint32_t reg;
258
259 sc = device_get_softc(dev);
260 mii = device_get_softc(sc->ale_miibus);
261 ifp = sc->ale_ifp;
262 if (mii == NULL || ifp == NULL ||
263 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
264 return;
265
266 sc->ale_flags &= ~ALE_FLAG_LINK;
267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
268 (IFM_ACTIVE | IFM_AVALID)) {
269 switch (IFM_SUBTYPE(mii->mii_media_active)) {
270 case IFM_10_T:
271 case IFM_100_TX:
272 sc->ale_flags |= ALE_FLAG_LINK;
273 break;
274 case IFM_1000_T:
275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
276 sc->ale_flags |= ALE_FLAG_LINK;
277 break;
278 default:
279 break;
280 }
281 }
282
283 /* Stop Rx/Tx MACs. */
284 ale_stop_mac(sc);
285
286 /* Program MACs with resolved speed/duplex/flow-control. */
287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
288 ale_mac_config(sc);
289 /* Reenable Tx/Rx MACs. */
290 reg = CSR_READ_4(sc, ALE_MAC_CFG);
291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
293 }
294 }
295
296 static void
297 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
298 {
299 struct ale_softc *sc;
300 struct mii_data *mii;
301
302 sc = ifp->if_softc;
303 ALE_LOCK(sc);
304 if ((ifp->if_flags & IFF_UP) == 0) {
305 ALE_UNLOCK(sc);
306 return;
307 }
308 mii = device_get_softc(sc->ale_miibus);
309
310 mii_pollstat(mii);
311 ifmr->ifm_status = mii->mii_media_status;
312 ifmr->ifm_active = mii->mii_media_active;
313 ALE_UNLOCK(sc);
314 }
315
316 static int
317 ale_mediachange(struct ifnet *ifp)
318 {
319 struct ale_softc *sc;
320 struct mii_data *mii;
321 struct mii_softc *miisc;
322 int error;
323
324 sc = ifp->if_softc;
325 ALE_LOCK(sc);
326 mii = device_get_softc(sc->ale_miibus);
327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
328 mii_phy_reset(miisc);
329 error = mii_mediachg(mii);
330 ALE_UNLOCK(sc);
331
332 return (error);
333 }
334
335 static int
336 ale_probe(device_t dev)
337 {
338 const struct ale_dev *sp;
339 int i;
340 uint16_t vendor, devid;
341
342 vendor = pci_get_vendor(dev);
343 devid = pci_get_device(dev);
344 sp = ale_devs;
345 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
346 if (vendor == sp->ale_vendorid &&
347 devid == sp->ale_deviceid) {
348 device_set_desc(dev, sp->ale_name);
349 return (BUS_PROBE_DEFAULT);
350 }
351 sp++;
352 }
353
354 return (ENXIO);
355 }
356
357 static void
358 ale_get_macaddr(struct ale_softc *sc)
359 {
360 uint32_t ea[2], reg;
361 int i, vpdc;
362
363 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
364 if ((reg & SPI_VPD_ENB) != 0) {
365 reg &= ~SPI_VPD_ENB;
366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
367 }
368
369 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
370 /*
371 * PCI VPD capability found, let TWSI reload EEPROM.
372 * This will set ethernet address of controller.
373 */
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
375 TWSI_CTRL_SW_LD_START);
376 for (i = 100; i > 0; i--) {
377 DELAY(1000);
378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
379 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
380 break;
381 }
382 if (i == 0)
383 device_printf(sc->ale_dev,
384 "reloading EEPROM timeout!\n");
385 } else {
386 if (bootverbose)
387 device_printf(sc->ale_dev,
388 "PCI VPD capability not found!\n");
389 }
390
391 ea[0] = CSR_READ_4(sc, ALE_PAR0);
392 ea[1] = CSR_READ_4(sc, ALE_PAR1);
393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
399 }
400
401 static void
402 ale_phy_reset(struct ale_softc *sc)
403 {
404
405 /* Reset magic from Linux. */
406 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
408 GPHY_CTRL_PHY_PLL_ON);
409 DELAY(1000);
410 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
413 DELAY(1000);
414
415 #define ATPHY_DBG_ADDR 0x1D
416 #define ATPHY_DBG_DATA 0x1E
417
418 /* Enable hibernation mode. */
419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
420 ATPHY_DBG_ADDR, 0x0B);
421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
422 ATPHY_DBG_DATA, 0xBC00);
423 /* Set Class A/B for all modes. */
424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
425 ATPHY_DBG_ADDR, 0x00);
426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
427 ATPHY_DBG_DATA, 0x02EF);
428 /* Enable 10BT power saving. */
429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
430 ATPHY_DBG_ADDR, 0x12);
431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
432 ATPHY_DBG_DATA, 0x4C04);
433 /* Adjust 1000T power. */
434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
435 ATPHY_DBG_ADDR, 0x04);
436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
437 ATPHY_DBG_ADDR, 0x8BBB);
438 /* 10BT center tap voltage. */
439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
440 ATPHY_DBG_ADDR, 0x05);
441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
442 ATPHY_DBG_ADDR, 0x2C46);
443
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
446 DELAY(1000);
447 }
448
449 static int
450 ale_attach(device_t dev)
451 {
452 struct ale_softc *sc;
453 struct ifnet *ifp;
454 uint16_t burst;
455 int error, i, msic, msixc, pmc;
456 uint32_t rxf_len, txf_len;
457
458 error = 0;
459 sc = device_get_softc(dev);
460 sc->ale_dev = dev;
461
462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
463 MTX_DEF);
464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
465 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
466
467 /* Map the device. */
468 pci_enable_busmaster(dev);
469 sc->ale_res_spec = ale_res_spec_mem;
470 sc->ale_irq_spec = ale_irq_spec_legacy;
471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
472 if (error != 0) {
473 device_printf(dev, "cannot allocate memory resources.\n");
474 goto fail;
475 }
476
477 /* Set PHY address. */
478 sc->ale_phyaddr = ALE_PHY_ADDR;
479
480 /* Reset PHY. */
481 ale_phy_reset(sc);
482
483 /* Reset the ethernet controller. */
484 ale_reset(sc);
485
486 /* Get PCI and chip id/revision. */
487 sc->ale_rev = pci_get_revid(dev);
488 if (sc->ale_rev >= 0xF0) {
489 /* L2E Rev. B. AR8114 */
490 sc->ale_flags |= ALE_FLAG_FASTETHER;
491 } else {
492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
493 /* L1E AR8121 */
494 sc->ale_flags |= ALE_FLAG_JUMBO;
495 } else {
496 /* L2E Rev. A. AR8113 */
497 sc->ale_flags |= ALE_FLAG_FASTETHER;
498 }
499 }
500 /*
501 * All known controllers seems to require 4 bytes alignment
502 * of Tx buffers to make Tx checksum offload with custom
503 * checksum generation method work.
504 */
505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
506 /*
507 * All known controllers seems to have issues on Rx checksum
508 * offload for fragmented IP datagrams.
509 */
510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
511 /*
512 * Don't use Tx CMB. It is known to cause RRS update failure
513 * under certain circumstances. Typical phenomenon of the
514 * issue would be unexpected sequence number encountered in
515 * Rx handler.
516 */
517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
519 MASTER_CHIP_REV_SHIFT;
520 if (bootverbose) {
521 device_printf(dev, "PCI device revision : 0x%04x\n",
522 sc->ale_rev);
523 device_printf(dev, "Chip id/revision : 0x%04x\n",
524 sc->ale_chip_rev);
525 }
526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
528 /*
529 * Uninitialized hardware returns an invalid chip id/revision
530 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
531 */
532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
533 rxf_len == 0xFFFFFFF) {
534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
536 txf_len, rxf_len);
537 error = ENXIO;
538 goto fail;
539 }
540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
541
542 /* Allocate IRQ resources. */
543 msixc = pci_msix_count(dev);
544 msic = pci_msi_count(dev);
545 if (bootverbose) {
546 device_printf(dev, "MSIX count : %d\n", msixc);
547 device_printf(dev, "MSI count : %d\n", msic);
548 }
549
550 /* Prefer MSIX over MSI. */
551 if (msix_disable == 0 || msi_disable == 0) {
552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
553 pci_alloc_msix(dev, &msixc) == 0) {
554 if (msixc == ALE_MSIX_MESSAGES) {
555 device_printf(dev, "Using %d MSIX messages.\n",
556 msixc);
557 sc->ale_flags |= ALE_FLAG_MSIX;
558 sc->ale_irq_spec = ale_irq_spec_msix;
559 } else
560 pci_release_msi(dev);
561 }
562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
563 msic == ALE_MSI_MESSAGES &&
564 pci_alloc_msi(dev, &msic) == 0) {
565 if (msic == ALE_MSI_MESSAGES) {
566 device_printf(dev, "Using %d MSI messages.\n",
567 msic);
568 sc->ale_flags |= ALE_FLAG_MSI;
569 sc->ale_irq_spec = ale_irq_spec_msi;
570 } else
571 pci_release_msi(dev);
572 }
573 }
574
575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
576 if (error != 0) {
577 device_printf(dev, "cannot allocate IRQ resources.\n");
578 goto fail;
579 }
580
581 /* Get DMA parameters from PCIe device control register. */
582 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
583 sc->ale_flags |= ALE_FLAG_PCIE;
584 burst = pci_read_config(dev, i + 0x08, 2);
585 /* Max read request size. */
586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
587 DMA_CFG_RD_BURST_SHIFT;
588 /* Max payload size. */
589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
590 DMA_CFG_WR_BURST_SHIFT;
591 if (bootverbose) {
592 device_printf(dev, "Read request size : %d bytes.\n",
593 128 << ((burst >> 12) & 0x07));
594 device_printf(dev, "TLP payload size : %d bytes.\n",
595 128 << ((burst >> 5) & 0x07));
596 }
597 } else {
598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
600 }
601
602 /* Create device sysctl node. */
603 ale_sysctl_node(sc);
604
605 if ((error = ale_dma_alloc(sc) != 0))
606 goto fail;
607
608 /* Load station address. */
609 ale_get_macaddr(sc);
610
611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
612 if (ifp == NULL) {
613 device_printf(dev, "cannot allocate ifnet structure.\n");
614 error = ENXIO;
615 goto fail;
616 }
617
618 ifp->if_softc = sc;
619 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
621 ifp->if_ioctl = ale_ioctl;
622 ifp->if_start = ale_start;
623 ifp->if_init = ale_init;
624 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
625 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
626 IFQ_SET_READY(&ifp->if_snd);
627 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
628 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
629 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
630 sc->ale_flags |= ALE_FLAG_PMCAP;
631 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
632 }
633 ifp->if_capenable = ifp->if_capabilities;
634
635 /* Set up MII bus. */
636 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
637 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
638 MIIF_DOPAUSE);
639 if (error != 0) {
640 device_printf(dev, "attaching PHYs failed\n");
641 goto fail;
642 }
643
644 ether_ifattach(ifp, sc->ale_eaddr);
645
646 /* VLAN capability setup. */
647 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
648 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
649 ifp->if_capenable = ifp->if_capabilities;
650 /*
651 * Even though controllers supported by ale(3) have Rx checksum
652 * offload bug the workaround for fragmented frames seemed to
653 * work so far. However it seems Rx checksum offload does not
654 * work under certain conditions. So disable Rx checksum offload
655 * until I find more clue about it but allow users to override it.
656 */
657 ifp->if_capenable &= ~IFCAP_RXCSUM;
658
659 /* Tell the upper layer(s) we support long frames. */
660 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
661
662 /* Create local taskq. */
663 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
664 taskqueue_thread_enqueue, &sc->ale_tq);
665 if (sc->ale_tq == NULL) {
666 device_printf(dev, "could not create taskqueue.\n");
667 ether_ifdetach(ifp);
668 error = ENXIO;
669 goto fail;
670 }
671 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
672 device_get_nameunit(sc->ale_dev));
673
674 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
675 msic = ALE_MSIX_MESSAGES;
676 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
677 msic = ALE_MSI_MESSAGES;
678 else
679 msic = 1;
680 for (i = 0; i < msic; i++) {
681 error = bus_setup_intr(dev, sc->ale_irq[i],
682 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
683 &sc->ale_intrhand[i]);
684 if (error != 0)
685 break;
686 }
687 if (error != 0) {
688 device_printf(dev, "could not set up interrupt handler.\n");
689 taskqueue_free(sc->ale_tq);
690 sc->ale_tq = NULL;
691 ether_ifdetach(ifp);
692 goto fail;
693 }
694
695 fail:
696 if (error != 0)
697 ale_detach(dev);
698
699 return (error);
700 }
701
702 static int
703 ale_detach(device_t dev)
704 {
705 struct ale_softc *sc;
706 struct ifnet *ifp;
707 int i, msic;
708
709 sc = device_get_softc(dev);
710
711 ifp = sc->ale_ifp;
712 if (device_is_attached(dev)) {
713 ether_ifdetach(ifp);
714 ALE_LOCK(sc);
715 ale_stop(sc);
716 ALE_UNLOCK(sc);
717 callout_drain(&sc->ale_tick_ch);
718 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
719 }
720
721 if (sc->ale_tq != NULL) {
722 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
723 taskqueue_free(sc->ale_tq);
724 sc->ale_tq = NULL;
725 }
726
727 if (sc->ale_miibus != NULL) {
728 device_delete_child(dev, sc->ale_miibus);
729 sc->ale_miibus = NULL;
730 }
731 bus_generic_detach(dev);
732 ale_dma_free(sc);
733
734 if (ifp != NULL) {
735 if_free(ifp);
736 sc->ale_ifp = NULL;
737 }
738
739 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
740 msic = ALE_MSIX_MESSAGES;
741 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
742 msic = ALE_MSI_MESSAGES;
743 else
744 msic = 1;
745 for (i = 0; i < msic; i++) {
746 if (sc->ale_intrhand[i] != NULL) {
747 bus_teardown_intr(dev, sc->ale_irq[i],
748 sc->ale_intrhand[i]);
749 sc->ale_intrhand[i] = NULL;
750 }
751 }
752
753 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
754 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
755 pci_release_msi(dev);
756 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
757 mtx_destroy(&sc->ale_mtx);
758
759 return (0);
760 }
761
762 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
763 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
764
765 #if __FreeBSD_version > 800000
766 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
767 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
768 #else
769 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
770 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
771 #endif
772
773 static void
774 ale_sysctl_node(struct ale_softc *sc)
775 {
776 struct sysctl_ctx_list *ctx;
777 struct sysctl_oid_list *child, *parent;
778 struct sysctl_oid *tree;
779 struct ale_hw_stats *stats;
780 int error;
781
782 stats = &sc->ale_stats;
783 ctx = device_get_sysctl_ctx(sc->ale_dev);
784 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
785
786 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
787 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
788 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
789 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
790 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
791 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
792 /* Pull in device tunables. */
793 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
794 error = resource_int_value(device_get_name(sc->ale_dev),
795 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
796 if (error == 0) {
797 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
798 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
799 device_printf(sc->ale_dev, "int_rx_mod value out of "
800 "range; using default: %d\n",
801 ALE_IM_RX_TIMER_DEFAULT);
802 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
803 }
804 }
805 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
806 error = resource_int_value(device_get_name(sc->ale_dev),
807 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
808 if (error == 0) {
809 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
810 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
811 device_printf(sc->ale_dev, "int_tx_mod value out of "
812 "range; using default: %d\n",
813 ALE_IM_TX_TIMER_DEFAULT);
814 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
815 }
816 }
817 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
818 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
819 sysctl_hw_ale_proc_limit, "I",
820 "max number of Rx events to process");
821 /* Pull in device tunables. */
822 sc->ale_process_limit = ALE_PROC_DEFAULT;
823 error = resource_int_value(device_get_name(sc->ale_dev),
824 device_get_unit(sc->ale_dev), "process_limit",
825 &sc->ale_process_limit);
826 if (error == 0) {
827 if (sc->ale_process_limit < ALE_PROC_MIN ||
828 sc->ale_process_limit > ALE_PROC_MAX) {
829 device_printf(sc->ale_dev,
830 "process_limit value out of range; "
831 "using default: %d\n", ALE_PROC_DEFAULT);
832 sc->ale_process_limit = ALE_PROC_DEFAULT;
833 }
834 }
835
836 /* Misc statistics. */
837 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
838 &stats->reset_brk_seq,
839 "Controller resets due to broken Rx sequnce number");
840
841 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
842 NULL, "ATE statistics");
843 parent = SYSCTL_CHILDREN(tree);
844
845 /* Rx statistics. */
846 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
847 NULL, "Rx MAC statistics");
848 child = SYSCTL_CHILDREN(tree);
849 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
850 &stats->rx_frames, "Good frames");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
852 &stats->rx_bcast_frames, "Good broadcast frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
854 &stats->rx_mcast_frames, "Good multicast frames");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
856 &stats->rx_pause_frames, "Pause control frames");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
858 &stats->rx_control_frames, "Control frames");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
860 &stats->rx_crcerrs, "CRC errors");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
862 &stats->rx_lenerrs, "Frames with length mismatched");
863 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
864 &stats->rx_bytes, "Good octets");
865 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
866 &stats->rx_bcast_bytes, "Good broadcast octets");
867 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
868 &stats->rx_mcast_bytes, "Good multicast octets");
869 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
870 &stats->rx_runts, "Too short frames");
871 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
872 &stats->rx_fragments, "Fragmented frames");
873 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
874 &stats->rx_pkts_64, "64 bytes frames");
875 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
876 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
878 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
880 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
882 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
884 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
886 &stats->rx_pkts_1519_max, "1519 to max frames");
887 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
888 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
889 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
890 &stats->rx_fifo_oflows, "FIFO overflows");
891 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
892 &stats->rx_rrs_errs, "Return status write-back errors");
893 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
894 &stats->rx_alignerrs, "Alignment errors");
895 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
896 &stats->rx_pkts_filtered,
897 "Frames dropped due to address filtering");
898
899 /* Tx statistics. */
900 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
901 NULL, "Tx MAC statistics");
902 child = SYSCTL_CHILDREN(tree);
903 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
904 &stats->tx_frames, "Good frames");
905 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
906 &stats->tx_bcast_frames, "Good broadcast frames");
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
908 &stats->tx_mcast_frames, "Good multicast frames");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
910 &stats->tx_pause_frames, "Pause control frames");
911 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
912 &stats->tx_control_frames, "Control frames");
913 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
914 &stats->tx_excess_defer, "Frames with excessive derferrals");
915 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
916 &stats->tx_excess_defer, "Frames with derferrals");
917 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
918 &stats->tx_bytes, "Good octets");
919 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
920 &stats->tx_bcast_bytes, "Good broadcast octets");
921 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
922 &stats->tx_mcast_bytes, "Good multicast octets");
923 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
924 &stats->tx_pkts_64, "64 bytes frames");
925 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
926 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
928 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
930 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
932 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
934 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
936 &stats->tx_pkts_1519_max, "1519 to max frames");
937 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
938 &stats->tx_single_colls, "Single collisions");
939 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
940 &stats->tx_multi_colls, "Multiple collisions");
941 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
942 &stats->tx_late_colls, "Late collisions");
943 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
944 &stats->tx_excess_colls, "Excessive collisions");
945 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
946 &stats->tx_abort, "Aborted frames due to Excessive collisions");
947 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
948 &stats->tx_underrun, "FIFO underruns");
949 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
950 &stats->tx_desc_underrun, "Descriptor write-back errors");
951 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
952 &stats->tx_lenerrs, "Frames with length mismatched");
953 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
954 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
955 }
956
957 #undef ALE_SYSCTL_STAT_ADD32
958 #undef ALE_SYSCTL_STAT_ADD64
959
960 struct ale_dmamap_arg {
961 bus_addr_t ale_busaddr;
962 };
963
964 static void
965 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
966 {
967 struct ale_dmamap_arg *ctx;
968
969 if (error != 0)
970 return;
971
972 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
973
974 ctx = (struct ale_dmamap_arg *)arg;
975 ctx->ale_busaddr = segs[0].ds_addr;
976 }
977
978 /*
979 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
980 * which specifies high address region of DMA blocks. Therefore these
981 * blocks should have the same high address of given 4GB address
982 * space(i.e. crossing 4GB boundary is not allowed).
983 */
984 static int
985 ale_check_boundary(struct ale_softc *sc)
986 {
987 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
988 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
989
990 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
991 sc->ale_pagesize;
992 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
993 sc->ale_pagesize;
994 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
995 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
996 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
997 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
998
999 if ((ALE_ADDR_HI(tx_ring_end) !=
1000 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
1001 (ALE_ADDR_HI(rx_page_end[0]) !=
1002 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
1003 (ALE_ADDR_HI(rx_page_end[1]) !=
1004 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
1005 (ALE_ADDR_HI(tx_cmb_end) !=
1006 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
1007 (ALE_ADDR_HI(rx_cmb_end[0]) !=
1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
1009 (ALE_ADDR_HI(rx_cmb_end[1]) !=
1010 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
1011 return (EFBIG);
1012
1013 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
1014 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
1015 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
1016 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
1017 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
1018 return (EFBIG);
1019
1020 return (0);
1021 }
1022
1023 static int
1024 ale_dma_alloc(struct ale_softc *sc)
1025 {
1026 struct ale_txdesc *txd;
1027 bus_addr_t lowaddr;
1028 struct ale_dmamap_arg ctx;
1029 int error, guard_size, i;
1030
1031 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1032 guard_size = ALE_JUMBO_FRAMELEN;
1033 else
1034 guard_size = ALE_MAX_FRAMELEN;
1035 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1036 ALE_RX_PAGE_ALIGN);
1037 lowaddr = BUS_SPACE_MAXADDR;
1038 again:
1039 /* Create parent DMA tag. */
1040 error = bus_dma_tag_create(
1041 bus_get_dma_tag(sc->ale_dev), /* parent */
1042 1, 0, /* alignment, boundary */
1043 lowaddr, /* lowaddr */
1044 BUS_SPACE_MAXADDR, /* highaddr */
1045 NULL, NULL, /* filter, filterarg */
1046 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1047 0, /* nsegments */
1048 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1049 0, /* flags */
1050 NULL, NULL, /* lockfunc, lockarg */
1051 &sc->ale_cdata.ale_parent_tag);
1052 if (error != 0) {
1053 device_printf(sc->ale_dev,
1054 "could not create parent DMA tag.\n");
1055 goto fail;
1056 }
1057
1058 /* Create DMA tag for Tx descriptor ring. */
1059 error = bus_dma_tag_create(
1060 sc->ale_cdata.ale_parent_tag, /* parent */
1061 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1062 BUS_SPACE_MAXADDR, /* lowaddr */
1063 BUS_SPACE_MAXADDR, /* highaddr */
1064 NULL, NULL, /* filter, filterarg */
1065 ALE_TX_RING_SZ, /* maxsize */
1066 1, /* nsegments */
1067 ALE_TX_RING_SZ, /* maxsegsize */
1068 0, /* flags */
1069 NULL, NULL, /* lockfunc, lockarg */
1070 &sc->ale_cdata.ale_tx_ring_tag);
1071 if (error != 0) {
1072 device_printf(sc->ale_dev,
1073 "could not create Tx ring DMA tag.\n");
1074 goto fail;
1075 }
1076
1077 /* Create DMA tag for Rx pages. */
1078 for (i = 0; i < ALE_RX_PAGES; i++) {
1079 error = bus_dma_tag_create(
1080 sc->ale_cdata.ale_parent_tag, /* parent */
1081 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1082 BUS_SPACE_MAXADDR, /* lowaddr */
1083 BUS_SPACE_MAXADDR, /* highaddr */
1084 NULL, NULL, /* filter, filterarg */
1085 sc->ale_pagesize, /* maxsize */
1086 1, /* nsegments */
1087 sc->ale_pagesize, /* maxsegsize */
1088 0, /* flags */
1089 NULL, NULL, /* lockfunc, lockarg */
1090 &sc->ale_cdata.ale_rx_page[i].page_tag);
1091 if (error != 0) {
1092 device_printf(sc->ale_dev,
1093 "could not create Rx page %d DMA tag.\n", i);
1094 goto fail;
1095 }
1096 }
1097
1098 /* Create DMA tag for Tx coalescing message block. */
1099 error = bus_dma_tag_create(
1100 sc->ale_cdata.ale_parent_tag, /* parent */
1101 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1102 BUS_SPACE_MAXADDR, /* lowaddr */
1103 BUS_SPACE_MAXADDR, /* highaddr */
1104 NULL, NULL, /* filter, filterarg */
1105 ALE_TX_CMB_SZ, /* maxsize */
1106 1, /* nsegments */
1107 ALE_TX_CMB_SZ, /* maxsegsize */
1108 0, /* flags */
1109 NULL, NULL, /* lockfunc, lockarg */
1110 &sc->ale_cdata.ale_tx_cmb_tag);
1111 if (error != 0) {
1112 device_printf(sc->ale_dev,
1113 "could not create Tx CMB DMA tag.\n");
1114 goto fail;
1115 }
1116
1117 /* Create DMA tag for Rx coalescing message block. */
1118 for (i = 0; i < ALE_RX_PAGES; i++) {
1119 error = bus_dma_tag_create(
1120 sc->ale_cdata.ale_parent_tag, /* parent */
1121 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1122 BUS_SPACE_MAXADDR, /* lowaddr */
1123 BUS_SPACE_MAXADDR, /* highaddr */
1124 NULL, NULL, /* filter, filterarg */
1125 ALE_RX_CMB_SZ, /* maxsize */
1126 1, /* nsegments */
1127 ALE_RX_CMB_SZ, /* maxsegsize */
1128 0, /* flags */
1129 NULL, NULL, /* lockfunc, lockarg */
1130 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1131 if (error != 0) {
1132 device_printf(sc->ale_dev,
1133 "could not create Rx page %d CMB DMA tag.\n", i);
1134 goto fail;
1135 }
1136 }
1137
1138 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1139 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1140 (void **)&sc->ale_cdata.ale_tx_ring,
1141 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1142 &sc->ale_cdata.ale_tx_ring_map);
1143 if (error != 0) {
1144 device_printf(sc->ale_dev,
1145 "could not allocate DMA'able memory for Tx ring.\n");
1146 goto fail;
1147 }
1148 ctx.ale_busaddr = 0;
1149 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1150 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1151 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1152 if (error != 0 || ctx.ale_busaddr == 0) {
1153 device_printf(sc->ale_dev,
1154 "could not load DMA'able memory for Tx ring.\n");
1155 goto fail;
1156 }
1157 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1158
1159 /* Rx pages. */
1160 for (i = 0; i < ALE_RX_PAGES; i++) {
1161 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1162 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1164 &sc->ale_cdata.ale_rx_page[i].page_map);
1165 if (error != 0) {
1166 device_printf(sc->ale_dev,
1167 "could not allocate DMA'able memory for "
1168 "Rx page %d.\n", i);
1169 goto fail;
1170 }
1171 ctx.ale_busaddr = 0;
1172 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1173 sc->ale_cdata.ale_rx_page[i].page_map,
1174 sc->ale_cdata.ale_rx_page[i].page_addr,
1175 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1176 if (error != 0 || ctx.ale_busaddr == 0) {
1177 device_printf(sc->ale_dev,
1178 "could not load DMA'able memory for "
1179 "Rx page %d.\n", i);
1180 goto fail;
1181 }
1182 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1183 }
1184
1185 /* Tx CMB. */
1186 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1187 (void **)&sc->ale_cdata.ale_tx_cmb,
1188 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1189 &sc->ale_cdata.ale_tx_cmb_map);
1190 if (error != 0) {
1191 device_printf(sc->ale_dev,
1192 "could not allocate DMA'able memory for Tx CMB.\n");
1193 goto fail;
1194 }
1195 ctx.ale_busaddr = 0;
1196 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1197 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1198 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1199 if (error != 0 || ctx.ale_busaddr == 0) {
1200 device_printf(sc->ale_dev,
1201 "could not load DMA'able memory for Tx CMB.\n");
1202 goto fail;
1203 }
1204 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1205
1206 /* Rx CMB. */
1207 for (i = 0; i < ALE_RX_PAGES; i++) {
1208 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1209 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1210 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1211 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1212 if (error != 0) {
1213 device_printf(sc->ale_dev, "could not allocate "
1214 "DMA'able memory for Rx page %d CMB.\n", i);
1215 goto fail;
1216 }
1217 ctx.ale_busaddr = 0;
1218 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1219 sc->ale_cdata.ale_rx_page[i].cmb_map,
1220 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1221 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1222 if (error != 0 || ctx.ale_busaddr == 0) {
1223 device_printf(sc->ale_dev, "could not load DMA'able "
1224 "memory for Rx page %d CMB.\n", i);
1225 goto fail;
1226 }
1227 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1228 }
1229
1230 /*
1231 * Tx descriptors/RXF0/CMB DMA blocks share the same
1232 * high address region of 64bit DMA address space.
1233 */
1234 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1235 (error = ale_check_boundary(sc)) != 0) {
1236 device_printf(sc->ale_dev, "4GB boundary crossed, "
1237 "switching to 32bit DMA addressing mode.\n");
1238 ale_dma_free(sc);
1239 /*
1240 * Limit max allowable DMA address space to 32bit
1241 * and try again.
1242 */
1243 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1244 goto again;
1245 }
1246
1247 /*
1248 * Create Tx buffer parent tag.
1249 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1250 * needs separate parent DMA tag as parent DMA address space
1251 * could be restricted to be within 32bit address space by
1252 * 4GB boundary crossing.
1253 */
1254 error = bus_dma_tag_create(
1255 bus_get_dma_tag(sc->ale_dev), /* parent */
1256 1, 0, /* alignment, boundary */
1257 BUS_SPACE_MAXADDR, /* lowaddr */
1258 BUS_SPACE_MAXADDR, /* highaddr */
1259 NULL, NULL, /* filter, filterarg */
1260 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1261 0, /* nsegments */
1262 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1263 0, /* flags */
1264 NULL, NULL, /* lockfunc, lockarg */
1265 &sc->ale_cdata.ale_buffer_tag);
1266 if (error != 0) {
1267 device_printf(sc->ale_dev,
1268 "could not create parent buffer DMA tag.\n");
1269 goto fail;
1270 }
1271
1272 /* Create DMA tag for Tx buffers. */
1273 error = bus_dma_tag_create(
1274 sc->ale_cdata.ale_buffer_tag, /* parent */
1275 1, 0, /* alignment, boundary */
1276 BUS_SPACE_MAXADDR, /* lowaddr */
1277 BUS_SPACE_MAXADDR, /* highaddr */
1278 NULL, NULL, /* filter, filterarg */
1279 ALE_TSO_MAXSIZE, /* maxsize */
1280 ALE_MAXTXSEGS, /* nsegments */
1281 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1282 0, /* flags */
1283 NULL, NULL, /* lockfunc, lockarg */
1284 &sc->ale_cdata.ale_tx_tag);
1285 if (error != 0) {
1286 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1287 goto fail;
1288 }
1289
1290 /* Create DMA maps for Tx buffers. */
1291 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1292 txd = &sc->ale_cdata.ale_txdesc[i];
1293 txd->tx_m = NULL;
1294 txd->tx_dmamap = NULL;
1295 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1296 &txd->tx_dmamap);
1297 if (error != 0) {
1298 device_printf(sc->ale_dev,
1299 "could not create Tx dmamap.\n");
1300 goto fail;
1301 }
1302 }
1303
1304 fail:
1305 return (error);
1306 }
1307
1308 static void
1309 ale_dma_free(struct ale_softc *sc)
1310 {
1311 struct ale_txdesc *txd;
1312 int i;
1313
1314 /* Tx buffers. */
1315 if (sc->ale_cdata.ale_tx_tag != NULL) {
1316 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1317 txd = &sc->ale_cdata.ale_txdesc[i];
1318 if (txd->tx_dmamap != NULL) {
1319 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1320 txd->tx_dmamap);
1321 txd->tx_dmamap = NULL;
1322 }
1323 }
1324 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1325 sc->ale_cdata.ale_tx_tag = NULL;
1326 }
1327 /* Tx descriptor ring. */
1328 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1329 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1330 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1331 sc->ale_cdata.ale_tx_ring_map);
1332 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1333 sc->ale_cdata.ale_tx_ring != NULL)
1334 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1335 sc->ale_cdata.ale_tx_ring,
1336 sc->ale_cdata.ale_tx_ring_map);
1337 sc->ale_cdata.ale_tx_ring = NULL;
1338 sc->ale_cdata.ale_tx_ring_map = NULL;
1339 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1340 sc->ale_cdata.ale_tx_ring_tag = NULL;
1341 }
1342 /* Rx page block. */
1343 for (i = 0; i < ALE_RX_PAGES; i++) {
1344 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1345 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1346 bus_dmamap_unload(
1347 sc->ale_cdata.ale_rx_page[i].page_tag,
1348 sc->ale_cdata.ale_rx_page[i].page_map);
1349 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1350 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1351 bus_dmamem_free(
1352 sc->ale_cdata.ale_rx_page[i].page_tag,
1353 sc->ale_cdata.ale_rx_page[i].page_addr,
1354 sc->ale_cdata.ale_rx_page[i].page_map);
1355 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1356 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1357 bus_dma_tag_destroy(
1358 sc->ale_cdata.ale_rx_page[i].page_tag);
1359 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1360 }
1361 }
1362 /* Rx CMB. */
1363 for (i = 0; i < ALE_RX_PAGES; i++) {
1364 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1365 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1366 bus_dmamap_unload(
1367 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1368 sc->ale_cdata.ale_rx_page[i].cmb_map);
1369 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1370 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1371 bus_dmamem_free(
1372 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1373 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1374 sc->ale_cdata.ale_rx_page[i].cmb_map);
1375 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1376 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1377 bus_dma_tag_destroy(
1378 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1379 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1380 }
1381 }
1382 /* Tx CMB. */
1383 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1384 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1385 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1386 sc->ale_cdata.ale_tx_cmb_map);
1387 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1388 sc->ale_cdata.ale_tx_cmb != NULL)
1389 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1390 sc->ale_cdata.ale_tx_cmb,
1391 sc->ale_cdata.ale_tx_cmb_map);
1392 sc->ale_cdata.ale_tx_cmb = NULL;
1393 sc->ale_cdata.ale_tx_cmb_map = NULL;
1394 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1395 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1396 }
1397 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1398 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1399 sc->ale_cdata.ale_buffer_tag = NULL;
1400 }
1401 if (sc->ale_cdata.ale_parent_tag != NULL) {
1402 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1403 sc->ale_cdata.ale_parent_tag = NULL;
1404 }
1405 }
1406
1407 static int
1408 ale_shutdown(device_t dev)
1409 {
1410
1411 return (ale_suspend(dev));
1412 }
1413
1414 /*
1415 * Note, this driver resets the link speed to 10/100Mbps by
1416 * restarting auto-negotiation in suspend/shutdown phase but we
1417 * don't know whether that auto-negotiation would succeed or not
1418 * as driver has no control after powering off/suspend operation.
1419 * If the renegotiation fail WOL may not work. Running at 1Gbps
1420 * will draw more power than 375mA at 3.3V which is specified in
1421 * PCI specification and that would result in complete
1422 * shutdowning power to ethernet controller.
1423 *
1424 * TODO
1425 * Save current negotiated media speed/duplex/flow-control to
1426 * softc and restore the same link again after resuming. PHY
1427 * handling such as power down/resetting to 100Mbps may be better
1428 * handled in suspend method in phy driver.
1429 */
1430 static void
1431 ale_setlinkspeed(struct ale_softc *sc)
1432 {
1433 struct mii_data *mii;
1434 int aneg, i;
1435
1436 mii = device_get_softc(sc->ale_miibus);
1437 mii_pollstat(mii);
1438 aneg = 0;
1439 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1440 (IFM_ACTIVE | IFM_AVALID)) {
1441 switch IFM_SUBTYPE(mii->mii_media_active) {
1442 case IFM_10_T:
1443 case IFM_100_TX:
1444 return;
1445 case IFM_1000_T:
1446 aneg++;
1447 break;
1448 default:
1449 break;
1450 }
1451 }
1452 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1453 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1454 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1455 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1456 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1457 DELAY(1000);
1458 if (aneg != 0) {
1459 /*
1460 * Poll link state until ale(4) get a 10/100Mbps link.
1461 */
1462 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1463 mii_pollstat(mii);
1464 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1465 == (IFM_ACTIVE | IFM_AVALID)) {
1466 switch (IFM_SUBTYPE(
1467 mii->mii_media_active)) {
1468 case IFM_10_T:
1469 case IFM_100_TX:
1470 ale_mac_config(sc);
1471 return;
1472 default:
1473 break;
1474 }
1475 }
1476 ALE_UNLOCK(sc);
1477 pause("alelnk", hz);
1478 ALE_LOCK(sc);
1479 }
1480 if (i == MII_ANEGTICKS_GIGE)
1481 device_printf(sc->ale_dev,
1482 "establishing a link failed, WOL may not work!");
1483 }
1484 /*
1485 * No link, force MAC to have 100Mbps, full-duplex link.
1486 * This is the last resort and may/may not work.
1487 */
1488 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1489 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1490 ale_mac_config(sc);
1491 }
1492
1493 static void
1494 ale_setwol(struct ale_softc *sc)
1495 {
1496 struct ifnet *ifp;
1497 uint32_t reg, pmcs;
1498 uint16_t pmstat;
1499 int pmc;
1500
1501 ALE_LOCK_ASSERT(sc);
1502
1503 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1504 /* Disable WOL. */
1505 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1506 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1507 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1508 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1509 /* Force PHY power down. */
1510 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1511 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1512 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1513 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1514 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1515 return;
1516 }
1517
1518 ifp = sc->ale_ifp;
1519 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1520 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1521 ale_setlinkspeed(sc);
1522 }
1523
1524 pmcs = 0;
1525 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1526 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1527 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1528 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1529 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1530 MAC_CFG_BCAST);
1531 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1532 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1533 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1534 reg |= MAC_CFG_RX_ENB;
1535 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1536
1537 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1538 /* WOL disabled, PHY power down. */
1539 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1540 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1541 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1542 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1543 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1544 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1545 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1546 GPHY_CTRL_PWDOWN_HW);
1547 }
1548 /* Request PME. */
1549 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1550 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1551 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1552 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1553 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1554 }
1555
1556 static int
1557 ale_suspend(device_t dev)
1558 {
1559 struct ale_softc *sc;
1560
1561 sc = device_get_softc(dev);
1562
1563 ALE_LOCK(sc);
1564 ale_stop(sc);
1565 ale_setwol(sc);
1566 ALE_UNLOCK(sc);
1567
1568 return (0);
1569 }
1570
1571 static int
1572 ale_resume(device_t dev)
1573 {
1574 struct ale_softc *sc;
1575 struct ifnet *ifp;
1576 int pmc;
1577 uint16_t pmstat;
1578
1579 sc = device_get_softc(dev);
1580
1581 ALE_LOCK(sc);
1582 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1583 /* Disable PME and clear PME status. */
1584 pmstat = pci_read_config(sc->ale_dev,
1585 pmc + PCIR_POWER_STATUS, 2);
1586 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1587 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1588 pci_write_config(sc->ale_dev,
1589 pmc + PCIR_POWER_STATUS, pmstat, 2);
1590 }
1591 }
1592 /* Reset PHY. */
1593 ale_phy_reset(sc);
1594 ifp = sc->ale_ifp;
1595 if ((ifp->if_flags & IFF_UP) != 0) {
1596 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1597 ale_init_locked(sc);
1598 }
1599 ALE_UNLOCK(sc);
1600
1601 return (0);
1602 }
1603
1604 static int
1605 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1606 {
1607 struct ale_txdesc *txd, *txd_last;
1608 struct tx_desc *desc;
1609 struct mbuf *m;
1610 struct ip *ip;
1611 struct tcphdr *tcp;
1612 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1613 bus_dmamap_t map;
1614 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1615 int error, i, nsegs, prod, si;
1616
1617 ALE_LOCK_ASSERT(sc);
1618
1619 M_ASSERTPKTHDR((*m_head));
1620
1621 m = *m_head;
1622 ip = NULL;
1623 tcp = NULL;
1624 cflags = vtag = 0;
1625 ip_off = poff = 0;
1626 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1627 /*
1628 * AR81xx requires offset of TCP/UDP payload in its Tx
1629 * descriptor to perform hardware Tx checksum offload.
1630 * Additionally, TSO requires IP/TCP header size and
1631 * modification of IP/TCP header in order to make TSO
1632 * engine work. This kind of operation takes many CPU
1633 * cycles on FreeBSD so fast host CPU is required to
1634 * get smooth TSO performance.
1635 */
1636 struct ether_header *eh;
1637
1638 if (M_WRITABLE(m) == 0) {
1639 /* Get a writable copy. */
1640 m = m_dup(*m_head, M_DONTWAIT);
1641 /* Release original mbufs. */
1642 m_freem(*m_head);
1643 if (m == NULL) {
1644 *m_head = NULL;
1645 return (ENOBUFS);
1646 }
1647 *m_head = m;
1648 }
1649
1650 /*
1651 * Buggy-controller requires 4 byte aligned Tx buffer
1652 * to make custom checksum offload work.
1653 */
1654 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1655 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1656 (mtod(m, intptr_t) & 3) != 0) {
1657 m = m_defrag(*m_head, M_DONTWAIT);
1658 if (m == NULL) {
1659 *m_head = NULL;
1660 return (ENOBUFS);
1661 }
1662 *m_head = m;
1663 }
1664
1665 ip_off = sizeof(struct ether_header);
1666 m = m_pullup(m, ip_off);
1667 if (m == NULL) {
1668 *m_head = NULL;
1669 return (ENOBUFS);
1670 }
1671 eh = mtod(m, struct ether_header *);
1672 /*
1673 * Check if hardware VLAN insertion is off.
1674 * Additional check for LLC/SNAP frame?
1675 */
1676 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1677 ip_off = sizeof(struct ether_vlan_header);
1678 m = m_pullup(m, ip_off);
1679 if (m == NULL) {
1680 *m_head = NULL;
1681 return (ENOBUFS);
1682 }
1683 }
1684 m = m_pullup(m, ip_off + sizeof(struct ip));
1685 if (m == NULL) {
1686 *m_head = NULL;
1687 return (ENOBUFS);
1688 }
1689 ip = (struct ip *)(mtod(m, char *) + ip_off);
1690 poff = ip_off + (ip->ip_hl << 2);
1691 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1692 /*
1693 * XXX
1694 * AR81xx requires the first descriptor should
1695 * not include any TCP playload for TSO case.
1696 * (i.e. ethernet header + IP + TCP header only)
1697 * m_pullup(9) above will ensure this too.
1698 * However it's not correct if the first mbuf
1699 * of the chain does not use cluster.
1700 */
1701 m = m_pullup(m, poff + sizeof(struct tcphdr));
1702 if (m == NULL) {
1703 *m_head = NULL;
1704 return (ENOBUFS);
1705 }
1706 ip = (struct ip *)(mtod(m, char *) + ip_off);
1707 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1708 m = m_pullup(m, poff + (tcp->th_off << 2));
1709 if (m == NULL) {
1710 *m_head = NULL;
1711 return (ENOBUFS);
1712 }
1713 /*
1714 * AR81xx requires IP/TCP header size and offset as
1715 * well as TCP pseudo checksum which complicates
1716 * TSO configuration. I guess this comes from the
1717 * adherence to Microsoft NDIS Large Send
1718 * specification which requires insertion of
1719 * pseudo checksum by upper stack. The pseudo
1720 * checksum that NDIS refers to doesn't include
1721 * TCP payload length so ale(4) should recompute
1722 * the pseudo checksum here. Hopefully this wouldn't
1723 * be much burden on modern CPUs.
1724 * Reset IP checksum and recompute TCP pseudo
1725 * checksum as NDIS specification said.
1726 */
1727 ip->ip_sum = 0;
1728 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1729 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1730 }
1731 *m_head = m;
1732 }
1733
1734 si = prod = sc->ale_cdata.ale_tx_prod;
1735 txd = &sc->ale_cdata.ale_txdesc[prod];
1736 txd_last = txd;
1737 map = txd->tx_dmamap;
1738
1739 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1740 *m_head, txsegs, &nsegs, 0);
1741 if (error == EFBIG) {
1742 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS);
1743 if (m == NULL) {
1744 m_freem(*m_head);
1745 *m_head = NULL;
1746 return (ENOMEM);
1747 }
1748 *m_head = m;
1749 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1750 *m_head, txsegs, &nsegs, 0);
1751 if (error != 0) {
1752 m_freem(*m_head);
1753 *m_head = NULL;
1754 return (error);
1755 }
1756 } else if (error != 0)
1757 return (error);
1758 if (nsegs == 0) {
1759 m_freem(*m_head);
1760 *m_head = NULL;
1761 return (EIO);
1762 }
1763
1764 /* Check descriptor overrun. */
1765 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1766 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1767 return (ENOBUFS);
1768 }
1769 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1770
1771 m = *m_head;
1772 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1773 /* Request TSO and set MSS. */
1774 cflags |= ALE_TD_TSO;
1775 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1776 /* Set IP/TCP header size. */
1777 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1778 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1779 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1780 /*
1781 * AR81xx supports Tx custom checksum offload feature
1782 * that offloads single 16bit checksum computation.
1783 * So you can choose one among IP, TCP and UDP.
1784 * Normally driver sets checksum start/insertion
1785 * position from the information of TCP/UDP frame as
1786 * TCP/UDP checksum takes more time than that of IP.
1787 * However it seems that custom checksum offload
1788 * requires 4 bytes aligned Tx buffers due to hardware
1789 * bug.
1790 * AR81xx also supports explicit Tx checksum computation
1791 * if it is told that the size of IP header and TCP
1792 * header(for UDP, the header size does not matter
1793 * because it's fixed length). However with this scheme
1794 * TSO does not work so you have to choose one either
1795 * TSO or explicit Tx checksum offload. I chosen TSO
1796 * plus custom checksum offload with work-around which
1797 * will cover most common usage for this consumer
1798 * ethernet controller. The work-around takes a lot of
1799 * CPU cycles if Tx buffer is not aligned on 4 bytes
1800 * boundary, though.
1801 */
1802 cflags |= ALE_TD_CXSUM;
1803 /* Set checksum start offset. */
1804 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1805 /* Set checksum insertion position of TCP/UDP. */
1806 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1807 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1808 }
1809
1810 /* Configure VLAN hardware tag insertion. */
1811 if ((m->m_flags & M_VLANTAG) != 0) {
1812 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1813 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1814 cflags |= ALE_TD_INSERT_VLAN_TAG;
1815 }
1816
1817 i = 0;
1818 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1819 /*
1820 * Make sure the first fragment contains
1821 * only ethernet and IP/TCP header with options.
1822 */
1823 hdrlen = poff + (tcp->th_off << 2);
1824 desc = &sc->ale_cdata.ale_tx_ring[prod];
1825 desc->addr = htole64(txsegs[i].ds_addr);
1826 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1827 desc->flags = htole32(cflags);
1828 sc->ale_cdata.ale_tx_cnt++;
1829 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1830 if (m->m_len - hdrlen > 0) {
1831 /* Handle remaining payload of the first fragment. */
1832 desc = &sc->ale_cdata.ale_tx_ring[prod];
1833 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1834 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1835 vtag);
1836 desc->flags = htole32(cflags);
1837 sc->ale_cdata.ale_tx_cnt++;
1838 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1839 }
1840 i = 1;
1841 }
1842 for (; i < nsegs; i++) {
1843 desc = &sc->ale_cdata.ale_tx_ring[prod];
1844 desc->addr = htole64(txsegs[i].ds_addr);
1845 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1846 desc->flags = htole32(cflags);
1847 sc->ale_cdata.ale_tx_cnt++;
1848 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1849 }
1850 /* Update producer index. */
1851 sc->ale_cdata.ale_tx_prod = prod;
1852 /* Set TSO header on the first descriptor. */
1853 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1854 desc = &sc->ale_cdata.ale_tx_ring[si];
1855 desc->flags |= htole32(ALE_TD_TSO_HDR);
1856 }
1857
1858 /* Finally set EOP on the last descriptor. */
1859 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1860 desc = &sc->ale_cdata.ale_tx_ring[prod];
1861 desc->flags |= htole32(ALE_TD_EOP);
1862
1863 /* Swap dmamap of the first and the last. */
1864 txd = &sc->ale_cdata.ale_txdesc[prod];
1865 map = txd_last->tx_dmamap;
1866 txd_last->tx_dmamap = txd->tx_dmamap;
1867 txd->tx_dmamap = map;
1868 txd->tx_m = m;
1869
1870 /* Sync descriptors. */
1871 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1872 sc->ale_cdata.ale_tx_ring_map,
1873 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1874
1875 return (0);
1876 }
1877
1878 static void
1879 ale_start(struct ifnet *ifp)
1880 {
1881 struct ale_softc *sc;
1882
1883 sc = ifp->if_softc;
1884 ALE_LOCK(sc);
1885 ale_start_locked(ifp);
1886 ALE_UNLOCK(sc);
1887 }
1888
1889 static void
1890 ale_start_locked(struct ifnet *ifp)
1891 {
1892 struct ale_softc *sc;
1893 struct mbuf *m_head;
1894 int enq;
1895
1896 sc = ifp->if_softc;
1897
1898 ALE_LOCK_ASSERT(sc);
1899
1900 /* Reclaim transmitted frames. */
1901 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1902 ale_txeof(sc);
1903
1904 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1905 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1906 return;
1907
1908 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1909 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1910 if (m_head == NULL)
1911 break;
1912 /*
1913 * Pack the data into the transmit ring. If we
1914 * don't have room, set the OACTIVE flag and wait
1915 * for the NIC to drain the ring.
1916 */
1917 if (ale_encap(sc, &m_head)) {
1918 if (m_head == NULL)
1919 break;
1920 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1921 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1922 break;
1923 }
1924
1925 enq++;
1926 /*
1927 * If there's a BPF listener, bounce a copy of this frame
1928 * to him.
1929 */
1930 ETHER_BPF_MTAP(ifp, m_head);
1931 }
1932
1933 if (enq > 0) {
1934 /* Kick. */
1935 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1936 sc->ale_cdata.ale_tx_prod);
1937 /* Set a timeout in case the chip goes out to lunch. */
1938 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1939 }
1940 }
1941
1942 static void
1943 ale_watchdog(struct ale_softc *sc)
1944 {
1945 struct ifnet *ifp;
1946
1947 ALE_LOCK_ASSERT(sc);
1948
1949 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1950 return;
1951
1952 ifp = sc->ale_ifp;
1953 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1954 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1955 ifp->if_oerrors++;
1956 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1957 ale_init_locked(sc);
1958 return;
1959 }
1960 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1961 ifp->if_oerrors++;
1962 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1963 ale_init_locked(sc);
1964 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1965 ale_start_locked(ifp);
1966 }
1967
1968 static int
1969 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1970 {
1971 struct ale_softc *sc;
1972 struct ifreq *ifr;
1973 struct mii_data *mii;
1974 int error, mask;
1975
1976 sc = ifp->if_softc;
1977 ifr = (struct ifreq *)data;
1978 error = 0;
1979 switch (cmd) {
1980 case SIOCSIFMTU:
1981 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1982 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1983 ifr->ifr_mtu > ETHERMTU))
1984 error = EINVAL;
1985 else if (ifp->if_mtu != ifr->ifr_mtu) {
1986 ALE_LOCK(sc);
1987 ifp->if_mtu = ifr->ifr_mtu;
1988 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1989 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1990 ale_init_locked(sc);
1991 }
1992 ALE_UNLOCK(sc);
1993 }
1994 break;
1995 case SIOCSIFFLAGS:
1996 ALE_LOCK(sc);
1997 if ((ifp->if_flags & IFF_UP) != 0) {
1998 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1999 if (((ifp->if_flags ^ sc->ale_if_flags)
2000 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2001 ale_rxfilter(sc);
2002 } else {
2003 ale_init_locked(sc);
2004 }
2005 } else {
2006 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2007 ale_stop(sc);
2008 }
2009 sc->ale_if_flags = ifp->if_flags;
2010 ALE_UNLOCK(sc);
2011 break;
2012 case SIOCADDMULTI:
2013 case SIOCDELMULTI:
2014 ALE_LOCK(sc);
2015 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2016 ale_rxfilter(sc);
2017 ALE_UNLOCK(sc);
2018 break;
2019 case SIOCSIFMEDIA:
2020 case SIOCGIFMEDIA:
2021 mii = device_get_softc(sc->ale_miibus);
2022 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2023 break;
2024 case SIOCSIFCAP:
2025 ALE_LOCK(sc);
2026 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2027 if ((mask & IFCAP_TXCSUM) != 0 &&
2028 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2029 ifp->if_capenable ^= IFCAP_TXCSUM;
2030 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2031 ifp->if_hwassist |= ALE_CSUM_FEATURES;
2032 else
2033 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2034 }
2035 if ((mask & IFCAP_RXCSUM) != 0 &&
2036 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2037 ifp->if_capenable ^= IFCAP_RXCSUM;
2038 if ((mask & IFCAP_TSO4) != 0 &&
2039 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2040 ifp->if_capenable ^= IFCAP_TSO4;
2041 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2042 ifp->if_hwassist |= CSUM_TSO;
2043 else
2044 ifp->if_hwassist &= ~CSUM_TSO;
2045 }
2046
2047 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2048 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2049 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2050 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2051 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2052 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2053 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2054 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2055 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2056 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2057 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2058 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2059 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2060 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2061 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2062 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2063 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2064 ale_rxvlan(sc);
2065 }
2066 ALE_UNLOCK(sc);
2067 VLAN_CAPABILITIES(ifp);
2068 break;
2069 default:
2070 error = ether_ioctl(ifp, cmd, data);
2071 break;
2072 }
2073
2074 return (error);
2075 }
2076
2077 static void
2078 ale_mac_config(struct ale_softc *sc)
2079 {
2080 struct mii_data *mii;
2081 uint32_t reg;
2082
2083 ALE_LOCK_ASSERT(sc);
2084
2085 mii = device_get_softc(sc->ale_miibus);
2086 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2087 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2088 MAC_CFG_SPEED_MASK);
2089 /* Reprogram MAC with resolved speed/duplex. */
2090 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2091 case IFM_10_T:
2092 case IFM_100_TX:
2093 reg |= MAC_CFG_SPEED_10_100;
2094 break;
2095 case IFM_1000_T:
2096 reg |= MAC_CFG_SPEED_1000;
2097 break;
2098 }
2099 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2100 reg |= MAC_CFG_FULL_DUPLEX;
2101 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2102 reg |= MAC_CFG_TX_FC;
2103 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2104 reg |= MAC_CFG_RX_FC;
2105 }
2106 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2107 }
2108
2109 static void
2110 ale_stats_clear(struct ale_softc *sc)
2111 {
2112 struct smb sb;
2113 uint32_t *reg;
2114 int i;
2115
2116 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2117 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2118 i += sizeof(uint32_t);
2119 }
2120 /* Read Tx statistics. */
2121 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2122 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2123 i += sizeof(uint32_t);
2124 }
2125 }
2126
2127 static void
2128 ale_stats_update(struct ale_softc *sc)
2129 {
2130 struct ale_hw_stats *stat;
2131 struct smb sb, *smb;
2132 struct ifnet *ifp;
2133 uint32_t *reg;
2134 int i;
2135
2136 ALE_LOCK_ASSERT(sc);
2137
2138 ifp = sc->ale_ifp;
2139 stat = &sc->ale_stats;
2140 smb = &sb;
2141
2142 /* Read Rx statistics. */
2143 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2144 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2145 i += sizeof(uint32_t);
2146 }
2147 /* Read Tx statistics. */
2148 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2149 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2150 i += sizeof(uint32_t);
2151 }
2152
2153 /* Rx stats. */
2154 stat->rx_frames += smb->rx_frames;
2155 stat->rx_bcast_frames += smb->rx_bcast_frames;
2156 stat->rx_mcast_frames += smb->rx_mcast_frames;
2157 stat->rx_pause_frames += smb->rx_pause_frames;
2158 stat->rx_control_frames += smb->rx_control_frames;
2159 stat->rx_crcerrs += smb->rx_crcerrs;
2160 stat->rx_lenerrs += smb->rx_lenerrs;
2161 stat->rx_bytes += smb->rx_bytes;
2162 stat->rx_runts += smb->rx_runts;
2163 stat->rx_fragments += smb->rx_fragments;
2164 stat->rx_pkts_64 += smb->rx_pkts_64;
2165 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2166 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2167 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2168 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2169 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2170 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2171 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2172 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2173 stat->rx_rrs_errs += smb->rx_rrs_errs;
2174 stat->rx_alignerrs += smb->rx_alignerrs;
2175 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2176 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2177 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2178
2179 /* Tx stats. */
2180 stat->tx_frames += smb->tx_frames;
2181 stat->tx_bcast_frames += smb->tx_bcast_frames;
2182 stat->tx_mcast_frames += smb->tx_mcast_frames;
2183 stat->tx_pause_frames += smb->tx_pause_frames;
2184 stat->tx_excess_defer += smb->tx_excess_defer;
2185 stat->tx_control_frames += smb->tx_control_frames;
2186 stat->tx_deferred += smb->tx_deferred;
2187 stat->tx_bytes += smb->tx_bytes;
2188 stat->tx_pkts_64 += smb->tx_pkts_64;
2189 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2190 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2191 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2192 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2193 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2194 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2195 stat->tx_single_colls += smb->tx_single_colls;
2196 stat->tx_multi_colls += smb->tx_multi_colls;
2197 stat->tx_late_colls += smb->tx_late_colls;
2198 stat->tx_excess_colls += smb->tx_excess_colls;
2199 stat->tx_abort += smb->tx_abort;
2200 stat->tx_underrun += smb->tx_underrun;
2201 stat->tx_desc_underrun += smb->tx_desc_underrun;
2202 stat->tx_lenerrs += smb->tx_lenerrs;
2203 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2204 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2205 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2206
2207 /* Update counters in ifnet. */
2208 ifp->if_opackets += smb->tx_frames;
2209
2210 ifp->if_collisions += smb->tx_single_colls +
2211 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2212 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2213
2214 /*
2215 * XXX
2216 * tx_pkts_truncated counter looks suspicious. It constantly
2217 * increments with no sign of Tx errors. This may indicate
2218 * the counter name is not correct one so I've removed the
2219 * counter in output errors.
2220 */
2221 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2222 smb->tx_underrun;
2223
2224 ifp->if_ipackets += smb->rx_frames;
2225
2226 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2227 smb->rx_runts + smb->rx_pkts_truncated +
2228 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2229 smb->rx_alignerrs;
2230 }
2231
2232 static int
2233 ale_intr(void *arg)
2234 {
2235 struct ale_softc *sc;
2236 uint32_t status;
2237
2238 sc = (struct ale_softc *)arg;
2239
2240 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2241 if ((status & ALE_INTRS) == 0)
2242 return (FILTER_STRAY);
2243 /* Disable interrupts. */
2244 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2245 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2246
2247 return (FILTER_HANDLED);
2248 }
2249
2250 static void
2251 ale_int_task(void *arg, int pending)
2252 {
2253 struct ale_softc *sc;
2254 struct ifnet *ifp;
2255 uint32_t status;
2256 int more;
2257
2258 sc = (struct ale_softc *)arg;
2259
2260 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2261 ALE_LOCK(sc);
2262 if (sc->ale_morework != 0)
2263 status |= INTR_RX_PKT;
2264 if ((status & ALE_INTRS) == 0)
2265 goto done;
2266
2267 /* Acknowledge interrupts but still disable interrupts. */
2268 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2269
2270 ifp = sc->ale_ifp;
2271 more = 0;
2272 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2273 more = ale_rxeof(sc, sc->ale_process_limit);
2274 if (more == EAGAIN)
2275 sc->ale_morework = 1;
2276 else if (more == EIO) {
2277 sc->ale_stats.reset_brk_seq++;
2278 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2279 ale_init_locked(sc);
2280 ALE_UNLOCK(sc);
2281 return;
2282 }
2283
2284 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2285 if ((status & INTR_DMA_RD_TO_RST) != 0)
2286 device_printf(sc->ale_dev,
2287 "DMA read error! -- resetting\n");
2288 if ((status & INTR_DMA_WR_TO_RST) != 0)
2289 device_printf(sc->ale_dev,
2290 "DMA write error! -- resetting\n");
2291 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2292 ale_init_locked(sc);
2293 ALE_UNLOCK(sc);
2294 return;
2295 }
2296 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2297 ale_start_locked(ifp);
2298 }
2299
2300 if (more == EAGAIN ||
2301 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2302 ALE_UNLOCK(sc);
2303 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2304 return;
2305 }
2306
2307 done:
2308 ALE_UNLOCK(sc);
2309
2310 /* Re-enable interrupts. */
2311 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2312 }
2313
2314 static void
2315 ale_txeof(struct ale_softc *sc)
2316 {
2317 struct ifnet *ifp;
2318 struct ale_txdesc *txd;
2319 uint32_t cons, prod;
2320 int prog;
2321
2322 ALE_LOCK_ASSERT(sc);
2323
2324 ifp = sc->ale_ifp;
2325
2326 if (sc->ale_cdata.ale_tx_cnt == 0)
2327 return;
2328
2329 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2330 sc->ale_cdata.ale_tx_ring_map,
2331 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2332 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2333 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2334 sc->ale_cdata.ale_tx_cmb_map,
2335 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2336 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2337 } else
2338 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2339 cons = sc->ale_cdata.ale_tx_cons;
2340 /*
2341 * Go through our Tx list and free mbufs for those
2342 * frames which have been transmitted.
2343 */
2344 for (prog = 0; cons != prod; prog++,
2345 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2346 if (sc->ale_cdata.ale_tx_cnt <= 0)
2347 break;
2348 prog++;
2349 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2350 sc->ale_cdata.ale_tx_cnt--;
2351 txd = &sc->ale_cdata.ale_txdesc[cons];
2352 if (txd->tx_m != NULL) {
2353 /* Reclaim transmitted mbufs. */
2354 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2355 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2356 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2357 txd->tx_dmamap);
2358 m_freem(txd->tx_m);
2359 txd->tx_m = NULL;
2360 }
2361 }
2362
2363 if (prog > 0) {
2364 sc->ale_cdata.ale_tx_cons = cons;
2365 /*
2366 * Unarm watchdog timer only when there is no pending
2367 * Tx descriptors in queue.
2368 */
2369 if (sc->ale_cdata.ale_tx_cnt == 0)
2370 sc->ale_watchdog_timer = 0;
2371 }
2372 }
2373
2374 static void
2375 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2376 uint32_t length, uint32_t *prod)
2377 {
2378 struct ale_rx_page *rx_page;
2379
2380 rx_page = *page;
2381 /* Update consumer position. */
2382 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2383 ALE_RX_PAGE_ALIGN);
2384 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2385 /*
2386 * End of Rx page reached, let hardware reuse
2387 * this page.
2388 */
2389 rx_page->cons = 0;
2390 *rx_page->cmb_addr = 0;
2391 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2393 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2394 RXF_VALID);
2395 /* Switch to alternate Rx page. */
2396 sc->ale_cdata.ale_rx_curp ^= 1;
2397 rx_page = *page =
2398 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2399 /* Page flipped, sync CMB and Rx page. */
2400 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2401 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2402 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2403 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2404 /* Sync completed, cache updated producer index. */
2405 *prod = *rx_page->cmb_addr;
2406 }
2407 }
2408
2409
2410 /*
2411 * It seems that AR81xx controller can compute partial checksum.
2412 * The partial checksum value can be used to accelerate checksum
2413 * computation for fragmented TCP/UDP packets. Upper network stack
2414 * already takes advantage of the partial checksum value in IP
2415 * reassembly stage. But I'm not sure the correctness of the
2416 * partial hardware checksum assistance due to lack of data sheet.
2417 * In addition, the Rx feature of controller that requires copying
2418 * for every frames effectively nullifies one of most nice offload
2419 * capability of controller.
2420 */
2421 static void
2422 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2423 {
2424 struct ifnet *ifp;
2425 struct ip *ip;
2426 char *p;
2427
2428 ifp = sc->ale_ifp;
2429 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2430 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2431 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2432
2433 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2434 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2435 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2436 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2437 m->m_pkthdr.csum_flags |=
2438 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2439 m->m_pkthdr.csum_data = 0xffff;
2440 }
2441 } else {
2442 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2443 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2444 p = mtod(m, char *);
2445 p += ETHER_HDR_LEN;
2446 if ((status & ALE_RD_802_3) != 0)
2447 p += LLC_SNAPFRAMELEN;
2448 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2449 (status & ALE_RD_VLAN) != 0)
2450 p += ETHER_VLAN_ENCAP_LEN;
2451 ip = (struct ip *)p;
2452 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2453 return;
2454 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2455 CSUM_PSEUDO_HDR;
2456 m->m_pkthdr.csum_data = 0xffff;
2457 }
2458 }
2459 /*
2460 * Don't mark bad checksum for TCP/UDP frames
2461 * as fragmented frames may always have set
2462 * bad checksummed bit of frame status.
2463 */
2464 }
2465
2466 /* Process received frames. */
2467 static int
2468 ale_rxeof(struct ale_softc *sc, int count)
2469 {
2470 struct ale_rx_page *rx_page;
2471 struct rx_rs *rs;
2472 struct ifnet *ifp;
2473 struct mbuf *m;
2474 uint32_t length, prod, seqno, status, vtags;
2475 int prog;
2476
2477 ifp = sc->ale_ifp;
2478 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2479 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2480 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2481 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2482 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2483 /*
2484 * Don't directly access producer index as hardware may
2485 * update it while Rx handler is in progress. It would
2486 * be even better if there is a way to let hardware
2487 * know how far driver processed its received frames.
2488 * Alternatively, hardware could provide a way to disable
2489 * CMB updates until driver acknowledges the end of CMB
2490 * access.
2491 */
2492 prod = *rx_page->cmb_addr;
2493 for (prog = 0; prog < count; prog++) {
2494 if (rx_page->cons >= prod)
2495 break;
2496 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2497 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2498 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2499 /*
2500 * Normally I believe this should not happen unless
2501 * severe driver bug or corrupted memory. However
2502 * it seems to happen under certain conditions which
2503 * is triggered by abrupt Rx events such as initiation
2504 * of bulk transfer of remote host. It's not easy to
2505 * reproduce this and I doubt it could be related
2506 * with FIFO overflow of hardware or activity of Tx
2507 * CMB updates. I also remember similar behaviour
2508 * seen on RealTek 8139 which uses resembling Rx
2509 * scheme.
2510 */
2511 if (bootverbose)
2512 device_printf(sc->ale_dev,
2513 "garbled seq: %u, expected: %u -- "
2514 "resetting!\n", seqno,
2515 sc->ale_cdata.ale_rx_seqno);
2516 return (EIO);
2517 }
2518 /* Frame received. */
2519 sc->ale_cdata.ale_rx_seqno++;
2520 length = ALE_RX_BYTES(le32toh(rs->length));
2521 status = le32toh(rs->flags);
2522 if ((status & ALE_RD_ERROR) != 0) {
2523 /*
2524 * We want to pass the following frames to upper
2525 * layer regardless of error status of Rx return
2526 * status.
2527 *
2528 * o IP/TCP/UDP checksum is bad.
2529 * o frame length and protocol specific length
2530 * does not match.
2531 */
2532 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2533 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2534 ALE_RD_TRUNC)) != 0) {
2535 ale_rx_update_page(sc, &rx_page, length, &prod);
2536 continue;
2537 }
2538 }
2539 /*
2540 * m_devget(9) is major bottle-neck of ale(4)(It comes
2541 * from hardware limitation). For jumbo frames we could
2542 * get a slightly better performance if driver use
2543 * m_getjcl(9) with proper buffer size argument. However
2544 * that would make code more complicated and I don't
2545 * think users would expect good Rx performance numbers
2546 * on these low-end consumer ethernet controller.
2547 */
2548 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2549 ETHER_ALIGN, ifp, NULL);
2550 if (m == NULL) {
2551 ifp->if_iqdrops++;
2552 ale_rx_update_page(sc, &rx_page, length, &prod);
2553 continue;
2554 }
2555 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2556 (status & ALE_RD_IPV4) != 0)
2557 ale_rxcsum(sc, m, status);
2558 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2559 (status & ALE_RD_VLAN) != 0) {
2560 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2561 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2562 m->m_flags |= M_VLANTAG;
2563 }
2564
2565 /* Pass it to upper layer. */
2566 ALE_UNLOCK(sc);
2567 (*ifp->if_input)(ifp, m);
2568 ALE_LOCK(sc);
2569
2570 ale_rx_update_page(sc, &rx_page, length, &prod);
2571 }
2572
2573 return (count > 0 ? 0 : EAGAIN);
2574 }
2575
2576 static void
2577 ale_tick(void *arg)
2578 {
2579 struct ale_softc *sc;
2580 struct mii_data *mii;
2581
2582 sc = (struct ale_softc *)arg;
2583
2584 ALE_LOCK_ASSERT(sc);
2585
2586 mii = device_get_softc(sc->ale_miibus);
2587 mii_tick(mii);
2588 ale_stats_update(sc);
2589 /*
2590 * Reclaim Tx buffers that have been transferred. It's not
2591 * needed here but it would release allocated mbuf chains
2592 * faster and limit the maximum delay to a hz.
2593 */
2594 ale_txeof(sc);
2595 ale_watchdog(sc);
2596 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2597 }
2598
2599 static void
2600 ale_reset(struct ale_softc *sc)
2601 {
2602 uint32_t reg;
2603 int i;
2604
2605 /* Initialize PCIe module. From Linux. */
2606 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2607
2608 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2609 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2610 DELAY(10);
2611 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2612 break;
2613 }
2614 if (i == 0)
2615 device_printf(sc->ale_dev, "master reset timeout!\n");
2616
2617 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2618 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2619 break;
2620 DELAY(10);
2621 }
2622
2623 if (i == 0)
2624 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2625 }
2626
2627 static void
2628 ale_init(void *xsc)
2629 {
2630 struct ale_softc *sc;
2631
2632 sc = (struct ale_softc *)xsc;
2633 ALE_LOCK(sc);
2634 ale_init_locked(sc);
2635 ALE_UNLOCK(sc);
2636 }
2637
2638 static void
2639 ale_init_locked(struct ale_softc *sc)
2640 {
2641 struct ifnet *ifp;
2642 struct mii_data *mii;
2643 uint8_t eaddr[ETHER_ADDR_LEN];
2644 bus_addr_t paddr;
2645 uint32_t reg, rxf_hi, rxf_lo;
2646
2647 ALE_LOCK_ASSERT(sc);
2648
2649 ifp = sc->ale_ifp;
2650 mii = device_get_softc(sc->ale_miibus);
2651
2652 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2653 return;
2654 /*
2655 * Cancel any pending I/O.
2656 */
2657 ale_stop(sc);
2658 /*
2659 * Reset the chip to a known state.
2660 */
2661 ale_reset(sc);
2662 /* Initialize Tx descriptors, DMA memory blocks. */
2663 ale_init_rx_pages(sc);
2664 ale_init_tx_ring(sc);
2665
2666 /* Reprogram the station address. */
2667 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2668 CSR_WRITE_4(sc, ALE_PAR0,
2669 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2670 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2671 /*
2672 * Clear WOL status and disable all WOL feature as WOL
2673 * would interfere Rx operation under normal environments.
2674 */
2675 CSR_READ_4(sc, ALE_WOL_CFG);
2676 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2677 /*
2678 * Set Tx descriptor/RXF0/CMB base addresses. They share
2679 * the same high address part of DMAable region.
2680 */
2681 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2682 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2683 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2684 CSR_WRITE_4(sc, ALE_TPD_CNT,
2685 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2686 /* Set Rx page base address, note we use single queue. */
2687 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2688 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2689 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2690 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2691 /* Set Tx/Rx CMB addresses. */
2692 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2693 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2694 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2695 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2696 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2697 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2698 /* Mark RXF0 is valid. */
2699 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2700 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2701 /*
2702 * No need to initialize RFX1/RXF2/RXF3. We don't use
2703 * multi-queue yet.
2704 */
2705
2706 /* Set Rx page size, excluding guard frame size. */
2707 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2708 /* Tell hardware that we're ready to load DMA blocks. */
2709 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2710
2711 /* Set Rx/Tx interrupt trigger threshold. */
2712 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2713 (4 << INT_TRIG_TX_THRESH_SHIFT));
2714 /*
2715 * XXX
2716 * Set interrupt trigger timer, its purpose and relation
2717 * with interrupt moderation mechanism is not clear yet.
2718 */
2719 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2720 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2721 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2722
2723 /* Configure interrupt moderation timer. */
2724 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2725 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2726 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2727 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2728 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2729 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2730 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2731 reg |= MASTER_IM_RX_TIMER_ENB;
2732 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2733 reg |= MASTER_IM_TX_TIMER_ENB;
2734 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2735 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2736
2737 /* Set Maximum frame size of controller. */
2738 if (ifp->if_mtu < ETHERMTU)
2739 sc->ale_max_frame_size = ETHERMTU;
2740 else
2741 sc->ale_max_frame_size = ifp->if_mtu;
2742 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2743 ETHER_CRC_LEN;
2744 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2745 /* Configure IPG/IFG parameters. */
2746 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2747 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2748 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2749 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2750 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2751 /* Set parameters for half-duplex media. */
2752 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2753 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2754 HDPX_CFG_LCOL_MASK) |
2755 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2756 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2757 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2758 HDPX_CFG_ABEBT_MASK) |
2759 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2760 HDPX_CFG_JAMIPG_MASK));
2761
2762 /* Configure Tx jumbo frame parameters. */
2763 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2764 if (ifp->if_mtu < ETHERMTU)
2765 reg = sc->ale_max_frame_size;
2766 else if (ifp->if_mtu < 6 * 1024)
2767 reg = (sc->ale_max_frame_size * 2) / 3;
2768 else
2769 reg = sc->ale_max_frame_size / 2;
2770 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2771 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2772 TX_JUMBO_THRESH_UNIT_SHIFT);
2773 }
2774 /* Configure TxQ. */
2775 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2776 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2777 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2778 TXQ_CFG_TPD_BURST_MASK;
2779 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2780
2781 /* Configure Rx jumbo frame & flow control parameters. */
2782 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2783 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2784 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2785 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2786 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2787 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2788 RX_JUMBO_LKAH_MASK));
2789 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2790 rxf_hi = (reg * 7) / 10;
2791 rxf_lo = (reg * 3)/ 10;
2792 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2793 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2794 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2795 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2796 RX_FIFO_PAUSE_THRESH_HI_MASK));
2797 }
2798
2799 /* Disable RSS. */
2800 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2801 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2802
2803 /* Configure RxQ. */
2804 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2805 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2806
2807 /* Configure DMA parameters. */
2808 reg = 0;
2809 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2810 reg |= DMA_CFG_TXCMB_ENB;
2811 CSR_WRITE_4(sc, ALE_DMA_CFG,
2812 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2813 sc->ale_dma_rd_burst | reg |
2814 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2815 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2816 DMA_CFG_RD_DELAY_CNT_MASK) |
2817 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2818 DMA_CFG_WR_DELAY_CNT_MASK));
2819
2820 /*
2821 * Hardware can be configured to issue SMB interrupt based
2822 * on programmed interval. Since there is a callout that is
2823 * invoked for every hz in driver we use that instead of
2824 * relying on periodic SMB interrupt.
2825 */
2826 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2827 /* Clear MAC statistics. */
2828 ale_stats_clear(sc);
2829
2830 /*
2831 * Configure Tx/Rx MACs.
2832 * - Auto-padding for short frames.
2833 * - Enable CRC generation.
2834 * Actual reconfiguration of MAC for resolved speed/duplex
2835 * is followed after detection of link establishment.
2836 * AR81xx always does checksum computation regardless of
2837 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2838 * cause Rx handling issue for fragmented IP datagrams due
2839 * to silicon bug.
2840 */
2841 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2842 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2843 MAC_CFG_PREAMBLE_MASK);
2844 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2845 reg |= MAC_CFG_SPEED_10_100;
2846 else
2847 reg |= MAC_CFG_SPEED_1000;
2848 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2849
2850 /* Set up the receive filter. */
2851 ale_rxfilter(sc);
2852 ale_rxvlan(sc);
2853
2854 /* Acknowledge all pending interrupts and clear it. */
2855 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2856 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2857 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2858
2859 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2860 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2861
2862 sc->ale_flags &= ~ALE_FLAG_LINK;
2863 /* Switch to the current media. */
2864 mii_mediachg(mii);
2865
2866 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2867 }
2868
2869 static void
2870 ale_stop(struct ale_softc *sc)
2871 {
2872 struct ifnet *ifp;
2873 struct ale_txdesc *txd;
2874 uint32_t reg;
2875 int i;
2876
2877 ALE_LOCK_ASSERT(sc);
2878 /*
2879 * Mark the interface down and cancel the watchdog timer.
2880 */
2881 ifp = sc->ale_ifp;
2882 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2883 sc->ale_flags &= ~ALE_FLAG_LINK;
2884 callout_stop(&sc->ale_tick_ch);
2885 sc->ale_watchdog_timer = 0;
2886 ale_stats_update(sc);
2887 /* Disable interrupts. */
2888 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2889 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2890 /* Disable queue processing and DMA. */
2891 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2892 reg &= ~TXQ_CFG_ENB;
2893 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2894 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2895 reg &= ~RXQ_CFG_ENB;
2896 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2897 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2898 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2899 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2900 DELAY(1000);
2901 /* Stop Rx/Tx MACs. */
2902 ale_stop_mac(sc);
2903 /* Disable interrupts which might be touched in taskq handler. */
2904 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2905
2906 /*
2907 * Free TX mbufs still in the queues.
2908 */
2909 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2910 txd = &sc->ale_cdata.ale_txdesc[i];
2911 if (txd->tx_m != NULL) {
2912 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2913 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2914 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2915 txd->tx_dmamap);
2916 m_freem(txd->tx_m);
2917 txd->tx_m = NULL;
2918 }
2919 }
2920 }
2921
2922 static void
2923 ale_stop_mac(struct ale_softc *sc)
2924 {
2925 uint32_t reg;
2926 int i;
2927
2928 ALE_LOCK_ASSERT(sc);
2929
2930 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2931 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2932 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2933 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2934 }
2935
2936 for (i = ALE_TIMEOUT; i > 0; i--) {
2937 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2938 if (reg == 0)
2939 break;
2940 DELAY(10);
2941 }
2942 if (i == 0)
2943 device_printf(sc->ale_dev,
2944 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2945 }
2946
2947 static void
2948 ale_init_tx_ring(struct ale_softc *sc)
2949 {
2950 struct ale_txdesc *txd;
2951 int i;
2952
2953 ALE_LOCK_ASSERT(sc);
2954
2955 sc->ale_cdata.ale_tx_prod = 0;
2956 sc->ale_cdata.ale_tx_cons = 0;
2957 sc->ale_cdata.ale_tx_cnt = 0;
2958
2959 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2960 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2961 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2962 txd = &sc->ale_cdata.ale_txdesc[i];
2963 txd->tx_m = NULL;
2964 }
2965 *sc->ale_cdata.ale_tx_cmb = 0;
2966 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2967 sc->ale_cdata.ale_tx_cmb_map,
2968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2969 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2970 sc->ale_cdata.ale_tx_ring_map,
2971 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2972 }
2973
2974 static void
2975 ale_init_rx_pages(struct ale_softc *sc)
2976 {
2977 struct ale_rx_page *rx_page;
2978 int i;
2979
2980 ALE_LOCK_ASSERT(sc);
2981
2982 sc->ale_morework = 0;
2983 sc->ale_cdata.ale_rx_seqno = 0;
2984 sc->ale_cdata.ale_rx_curp = 0;
2985
2986 for (i = 0; i < ALE_RX_PAGES; i++) {
2987 rx_page = &sc->ale_cdata.ale_rx_page[i];
2988 bzero(rx_page->page_addr, sc->ale_pagesize);
2989 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2990 rx_page->cons = 0;
2991 *rx_page->cmb_addr = 0;
2992 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2994 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2996 }
2997 }
2998
2999 static void
3000 ale_rxvlan(struct ale_softc *sc)
3001 {
3002 struct ifnet *ifp;
3003 uint32_t reg;
3004
3005 ALE_LOCK_ASSERT(sc);
3006
3007 ifp = sc->ale_ifp;
3008 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3009 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3010 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3011 reg |= MAC_CFG_VLAN_TAG_STRIP;
3012 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3013 }
3014
3015 static void
3016 ale_rxfilter(struct ale_softc *sc)
3017 {
3018 struct ifnet *ifp;
3019 struct ifmultiaddr *ifma;
3020 uint32_t crc;
3021 uint32_t mchash[2];
3022 uint32_t rxcfg;
3023
3024 ALE_LOCK_ASSERT(sc);
3025
3026 ifp = sc->ale_ifp;
3027
3028 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3029 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3030 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3031 rxcfg |= MAC_CFG_BCAST;
3032 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3033 if ((ifp->if_flags & IFF_PROMISC) != 0)
3034 rxcfg |= MAC_CFG_PROMISC;
3035 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3036 rxcfg |= MAC_CFG_ALLMULTI;
3037 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3038 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3039 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3040 return;
3041 }
3042
3043 /* Program new filter. */
3044 bzero(mchash, sizeof(mchash));
3045
3046 if_maddr_rlock(ifp);
3047 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3048 if (ifma->ifma_addr->sa_family != AF_LINK)
3049 continue;
3050 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3051 ifma->ifma_addr), ETHER_ADDR_LEN);
3052 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3053 }
3054 if_maddr_runlock(ifp);
3055
3056 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3057 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3058 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3059 }
3060
3061 static int
3062 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3063 {
3064 int error, value;
3065
3066 if (arg1 == NULL)
3067 return (EINVAL);
3068 value = *(int *)arg1;
3069 error = sysctl_handle_int(oidp, &value, 0, req);
3070 if (error || req->newptr == NULL)
3071 return (error);
3072 if (value < low || value > high)
3073 return (EINVAL);
3074 *(int *)arg1 = value;
3075
3076 return (0);
3077 }
3078
3079 static int
3080 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3081 {
3082 return (sysctl_int_range(oidp, arg1, arg2, req,
3083 ALE_PROC_MIN, ALE_PROC_MAX));
3084 }
3085
3086 static int
3087 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3088 {
3089
3090 return (sysctl_int_range(oidp, arg1, arg2, req,
3091 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
3092 }
Cache object: 259eb53395fd37efb476e9ef58d730b7
|