Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/altera/atse/a_api.h
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1 /*- 2 * Copyright (c) 2012 Bjoern A. Zeeb 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 7 * ("MRC2"), as part of the DARPA MRC research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: releng/11.0/sys/dev/altera/atse/a_api.h 271679 2014-09-16 15:45:53Z bz $ 31 */ 32 /* 33 * Altera, Embedded Peripherals IP, User Guide, v. 11.0, June 2011. 34 * UG-01085-11.0. 35 */ 36 37 #ifndef _A_API_H 38 #define _A_API_H 39 40 /* Table 16-1. Memory Map. */ 41 #define A_ONCHIP_FIFO_MEM_CORE_DATA 0x00 42 #define A_ONCHIP_FIFO_MEM_CORE_METADATA 0x04 43 44 #define A_ONCHIP_FIFO_MEM_CORE_SOP (1<<0) 45 #define A_ONCHIP_FIFO_MEM_CORE_EOP (1<<1) 46 #define A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK 0x000000f7 47 #define A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT 2 48 /* Reserved (1<<7) */ 49 #define A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK 0x0000ff00 50 #define A_ONCHIP_FIFO_MEM_CORE_CHANNEL_SHIFT 8 51 #define A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK 0x00ff0000 52 #define A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT 16 53 /* Reserved 0xff000000 */ 54 55 /* Table 16-3. FIFO Status Register Memory Map. */ 56 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL 0x00 57 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_I_STATUS 0x04 58 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT 0x08 59 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE 0x0c 60 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTFULL 0x10 61 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTEMPTY 0x14 62 63 /* Table 16-5. Status Bit Field Descriptions. */ 64 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_FULL (1<<0) 65 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_EMPTY (1<<1) 66 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTFULL (1<<2) 67 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTEMPTY (1<<3) 68 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_OVERFLOW (1<<4) 69 #define A_ONCHIP_FIFO_MEM_CORE_STATUS_UNDERFLOW (1<<5) 70 71 /* Table 16-6. Event Bit Field Descriptions. */ 72 /* XXX Datasheet has incorrect bit fields. Validate. */ 73 #define A_ONCHIP_FIFO_MEM_CORE_EVENT_FULL (1<<0) 74 #define A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY (1<<1) 75 #define A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTFULL (1<<2) 76 #define A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTEMPTY (1<<3) 77 #define A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW (1<<4) 78 #define A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW (1<<5) 79 80 /* Table 16-7. InterruptEnable Bit Field Descriptions. */ 81 /* XXX Datasheet has incorrect bit fields. Validate. */ 82 #define A_ONCHIP_FIFO_MEM_CORE_INTR_FULL (1<<0) 83 #define A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY (1<<1) 84 #define A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL (1<<2) 85 #define A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY (1<<3) 86 #define A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW (1<<4) 87 #define A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW (1<<5) 88 #define A_ONCHIP_FIFO_MEM_CORE_INTR_ALL \ 89 (A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY| \ 90 A_ONCHIP_FIFO_MEM_CORE_INTR_FULL| \ 91 A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY| \ 92 A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL| \ 93 A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW| \ 94 A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW) 95 96 #endif /* _A_API_H */ 97 98 /* end */
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