1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012, 2013 Bjoern A. Zeeb
5 * Copyright (c) 2014 Robert N. M. Watson
6 * Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com>
7 * All rights reserved.
8 *
9 * This software was developed by SRI International and the University of
10 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
11 * ("MRC2"), as part of the DARPA MRC research programme.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34 /*
35 * Altera Triple-Speed Ethernet MegaCore, Function User Guide
36 * UG-01008-3.0, Software Version: 12.0, June 2012.
37 * Available at the time of writing at:
38 * http://www.altera.com/literature/ug/ug_ethernet.pdf
39 *
40 * We are using an Marvell E1111 (Alaska) PHY on the DE4. See mii/e1000phy.c.
41 */
42 /*
43 * XXX-BZ NOTES:
44 * - ifOutBroadcastPkts are only counted if both ether dst and src are all-1s;
45 * seems an IP core bug, they count ether broadcasts as multicast. Is this
46 * still the case?
47 * - figure out why the TX FIFO fill status and intr did not work as expected.
48 * - test 100Mbit/s and 10Mbit/s
49 * - blacklist the one special factory programmed ethernet address (for now
50 * hardcoded, later from loader?)
51 * - resolve all XXX, left as reminders to shake out details later
52 * - Jumbo frame support
53 */
54
55 #include <sys/cdefs.h>
56 __FBSDID("$FreeBSD$");
57
58 #include "opt_device_polling.h"
59
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/bus.h>
64 #include <sys/endian.h>
65 #include <sys/jail.h>
66 #include <sys/lock.h>
67 #include <sys/module.h>
68 #include <sys/mutex.h>
69 #include <sys/proc.h>
70 #include <sys/socket.h>
71 #include <sys/sockio.h>
72 #include <sys/types.h>
73
74 #include <net/ethernet.h>
75 #include <net/if.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_vlan_var.h>
81
82 #include <net/bpf.h>
83
84 #include <machine/bus.h>
85 #include <machine/resource.h>
86 #include <sys/rman.h>
87
88 #include <dev/mii/mii.h>
89 #include <dev/mii/miivar.h>
90
91 #include <dev/altera/atse/if_atsereg.h>
92 #include <dev/xdma/xdma.h>
93
94 #define RX_QUEUE_SIZE 4096
95 #define TX_QUEUE_SIZE 4096
96 #define NUM_RX_MBUF 512
97 #define BUFRING_SIZE 8192
98
99 #include <machine/cache.h>
100
101 /* XXX once we'd do parallel attach, we need a global lock for this. */
102 #define ATSE_ETHERNET_OPTION_BITS_UNDEF 0
103 #define ATSE_ETHERNET_OPTION_BITS_READ 1
104 static int atse_ethernet_option_bits_flag = ATSE_ETHERNET_OPTION_BITS_UNDEF;
105 static uint8_t atse_ethernet_option_bits[ALTERA_ETHERNET_OPTION_BITS_LEN];
106
107 /*
108 * Softc and critical resource locking.
109 */
110 #define ATSE_LOCK(_sc) mtx_lock(&(_sc)->atse_mtx)
111 #define ATSE_UNLOCK(_sc) mtx_unlock(&(_sc)->atse_mtx)
112 #define ATSE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->atse_mtx, MA_OWNED)
113
114 #define ATSE_DEBUG
115 #undef ATSE_DEBUG
116
117 #ifdef ATSE_DEBUG
118 #define DPRINTF(format, ...) printf(format, __VA_ARGS__)
119 #else
120 #define DPRINTF(format, ...)
121 #endif
122
123 /*
124 * Register space access macros.
125 */
126 static inline void
127 csr_write_4(struct atse_softc *sc, uint32_t reg, uint32_t val4,
128 const char *f, const int l)
129 {
130
131 val4 = htole32(val4);
132 DPRINTF("[%s:%d] CSR W %s 0x%08x (0x%08x) = 0x%08x\n", f, l,
133 "atse_mem_res", reg, reg * 4, val4);
134 bus_write_4(sc->atse_mem_res, reg * 4, val4);
135 }
136
137 static inline uint32_t
138 csr_read_4(struct atse_softc *sc, uint32_t reg, const char *f, const int l)
139 {
140 uint32_t val4;
141
142 val4 = le32toh(bus_read_4(sc->atse_mem_res, reg * 4));
143 DPRINTF("[%s:%d] CSR R %s 0x%08x (0x%08x) = 0x%08x\n", f, l,
144 "atse_mem_res", reg, reg * 4, val4);
145
146 return (val4);
147 }
148
149 /*
150 * See page 5-2 that it's all dword offsets and the MS 16 bits need to be zero
151 * on write and ignored on read.
152 */
153 static inline void
154 pxx_write_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, uint16_t val,
155 const char *f, const int l, const char *s)
156 {
157 uint32_t val4;
158
159 val4 = htole32(val & 0x0000ffff);
160 DPRINTF("[%s:%d] %s W %s 0x%08x (0x%08jx) = 0x%08x\n", f, l, s,
161 "atse_mem_res", reg, (bmcr + reg) * 4, val4);
162 bus_write_4(sc->atse_mem_res, (bmcr + reg) * 4, val4);
163 }
164
165 static inline uint16_t
166 pxx_read_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, const char *f,
167 const int l, const char *s)
168 {
169 uint32_t val4;
170 uint16_t val;
171
172 val4 = bus_read_4(sc->atse_mem_res, (bmcr + reg) * 4);
173 val = le32toh(val4) & 0x0000ffff;
174 DPRINTF("[%s:%d] %s R %s 0x%08x (0x%08jx) = 0x%04x\n", f, l, s,
175 "atse_mem_res", reg, (bmcr + reg) * 4, val);
176
177 return (val);
178 }
179
180 #define CSR_WRITE_4(sc, reg, val) \
181 csr_write_4((sc), (reg), (val), __func__, __LINE__)
182 #define CSR_READ_4(sc, reg) \
183 csr_read_4((sc), (reg), __func__, __LINE__)
184 #define PCS_WRITE_2(sc, reg, val) \
185 pxx_write_2((sc), sc->atse_bmcr0, (reg), (val), __func__, __LINE__, \
186 "PCS")
187 #define PCS_READ_2(sc, reg) \
188 pxx_read_2((sc), sc->atse_bmcr0, (reg), __func__, __LINE__, "PCS")
189 #define PHY_WRITE_2(sc, reg, val) \
190 pxx_write_2((sc), sc->atse_bmcr1, (reg), (val), __func__, __LINE__, \
191 "PHY")
192 #define PHY_READ_2(sc, reg) \
193 pxx_read_2((sc), sc->atse_bmcr1, (reg), __func__, __LINE__, "PHY")
194
195 static void atse_tick(void *);
196 static int atse_detach(device_t);
197
198 devclass_t atse_devclass;
199
200 static int
201 atse_rx_enqueue(struct atse_softc *sc, uint32_t n)
202 {
203 struct mbuf *m;
204 int i;
205
206 for (i = 0; i < n; i++) {
207 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
208 if (m == NULL) {
209 device_printf(sc->dev,
210 "%s: Can't alloc rx mbuf\n", __func__);
211 return (-1);
212 }
213
214 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
215 xdma_enqueue_mbuf(sc->xchan_rx, &m, 0, 4, 4, XDMA_DEV_TO_MEM);
216 }
217
218 return (0);
219 }
220
221 static int
222 atse_xdma_tx_intr(void *arg, xdma_transfer_status_t *status)
223 {
224 xdma_transfer_status_t st;
225 struct atse_softc *sc;
226 struct ifnet *ifp;
227 struct mbuf *m;
228 int err;
229
230 sc = arg;
231
232 ATSE_LOCK(sc);
233
234 ifp = sc->atse_ifp;
235
236 for (;;) {
237 err = xdma_dequeue_mbuf(sc->xchan_tx, &m, &st);
238 if (err != 0) {
239 break;
240 }
241
242 if (st.error != 0) {
243 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
244 }
245
246 m_freem(m);
247 sc->txcount--;
248 }
249
250 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
251
252 ATSE_UNLOCK(sc);
253
254 return (0);
255 }
256
257 static int
258 atse_xdma_rx_intr(void *arg, xdma_transfer_status_t *status)
259 {
260 xdma_transfer_status_t st;
261 struct atse_softc *sc;
262 struct ifnet *ifp;
263 struct mbuf *m;
264 int err;
265 uint32_t cnt_processed;
266
267 sc = arg;
268
269 ATSE_LOCK(sc);
270
271 ifp = sc->atse_ifp;
272
273 cnt_processed = 0;
274 for (;;) {
275 err = xdma_dequeue_mbuf(sc->xchan_rx, &m, &st);
276 if (err != 0) {
277 break;
278 }
279 cnt_processed++;
280
281 if (st.error != 0) {
282 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
283 m_freem(m);
284 continue;
285 }
286
287 m->m_pkthdr.len = m->m_len = st.transferred;
288 m->m_pkthdr.rcvif = ifp;
289 m_adj(m, ETHER_ALIGN);
290 ATSE_UNLOCK(sc);
291 (*ifp->if_input)(ifp, m);
292 ATSE_LOCK(sc);
293 }
294
295 atse_rx_enqueue(sc, cnt_processed);
296
297 ATSE_UNLOCK(sc);
298
299 return (0);
300 }
301
302 static int
303 atse_transmit_locked(struct ifnet *ifp)
304 {
305 struct atse_softc *sc;
306 struct mbuf *m;
307 struct buf_ring *br;
308 int error;
309 int enq;
310
311 sc = ifp->if_softc;
312 br = sc->br;
313
314 enq = 0;
315
316 while ((m = drbr_peek(ifp, br)) != NULL) {
317 error = xdma_enqueue_mbuf(sc->xchan_tx, &m, 0, 4, 4, XDMA_MEM_TO_DEV);
318 if (error != 0) {
319 /* No space in request queue available yet. */
320 drbr_putback(ifp, br, m);
321 break;
322 }
323
324 drbr_advance(ifp, br);
325
326 sc->txcount++;
327 enq++;
328
329 /* If anyone is interested give them a copy. */
330 ETHER_BPF_MTAP(ifp, m);
331 }
332
333 if (enq > 0)
334 xdma_queue_submit(sc->xchan_tx);
335
336 return (0);
337 }
338
339 static int
340 atse_transmit(struct ifnet *ifp, struct mbuf *m)
341 {
342 struct atse_softc *sc;
343 struct buf_ring *br;
344 int error;
345
346 sc = ifp->if_softc;
347 br = sc->br;
348
349 ATSE_LOCK(sc);
350
351 mtx_lock(&sc->br_mtx);
352
353 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) {
354 error = drbr_enqueue(ifp, sc->br, m);
355 mtx_unlock(&sc->br_mtx);
356 ATSE_UNLOCK(sc);
357 return (error);
358 }
359
360 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) {
361 error = drbr_enqueue(ifp, sc->br, m);
362 mtx_unlock(&sc->br_mtx);
363 ATSE_UNLOCK(sc);
364 return (error);
365 }
366
367 error = drbr_enqueue(ifp, br, m);
368 if (error) {
369 mtx_unlock(&sc->br_mtx);
370 ATSE_UNLOCK(sc);
371 return (error);
372 }
373 error = atse_transmit_locked(ifp);
374
375 mtx_unlock(&sc->br_mtx);
376 ATSE_UNLOCK(sc);
377
378 return (error);
379 }
380
381 static void
382 atse_qflush(struct ifnet *ifp)
383 {
384 struct atse_softc *sc;
385
386 sc = ifp->if_softc;
387
388 printf("%s\n", __func__);
389 }
390
391 static int
392 atse_stop_locked(struct atse_softc *sc)
393 {
394 uint32_t mask, val4;
395 struct ifnet *ifp;
396 int i;
397
398 ATSE_LOCK_ASSERT(sc);
399
400 callout_stop(&sc->atse_tick);
401
402 ifp = sc->atse_ifp;
403 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
404
405 /* Disable MAC transmit and receive datapath. */
406 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA;
407 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
408 val4 &= ~mask;
409 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
410
411 /* Wait for bits to be cleared; i=100 is excessive. */
412 for (i = 0; i < 100; i++) {
413 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
414 if ((val4 & mask) == 0) {
415 break;
416 }
417 DELAY(10);
418 }
419
420 if ((val4 & mask) != 0) {
421 device_printf(sc->atse_dev, "Disabling MAC TX/RX timed out.\n");
422 /* Punt. */
423 }
424
425 sc->atse_flags &= ~ATSE_FLAGS_LINK;
426
427 return (0);
428 }
429
430 static u_int
431 atse_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
432 {
433 uint64_t *h = arg;
434 uint8_t *addr, x, y;
435 int i, j;
436
437 addr = LLADDR(sdl);
438 x = 0;
439 for (i = 0; i < ETHER_ADDR_LEN; i++) {
440 y = addr[i] & 0x01;
441 for (j = 1; j < 8; j++)
442 y ^= (addr[i] >> j) & 0x01;
443 x |= (y << i);
444 }
445 *h |= (1 << x);
446
447 return (1);
448 }
449
450 static int
451 atse_rxfilter_locked(struct atse_softc *sc)
452 {
453 struct ifnet *ifp;
454 uint32_t val4;
455 int i;
456
457 /* XXX-BZ can we find out if we have the MHASH synthesized? */
458 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
459 /* For simplicity always hash full 48 bits of addresses. */
460 if ((val4 & BASE_CFG_COMMAND_CONFIG_MHASH_SEL) != 0)
461 val4 &= ~BASE_CFG_COMMAND_CONFIG_MHASH_SEL;
462
463 ifp = sc->atse_ifp;
464 if (ifp->if_flags & IFF_PROMISC) {
465 val4 |= BASE_CFG_COMMAND_CONFIG_PROMIS_EN;
466 } else {
467 val4 &= ~BASE_CFG_COMMAND_CONFIG_PROMIS_EN;
468 }
469
470 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
471
472 if (ifp->if_flags & IFF_ALLMULTI) {
473 /* Accept all multicast addresses. */
474 for (i = 0; i <= MHASH_LEN; i++)
475 CSR_WRITE_4(sc, MHASH_START + i, 0x1);
476 } else {
477 /*
478 * Can hold MHASH_LEN entries.
479 * XXX-BZ bitstring.h would be more general.
480 */
481 uint64_t h;
482
483 /*
484 * Re-build and re-program hash table. First build the
485 * bit-field "yes" or "no" for each slot per address, then
486 * do all the programming afterwards.
487 */
488 h = 0;
489 (void)if_foreach_llmaddr(ifp, atse_hash_maddr, &h);
490 for (i = 0; i <= MHASH_LEN; i++) {
491 CSR_WRITE_4(sc, MHASH_START + i,
492 (h & (1 << i)) ? 0x01 : 0x00);
493 }
494 }
495
496 return (0);
497 }
498
499 static int
500 atse_ethernet_option_bits_read_fdt(device_t dev)
501 {
502 struct resource *res;
503 device_t fdev;
504 int i, rid;
505
506 if (atse_ethernet_option_bits_flag & ATSE_ETHERNET_OPTION_BITS_READ) {
507 return (0);
508 }
509
510 fdev = device_find_child(device_get_parent(dev), "cfi", 0);
511 if (fdev == NULL) {
512 return (ENOENT);
513 }
514
515 rid = 0;
516 res = bus_alloc_resource_any(fdev, SYS_RES_MEMORY, &rid,
517 RF_ACTIVE | RF_SHAREABLE);
518 if (res == NULL) {
519 return (ENXIO);
520 }
521
522 for (i = 0; i < ALTERA_ETHERNET_OPTION_BITS_LEN; i++) {
523 atse_ethernet_option_bits[i] = bus_read_1(res,
524 ALTERA_ETHERNET_OPTION_BITS_OFF + i);
525 }
526
527 bus_release_resource(fdev, SYS_RES_MEMORY, rid, res);
528 atse_ethernet_option_bits_flag |= ATSE_ETHERNET_OPTION_BITS_READ;
529
530 return (0);
531 }
532
533 static int
534 atse_ethernet_option_bits_read(device_t dev)
535 {
536 int error;
537
538 error = atse_ethernet_option_bits_read_fdt(dev);
539 if (error == 0)
540 return (0);
541
542 device_printf(dev, "Cannot read Ethernet addresses from flash.\n");
543
544 return (error);
545 }
546
547 static int
548 atse_get_eth_address(struct atse_softc *sc)
549 {
550 unsigned long hostid;
551 uint32_t val4;
552 int unit;
553
554 /*
555 * Make sure to only ever do this once. Otherwise a reset would
556 * possibly change our ethernet address, which is not good at all.
557 */
558 if (sc->atse_eth_addr[0] != 0x00 || sc->atse_eth_addr[1] != 0x00 ||
559 sc->atse_eth_addr[2] != 0x00) {
560 return (0);
561 }
562
563 if ((atse_ethernet_option_bits_flag &
564 ATSE_ETHERNET_OPTION_BITS_READ) == 0) {
565 goto get_random;
566 }
567
568 val4 = atse_ethernet_option_bits[0] << 24;
569 val4 |= atse_ethernet_option_bits[1] << 16;
570 val4 |= atse_ethernet_option_bits[2] << 8;
571 val4 |= atse_ethernet_option_bits[3];
572 /* They chose "safe". */
573 if (val4 != le32toh(0x00005afe)) {
574 device_printf(sc->atse_dev, "Magic '5afe' is not safe: 0x%08x. "
575 "Falling back to random numbers for hardware address.\n",
576 val4);
577 goto get_random;
578 }
579
580 sc->atse_eth_addr[0] = atse_ethernet_option_bits[4];
581 sc->atse_eth_addr[1] = atse_ethernet_option_bits[5];
582 sc->atse_eth_addr[2] = atse_ethernet_option_bits[6];
583 sc->atse_eth_addr[3] = atse_ethernet_option_bits[7];
584 sc->atse_eth_addr[4] = atse_ethernet_option_bits[8];
585 sc->atse_eth_addr[5] = atse_ethernet_option_bits[9];
586
587 /* Handle factory default ethernet addresss: 00:07:ed:ff:ed:15 */
588 if (sc->atse_eth_addr[0] == 0x00 && sc->atse_eth_addr[1] == 0x07 &&
589 sc->atse_eth_addr[2] == 0xed && sc->atse_eth_addr[3] == 0xff &&
590 sc->atse_eth_addr[4] == 0xed && sc->atse_eth_addr[5] == 0x15) {
591 device_printf(sc->atse_dev, "Factory programmed Ethernet "
592 "hardware address blacklisted. Falling back to random "
593 "address to avoid collisions.\n");
594 device_printf(sc->atse_dev, "Please re-program your flash.\n");
595 goto get_random;
596 }
597
598 if (sc->atse_eth_addr[0] == 0x00 && sc->atse_eth_addr[1] == 0x00 &&
599 sc->atse_eth_addr[2] == 0x00 && sc->atse_eth_addr[3] == 0x00 &&
600 sc->atse_eth_addr[4] == 0x00 && sc->atse_eth_addr[5] == 0x00) {
601 device_printf(sc->atse_dev, "All zero's Ethernet hardware "
602 "address blacklisted. Falling back to random address.\n");
603 device_printf(sc->atse_dev, "Please re-program your flash.\n");
604 goto get_random;
605 }
606
607 if (ETHER_IS_MULTICAST(sc->atse_eth_addr)) {
608 device_printf(sc->atse_dev, "Multicast Ethernet hardware "
609 "address blacklisted. Falling back to random address.\n");
610 device_printf(sc->atse_dev, "Please re-program your flash.\n");
611 goto get_random;
612 }
613
614 /*
615 * If we find an Altera prefixed address with a 0x0 ending
616 * adjust by device unit. If not and this is not the first
617 * Ethernet, go to random.
618 */
619 unit = device_get_unit(sc->atse_dev);
620 if (unit == 0x00) {
621 return (0);
622 }
623
624 if (unit > 0x0f) {
625 device_printf(sc->atse_dev, "We do not support Ethernet "
626 "addresses for more than 16 MACs. Falling back to "
627 "random hadware address.\n");
628 goto get_random;
629 }
630 if ((sc->atse_eth_addr[0] & ~0x2) != 0 ||
631 sc->atse_eth_addr[1] != 0x07 || sc->atse_eth_addr[2] != 0xed ||
632 (sc->atse_eth_addr[5] & 0x0f) != 0x0) {
633 device_printf(sc->atse_dev, "Ethernet address not meeting our "
634 "multi-MAC standards. Falling back to random hadware "
635 "address.\n");
636 goto get_random;
637 }
638 sc->atse_eth_addr[5] |= (unit & 0x0f);
639
640 return (0);
641
642 get_random:
643 /*
644 * Fall back to random code we also use on bridge(4).
645 */
646 getcredhostid(curthread->td_ucred, &hostid);
647 if (hostid == 0) {
648 arc4rand(sc->atse_eth_addr, ETHER_ADDR_LEN, 1);
649 sc->atse_eth_addr[0] &= ~1;/* clear multicast bit */
650 sc->atse_eth_addr[0] |= 2; /* set the LAA bit */
651 } else {
652 sc->atse_eth_addr[0] = 0x2;
653 sc->atse_eth_addr[1] = (hostid >> 24) & 0xff;
654 sc->atse_eth_addr[2] = (hostid >> 16) & 0xff;
655 sc->atse_eth_addr[3] = (hostid >> 8 ) & 0xff;
656 sc->atse_eth_addr[4] = hostid & 0xff;
657 sc->atse_eth_addr[5] = sc->atse_unit & 0xff;
658 }
659
660 return (0);
661 }
662
663 static int
664 atse_set_eth_address(struct atse_softc *sc, int n)
665 {
666 uint32_t v0, v1;
667
668 v0 = (sc->atse_eth_addr[3] << 24) | (sc->atse_eth_addr[2] << 16) |
669 (sc->atse_eth_addr[1] << 8) | sc->atse_eth_addr[0];
670 v1 = (sc->atse_eth_addr[5] << 8) | sc->atse_eth_addr[4];
671
672 if (n & ATSE_ETH_ADDR_DEF) {
673 CSR_WRITE_4(sc, BASE_CFG_MAC_0, v0);
674 CSR_WRITE_4(sc, BASE_CFG_MAC_1, v1);
675 }
676 if (n & ATSE_ETH_ADDR_SUPP1) {
677 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_0, v0);
678 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_1, v1);
679 }
680 if (n & ATSE_ETH_ADDR_SUPP2) {
681 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_0, v0);
682 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_1, v1);
683 }
684 if (n & ATSE_ETH_ADDR_SUPP3) {
685 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_2_0, v0);
686 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_2_1, v1);
687 }
688 if (n & ATSE_ETH_ADDR_SUPP4) {
689 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_3_0, v0);
690 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_3_1, v1);
691 }
692
693 return (0);
694 }
695
696 static int
697 atse_reset(struct atse_softc *sc)
698 {
699 uint32_t val4, mask;
700 uint16_t val;
701 int i;
702
703 /* 1. External PHY Initialization using MDIO. */
704 /*
705 * We select the right MDIO space in atse_attach() and let MII do
706 * anything else.
707 */
708
709 /* 2. PCS Configuration Register Initialization. */
710 /* a. Set auto negotiation link timer to 1.6ms for SGMII. */
711 PCS_WRITE_2(sc, PCS_EXT_LINK_TIMER_0, 0x0D40);
712 PCS_WRITE_2(sc, PCS_EXT_LINK_TIMER_1, 0x0003);
713
714 /* b. Configure SGMII. */
715 val = PCS_EXT_IF_MODE_SGMII_ENA|PCS_EXT_IF_MODE_USE_SGMII_AN;
716 PCS_WRITE_2(sc, PCS_EXT_IF_MODE, val);
717
718 /* c. Enable auto negotiation. */
719 /* Ignore Bits 6,8,13; should be set,set,unset. */
720 val = PCS_READ_2(sc, PCS_CONTROL);
721 val &= ~(PCS_CONTROL_ISOLATE|PCS_CONTROL_POWERDOWN);
722 val &= ~PCS_CONTROL_LOOPBACK; /* Make this a -link1 option? */
723 val |= PCS_CONTROL_AUTO_NEGOTIATION_ENABLE;
724 PCS_WRITE_2(sc, PCS_CONTROL, val);
725
726 /* d. PCS reset. */
727 val = PCS_READ_2(sc, PCS_CONTROL);
728 val |= PCS_CONTROL_RESET;
729 PCS_WRITE_2(sc, PCS_CONTROL, val);
730
731 /* Wait for reset bit to clear; i=100 is excessive. */
732 for (i = 0; i < 100; i++) {
733 val = PCS_READ_2(sc, PCS_CONTROL);
734 if ((val & PCS_CONTROL_RESET) == 0) {
735 break;
736 }
737 DELAY(10);
738 }
739
740 if ((val & PCS_CONTROL_RESET) != 0) {
741 device_printf(sc->atse_dev, "PCS reset timed out.\n");
742 return (ENXIO);
743 }
744
745 /* 3. MAC Configuration Register Initialization. */
746 /* a. Disable MAC transmit and receive datapath. */
747 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA;
748 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
749 val4 &= ~mask;
750 /* Samples in the manual do have the SW_RESET bit set here, why? */
751 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
752 /* Wait for bits to be cleared; i=100 is excessive. */
753 for (i = 0; i < 100; i++) {
754 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
755 if ((val4 & mask) == 0) {
756 break;
757 }
758 DELAY(10);
759 }
760 if ((val4 & mask) != 0) {
761 device_printf(sc->atse_dev, "Disabling MAC TX/RX timed out.\n");
762 return (ENXIO);
763 }
764 /* b. MAC FIFO configuration. */
765 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_EMPTY, FIFO_DEPTH_TX - 16);
766 CSR_WRITE_4(sc, BASE_CFG_TX_ALMOST_FULL, 3);
767 CSR_WRITE_4(sc, BASE_CFG_TX_ALMOST_EMPTY, 8);
768 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_EMPTY, FIFO_DEPTH_RX - 16);
769 CSR_WRITE_4(sc, BASE_CFG_RX_ALMOST_FULL, 8);
770 CSR_WRITE_4(sc, BASE_CFG_RX_ALMOST_EMPTY, 8);
771 #if 0
772 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_FULL, 16);
773 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_FULL, 16);
774 #else
775 /* For store-and-forward mode, set this threshold to 0. */
776 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_FULL, 0);
777 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_FULL, 0);
778 #endif
779 /* c. MAC address configuration. */
780 /* Also intialize supplementary addresses to our primary one. */
781 /* XXX-BZ FreeBSD really needs to grow and API for using these. */
782 atse_get_eth_address(sc);
783 atse_set_eth_address(sc, ATSE_ETH_ADDR_ALL);
784
785 /* d. MAC function configuration. */
786 CSR_WRITE_4(sc, BASE_CFG_FRM_LENGTH, 1518); /* Default. */
787 CSR_WRITE_4(sc, BASE_CFG_TX_IPG_LENGTH, 12);
788 CSR_WRITE_4(sc, BASE_CFG_PAUSE_QUANT, 0xFFFF);
789
790 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
791 /*
792 * If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3)
793 * and ENA_10 (bit 25) in command_config register to 0. If half duplex
794 * is reported in the PHY/PCS status register, set the HD_ENA (bit 10)
795 * to 1 in command_config register.
796 * BZ: We shoot for 1000 instead.
797 */
798 #if 0
799 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
800 #else
801 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
802 #endif
803 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
804 #if 0
805 /*
806 * We do not want to set this, otherwise, we could not even send
807 * random raw ethernet frames for various other research. By default
808 * FreeBSD will use the right ether source address.
809 */
810 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS;
811 #endif
812 val4 |= BASE_CFG_COMMAND_CONFIG_PAD_EN;
813 val4 &= ~BASE_CFG_COMMAND_CONFIG_CRC_FWD;
814 #if 0
815 val4 |= BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA;
816 #endif
817 #if 1
818 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC;
819 #endif
820 val &= ~BASE_CFG_COMMAND_CONFIG_LOOP_ENA; /* link0? */
821 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
822
823 /*
824 * Make sure we do not enable 32bit alignment; FreeBSD cannot
825 * cope with the additional padding (though we should!?).
826 * Also make sure we get the CRC appended.
827 */
828 val4 = CSR_READ_4(sc, TX_CMD_STAT);
829 val4 &= ~(TX_CMD_STAT_OMIT_CRC|TX_CMD_STAT_TX_SHIFT16);
830 CSR_WRITE_4(sc, TX_CMD_STAT, val4);
831
832 val4 = CSR_READ_4(sc, RX_CMD_STAT);
833 val4 &= ~RX_CMD_STAT_RX_SHIFT16;
834 val4 |= RX_CMD_STAT_RX_SHIFT16;
835 CSR_WRITE_4(sc, RX_CMD_STAT, val4);
836
837 /* e. Reset MAC. */
838 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
839 val4 |= BASE_CFG_COMMAND_CONFIG_SW_RESET;
840 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
841 /* Wait for bits to be cleared; i=100 is excessive. */
842 for (i = 0; i < 100; i++) {
843 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
844 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) == 0) {
845 break;
846 }
847 DELAY(10);
848 }
849 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) != 0) {
850 device_printf(sc->atse_dev, "MAC reset timed out.\n");
851 return (ENXIO);
852 }
853
854 /* f. Enable MAC transmit and receive datapath. */
855 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA;
856 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
857 val4 |= mask;
858 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
859 /* Wait for bits to be cleared; i=100 is excessive. */
860 for (i = 0; i < 100; i++) {
861 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
862 if ((val4 & mask) == mask) {
863 break;
864 }
865 DELAY(10);
866 }
867 if ((val4 & mask) != mask) {
868 device_printf(sc->atse_dev, "Enabling MAC TX/RX timed out.\n");
869 return (ENXIO);
870 }
871
872 return (0);
873 }
874
875 static void
876 atse_init_locked(struct atse_softc *sc)
877 {
878 struct ifnet *ifp;
879 struct mii_data *mii;
880 uint8_t *eaddr;
881
882 ATSE_LOCK_ASSERT(sc);
883 ifp = sc->atse_ifp;
884
885 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
886 return;
887 }
888
889 /*
890 * Must update the ether address if changed. Given we do not handle
891 * in atse_ioctl() but it's in the general framework, just always
892 * do it here before atse_reset().
893 */
894 eaddr = IF_LLADDR(sc->atse_ifp);
895 bcopy(eaddr, &sc->atse_eth_addr, ETHER_ADDR_LEN);
896
897 /* Make things frind to halt, cleanup, ... */
898 atse_stop_locked(sc);
899
900 atse_reset(sc);
901
902 /* ... and fire up the engine again. */
903 atse_rxfilter_locked(sc);
904
905 sc->atse_flags &= ATSE_FLAGS_LINK; /* Preserve. */
906
907 mii = device_get_softc(sc->atse_miibus);
908
909 sc->atse_flags &= ~ATSE_FLAGS_LINK;
910 mii_mediachg(mii);
911
912 ifp->if_drv_flags |= IFF_DRV_RUNNING;
913 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
914
915 callout_reset(&sc->atse_tick, hz, atse_tick, sc);
916 }
917
918 static void
919 atse_init(void *xsc)
920 {
921 struct atse_softc *sc;
922
923 /*
924 * XXXRW: There is some argument that we should immediately do RX
925 * processing after enabling interrupts, or one may not fire if there
926 * are buffered packets.
927 */
928 sc = (struct atse_softc *)xsc;
929 ATSE_LOCK(sc);
930 atse_init_locked(sc);
931 ATSE_UNLOCK(sc);
932 }
933
934 static int
935 atse_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
936 {
937 struct atse_softc *sc;
938 struct ifreq *ifr;
939 int error, mask;
940
941 error = 0;
942 sc = ifp->if_softc;
943 ifr = (struct ifreq *)data;
944
945 switch (command) {
946 case SIOCSIFFLAGS:
947 ATSE_LOCK(sc);
948 if (ifp->if_flags & IFF_UP) {
949 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
950 ((ifp->if_flags ^ sc->atse_if_flags) &
951 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
952 atse_rxfilter_locked(sc);
953 else
954 atse_init_locked(sc);
955 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
956 atse_stop_locked(sc);
957 sc->atse_if_flags = ifp->if_flags;
958 ATSE_UNLOCK(sc);
959 break;
960 case SIOCSIFCAP:
961 ATSE_LOCK(sc);
962 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
963 ATSE_UNLOCK(sc);
964 break;
965 case SIOCADDMULTI:
966 case SIOCDELMULTI:
967 ATSE_LOCK(sc);
968 atse_rxfilter_locked(sc);
969 ATSE_UNLOCK(sc);
970 break;
971 case SIOCGIFMEDIA:
972 case SIOCSIFMEDIA:
973 {
974 struct mii_data *mii;
975 struct ifreq *ifr;
976
977 mii = device_get_softc(sc->atse_miibus);
978 ifr = (struct ifreq *)data;
979 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
980 break;
981 }
982 default:
983 error = ether_ioctl(ifp, command, data);
984 break;
985 }
986
987 return (error);
988 }
989
990 static void
991 atse_tick(void *xsc)
992 {
993 struct atse_softc *sc;
994 struct mii_data *mii;
995 struct ifnet *ifp;
996
997 sc = (struct atse_softc *)xsc;
998 ATSE_LOCK_ASSERT(sc);
999 ifp = sc->atse_ifp;
1000
1001 mii = device_get_softc(sc->atse_miibus);
1002 mii_tick(mii);
1003 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) {
1004 atse_miibus_statchg(sc->atse_dev);
1005 }
1006
1007 callout_reset(&sc->atse_tick, hz, atse_tick, sc);
1008 }
1009
1010 /*
1011 * Set media options.
1012 */
1013 static int
1014 atse_ifmedia_upd(struct ifnet *ifp)
1015 {
1016 struct atse_softc *sc;
1017 struct mii_data *mii;
1018 struct mii_softc *miisc;
1019 int error;
1020
1021 sc = ifp->if_softc;
1022
1023 ATSE_LOCK(sc);
1024 mii = device_get_softc(sc->atse_miibus);
1025 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1026 PHY_RESET(miisc);
1027 }
1028 error = mii_mediachg(mii);
1029 ATSE_UNLOCK(sc);
1030
1031 return (error);
1032 }
1033
1034 /*
1035 * Report current media status.
1036 */
1037 static void
1038 atse_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1039 {
1040 struct atse_softc *sc;
1041 struct mii_data *mii;
1042
1043 sc = ifp->if_softc;
1044
1045 ATSE_LOCK(sc);
1046 mii = device_get_softc(sc->atse_miibus);
1047 mii_pollstat(mii);
1048 ifmr->ifm_active = mii->mii_media_active;
1049 ifmr->ifm_status = mii->mii_media_status;
1050 ATSE_UNLOCK(sc);
1051 }
1052
1053 static struct atse_mac_stats_regs {
1054 const char *name;
1055 const char *descr; /* Mostly copied from Altera datasheet. */
1056 } atse_mac_stats_regs[] = {
1057 [0x1a] =
1058 { "aFramesTransmittedOK",
1059 "The number of frames that are successfully transmitted including "
1060 "the pause frames." },
1061 { "aFramesReceivedOK",
1062 "The number of frames that are successfully received including the "
1063 "pause frames." },
1064 { "aFrameCheckSequenceErrors",
1065 "The number of receive frames with CRC error." },
1066 { "aAlignmentErrors",
1067 "The number of receive frames with alignment error." },
1068 { "aOctetsTransmittedOK",
1069 "The lower 32 bits of the number of data and padding octets that "
1070 "are successfully transmitted." },
1071 { "aOctetsReceivedOK",
1072 "The lower 32 bits of the number of data and padding octets that "
1073 " are successfully received." },
1074 { "aTxPAUSEMACCtrlFrames",
1075 "The number of pause frames transmitted." },
1076 { "aRxPAUSEMACCtrlFrames",
1077 "The number received pause frames received." },
1078 { "ifInErrors",
1079 "The number of errored frames received." },
1080 { "ifOutErrors",
1081 "The number of transmit frames with either a FIFO overflow error, "
1082 "a FIFO underflow error, or a error defined by the user "
1083 "application." },
1084 { "ifInUcastPkts",
1085 "The number of valid unicast frames received." },
1086 { "ifInMulticastPkts",
1087 "The number of valid multicast frames received. The count does "
1088 "not include pause frames." },
1089 { "ifInBroadcastPkts",
1090 "The number of valid broadcast frames received." },
1091 { "ifOutDiscards",
1092 "This statistics counter is not in use. The MAC function does not "
1093 "discard frames that are written to the FIFO buffer by the user "
1094 "application." },
1095 { "ifOutUcastPkts",
1096 "The number of valid unicast frames transmitted." },
1097 { "ifOutMulticastPkts",
1098 "The number of valid multicast frames transmitted, excluding pause "
1099 "frames." },
1100 { "ifOutBroadcastPkts",
1101 "The number of valid broadcast frames transmitted." },
1102 { "etherStatsDropEvents",
1103 "The number of frames that are dropped due to MAC internal errors "
1104 "when FIFO buffer overflow persists." },
1105 { "etherStatsOctets",
1106 "The lower 32 bits of the total number of octets received. This "
1107 "count includes both good and errored frames." },
1108 { "etherStatsPkts",
1109 "The total number of good and errored frames received." },
1110 { "etherStatsUndersizePkts",
1111 "The number of frames received with length less than 64 bytes. "
1112 "This count does not include errored frames." },
1113 { "etherStatsOversizePkts",
1114 "The number of frames received that are longer than the value "
1115 "configured in the frm_length register. This count does not "
1116 "include errored frames." },
1117 { "etherStatsPkts64Octets",
1118 "The number of 64-byte frames received. This count includes good "
1119 "and errored frames." },
1120 { "etherStatsPkts65to127Octets",
1121 "The number of received good and errored frames between the length "
1122 "of 65 and 127 bytes." },
1123 { "etherStatsPkts128to255Octets",
1124 "The number of received good and errored frames between the length "
1125 "of 128 and 255 bytes." },
1126 { "etherStatsPkts256to511Octets",
1127 "The number of received good and errored frames between the length "
1128 "of 256 and 511 bytes." },
1129 { "etherStatsPkts512to1023Octets",
1130 "The number of received good and errored frames between the length "
1131 "of 512 and 1023 bytes." },
1132 { "etherStatsPkts1024to1518Octets",
1133 "The number of received good and errored frames between the length "
1134 "of 1024 and 1518 bytes." },
1135 { "etherStatsPkts1519toXOctets",
1136 "The number of received good and errored frames between the length "
1137 "of 1519 and the maximum frame length configured in the frm_length "
1138 "register." },
1139 { "etherStatsJabbers",
1140 "Too long frames with CRC error." },
1141 { "etherStatsFragments",
1142 "Too short frames with CRC error." },
1143 /* 0x39 unused, 0x3a/b non-stats. */
1144 [0x3c] =
1145 /* Extended Statistics Counters */
1146 { "msb_aOctetsTransmittedOK",
1147 "Upper 32 bits of the number of data and padding octets that are "
1148 "successfully transmitted." },
1149 { "msb_aOctetsReceivedOK",
1150 "Upper 32 bits of the number of data and padding octets that are "
1151 "successfully received." },
1152 { "msb_etherStatsOctets",
1153 "Upper 32 bits of the total number of octets received. This count "
1154 "includes both good and errored frames." }
1155 };
1156
1157 static int
1158 sysctl_atse_mac_stats_proc(SYSCTL_HANDLER_ARGS)
1159 {
1160 struct atse_softc *sc;
1161 int error, offset, s;
1162
1163 sc = arg1;
1164 offset = arg2;
1165
1166 s = CSR_READ_4(sc, offset);
1167 error = sysctl_handle_int(oidp, &s, 0, req);
1168 if (error || !req->newptr) {
1169 return (error);
1170 }
1171
1172 return (0);
1173 }
1174
1175 static struct atse_rx_err_stats_regs {
1176 const char *name;
1177 const char *descr;
1178 } atse_rx_err_stats_regs[] = {
1179 #define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */
1180 #define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */
1181 #define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */
1182 #define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */
1183 #define ATSE_RX_ERR_4 4 /* ? */
1184 #define ATSE_RX_ERR_5 5 /* / */
1185
1186 { "rx_err_fifo_thres_eop",
1187 "FIFO threshold reached, reported on EOP." },
1188 { "rx_err_fifo_elen",
1189 "Frame or payload length not valid." },
1190 { "rx_err_fifo_crc32",
1191 "CRC-32 error." },
1192 { "rx_err_fifo_thres_trunc",
1193 "FIFO threshold reached, truncated frame" },
1194 { "rx_err_4",
1195 "?" },
1196 { "rx_err_5",
1197 "?" },
1198 };
1199
1200 static int
1201 sysctl_atse_rx_err_stats_proc(SYSCTL_HANDLER_ARGS)
1202 {
1203 struct atse_softc *sc;
1204 int error, offset, s;
1205
1206 sc = arg1;
1207 offset = arg2;
1208
1209 s = sc->atse_rx_err[offset];
1210 error = sysctl_handle_int(oidp, &s, 0, req);
1211 if (error || !req->newptr) {
1212 return (error);
1213 }
1214
1215 return (0);
1216 }
1217
1218 static void
1219 atse_sysctl_stats_attach(device_t dev)
1220 {
1221 struct sysctl_ctx_list *sctx;
1222 struct sysctl_oid *soid;
1223 struct atse_softc *sc;
1224 int i;
1225
1226 sc = device_get_softc(dev);
1227 sctx = device_get_sysctl_ctx(dev);
1228 soid = device_get_sysctl_tree(dev);
1229
1230 /* MAC statistics. */
1231 for (i = 0; i < nitems(atse_mac_stats_regs); i++) {
1232 if (atse_mac_stats_regs[i].name == NULL ||
1233 atse_mac_stats_regs[i].descr == NULL) {
1234 continue;
1235 }
1236
1237 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
1238 atse_mac_stats_regs[i].name,
1239 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
1240 sc, i, sysctl_atse_mac_stats_proc, "IU",
1241 atse_mac_stats_regs[i].descr);
1242 }
1243
1244 /* rx_err[]. */
1245 for (i = 0; i < ATSE_RX_ERR_MAX; i++) {
1246 if (atse_rx_err_stats_regs[i].name == NULL ||
1247 atse_rx_err_stats_regs[i].descr == NULL) {
1248 continue;
1249 }
1250
1251 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
1252 atse_rx_err_stats_regs[i].name,
1253 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
1254 sc, i, sysctl_atse_rx_err_stats_proc, "IU",
1255 atse_rx_err_stats_regs[i].descr);
1256 }
1257 }
1258
1259 /*
1260 * Generic device handling routines.
1261 */
1262 int
1263 atse_attach(device_t dev)
1264 {
1265 struct atse_softc *sc;
1266 struct ifnet *ifp;
1267 uint32_t caps;
1268 int error;
1269
1270 sc = device_get_softc(dev);
1271 sc->dev = dev;
1272
1273 /* Get xDMA controller */
1274 sc->xdma_tx = xdma_ofw_get(sc->dev, "tx");
1275 if (sc->xdma_tx == NULL) {
1276 device_printf(dev, "Can't find DMA controller.\n");
1277 return (ENXIO);
1278 }
1279
1280 /*
1281 * Only final (EOP) write can be less than "symbols per beat" value
1282 * so we have to defrag mbuf chain.
1283 * Chapter 15. On-Chip FIFO Memory Core.
1284 * Embedded Peripherals IP User Guide.
1285 */
1286 caps = XCHAN_CAP_NOSEG;
1287
1288 /* Alloc xDMA virtual channel. */
1289 sc->xchan_tx = xdma_channel_alloc(sc->xdma_tx, caps);
1290 if (sc->xchan_tx == NULL) {
1291 device_printf(dev, "Can't alloc virtual DMA channel.\n");
1292 return (ENXIO);
1293 }
1294
1295 /* Setup interrupt handler. */
1296 error = xdma_setup_intr(sc->xchan_tx, 0,
1297 atse_xdma_tx_intr, sc, &sc->ih_tx);
1298 if (error) {
1299 device_printf(sc->dev,
1300 "Can't setup xDMA interrupt handler.\n");
1301 return (ENXIO);
1302 }
1303
1304 xdma_prep_sg(sc->xchan_tx,
1305 TX_QUEUE_SIZE, /* xchan requests queue size */
1306 MCLBYTES, /* maxsegsize */
1307 8, /* maxnsegs */
1308 16, /* alignment */
1309 0, /* boundary */
1310 BUS_SPACE_MAXADDR_32BIT,
1311 BUS_SPACE_MAXADDR);
1312
1313 /* Get RX xDMA controller */
1314 sc->xdma_rx = xdma_ofw_get(sc->dev, "rx");
1315 if (sc->xdma_rx == NULL) {
1316 device_printf(dev, "Can't find DMA controller.\n");
1317 return (ENXIO);
1318 }
1319
1320 /* Alloc xDMA virtual channel. */
1321 sc->xchan_rx = xdma_channel_alloc(sc->xdma_rx, caps);
1322 if (sc->xchan_rx == NULL) {
1323 device_printf(dev, "Can't alloc virtual DMA channel.\n");
1324 return (ENXIO);
1325 }
1326
1327 /* Setup interrupt handler. */
1328 error = xdma_setup_intr(sc->xchan_rx, XDMA_INTR_NET,
1329 atse_xdma_rx_intr, sc, &sc->ih_rx);
1330 if (error) {
1331 device_printf(sc->dev,
1332 "Can't setup xDMA interrupt handler.\n");
1333 return (ENXIO);
1334 }
1335
1336 xdma_prep_sg(sc->xchan_rx,
1337 RX_QUEUE_SIZE, /* xchan requests queue size */
1338 MCLBYTES, /* maxsegsize */
1339 1, /* maxnsegs */
1340 16, /* alignment */
1341 0, /* boundary */
1342 BUS_SPACE_MAXADDR_32BIT,
1343 BUS_SPACE_MAXADDR);
1344
1345 mtx_init(&sc->br_mtx, "buf ring mtx", NULL, MTX_DEF);
1346 sc->br = buf_ring_alloc(BUFRING_SIZE, M_DEVBUF,
1347 M_NOWAIT, &sc->br_mtx);
1348 if (sc->br == NULL) {
1349 return (ENOMEM);
1350 }
1351
1352 atse_ethernet_option_bits_read(dev);
1353
1354 mtx_init(&sc->atse_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1355 MTX_DEF);
1356
1357 callout_init_mtx(&sc->atse_tick, &sc->atse_mtx, 0);
1358
1359 /*
1360 * We are only doing single-PHY with this driver currently. The
1361 * defaults would be right so that BASE_CFG_MDIO_ADDR0 points to the
1362 * 1st PHY address (0) apart from the fact that BMCR0 is always
1363 * the PCS mapping, so we always use BMCR1. See Table 5-1 0xA0-0xBF.
1364 */
1365 #if 0 /* Always PCS. */
1366 sc->atse_bmcr0 = MDIO_0_START;
1367 CSR_WRITE_4(sc, BASE_CFG_MDIO_ADDR0, 0x00);
1368 #endif
1369 /* Always use matching PHY for atse[0..]. */
1370 sc->atse_phy_addr = device_get_unit(dev);
1371 sc->atse_bmcr1 = MDIO_1_START;
1372 CSR_WRITE_4(sc, BASE_CFG_MDIO_ADDR1, sc->atse_phy_addr);
1373
1374 /* Reset the adapter. */
1375 atse_reset(sc);
1376
1377 /* Setup interface. */
1378 ifp = sc->atse_ifp = if_alloc(IFT_ETHER);
1379 if (ifp == NULL) {
1380 device_printf(dev, "if_alloc() failed\n");
1381 error = ENOSPC;
1382 goto err;
1383 }
1384 ifp->if_softc = sc;
1385 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1387 ifp->if_ioctl = atse_ioctl;
1388 ifp->if_transmit = atse_transmit;
1389 ifp->if_qflush = atse_qflush;
1390 ifp->if_init = atse_init;
1391 IFQ_SET_MAXLEN(&ifp->if_snd, ATSE_TX_LIST_CNT - 1);
1392 ifp->if_snd.ifq_drv_maxlen = ATSE_TX_LIST_CNT - 1;
1393 IFQ_SET_READY(&ifp->if_snd);
1394
1395 /* MII setup. */
1396 error = mii_attach(dev, &sc->atse_miibus, ifp, atse_ifmedia_upd,
1397 atse_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1398 if (error != 0) {
1399 device_printf(dev, "attaching PHY failed: %d\n", error);
1400 goto err;
1401 }
1402
1403 /* Call media-indepedent attach routine. */
1404 ether_ifattach(ifp, sc->atse_eth_addr);
1405
1406 /* Tell the upper layer(s) about vlan mtu support. */
1407 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1408 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1409 ifp->if_capenable = ifp->if_capabilities;
1410
1411 err:
1412 if (error != 0) {
1413 atse_detach(dev);
1414 }
1415
1416 if (error == 0) {
1417 atse_sysctl_stats_attach(dev);
1418 }
1419
1420 atse_rx_enqueue(sc, NUM_RX_MBUF);
1421 xdma_queue_submit(sc->xchan_rx);
1422
1423 return (error);
1424 }
1425
1426 static int
1427 atse_detach(device_t dev)
1428 {
1429 struct atse_softc *sc;
1430 struct ifnet *ifp;
1431
1432 sc = device_get_softc(dev);
1433 KASSERT(mtx_initialized(&sc->atse_mtx), ("%s: mutex not initialized",
1434 device_get_nameunit(dev)));
1435 ifp = sc->atse_ifp;
1436
1437 /* Only cleanup if attach succeeded. */
1438 if (device_is_attached(dev)) {
1439 ATSE_LOCK(sc);
1440 atse_stop_locked(sc);
1441 ATSE_UNLOCK(sc);
1442 callout_drain(&sc->atse_tick);
1443 ether_ifdetach(ifp);
1444 }
1445 if (sc->atse_miibus != NULL) {
1446 device_delete_child(dev, sc->atse_miibus);
1447 }
1448
1449 if (ifp != NULL) {
1450 if_free(ifp);
1451 }
1452
1453 mtx_destroy(&sc->atse_mtx);
1454
1455 xdma_channel_free(sc->xchan_tx);
1456 xdma_channel_free(sc->xchan_rx);
1457 xdma_put(sc->xdma_tx);
1458 xdma_put(sc->xdma_rx);
1459
1460 return (0);
1461 }
1462
1463 /* Shared between nexus and fdt implementation. */
1464 void
1465 atse_detach_resources(device_t dev)
1466 {
1467 struct atse_softc *sc;
1468
1469 sc = device_get_softc(dev);
1470
1471 if (sc->atse_mem_res != NULL) {
1472 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_mem_rid,
1473 sc->atse_mem_res);
1474 sc->atse_mem_res = NULL;
1475 }
1476 }
1477
1478 int
1479 atse_detach_dev(device_t dev)
1480 {
1481 int error;
1482
1483 error = atse_detach(dev);
1484 if (error) {
1485 /* We are basically in undefined state now. */
1486 device_printf(dev, "atse_detach() failed: %d\n", error);
1487 return (error);
1488 }
1489
1490 atse_detach_resources(dev);
1491
1492 return (0);
1493 }
1494
1495 int
1496 atse_miibus_readreg(device_t dev, int phy, int reg)
1497 {
1498 struct atse_softc *sc;
1499 int val;
1500
1501 sc = device_get_softc(dev);
1502
1503 /*
1504 * We currently do not support re-mapping of MDIO space on-the-fly
1505 * but de-facto hard-code the phy#.
1506 */
1507 if (phy != sc->atse_phy_addr) {
1508 return (0);
1509 }
1510
1511 val = PHY_READ_2(sc, reg);
1512
1513 return (val);
1514 }
1515
1516 int
1517 atse_miibus_writereg(device_t dev, int phy, int reg, int data)
1518 {
1519 struct atse_softc *sc;
1520
1521 sc = device_get_softc(dev);
1522
1523 /*
1524 * We currently do not support re-mapping of MDIO space on-the-fly
1525 * but de-facto hard-code the phy#.
1526 */
1527 if (phy != sc->atse_phy_addr) {
1528 return (0);
1529 }
1530
1531 PHY_WRITE_2(sc, reg, data);
1532 return (0);
1533 }
1534
1535 void
1536 atse_miibus_statchg(device_t dev)
1537 {
1538 struct atse_softc *sc;
1539 struct mii_data *mii;
1540 struct ifnet *ifp;
1541 uint32_t val4;
1542
1543 sc = device_get_softc(dev);
1544 ATSE_LOCK_ASSERT(sc);
1545
1546 mii = device_get_softc(sc->atse_miibus);
1547 ifp = sc->atse_ifp;
1548 if (mii == NULL || ifp == NULL ||
1549 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1550 return;
1551 }
1552
1553 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
1554
1555 /* Assume no link. */
1556 sc->atse_flags &= ~ATSE_FLAGS_LINK;
1557
1558 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1559 (IFM_ACTIVE | IFM_AVALID)) {
1560 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1561 case IFM_10_T:
1562 val4 |= BASE_CFG_COMMAND_CONFIG_ENA_10;
1563 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
1564 sc->atse_flags |= ATSE_FLAGS_LINK;
1565 break;
1566 case IFM_100_TX:
1567 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
1568 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
1569 sc->atse_flags |= ATSE_FLAGS_LINK;
1570 break;
1571 case IFM_1000_T:
1572 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10;
1573 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED;
1574 sc->atse_flags |= ATSE_FLAGS_LINK;
1575 break;
1576 default:
1577 break;
1578 }
1579 }
1580
1581 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) {
1582 /* Need to stop the MAC? */
1583 return;
1584 }
1585
1586 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
1587 val4 &= ~BASE_CFG_COMMAND_CONFIG_HD_ENA;
1588 } else {
1589 val4 |= BASE_CFG_COMMAND_CONFIG_HD_ENA;
1590 }
1591
1592 /* flow control? */
1593
1594 /* Make sure the MAC is activated. */
1595 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ENA;
1596 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ENA;
1597
1598 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4);
1599 }
1600
1601 MODULE_DEPEND(atse, ether, 1, 1, 1);
1602 MODULE_DEPEND(atse, miibus, 1, 1, 1);
Cache object: 92f1299babe306cc4ad71a201258ffba
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