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sys/dev/altera/atse/if_atsereg.h
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1 /*- 2 * Copyright (c) 2012 Bjoern A. Zeeb 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 7 * ("MRC2"), as part of the DARPA MRC research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: releng/11.0/sys/dev/altera/atse/if_atsereg.h 256752 2013-10-18 20:44:19Z brooks $ 31 */ 32 33 #ifndef _DEV_IF_ATSEREG_H 34 #define _DEV_IF_ATSEREG_H 35 36 #define ATSE_VENDOR 0x6af7 37 #define ATSE_DEVICE 0x00bd 38 39 /* See hints file/fdt for ctrl port and Avalon FIFO addresses. */ 40 41 /* Section 3. Parameter Settings. */ 42 /* 43 * This is a lot of options that affect the way things are synthesized. 44 * We cannot really make them all hints and most of them might be stale. 45 */ 46 47 /* 3-1 Core Configuration */ 48 #if 0 49 static const char *atse_core_core_variation[] = { 50 [0] = "10/100/1000 Mbps Ethernet MAC only", 51 [1] = "10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS", 52 [2] = "1000BASE-X/SGMII PCS only", 53 [3] = "1000 Mbps Small MAC", 54 [4] = "10/100 Mbps Small MAC", 55 NULL 56 }; 57 static const char *atse_core_interface[] = { 58 [0] = "MII", /* Core variation 4. */ 59 [1] = "GMII", /* Core variation 3. */ 60 [2] = "RGMII", /* Core variation 0,1,3. */ 61 [3] = "MII/GMII", /* Core variation 0,1. */ 62 NULL 63 }; 64 #endif 65 #define CORE_CORE_VARIATION 1 /* atse_core_core_variation[] */ 66 #define CORE_INTERFACE 3 /* atse_core_interface[] */ 67 #define CORE_USE_INTERNAL_FIFO 1 68 #define CORE_NUMBER_OF_PORTS 1 /* Internal FIFO count. */ 69 #define CORE_USE_TRANSCEIVER_BLOCK 1 /* SGMII PCS transceiver: 70 * LVDS I/O. */ 71 72 /* 3-2 MAC Options. */ 73 /* Ethernet MAC Options. */ 74 #define MAC_ENABLE_10_100_HDX_SUPPORT 0 75 #define MAC_ENABLE_RG_G_MII_LOOPBACK 0 76 #define MAC_ENABLE_SUPL_MAC_UCAST_ADDR 0 /* Supplementary MAC unicast. */ 77 #define MAC_INCLUDE_STATISTICS_COUNTERS 0 78 #define MAC_STATISTICS_COUNTERS_64BIT 0 79 #define MAC_INCLUDE_MC_HASHTABLE 0 /* Multicast. */ 80 #define MAC_ALIGN_PKTHDR_32BIT 1 81 #define MAC_ENABLE_FDX_FLOW_CTRL 0 82 #define MAC_ENABLE_VLAN_DETECTION 0 /* VLAN and stacked VLANs. */ 83 #define MAC_ENABLE_MAGIC_PKT_DETECTION 0 84 /* MDIO Module. */ 85 #define MAC_MDIO_INCLUDE_MDIO_MODULE 1 86 #define MAC_MDIO_HOST_CLOCK_DIVISOR 40 /* Not just On/Off. */ 87 88 /* 3-4 FIFO Options. */ 89 /* Width and Memory Type. */ 90 #if 0 91 static char *fifo_memory_block[] = { 92 [0] = "M4K", 93 [1] = "M9K", 94 [2] = "M144K", 95 [3] = "MRAM", 96 [4] = "AUTO", 97 NULL 98 }; 99 #endif 100 #define FIFO_MEMORY_BLOCK 4 101 #define FIFO_WITDH 32 /* Other: 8 bits. */ 102 /* Depth. */ 103 #define FIFO_DEPTH_TX 2048 /* 64 .. 64k, 2048x32bits. */ 104 #define FIFO_DEPTH_RX 2048 /* 64 .. 64k, 2048x32bits. */ 105 106 #define ATSE_TX_LIST_CNT 5 /* Certainly not bufferbloat. */ 107 108 /* 3-4 PCS/Transceiver Options */ 109 /* PCS Options. */ 110 #define PCS_TXRX_PHY_ID 0x00000000 /* 32 bits */ 111 #define PCS_TXRX_ENABLE_SGMII_BRIDGE 0 112 /* Transceiver Options. */ 113 #define PCS_TXRX_EXP_POWER_DOWN_SIGNAL 0 /* Export power down signal. */ 114 #define PCS_TXRX_ENABLE_DYNAMIC_RECONF 0 /* Dynamic trans. reconfig. */ 115 #define PCS_TXRX_STARTING_CHANNEL 0 /* 0..284. */ 116 117 118 /* -------------------------------------------------------------------------- */ 119 120 /* XXX more values based on the bitmaps provided. Cleanup. */ 121 /* See regs above. */ 122 #define AVALON_FIFO_TX_BLOCK_DIAGRAM 0 123 #define AVALON_FIFO_TX_BLOCK_DIAGRAM_SHOW_SIGANLS 0 124 #define AVALON_FIFO_TX_PARAM_SINGLE_RESET_MODE 0 125 #define AVALON_FIFO_TX_BASIC_OPTS_DEPTH 16 126 #define AVALON_FIFO_TX_BASIC_OPTS_ALLOW_BACKPRESSURE 1 127 #define AVALON_FIFO_TX_BASIC_OPTS_CLOCK_SETTING "Single Clock Mode" 128 #define AVALON_FIFO_TX_BASIC_OPTS_FIFO_IMPL "Construct FIFO from embedded memory blocks" 129 #define AVALON_FIFO_TX_STATUS_PORT_CREATE_STATUS_INT_FOR_INPUT 1 130 #define AVALON_FIFO_TX_STATUS_PORT_CREATE_STATUS_INT_FOR_OUTPUT 0 131 #define AVALON_FIFO_TX_STATUS_PORT_ENABLE_IRQ_FOR_STATUS_PORT 1 132 #define AVALON_FIFO_TX_INPUT_TYPE "AVALONMM_WRITE" 133 #define AVALON_FIFO_TX_OUTPUT_TYPE "AVALONST_SOURCE" 134 #define AVALON_FIFO_TX_AVALON_MM_PORT_SETTINGS_DATA_WIDTH "" 135 #define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_BITS_PER_SYMBOL 8 136 #define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_SYM_PER_BEAT 4 137 #define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_ERROR_WIDTH 1 138 #define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_CHANNEL_WIDTH 0 139 #define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_ENABLE_PACKET_DATA 1 140 141 #define AVALON_FIFO_RX_BLOCK_DIAGRAM 0 142 #define AVALON_FIFO_RX_BLOCK_DIAGRAM_SHOW_SIGNALS 0 143 #define AVALON_FIFO_RX_PARAM_SINGLE_RESET_MODE 0 144 #define AVALON_FIFO_RX_BASIC_OPTS_DEPTH 16 145 #define AVALON_FIFO_RX_BASIC_OPTS_ALLOW_BACKPRESSURE 1 146 #define AVALON_FIFO_RX_BASIC_OPTS_CLOCK_SETTING "Single Clock Mode" 147 #define AVALON_FIFO_RX_BASIC_OPTS_FIFO_IMPL "Construct FIFO from embedded memory blocks" 148 #define AVALON_FIFO_RX_STATUS_PORT_CREATE_STATUS_INT_FOR_INPUT 1 149 #define AVALON_FIFO_RX_STATUS_PORT_CREATE_STATUS_INT_FOR_OUTPUT 0 150 #define AVALON_FIFO_RX_STATUS_PORT_ENABLE_IRQ_FOR_STATUS_PORT 1 151 #define AVALON_FIFO_RX_INPUT_TYPE "AVALONST_SINK" 152 #define AVALON_FIFO_RX_OUTPUT_TYPE "AVALONMM_READ" 153 #define AVALON_FIFO_RX_AVALON_MM_PORT_SETTINGS_DATA_WIDTH "" 154 #define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_BITS_PER_SYMBOL 8 155 #define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_SYM_PER_BEAT 4 156 #define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_ERROR_WIDTH 6 157 #define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_CHANNEL_WIDTH 0 158 #define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_ENABLE_PACKET_DATA 1 159 160 /* -------------------------------------------------------------------------- */ 161 162 /* 5. Configuration Register Space. */ 163 164 /* 5-1, MAC Configuration Register Space; Dword offsets. */ 165 /* 0x00 - 0x17, Base Configuration. */ 166 #define BASE_CONFIG_REV 0x00 /* ro, IP Core ver. */ 167 #define BASE_CFG_REV_VER_MASK 0x0000FFFF 168 #define BASE_CFG_REV_CUST_VERSION__MASK 0xFFFF0000 169 170 #define BASE_CFG_SCRATCH 0x01 /* rw, 0 */ 171 172 #define BASE_CFG_COMMAND_CONFIG 0x02 /* rw, 0 */ 173 #define BASE_CFG_COMMAND_CONFIG_TX_ENA (1<<0) /* rw */ 174 #define BASE_CFG_COMMAND_CONFIG_RX_ENA (1<<1) /* rw */ 175 #define BASE_CFG_COMMAND_CONFIG_XON_GEN (1<<2) /* rw */ 176 #define BASE_CFG_COMMAND_CONFIG_ETH_SPEED (1<<3) /* rw */ 177 #define BASE_CFG_COMMAND_CONFIG_PROMIS_EN (1<<4) /* rw */ 178 #define BASE_CFG_COMMAND_CONFIG_PAD_EN (1<<5) /* rw */ 179 #define BASE_CFG_COMMAND_CONFIG_CRC_FWD (1<<6) /* rw */ 180 #define BASE_CFG_COMMAND_CONFIG_PAUSE_FWD (1<<7) /* rw */ 181 #define BASE_CFG_COMMAND_CONFIG_PAUSE_IGNORE (1<<8) /* rw */ 182 #define BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS (1<<9) /* rw */ 183 #define BASE_CFG_COMMAND_CONFIG_HD_ENA (1<<10) /* rw */ 184 #define BASE_CFG_COMMAND_CONFIG_EXCESS_COL (1<<11) /* ro */ 185 #define BASE_CFG_COMMAND_CONFIG_LATE_COL (1<<12) /* ro */ 186 #define BASE_CFG_COMMAND_CONFIG_SW_RESET (1<<13) /* rw */ 187 #define BASE_CFG_COMMAND_CONFIG_MHASH_SEL (1<<14) /* rw */ 188 #define BASE_CFG_COMMAND_CONFIG_LOOP_ENA (1<<15) /* rw */ 189 #define BASE_CFG_COMMAND_CONFIG_TX_ADDR_SEL (1<<16|1<<17|1<<18) /* rw */ 190 #define BASE_CFG_COMMAND_CONFIG_MAGIC_ENA (1<<19) /* rw */ 191 #define BASE_CFG_COMMAND_CONFIG_SLEEP (1<<20) /* rw */ 192 #define BASE_CFG_COMMAND_CONFIG_WAKEUP (1<<21) /* ro */ 193 #define BASE_CFG_COMMAND_CONFIG_XOFF_GEN (1<<22) /* rw */ 194 #define BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA (1<<23) /* rw */ 195 #define BASE_CFG_COMMAND_CONFIG_NO_LGTH_CHECK (1<<24) /* rw */ 196 #define BASE_CFG_COMMAND_CONFIG_ENA_10 (1<<25) /* rw */ 197 #define BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC (1<<26) /* rw */ 198 #define BASE_CFG_COMMAND_CONFIG_DISABLE_READ_TIMEOUT (1<<27) /* rw */ 199 /* 28-30 Reserved. */ /* - */ 200 #define BASE_CFG_COMMAND_CONFIG_CNT_RESET (1<<31) /* rw */ 201 202 #define BASE_CFG_MAC_0 0x03 /* rw, 0 */ 203 #define BASE_CFG_MAC_1 0x04 /* rw, 0 */ 204 #define BASE_CFG_FRM_LENGTH 0x05 /* rw/ro, 1518 */ 205 #define BASE_CFG_PAUSE_QUANT 0x06 /* rw, 0 */ 206 #define BASE_CFG_RX_SECTION_EMPTY 0x07 /* rw/ro, 0 */ 207 #define BASE_CFG_RX_SECTION_FULL 0x08 /* rw/ro, 0 */ 208 #define BASE_CFG_TX_SECTION_EMPTY 0x09 /* rw/ro, 0 */ 209 #define BASE_CFG_TX_SECTION_FULL 0x0A /* rw/ro, 0 */ 210 #define BASE_CFG_RX_ALMOST_EMPTY 0x0B /* rw/ro, 0 */ 211 #define BASE_CFG_RX_ALMOST_FULL 0x0C /* rw/ro, 0 */ 212 #define BASE_CFG_TX_ALMOST_EMPTY 0x0D /* rw/ro, 0 */ 213 #define BASE_CFG_TX_ALMOST_FULL 0x0E /* rw/ro, 0 */ 214 #define BASE_CFG_MDIO_ADDR0 0x0F /* rw, 0 */ 215 #define BASE_CFG_MDIO_ADDR1 0x10 /* rw, 1 */ 216 #define BASE_CFG_HOLDOFF_QUANT 0x11 /* rw, 0xFFFF */ 217 /* 0x12-0x16 Reserved. */ /* -, 0 */ 218 #define BASE_CFG_TX_IPG_LENGTH 0x17 /* rw, 0 */ 219 220 /* 0x18 - 0x38, Statistics Counters. */ 221 #define STATS_A_MAC_ID_0 0x18 /* ro */ 222 #define STATS_A_MAC_ID_1 0x19 /* ro */ 223 #define STATS_A_FRAMES_TX_OK 0x1A /* ro */ 224 #define STATS_A_FRAMES_RX_OK 0x1B /* ro */ 225 #define STATS_A_FCS_ERRORS 0x1C /* ro */ 226 #define STATS_A_ALIGNMENT_ERRORS 0x1D /* ro */ 227 #define STATS_A_OCTETS_TX_OK 0x1E /* ro */ 228 #define STATS_A_OCTETS_RX_OK 0x1F /* ro */ 229 #define STATS_A_TX_PAUSE_MAX_CTRL_FRAME 0x20 /* ro */ 230 #define STATS_A_RX_PAUSE_MAX_CTRL_FRAME 0x21 /* ro */ 231 #define STATS_IF_IN_ERRORS 0x22 /* ro */ 232 #define STATS_IF_OUT_ERRORS 0x23 /* ro */ 233 #define STATS_IF_IN_UCAST_PKTS 0x24 /* ro */ 234 #define STATS_IF_IN_MULTICAST_PKTS 0x25 /* ro */ 235 #define STATS_IF_IN_BROADCAST_PKTS 0x26 /* ro */ 236 #define STATS_IF_OUT_DISCARDS 0x27 /* ro */ 237 #define STATS_IF_OUT_UCAST_PKTS 0x28 /* ro */ 238 #define STATS_IF_OUT_MULTICAST_PKTS 0x29 /* ro */ 239 #define STATS_IF_OUT_BROADCAST_PKTS 0x2A /* ro */ 240 #define STATS_ETHER_STATS_DROP_EVENT 0x2B /* ro */ 241 #define STATS_ETHER_STATS_OCTETS 0x2C /* ro */ 242 #define STATS_ETHER_STATS_PKTS 0x2D /* ro */ 243 #define STATS_ETHER_STATS_USIZE_PKTS 0x2E /* ro */ 244 #define STATS_ETHER_STATS_OSIZE_PKTS 0x2F /* ro */ 245 #define STATS_ETHER_STATS_PKTS_64_OCTETS 0x30 /* ro */ 246 #define STATS_ETHER_STATS_PKTS_65_TO_127_OCTETS 0x31 /* ro */ 247 #define STATS_ETHER_STATS_PKTS_128_TO_255_OCTETS 0x32 /* ro */ 248 #define STATS_ETHER_STATS_PKTS_256_TO_511_OCTETS 0x33 /* ro */ 249 #define STATS_ETHER_STATS_PKTS_512_TO_1023_OCTETS 0x34 /* ro */ 250 #define STATS_ETHER_STATS_PKTS_1024_TO_1518_OCTETS 0x35 /* ro */ 251 #define STATS_ETHER_STATS_PKTS_1519_TO_X_OCTETS 0x36 /* ro */ 252 #define STATS_ETHER_STATS_JABBERS 0x37 /* ro */ 253 #define STATS_ETHER_STATS_FRAGMENTS 0x38 /* ro */ 254 /* 0x39, Reserved. */ /* - */ 255 256 /* 0x3A, Transmit Command. */ 257 #define TX_CMD_STAT 0x3A /* rw */ 258 #define TX_CMD_STAT_OMIT_CRC (1<<17) 259 #define TX_CMD_STAT_TX_SHIFT16 (1<<18) 260 261 /* 0x3B, Receive Command. */ 262 #define RX_CMD_STAT 0x3B /* rw */ 263 #define RX_CMD_STAT_RX_SHIFT16 (1<<25) 264 265 /* 0x3C - 0x3E, Extended Statistics Counters. */ 266 #define ESTATS_MSB_A_OCTETS_TX_OK 0x3C /* ro */ 267 #define ESTATS_MSB_A_OCTETS_RX_OK 0x3D /* ro */ 268 #define ESTATS_MSB_ETHER_STATS_OCTETS 0x3E /* ro */ 269 270 /* 0x3F, Reserved. */ 271 272 /* 0x40 - 0x7F, Multicast Hash Table. */ 273 #define MHASH_START 0x40 274 #define MHASH_LEN 0x3F 275 276 /* 0x80 - 0x9F, MDIO Space 0 or PCS Function Configuration. */ 277 #define MDIO_0_START 0x80 278 279 /* The following are offsets to the first PCS register at 0x80. */ 280 /* See sys/dev/mii/mii.h. */ 281 #define PCS_CONTROL 0x00 /* rw */ 282 /* Bits 0:4, Reserved. */ /* - */ 283 #define PCS_CONTROL_UNIDIRECTIONAL_ENABLE (1<<5) /* rw */ 284 #define PCS_CONTROL_SPEED_SELECTION (1<<6|1<<13) /* ro */ 285 #define PCS_CONTROL_COLLISION_TEST (1<<7) /* ro */ 286 #define PCS_CONTROL_DUPLEX_MODE (1<<8) /* ro */ 287 #define PCS_CONTROL_RESTART_AUTO_NEGOTIATION (1<<9) /* rw */ 288 #define PCS_CONTROL_ISOLATE (1<<10) /* rw */ 289 #define PCS_CONTROL_POWERDOWN (1<<11) /* rw */ 290 #define PCS_CONTROL_AUTO_NEGOTIATION_ENABLE (1<<12) /* rw */ 291 /* See bit 6 above. */ /* ro */ 292 #define PCS_CONTROL_LOOPBACK (1<<14) /* rw */ 293 #define PCS_CONTROL_RESET (1<<15) /* rw */ 294 295 #define PCS_STATUS 0x01 /* ro */ 296 #define PCS_STATUS_EXTENDED_CAPABILITY (1<<0) /* ro */ 297 #define PCS_STATUS_JABBER_DETECT (1<<1) /* -, 0 */ 298 #define PCS_STATUS_LINK_STATUS (1<<2) /* ro */ 299 #define PCS_STATUS_AUTO_NEGOTIATION_ABILITY (1<<3) /* ro */ 300 #define PCS_STATUS_REMOTE_FAULT (1<<4) /* -, 0 */ 301 #define PCS_STATUS_AUTO_NEGOTIATION_COMPLETE (1<<5) /* ro */ 302 #define PCS_STATUS_MF_PREAMBLE_SUPPRESSION (1<<6) /* -, 0 */ 303 #define PCS_STATUS_UNIDIRECTIONAL_ABILITY (1<<7) /* ro */ 304 #define PCS_STATUS_EXTENDED_STATUS (1<<8) /* -, 0 */ 305 #define PCS_STATUS_100BASET2_HALF_DUPLEX (1<<9) /* ro */ 306 #define PCS_STATUS_100BASET2_FULL_DUPLEX (1<<10) /* ro */ 307 #define PCS_STATUS_10MBPS_HALF_DUPLEX (1<<11) /* ro */ 308 #define PCS_STATUS_10MBPS_FULL_DUPLEX (1<<12) /* ro */ 309 #define PCS_STATUS_100BASE_X_HALF_DUPLEX (1<<13) /* ro */ 310 #define PCS_STATUS_100BASE_X_FULL_DUPLEX (1<<14) /* ro */ 311 #define PCS_STATUS_100BASE_T4 (1<<15) /* ro */ 312 313 #define PCS_PHY_IDENTIFIER_0 0x02 /* ro */ 314 #define PCS_PHY_IDENTIFIER_1 0x03 /* ro */ 315 316 #define PCS_DEV_ABILITY 0x04 /* rw */ 317 /* 1000BASE-X */ 318 /* Bits 0:4, Reserved. */ /* - */ 319 #define PCS_DEV_ABILITY_1000BASE_X_FD (1<<5) /* rw */ 320 #define PCS_DEV_ABILITY_1000BASE_X_HD (1<<6) /* rw */ 321 #define PCS_DEV_ABILITY_1000BASE_X_PS1 (1<<7) /* rw */ 322 #define PCS_DEV_ABILITY_1000BASE_X_PS2 (1<<8) /* rw */ 323 /* Bits 9:11, Reserved. */ /* - */ 324 #define PCS_DEV_ABILITY_1000BASE_X_RF1 (1<<12) /* rw */ 325 #define PCS_DEV_ABILITY_1000BASE_X_RF2 (1<<13) /* rw */ 326 #define PCS_DEV_ABILITY_1000BASE_X_ACK (1<<14) /* rw */ 327 #define PCS_DEV_ABILITY_1000BASE_X_NP (1<<15) /* rw */ 328 329 #define PCS_PARTNER_ABILITY 0x05 /* ro */ 330 /* 1000BASE-X */ 331 /* Bits 0:4, Reserved. */ /* - */ 332 #define PCS_PARTNER_ABILITY_1000BASE_X_FD (1<<5) /* ro */ 333 #define PCS_PARTNER_ABILITY_1000BASE_X_HD (1<<6) /* ro */ 334 #define PCS_PARTNER_ABILITY_1000BASE_X_PS1 (1<<7) /* ro */ 335 #define PCS_PARTNER_ABILITY_1000BASE_X_PS2 (1<<8) /* ro */ 336 /* Bits 9:11, Reserved. */ /* - */ 337 #define PCS_PARTNER_ABILITY_1000BASE_X_RF1 (1<<12) /* ro */ 338 #define PCS_PARTNER_ABILITY_1000BASE_X_RF2 (1<<13) /* ro */ 339 #define PCS_PARTNER_ABILITY_1000BASE_X_ACK (1<<14) /* ro */ 340 #define PCS_PARTNER_ABILITY_1000BASE_X_NP (1<<15) /* ro */ 341 /* SGMII */ 342 /* Bits 0:9, Reserved. */ /* - */ 343 #define PCS_PARTNER_ABILITY_SGMII_COPPER_SPEED0 (1<<10) /* ro */ 344 #define PCS_PARTNER_ABILITY_SGMII_COPPER_SPEED1 (1<<11) /* ro */ 345 #define PCS_PARTNER_ABILITY_SGMII_COPPER_DUPLEX_STATUS (1<<12) /* ro */ 346 /* Bit 13, Reserved. */ /* - */ 347 #define PCS_PARTNER_ABILITY_SGMII_ACK (1<<14) /* ro */ 348 #define PCS_PARTNER_ABILITY_SGMII_COPPER_LINK_STATUS (1<<15) /* ro */ 349 350 #define PCS_AN_EXPANSION 0x06 /* ro */ 351 #define PCS_AN_EXPANSION_LINK_PARTNER_AUTO_NEGOTIATION_ABLE (1<<0) /* ro */ 352 #define PCS_AN_EXPANSION_PAGE_RECEIVE (1<<1) /* ro */ 353 #define PCS_AN_EXPANSION_NEXT_PAGE_ABLE (1<<2) /* -, 0 */ 354 /* Bits 3:15, Reserved. */ /* - */ 355 356 #define PCS_DEVICE_NEXT_PAGE 0x07 /* ro */ 357 #define PCS_PARTNER_NEXT_PAGE 0x08 /* ro */ 358 #define PCS_MASTER_SLAVE_CNTL 0x09 /* ro */ 359 #define PCS_MASTER_SLAVE_STAT 0x0A /* ro */ 360 /* 0x0B - 0x0E, Reserved */ /* - */ 361 #define PCS_EXTENDED_STATUS 0x0F /* ro */ 362 /* Specific Extended Registers. */ 363 #define PCS_EXT_SCRATCH 0x10 /* rw */ 364 #define PCS_EXT_REV 0x11 /* ro */ 365 #define PCS_EXT_LINK_TIMER_0 0x12 /* rw */ 366 #define PCS_EXT_LINK_TIMER_1 0x13 /* rw */ 367 #define PCS_EXT_IF_MODE 0x14 /* rw */ 368 #define PCS_EXT_IF_MODE_SGMII_ENA (1<<0) /* rw */ 369 #define PCS_EXT_IF_MODE_USE_SGMII_AN (1<<1) /* rw */ 370 #define PCS_EXT_IF_MODE_SGMII_SPEED1 (1<<2) /* rw */ 371 #define PCS_EXT_IF_MODE_SGMII_SPEED0 (1<<3) /* rw */ 372 #define PCS_EXT_IF_MODE_SGMII_DUPLEX (1<<4) /* rw */ 373 /* Bits 5:15, Reserved. */ /* - */ 374 375 #define PCS_EXT_DISABLE_READ_TIMEOUT 0x15 /* rw */ 376 #define PCS_EXT_READ_TIMEOUT 0x16 /* r0 */ 377 /* 0x17-0x1F, Reserved. */ 378 379 /* 0xA0 - 0xBF, MDIO Space 1. */ 380 #define MDIO_1_START 0xA0 381 #define ATSE_BMCR MDIO_1_START 382 383 /* 0xC0 - 0xC7, Supplementary Address. */ 384 #define SUPPL_ADDR_SMAC_0_0 0xC0 /* rw */ 385 #define SUPPL_ADDR_SMAC_0_1 0xC1 /* rw */ 386 #define SUPPL_ADDR_SMAC_1_0 0xC2 /* rw */ 387 #define SUPPL_ADDR_SMAC_1_1 0xC3 /* rw */ 388 #define SUPPL_ADDR_SMAC_2_0 0xC4 /* rw */ 389 #define SUPPL_ADDR_SMAC_2_1 0xC5 /* rw */ 390 #define SUPPL_ADDR_SMAC_3_0 0xC6 /* rw */ 391 #define SUPPL_ADDR_SMAC_3_1 0xC7 /* rw */ 392 393 /* 0xC8 - 0xCF, Reserved; set to zero, ignore on read. */ 394 /* 0xD7 - 0xFF, Reserved; set to zero, ignore on read. */ 395 396 397 /* -------------------------------------------------------------------------- */ 398 399 /* DE4 Intel Strata Flash Ethernet Option Bits area. */ 400 /* XXX-BZ this is something a loader will have to handle for us. */ 401 #define ALTERA_ETHERNET_OPTION_BITS_OFF 0x00008000 402 #define ALTERA_ETHERNET_OPTION_BITS_LEN 0x00007fff 403 404 /* -------------------------------------------------------------------------- */ 405 406 struct atse_softc { 407 struct ifnet *atse_ifp; 408 struct mbuf *atse_rx_m; 409 struct mbuf *atse_tx_m; 410 uint8_t *atse_tx_buf; 411 struct resource *atse_mem_res; 412 struct resource *atse_rx_irq_res; 413 struct resource *atse_rx_mem_res; 414 struct resource *atse_rxc_mem_res; 415 struct resource *atse_tx_irq_res; 416 struct resource *atse_tx_mem_res; 417 struct resource *atse_txc_mem_res; 418 device_t atse_miibus; 419 device_t atse_dev; 420 int atse_unit; 421 int atse_mem_rid; 422 int atse_rx_irq_rid; 423 int atse_rx_mem_rid; 424 int atse_rxc_mem_rid; 425 int atse_tx_irq_rid; 426 int atse_tx_mem_rid; 427 int atse_txc_mem_rid; 428 int atse_phy_addr; 429 int atse_if_flags; 430 int atse_rx_irq; 431 int atse_tx_irq; 432 u_long atse_rx_maddr; 433 u_long atse_rx_msize; 434 u_long atse_tx_maddr; 435 u_long atse_tx_msize; 436 u_long atse_rxc_maddr; 437 u_long atse_rxc_msize; 438 u_long atse_txc_maddr; 439 u_long atse_txc_msize; 440 void *atse_rx_intrhand; 441 void *atse_tx_intrhand; 442 bus_addr_t atse_bmcr0; 443 bus_addr_t atse_bmcr1; 444 uint32_t atse_flags; 445 #define ATSE_FLAGS_LINK 0x00000001 446 #define ATSE_FLAGS_ERROR 0x00000002 447 #define ATSE_FLAGS_SOP_SEEN 0x00000004 448 uint8_t atse_eth_addr[ETHER_ADDR_LEN]; 449 #define ATSE_ETH_ADDR_DEF 0x01 450 #define ATSE_ETH_ADDR_SUPP1 0x02 451 #define ATSE_ETH_ADDR_SUPP2 0x04 452 #define ATSE_ETH_ADDR_SUPP3 0x08 453 #define ATSE_ETH_ADDR_SUPP4 0x10 454 #define ATSE_ETH_ADDR_ALL 0x1f 455 uint16_t atse_watchdog_timer; 456 uint16_t atse_tx_m_offset; 457 uint16_t atse_tx_buf_len; 458 uint16_t atse_rx_buf_len; 459 int16_t atse_rx_cycles; /* POLLING */ 460 #define RX_CYCLES_IN_INTR 5 461 uint32_t atse_rx_err[6]; 462 #define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */ 463 #define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */ 464 #define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */ 465 #define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */ 466 #define ATSE_RX_ERR_4 4 /* ? */ 467 #define ATSE_RX_ERR_5 5 /* / */ 468 #define ATSE_RX_ERR_MAX 6 469 struct callout atse_tick; 470 struct mtx atse_mtx; 471 }; 472 473 474 int atse_attach(device_t); 475 int atse_detach_dev(device_t); 476 void atse_detach_resources(device_t); 477 478 int atse_miibus_readreg(device_t, int, int); 479 int atse_miibus_writereg(device_t, int, int, int); 480 void atse_miibus_statchg(device_t); 481 482 extern devclass_t atse_devclass; 483 484 #endif /* _DEV_IF_ATSEREG_H */ 485 486 /* end */
Cache object: ee964104fce51eec3fb9bdc516503778
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