Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/amdgpio/amdgpio.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Advanced Micro Devices 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifdef DEBUG 32 #define dprintf(fmt, args...) do { \ 33 printf("%s(): ", __func__); \ 34 printf(fmt,##args); \ 35 } while (0) 36 #else 37 #define dprintf(fmt, args...) 38 #endif 39 40 #define AMD_GPIO_PREFIX "AMDGPIO" 41 42 #define AMD_GPIO_NUM_PIN_BANK 4 43 #define AMD_GPIO_PINS_PER_BANK 64 44 #define AMD_GPIO_PINS_MAX 256 /* 4 banks * 64 pins */ 45 46 /* Number of pins in each bank */ 47 #define AMD_GPIO_PINS_BANK0 63 48 #define AMD_GPIO_PINS_BANK1 64 49 #define AMD_GPIO_PINS_BANK2 56 50 #define AMD_GPIO_PINS_BANK3 32 51 #define AMD_GPIO_PIN_PRESENT (AMD_GPIO_PINS_BANK0 + \ 52 AMD_GPIO_PINS_BANK1 + \ 53 AMD_GPIO_PINS_BANK2 + \ 54 AMD_GPIO_PINS_BANK3) 55 #define AMDGPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 56 57 /* Register related macros */ 58 #define AMDGPIO_PIN_REGISTER(pin) (pin * 4) 59 60 #define WAKE_INT_MASTER_REG 0xfc 61 #define EOI_MASK (1 << 29) 62 #define WAKE_INT_STATUS_REG0 0x2f8 63 #define WAKE_INT_STATUS_REG1 0x2fc 64 65 /* Bit definition of 32 bits of each pin register */ 66 #define DB_TMR_OUT_OFF 0 67 #define DB_TMR_OUT_UNIT_OFF 4 68 #define DB_CNTRL_OFF 5 69 #define DB_TMR_LARGE_OFF 7 70 #define LEVEL_TRIG_OFF 8 71 #define ACTIVE_LEVEL_OFF 9 72 #define INTERRUPT_ENABLE_OFF 11 73 #define INTERRUPT_MASK_OFF 12 74 #define WAKE_CNTRL_OFF_S0I3 13 75 #define WAKE_CNTRL_OFF_S3 14 76 #define WAKE_CNTRL_OFF_S4 15 77 #define PIN_STS_OFF 16 78 #define DRV_STRENGTH_SEL_OFF 17 79 #define PULL_UP_SEL_OFF 19 80 #define PULL_UP_ENABLE_OFF 20 81 #define PULL_DOWN_ENABLE_OFF 21 82 #define OUTPUT_VALUE_OFF 22 83 #define OUTPUT_ENABLE_OFF 23 84 #define SW_CNTRL_IN_OFF 24 85 #define SW_CNTRL_EN_OFF 25 86 #define INTERRUPT_STS_OFF 28 87 #define WAKE_STS_OFF 29 88 89 #define DB_TMR_OUT_MASK 0xFUL 90 #define DB_CNTRL_MASK 0x3UL 91 #define ACTIVE_LEVEL_MASK 0x3UL 92 #define DRV_STRENGTH_SEL_MASK 0x3UL 93 94 #define DB_TYPE_NO_DEBOUNCE 0x0UL 95 #define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL 96 #define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL 97 #define DB_TYPE_REMOVE_GLITCH 0x3UL 98 99 #define EDGE_TRIGGER 0x0UL 100 #define LEVEL_TRIGGER 0x1UL 101 102 #define ACTIVE_HIGH 0x0UL 103 #define ACTIVE_LOW 0x1UL 104 #define BOTH_EDGE 0x2UL 105 106 #define ENABLE_INTERRUPT 0x1UL 107 #define DISABLE_INTERRUPT 0x0UL 108 109 #define ENABLE_INTERRUPT_MASK 0x0UL 110 #define DISABLE_INTERRUPT_MASK 0x1UL 111 #define CLR_INTR_STAT 0x1UL 112 113 #define BIT(bit) (1 << bit) 114 #define GPIO_PIN_INFO(p, n) { .pin_num = (p), .pin_name = (n) } 115 116 struct pin_info { 117 int pin_num; 118 char *pin_name; 119 }; 120 121 /* Pins exposed to drivers */ 122 static const struct pin_info kernzp_pins[] = { 123 GPIO_PIN_INFO(0, "PIN_0"), 124 GPIO_PIN_INFO(1, "PIN_1"), 125 GPIO_PIN_INFO(2, "PIN_2"), 126 GPIO_PIN_INFO(3, "PIN_3"), 127 GPIO_PIN_INFO(4, "PIN_4"), 128 GPIO_PIN_INFO(5, "PIN_5"), 129 GPIO_PIN_INFO(6, "PIN_6"), 130 GPIO_PIN_INFO(7, "PIN_7"), 131 GPIO_PIN_INFO(8, "PIN_8"), 132 GPIO_PIN_INFO(9, "PIN_9"), 133 GPIO_PIN_INFO(10, "PIN_10"), 134 GPIO_PIN_INFO(11, "PIN_11"), 135 GPIO_PIN_INFO(12, "PIN_12"), 136 GPIO_PIN_INFO(13, "PIN_13"), 137 GPIO_PIN_INFO(14, "PIN_14"), 138 GPIO_PIN_INFO(15, "PIN_15"), 139 GPIO_PIN_INFO(16, "PIN_16"), 140 GPIO_PIN_INFO(17, "PIN_17"), 141 GPIO_PIN_INFO(18, "PIN_18"), 142 GPIO_PIN_INFO(19, "PIN_19"), 143 GPIO_PIN_INFO(20, "PIN_20"), 144 GPIO_PIN_INFO(23, "PIN_23"), 145 GPIO_PIN_INFO(24, "PIN_24"), 146 GPIO_PIN_INFO(25, "PIN_25"), 147 GPIO_PIN_INFO(26, "PIN_26"), 148 GPIO_PIN_INFO(39, "PIN_39"), 149 GPIO_PIN_INFO(40, "PIN_40"), 150 GPIO_PIN_INFO(43, "PIN_43"), 151 GPIO_PIN_INFO(46, "PIN_46"), 152 GPIO_PIN_INFO(47, "PIN_47"), 153 GPIO_PIN_INFO(48, "PIN_48"), 154 GPIO_PIN_INFO(49, "PIN_49"), 155 GPIO_PIN_INFO(50, "PIN_50"), 156 GPIO_PIN_INFO(51, "PIN_51"), 157 GPIO_PIN_INFO(52, "PIN_52"), 158 GPIO_PIN_INFO(53, "PIN_53"), 159 GPIO_PIN_INFO(54, "PIN_54"), 160 GPIO_PIN_INFO(55, "PIN_55"), 161 GPIO_PIN_INFO(56, "PIN_56"), 162 GPIO_PIN_INFO(57, "PIN_57"), 163 GPIO_PIN_INFO(58, "PIN_58"), 164 GPIO_PIN_INFO(59, "PIN_59"), 165 GPIO_PIN_INFO(60, "PIN_60"), 166 GPIO_PIN_INFO(61, "PIN_61"), 167 GPIO_PIN_INFO(62, "PIN_62"), 168 GPIO_PIN_INFO(64, "PIN_64"), 169 GPIO_PIN_INFO(65, "PIN_65"), 170 GPIO_PIN_INFO(66, "PIN_66"), 171 GPIO_PIN_INFO(68, "PIN_68"), 172 GPIO_PIN_INFO(69, "PIN_69"), 173 GPIO_PIN_INFO(70, "PIN_70"), 174 GPIO_PIN_INFO(71, "PIN_71"), 175 GPIO_PIN_INFO(72, "PIN_72"), 176 GPIO_PIN_INFO(74, "PIN_74"), 177 GPIO_PIN_INFO(75, "PIN_75"), 178 GPIO_PIN_INFO(76, "PIN_76"), 179 GPIO_PIN_INFO(84, "PIN_84"), 180 GPIO_PIN_INFO(85, "PIN_85"), 181 GPIO_PIN_INFO(86, "PIN_86"), 182 GPIO_PIN_INFO(87, "PIN_87"), 183 GPIO_PIN_INFO(88, "PIN_88"), 184 GPIO_PIN_INFO(89, "PIN_89"), 185 GPIO_PIN_INFO(90, "PIN_90"), 186 GPIO_PIN_INFO(91, "PIN_91"), 187 GPIO_PIN_INFO(92, "PIN_92"), 188 GPIO_PIN_INFO(93, "PIN_93"), 189 GPIO_PIN_INFO(95, "PIN_95"), 190 GPIO_PIN_INFO(96, "PIN_96"), 191 GPIO_PIN_INFO(97, "PIN_97"), 192 GPIO_PIN_INFO(98, "PIN_98"), 193 GPIO_PIN_INFO(99, "PIN_99"), 194 GPIO_PIN_INFO(100, "PIN_100"), 195 GPIO_PIN_INFO(101, "PIN_101"), 196 GPIO_PIN_INFO(102, "PIN_102"), 197 GPIO_PIN_INFO(113, "PIN_113"), 198 GPIO_PIN_INFO(114, "PIN_114"), 199 GPIO_PIN_INFO(115, "PIN_115"), 200 GPIO_PIN_INFO(116, "PIN_116"), 201 GPIO_PIN_INFO(117, "PIN_117"), 202 GPIO_PIN_INFO(118, "PIN_118"), 203 GPIO_PIN_INFO(119, "PIN_119"), 204 GPIO_PIN_INFO(120, "PIN_120"), 205 GPIO_PIN_INFO(121, "PIN_121"), 206 GPIO_PIN_INFO(122, "PIN_122"), 207 GPIO_PIN_INFO(126, "PIN_126"), 208 GPIO_PIN_INFO(129, "PIN_129"), 209 GPIO_PIN_INFO(130, "PIN_130"), 210 GPIO_PIN_INFO(131, "PIN_131"), 211 GPIO_PIN_INFO(132, "PIN_132"), 212 GPIO_PIN_INFO(133, "PIN_133"), 213 GPIO_PIN_INFO(135, "PIN_135"), 214 GPIO_PIN_INFO(136, "PIN_136"), 215 GPIO_PIN_INFO(137, "PIN_137"), 216 GPIO_PIN_INFO(138, "PIN_138"), 217 GPIO_PIN_INFO(139, "PIN_139"), 218 GPIO_PIN_INFO(140, "PIN_140"), 219 GPIO_PIN_INFO(141, "PIN_141"), 220 GPIO_PIN_INFO(142, "PIN_142"), 221 GPIO_PIN_INFO(143, "PIN_143"), 222 GPIO_PIN_INFO(144, "PIN_144"), 223 GPIO_PIN_INFO(145, "PIN_145"), 224 GPIO_PIN_INFO(146, "PIN_146"), 225 GPIO_PIN_INFO(147, "PIN_147"), 226 GPIO_PIN_INFO(148, "PIN_148"), 227 GPIO_PIN_INFO(166, "PIN_166"), 228 GPIO_PIN_INFO(167, "PIN_167"), 229 GPIO_PIN_INFO(168, "PIN_168"), 230 GPIO_PIN_INFO(169, "PIN_169"), 231 GPIO_PIN_INFO(170, "PIN_170"), 232 GPIO_PIN_INFO(171, "PIN_171"), 233 GPIO_PIN_INFO(172, "PIN_172"), 234 GPIO_PIN_INFO(173, "PIN_173"), 235 GPIO_PIN_INFO(174, "PIN_174"), 236 GPIO_PIN_INFO(175, "PIN_175"), 237 GPIO_PIN_INFO(176, "PIN_176"), 238 GPIO_PIN_INFO(177, "PIN_177"), 239 }; 240 241 #define AMD_GPIO_PINS_EXPOSED nitems(kernzp_pins) 242 243 static const unsigned i2c0_pins[] = {145, 146}; 244 static const unsigned i2c1_pins[] = {147, 148}; 245 static const unsigned i2c2_pins[] = {113, 114}; 246 static const unsigned i2c3_pins[] = {19, 20}; 247 static const unsigned i2c4_pins[] = {149, 150}; 248 static const unsigned i2c5_pins[] = {151, 152}; 249 250 static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; 251 static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; 252 253 struct amd_pingroup { 254 const char *name; 255 const unsigned *pins; 256 unsigned npins; 257 }; 258 259 static const struct amd_pingroup kernzp_groups[] = { 260 { 261 .name = "i2c0", 262 .pins = i2c0_pins, 263 .npins = 2, 264 }, 265 { 266 .name = "i2c1", 267 .pins = i2c1_pins, 268 .npins = 2, 269 }, 270 { 271 .name = "i2c2", 272 .pins = i2c2_pins, 273 .npins = 2, 274 }, 275 { 276 .name = "i2c3", 277 .pins = i2c3_pins, 278 .npins = 2, 279 }, 280 { 281 .name = "i2c4", 282 .pins = i2c4_pins, 283 .npins = 2, 284 }, 285 { 286 .name = "i2c5", 287 .pins = i2c5_pins, 288 .npins = 2, 289 }, 290 { 291 .name = "uart0", 292 .pins = uart0_pins, 293 .npins = 5, 294 }, 295 { 296 .name = "uart1", 297 .pins = uart1_pins, 298 .npins = 5, 299 }, 300 }; 301 302 /* Macros for driver mutex locking */ 303 #define AMDGPIO_LOCK_INIT(_sc) \ 304 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 305 "amdgpio", MTX_SPIN) 306 #define AMDGPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 307 #define AMDGPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 308 #define AMDGPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 309 #define AMDGPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 310 #define AMDGPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 311 312 struct amdgpio_softc { 313 ACPI_HANDLE sc_handle; 314 device_t sc_dev; 315 device_t sc_busdev; 316 const char* sc_bank_prefix; 317 int sc_nbanks; 318 int sc_npins; 319 int sc_ngroups; 320 struct mtx sc_mtx; 321 struct resource *sc_res[AMD_GPIO_NUM_PIN_BANK + 1]; 322 bus_space_tag_t sc_bst; 323 bus_space_handle_t sc_bsh; 324 struct gpio_pin sc_gpio_pins[AMD_GPIO_PINS_MAX]; 325 const struct pin_info *sc_pin_info; 326 const struct amd_pingroup *sc_groups; 327 }; 328 329 struct amdgpio_sysctl { 330 struct amdgpio_softc *sc; 331 uint32_t pin; 332 };
Cache object: 1e2a555d78e4a131ea2b3c51947dfb3c
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