1 /*-
2 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
29 * southbridges.
30 * Please see the following specifications for the descriptions of the
31 * registers and flags:
32 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
33 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
34 * - AMD SB700/710/750 Register Reference Guide (RRG)
35 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
36 * - AMD SB700/710/750 Register Programming Requirements (RPR)
37 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
38 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
39 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf
40 * Please see the following for Watchdog Resource Table specification:
41 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
42 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
43 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
44 * specifications, but the table hasn't been spotted in the wild yet.
45 */
46
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD: releng/11.2/sys/dev/amdsbwd/amdsbwd.c 331722 2018-03-29 02:50:57Z eadler $");
49
50 #include <sys/param.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
55 #include <sys/bus.h>
56 #include <machine/bus.h>
57 #include <sys/rman.h>
58 #include <machine/resource.h>
59 #include <sys/watchdog.h>
60
61 #include <dev/pci/pcivar.h>
62 #include <dev/amdsbwd/amd_chipset.h>
63 #include <isa/isavar.h>
64
65 /*
66 * Registers in the Watchdog IO space.
67 * See SB7xx RRG 2.3.4, WDRT.
68 */
69 #define AMDSB_WD_CTRL 0x00
70 #define AMDSB_WD_RUN 0x01
71 #define AMDSB_WD_FIRED 0x02
72 #define AMDSB_WD_SHUTDOWN 0x04
73 #define AMDSB_WD_DISABLE 0x08
74 #define AMDSB_WD_RESERVED 0x70
75 #define AMDSB_WD_RELOAD 0x80
76 #define AMDSB_WD_COUNT 0x04
77 #define AMDSB_WD_COUNT_MASK 0xffff
78 #define AMDSB_WDIO_REG_WIDTH 4
79
80 #define amdsbwd_verbose_printf(dev, ...) \
81 do { \
82 if (bootverbose) \
83 device_printf(dev, __VA_ARGS__);\
84 } while (0)
85
86 struct amdsbwd_softc {
87 device_t dev;
88 eventhandler_tag ev_tag;
89 struct resource *res_ctrl;
90 struct resource *res_count;
91 int rid_ctrl;
92 int rid_count;
93 int ms_per_tick;
94 int max_ticks;
95 int active;
96 unsigned int timeout;
97 };
98
99 static void amdsbwd_identify(driver_t *driver, device_t parent);
100 static int amdsbwd_probe(device_t dev);
101 static int amdsbwd_attach(device_t dev);
102 static int amdsbwd_detach(device_t dev);
103
104 static device_method_t amdsbwd_methods[] = {
105 DEVMETHOD(device_identify, amdsbwd_identify),
106 DEVMETHOD(device_probe, amdsbwd_probe),
107 DEVMETHOD(device_attach, amdsbwd_attach),
108 DEVMETHOD(device_detach, amdsbwd_detach),
109 #if 0
110 DEVMETHOD(device_shutdown, amdsbwd_detach),
111 #endif
112 DEVMETHOD_END
113 };
114
115 static devclass_t amdsbwd_devclass;
116 static driver_t amdsbwd_driver = {
117 "amdsbwd",
118 amdsbwd_methods,
119 sizeof(struct amdsbwd_softc)
120 };
121
122 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
123
124
125 static uint8_t
126 pmio_read(struct resource *res, uint8_t reg)
127 {
128 bus_write_1(res, 0, reg); /* Index */
129 return (bus_read_1(res, 1)); /* Data */
130 }
131
132 static void
133 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
134 {
135 bus_write_1(res, 0, reg); /* Index */
136 bus_write_1(res, 1, val); /* Data */
137 }
138
139 static uint32_t
140 wdctrl_read(struct amdsbwd_softc *sc)
141 {
142 return (bus_read_4(sc->res_ctrl, 0));
143 }
144
145 static void
146 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
147 {
148 bus_write_4(sc->res_ctrl, 0, val);
149 }
150
151 static __unused uint32_t
152 wdcount_read(struct amdsbwd_softc *sc)
153 {
154 return (bus_read_4(sc->res_count, 0));
155 }
156
157 static void
158 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
159 {
160 bus_write_4(sc->res_count, 0, val);
161 }
162
163 static void
164 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
165 {
166 uint32_t val;
167
168 val = wdctrl_read(sc);
169 val |= AMDSB_WD_RUN;
170 wdctrl_write(sc, val);
171 sc->active = 1;
172 amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
173 }
174
175 static void
176 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
177 {
178 uint32_t val;
179
180 val = wdctrl_read(sc);
181 val &= ~AMDSB_WD_RUN;
182 wdctrl_write(sc, val);
183 sc->active = 0;
184 amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
185 }
186
187 static void
188 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
189 {
190 uint32_t val;
191
192 val = wdctrl_read(sc);
193 val |= AMDSB_WD_RELOAD;
194 wdctrl_write(sc, val);
195 }
196
197 static void
198 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
199 {
200
201 timeout &= AMDSB_WD_COUNT_MASK;
202 wdcount_write(sc, timeout);
203 sc->timeout = timeout;
204 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
205 }
206
207 static void
208 amdsbwd_event(void *arg, unsigned int cmd, int *error)
209 {
210 struct amdsbwd_softc *sc = arg;
211 uint64_t timeout;
212
213 if (cmd != 0) {
214 timeout = 0;
215 cmd &= WD_INTERVAL;
216 if (cmd >= WD_TO_1MS) {
217 timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
218 timeout = timeout / sc->ms_per_tick;
219 }
220 /* For a too short timeout use 1 tick. */
221 if (timeout == 0)
222 timeout = 1;
223 /* For a too long timeout stop the timer. */
224 if (timeout > sc->max_ticks)
225 timeout = 0;
226 } else {
227 timeout = 0;
228 }
229
230 if (timeout != 0) {
231 if (timeout != sc->timeout)
232 amdsbwd_tmr_set(sc, timeout);
233 if (!sc->active)
234 amdsbwd_tmr_enable(sc);
235 amdsbwd_tmr_reload(sc);
236 *error = 0;
237 } else {
238 if (sc->active)
239 amdsbwd_tmr_disable(sc);
240 }
241 }
242
243 static void
244 amdsbwd_identify(driver_t *driver, device_t parent)
245 {
246 device_t child;
247 device_t smb_dev;
248
249 if (resource_disabled("amdsbwd", 0))
250 return;
251 if (device_find_child(parent, "amdsbwd", -1) != NULL)
252 return;
253
254 /*
255 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
256 * that should be present at bus 0, device 20, function 0.
257 */
258 smb_dev = pci_find_bsf(0, 20, 0);
259 if (smb_dev == NULL)
260 return;
261 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
262 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
263 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID)
264 return;
265
266 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
267 if (child == NULL)
268 device_printf(parent, "add amdsbwd child failed\n");
269 }
270
271
272 static void
273 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
274 {
275 uint8_t val;
276 int i;
277
278 /* Report cause of previous reset for user's convenience. */
279 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
280 if (val != 0)
281 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
282 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
283 if (val != 0)
284 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
285 if ((val & AMDSB_WD_RST_STS) != 0)
286 device_printf(dev, "Previous Reset was caused by Watchdog\n");
287
288 /* Find base address of memory mapped WDT registers. */
289 for (*addr = 0, i = 0; i < 4; i++) {
290 *addr <<= 8;
291 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
292 }
293 *addr &= ~0x07u;
294
295 /* Set watchdog timer tick to 1s. */
296 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
297 val &= ~AMDSB_WDT_RES_MASK;
298 val |= AMDSB_WDT_RES_1S;
299 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
300
301 /* Enable watchdog device (in stopped state). */
302 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
303 val &= ~AMDSB_WDT_DISABLE;
304 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
305
306 /*
307 * XXX TODO: Ensure that watchdog decode is enabled
308 * (register 0x41, bit 3).
309 */
310 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
311 }
312
313 static void
314 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
315 {
316 uint8_t val;
317 int i;
318
319 /* Report cause of previous reset for user's convenience. */
320 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0);
321 if (val != 0)
322 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
323 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1);
324 if (val != 0)
325 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
326 if ((val & AMDSB8_WD_RST_STS) != 0)
327 device_printf(dev, "Previous Reset was caused by Watchdog\n");
328
329 /* Find base address of memory mapped WDT registers. */
330 for (*addr = 0, i = 0; i < 4; i++) {
331 *addr <<= 8;
332 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
333 }
334 *addr &= ~0x07u;
335
336 /* Set watchdog timer tick to 1s. */
337 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
338 val &= ~AMDSB8_WDT_RES_MASK;
339 val |= AMDSB8_WDT_1HZ;
340 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
341 #ifdef AMDSBWD_DEBUG
342 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
343 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
344 #endif
345
346 /*
347 * Enable watchdog device (in stopped state)
348 * and decoding of its address.
349 */
350 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
351 val &= ~AMDSB8_WDT_DISABLE;
352 val |= AMDSB8_WDT_DEC_EN;
353 pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
354 #ifdef AMDSBWD_DEBUG
355 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
356 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
357 #endif
358 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
359 }
360
361 static void
362 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
363 {
364 uint8_t val;
365
366 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
367 if ((val & AMDFCH41_MMIO_EN) != 0) {
368 /* Fixed offset for the watchdog within ACPI MMIO range. */
369 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
370 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
371 } else {
372 /*
373 * Enable decoding of watchdog MMIO address.
374 */
375 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
376 val |= AMDFCH41_WDT_EN;
377 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
378 #ifdef AMDSBWD_DEBUG
379 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
380 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
381 val);
382 #endif
383
384 /* Special fixed MMIO range for the watchdog. */
385 *addr = AMDFCH41_WDT_FIXED_ADDR;
386 }
387
388 /*
389 * Set watchdog timer tick to 1s and
390 * enable the watchdog device (in stopped state).
391 */
392 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
393 val &= ~AMDFCH41_WDT_RES_MASK;
394 val |= AMDFCH41_WDT_RES_1S;
395 val &= ~AMDFCH41_WDT_EN_MASK;
396 val |= AMDFCH41_WDT_ENABLE;
397 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
398 #ifdef AMDSBWD_DEBUG
399 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
400 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
401 val);
402 #endif
403 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer");
404 }
405
406 static int
407 amdsbwd_probe(device_t dev)
408 {
409 struct resource *res;
410 device_t smb_dev;
411 uint32_t addr;
412 int rid;
413 int rc;
414 uint32_t devid;
415 uint8_t revid;
416
417 /* Do not claim some ISA PnP device by accident. */
418 if (isa_get_logicalid(dev) != 0)
419 return (ENXIO);
420
421 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
422 AMDSB_PMIO_WIDTH);
423 if (rc != 0) {
424 device_printf(dev, "bus_set_resource for IO failed\n");
425 return (ENXIO);
426 }
427 rid = 0;
428 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
429 RF_ACTIVE | RF_SHAREABLE);
430 if (res == NULL) {
431 device_printf(dev, "bus_alloc_resource for IO failed\n");
432 return (ENXIO);
433 }
434
435 smb_dev = pci_find_bsf(0, 20, 0);
436 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
437 devid = pci_get_devid(smb_dev);
438 revid = pci_get_revid(smb_dev);
439 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
440 amdsbwd_probe_sb7xx(dev, res, &addr);
441 else if (devid == AMDSB_SMBUS_DEVID ||
442 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
443 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID))
444 amdsbwd_probe_sb8xx(dev, res, &addr);
445 else
446 amdsbwd_probe_fch41(dev, res, &addr);
447
448 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
449 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
450
451 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
452 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
453 AMDSB_WDIO_REG_WIDTH);
454 if (rc != 0) {
455 device_printf(dev, "bus_set_resource for control failed\n");
456 return (ENXIO);
457 }
458 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
459 AMDSB_WDIO_REG_WIDTH);
460 if (rc != 0) {
461 device_printf(dev, "bus_set_resource for count failed\n");
462 return (ENXIO);
463 }
464
465 return (0);
466 }
467
468 static int
469 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
470 {
471
472 sc->max_ticks = UINT16_MAX;
473 sc->rid_ctrl = 0;
474 sc->rid_count = 1;
475
476 sc->ms_per_tick = 1000;
477
478 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
479 &sc->rid_ctrl, RF_ACTIVE);
480 if (sc->res_ctrl == NULL) {
481 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
482 return (ENXIO);
483 }
484 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
485 &sc->rid_count, RF_ACTIVE);
486 if (sc->res_count == NULL) {
487 device_printf(dev, "bus_alloc_resource for count failed\n");
488 return (ENXIO);
489 }
490 return (0);
491 }
492
493 static int
494 amdsbwd_attach(device_t dev)
495 {
496 struct amdsbwd_softc *sc;
497 int rc;
498
499 sc = device_get_softc(dev);
500 sc->dev = dev;
501
502 rc = amdsbwd_attach_sb(dev, sc);
503 if (rc != 0)
504 goto fail;
505
506 #ifdef AMDSBWD_DEBUG
507 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
508 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
509 #endif
510
511 /* Setup initial state of Watchdog Control. */
512 wdctrl_write(sc, AMDSB_WD_FIRED);
513
514 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
515 device_printf(dev, "watchdog hardware is disabled\n");
516 goto fail;
517 }
518
519 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
520 EVENTHANDLER_PRI_ANY);
521
522 return (0);
523
524 fail:
525 amdsbwd_detach(dev);
526 return (ENXIO);
527 }
528
529 static int
530 amdsbwd_detach(device_t dev)
531 {
532 struct amdsbwd_softc *sc;
533
534 sc = device_get_softc(dev);
535 if (sc->ev_tag != NULL)
536 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
537
538 if (sc->active)
539 amdsbwd_tmr_disable(sc);
540
541 if (sc->res_ctrl != NULL)
542 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
543 sc->res_ctrl);
544
545 if (sc->res_count != NULL)
546 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
547 sc->res_count);
548
549 return (0);
550 }
551
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