The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/amdsbwd/amdsbwd.c

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    1 /*-
    2  * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
   29  * southbridges.
   30  * Please see the following specifications for the descriptions of the
   31  * registers and flags:
   32  * - AMD SB600 Register Reference Guide, Public Version,  Rev. 3.03 (SB600 RRG)
   33  *   http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
   34  * - AMD SB700/710/750 Register Reference Guide (RRG)
   35  *   http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
   36  * - AMD SB700/710/750 Register Programming Requirements (RPR)
   37  *   http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
   38  * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
   39  *   http://support.amd.com/us/Embedded_TechDocs/45482.pdf
   40  * Please see the following for Watchdog Resource Table specification:
   41  * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
   42  *   http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
   43  * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
   44  * specifications, but the table hasn't been spotted in the wild yet.
   45  */
   46 
   47 #include <sys/cdefs.h>
   48 __FBSDID("$FreeBSD: stable/11/sys/dev/amdsbwd/amdsbwd.c 335542 2018-06-22 09:25:24Z avg $");
   49 
   50 #include <sys/param.h>
   51 #include <sys/kernel.h>
   52 #include <sys/module.h>
   53 #include <sys/systm.h>
   54 #include <sys/sysctl.h>
   55 #include <sys/bus.h>
   56 #include <machine/bus.h>
   57 #include <sys/rman.h>
   58 #include <machine/resource.h>
   59 #include <sys/watchdog.h>
   60 
   61 #include <dev/pci/pcivar.h>
   62 #include <dev/amdsbwd/amd_chipset.h>
   63 #include <isa/isavar.h>
   64 
   65 /*
   66  * Registers in the Watchdog IO space.
   67  * See SB7xx RRG 2.3.4, WDRT.
   68  */
   69 #define AMDSB_WD_CTRL                   0x00
   70 #define         AMDSB_WD_RUN            0x01
   71 #define         AMDSB_WD_FIRED          0x02
   72 #define         AMDSB_WD_SHUTDOWN       0x04
   73 #define         AMDSB_WD_DISABLE        0x08
   74 #define         AMDSB_WD_RESERVED       0x70
   75 #define         AMDSB_WD_RELOAD         0x80
   76 #define AMDSB_WD_COUNT                  0x04
   77 #define         AMDSB_WD_COUNT_MASK     0xffff
   78 #define AMDSB_WDIO_REG_WIDTH            4
   79 
   80 #define amdsbwd_verbose_printf(dev, ...)        \
   81         do {                                            \
   82                 if (bootverbose)                        \
   83                         device_printf(dev, __VA_ARGS__);\
   84         } while (0)
   85 
   86 struct amdsbwd_softc {
   87         device_t                dev;
   88         eventhandler_tag        ev_tag;
   89         struct resource         *res_ctrl;
   90         struct resource         *res_count;
   91         int                     rid_ctrl;
   92         int                     rid_count;
   93         int                     ms_per_tick;
   94         int                     max_ticks;
   95         int                     active;
   96         unsigned int            timeout;
   97 };
   98 
   99 static void     amdsbwd_identify(driver_t *driver, device_t parent);
  100 static int      amdsbwd_probe(device_t dev);
  101 static int      amdsbwd_attach(device_t dev);
  102 static int      amdsbwd_detach(device_t dev);
  103 static int      amdsbwd_suspend(device_t dev);
  104 static int      amdsbwd_resume(device_t dev);
  105 
  106 static device_method_t amdsbwd_methods[] = {
  107         DEVMETHOD(device_identify,      amdsbwd_identify),
  108         DEVMETHOD(device_probe,         amdsbwd_probe),
  109         DEVMETHOD(device_attach,        amdsbwd_attach),
  110         DEVMETHOD(device_detach,        amdsbwd_detach),
  111         DEVMETHOD(device_suspend,       amdsbwd_suspend),
  112         DEVMETHOD(device_resume,        amdsbwd_resume),
  113 #if 0
  114         DEVMETHOD(device_shutdown,      amdsbwd_detach),
  115 #endif
  116         DEVMETHOD_END
  117 };
  118 
  119 static devclass_t       amdsbwd_devclass;
  120 static driver_t         amdsbwd_driver = {
  121         "amdsbwd",
  122         amdsbwd_methods,
  123         sizeof(struct amdsbwd_softc)
  124 };
  125 
  126 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
  127 
  128 
  129 static uint8_t
  130 pmio_read(struct resource *res, uint8_t reg)
  131 {
  132         bus_write_1(res, 0, reg);       /* Index */
  133         return (bus_read_1(res, 1));    /* Data */
  134 }
  135 
  136 static void
  137 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
  138 {
  139         bus_write_1(res, 0, reg);       /* Index */
  140         bus_write_1(res, 1, val);       /* Data */
  141 }
  142 
  143 static uint32_t
  144 wdctrl_read(struct amdsbwd_softc *sc)
  145 {
  146         return (bus_read_4(sc->res_ctrl, 0));
  147 }
  148 
  149 static void
  150 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
  151 {
  152         bus_write_4(sc->res_ctrl, 0, val);
  153 }
  154 
  155 static __unused uint32_t
  156 wdcount_read(struct amdsbwd_softc *sc)
  157 {
  158         return (bus_read_4(sc->res_count, 0));
  159 }
  160 
  161 static void
  162 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
  163 {
  164         bus_write_4(sc->res_count, 0, val);
  165 }
  166 
  167 static void
  168 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
  169 {
  170         uint32_t val;
  171 
  172         val = wdctrl_read(sc);
  173         val |= AMDSB_WD_RUN;
  174         wdctrl_write(sc, val);
  175         sc->active = 1;
  176         amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
  177 }
  178 
  179 static void
  180 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
  181 {
  182         uint32_t val;
  183 
  184         val = wdctrl_read(sc);
  185         val &= ~AMDSB_WD_RUN;
  186         wdctrl_write(sc, val);
  187         sc->active = 0;
  188         amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
  189 }
  190 
  191 static void
  192 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
  193 {
  194         uint32_t val;
  195 
  196         val = wdctrl_read(sc);
  197         val |= AMDSB_WD_RELOAD;
  198         wdctrl_write(sc, val);
  199 }
  200 
  201 static void
  202 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
  203 {
  204 
  205         timeout &= AMDSB_WD_COUNT_MASK;
  206         wdcount_write(sc, timeout);
  207         sc->timeout = timeout;
  208         amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
  209 }
  210 
  211 static void
  212 amdsbwd_event(void *arg, unsigned int cmd, int *error)
  213 {
  214         struct amdsbwd_softc *sc = arg;
  215         uint64_t timeout;
  216 
  217         if (cmd != 0) {
  218                 timeout = 0;
  219                 cmd &= WD_INTERVAL;
  220                 if (cmd >= WD_TO_1MS) {
  221                         timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
  222                         timeout = timeout / sc->ms_per_tick;
  223                 }
  224                 /* For a too short timeout use 1 tick. */
  225                 if (timeout == 0)
  226                         timeout = 1;
  227                 /* For a too long timeout stop the timer. */
  228                 if (timeout > sc->max_ticks)
  229                         timeout = 0;
  230         } else {
  231                 timeout = 0;
  232         }
  233 
  234         if (timeout != 0) {
  235                 if (timeout != sc->timeout)
  236                         amdsbwd_tmr_set(sc, timeout);
  237                 if (!sc->active)
  238                         amdsbwd_tmr_enable(sc);
  239                 amdsbwd_tmr_reload(sc);
  240                 *error = 0;
  241         } else {
  242                 if (sc->active)
  243                         amdsbwd_tmr_disable(sc);
  244         }
  245 }
  246 
  247 static void
  248 amdsbwd_identify(driver_t *driver, device_t parent)
  249 {
  250         device_t                child;
  251         device_t                smb_dev;
  252 
  253         if (resource_disabled("amdsbwd", 0))
  254                 return;
  255         if (device_find_child(parent, "amdsbwd", -1) != NULL)
  256                 return;
  257 
  258         /*
  259          * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
  260          * that should be present at bus 0, device 20, function 0.
  261          */
  262         smb_dev = pci_find_bsf(0, 20, 0);
  263         if (smb_dev == NULL)
  264                 return;
  265         if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
  266             pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
  267             pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID)
  268                 return;
  269 
  270         child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
  271         if (child == NULL)
  272                 device_printf(parent, "add amdsbwd child failed\n");
  273 }
  274 
  275 
  276 static void
  277 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
  278 {
  279         uint8_t val;
  280         int     i;
  281 
  282         /* Report cause of previous reset for user's convenience. */
  283         val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
  284         if (val != 0)
  285                 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
  286         val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
  287         if (val != 0)
  288                 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
  289         if ((val & AMDSB_WD_RST_STS) != 0)
  290                 device_printf(dev, "Previous Reset was caused by Watchdog\n");
  291 
  292         /* Find base address of memory mapped WDT registers. */
  293         for (*addr = 0, i = 0; i < 4; i++) {
  294                 *addr <<= 8;
  295                 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
  296         }
  297         *addr &= ~0x07u;
  298 
  299         /* Set watchdog timer tick to 1s. */
  300         val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
  301         val &= ~AMDSB_WDT_RES_MASK;
  302         val |= AMDSB_WDT_RES_1S;
  303         pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
  304 
  305         /* Enable watchdog device (in stopped state). */
  306         val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
  307         val &= ~AMDSB_WDT_DISABLE;
  308         pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
  309 
  310         /*
  311          * XXX TODO: Ensure that watchdog decode is enabled
  312          * (register 0x41, bit 3).
  313          */
  314         device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
  315 }
  316 
  317 static void
  318 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
  319 {
  320         uint32_t        val;
  321         int             i;
  322 
  323         /* Report cause of previous reset for user's convenience. */
  324 
  325         val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL);
  326         if ((val & AMDSB8_RST_STS_DIS) != 0) {
  327                 val &= ~AMDSB8_RST_STS_DIS;
  328                 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val);
  329         }
  330         val = 0;
  331         for (i = 3; i >= 0; i--) {
  332                 val <<= 8;
  333                 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i);
  334         }
  335         if (val != 0)
  336                 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val);
  337         if ((val & AMDSB8_WD_RST_STS) != 0)
  338                 device_printf(dev, "Previous Reset was caused by Watchdog\n");
  339 
  340         /* Find base address of memory mapped WDT registers. */
  341         for (*addr = 0, i = 0; i < 4; i++) {
  342                 *addr <<= 8;
  343                 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
  344         }
  345         *addr &= ~0x07u;
  346 
  347         /* Set watchdog timer tick to 1s. */
  348         val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
  349         val &= ~AMDSB8_WDT_RES_MASK;
  350         val |= AMDSB8_WDT_1HZ;
  351         pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
  352 #ifdef AMDSBWD_DEBUG
  353         val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
  354         amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
  355 #endif
  356 
  357         /*
  358          * Enable watchdog device (in stopped state)
  359          * and decoding of its address.
  360          */
  361         val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
  362         val &= ~AMDSB8_WDT_DISABLE;
  363         val |= AMDSB8_WDT_DEC_EN;
  364         pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
  365 #ifdef AMDSBWD_DEBUG
  366         val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
  367         device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
  368 #endif
  369         device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
  370 }
  371 
  372 static void
  373 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
  374 {
  375         uint8_t val;
  376 
  377         val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
  378         if ((val & AMDFCH41_MMIO_EN) != 0) {
  379                 /* Fixed offset for the watchdog within ACPI MMIO range. */
  380                 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
  381                 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
  382         } else {
  383                 /*
  384                  * Enable decoding of watchdog MMIO address.
  385                  */
  386                 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
  387                 val |= AMDFCH41_WDT_EN;
  388                 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
  389 #ifdef AMDSBWD_DEBUG
  390                 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
  391                 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
  392                     val);
  393 #endif
  394 
  395                 /* Special fixed MMIO range for the watchdog. */
  396                 *addr = AMDFCH41_WDT_FIXED_ADDR;
  397         }
  398 
  399         /*
  400          * Set watchdog timer tick to 1s and
  401          * enable the watchdog device (in stopped state).
  402          */
  403         val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
  404         val &= ~AMDFCH41_WDT_RES_MASK;
  405         val |= AMDFCH41_WDT_RES_1S;
  406         val &= ~AMDFCH41_WDT_EN_MASK;
  407         val |= AMDFCH41_WDT_ENABLE;
  408         pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
  409 #ifdef AMDSBWD_DEBUG
  410         val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
  411         amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
  412             val);
  413 #endif
  414         device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer");
  415 }
  416 
  417 static int
  418 amdsbwd_probe(device_t dev)
  419 {
  420         struct resource         *res;
  421         device_t                smb_dev;
  422         uint32_t                addr;
  423         int                     rid;
  424         int                     rc;
  425         uint32_t                devid;
  426         uint8_t                 revid;
  427 
  428         /* Do not claim some ISA PnP device by accident. */
  429         if (isa_get_logicalid(dev) != 0)
  430                 return (ENXIO);
  431 
  432         rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
  433             AMDSB_PMIO_WIDTH);
  434         if (rc != 0) {
  435                 device_printf(dev, "bus_set_resource for IO failed\n");
  436                 return (ENXIO);
  437         }
  438         rid = 0;
  439         res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
  440             RF_ACTIVE | RF_SHAREABLE);
  441         if (res == NULL) {
  442                 device_printf(dev, "bus_alloc_resource for IO failed\n");
  443                 return (ENXIO);
  444         }
  445 
  446         smb_dev = pci_find_bsf(0, 20, 0);
  447         KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
  448         devid = pci_get_devid(smb_dev);
  449         revid = pci_get_revid(smb_dev);
  450         if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
  451                 amdsbwd_probe_sb7xx(dev, res, &addr);
  452         else if (devid == AMDSB_SMBUS_DEVID ||
  453             (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
  454             (devid == AMDCZ_SMBUS_DEVID  && revid < AMDCZ49_SMBUS_REVID))
  455                 amdsbwd_probe_sb8xx(dev, res, &addr);
  456         else
  457                 amdsbwd_probe_fch41(dev, res, &addr);
  458 
  459         bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
  460         bus_delete_resource(dev, SYS_RES_IOPORT, rid);
  461 
  462         amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
  463         rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
  464             AMDSB_WDIO_REG_WIDTH);
  465         if (rc != 0) {
  466                 device_printf(dev, "bus_set_resource for control failed\n");
  467                 return (ENXIO);
  468         }
  469         rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
  470             AMDSB_WDIO_REG_WIDTH);
  471         if (rc != 0) {
  472                 device_printf(dev, "bus_set_resource for count failed\n");
  473                 return (ENXIO);
  474         }
  475 
  476         return (0);
  477 }
  478 
  479 static int
  480 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
  481 {
  482 
  483         sc->max_ticks = UINT16_MAX;
  484         sc->rid_ctrl = 0;
  485         sc->rid_count = 1;
  486 
  487         sc->ms_per_tick = 1000;
  488 
  489         sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  490             &sc->rid_ctrl, RF_ACTIVE);
  491         if (sc->res_ctrl == NULL) {
  492                 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
  493                 return (ENXIO);
  494         }
  495         sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  496             &sc->rid_count, RF_ACTIVE);
  497         if (sc->res_count == NULL) {
  498                 device_printf(dev, "bus_alloc_resource for count failed\n");
  499                 return (ENXIO);
  500         }
  501         return (0);
  502 }
  503 
  504 static int
  505 amdsbwd_attach(device_t dev)
  506 {
  507         struct amdsbwd_softc    *sc;
  508         int                     rc;
  509 
  510         sc = device_get_softc(dev);
  511         sc->dev = dev;
  512 
  513         rc = amdsbwd_attach_sb(dev, sc);
  514         if (rc != 0)
  515                 goto fail;
  516 
  517 #ifdef AMDSBWD_DEBUG
  518         device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
  519         device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
  520 #endif
  521 
  522         /* Setup initial state of Watchdog Control. */
  523         wdctrl_write(sc, AMDSB_WD_FIRED);
  524 
  525         if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
  526                 device_printf(dev, "watchdog hardware is disabled\n");
  527                 goto fail;
  528         }
  529 
  530         sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
  531             EVENTHANDLER_PRI_ANY);
  532 
  533         return (0);
  534 
  535 fail:
  536         amdsbwd_detach(dev);
  537         return (ENXIO);
  538 }
  539 
  540 static int
  541 amdsbwd_detach(device_t dev)
  542 {
  543         struct amdsbwd_softc *sc;
  544 
  545         sc = device_get_softc(dev);
  546         if (sc->ev_tag != NULL)
  547                 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
  548 
  549         if (sc->active)
  550                 amdsbwd_tmr_disable(sc);
  551 
  552         if (sc->res_ctrl != NULL)
  553                 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
  554                     sc->res_ctrl);
  555 
  556         if (sc->res_count != NULL)
  557                 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
  558                     sc->res_count);
  559 
  560         return (0);
  561 }
  562 
  563 static int
  564 amdsbwd_suspend(device_t dev)
  565 {
  566         struct amdsbwd_softc *sc;
  567         uint32_t val;
  568 
  569         sc = device_get_softc(dev);
  570         val = wdctrl_read(sc);
  571         val &= ~AMDSB_WD_RUN;
  572         wdctrl_write(sc, val);
  573         return (0);
  574 }
  575 
  576 static int
  577 amdsbwd_resume(device_t dev)
  578 {
  579         struct amdsbwd_softc *sc;
  580 
  581         sc = device_get_softc(dev);
  582         wdctrl_write(sc, AMDSB_WD_FIRED);
  583         if (sc->active) {
  584                 amdsbwd_tmr_set(sc, sc->timeout);
  585                 amdsbwd_tmr_enable(sc);
  586                 amdsbwd_tmr_reload(sc);
  587         }
  588         return (0);
  589 }

Cache object: ec41b11b2b81fd361ca430df0bbf146d


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