The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/an/if_anreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-4-Clause
    3  *
    4  * Copyright (c) 1997, 1998, 1999
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: head/sys/dev/an/if_anreg.h 325966 2017-11-18 14:26:50Z pfg $
   35  */
   36 
   37 #define AN_TIMEOUT      65536
   38 
   39 /* Default network name: <empty string> */
   40 #define AN_DEFAULT_NETNAME      ""
   41 
   42 /* The nodename must be less than 16 bytes */
   43 #define AN_DEFAULT_NODENAME     "FreeBSD"
   44 
   45 #define AN_DEFAULT_IBSS         "FreeBSD IBSS"
   46 
   47 /*
   48  * register space access macros
   49  */
   50 #define CSR_WRITE_2(sc, reg, val)       bus_write_2(sc->port_res, reg, val)
   51 
   52 #define CSR_READ_2(sc, reg)             bus_read_2(sc->port_res, reg)
   53 
   54 #define CSR_WRITE_1(sc, reg, val)       bus_write_1(sc->port_res, reg, val)
   55 
   56 #define CSR_READ_1(sc, reg)             bus_read_1(sc->port_res, reg)
   57 
   58 /*
   59  * memory space access macros
   60  */
   61 #define CSR_MEM_WRITE_2(sc, reg, val)   bus_write_2(sc->mem_res, reg, val)
   62 
   63 #define CSR_MEM_READ_2(sc, reg)         bus_read_2(sc->mem_res, reg)
   64 
   65 #define CSR_MEM_WRITE_1(sc, reg, val)   bus_write_1(sc->mem_res, reg, val)
   66 
   67 #define CSR_MEM_READ_1(sc, reg)         bus_read_1(sc->mem_res, reg)
   68 
   69 /*
   70  * aux. memory space access macros
   71  */
   72 #define CSR_MEM_AUX_WRITE_4(sc, reg, val)       \
   73         bus_write_4(sc->mem_aux_res, reg, val)
   74 
   75 #define CSR_MEM_AUX_READ_4(sc, reg)             \
   76         bus_read_4(sc->mem_aux_res, reg)
   77 
   78 #define CSR_MEM_AUX_WRITE_1(sc, reg, val)       \
   79         bus_write_1(sc->mem_aux_res, reg, val)
   80 
   81 #define CSR_MEM_AUX_READ_1(sc, reg)             \
   82         bus_read_1(sc->mem_aux_res, reg)
   83 
   84 /*
   85  * Size of Aironet I/O space.
   86  */
   87 #define AN_IOSIZ                0x40
   88 
   89 /*
   90  * Size of aux. memory space ... probably not needed DJA 
   91  */
   92 #define AN_AUX_MEM_SIZE         (256 * 1024)
   93 
   94 /*
   95  * Hermes register definitions and what little I know about them.
   96  */
   97 
   98 /* Hermes command/status registers. */
   99 #define AN_COMMAND(x)           (x ? 0x00 : 0x00)
  100 #define AN_PARAM0(x)            (x ? 0x04 : 0x02)
  101 #define AN_PARAM1(x)            (x ? 0x08 : 0x04)
  102 #define AN_PARAM2(x)            (x ? 0x0c : 0x06)
  103 #define AN_STATUS(x)            (x ? 0x10 : 0x08)
  104 #define AN_RESP0(x)             (x ? 0x14 : 0x0A)
  105 #define AN_RESP1(x)             (x ? 0x18 : 0x0C)
  106 #define AN_RESP2(x)             (x ? 0x1c : 0x0E)
  107 #define AN_LINKSTAT(x)          (x ? 0x20 : 0x10)
  108 
  109 /* Command register */
  110 #define AN_CMD_BUSY             0x8000 /* busy bit */
  111 #define AN_CMD_NO_ACK           0x0080 /* don't acknowledge command */
  112 #define AN_CMD_CODE_MASK        0x003F
  113 #define AN_CMD_QUAL_MASK        0x7F00
  114 
  115 /* Command codes */
  116 #define AN_CMD_NOOP             0x0000 /* no-op */
  117 #define AN_CMD_ENABLE           0x0001 /* enable */
  118 #define AN_CMD_DISABLE          0x0002 /* disable */
  119 #define AN_CMD_FORCE_SYNCLOSS   0x0003 /* force loss of sync */
  120 #define AN_CMD_FW_RESTART       0x0004 /* firmware restart */
  121 #define AN_CMD_HOST_SLEEP       0x0005
  122 #define AN_CMD_MAGIC_PKT        0x0006
  123 #define AN_CMD_READCFG          0x0008
  124 #define AN_CMD_SET_MODE         0x0009
  125 #define AN_CMD_ALLOC_MEM        0x000A /* allocate NIC memory */
  126 #define AN_CMD_TX               0x000B /* transmit */
  127 #define AN_CMD_DEALLOC_MEM      0x000C
  128 #define AN_CMD_NOOP2            0x0010
  129 #define AN_CMD_ALLOC_DESC       0x0020
  130 #define AN_CMD_ACCESS           0x0021
  131 #define AN_CMD_ALLOC_BUF        0x0028
  132 #define AN_CMD_PSP_NODES        0x0030
  133 #define AN_CMD_SET_PHYREG       0x003E
  134 #define AN_CMD_TX_TEST          0x003F
  135 #define AN_CMD_SLEEP            0x0085
  136 #define AN_CMD_SAVECFG          0x0108
  137 
  138 /*
  139  * MPI 350 DMA descriptor information
  140  */
  141 #define AN_DESCRIPTOR_TX        0x01
  142 #define AN_DESCRIPTOR_RX        0x02
  143 #define AN_DESCRIPTOR_TXCMP     0x04
  144 #define AN_DESCRIPTOR_HOSTWRITE 0x08
  145 #define AN_DESCRIPTOR_HOSTREAD  0x10
  146 #define AN_DESCRIPTOR_HOSTRW    0x20
  147 
  148 #define AN_MAX_RX_DESC 1
  149 #define AN_MAX_TX_DESC 1
  150 #define AN_HOSTBUFSIZ 1840
  151 
  152 struct an_card_rid_desc
  153 {
  154         unsigned        an_rid:16;
  155         unsigned        an_len:15;
  156         unsigned        an_valid:1;
  157         u_int64_t       an_phys;
  158 };
  159 
  160 struct an_card_rx_desc
  161 {
  162         unsigned        an_ctrl:15;
  163         unsigned        an_done:1;
  164         unsigned        an_len:15;
  165         unsigned        an_valid:1;
  166         u_int64_t       an_phys;
  167 };
  168 
  169 struct an_card_tx_desc
  170 {
  171         unsigned        an_offset:15;
  172         unsigned        an_eoc:1;
  173         unsigned        an_len:15;
  174         unsigned        an_valid:1;
  175         u_int64_t       an_phys;
  176 };
  177 
  178 #define AN_RID_BUFFER_SIZE      AN_MAX_DATALEN
  179 #define AN_RX_BUFFER_SIZE       AN_HOSTBUFSIZ
  180 #define AN_TX_BUFFER_SIZE       AN_HOSTBUFSIZ
  181 /*#define AN_HOST_DESC_OFFSET   0xC sort of works */
  182 #define AN_HOST_DESC_OFFSET     0x800
  183 #define AN_RX_DESC_OFFSET  (AN_HOST_DESC_OFFSET + \
  184     sizeof(struct an_card_rid_desc))
  185 #define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \
  186     (AN_MAX_RX_DESC * sizeof(struct an_card_rx_desc)))
  187 
  188 struct an_command {
  189         u_int16_t       an_cmd;
  190         u_int16_t       an_parm0;
  191         u_int16_t       an_parm1;
  192         u_int16_t       an_parm2;
  193 };
  194 
  195 struct an_reply {
  196         u_int16_t       an_status;
  197         u_int16_t       an_resp0;
  198         u_int16_t       an_resp1;
  199         u_int16_t       an_resp2;
  200 };
  201 
  202 /*
  203  * Reclaim qualifier bit, applicable to the
  204  * TX command.
  205  */
  206 #define AN_RECLAIM              0x0100 /* reclaim NIC memory */
  207 
  208 /*
  209  * ACCESS command qualifier bits.
  210  */
  211 #define AN_ACCESS_READ          0x0000
  212 #define AN_ACCESS_WRITE         0x0100
  213 
  214 /*
  215  * PROGRAM command qualifier bits.
  216  */
  217 #define AN_PROGRAM_DISABLE      0x0000
  218 #define AN_PROGRAM_ENABLE_RAM   0x0100
  219 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
  220 #define AN_PROGRAM_NVRAM        0x0300
  221 
  222 /* Status register values */
  223 #define AN_STAT_CMD_CODE        0x003F
  224 #define AN_STAT_CMD_RESULT      0x7F00
  225 
  226 /* Linkstat register */
  227 #define AN_LINKSTAT_ASSOCIATED          0x0400
  228 #define AN_LINKSTAT_AUTHFAIL            0x0300
  229 #define AN_LINKSTAT_ASSOC_FAIL          0x8400
  230 #define AN_LINKSTAT_DISASSOC            0x8200
  231 #define AN_LINKSTAT_DEAUTH              0x8100
  232 #define AN_LINKSTAT_SYNCLOST_TSF        0x8004
  233 #define AN_LINKSTAT_SYNCLOST_HOSTREQ    0x8003
  234 #define AN_LINKSTAT_SYNCLOST_AVGRETRY   0x8002
  235 #define AN_LINKSTAT_SYNCLOST_MAXRETRY   0x8001
  236 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
  237 
  238 /* memory handle management registers */
  239 #define AN_RX_FID               0x20
  240 #define AN_ALLOC_FID            0x22
  241 #define AN_TX_CMP_FID(x)        (x ? 0x1a : 0x24)
  242 
  243 /*
  244  * Buffer Access Path (BAP) registers.
  245  * These are I/O channels. I believe you can use each one for
  246  * any desired purpose independently of the other. In general
  247  * though, we use BAP1 for reading and writing LTV records and
  248  * reading received data frames, and BAP0 for writing transmit
  249  * frames. This is a convention though, not a rule.
  250  */
  251 #define AN_SEL0                 0x18
  252 #define AN_SEL1                 0x1A
  253 #define AN_OFF0                 0x1C
  254 #define AN_OFF1                 0x1E
  255 #define AN_DATA0                0x36
  256 #define AN_DATA1                0x38
  257 #define AN_BAP0                 AN_DATA0
  258 #define AN_BAP1                 AN_DATA1
  259 
  260 #define AN_OFF_BUSY             0x8000
  261 #define AN_OFF_ERR              0x4000
  262 #define AN_OFF_DONE             0x2000
  263 #define AN_OFF_DATAOFF          0x0FFF
  264 
  265 /* Event registers */
  266 #define AN_EVENT_STAT(x)        (x ? 0x60 : 0x30)       /* Event status */
  267 #define AN_INT_EN(x)            (x ? 0x64 : 0x32)       /* Interrupt enable/
  268                                                            disable */
  269 #define AN_EVENT_ACK(x)         (x ? 0x68 : 0x34)       /* Ack event */
  270 
  271 /* Events */
  272 #define AN_EV_CLR_STUCK_BUSY    0x4000  /* clear stuck busy bit */
  273 #define AN_EV_WAKEREQUEST       0x2000  /* awaken from PSP mode */
  274 #define AN_EV_MIC               0x1000  /* Message Integrity Check*/
  275 #define AN_EV_AWAKE             0x0100  /* station woke up from PSP mode*/
  276 #define AN_EV_LINKSTAT          0x0080  /* link status available */
  277 #define AN_EV_CMD               0x0010  /* command completed */
  278 #define AN_EV_ALLOC             0x0008  /* async alloc/reclaim completed */
  279 #define AN_EV_TX_CPY            0x0400
  280 #define AN_EV_TX_EXC            0x0004  /* async xmit completed with failure */
  281 #define AN_EV_TX                0x0002  /* async xmit completed successfully */
  282 #define AN_EV_RX                0x0001  /* async rx completed */
  283 
  284 #define AN_INTRS(x)     \
  285         ( x ? (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_TX_CPY|AN_EV_ALLOC \
  286                |AN_EV_LINKSTAT|AN_EV_MIC) \
  287           : \
  288               (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC \
  289                |AN_EV_LINKSTAT|AN_EV_MIC) \
  290               )
  291 
  292 /* Host software registers */
  293 #define AN_SW0(x)               (x ? 0x50 : 0x28)
  294 #define AN_SW1(x)               (x ? 0x54 : 0x2A)
  295 #define AN_SW2(x)               (x ? 0x58 : 0x2C)
  296 #define AN_SW3(x)               (x ? 0x5c : 0x2E)
  297 
  298 #define AN_CNTL                 0x14
  299 
  300 #define AN_CNTL_AUX_ENA         0xC000
  301 #define AN_CNTL_AUX_ENA_STAT    0xC000
  302 #define AN_CNTL_AUX_DIS_STAT    0x0000
  303 #define AN_CNTL_AUX_ENA_CNTL    0x8000
  304 #define AN_CNTL_AUX_DIS_CNTL    0x4000
  305 
  306 #define AN_AUX_PAGE             0x3A
  307 #define AN_AUX_OFFSET           0x3C
  308 #define AN_AUX_DATA             0x3E
  309 
  310 /*
  311  * Length, Type, Value (LTV) record definitions and RID values.
  312  */
  313 struct an_ltv_gen {
  314         u_int16_t               an_len;
  315         u_int16_t               an_type;
  316         u_int16_t               an_val;
  317 };
  318 
  319 #define AN_DEF_SSID_LEN         7
  320 #define AN_DEF_SSID             "tsunami"
  321 
  322 #define AN_RXGAP_MAX    8
  323 
  324 /*
  325  * Transmit frame structure.
  326  */
  327 struct an_txframe {
  328         u_int32_t               an_tx_sw;               /* 0x00 */
  329         u_int16_t               an_tx_status;           /* 0x04 */
  330         u_int16_t               an_tx_payload_len;      /* 0x06 */
  331         u_int16_t               an_tx_ctl;              /* 0x08 */
  332         u_int16_t               an_tx_assoc_id;         /* 0x0A */
  333         u_int16_t               an_tx_retry;            /* 0x0C */
  334         u_int8_t                an_tx_assoc_cnt;        /* 0x0E */
  335         u_int8_t                an_tx_rate;             /* 0x0F */
  336         u_int8_t                an_tx_max_long_retries; /* 0x10 */
  337         u_int8_t                an_tx_max_short_retries; /*0x11 */
  338         u_int8_t                an_rsvd0[2];            /* 0x12 */
  339         u_int16_t               an_frame_ctl;           /* 0x14 */
  340         u_int16_t               an_duration;            /* 0x16 */
  341         u_int8_t                an_addr1[6];            /* 0x18 */
  342         u_int8_t                an_addr2[6];            /* 0x1E */
  343         u_int8_t                an_addr3[6];            /* 0x24 */
  344         u_int16_t               an_seq_ctl;             /* 0x2A */
  345         u_int8_t                an_addr4[6];            /* 0x2C */
  346         u_int8_t                an_gaplen;              /* 0x32 */
  347 } __packed;
  348 
  349 struct an_rxframe_802_3 {
  350         u_int16_t               an_rx_802_3_status;     /* 0x34 */
  351         u_int16_t               an_rx_802_3_payload_len;/* 0x36 */
  352         u_int8_t                an_rx_dst_addr[6];      /* 0x38 */
  353         u_int8_t                an_rx_src_addr[6];      /* 0x3E */
  354 };
  355 #define AN_RXGAP_MAX    8
  356 
  357 
  358 struct an_txframe_802_3 {
  359 /*
  360  * Transmit 802.3 header structure.
  361  */
  362         u_int16_t               an_tx_802_3_status;     /* 0x34 */
  363         u_int16_t               an_tx_802_3_payload_len;/* 0x36 */
  364         u_int8_t                an_tx_dst_addr[6];      /* 0x38 */
  365         u_int8_t                an_tx_src_addr[6];      /* 0x3E */
  366 };
  367 
  368 #define AN_TXSTAT_EXCESS_RETRY  0x0002
  369 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
  370 #define AN_TXSTAT_AID_FAIL      0x0008
  371 #define AN_TXSTAT_MAC_DISABLED  0x0010
  372 #define AN_TXSTAT_ASSOC_LOST    0x0020
  373 
  374 #define AN_TXCTL_RSVD           0x0001
  375 #define AN_TXCTL_TXOK_INTR      0x0002
  376 #define AN_TXCTL_TXERR_INTR     0x0004
  377 #define AN_TXCTL_HEADER_TYPE    0x0008
  378 #define AN_TXCTL_PAYLOAD_TYPE   0x0010
  379 #define AN_TXCTL_NORELEASE      0x0020
  380 #define AN_TXCTL_NORETRIES      0x0040
  381 #define AN_TXCTL_CLEAR_AID      0x0080
  382 #define AN_TXCTL_STRICT_ORDER   0x0100
  383 #define AN_TXCTL_USE_RTS        0x0200
  384 
  385 #define AN_HEADERTYPE_8023      0x0000
  386 #define AN_HEADERTYPE_80211     0x0008
  387 
  388 #define AN_PAYLOADTYPE_ETHER    0x0000
  389 #define AN_PAYLOADTYPE_LLC      0x0010
  390 
  391 #define AN_TXCTL_80211          (AN_HEADERTYPE_80211|AN_PAYLOADTYPE_LLC)
  392 
  393 #define AN_TXCTL_8023           (AN_HEADERTYPE_8023|AN_PAYLOADTYPE_ETHER)
  394 
  395 /*
  396  * Additions to transmit control bits for MPI350
  397  */
  398 #define AN_TXCTL_HW(x)  \
  399         ( x ? (AN_TXCTL_NORELEASE) \
  400           : \
  401               (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_TXCTL_NORELEASE) \
  402               )
  403 
  404 #define AN_TXGAP_80211          0
  405 #define AN_TXGAP_8023           0
  406 
  407 struct an_802_3_hdr {
  408         u_int16_t               an_8023_status;
  409         u_int16_t               an_8023_payload_len;
  410         u_int8_t                an_8023_dst_addr[6];
  411         u_int8_t                an_8023_src_addr[6];
  412         u_int16_t               an_8023_dat[3]; /* SNAP header */
  413         u_int16_t               an_8023_type;
  414 };
  415 
  416 struct an_snap_hdr {
  417         u_int16_t               an_snap_dat[3]; /* SNAP header */
  418         u_int16_t               an_snap_type;
  419 };
  420 
  421 struct an_dma_alloc {
  422         u_int32_t               an_dma_paddr;
  423         caddr_t                 an_dma_vaddr;
  424         bus_dmamap_t            an_dma_map;
  425         bus_dma_segment_t       an_dma_seg;
  426         bus_size_t              an_dma_size;
  427         int                     an_dma_nseg;
  428 };
  429 
  430 #define AN_TX_RING_CNT          4
  431 #define AN_INC(x, y)            (x) = (x + 1) % y
  432 
  433 struct an_tx_ring_data {
  434         u_int16_t               an_tx_fids[AN_TX_RING_CNT];
  435         u_int16_t               an_tx_ring[AN_TX_RING_CNT];
  436         int                     an_tx_prod;
  437         int                     an_tx_cons;
  438         int                     an_tx_empty;
  439 };
  440 
  441 struct an_softc {
  442         struct ifnet            *an_ifp;
  443 
  444         int     port_rid;       /* resource id for port range */
  445         struct resource* port_res; /* resource for port range */
  446         int     mem_rid;        /* resource id for memory range */
  447         int     mem_used;       /* nonzero if memory used */
  448         struct resource* mem_res; /* resource for memory range */
  449         int     mem_aux_rid;    /* resource id for memory range */
  450         int     mem_aux_used;   /* nonzero if memory used */
  451         struct resource* mem_aux_res; /* resource for memory range */
  452         int     irq_rid;        /* resource id for irq */
  453         void*   irq_handle;     /* handle for irq handler */
  454         struct resource* irq_res; /* resource for irq */
  455 
  456         bus_space_handle_t      an_mem_aux_bhandle;
  457         bus_space_tag_t         an_mem_aux_btag;
  458         bus_dma_tag_t           an_dtag;
  459         struct an_ltv_genconfig an_config;
  460         struct an_ltv_caps      an_caps;
  461         struct an_ltv_ssidlist_new      an_ssidlist;
  462         struct an_ltv_aplist    an_aplist;
  463         struct an_ltv_key       an_temp_keys[4];
  464         int                     an_tx_rate;
  465         int                     an_rxmode;
  466         int                     an_gone;
  467         int                     an_if_flags;
  468         u_int8_t                an_txbuf[1536];
  469         struct an_tx_ring_data  an_rdata;
  470         struct an_ltv_stats     an_stats;
  471         struct an_ltv_status    an_status;
  472         u_int8_t                an_associated;
  473 #ifdef ANCACHE
  474         int                     an_sigitems;
  475         struct an_sigcache      an_sigcache[MAXANCACHE];
  476         int                     an_nextitem;
  477         int                     an_have_rssimap;
  478         struct an_ltv_rssi_map  an_rssimap;
  479 #endif
  480         struct callout          an_stat_ch;
  481         struct mtx              an_mtx;
  482         device_t                an_dev;
  483         struct ifmedia          an_ifmedia;
  484         int                     an_monitor;
  485         int                     an_was_monitor;
  486         int                     an_timer;
  487         u_char                  buf_802_11[MCLBYTES];
  488         struct an_req           areq;
  489         unsigned short*         an_flash_buffer;
  490         int                     mpi350;
  491         struct an_dma_alloc     an_rid_buffer;
  492         struct an_dma_alloc     an_rx_buffer[AN_MAX_RX_DESC];
  493         struct an_dma_alloc     an_tx_buffer[AN_MAX_TX_DESC];
  494 };
  495 
  496 #define AN_LOCK(_sc)            mtx_lock(&(_sc)->an_mtx)
  497 #define AN_UNLOCK(_sc)          mtx_unlock(&(_sc)->an_mtx)
  498 #define AN_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->an_mtx, MA_OWNED)
  499 
  500 void    an_release_resources    (device_t);
  501 int     an_alloc_port           (device_t, int, int);
  502 int     an_alloc_memory         (device_t, int, int);
  503 int     an_alloc_aux_memory     (device_t, int, int);
  504 int     an_alloc_irq            (device_t, int, int);
  505 int     an_probe        (device_t);
  506 int     an_shutdown     (device_t);
  507 void    an_resume       (device_t);
  508 int     an_attach               (struct an_softc *, int);
  509 int     an_detach       (device_t);
  510 void    an_stop         (struct an_softc *);
  511 
  512 driver_intr_t   an_intr;
  513 
  514 #define AN_802_3_OFFSET         0x2E
  515 #define AN_802_11_OFFSET        0x44
  516 #define AN_802_11_OFFSET_RAW    0x3C
  517 
  518 #define AN_STAT_BADCRC          0x0001
  519 #define AN_STAT_UNDECRYPTABLE   0x0002
  520 #define AN_STAT_ERRSTAT         0x0003
  521 #define AN_STAT_MAC_PORT        0x0700
  522 #define AN_STAT_1042            0x2000  /* RFC1042 encoded */
  523 #define AN_STAT_TUNNEL          0x4000  /* Bridge-tunnel encoded */
  524 #define AN_STAT_WMP_MSG         0x6000  /* WaveLAN-II management protocol */
  525 #define AN_RXSTAT_MSG_TYPE      0xE000
  526 
  527 #define AN_ENC_TX_802_3         0x00
  528 #define AN_ENC_TX_802_11        0x11
  529 #define AN_ENC_TX_E_II          0x0E
  530 
  531 #define AN_ENC_TX_1042          0x00
  532 #define AN_ENC_TX_TUNNEL        0xF8
  533 
  534 #define AN_TXCNTL_MACPORT       0x00FF
  535 #define AN_TXCNTL_STRUCTTYPE    0xFF00
  536 
  537 /*
  538  * SNAP (sub-network access protocol) constants for transmission
  539  * of IP datagrams over IEEE 802 networks, taken from RFC1042.
  540  * We need these for the LLC/SNAP header fields in the TX/RX frame
  541  * structure.
  542  */
  543 #define AN_SNAP_K1              0xaa    /* assigned global SAP for SNAP */
  544 #define AN_SNAP_K2              0x00
  545 #define AN_SNAP_CONTROL         0x03    /* unnumbered information format */
  546 #define AN_SNAP_WORD0           (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
  547 #define AN_SNAP_WORD1           (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
  548 #define AN_SNAPHDR_LEN          0x6

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