The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/an/if_anreg.h

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    1 /*
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.0/sys/dev/an/if_anreg.h 103870 2002-09-23 18:54:32Z alfred $
   33  */
   34 
   35 #define AN_TIMEOUT      65536
   36 
   37 /* Default network name: <empty string> */
   38 #define AN_DEFAULT_NETNAME      ""
   39 
   40 /* The nodename must be less than 16 bytes */
   41 #define AN_DEFAULT_NODENAME     "FreeBSD"
   42 
   43 #define AN_DEFAULT_IBSS         "FreeBSD IBSS"
   44 
   45 /*
   46  * register space access macros
   47  */
   48 #define CSR_WRITE_2(sc, reg, val)       \
   49         bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
   50 
   51 #define CSR_READ_2(sc, reg)             \
   52         bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
   53 
   54 #define CSR_WRITE_1(sc, reg, val)       \
   55         bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
   56 
   57 #define CSR_READ_1(sc, reg)             \
   58         bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
   59 
   60 /*
   61  * Size of Aironet I/O space.
   62  */
   63 #define AN_IOSIZ                0x40
   64 
   65 /*
   66  * Hermes register definitions and what little I know about them.
   67  */
   68 
   69 /* Hermes command/status registers. */
   70 #define AN_COMMAND              0x00
   71 #define AN_PARAM0               0x02
   72 #define AN_PARAM1               0x04
   73 #define AN_PARAM2               0x06
   74 #define AN_STATUS               0x08
   75 #define AN_RESP0                0x0A
   76 #define AN_RESP1                0x0C
   77 #define AN_RESP2                0x0E
   78 #define AN_LINKSTAT             0x10
   79 
   80 /* Command register */
   81 #define AN_CMD_BUSY             0x8000 /* busy bit */
   82 #define AN_CMD_NO_ACK           0x0080 /* don't acknowledge command */
   83 #define AN_CMD_CODE_MASK        0x003F
   84 #define AN_CMD_QUAL_MASK        0x7F00
   85 
   86 /* Command codes */
   87 #define AN_CMD_NOOP             0x0000 /* no-op */
   88 #define AN_CMD_ENABLE           0x0001 /* enable */
   89 #define AN_CMD_DISABLE          0x0002 /* disable */
   90 #define AN_CMD_FORCE_SYNCLOSS   0x0003 /* force loss of sync */
   91 #define AN_CMD_FW_RESTART       0x0004 /* firmware resrart */
   92 #define AN_CMD_HOST_SLEEP       0x0005
   93 #define AN_CMD_MAGIC_PKT        0x0006
   94 #define AN_CMD_READCFG          0x0008
   95 #define AN_CMD_SET_MODE         0x0009
   96 #define AN_CMD_ALLOC_MEM        0x000A /* allocate NIC memory */
   97 #define AN_CMD_TX               0x000B /* transmit */
   98 #define AN_CMD_DEALLOC_MEM      0x000C
   99 #define AN_CMD_NOOP2            0x0010
  100 #define AN_CMD_ACCESS           0x0021
  101 #define AN_CMD_ALLOC_BUF        0x0028
  102 #define AN_CMD_PSP_NODES        0x0030
  103 #define AN_CMD_SET_PHYREG       0x003E
  104 #define AN_CMD_TX_TEST          0x003F
  105 #define AN_CMD_SLEEP            0x0085
  106 #define AN_CMD_SAVECFG          0x0108
  107 
  108 /*
  109  * Reclaim qualifier bit, applicable to the
  110  * TX command.
  111  */
  112 #define AN_RECLAIM              0x0100 /* reclaim NIC memory */
  113 
  114 /*
  115  * ACCESS command qualifier bits.
  116  */
  117 #define AN_ACCESS_READ          0x0000
  118 #define AN_ACCESS_WRITE         0x0100
  119 
  120 /*
  121  * PROGRAM command qualifier bits.
  122  */
  123 #define AN_PROGRAM_DISABLE      0x0000
  124 #define AN_PROGRAM_ENABLE_RAM   0x0100
  125 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
  126 #define AN_PROGRAM_NVRAM        0x0300
  127 
  128 /* Status register values */
  129 #define AN_STAT_CMD_CODE        0x003F
  130 #define AN_STAT_CMD_RESULT      0x7F00
  131 
  132 /* Linkstat register */
  133 #define AN_LINKSTAT_ASSOCIATED          0x0400
  134 #define AN_LINKSTAT_AUTHFAIL            0x0300
  135 #define AN_LINKSTAT_ASSOC_FAIL          0x8400
  136 #define AN_LINKSTAT_DISASSOC            0x8200
  137 #define AN_LINKSTAT_DEAUTH              0x8100
  138 #define AN_LINKSTAT_SYNCLOST_TSF        0x8004
  139 #define AN_LINKSTAT_SYNCLOST_HOSTREQ    0x8003
  140 #define AN_LINKSTAT_SYNCLOST_AVGRETRY   0x8002
  141 #define AN_LINKSTAT_SYNCLOST_MAXRETRY   0x8001
  142 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
  143 
  144 /* memory handle management registers */
  145 #define AN_RX_FID               0x20
  146 #define AN_ALLOC_FID            0x22
  147 #define AN_TX_CMP_FID           0x24
  148 
  149 /*
  150  * Buffer Access Path (BAP) registers.
  151  * These are I/O channels. I believe you can use each one for
  152  * any desired purpose independently of the other. In general
  153  * though, we use BAP1 for reading and writing LTV records and
  154  * reading received data frames, and BAP0 for writing transmit
  155  * frames. This is a convention though, not a rule.
  156  */
  157 #define AN_SEL0                 0x18
  158 #define AN_SEL1                 0x1A
  159 #define AN_OFF0                 0x1C
  160 #define AN_OFF1                 0x1E
  161 #define AN_DATA0                0x36
  162 #define AN_DATA1                0x38
  163 #define AN_BAP0                 AN_DATA0
  164 #define AN_BAP1                 AN_DATA1
  165 
  166 #define AN_OFF_BUSY             0x8000
  167 #define AN_OFF_ERR              0x4000
  168 #define AN_OFF_DONE             0x2000
  169 #define AN_OFF_DATAOFF          0x0FFF
  170 
  171 /* Event registers */
  172 #define AN_EVENT_STAT           0x30    /* Event status */
  173 #define AN_INT_EN               0x32    /* Interrupt enable/disable */
  174 #define AN_EVENT_ACK            0x34    /* Ack event */
  175 
  176 /* Events */
  177 #define AN_EV_CLR_STUCK_BUSY    0x4000  /* clear stuck busy bit */
  178 #define AN_EV_WAKEREQUEST       0x2000  /* awaken from PSP mode */
  179 #define AN_EV_AWAKE             0x0100  /* station woke up from PSP mode*/
  180 #define AN_EV_LINKSTAT          0x0080  /* link status available */
  181 #define AN_EV_CMD               0x0010  /* command completed */
  182 #define AN_EV_ALLOC             0x0008  /* async alloc/reclaim completed */
  183 #define AN_EV_TX_EXC            0x0004  /* async xmit completed with failure */
  184 #define AN_EV_TX                0x0002  /* async xmit completed succesfully */
  185 #define AN_EV_RX                0x0001  /* async rx completed */
  186 
  187 #define AN_INTRS        \
  188         (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT)
  189 
  190 /* Host software registers */
  191 #define AN_SW0                  0x28
  192 #define AN_SW1                  0x2A
  193 #define AN_SW2                  0x2C
  194 #define AN_SW3                  0x2E
  195 
  196 #define AN_CNTL                 0x14
  197 
  198 #define AN_CNTL_AUX_ENA         0xC000
  199 #define AN_CNTL_AUX_ENA_STAT    0xC000
  200 #define AN_CNTL_AUX_DIS_STAT    0x0000
  201 #define AN_CNTL_AUX_ENA_CNTL    0x8000
  202 #define AN_CNTL_AUX_DIS_CNTL    0x4000
  203 
  204 #define AN_AUX_PAGE             0x3A
  205 #define AN_AUX_OFFSET           0x3C
  206 #define AN_AUX_DATA             0x3E
  207 
  208 /*
  209  * Length, Type, Value (LTV) record definitions and RID values.
  210  */
  211 struct an_ltv_gen {
  212         u_int16_t               an_len;
  213         u_int16_t               an_type;
  214         u_int16_t               an_val;
  215 };
  216 
  217 #define AN_DEF_SSID_LEN         7
  218 #define AN_DEF_SSID             "tsunami"
  219 
  220 #define AN_RXGAP_MAX    8
  221 
  222 /*
  223  * Transmit frame structure.
  224  */
  225 struct an_txframe {
  226         u_int32_t               an_tx_sw;               /* 0x00 */
  227         u_int16_t               an_tx_status;           /* 0x04 */
  228         u_int16_t               an_tx_payload_len;      /* 0x06 */
  229         u_int16_t               an_tx_ctl;              /* 0x08 */
  230         u_int16_t               an_tx_assoc_id;         /* 0x0A */
  231         u_int16_t               an_tx_retry;            /* 0x0C */
  232         u_int8_t                an_tx_assoc_cnt;        /* 0x0E */
  233         u_int8_t                an_tx_rate;             /* 0x0F */
  234         u_int8_t                an_tx_max_long_retries; /* 0x10 */
  235         u_int8_t                an_tx_max_short_retries; /*0x11 */
  236         u_int8_t                an_rsvd0[2];            /* 0x12 */
  237         u_int16_t               an_frame_ctl;           /* 0x14 */
  238         u_int16_t               an_duration;            /* 0x16 */
  239         u_int8_t                an_addr1[6];            /* 0x18 */
  240         u_int8_t                an_addr2[6];            /* 0x1E */
  241         u_int8_t                an_addr3[6];            /* 0x24 */
  242         u_int16_t               an_seq_ctl;             /* 0x2A */
  243         u_int8_t                an_addr4[6];            /* 0x2C */
  244         u_int8_t                an_gaplen;              /* 0x32 */
  245 } __packed;
  246 
  247 struct an_rxframe_802_3 {
  248         u_int16_t               an_rx_802_3_status;     /* 0x34 */
  249         u_int16_t               an_rx_802_3_payload_len;/* 0x36 */
  250         u_int8_t                an_rx_dst_addr[6];      /* 0x38 */
  251         u_int8_t                an_rx_src_addr[6];      /* 0x3E */
  252 };
  253 #define AN_RXGAP_MAX    8
  254 
  255 
  256 struct an_txframe_802_3 {
  257 /*
  258  * Transmit 802.3 header structure.
  259  */
  260         u_int16_t               an_tx_802_3_status;     /* 0x34 */
  261         u_int16_t               an_tx_802_3_payload_len;/* 0x36 */
  262         u_int8_t                an_tx_dst_addr[6];      /* 0x38 */
  263         u_int8_t                an_tx_src_addr[6];      /* 0x3E */
  264 };
  265 
  266 #define AN_TXSTAT_EXCESS_RETRY  0x0002
  267 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
  268 #define AN_TXSTAT_AID_FAIL      0x0008
  269 #define AN_TXSTAT_MAC_DISABLED  0x0010
  270 #define AN_TXSTAT_ASSOC_LOST    0x0020
  271 
  272 #define AN_TXCTL_RSVD           0x0001
  273 #define AN_TXCTL_TXOK_INTR      0x0002
  274 #define AN_TXCTL_TXERR_INTR     0x0004
  275 #define AN_TXCTL_HEADER_TYPE    0x0008
  276 #define AN_TXCTL_PAYLOAD_TYPE   0x0010
  277 #define AN_TXCTL_NORELEASE      0x0020
  278 #define AN_TXCTL_NORETRIES      0x0040
  279 #define AN_TXCTL_CLEAR_AID      0x0080
  280 #define AN_TXCTL_STRICT_ORDER   0x0100
  281 #define AN_TXCTL_USE_RTS        0x0200
  282 
  283 #define AN_HEADERTYPE_8023      0x0000
  284 #define AN_HEADERTYPE_80211     0x0008
  285 
  286 #define AN_PAYLOADTYPE_ETHER    0x0000
  287 #define AN_PAYLOADTYPE_LLC      0x0010
  288 
  289 #define AN_TXCTL_80211  \
  290         (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211|    \
  291         AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE)
  292 
  293 #define AN_TXCTL_8023   \
  294         (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023|     \
  295         AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE)
  296 
  297 #define AN_TXGAP_80211          0
  298 #define AN_TXGAP_8023           0
  299 
  300 struct an_802_3_hdr {
  301         u_int16_t               an_8023_status;
  302         u_int16_t               an_8023_payload_len;
  303         u_int8_t                an_8023_dst_addr[6];
  304         u_int8_t                an_8023_src_addr[6];
  305         u_int16_t               an_8023_dat[3]; /* SNAP header */
  306         u_int16_t               an_8023_type;
  307 };
  308 
  309 struct an_snap_hdr {
  310         u_int16_t               an_snap_dat[3]; /* SNAP header */
  311         u_int16_t               an_snap_type;
  312 };
  313 
  314 #define AN_TX_RING_CNT          4
  315 #define AN_INC(x, y)            (x) = (x + 1) % y
  316 
  317 struct an_tx_ring_data {
  318         u_int16_t               an_tx_fids[AN_TX_RING_CNT];
  319         u_int16_t               an_tx_ring[AN_TX_RING_CNT];
  320         int                     an_tx_prod;
  321         int                     an_tx_cons;
  322 };
  323 
  324 struct an_softc {
  325         struct arpcom           arpcom;
  326 
  327         int                     an_unit;
  328 
  329         int     port_rid;       /* resource id for port range */
  330         struct resource* port_res; /* resource for port range */
  331         int     irq_rid;        /* resource id for irq */
  332         struct resource* irq_res; /* resource for irq */
  333         void*   irq_handle;     /* handle for irq handler */
  334 
  335         bus_space_handle_t      an_bhandle_p;
  336         bus_space_handle_t      an_bhandle;
  337         bus_space_tag_t         an_btag;
  338         struct an_ltv_genconfig an_config;
  339         struct an_ltv_caps      an_caps;
  340         struct an_ltv_ssidlist  an_ssidlist;
  341         struct an_ltv_aplist    an_aplist;
  342         struct an_ltv_key       an_temp_keys;
  343         struct an_ltv_key       an_perm_keys;
  344         int                     an_tx_rate;
  345         int                     an_rxmode;
  346         int                     an_gone;
  347         int                     an_if_flags;
  348         u_int8_t                an_txbuf[1536];
  349         struct an_tx_ring_data  an_rdata;
  350         struct an_ltv_stats     an_stats;
  351         struct an_ltv_status    an_status;
  352         u_int8_t                an_associated;
  353 #ifdef ANCACHE
  354         int                     an_sigitems;
  355         struct an_sigcache      an_sigcache[MAXANCACHE];
  356         int                     an_nextitem;
  357 #endif
  358         struct callout_handle   an_stat_ch;
  359         struct mtx              an_mtx;
  360         device_t                an_dev;
  361         struct ifmedia          an_ifmedia;
  362         int                     an_monitor;
  363         int                     an_was_monitor;
  364         u_char                  buf_802_11[MCLBYTES];
  365         struct an_req           areq;
  366 };
  367 
  368 #define AN_LOCK(_sc)            mtx_lock(&(_sc)->an_mtx)
  369 #define AN_UNLOCK(_sc)          mtx_unlock(&(_sc)->an_mtx)
  370 
  371 void    an_release_resources    (device_t);
  372 int     an_alloc_port           (device_t, int, int);
  373 int     an_alloc_memory         (device_t, int, int);
  374 int     an_alloc_irq            (device_t, int, int);
  375 int     an_probe        (device_t);
  376 void    an_shutdown     (device_t);
  377 int     an_attach               (struct an_softc *, int, int);
  378 void    an_stop         (struct an_softc *);
  379 
  380 driver_intr_t   an_intr;
  381 
  382 #define AN_802_3_OFFSET         0x2E
  383 #define AN_802_11_OFFSET        0x44
  384 #define AN_802_11_OFFSET_RAW    0x3C
  385 
  386 #define AN_STAT_BADCRC          0x0001
  387 #define AN_STAT_UNDECRYPTABLE   0x0002
  388 #define AN_STAT_ERRSTAT         0x0003
  389 #define AN_STAT_MAC_PORT        0x0700
  390 #define AN_STAT_1042            0x2000  /* RFC1042 encoded */
  391 #define AN_STAT_TUNNEL          0x4000  /* Bridge-tunnel encoded */
  392 #define AN_STAT_WMP_MSG         0x6000  /* WaveLAN-II management protocol */
  393 #define AN_RXSTAT_MSG_TYPE      0xE000
  394 
  395 #define AN_ENC_TX_802_3         0x00
  396 #define AN_ENC_TX_802_11        0x11
  397 #define AN_ENC_TX_E_II          0x0E
  398 
  399 #define AN_ENC_TX_1042          0x00
  400 #define AN_ENC_TX_TUNNEL        0xF8
  401 
  402 #define AN_TXCNTL_MACPORT       0x00FF
  403 #define AN_TXCNTL_STRUCTTYPE    0xFF00
  404 
  405 /*
  406  * SNAP (sub-network access protocol) constants for transmission
  407  * of IP datagrams over IEEE 802 networks, taken from RFC1042.
  408  * We need these for the LLC/SNAP header fields in the TX/RX frame
  409  * structure.
  410  */
  411 #define AN_SNAP_K1              0xaa    /* assigned global SAP for SNAP */
  412 #define AN_SNAP_K2              0x00
  413 #define AN_SNAP_CONTROL         0x03    /* unnumbered information format */
  414 #define AN_SNAP_WORD0           (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
  415 #define AN_SNAP_WORD1           (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
  416 #define AN_SNAPHDR_LEN          0x6

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