FreeBSD/Linux Kernel Cross Reference
sys/dev/an/if_anreg.h
1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 #define AN_TIMEOUT 65536
36
37 /* Default network name: <empty string> */
38 #define AN_DEFAULT_NETNAME ""
39
40 /* The nodename must be less than 16 bytes */
41 #define AN_DEFAULT_NODENAME "FreeBSD"
42
43 #define AN_DEFAULT_IBSS "FreeBSD IBSS"
44
45 /*
46 * register space access macros
47 */
48 #define CSR_WRITE_2(sc, reg, val) \
49 bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
50
51 #define CSR_READ_2(sc, reg) \
52 bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
53
54 #define CSR_WRITE_1(sc, reg, val) \
55 bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
56
57 #define CSR_READ_1(sc, reg) \
58 bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
59
60 /*
61 * memory space access macros
62 */
63 #define CSR_MEM_WRITE_2(sc, reg, val) \
64 bus_space_write_2(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
65
66 #define CSR_MEM_READ_2(sc, reg) \
67 bus_space_read_2(sc->an_mem_btag, sc->an_mem_bhandle, reg)
68
69 #define CSR_MEM_WRITE_1(sc, reg, val) \
70 bus_space_write_1(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
71
72 #define CSR_MEM_READ_1(sc, reg) \
73 bus_space_read_1(sc->an_mem_btag, sc->an_mem_bhandle, reg)
74
75 /*
76 * aux. memory space access macros
77 */
78 #define CSR_MEM_AUX_WRITE_4(sc, reg, val) \
79 bus_space_write_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
80
81 #define CSR_MEM_AUX_READ_4(sc, reg) \
82 bus_space_read_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
83
84 #define CSR_MEM_AUX_WRITE_1(sc, reg, val) \
85 bus_space_write_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
86
87 #define CSR_MEM_AUX_READ_1(sc, reg) \
88 bus_space_read_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
89
90 /*
91 * Size of Aironet I/O space.
92 */
93 #define AN_IOSIZ 0x40
94
95 /*
96 * Size of aux. memory space ... probably not needed DJA
97 */
98 #define AN_AUX_MEM_SIZE (256 * 1024)
99
100 /*
101 * Hermes register definitions and what little I know about them.
102 */
103
104 /* Hermes command/status registers. */
105 #define AN_COMMAND(x) (x ? 0x00 : 0x00)
106 #define AN_PARAM0(x) (x ? 0x04 : 0x02)
107 #define AN_PARAM1(x) (x ? 0x08 : 0x04)
108 #define AN_PARAM2(x) (x ? 0x0c : 0x06)
109 #define AN_STATUS(x) (x ? 0x10 : 0x08)
110 #define AN_RESP0(x) (x ? 0x14 : 0x0A)
111 #define AN_RESP1(x) (x ? 0x18 : 0x0C)
112 #define AN_RESP2(x) (x ? 0x1c : 0x0E)
113 #define AN_LINKSTAT(x) (x ? 0x20 : 0x10)
114
115 /* Command register */
116 #define AN_CMD_BUSY 0x8000 /* busy bit */
117 #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */
118 #define AN_CMD_CODE_MASK 0x003F
119 #define AN_CMD_QUAL_MASK 0x7F00
120
121 /* Command codes */
122 #define AN_CMD_NOOP 0x0000 /* no-op */
123 #define AN_CMD_ENABLE 0x0001 /* enable */
124 #define AN_CMD_DISABLE 0x0002 /* disable */
125 #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */
126 #define AN_CMD_FW_RESTART 0x0004 /* firmware restart */
127 #define AN_CMD_HOST_SLEEP 0x0005
128 #define AN_CMD_MAGIC_PKT 0x0006
129 #define AN_CMD_READCFG 0x0008
130 #define AN_CMD_SET_MODE 0x0009
131 #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
132 #define AN_CMD_TX 0x000B /* transmit */
133 #define AN_CMD_DEALLOC_MEM 0x000C
134 #define AN_CMD_NOOP2 0x0010
135 #define AN_CMD_ALLOC_DESC 0x0020
136 #define AN_CMD_ACCESS 0x0021
137 #define AN_CMD_ALLOC_BUF 0x0028
138 #define AN_CMD_PSP_NODES 0x0030
139 #define AN_CMD_SET_PHYREG 0x003E
140 #define AN_CMD_TX_TEST 0x003F
141 #define AN_CMD_SLEEP 0x0085
142 #define AN_CMD_SAVECFG 0x0108
143
144 /*
145 * MPI 350 DMA descriptor information
146 */
147 #define AN_DESCRIPTOR_TX 0x01
148 #define AN_DESCRIPTOR_RX 0x02
149 #define AN_DESCRIPTOR_TXCMP 0x04
150 #define AN_DESCRIPTOR_HOSTWRITE 0x08
151 #define AN_DESCRIPTOR_HOSTREAD 0x10
152 #define AN_DESCRIPTOR_HOSTRW 0x20
153
154 #define AN_MAX_RX_DESC 1
155 #define AN_MAX_TX_DESC 1
156 #define AN_HOSTBUFSIZ 1840
157
158 struct an_card_rid_desc
159 {
160 unsigned an_rid:16;
161 unsigned an_len:15;
162 unsigned an_valid:1;
163 u_int64_t an_phys;
164 };
165
166 struct an_card_rx_desc
167 {
168 unsigned an_ctrl:15;
169 unsigned an_done:1;
170 unsigned an_len:15;
171 unsigned an_valid:1;
172 u_int64_t an_phys;
173 };
174
175 struct an_card_tx_desc
176 {
177 unsigned an_offset:15;
178 unsigned an_eoc:1;
179 unsigned an_len:15;
180 unsigned an_valid:1;
181 u_int64_t an_phys;
182 };
183
184 #define AN_RID_BUFFER_SIZE AN_MAX_DATALEN
185 #define AN_RX_BUFFER_SIZE AN_HOSTBUFSIZ
186 #define AN_TX_BUFFER_SIZE AN_HOSTBUFSIZ
187 /*#define AN_HOST_DESC_OFFSET 0xC sort of works */
188 #define AN_HOST_DESC_OFFSET 0x800
189 #define AN_RX_DESC_OFFSET (AN_HOST_DESC_OFFSET + \
190 sizeof(struct an_card_rid_desc))
191 #define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \
192 (AN_MAX_RX_DESC * sizeof(struct an_card_rx_desc)))
193
194 struct an_command {
195 u_int16_t an_cmd;
196 u_int16_t an_parm0;
197 u_int16_t an_parm1;
198 u_int16_t an_parm2;
199 };
200
201 struct an_reply {
202 u_int16_t an_status;
203 u_int16_t an_resp0;
204 u_int16_t an_resp1;
205 u_int16_t an_resp2;
206 };
207
208 /*
209 * Reclaim qualifier bit, applicable to the
210 * TX command.
211 */
212 #define AN_RECLAIM 0x0100 /* reclaim NIC memory */
213
214 /*
215 * ACCESS command qualifier bits.
216 */
217 #define AN_ACCESS_READ 0x0000
218 #define AN_ACCESS_WRITE 0x0100
219
220 /*
221 * PROGRAM command qualifier bits.
222 */
223 #define AN_PROGRAM_DISABLE 0x0000
224 #define AN_PROGRAM_ENABLE_RAM 0x0100
225 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
226 #define AN_PROGRAM_NVRAM 0x0300
227
228 /* Status register values */
229 #define AN_STAT_CMD_CODE 0x003F
230 #define AN_STAT_CMD_RESULT 0x7F00
231
232 /* Linkstat register */
233 #define AN_LINKSTAT_ASSOCIATED 0x0400
234 #define AN_LINKSTAT_AUTHFAIL 0x0300
235 #define AN_LINKSTAT_ASSOC_FAIL 0x8400
236 #define AN_LINKSTAT_DISASSOC 0x8200
237 #define AN_LINKSTAT_DEAUTH 0x8100
238 #define AN_LINKSTAT_SYNCLOST_TSF 0x8004
239 #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003
240 #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002
241 #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001
242 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
243
244 /* memory handle management registers */
245 #define AN_RX_FID 0x20
246 #define AN_ALLOC_FID 0x22
247 #define AN_TX_CMP_FID(x) (x ? 0x1a : 0x24)
248
249 /*
250 * Buffer Access Path (BAP) registers.
251 * These are I/O channels. I believe you can use each one for
252 * any desired purpose independently of the other. In general
253 * though, we use BAP1 for reading and writing LTV records and
254 * reading received data frames, and BAP0 for writing transmit
255 * frames. This is a convention though, not a rule.
256 */
257 #define AN_SEL0 0x18
258 #define AN_SEL1 0x1A
259 #define AN_OFF0 0x1C
260 #define AN_OFF1 0x1E
261 #define AN_DATA0 0x36
262 #define AN_DATA1 0x38
263 #define AN_BAP0 AN_DATA0
264 #define AN_BAP1 AN_DATA1
265
266 #define AN_OFF_BUSY 0x8000
267 #define AN_OFF_ERR 0x4000
268 #define AN_OFF_DONE 0x2000
269 #define AN_OFF_DATAOFF 0x0FFF
270
271 /* Event registers */
272 #define AN_EVENT_STAT(x) (x ? 0x60 : 0x30) /* Event status */
273 #define AN_INT_EN(x) (x ? 0x64 : 0x32) /* Interrupt enable/
274 disable */
275 #define AN_EVENT_ACK(x) (x ? 0x68 : 0x34) /* Ack event */
276
277 /* Events */
278 #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */
279 #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */
280 #define AN_EV_MIC 0x1000 /* Message Integrity Check*/
281 #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/
282 #define AN_EV_LINKSTAT 0x0080 /* link status available */
283 #define AN_EV_CMD 0x0010 /* command completed */
284 #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
285 #define AN_EV_TX_CPY 0x0400
286 #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */
287 #define AN_EV_TX 0x0002 /* async xmit completed succesfully */
288 #define AN_EV_RX 0x0001 /* async rx completed */
289
290 #define AN_INTRS(x) \
291 ( x ? (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_TX_CPY|AN_EV_ALLOC \
292 |AN_EV_LINKSTAT|AN_EV_MIC) \
293 : \
294 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC \
295 |AN_EV_LINKSTAT|AN_EV_MIC) \
296 )
297
298 /* Host software registers */
299 #define AN_SW0(x) (x ? 0x50 : 0x28)
300 #define AN_SW1(x) (x ? 0x54 : 0x2A)
301 #define AN_SW2(x) (x ? 0x58 : 0x2C)
302 #define AN_SW3(x) (x ? 0x5c : 0x2E)
303
304 #define AN_CNTL 0x14
305
306 #define AN_CNTL_AUX_ENA 0xC000
307 #define AN_CNTL_AUX_ENA_STAT 0xC000
308 #define AN_CNTL_AUX_DIS_STAT 0x0000
309 #define AN_CNTL_AUX_ENA_CNTL 0x8000
310 #define AN_CNTL_AUX_DIS_CNTL 0x4000
311
312 #define AN_AUX_PAGE 0x3A
313 #define AN_AUX_OFFSET 0x3C
314 #define AN_AUX_DATA 0x3E
315
316 /*
317 * Length, Type, Value (LTV) record definitions and RID values.
318 */
319 struct an_ltv_gen {
320 u_int16_t an_len;
321 u_int16_t an_type;
322 u_int16_t an_val;
323 };
324
325 #define AN_DEF_SSID_LEN 7
326 #define AN_DEF_SSID "tsunami"
327
328 #define AN_RXGAP_MAX 8
329
330 /*
331 * Transmit frame structure.
332 */
333 struct an_txframe {
334 u_int32_t an_tx_sw; /* 0x00 */
335 u_int16_t an_tx_status; /* 0x04 */
336 u_int16_t an_tx_payload_len; /* 0x06 */
337 u_int16_t an_tx_ctl; /* 0x08 */
338 u_int16_t an_tx_assoc_id; /* 0x0A */
339 u_int16_t an_tx_retry; /* 0x0C */
340 u_int8_t an_tx_assoc_cnt; /* 0x0E */
341 u_int8_t an_tx_rate; /* 0x0F */
342 u_int8_t an_tx_max_long_retries; /* 0x10 */
343 u_int8_t an_tx_max_short_retries; /*0x11 */
344 u_int8_t an_rsvd0[2]; /* 0x12 */
345 u_int16_t an_frame_ctl; /* 0x14 */
346 u_int16_t an_duration; /* 0x16 */
347 u_int8_t an_addr1[6]; /* 0x18 */
348 u_int8_t an_addr2[6]; /* 0x1E */
349 u_int8_t an_addr3[6]; /* 0x24 */
350 u_int16_t an_seq_ctl; /* 0x2A */
351 u_int8_t an_addr4[6]; /* 0x2C */
352 u_int8_t an_gaplen; /* 0x32 */
353 } __packed;
354
355 struct an_rxframe_802_3 {
356 u_int16_t an_rx_802_3_status; /* 0x34 */
357 u_int16_t an_rx_802_3_payload_len;/* 0x36 */
358 u_int8_t an_rx_dst_addr[6]; /* 0x38 */
359 u_int8_t an_rx_src_addr[6]; /* 0x3E */
360 };
361 #define AN_RXGAP_MAX 8
362
363
364 struct an_txframe_802_3 {
365 /*
366 * Transmit 802.3 header structure.
367 */
368 u_int16_t an_tx_802_3_status; /* 0x34 */
369 u_int16_t an_tx_802_3_payload_len;/* 0x36 */
370 u_int8_t an_tx_dst_addr[6]; /* 0x38 */
371 u_int8_t an_tx_src_addr[6]; /* 0x3E */
372 };
373
374 #define AN_TXSTAT_EXCESS_RETRY 0x0002
375 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
376 #define AN_TXSTAT_AID_FAIL 0x0008
377 #define AN_TXSTAT_MAC_DISABLED 0x0010
378 #define AN_TXSTAT_ASSOC_LOST 0x0020
379
380 #define AN_TXCTL_RSVD 0x0001
381 #define AN_TXCTL_TXOK_INTR 0x0002
382 #define AN_TXCTL_TXERR_INTR 0x0004
383 #define AN_TXCTL_HEADER_TYPE 0x0008
384 #define AN_TXCTL_PAYLOAD_TYPE 0x0010
385 #define AN_TXCTL_NORELEASE 0x0020
386 #define AN_TXCTL_NORETRIES 0x0040
387 #define AN_TXCTL_CLEAR_AID 0x0080
388 #define AN_TXCTL_STRICT_ORDER 0x0100
389 #define AN_TXCTL_USE_RTS 0x0200
390
391 #define AN_HEADERTYPE_8023 0x0000
392 #define AN_HEADERTYPE_80211 0x0008
393
394 #define AN_PAYLOADTYPE_ETHER 0x0000
395 #define AN_PAYLOADTYPE_LLC 0x0010
396
397 #define AN_TXCTL_80211 (AN_HEADERTYPE_80211|AN_PAYLOADTYPE_LLC)
398
399 #define AN_TXCTL_8023 (AN_HEADERTYPE_8023|AN_PAYLOADTYPE_ETHER)
400
401 /*
402 * Additions to transmit control bits for MPI350
403 */
404 #define AN_TXCTL_HW(x) \
405 ( x ? (AN_TXCTL_NORELEASE) \
406 : \
407 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_TXCTL_NORELEASE) \
408 )
409
410 #define AN_TXGAP_80211 0
411 #define AN_TXGAP_8023 0
412
413 struct an_802_3_hdr {
414 u_int16_t an_8023_status;
415 u_int16_t an_8023_payload_len;
416 u_int8_t an_8023_dst_addr[6];
417 u_int8_t an_8023_src_addr[6];
418 u_int16_t an_8023_dat[3]; /* SNAP header */
419 u_int16_t an_8023_type;
420 };
421
422 struct an_snap_hdr {
423 u_int16_t an_snap_dat[3]; /* SNAP header */
424 u_int16_t an_snap_type;
425 };
426
427 struct an_dma_alloc {
428 u_int32_t an_dma_paddr;
429 caddr_t an_dma_vaddr;
430 bus_dmamap_t an_dma_map;
431 bus_dma_segment_t an_dma_seg;
432 bus_size_t an_dma_size;
433 int an_dma_nseg;
434 };
435
436 #define AN_TX_RING_CNT 4
437 #define AN_INC(x, y) (x) = (x + 1) % y
438
439 struct an_tx_ring_data {
440 u_int16_t an_tx_fids[AN_TX_RING_CNT];
441 u_int16_t an_tx_ring[AN_TX_RING_CNT];
442 int an_tx_prod;
443 int an_tx_cons;
444 int an_tx_empty;
445 };
446
447 struct an_softc {
448 struct ifnet *an_ifp;
449
450 int an_unit;
451
452 int port_rid; /* resource id for port range */
453 struct resource* port_res; /* resource for port range */
454 int mem_rid; /* resource id for memory range */
455 int mem_used; /* nonzero if memory used */
456 struct resource* mem_res; /* resource for memory range */
457 int mem_aux_rid; /* resource id for memory range */
458 int mem_aux_used; /* nonzero if memory used */
459 struct resource* mem_aux_res; /* resource for memory range */
460 int irq_rid; /* resource id for irq */
461 void* irq_handle; /* handle for irq handler */
462 struct resource* irq_res; /* resource for irq */
463
464 bus_space_handle_t an_bhandle_p;
465 bus_space_handle_t an_bhandle;
466 bus_space_tag_t an_btag;
467 bus_space_handle_t an_mem_bhandle;
468 bus_space_tag_t an_mem_btag;
469 bus_space_handle_t an_mem_aux_bhandle;
470 bus_space_tag_t an_mem_aux_btag;
471 bus_dma_tag_t an_dtag;
472 struct an_ltv_genconfig an_config;
473 struct an_ltv_caps an_caps;
474 struct an_ltv_ssidlist_new an_ssidlist;
475 struct an_ltv_aplist an_aplist;
476 struct an_ltv_key an_temp_keys[4];
477 int an_tx_rate;
478 int an_rxmode;
479 int an_gone;
480 int an_if_flags;
481 u_int8_t an_txbuf[1536];
482 struct an_tx_ring_data an_rdata;
483 struct an_ltv_stats an_stats;
484 struct an_ltv_status an_status;
485 u_int8_t an_associated;
486 #ifdef ANCACHE
487 int an_sigitems;
488 struct an_sigcache an_sigcache[MAXANCACHE];
489 int an_nextitem;
490 int an_have_rssimap;
491 struct an_ltv_rssi_map an_rssimap;
492 #endif
493 struct callout an_stat_ch;
494 struct mtx an_mtx;
495 device_t an_dev;
496 struct ifmedia an_ifmedia;
497 int an_monitor;
498 int an_was_monitor;
499 u_char buf_802_11[MCLBYTES];
500 struct an_req areq;
501 unsigned short* an_flash_buffer;
502 int mpi350;
503 struct an_dma_alloc an_rid_buffer;
504 struct an_dma_alloc an_rx_buffer[AN_MAX_RX_DESC];
505 struct an_dma_alloc an_tx_buffer[AN_MAX_TX_DESC];
506 };
507
508 #define AN_LOCK(_sc) mtx_lock(&(_sc)->an_mtx)
509 #define AN_UNLOCK(_sc) mtx_unlock(&(_sc)->an_mtx)
510 #define AN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->an_mtx, MA_OWNED)
511
512 void an_release_resources (device_t);
513 int an_alloc_port (device_t, int, int);
514 int an_alloc_memory (device_t, int, int);
515 int an_alloc_aux_memory (device_t, int, int);
516 int an_alloc_irq (device_t, int, int);
517 int an_pci_probe (device_t);
518 int an_probe (device_t);
519 int an_shutdown (device_t);
520 void an_resume (device_t);
521 int an_attach (struct an_softc *, int, int);
522 int an_detach (device_t);
523 void an_stop (struct an_softc *);
524
525 driver_intr_t an_intr;
526
527 #define AN_802_3_OFFSET 0x2E
528 #define AN_802_11_OFFSET 0x44
529 #define AN_802_11_OFFSET_RAW 0x3C
530
531 #define AN_STAT_BADCRC 0x0001
532 #define AN_STAT_UNDECRYPTABLE 0x0002
533 #define AN_STAT_ERRSTAT 0x0003
534 #define AN_STAT_MAC_PORT 0x0700
535 #define AN_STAT_1042 0x2000 /* RFC1042 encoded */
536 #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
537 #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
538 #define AN_RXSTAT_MSG_TYPE 0xE000
539
540 #define AN_ENC_TX_802_3 0x00
541 #define AN_ENC_TX_802_11 0x11
542 #define AN_ENC_TX_E_II 0x0E
543
544 #define AN_ENC_TX_1042 0x00
545 #define AN_ENC_TX_TUNNEL 0xF8
546
547 #define AN_TXCNTL_MACPORT 0x00FF
548 #define AN_TXCNTL_STRUCTTYPE 0xFF00
549
550 /*
551 * SNAP (sub-network access protocol) constants for transmission
552 * of IP datagrams over IEEE 802 networks, taken from RFC1042.
553 * We need these for the LLC/SNAP header fields in the TX/RX frame
554 * structure.
555 */
556 #define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */
557 #define AN_SNAP_K2 0x00
558 #define AN_SNAP_CONTROL 0x03 /* unnumbered information format */
559 #define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
560 #define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
561 #define AN_SNAPHDR_LEN 0x6
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