Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ar/if_ar.c
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1 /* 2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Programming assumptions and other issues. 33 * 34 * The descriptors of a DMA channel will fit in a 16K memory window. 35 * 36 * The buffers of a transmit DMA channel will fit in a 16K memory window. 37 * 38 * Only the ISA bus cards with X.21 and V.35 is tested. 39 * 40 * When interface is going up, handshaking is set and it is only cleared 41 * when the interface is down'ed. 42 * 43 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 44 * internal/external clock, etc..... 45 * 46 */ 47 48 #include "opt_netgraph.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/mbuf.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/module.h> 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus_memio.h> 63 #include <sys/rman.h> 64 65 #include <net/if.h> 66 #ifdef NETGRAPH 67 #include <netgraph/ng_message.h> 68 #include <netgraph/netgraph.h> 69 #include <sys/syslog.h> 70 #include <dev/ar/if_ar.h> 71 #else /* NETGRAPH */ 72 #include <net/if_sppp.h> 73 #include <net/bpf.h> 74 #endif /* NETGRAPH */ 75 76 #include <machine/clock.h> 77 #include <machine/md_var.h> 78 79 #include <dev/ic/hd64570.h> 80 #include <dev/ar/if_arregs.h> 81 82 #ifdef TRACE 83 #define TRC(x) x 84 #else 85 #define TRC(x) 86 #endif 87 88 #define TRCL(x) x 89 90 #define PPP_HEADER_LEN 4 91 92 struct ar_softc { 93 #ifndef NETGRAPH 94 struct sppp ifsppp; 95 #endif /* NETGRAPH */ 96 int unit; /* With regards to all ar devices */ 97 int subunit; /* With regards to this card */ 98 struct ar_hardc *hc; 99 100 struct buf_block { 101 u_int txdesc; /* On card address */ 102 u_int txstart; /* On card address */ 103 u_int txend; /* On card address */ 104 u_int txtail; /* Index of first unused buffer */ 105 u_int txmax; /* number of usable buffers/descriptors */ 106 u_int txeda; /* Error descriptor addresses */ 107 }block[AR_TX_BLOCKS]; 108 109 char xmit_busy; /* Transmitter is busy */ 110 char txb_inuse; /* Number of tx blocks currently in use */ 111 u_char txb_new; /* Index to where new buffer will be added */ 112 u_char txb_next_tx; /* Index to next block ready to tx */ 113 114 u_int rxdesc; /* On card address */ 115 u_int rxstart; /* On card address */ 116 u_int rxend; /* On card address */ 117 u_int rxhind; /* Index to the head of the rx buffers. */ 118 u_int rxmax; /* number of usable buffers/descriptors */ 119 120 int scano; 121 int scachan; 122 sca_regs *sca; 123 #ifdef NETGRAPH 124 int running; /* something is attached so we are running */ 125 int dcd; /* do we have dcd? */ 126 /* ---netgraph bits --- */ 127 char nodename[NG_NODELEN + 1]; /* store our node name */ 128 int datahooks; /* number of data hooks attached */ 129 node_p node; /* netgraph node */ 130 hook_p hook; /* data hook */ 131 hook_p debug_hook; 132 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 133 struct ifqueue xmitq; /* transmit queue */ 134 int flags; /* state */ 135 #define SCF_RUNNING 0x01 /* board is active */ 136 #define SCF_OACTIVE 0x02 /* output is active */ 137 int out_dog; /* watchdog cycles output count-down */ 138 struct callout_handle handle; /* timeout(9) handle */ 139 u_long inbytes, outbytes; /* stats */ 140 u_long lastinbytes, lastoutbytes; /* a second ago */ 141 u_long inrate, outrate; /* highest rate seen */ 142 u_long inlast; /* last input N secs ago */ 143 u_long out_deficit; /* output since last input */ 144 u_long oerrors, ierrors[6]; 145 u_long opackets, ipackets; 146 #endif /* NETGRAPH */ 147 }; 148 149 static int next_ar_unit = 0; 150 151 #ifdef NETGRAPH 152 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 153 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 154 #define LOTS_OF_PACKETS 100 155 #endif /* NETGRAPH */ 156 157 /* 158 * This translate from irq numbers to 159 * the value that the arnet card needs 160 * in the lower part of the AR_INT_SEL 161 * register. 162 */ 163 static int irqtable[16] = { 164 0, /* 0 */ 165 0, /* 1 */ 166 0, /* 2 */ 167 1, /* 3 */ 168 0, /* 4 */ 169 2, /* 5 */ 170 0, /* 6 */ 171 3, /* 7 */ 172 0, /* 8 */ 173 0, /* 9 */ 174 4, /* 10 */ 175 5, /* 11 */ 176 6, /* 12 */ 177 0, /* 13 */ 178 0, /* 14 */ 179 7 /* 15 */ 180 }; 181 182 #ifndef NETGRAPH 183 MODULE_DEPEND(if_ar, sppp, 1, 1, 1); 184 #else 185 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1); 186 #endif 187 188 static void arintr(void *arg); 189 static void ar_xmit(struct ar_softc *sc); 190 #ifndef NETGRAPH 191 static void arstart(struct ifnet *ifp); 192 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 193 static void arwatchdog(struct ifnet *ifp); 194 #else /* NETGRAPH */ 195 static void arstart(struct ar_softc *sc); 196 static void arwatchdog(struct ar_softc *sc); 197 #endif /* NETGRAPH */ 198 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat); 199 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len); 200 static void ar_eat_packet(struct ar_softc *sc, int single); 201 static void ar_get_packets(struct ar_softc *sc); 202 203 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel); 204 static void ar_up(struct ar_softc *sc); 205 static void ar_down(struct ar_softc *sc); 206 static void arc_init(struct ar_hardc *hc); 207 static void ar_init_sca(struct ar_hardc *hc, int scano); 208 static void ar_init_msci(struct ar_softc *sc); 209 static void ar_init_rx_dmac(struct ar_softc *sc); 210 static void ar_init_tx_dmac(struct ar_softc *sc); 211 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr); 212 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr); 213 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr); 214 215 #ifdef NETGRAPH 216 static void ngar_watchdog_frame(void * arg); 217 static void ngar_init(void* ignored); 218 219 static ng_constructor_t ngar_constructor; 220 static ng_rcvmsg_t ngar_rcvmsg; 221 static ng_shutdown_t ngar_rmnode; 222 static ng_newhook_t ngar_newhook; 223 /*static ng_findhook_t ngar_findhook; */ 224 static ng_connect_t ngar_connect; 225 static ng_rcvdata_t ngar_rcvdata; 226 static ng_disconnect_t ngar_disconnect; 227 228 static struct ng_type typestruct = { 229 NG_VERSION, 230 NG_AR_NODE_TYPE, 231 NULL, 232 ngar_constructor, 233 ngar_rcvmsg, 234 ngar_rmnode, 235 ngar_newhook, 236 NULL, 237 ngar_connect, 238 ngar_rcvdata, 239 ngar_rcvdata, 240 ngar_disconnect, 241 NULL 242 }; 243 244 static int ngar_done_init = 0; 245 #endif /* NETGRAPH */ 246 247 int 248 ar_attach(device_t device) 249 { 250 struct ar_hardc *hc; 251 struct ar_softc *sc; 252 #ifndef NETGRAPH 253 struct ifnet *ifp; 254 char *iface; 255 #endif /* NETGRAPH */ 256 int unit; 257 258 hc = (struct ar_hardc *)device_get_softc(device); 259 260 printf("arc%d: %uK RAM, %u ports, rev %u.\n", 261 hc->cunit, 262 hc->memsize/1024, 263 hc->numports, 264 hc->revision); 265 266 arc_init(hc); 267 268 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, 269 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0) 270 return (1); 271 272 sc = hc->sc; 273 274 for(unit=0;unit<hc->numports;unit+=NCHAN) 275 ar_init_sca(hc, unit / NCHAN); 276 277 /* 278 * Now configure each port on the card. 279 */ 280 for(unit=0;unit<hc->numports;sc++,unit++) { 281 sc->hc = hc; 282 sc->subunit = unit; 283 sc->unit = next_ar_unit; 284 next_ar_unit++; 285 sc->scano = unit / NCHAN; 286 sc->scachan = unit%NCHAN; 287 288 ar_init_rx_dmac(sc); 289 ar_init_tx_dmac(sc); 290 ar_init_msci(sc); 291 292 #ifndef NETGRAPH 293 ifp = &sc->ifsppp.pp_if; 294 295 ifp->if_softc = sc; 296 ifp->if_unit = sc->unit; 297 ifp->if_name = "ar"; 298 ifp->if_mtu = PP_MTU; 299 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 300 ifp->if_ioctl = arioctl; 301 ifp->if_start = arstart; 302 ifp->if_watchdog = arwatchdog; 303 304 sc->ifsppp.pp_flags = PP_KEEPALIVE; 305 306 switch(hc->interface[unit]) { 307 default: iface = "UNKNOWN"; break; 308 case AR_IFACE_EIA_232: iface = "EIA-232"; break; 309 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break; 310 case AR_IFACE_EIA_530: iface = "EIA-530"; break; 311 case AR_IFACE_X_21: iface = "X.21"; break; 312 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break; 313 } 314 315 printf("ar%d: Adapter %d, port %d, interface %s.\n", 316 sc->unit, 317 hc->cunit, 318 sc->subunit, 319 iface); 320 321 sppp_attach((struct ifnet *)&sc->ifsppp); 322 if_attach(ifp); 323 324 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 325 #else /* NETGRAPH */ 326 /* 327 * we have found a node, make sure our 'type' is availabe. 328 */ 329 if (ngar_done_init == 0) ngar_init(NULL); 330 if (ng_make_node_common(&typestruct, &sc->node) != 0) 331 return (1); 332 sc->node->private = sc; 333 callout_handle_init(&sc->handle); 334 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 335 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 336 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 337 if (ng_name_node(sc->node, sc->nodename)) { 338 ng_rmnode(sc->node); 339 ng_unref(sc->node); 340 return (1); 341 } 342 sc->running = 0; 343 #endif /* NETGRAPH */ 344 } 345 346 if(hc->bustype == AR_BUS_ISA) 347 ARC_SET_OFF(hc->iobase); 348 349 return (0); 350 } 351 352 int 353 ar_detach(device_t device) 354 { 355 device_t parent = device_get_parent(device); 356 struct ar_hardc *hc = device_get_softc(device); 357 358 if (hc->intr_cookie != NULL) { 359 if (BUS_TEARDOWN_INTR(parent, device, 360 hc->res_irq, hc->intr_cookie) != 0) { 361 printf("intr teardown failed.. continuing\n"); 362 } 363 hc->intr_cookie = NULL; 364 } 365 366 /* 367 * deallocate any system resources we may have 368 * allocated on behalf of this driver. 369 */ 370 FREE(hc->sc, M_DEVBUF); 371 hc->sc = NULL; 372 hc->mem_start = NULL; 373 return (ar_deallocate_resources(device)); 374 } 375 376 int 377 ar_allocate_ioport(device_t device, int rid, u_long size) 378 { 379 struct ar_hardc *hc = device_get_softc(device); 380 381 hc->rid_ioport = rid; 382 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, 383 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); 384 if (hc->res_ioport == NULL) { 385 goto errexit; 386 } 387 return (0); 388 389 errexit: 390 ar_deallocate_resources(device); 391 return (ENXIO); 392 } 393 394 int 395 ar_allocate_irq(device_t device, int rid, u_long size) 396 { 397 struct ar_hardc *hc = device_get_softc(device); 398 399 hc->rid_irq = rid; 400 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ, 401 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE); 402 if (hc->res_irq == NULL) { 403 goto errexit; 404 } 405 return (0); 406 407 errexit: 408 ar_deallocate_resources(device); 409 return (ENXIO); 410 } 411 412 int 413 ar_allocate_memory(device_t device, int rid, u_long size) 414 { 415 struct ar_hardc *hc = device_get_softc(device); 416 417 hc->rid_memory = rid; 418 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 419 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); 420 if (hc->res_memory == NULL) { 421 goto errexit; 422 } 423 return (0); 424 425 errexit: 426 ar_deallocate_resources(device); 427 return (ENXIO); 428 } 429 430 int 431 ar_allocate_plx_memory(device_t device, int rid, u_long size) 432 { 433 struct ar_hardc *hc = device_get_softc(device); 434 435 hc->rid_plx_memory = rid; 436 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 437 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); 438 if (hc->res_plx_memory == NULL) { 439 goto errexit; 440 } 441 return (0); 442 443 errexit: 444 ar_deallocate_resources(device); 445 return (ENXIO); 446 } 447 448 int 449 ar_deallocate_resources(device_t device) 450 { 451 struct ar_hardc *hc = device_get_softc(device); 452 453 if (hc->res_irq != 0) { 454 bus_deactivate_resource(device, SYS_RES_IRQ, 455 hc->rid_irq, hc->res_irq); 456 bus_release_resource(device, SYS_RES_IRQ, 457 hc->rid_irq, hc->res_irq); 458 hc->res_irq = 0; 459 } 460 if (hc->res_ioport != 0) { 461 bus_deactivate_resource(device, SYS_RES_IOPORT, 462 hc->rid_ioport, hc->res_ioport); 463 bus_release_resource(device, SYS_RES_IOPORT, 464 hc->rid_ioport, hc->res_ioport); 465 hc->res_ioport = 0; 466 } 467 if (hc->res_memory != 0) { 468 bus_deactivate_resource(device, SYS_RES_MEMORY, 469 hc->rid_memory, hc->res_memory); 470 bus_release_resource(device, SYS_RES_MEMORY, 471 hc->rid_memory, hc->res_memory); 472 hc->res_memory = 0; 473 } 474 if (hc->res_plx_memory != 0) { 475 bus_deactivate_resource(device, SYS_RES_MEMORY, 476 hc->rid_plx_memory, hc->res_plx_memory); 477 bus_release_resource(device, SYS_RES_MEMORY, 478 hc->rid_plx_memory, hc->res_plx_memory); 479 hc->res_plx_memory = 0; 480 } 481 return (0); 482 } 483 484 /* 485 * First figure out which SCA gave the interrupt. 486 * Process it. 487 * See if there is other interrupts pending. 488 * Repeat until there is no more interrupts. 489 */ 490 static void 491 arintr(void *arg) 492 { 493 struct ar_hardc *hc = (struct ar_hardc *)arg; 494 sca_regs *sca; 495 u_char isr0, isr1, isr2, arisr; 496 int scano; 497 498 /* XXX Use the PCI interrupt score board register later */ 499 if(hc->bustype == AR_BUS_PCI) 500 arisr = hc->orbase[AR_ISTAT * 4]; 501 else 502 arisr = inb(hc->iobase + AR_ISTAT); 503 504 while(arisr & AR_BD_INT) { 505 TRC(printf("arisr = %x\n", arisr)); 506 if(arisr & AR_INT_0) 507 scano = 0; 508 else if(arisr & AR_INT_1) 509 scano = 1; 510 else { 511 /* XXX Oops this shouldn't happen. */ 512 printf("arc%d: Interrupted with no interrupt.\n", 513 hc->cunit); 514 return; 515 } 516 sca = hc->sca[scano]; 517 518 if(hc->bustype == AR_BUS_ISA) 519 ARC_SET_SCA(hc->iobase, scano); 520 521 isr0 = sca->isr0; 522 isr1 = sca->isr1; 523 isr2 = sca->isr2; 524 525 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n", 526 hc->cunit, 527 isr0, 528 isr1, 529 isr2)); 530 if(isr0) 531 ar_msci_intr(hc, scano, isr0); 532 533 if(isr1) 534 ar_dmac_intr(hc, scano, isr1); 535 536 if(isr2) 537 ar_timer_intr(hc, scano, isr2); 538 539 /* 540 * Proccess the second sca's interrupt if available. 541 * Else see if there are any new interrupts. 542 */ 543 if((arisr & AR_INT_0) && (arisr & AR_INT_1)) 544 arisr &= ~AR_INT_0; 545 else { 546 if(hc->bustype == AR_BUS_PCI) 547 arisr = hc->orbase[AR_ISTAT * 4]; 548 else 549 arisr = inb(hc->iobase + AR_ISTAT); 550 } 551 } 552 553 if(hc->bustype == AR_BUS_ISA) 554 ARC_SET_OFF(hc->iobase); 555 } 556 557 558 /* 559 * This will only start the transmitter. It is assumed that the data 560 * is already there. It is normally called from arstart() or ar_dmac_intr(). 561 * 562 */ 563 static void 564 ar_xmit(struct ar_softc *sc) 565 { 566 #ifndef NETGRAPH 567 struct ifnet *ifp; 568 #endif /* NETGRAPH */ 569 dmac_channel *dmac; 570 571 #ifndef NETGRAPH 572 ifp = &sc->ifsppp.pp_if; 573 #endif /* NETGRAPH */ 574 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 575 576 if(sc->hc->bustype == AR_BUS_ISA) 577 ARC_SET_SCA(sc->hc->iobase, sc->scano); 578 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff); 579 580 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff); 581 dmac->dsr = SCA_DSR_DE; 582 583 sc->xmit_busy = 1; 584 585 sc->txb_next_tx++; 586 if(sc->txb_next_tx == AR_TX_BLOCKS) 587 sc->txb_next_tx = 0; 588 589 #ifndef NETGRAPH 590 ifp->if_timer = 2; /* Value in seconds. */ 591 #else /* NETGRAPH */ 592 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 593 #endif /* NETGRAPH */ 594 if(sc->hc->bustype == AR_BUS_ISA) 595 ARC_SET_OFF(sc->hc->iobase); 596 } 597 598 /* 599 * This function will be called from the upper level when a user add a 600 * packet to be send, and from the interrupt handler after a finished 601 * transmit. 602 * 603 * NOTE: it should run at spl_imp(). 604 * 605 * This function only place the data in the oncard buffers. It does not 606 * start the transmition. ar_xmit() does that. 607 * 608 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function 609 * that clears that should ensure that the transmitter and its DMA is 610 * in a "good" idle state. 611 */ 612 #ifndef NETGRAPH 613 static void 614 arstart(struct ifnet *ifp) 615 { 616 struct ar_softc *sc = ifp->if_softc; 617 #else /* NETGRAPH */ 618 static void 619 arstart(struct ar_softc *sc) 620 { 621 #endif /* NETGRAPH */ 622 int i, len, tlen; 623 struct mbuf *mtx; 624 u_char *txdata; 625 sca_descriptor *txdesc; 626 struct buf_block *blkp; 627 628 #ifndef NETGRAPH 629 if(!(ifp->if_flags & IFF_RUNNING)) 630 return; 631 #else /* NETGRAPH */ 632 /* XXX */ 633 #endif /* NETGRAPH */ 634 635 top_arstart: 636 637 /* 638 * See if we have space for more packets. 639 */ 640 if(sc->txb_inuse == AR_TX_BLOCKS) { 641 #ifndef NETGRAPH 642 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 643 #else /* NETGRAPH */ 644 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ 645 #endif /* NETGRAPH */ 646 return; 647 } 648 649 #ifndef NETGRAPH 650 mtx = sppp_dequeue(ifp); 651 #else /* NETGRAPH */ 652 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 653 if (mtx == NULL) { 654 IF_DEQUEUE(&sc->xmitq, mtx); 655 } 656 #endif /* NETGRAPH */ 657 if(!mtx) 658 return; 659 660 /* 661 * It is OK to set the memory window outside the loop because 662 * all tx buffers and descriptors are assumed to be in the same 663 * 16K window. 664 */ 665 if(sc->hc->bustype == AR_BUS_ISA) 666 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc); 667 668 /* 669 * We stay in this loop until there is nothing in the 670 * TX queue left or the tx buffer is full. 671 */ 672 i = 0; 673 blkp = &sc->block[sc->txb_new]; 674 txdesc = (sca_descriptor *) 675 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk)); 676 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk)); 677 for(;;) { 678 len = mtx->m_pkthdr.len; 679 680 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len)); 681 682 /* 683 * We can do this because the tx buffers don't wrap. 684 */ 685 m_copydata(mtx, 0, len, txdata); 686 tlen = len; 687 while(tlen > AR_BUF_SIZ) { 688 txdesc->stat = 0; 689 txdesc->len = AR_BUF_SIZ; 690 tlen -= AR_BUF_SIZ; 691 txdesc++; 692 txdata += AR_BUF_SIZ; 693 i++; 694 } 695 /* XXX Move into the loop? */ 696 txdesc->stat = SCA_DESC_EOM; 697 txdesc->len = tlen; 698 txdesc++; 699 txdata += AR_BUF_SIZ; 700 i++; 701 702 #ifndef NETGRAPH 703 if(ifp->if_bpf) 704 bpf_mtap(ifp, mtx); 705 m_freem(mtx); 706 ++sc->ifsppp.pp_if.if_opackets; 707 #else /* NETGRAPH */ 708 m_freem(mtx); 709 sc->outbytes += len; 710 ++sc->opackets; 711 #endif /* NETGRAPH */ 712 713 /* 714 * Check if we have space for another mbuf. 715 * XXX This is hardcoded. A packet won't be larger 716 * than 3 buffers (3 x 512). 717 */ 718 if((i + 3) >= blkp->txmax) 719 break; 720 721 #ifndef NETGRAPH 722 mtx = sppp_dequeue(ifp); 723 #else /* NETGRAPH */ 724 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 725 if (mtx == NULL) { 726 IF_DEQUEUE(&sc->xmitq, mtx); 727 } 728 #endif /* NETGRAPH */ 729 if(!mtx) 730 break; 731 } 732 733 blkp->txtail = i; 734 735 /* 736 * Mark the last descriptor, so that the SCA know where 737 * to stop. 738 */ 739 txdesc--; 740 txdesc->stat |= SCA_DESC_EOT; 741 742 txdesc = (sca_descriptor *)blkp->txdesc; 743 blkp->txeda = (u_short)((u_int)&txdesc[i]); 744 745 #if 0 746 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp); 747 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp); 748 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb); 749 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len); 750 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat); 751 #endif 752 753 sc->txb_inuse++; 754 sc->txb_new++; 755 if(sc->txb_new == AR_TX_BLOCKS) 756 sc->txb_new = 0; 757 758 if(sc->xmit_busy == 0) 759 ar_xmit(sc); 760 761 if(sc->hc->bustype == AR_BUS_ISA) 762 ARC_SET_OFF(sc->hc->iobase); 763 764 goto top_arstart; 765 } 766 767 #ifndef NETGRAPH 768 static int 769 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 770 { 771 int s, error; 772 int was_up, should_be_up; 773 struct ar_softc *sc = ifp->if_softc; 774 775 TRC(printf("ar%d: arioctl.\n", ifp->if_unit);) 776 777 was_up = ifp->if_flags & IFF_RUNNING; 778 779 error = sppp_ioctl(ifp, cmd, data); 780 TRC(printf("ar%d: ioctl: ifsppp.pp_flags = %x, if_flags %x.\n", 781 ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);) 782 if(error) 783 return (error); 784 785 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR)) 786 return (0); 787 788 TRC(printf("ar%d: arioctl %s.\n", ifp->if_unit, 789 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");) 790 791 s = splimp(); 792 should_be_up = ifp->if_flags & IFF_RUNNING; 793 794 if(!was_up && should_be_up) { 795 /* Interface should be up -- start it. */ 796 ar_up(sc); 797 arstart(ifp); 798 /* XXX Maybe clear the IFF_UP flag so that the link 799 * will only go up after sppp lcp and ipcp negotiation. 800 */ 801 } else if(was_up && !should_be_up) { 802 /* Interface should be down -- stop it. */ 803 ar_down(sc); 804 sppp_flush(ifp); 805 } 806 splx(s); 807 return (0); 808 } 809 #endif /* NETGRAPH */ 810 811 /* 812 * This is to catch lost tx interrupts. 813 */ 814 static void 815 #ifndef NETGRAPH 816 arwatchdog(struct ifnet *ifp) 817 { 818 struct ar_softc *sc = ifp->if_softc; 819 #else /* NETGRAPH */ 820 arwatchdog(struct ar_softc *sc) 821 { 822 #endif /* NETGRAPH */ 823 msci_channel *msci = &sc->sca->msci[sc->scachan]; 824 825 #ifndef NETGRAPH 826 if(!(ifp->if_flags & IFF_RUNNING)) 827 return; 828 #endif /* NETGRAPH */ 829 830 if(sc->hc->bustype == AR_BUS_ISA) 831 ARC_SET_SCA(sc->hc->iobase, sc->scano); 832 833 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */ 834 printf("ar%d: transmit failed, " 835 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n", 836 sc->unit, 837 msci->st0, 838 msci->st1, 839 msci->st3, 840 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr); 841 842 if(msci->st1 & SCA_ST1_UDRN) { 843 msci->cmd = SCA_CMD_TXABORT; 844 msci->cmd = SCA_CMD_TXENABLE; 845 msci->st1 = SCA_ST1_UDRN; 846 } 847 848 sc->xmit_busy = 0; 849 #ifndef NETGRAPH 850 ifp->if_flags &= ~IFF_OACTIVE; 851 #else /* NETGRAPH */ 852 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */ 853 #endif /* NETGRAPH */ 854 855 if(sc->txb_inuse && --sc->txb_inuse) 856 ar_xmit(sc); 857 858 #ifndef NETGRAPH 859 arstart(ifp); 860 #else /* NETGRAPH */ 861 arstart(sc); 862 #endif /* NETGRAPH */ 863 } 864 865 static void 866 ar_up(struct ar_softc *sc) 867 { 868 sca_regs *sca; 869 msci_channel *msci; 870 871 sca = sc->sca; 872 msci = &sca->msci[sc->scachan]; 873 874 TRC(printf("ar%d: sca %p, msci %p, ch %d\n", 875 sc->unit, sca, msci, sc->scachan)); 876 877 /* 878 * Enable transmitter and receiver. 879 * Raise DTR and RTS. 880 * Enable interrupts. 881 */ 882 if(sc->hc->bustype == AR_BUS_ISA) 883 ARC_SET_SCA(sc->hc->iobase, sc->scano); 884 885 /* XXX 886 * What about using AUTO mode in msci->md0 ??? 887 * And what about CTS/DCD etc... ? 888 */ 889 if(sc->hc->handshake & AR_SHSK_RTS) 890 msci->ctl &= ~SCA_CTL_RTS; 891 if(sc->hc->handshake & AR_SHSK_DTR) { 892 sc->hc->txc_dtr[sc->scano] &= sc->scachan ? 893 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0; 894 if(sc->hc->bustype == AR_BUS_PCI) 895 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 896 sc->hc->txc_dtr[sc->scano]; 897 else 898 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano], 899 sc->hc->txc_dtr[sc->scano]); 900 } 901 902 if(sc->scachan == 0) { 903 sca->ier0 |= 0x0F; 904 sca->ier1 |= 0x0F; 905 } else { 906 sca->ier0 |= 0xF0; 907 sca->ier1 |= 0xF0; 908 } 909 910 msci->cmd = SCA_CMD_RXENABLE; 911 if(sc->hc->bustype == AR_BUS_ISA) 912 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */ 913 msci->cmd = SCA_CMD_TXENABLE; 914 915 if(sc->hc->bustype == AR_BUS_ISA) 916 ARC_SET_OFF(sc->hc->iobase); 917 #ifdef NETGRAPH 918 untimeout(ngar_watchdog_frame, sc, sc->handle); 919 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 920 sc->running = 1; 921 #endif /* NETGRAPH */ 922 } 923 924 static void 925 ar_down(struct ar_softc *sc) 926 { 927 sca_regs *sca; 928 msci_channel *msci; 929 930 sca = sc->sca; 931 msci = &sca->msci[sc->scachan]; 932 933 #ifdef NETGRAPH 934 untimeout(ngar_watchdog_frame, sc, sc->handle); 935 sc->running = 0; 936 #endif /* NETGRAPH */ 937 /* 938 * Disable transmitter and receiver. 939 * Lower DTR and RTS. 940 * Disable interrupts. 941 */ 942 if(sc->hc->bustype == AR_BUS_ISA) 943 ARC_SET_SCA(sc->hc->iobase, sc->scano); 944 msci->cmd = SCA_CMD_RXDISABLE; 945 if(sc->hc->bustype == AR_BUS_ISA) 946 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */ 947 msci->cmd = SCA_CMD_TXDISABLE; 948 949 if(sc->hc->handshake & AR_SHSK_RTS) 950 msci->ctl |= SCA_CTL_RTS; 951 if(sc->hc->handshake & AR_SHSK_DTR) { 952 sc->hc->txc_dtr[sc->scano] |= sc->scachan ? 953 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0; 954 if(sc->hc->bustype == AR_BUS_PCI) 955 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 956 sc->hc->txc_dtr[sc->scano]; 957 else 958 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano], 959 sc->hc->txc_dtr[sc->scano]); 960 } 961 962 if(sc->scachan == 0) { 963 sca->ier0 &= ~0x0F; 964 sca->ier1 &= ~0x0F; 965 } else { 966 sca->ier0 &= ~0xF0; 967 sca->ier1 &= ~0xF0; 968 } 969 970 if(sc->hc->bustype == AR_BUS_ISA) 971 ARC_SET_OFF(sc->hc->iobase); 972 } 973 974 static int 975 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel) 976 { 977 int ctype, i, val, x; 978 volatile u_char *pimctrl; 979 980 ctype = 0; 981 val = 0; 982 983 pimctrl = hc->orbase + AR_PIMCTRL; 984 985 /* Reset the PIM */ 986 *pimctrl = 0x00; 987 *pimctrl = AR_PIM_STROBE; 988 989 /* Check if there is a PIM */ 990 *pimctrl = 0x00; 991 *pimctrl = AR_PIM_READ; 992 x = *pimctrl; 993 TRC(printf("x = %x", x)); 994 if(x & AR_PIM_DATA) { 995 printf("No PIM installed\n"); 996 return (AR_IFACE_UNKNOWN); 997 } 998 999 x = (x >> 1) & 0x01; 1000 val |= x << 0; 1001 1002 /* Now read the next 15 bits */ 1003 for(i = 1; i < 16; i++) { 1004 *pimctrl = AR_PIM_READ; 1005 *pimctrl = AR_PIM_READ | AR_PIM_STROBE; 1006 x = *pimctrl; 1007 TRC(printf(" %x ", x)); 1008 x = (x >> 1) & 0x01; 1009 val |= x << i; 1010 if(i == 8 && (val & 0x000f) == 0x0004) { 1011 int ii; 1012 1013 /* Start bit */ 1014 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1015 *pimctrl = AR_PIM_A2D_DOUT; 1016 1017 /* Mode bit */ 1018 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1019 *pimctrl = AR_PIM_A2D_DOUT; 1020 1021 /* Sign bit */ 1022 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1023 *pimctrl = AR_PIM_A2D_DOUT; 1024 1025 /* Select channel */ 1026 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2); 1027 *pimctrl = ((channel & 2) << 2); 1028 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3); 1029 *pimctrl = ((channel & 1) << 3); 1030 1031 *pimctrl = AR_PIM_A2D_STROBE; 1032 1033 x = *pimctrl; 1034 if(x & AR_PIM_DATA) 1035 printf("\nOops A2D start bit not zero (%X)\n", x); 1036 1037 for(ii = 7; ii >= 0; ii--) { 1038 *pimctrl = 0x00; 1039 *pimctrl = AR_PIM_A2D_STROBE; 1040 x = *pimctrl; 1041 if(x & AR_PIM_DATA) 1042 ctype |= 1 << ii; 1043 } 1044 } 1045 } 1046 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype)); 1047 *pimctrl = AR_PIM_MODEG; 1048 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1049 if(ctype > 255) 1050 return (AR_IFACE_UNKNOWN); 1051 if(ctype > 239) 1052 return (AR_IFACE_V_35); 1053 if(ctype > 207) 1054 return (AR_IFACE_EIA_232); 1055 if(ctype > 178) 1056 return (AR_IFACE_X_21); 1057 if(ctype > 150) 1058 return (AR_IFACE_EIA_530); 1059 if(ctype > 25) 1060 return (AR_IFACE_UNKNOWN); 1061 if(ctype > 7) 1062 return (AR_IFACE_LOOPBACK); 1063 return (AR_IFACE_UNKNOWN); 1064 } 1065 1066 /* 1067 * Initialize the card, allocate memory for the ar_softc structures 1068 * and fill in the pointers. 1069 */ 1070 static void 1071 arc_init(struct ar_hardc *hc) 1072 { 1073 struct ar_softc *sc; 1074 int x; 1075 u_int chanmem; 1076 u_int bufmem; 1077 u_int next; 1078 u_int descneeded; 1079 u_char isr, mar; 1080 1081 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc), 1082 M_DEVBUF, M_WAITOK | M_ZERO); 1083 if (sc == NULL) 1084 return; 1085 hc->sc = sc; 1086 1087 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET | 1088 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1089 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1090 hc->txc_dtr_off[0] = AR_TXC_DTR0; 1091 hc->txc_dtr_off[1] = AR_TXC_DTR2; 1092 if(hc->bustype == AR_BUS_PCI) { 1093 hc->txc_dtr_off[0] *= 4; 1094 hc->txc_dtr_off[1] *= 4; 1095 } 1096 1097 /* 1098 * reset the card and wait at least 1uS. 1099 */ 1100 if(hc->bustype == AR_BUS_PCI) 1101 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET & 1102 hc->txc_dtr[0]; 1103 else 1104 outb(hc->iobase + AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & 1105 hc->txc_dtr[0]); 1106 DELAY(2); 1107 if(hc->bustype == AR_BUS_PCI) 1108 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1109 else 1110 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]); 1111 1112 if(hc->bustype == AR_BUS_ISA) { 1113 /* 1114 * Configure the card. 1115 * Mem address, irq, 1116 */ 1117 mar = kvtop(hc->mem_start) >> 16; 1118 isr = irqtable[hc->isa_irq] << 1; 1119 if(isr == 0) 1120 printf("ar%d: Warning illegal interrupt %d\n", 1121 hc->cunit, hc->isa_irq); 1122 isr = isr | ((kvtop(hc->mem_start) & 0xc000) >> 10); 1123 1124 hc->sca[0] = (sca_regs *)hc->mem_start; 1125 hc->sca[1] = (sca_regs *)hc->mem_start; 1126 1127 outb(hc->iobase + AR_MEM_SEL, mar); 1128 outb(hc->iobase + AR_INT_SEL, isr | AR_INTS_CEN); 1129 } 1130 1131 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM) 1132 for(x = 0; x < hc->numports; x++) 1133 hc->interface[x] = ar_read_pim_iface(hc, x); 1134 1135 /* 1136 * Set the TX clock direction and enable TX. 1137 */ 1138 for(x=0;x<hc->numports;x++) { 1139 switch(hc->interface[x]) { 1140 case AR_IFACE_V_35: 1141 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1142 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1143 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1144 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1; 1145 break; 1146 case AR_IFACE_EIA_530: 1147 case AR_IFACE_COMBO: 1148 case AR_IFACE_X_21: 1149 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1150 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1151 break; 1152 } 1153 } 1154 1155 if(hc->bustype == AR_BUS_PCI) 1156 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1157 else 1158 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]); 1159 if(hc->numports > NCHAN) { 1160 if(hc->bustype == AR_BUS_PCI) 1161 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1]; 1162 else 1163 outb(hc->iobase + AR_TXC_DTR2, hc->txc_dtr[1]); 1164 } 1165 1166 chanmem = hc->memsize / hc->numports; 1167 next = 0; 1168 1169 for(x=0;x<hc->numports;x++, sc++) { 1170 int blk; 1171 1172 sc->sca = hc->sca[x / NCHAN]; 1173 1174 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1175 sc->block[blk].txdesc = next; 1176 bufmem = (16 * 1024) / AR_TX_BLOCKS; 1177 descneeded = bufmem / AR_BUF_SIZ; 1178 sc->block[blk].txstart = sc->block[blk].txdesc + 1179 ((((descneeded * sizeof(sca_descriptor)) / 1180 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1181 sc->block[blk].txend = next + bufmem; 1182 sc->block[blk].txmax = 1183 (sc->block[blk].txend - sc->block[blk].txstart) 1184 / AR_BUF_SIZ; 1185 next += bufmem; 1186 1187 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, " 1188 "txend %x, txmax %d\n", 1189 x, 1190 blk, 1191 sc->block[blk].txdesc, 1192 sc->block[blk].txstart, 1193 sc->block[blk].txend, 1194 sc->block[blk].txmax)); 1195 } 1196 1197 sc->rxdesc = next; 1198 bufmem = chanmem - (bufmem * AR_TX_BLOCKS); 1199 descneeded = bufmem / AR_BUF_SIZ; 1200 sc->rxstart = sc->rxdesc + 1201 ((((descneeded * sizeof(sca_descriptor)) / 1202 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1203 sc->rxend = next + bufmem; 1204 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ; 1205 next += bufmem; 1206 TRC(printf("ar%d: rxdesc %x, rxstart %x, " 1207 "rxend %x, rxmax %d\n", 1208 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax)); 1209 } 1210 1211 if(hc->bustype == AR_BUS_PCI) 1212 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1213 } 1214 1215 1216 /* 1217 * The things done here are channel independent. 1218 * 1219 * Configure the sca waitstates. 1220 * Configure the global interrupt registers. 1221 * Enable master dma enable. 1222 */ 1223 static void 1224 ar_init_sca(struct ar_hardc *hc, int scano) 1225 { 1226 sca_regs *sca; 1227 1228 sca = hc->sca[scano]; 1229 if(hc->bustype == AR_BUS_ISA) 1230 ARC_SET_SCA(hc->iobase, scano); 1231 1232 /* 1233 * Do the wait registers. 1234 * Set everything to 0 wait states. 1235 */ 1236 sca->pabr0 = 0; 1237 sca->pabr1 = 0; 1238 sca->wcrl = 0; 1239 sca->wcrm = 0; 1240 sca->wcrh = 0; 1241 1242 /* 1243 * Configure the interrupt registers. 1244 * Most are cleared until the interface is configured. 1245 */ 1246 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */ 1247 sca->ier1 = 0x00; /* DMAC interrupts */ 1248 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */ 1249 sca->itcr = 0x00; /* Use ivr and no intr ack */ 1250 sca->ivr = 0x40; /* Fill in the interrupt vector. */ 1251 sca->imvr = 0x40; 1252 1253 /* 1254 * Configure the timers. 1255 * XXX Later 1256 */ 1257 1258 1259 /* 1260 * Set the DMA channel priority to rotate between 1261 * all four channels. 1262 * 1263 * Enable all dma channels. 1264 */ 1265 if(hc->bustype == AR_BUS_PCI) { 1266 u_char *t; 1267 1268 /* 1269 * Stupid problem with the PCI interface chip that break 1270 * things. 1271 * XXX 1272 */ 1273 t = (u_char *)sca; 1274 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2; 1275 t[AR_PCI_SCA_DMER] = SCA_DMER_EN; 1276 } else { 1277 sca->pcr = SCA_PCR_PR2; 1278 sca->dmer = SCA_DMER_EN; 1279 } 1280 } 1281 1282 1283 /* 1284 * Configure the msci 1285 * 1286 * NOTE: The serial port configuration is hardcoded at the moment. 1287 */ 1288 static void 1289 ar_init_msci(struct ar_softc *sc) 1290 { 1291 msci_channel *msci; 1292 1293 msci = &sc->sca->msci[sc->scachan]; 1294 1295 if(sc->hc->bustype == AR_BUS_ISA) 1296 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1297 1298 msci->cmd = SCA_CMD_RESET; 1299 1300 msci->md0 = SCA_MD0_CRC_1 | 1301 SCA_MD0_CRC_CCITT | 1302 SCA_MD0_CRC_ENABLE | 1303 SCA_MD0_MODE_HDLC; 1304 msci->md1 = SCA_MD1_NOADDRCHK; 1305 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ; 1306 1307 /* 1308 * Acording to the manual I should give a reset after changing the 1309 * mode registers. 1310 */ 1311 msci->cmd = SCA_CMD_RXRESET; 1312 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS; 1313 1314 /* 1315 * For now all interfaces are programmed to use the RX clock for 1316 * the TX clock. 1317 */ 1318 switch(sc->hc->interface[sc->subunit]) { 1319 case AR_IFACE_V_35: 1320 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1321 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1; 1322 break; 1323 case AR_IFACE_X_21: 1324 case AR_IFACE_EIA_530: 1325 case AR_IFACE_COMBO: 1326 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1327 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1; 1328 } 1329 1330 msci->tmc = 153; /* This give 64k for loopback */ 1331 1332 /* XXX 1333 * Disable all interrupts for now. I think if you are using 1334 * the dmac you don't use these interrupts. 1335 */ 1336 msci->ie0 = 0; 1337 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */ 1338 msci->ie2 = 0; 1339 msci->fie = 0; 1340 1341 msci->sa0 = 0; 1342 msci->sa1 = 0; 1343 1344 msci->idl = 0x7E; /* XXX This is what cisco does. */ 1345 1346 /* 1347 * This is what the ARNET diags use. 1348 */ 1349 msci->rrc = 0x0E; 1350 msci->trc0 = 0x12; 1351 msci->trc1 = 0x1F; 1352 } 1353 1354 /* 1355 * Configure the rx dma controller. 1356 */ 1357 static void 1358 ar_init_rx_dmac(struct ar_softc *sc) 1359 { 1360 dmac_channel *dmac; 1361 sca_descriptor *rxd; 1362 u_int rxbuf; 1363 u_int rxda; 1364 u_int rxda_d; 1365 int x = 0; 1366 1367 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1368 1369 if(sc->hc->bustype == AR_BUS_ISA) 1370 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1371 1372 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk)); 1373 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk); 1374 1375 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) { 1376 rxda = (u_int)&rxd[1] - rxda_d; 1377 rxd->cp = (u_short)(rxda & 0xfffful); 1378 1379 x++; 1380 if(x < 6) 1381 TRC(printf("Descrp %p, data pt %x, data %x, ", 1382 rxd, rxda, rxbuf)); 1383 1384 rxd->bp = (u_short)(rxbuf & 0xfffful); 1385 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff); 1386 rxd->len = 0; 1387 rxd->stat = 0xff; /* The sca write here when it is finished. */ 1388 1389 if(x < 6) 1390 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp)); 1391 } 1392 rxd--; 1393 rxd->cp = (u_short)(sc->rxdesc & 0xfffful); 1394 1395 sc->rxhind = 0; 1396 1397 if(sc->hc->bustype == AR_BUS_ISA) 1398 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1399 1400 dmac->dsr = 0; /* Disable DMA transfer */ 1401 dmac->dcr = SCA_DCR_ABRT; 1402 1403 /* XXX maybe also SCA_DMR_CNTE */ 1404 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1405 dmac->bfl = AR_BUF_SIZ; 1406 1407 dmac->cda = (u_short)(sc->rxdesc & 0xffff); 1408 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff); 1409 1410 rxd = (sca_descriptor *)sc->rxstart; 1411 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff); 1412 1413 dmac->dir = 0xF0; 1414 1415 dmac->dsr = SCA_DSR_DE; 1416 } 1417 1418 /* 1419 * Configure the TX DMA descriptors. 1420 * Initialize the needed values and chain the descriptors. 1421 */ 1422 static void 1423 ar_init_tx_dmac(struct ar_softc *sc) 1424 { 1425 dmac_channel *dmac; 1426 struct buf_block *blkp; 1427 int blk; 1428 sca_descriptor *txd; 1429 u_int txbuf; 1430 u_int txda; 1431 u_int txda_d; 1432 1433 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1434 1435 if(sc->hc->bustype == AR_BUS_ISA) 1436 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc); 1437 1438 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1439 blkp = &sc->block[blk]; 1440 txd = (sca_descriptor *)(sc->hc->mem_start + 1441 (blkp->txdesc&sc->hc->winmsk)); 1442 txda_d = (u_int)sc->hc->mem_start - 1443 (blkp->txdesc & ~sc->hc->winmsk); 1444 1445 txbuf=blkp->txstart; 1446 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) { 1447 txda = (u_int)&txd[1] - txda_d; 1448 txd->cp = (u_short)(txda & 0xfffful); 1449 1450 txd->bp = (u_short)(txbuf & 0xfffful); 1451 txd->bpb = (u_char)((txbuf >> 16) & 0xff); 1452 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n", 1453 sc->unit, txbuf, txd->bpb, txd->bp)); 1454 txd->len = 0; 1455 txd->stat = 0; 1456 } 1457 txd--; 1458 txd->cp = (u_short)(blkp->txdesc & 0xfffful); 1459 1460 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start; 1461 TRC(printf("TX Descriptors start %x, end %x.\n", 1462 blkp->txdesc, 1463 blkp->txtail)); 1464 } 1465 1466 if(sc->hc->bustype == AR_BUS_ISA) 1467 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1468 1469 dmac->dsr = 0; /* Disable DMA */ 1470 dmac->dcr = SCA_DCR_ABRT; 1471 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1472 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF; 1473 1474 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff); 1475 } 1476 1477 1478 /* 1479 * Look through the descriptors to see if there is a complete packet 1480 * available. Stop if we get to where the sca is busy. 1481 * 1482 * Return the length and status of the packet. 1483 * Return nonzero if there is a packet available. 1484 * 1485 * NOTE: 1486 * It seems that we get the interrupt a bit early. The updateing of 1487 * descriptor values is not always completed when this is called. 1488 */ 1489 static int 1490 ar_packet_avail(struct ar_softc *sc, 1491 int *len, 1492 u_char *rxstat) 1493 { 1494 dmac_channel *dmac; 1495 sca_descriptor *rxdesc; 1496 sca_descriptor *endp; 1497 sca_descriptor *cda; 1498 1499 if(sc->hc->bustype == AR_BUS_ISA) 1500 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1501 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1502 cda = (sca_descriptor *)(sc->hc->mem_start + 1503 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1504 1505 if(sc->hc->bustype == AR_BUS_ISA) 1506 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1507 rxdesc = (sca_descriptor *) 1508 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1509 endp = rxdesc; 1510 rxdesc = &rxdesc[sc->rxhind]; 1511 endp = &endp[sc->rxmax]; 1512 1513 *len = 0; 1514 1515 while(rxdesc != cda) { 1516 *len += rxdesc->len; 1517 1518 if(rxdesc->stat & SCA_DESC_EOM) { 1519 *rxstat = rxdesc->stat; 1520 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n", 1521 sc->unit, *len, *rxstat)); 1522 return (1); 1523 } 1524 1525 rxdesc++; 1526 if(rxdesc == endp) 1527 rxdesc = (sca_descriptor *) 1528 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1529 } 1530 1531 *len = 0; 1532 *rxstat = 0; 1533 return (0); 1534 } 1535 1536 1537 /* 1538 * Copy a packet from the on card memory into a provided mbuf. 1539 * Take into account that buffers wrap and that a packet may 1540 * be larger than a buffer. 1541 */ 1542 static void 1543 ar_copy_rxbuf(struct mbuf *m, 1544 struct ar_softc *sc, 1545 int len) 1546 { 1547 sca_descriptor *rxdesc; 1548 u_int rxdata; 1549 u_int rxmax; 1550 u_int off = 0; 1551 u_int tlen; 1552 1553 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ); 1554 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ); 1555 1556 rxdesc = (sca_descriptor *) 1557 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1558 rxdesc = &rxdesc[sc->rxhind]; 1559 1560 while(len) { 1561 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ; 1562 if(sc->hc->bustype == AR_BUS_ISA) 1563 ARC_SET_MEM(sc->hc->iobase, rxdata); 1564 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk), 1565 mtod(m, caddr_t) + off, 1566 tlen); 1567 1568 off += tlen; 1569 len -= tlen; 1570 1571 if(sc->hc->bustype == AR_BUS_ISA) 1572 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1573 rxdesc->len = 0; 1574 rxdesc->stat = 0xff; 1575 1576 rxdata += AR_BUF_SIZ; 1577 rxdesc++; 1578 if(rxdata == rxmax) { 1579 rxdata = sc->rxstart; 1580 rxdesc = (sca_descriptor *) 1581 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1582 } 1583 } 1584 } 1585 1586 /* 1587 * If single is set, just eat a packet. Otherwise eat everything up to 1588 * where cda points. Update pointers to point to the next packet. 1589 */ 1590 static void 1591 ar_eat_packet(struct ar_softc *sc, int single) 1592 { 1593 dmac_channel *dmac; 1594 sca_descriptor *rxdesc; 1595 sca_descriptor *endp; 1596 sca_descriptor *cda; 1597 int loopcnt = 0; 1598 u_char stat; 1599 1600 if(sc->hc->bustype == AR_BUS_ISA) 1601 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1602 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1603 cda = (sca_descriptor *)(sc->hc->mem_start + 1604 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1605 1606 /* 1607 * Loop until desc->stat == (0xff || EOM) 1608 * Clear the status and length in the descriptor. 1609 * Increment the descriptor. 1610 */ 1611 if(sc->hc->bustype == AR_BUS_ISA) 1612 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1613 rxdesc = (sca_descriptor *) 1614 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1615 endp = rxdesc; 1616 rxdesc = &rxdesc[sc->rxhind]; 1617 endp = &endp[sc->rxmax]; 1618 1619 while(rxdesc != cda) { 1620 loopcnt++; 1621 if(loopcnt > sc->rxmax) { 1622 printf("ar%d: eat pkt %d loop, cda %p, " 1623 "rxdesc %p, stat %x.\n", 1624 sc->unit, 1625 loopcnt, 1626 (void *)cda, 1627 (void *)rxdesc, 1628 rxdesc->stat); 1629 break; 1630 } 1631 1632 stat = rxdesc->stat; 1633 1634 rxdesc->len = 0; 1635 rxdesc->stat = 0xff; 1636 1637 rxdesc++; 1638 sc->rxhind++; 1639 if(rxdesc == endp) { 1640 rxdesc = (sca_descriptor *) 1641 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1642 sc->rxhind = 0; 1643 } 1644 1645 if(single && (stat == SCA_DESC_EOM)) 1646 break; 1647 } 1648 1649 /* 1650 * Update the eda to the previous descriptor. 1651 */ 1652 if(sc->hc->bustype == AR_BUS_ISA) 1653 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1654 1655 rxdesc = (sca_descriptor *)sc->rxdesc; 1656 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1657 1658 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1659 (u_short)((u_int)rxdesc & 0xffff); 1660 } 1661 1662 1663 /* 1664 * While there is packets available in the rx buffer, read them out 1665 * into mbufs and ship them off. 1666 */ 1667 static void 1668 ar_get_packets(struct ar_softc *sc) 1669 { 1670 sca_descriptor *rxdesc; 1671 struct mbuf *m = NULL; 1672 int i; 1673 int len; 1674 u_char rxstat; 1675 1676 while(ar_packet_avail(sc, &len, &rxstat)) { 1677 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat)); 1678 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 1679 MGETHDR(m, M_DONTWAIT, MT_DATA); 1680 if(m == NULL) { 1681 /* eat packet if get mbuf fail!! */ 1682 ar_eat_packet(sc, 1); 1683 continue; 1684 } 1685 #ifndef NETGRAPH 1686 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if; 1687 #else /* NETGRAPH */ 1688 m->m_pkthdr.rcvif = NULL; 1689 sc->inbytes += len; 1690 sc->inlast = 0; 1691 #endif /* NETGRAPH */ 1692 m->m_pkthdr.len = m->m_len = len; 1693 if(len > MHLEN) { 1694 MCLGET(m, M_DONTWAIT); 1695 if((m->m_flags & M_EXT) == 0) { 1696 m_freem(m); 1697 ar_eat_packet(sc, 1); 1698 continue; 1699 } 1700 } 1701 ar_copy_rxbuf(m, sc, len); 1702 #ifndef NETGRAPH 1703 if(sc->ifsppp.pp_if.if_bpf) 1704 bpf_mtap(&sc->ifsppp.pp_if, m); 1705 sppp_input(&sc->ifsppp.pp_if, m); 1706 sc->ifsppp.pp_if.if_ipackets++; 1707 #else /* NETGRAPH */ 1708 ng_queue_data(sc->hook, m, NULL); 1709 sc->ipackets++; 1710 #endif /* NETGRAPH */ 1711 1712 /* 1713 * Update the eda to the previous descriptor. 1714 */ 1715 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ; 1716 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 1717 1718 if(sc->hc->bustype == AR_BUS_ISA) 1719 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1720 1721 rxdesc = (sca_descriptor *)sc->rxdesc; 1722 rxdesc = 1723 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1724 1725 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1726 (u_short)((u_int)rxdesc & 0xffff); 1727 } else { 1728 int tries = 5; 1729 1730 while((rxstat == 0xff) && --tries) 1731 ar_packet_avail(sc, &len, &rxstat); 1732 1733 /* 1734 * It look like we get an interrupt early 1735 * sometimes and then the status is not 1736 * filled in yet. 1737 */ 1738 if(tries && (tries != 5)) 1739 continue; 1740 1741 ar_eat_packet(sc, 1); 1742 1743 #ifndef NETGRAPH 1744 sc->ifsppp.pp_if.if_ierrors++; 1745 #else /* NETGRAPH */ 1746 sc->ierrors[0]++; 1747 #endif /* NETGRAPH */ 1748 1749 if(sc->hc->bustype == AR_BUS_ISA) 1750 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1751 1752 TRCL(printf("ar%d: Receive error chan %d, " 1753 "stat %x, msci st3 %x," 1754 "rxhind %d, cda %x, eda %x.\n", 1755 sc->unit, 1756 sc->scachan, 1757 rxstat, 1758 sc->sca->msci[sc->scachan].st3, 1759 sc->rxhind, 1760 sc->sca->dmac[ 1761 DMAC_RXCH(sc->scachan)].cda, 1762 sc->sca->dmac[ 1763 DMAC_RXCH(sc->scachan)].eda)); 1764 } 1765 } 1766 } 1767 1768 1769 /* 1770 * All DMA interrupts come here. 1771 * 1772 * Each channel has two interrupts. 1773 * Interrupt A for errors and Interrupt B for normal stuff like end 1774 * of transmit or receive dmas. 1775 */ 1776 static void 1777 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1) 1778 { 1779 u_char dsr; 1780 u_char dotxstart = isr1; 1781 int mch; 1782 struct ar_softc *sc; 1783 sca_regs *sca; 1784 dmac_channel *dmac; 1785 1786 sca = hc->sca[scano]; 1787 mch = 0; 1788 /* 1789 * Shortcut if there is no interrupts for dma channel 0 or 1 1790 */ 1791 if((isr1 & 0x0F) == 0) { 1792 mch = 1; 1793 isr1 >>= 4; 1794 } 1795 1796 do { 1797 sc = &hc->sc[mch + (NCHAN * scano)]; 1798 1799 /* 1800 * Transmit channel 1801 */ 1802 if(isr1 & 0x0C) { 1803 dmac = &sca->dmac[DMAC_TXCH(mch)]; 1804 1805 if(hc->bustype == AR_BUS_ISA) 1806 ARC_SET_SCA(hc->iobase, scano); 1807 1808 dsr = dmac->dsr; 1809 dmac->dsr = dsr; 1810 1811 /* Counter overflow */ 1812 if(dsr & SCA_DSR_COF) { 1813 printf("ar%d: TX DMA Counter overflow, " 1814 "txpacket no %lu.\n", 1815 sc->unit, 1816 #ifndef NETGRAPH 1817 sc->ifsppp.pp_if.if_opackets); 1818 sc->ifsppp.pp_if.if_oerrors++; 1819 #else /* NETGRAPH */ 1820 sc->opackets); 1821 sc->oerrors++; 1822 #endif /* NETGRAPH */ 1823 } 1824 1825 /* Buffer overflow */ 1826 if(dsr & SCA_DSR_BOF) { 1827 printf("ar%d: TX DMA Buffer overflow, " 1828 "txpacket no %lu, dsr %02x, " 1829 "cda %04x, eda %04x.\n", 1830 sc->unit, 1831 #ifndef NETGRAPH 1832 sc->ifsppp.pp_if.if_opackets, 1833 #else /* NETGRAPH */ 1834 sc->opackets, 1835 #endif /* NETGRAPH */ 1836 dsr, 1837 dmac->cda, 1838 dmac->eda); 1839 #ifndef NETGRAPH 1840 sc->ifsppp.pp_if.if_oerrors++; 1841 #else /* NETGRAPH */ 1842 sc->oerrors++; 1843 #endif /* NETGRAPH */ 1844 } 1845 1846 /* End of Transfer */ 1847 if(dsr & SCA_DSR_EOT) { 1848 /* 1849 * This should be the most common case. 1850 * 1851 * Clear the IFF_OACTIVE flag. 1852 * 1853 * Call arstart to start a new transmit if 1854 * there is data to transmit. 1855 */ 1856 sc->xmit_busy = 0; 1857 #ifndef NETGRAPH 1858 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 1859 sc->ifsppp.pp_if.if_timer = 0; 1860 #else /* NETGRAPH */ 1861 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */ 1862 sc->out_dog = 0; /* XXX */ 1863 #endif /* NETGRAPH */ 1864 1865 if(sc->txb_inuse && --sc->txb_inuse) 1866 ar_xmit(sc); 1867 } 1868 } 1869 1870 /* 1871 * Receive channel 1872 */ 1873 if(isr1 & 0x03) { 1874 dmac = &sca->dmac[DMAC_RXCH(mch)]; 1875 1876 if(hc->bustype == AR_BUS_ISA) 1877 ARC_SET_SCA(hc->iobase, scano); 1878 1879 dsr = dmac->dsr; 1880 dmac->dsr = dsr; 1881 1882 TRC(printf("AR: RX DSR %x\n", dsr)); 1883 1884 /* End of frame */ 1885 if(dsr & SCA_DSR_EOM) { 1886 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;) 1887 TRC(int ind = sc->rxhind;) 1888 1889 ar_get_packets(sc); 1890 TRC( 1891 #ifndef NETGRAPH 1892 if(tt == sc->ifsppp.pp_if.if_ipackets) { 1893 #else /* NETGRAPH */ 1894 if(tt == sc->ipackets) { 1895 #endif /* NETGRAPH */ 1896 sca_descriptor *rxdesc; 1897 int i; 1898 1899 if(hc->bustype == AR_BUS_ISA) 1900 ARC_SET_SCA(hc->iobase, scano); 1901 printf("AR: RXINTR isr1 %x, dsr %x, " 1902 "no data %d pkts, orxhind %d.\n", 1903 dotxstart, 1904 dsr, 1905 tt, 1906 ind); 1907 printf("AR: rxdesc %x, rxstart %x, " 1908 "rxend %x, rxhind %d, " 1909 "rxmax %d.\n", 1910 sc->rxdesc, 1911 sc->rxstart, 1912 sc->rxend, 1913 sc->rxhind, 1914 sc->rxmax); 1915 printf("AR: cda %x, eda %x.\n", 1916 dmac->cda, 1917 dmac->eda); 1918 1919 if(sc->hc->bustype == AR_BUS_ISA) 1920 ARC_SET_MEM(sc->hc->iobase, 1921 sc->rxdesc); 1922 rxdesc = (sca_descriptor *) 1923 (sc->hc->mem_start + 1924 (sc->rxdesc & sc->hc->winmsk)); 1925 rxdesc = &rxdesc[sc->rxhind]; 1926 for(i=0;i<3;i++,rxdesc++) 1927 printf("AR: rxdesc->stat %x, " 1928 "len %d.\n", 1929 rxdesc->stat, 1930 rxdesc->len); 1931 }) 1932 } 1933 1934 /* Counter overflow */ 1935 if(dsr & SCA_DSR_COF) { 1936 printf("ar%d: RX DMA Counter overflow, " 1937 "rxpkts %lu.\n", 1938 sc->unit, 1939 #ifndef NETGRAPH 1940 sc->ifsppp.pp_if.if_ipackets); 1941 sc->ifsppp.pp_if.if_ierrors++; 1942 #else /* NETGRAPH */ 1943 sc->ipackets); 1944 sc->ierrors[1]++; 1945 #endif /* NETGRAPH */ 1946 } 1947 1948 /* Buffer overflow */ 1949 if(dsr & SCA_DSR_BOF) { 1950 if(hc->bustype == AR_BUS_ISA) 1951 ARC_SET_SCA(hc->iobase, scano); 1952 printf("ar%d: RX DMA Buffer overflow, " 1953 "rxpkts %lu, rxind %d, " 1954 "cda %x, eda %x, dsr %x.\n", 1955 sc->unit, 1956 #ifndef NETGRAPH 1957 sc->ifsppp.pp_if.if_ipackets, 1958 #else /* NETGRAPH */ 1959 sc->ipackets, 1960 #endif /* NETGRAPH */ 1961 sc->rxhind, 1962 dmac->cda, 1963 dmac->eda, 1964 dsr); 1965 /* 1966 * Make sure we eat as many as possible. 1967 * Then get the system running again. 1968 */ 1969 ar_eat_packet(sc, 0); 1970 #ifndef NETGRAPH 1971 sc->ifsppp.pp_if.if_ierrors++; 1972 #else /* NETGRAPH */ 1973 sc->ierrors[2]++; 1974 #endif /* NETGRAPH */ 1975 if(hc->bustype == AR_BUS_ISA) 1976 ARC_SET_SCA(hc->iobase, scano); 1977 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ; 1978 dmac->dsr = SCA_DSR_DE; 1979 1980 TRC(printf("ar%d: RX DMA Buffer overflow, " 1981 "rxpkts %lu, rxind %d, " 1982 "cda %x, eda %x, dsr %x. After\n", 1983 sc->unit, 1984 sc->ifsppp.pp_if.if_ipackets, 1985 sc->rxhind, 1986 dmac->cda, 1987 dmac->eda, 1988 dmac->dsr);) 1989 } 1990 1991 /* End of Transfer */ 1992 if(dsr & SCA_DSR_EOT) { 1993 /* 1994 * If this happen, it means that we are 1995 * receiving faster than what the processor 1996 * can handle. 1997 * 1998 * XXX We should enable the dma again. 1999 */ 2000 printf("ar%d: RX End of transfer, rxpkts %lu.\n", 2001 sc->unit, 2002 #ifndef NETGRAPH 2003 sc->ifsppp.pp_if.if_ipackets); 2004 sc->ifsppp.pp_if.if_ierrors++; 2005 #else /* NETGRAPH */ 2006 sc->ipackets); 2007 sc->ierrors[3]++; 2008 #endif /* NETGRAPH */ 2009 } 2010 } 2011 2012 isr1 >>= 4; 2013 2014 mch++; 2015 }while((mch<NCHAN) && isr1); 2016 2017 /* 2018 * Now that we have done all the urgent things, see if we 2019 * can fill the transmit buffers. 2020 */ 2021 for(mch = 0; mch < NCHAN; mch++) { 2022 if(dotxstart & 0x0C) { 2023 sc = &hc->sc[mch + (NCHAN * scano)]; 2024 #ifndef NETGRAPH 2025 arstart(&sc->ifsppp.pp_if); 2026 #else /* NETGRAPH */ 2027 arstart(sc); 2028 #endif /* NETGRAPH */ 2029 } 2030 dotxstart >>= 4; 2031 } 2032 } 2033 2034 static void 2035 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0) 2036 { 2037 printf("arc%d: ARINTR: MSCI\n", hc->cunit); 2038 } 2039 2040 static void 2041 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2) 2042 { 2043 printf("arc%d: ARINTR: TIMER\n", hc->cunit); 2044 } 2045 2046 2047 #ifdef NETGRAPH 2048 /***************************************** 2049 * Device timeout/watchdog routine. 2050 * called once per second. 2051 * checks to see that if activity was expected, that it hapenned. 2052 * At present we only look to see if expected output was completed. 2053 */ 2054 static void 2055 ngar_watchdog_frame(void * arg) 2056 { 2057 struct ar_softc * sc = arg; 2058 int s; 2059 int speed; 2060 2061 if(sc->running == 0) 2062 return; /* if we are not running let timeouts die */ 2063 /* 2064 * calculate the apparent throughputs 2065 * XXX a real hack 2066 */ 2067 s = splimp(); 2068 speed = sc->inbytes - sc->lastinbytes; 2069 sc->lastinbytes = sc->inbytes; 2070 if ( sc->inrate < speed ) 2071 sc->inrate = speed; 2072 speed = sc->outbytes - sc->lastoutbytes; 2073 sc->lastoutbytes = sc->outbytes; 2074 if ( sc->outrate < speed ) 2075 sc->outrate = speed; 2076 sc->inlast++; 2077 splx(s); 2078 2079 if ((sc->inlast > QUITE_A_WHILE) 2080 && (sc->out_deficit > LOTS_OF_PACKETS)) { 2081 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit); 2082 s = splimp(); 2083 ar_down(sc); 2084 ar_up(sc); 2085 sc->inlast = sc->out_deficit = 0; 2086 splx(s); 2087 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 2088 if (sc->out_dog == 0) { 2089 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n", 2090 sc->unit); 2091 s = splimp(); 2092 arwatchdog(sc); 2093 #if 0 2094 ar_down(sc); 2095 ar_up(sc); 2096 #endif 2097 splx(s); 2098 sc->inlast = sc->out_deficit = 0; 2099 } else { 2100 sc->out_dog--; 2101 } 2102 } 2103 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 2104 } 2105 2106 /*********************************************************************** 2107 * This section contains the methods for the Netgraph interface 2108 ***********************************************************************/ 2109 /* 2110 * It is not possible or allowable to create a node of this type. 2111 * If the hardware exists, it will already have created it. 2112 */ 2113 static int 2114 ngar_constructor(node_p *nodep) 2115 { 2116 return (EINVAL); 2117 } 2118 2119 /* 2120 * give our ok for a hook to be added... 2121 * If we are not running this should kick the device into life. 2122 * The hook's private info points to our stash of info about that 2123 * channel. 2124 */ 2125 static int 2126 ngar_newhook(node_p node, hook_p hook, const char *name) 2127 { 2128 struct ar_softc * sc = node->private; 2129 2130 /* 2131 * check if it's our friend the debug hook 2132 */ 2133 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) { 2134 hook->private = NULL; /* paranoid */ 2135 sc->debug_hook = hook; 2136 return (0); 2137 } 2138 2139 /* 2140 * Check for raw mode hook. 2141 */ 2142 if (strcmp(name, NG_AR_HOOK_RAW) != 0) { 2143 return (EINVAL); 2144 } 2145 hook->private = sc; 2146 sc->hook = hook; 2147 sc->datahooks++; 2148 ar_up(sc); 2149 return (0); 2150 } 2151 2152 /* 2153 * incoming messages. 2154 * Just respond to the generic TEXT_STATUS message 2155 */ 2156 static int 2157 ngar_rcvmsg(node_p node, 2158 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 2159 { 2160 struct ar_softc * sc; 2161 int error = 0; 2162 2163 sc = node->private; 2164 switch (msg->header.typecookie) { 2165 case NG_AR_COOKIE: 2166 error = EINVAL; 2167 break; 2168 case NGM_GENERIC_COOKIE: 2169 switch(msg->header.cmd) { 2170 case NGM_TEXT_STATUS: { 2171 char *arg; 2172 int pos = 0; 2173 int resplen = sizeof(struct ng_mesg) + 512; 2174 MALLOC(*resp, struct ng_mesg *, resplen, 2175 M_NETGRAPH, M_NOWAIT | M_ZERO); 2176 if (*resp == NULL) { 2177 error = ENOMEM; 2178 break; 2179 } 2180 arg = (*resp)->data; 2181 2182 /* 2183 * Put in the throughput information. 2184 */ 2185 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 2186 "highest rate seen: %ld B/S in, %ld B/S out\n", 2187 sc->inbytes, sc->outbytes, 2188 sc->inrate, sc->outrate); 2189 pos += sprintf(arg + pos, 2190 "%ld output errors\n", 2191 sc->oerrors); 2192 pos += sprintf(arg + pos, 2193 "ierrors = %ld, %ld, %ld, %ld\n", 2194 sc->ierrors[0], 2195 sc->ierrors[1], 2196 sc->ierrors[2], 2197 sc->ierrors[3]); 2198 2199 (*resp)->header.version = NG_VERSION; 2200 (*resp)->header.arglen = strlen(arg) + 1; 2201 (*resp)->header.token = msg->header.token; 2202 (*resp)->header.typecookie = NG_AR_COOKIE; 2203 (*resp)->header.cmd = msg->header.cmd; 2204 strncpy((*resp)->header.cmdstr, "status", 2205 NG_CMDSTRLEN); 2206 } 2207 break; 2208 default: 2209 error = EINVAL; 2210 break; 2211 } 2212 break; 2213 default: 2214 error = EINVAL; 2215 break; 2216 } 2217 free(msg, M_NETGRAPH); 2218 return (error); 2219 } 2220 2221 /* 2222 * get data from another node and transmit it to the correct channel 2223 */ 2224 static int 2225 ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 2226 { 2227 int s; 2228 int error = 0; 2229 struct ar_softc * sc = hook->node->private; 2230 struct ifqueue *xmitq_p; 2231 2232 /* 2233 * data doesn't come in from just anywhere (e.g control hook) 2234 */ 2235 if ( hook->private == NULL) { 2236 error = ENETDOWN; 2237 goto bad; 2238 } 2239 2240 /* 2241 * Now queue the data for when it can be sent 2242 */ 2243 if (meta && meta->priority > 0) { 2244 xmitq_p = (&sc->xmitq_hipri); 2245 } else { 2246 xmitq_p = (&sc->xmitq); 2247 } 2248 s = splimp(); 2249 if (IF_QFULL(xmitq_p)) { 2250 IF_DROP(xmitq_p); 2251 splx(s); 2252 error = ENOBUFS; 2253 goto bad; 2254 } 2255 IF_ENQUEUE(xmitq_p, m); 2256 arstart(sc); 2257 splx(s); 2258 return (0); 2259 2260 bad: 2261 /* 2262 * It was an error case. 2263 * check if we need to free the mbuf, and then return the error 2264 */ 2265 NG_FREE_DATA(m, meta); 2266 return (error); 2267 } 2268 2269 /* 2270 * do local shutdown processing.. 2271 * this node will refuse to go away, unless the hardware says to.. 2272 * don't unref the node, or remove our name. just clear our links up. 2273 */ 2274 static int 2275 ngar_rmnode(node_p node) 2276 { 2277 struct ar_softc * sc = node->private; 2278 2279 ar_down(sc); 2280 ng_cutlinks(node); 2281 node->flags &= ~NG_INVALID; /* bounce back to life */ 2282 return (0); 2283 } 2284 2285 /* already linked */ 2286 static int 2287 ngar_connect(hook_p hook) 2288 { 2289 /* be really amiable and just say "YUP that's OK by me! " */ 2290 return (0); 2291 } 2292 2293 /* 2294 * notify on hook disconnection (destruction) 2295 * 2296 * Invalidate the private data associated with this dlci. 2297 * For this type, removal of the last link resets tries to destroy the node. 2298 * As the device still exists, the shutdown method will not actually 2299 * destroy the node, but reset the device and leave it 'fresh' :) 2300 * 2301 * The node removal code will remove all references except that owned by the 2302 * driver. 2303 */ 2304 static int 2305 ngar_disconnect(hook_p hook) 2306 { 2307 struct ar_softc * sc = hook->node->private; 2308 int s; 2309 /* 2310 * If it's the data hook, then free resources etc. 2311 */ 2312 if (hook->private) { 2313 s = splimp(); 2314 sc->datahooks--; 2315 if (sc->datahooks == 0) 2316 ar_down(sc); 2317 splx(s); 2318 } else { 2319 sc->debug_hook = NULL; 2320 } 2321 return (0); 2322 } 2323 2324 /* 2325 * called during bootup 2326 * or LKM loading to put this type into the list of known modules 2327 */ 2328 static void 2329 ngar_init(void *ignored) 2330 { 2331 if (ng_newtype(&typestruct)) 2332 printf("ngar install failed\n"); 2333 ngar_done_init = 1; 2334 } 2335 #endif /* NETGRAPH */ 2336 2337 /* 2338 ********************************* END ************************************ 2339 */
Cache object: e12412748dbc68602d7c0326b230a574
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