Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ar/if_ar.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: releng/5.0/sys/dev/ar/if_ar.c 106937 2002-11-14 23:54:55Z sam $ 29 */ 30 31 /* 32 * Programming assumptions and other issues. 33 * 34 * The descriptors of a DMA channel will fit in a 16K memory window. 35 * 36 * The buffers of a transmit DMA channel will fit in a 16K memory window. 37 * 38 * Only the ISA bus cards with X.21 and V.35 is tested. 39 * 40 * When interface is going up, handshaking is set and it is only cleared 41 * when the interface is down'ed. 42 * 43 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 44 * internal/external clock, etc..... 45 * 46 */ 47 48 #include "opt_netgraph.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/mbuf.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/module.h> 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus_memio.h> 63 #include <sys/rman.h> 64 65 #include <net/if.h> 66 #ifdef NETGRAPH 67 #include <netgraph/ng_message.h> 68 #include <netgraph/netgraph.h> 69 #include <sys/syslog.h> 70 #include <dev/ar/if_ar.h> 71 #else /* NETGRAPH */ 72 #include <net/if_sppp.h> 73 #include <net/bpf.h> 74 #endif /* NETGRAPH */ 75 76 #include <machine/md_var.h> 77 78 #include <dev/ic/hd64570.h> 79 #include <dev/ar/if_arregs.h> 80 81 #ifdef TRACE 82 #define TRC(x) x 83 #else 84 #define TRC(x) 85 #endif 86 87 #define TRCL(x) x 88 89 #define PPP_HEADER_LEN 4 90 91 struct ar_softc { 92 #ifndef NETGRAPH 93 struct sppp ifsppp; 94 #endif /* NETGRAPH */ 95 int unit; /* With regards to all ar devices */ 96 int subunit; /* With regards to this card */ 97 struct ar_hardc *hc; 98 99 struct buf_block { 100 u_int txdesc; /* On card address */ 101 u_int txstart; /* On card address */ 102 u_int txend; /* On card address */ 103 u_int txtail; /* Index of first unused buffer */ 104 u_int txmax; /* number of usable buffers/descriptors */ 105 u_int txeda; /* Error descriptor addresses */ 106 }block[AR_TX_BLOCKS]; 107 108 char xmit_busy; /* Transmitter is busy */ 109 char txb_inuse; /* Number of tx blocks currently in use */ 110 u_char txb_new; /* Index to where new buffer will be added */ 111 u_char txb_next_tx; /* Index to next block ready to tx */ 112 113 u_int rxdesc; /* On card address */ 114 u_int rxstart; /* On card address */ 115 u_int rxend; /* On card address */ 116 u_int rxhind; /* Index to the head of the rx buffers. */ 117 u_int rxmax; /* number of usable buffers/descriptors */ 118 119 int scano; 120 int scachan; 121 sca_regs *sca; 122 #ifdef NETGRAPH 123 int running; /* something is attached so we are running */ 124 int dcd; /* do we have dcd? */ 125 /* ---netgraph bits --- */ 126 char nodename[NG_NODELEN + 1]; /* store our node name */ 127 int datahooks; /* number of data hooks attached */ 128 node_p node; /* netgraph node */ 129 hook_p hook; /* data hook */ 130 hook_p debug_hook; 131 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 132 struct ifqueue xmitq; /* transmit queue */ 133 int flags; /* state */ 134 #define SCF_RUNNING 0x01 /* board is active */ 135 #define SCF_OACTIVE 0x02 /* output is active */ 136 int out_dog; /* watchdog cycles output count-down */ 137 struct callout_handle handle; /* timeout(9) handle */ 138 u_long inbytes, outbytes; /* stats */ 139 u_long lastinbytes, lastoutbytes; /* a second ago */ 140 u_long inrate, outrate; /* highest rate seen */ 141 u_long inlast; /* last input N secs ago */ 142 u_long out_deficit; /* output since last input */ 143 u_long oerrors, ierrors[6]; 144 u_long opackets, ipackets; 145 #endif /* NETGRAPH */ 146 }; 147 148 static int next_ar_unit = 0; 149 150 #ifdef NETGRAPH 151 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 152 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 153 #define LOTS_OF_PACKETS 100 154 #endif /* NETGRAPH */ 155 156 /* 157 * This translate from irq numbers to 158 * the value that the arnet card needs 159 * in the lower part of the AR_INT_SEL 160 * register. 161 */ 162 static int irqtable[16] = { 163 0, /* 0 */ 164 0, /* 1 */ 165 0, /* 2 */ 166 1, /* 3 */ 167 0, /* 4 */ 168 2, /* 5 */ 169 0, /* 6 */ 170 3, /* 7 */ 171 0, /* 8 */ 172 0, /* 9 */ 173 4, /* 10 */ 174 5, /* 11 */ 175 6, /* 12 */ 176 0, /* 13 */ 177 0, /* 14 */ 178 7 /* 15 */ 179 }; 180 181 #ifndef NETGRAPH 182 MODULE_DEPEND(if_ar, sppp, 1, 1, 1); 183 #else 184 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1); 185 #endif 186 187 static void arintr(void *arg); 188 static void ar_xmit(struct ar_softc *sc); 189 #ifndef NETGRAPH 190 static void arstart(struct ifnet *ifp); 191 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 192 static void arwatchdog(struct ifnet *ifp); 193 #else /* NETGRAPH */ 194 static void arstart(struct ar_softc *sc); 195 static void arwatchdog(struct ar_softc *sc); 196 #endif /* NETGRAPH */ 197 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat); 198 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len); 199 static void ar_eat_packet(struct ar_softc *sc, int single); 200 static void ar_get_packets(struct ar_softc *sc); 201 202 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel); 203 static void ar_up(struct ar_softc *sc); 204 static void ar_down(struct ar_softc *sc); 205 static void arc_init(struct ar_hardc *hc); 206 static void ar_init_sca(struct ar_hardc *hc, int scano); 207 static void ar_init_msci(struct ar_softc *sc); 208 static void ar_init_rx_dmac(struct ar_softc *sc); 209 static void ar_init_tx_dmac(struct ar_softc *sc); 210 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr); 211 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr); 212 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr); 213 214 #ifdef NETGRAPH 215 static void ngar_watchdog_frame(void * arg); 216 static void ngar_init(void* ignored); 217 218 static ng_constructor_t ngar_constructor; 219 static ng_rcvmsg_t ngar_rcvmsg; 220 static ng_shutdown_t ngar_shutdown; 221 static ng_newhook_t ngar_newhook; 222 /*static ng_findhook_t ngar_findhook; */ 223 static ng_connect_t ngar_connect; 224 static ng_rcvdata_t ngar_rcvdata; 225 static ng_disconnect_t ngar_disconnect; 226 227 static struct ng_type typestruct = { 228 NG_ABI_VERSION, 229 NG_AR_NODE_TYPE, 230 NULL, 231 ngar_constructor, 232 ngar_rcvmsg, 233 ngar_shutdown, 234 ngar_newhook, 235 NULL, 236 ngar_connect, 237 ngar_rcvdata, 238 ngar_disconnect, 239 NULL 240 }; 241 242 static int ngar_done_init = 0; 243 #endif /* NETGRAPH */ 244 245 int 246 ar_attach(device_t device) 247 { 248 struct ar_hardc *hc; 249 struct ar_softc *sc; 250 #ifndef NETGRAPH 251 struct ifnet *ifp; 252 char *iface; 253 #endif /* NETGRAPH */ 254 int unit; 255 256 hc = (struct ar_hardc *)device_get_softc(device); 257 258 printf("arc%d: %uK RAM, %u ports, rev %u.\n", 259 hc->cunit, 260 hc->memsize/1024, 261 hc->numports, 262 hc->revision); 263 264 arc_init(hc); 265 266 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, 267 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0) 268 return (1); 269 270 sc = hc->sc; 271 272 for(unit=0;unit<hc->numports;unit+=NCHAN) 273 ar_init_sca(hc, unit / NCHAN); 274 275 /* 276 * Now configure each port on the card. 277 */ 278 for(unit=0;unit<hc->numports;sc++,unit++) { 279 sc->hc = hc; 280 sc->subunit = unit; 281 sc->unit = next_ar_unit; 282 next_ar_unit++; 283 sc->scano = unit / NCHAN; 284 sc->scachan = unit%NCHAN; 285 286 ar_init_rx_dmac(sc); 287 ar_init_tx_dmac(sc); 288 ar_init_msci(sc); 289 290 #ifndef NETGRAPH 291 ifp = &sc->ifsppp.pp_if; 292 293 ifp->if_softc = sc; 294 ifp->if_unit = sc->unit; 295 ifp->if_name = "ar"; 296 ifp->if_mtu = PP_MTU; 297 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 298 ifp->if_ioctl = arioctl; 299 ifp->if_start = arstart; 300 ifp->if_watchdog = arwatchdog; 301 302 sc->ifsppp.pp_flags = PP_KEEPALIVE; 303 304 switch(hc->interface[unit]) { 305 default: iface = "UNKNOWN"; break; 306 case AR_IFACE_EIA_232: iface = "EIA-232"; break; 307 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break; 308 case AR_IFACE_EIA_530: iface = "EIA-530"; break; 309 case AR_IFACE_X_21: iface = "X.21"; break; 310 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break; 311 } 312 313 printf("ar%d: Adapter %d, port %d, interface %s.\n", 314 sc->unit, 315 hc->cunit, 316 sc->subunit, 317 iface); 318 319 sppp_attach((struct ifnet *)&sc->ifsppp); 320 if_attach(ifp); 321 322 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 323 #else /* NETGRAPH */ 324 /* 325 * we have found a node, make sure our 'type' is availabe. 326 */ 327 if (ngar_done_init == 0) ngar_init(NULL); 328 if (ng_make_node_common(&typestruct, &sc->node) != 0) 329 return (1); 330 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 331 if (ng_name_node(sc->node, sc->nodename)) { 332 NG_NODE_UNREF(sc->node); /* drop it again */ 333 return (1); 334 } 335 NG_NODE_SET_PRIVATE(sc->node, sc); 336 callout_handle_init(&sc->handle); 337 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 338 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 339 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF); 340 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL, 341 MTX_DEF); 342 sc->running = 0; 343 #endif /* NETGRAPH */ 344 } 345 346 if(hc->bustype == AR_BUS_ISA) 347 ARC_SET_OFF(hc->iobase); 348 349 return (0); 350 } 351 352 int 353 ar_detach(device_t device) 354 { 355 device_t parent = device_get_parent(device); 356 struct ar_hardc *hc = device_get_softc(device); 357 358 if (hc->intr_cookie != NULL) { 359 if (BUS_TEARDOWN_INTR(parent, device, 360 hc->res_irq, hc->intr_cookie) != 0) { 361 printf("intr teardown failed.. continuing\n"); 362 } 363 hc->intr_cookie = NULL; 364 } 365 366 /* 367 * deallocate any system resources we may have 368 * allocated on behalf of this driver. 369 */ 370 FREE(hc->sc, M_DEVBUF); 371 hc->sc = NULL; 372 hc->mem_start = NULL; 373 return (ar_deallocate_resources(device)); 374 } 375 376 int 377 ar_allocate_ioport(device_t device, int rid, u_long size) 378 { 379 struct ar_hardc *hc = device_get_softc(device); 380 381 hc->rid_ioport = rid; 382 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, 383 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); 384 if (hc->res_ioport == NULL) { 385 goto errexit; 386 } 387 return (0); 388 389 errexit: 390 ar_deallocate_resources(device); 391 return (ENXIO); 392 } 393 394 int 395 ar_allocate_irq(device_t device, int rid, u_long size) 396 { 397 struct ar_hardc *hc = device_get_softc(device); 398 399 hc->rid_irq = rid; 400 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ, 401 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE); 402 if (hc->res_irq == NULL) { 403 goto errexit; 404 } 405 return (0); 406 407 errexit: 408 ar_deallocate_resources(device); 409 return (ENXIO); 410 } 411 412 int 413 ar_allocate_memory(device_t device, int rid, u_long size) 414 { 415 struct ar_hardc *hc = device_get_softc(device); 416 417 hc->rid_memory = rid; 418 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 419 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); 420 if (hc->res_memory == NULL) { 421 goto errexit; 422 } 423 return (0); 424 425 errexit: 426 ar_deallocate_resources(device); 427 return (ENXIO); 428 } 429 430 int 431 ar_allocate_plx_memory(device_t device, int rid, u_long size) 432 { 433 struct ar_hardc *hc = device_get_softc(device); 434 435 hc->rid_plx_memory = rid; 436 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 437 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); 438 if (hc->res_plx_memory == NULL) { 439 goto errexit; 440 } 441 return (0); 442 443 errexit: 444 ar_deallocate_resources(device); 445 return (ENXIO); 446 } 447 448 int 449 ar_deallocate_resources(device_t device) 450 { 451 struct ar_hardc *hc = device_get_softc(device); 452 453 if (hc->res_irq != 0) { 454 bus_deactivate_resource(device, SYS_RES_IRQ, 455 hc->rid_irq, hc->res_irq); 456 bus_release_resource(device, SYS_RES_IRQ, 457 hc->rid_irq, hc->res_irq); 458 hc->res_irq = 0; 459 } 460 if (hc->res_ioport != 0) { 461 bus_deactivate_resource(device, SYS_RES_IOPORT, 462 hc->rid_ioport, hc->res_ioport); 463 bus_release_resource(device, SYS_RES_IOPORT, 464 hc->rid_ioport, hc->res_ioport); 465 hc->res_ioport = 0; 466 } 467 if (hc->res_memory != 0) { 468 bus_deactivate_resource(device, SYS_RES_MEMORY, 469 hc->rid_memory, hc->res_memory); 470 bus_release_resource(device, SYS_RES_MEMORY, 471 hc->rid_memory, hc->res_memory); 472 hc->res_memory = 0; 473 } 474 if (hc->res_plx_memory != 0) { 475 bus_deactivate_resource(device, SYS_RES_MEMORY, 476 hc->rid_plx_memory, hc->res_plx_memory); 477 bus_release_resource(device, SYS_RES_MEMORY, 478 hc->rid_plx_memory, hc->res_plx_memory); 479 hc->res_plx_memory = 0; 480 } 481 return (0); 482 } 483 484 /* 485 * First figure out which SCA gave the interrupt. 486 * Process it. 487 * See if there is other interrupts pending. 488 * Repeat until there is no more interrupts. 489 */ 490 static void 491 arintr(void *arg) 492 { 493 struct ar_hardc *hc = (struct ar_hardc *)arg; 494 sca_regs *sca; 495 u_char isr0, isr1, isr2, arisr; 496 int scano; 497 498 /* XXX Use the PCI interrupt score board register later */ 499 if(hc->bustype == AR_BUS_PCI) 500 arisr = hc->orbase[AR_ISTAT * 4]; 501 else 502 arisr = inb(hc->iobase + AR_ISTAT); 503 504 while(arisr & AR_BD_INT) { 505 TRC(printf("arisr = %x\n", arisr)); 506 if(arisr & AR_INT_0) 507 scano = 0; 508 else if(arisr & AR_INT_1) 509 scano = 1; 510 else { 511 /* XXX Oops this shouldn't happen. */ 512 printf("arc%d: Interrupted with no interrupt.\n", 513 hc->cunit); 514 return; 515 } 516 sca = hc->sca[scano]; 517 518 if(hc->bustype == AR_BUS_ISA) 519 ARC_SET_SCA(hc->iobase, scano); 520 521 isr0 = sca->isr0; 522 isr1 = sca->isr1; 523 isr2 = sca->isr2; 524 525 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n", 526 hc->cunit, 527 isr0, 528 isr1, 529 isr2)); 530 if(isr0) 531 ar_msci_intr(hc, scano, isr0); 532 533 if(isr1) 534 ar_dmac_intr(hc, scano, isr1); 535 536 if(isr2) 537 ar_timer_intr(hc, scano, isr2); 538 539 /* 540 * Proccess the second sca's interrupt if available. 541 * Else see if there are any new interrupts. 542 */ 543 if((arisr & AR_INT_0) && (arisr & AR_INT_1)) 544 arisr &= ~AR_INT_0; 545 else { 546 if(hc->bustype == AR_BUS_PCI) 547 arisr = hc->orbase[AR_ISTAT * 4]; 548 else 549 arisr = inb(hc->iobase + AR_ISTAT); 550 } 551 } 552 553 if(hc->bustype == AR_BUS_ISA) 554 ARC_SET_OFF(hc->iobase); 555 } 556 557 558 /* 559 * This will only start the transmitter. It is assumed that the data 560 * is already there. It is normally called from arstart() or ar_dmac_intr(). 561 * 562 */ 563 static void 564 ar_xmit(struct ar_softc *sc) 565 { 566 #ifndef NETGRAPH 567 struct ifnet *ifp; 568 #endif /* NETGRAPH */ 569 dmac_channel *dmac; 570 571 #ifndef NETGRAPH 572 ifp = &sc->ifsppp.pp_if; 573 #endif /* NETGRAPH */ 574 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 575 576 if(sc->hc->bustype == AR_BUS_ISA) 577 ARC_SET_SCA(sc->hc->iobase, sc->scano); 578 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff); 579 580 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff); 581 dmac->dsr = SCA_DSR_DE; 582 583 sc->xmit_busy = 1; 584 585 sc->txb_next_tx++; 586 if(sc->txb_next_tx == AR_TX_BLOCKS) 587 sc->txb_next_tx = 0; 588 589 #ifndef NETGRAPH 590 ifp->if_timer = 2; /* Value in seconds. */ 591 #else /* NETGRAPH */ 592 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 593 #endif /* NETGRAPH */ 594 if(sc->hc->bustype == AR_BUS_ISA) 595 ARC_SET_OFF(sc->hc->iobase); 596 } 597 598 /* 599 * This function will be called from the upper level when a user add a 600 * packet to be send, and from the interrupt handler after a finished 601 * transmit. 602 * 603 * NOTE: it should run at spl_imp(). 604 * 605 * This function only place the data in the oncard buffers. It does not 606 * start the transmition. ar_xmit() does that. 607 * 608 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function 609 * that clears that should ensure that the transmitter and its DMA is 610 * in a "good" idle state. 611 */ 612 #ifndef NETGRAPH 613 static void 614 arstart(struct ifnet *ifp) 615 { 616 struct ar_softc *sc = ifp->if_softc; 617 #else /* NETGRAPH */ 618 static void 619 arstart(struct ar_softc *sc) 620 { 621 #endif /* NETGRAPH */ 622 int i, len, tlen; 623 struct mbuf *mtx; 624 u_char *txdata; 625 sca_descriptor *txdesc; 626 struct buf_block *blkp; 627 628 #ifndef NETGRAPH 629 if(!(ifp->if_flags & IFF_RUNNING)) 630 return; 631 #else /* NETGRAPH */ 632 /* XXX */ 633 #endif /* NETGRAPH */ 634 635 top_arstart: 636 637 /* 638 * See if we have space for more packets. 639 */ 640 if(sc->txb_inuse == AR_TX_BLOCKS) { 641 #ifndef NETGRAPH 642 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 643 #else /* NETGRAPH */ 644 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ 645 #endif /* NETGRAPH */ 646 return; 647 } 648 649 #ifndef NETGRAPH 650 mtx = sppp_dequeue(ifp); 651 #else /* NETGRAPH */ 652 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 653 if (mtx == NULL) { 654 IF_DEQUEUE(&sc->xmitq, mtx); 655 } 656 #endif /* NETGRAPH */ 657 if(!mtx) 658 return; 659 660 /* 661 * It is OK to set the memory window outside the loop because 662 * all tx buffers and descriptors are assumed to be in the same 663 * 16K window. 664 */ 665 if(sc->hc->bustype == AR_BUS_ISA) 666 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc); 667 668 /* 669 * We stay in this loop until there is nothing in the 670 * TX queue left or the tx buffer is full. 671 */ 672 i = 0; 673 blkp = &sc->block[sc->txb_new]; 674 txdesc = (sca_descriptor *) 675 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk)); 676 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk)); 677 for(;;) { 678 len = mtx->m_pkthdr.len; 679 680 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len)); 681 682 /* 683 * We can do this because the tx buffers don't wrap. 684 */ 685 m_copydata(mtx, 0, len, txdata); 686 tlen = len; 687 while(tlen > AR_BUF_SIZ) { 688 txdesc->stat = 0; 689 txdesc->len = AR_BUF_SIZ; 690 tlen -= AR_BUF_SIZ; 691 txdesc++; 692 txdata += AR_BUF_SIZ; 693 i++; 694 } 695 /* XXX Move into the loop? */ 696 txdesc->stat = SCA_DESC_EOM; 697 txdesc->len = tlen; 698 txdesc++; 699 txdata += AR_BUF_SIZ; 700 i++; 701 702 #ifndef NETGRAPH 703 BPF_MTAP(ifp, mtx); 704 m_freem(mtx); 705 ++sc->ifsppp.pp_if.if_opackets; 706 #else /* NETGRAPH */ 707 m_freem(mtx); 708 sc->outbytes += len; 709 ++sc->opackets; 710 #endif /* NETGRAPH */ 711 712 /* 713 * Check if we have space for another mbuf. 714 * XXX This is hardcoded. A packet won't be larger 715 * than 3 buffers (3 x 512). 716 */ 717 if((i + 3) >= blkp->txmax) 718 break; 719 720 #ifndef NETGRAPH 721 mtx = sppp_dequeue(ifp); 722 #else /* NETGRAPH */ 723 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 724 if (mtx == NULL) { 725 IF_DEQUEUE(&sc->xmitq, mtx); 726 } 727 #endif /* NETGRAPH */ 728 if(!mtx) 729 break; 730 } 731 732 blkp->txtail = i; 733 734 /* 735 * Mark the last descriptor, so that the SCA know where 736 * to stop. 737 */ 738 txdesc--; 739 txdesc->stat |= SCA_DESC_EOT; 740 741 txdesc = (sca_descriptor *)blkp->txdesc; 742 blkp->txeda = (u_short)((u_int)&txdesc[i]); 743 744 #if 0 745 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp); 746 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp); 747 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb); 748 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len); 749 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat); 750 #endif 751 752 sc->txb_inuse++; 753 sc->txb_new++; 754 if(sc->txb_new == AR_TX_BLOCKS) 755 sc->txb_new = 0; 756 757 if(sc->xmit_busy == 0) 758 ar_xmit(sc); 759 760 if(sc->hc->bustype == AR_BUS_ISA) 761 ARC_SET_OFF(sc->hc->iobase); 762 763 goto top_arstart; 764 } 765 766 #ifndef NETGRAPH 767 static int 768 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 769 { 770 int s, error; 771 int was_up, should_be_up; 772 struct ar_softc *sc = ifp->if_softc; 773 774 TRC(if_printf(ifp, "arioctl.\n");) 775 776 was_up = ifp->if_flags & IFF_RUNNING; 777 778 error = sppp_ioctl(ifp, cmd, data); 779 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n", 780 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);) 781 if(error) 782 return (error); 783 784 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR)) 785 return (0); 786 787 TRC(if_printf(ifp, "arioctl %s.\n", 788 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");) 789 790 s = splimp(); 791 should_be_up = ifp->if_flags & IFF_RUNNING; 792 793 if(!was_up && should_be_up) { 794 /* Interface should be up -- start it. */ 795 ar_up(sc); 796 arstart(ifp); 797 /* XXX Maybe clear the IFF_UP flag so that the link 798 * will only go up after sppp lcp and ipcp negotiation. 799 */ 800 } else if(was_up && !should_be_up) { 801 /* Interface should be down -- stop it. */ 802 ar_down(sc); 803 sppp_flush(ifp); 804 } 805 splx(s); 806 return (0); 807 } 808 #endif /* NETGRAPH */ 809 810 /* 811 * This is to catch lost tx interrupts. 812 */ 813 static void 814 #ifndef NETGRAPH 815 arwatchdog(struct ifnet *ifp) 816 { 817 struct ar_softc *sc = ifp->if_softc; 818 #else /* NETGRAPH */ 819 arwatchdog(struct ar_softc *sc) 820 { 821 #endif /* NETGRAPH */ 822 msci_channel *msci = &sc->sca->msci[sc->scachan]; 823 824 #ifndef NETGRAPH 825 if(!(ifp->if_flags & IFF_RUNNING)) 826 return; 827 #endif /* NETGRAPH */ 828 829 if(sc->hc->bustype == AR_BUS_ISA) 830 ARC_SET_SCA(sc->hc->iobase, sc->scano); 831 832 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */ 833 printf("ar%d: transmit failed, " 834 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n", 835 sc->unit, 836 msci->st0, 837 msci->st1, 838 msci->st3, 839 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr); 840 841 if(msci->st1 & SCA_ST1_UDRN) { 842 msci->cmd = SCA_CMD_TXABORT; 843 msci->cmd = SCA_CMD_TXENABLE; 844 msci->st1 = SCA_ST1_UDRN; 845 } 846 847 sc->xmit_busy = 0; 848 #ifndef NETGRAPH 849 ifp->if_flags &= ~IFF_OACTIVE; 850 #else /* NETGRAPH */ 851 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */ 852 #endif /* NETGRAPH */ 853 854 if(sc->txb_inuse && --sc->txb_inuse) 855 ar_xmit(sc); 856 857 #ifndef NETGRAPH 858 arstart(ifp); 859 #else /* NETGRAPH */ 860 arstart(sc); 861 #endif /* NETGRAPH */ 862 } 863 864 static void 865 ar_up(struct ar_softc *sc) 866 { 867 sca_regs *sca; 868 msci_channel *msci; 869 870 sca = sc->sca; 871 msci = &sca->msci[sc->scachan]; 872 873 TRC(printf("ar%d: sca %p, msci %p, ch %d\n", 874 sc->unit, sca, msci, sc->scachan)); 875 876 /* 877 * Enable transmitter and receiver. 878 * Raise DTR and RTS. 879 * Enable interrupts. 880 */ 881 if(sc->hc->bustype == AR_BUS_ISA) 882 ARC_SET_SCA(sc->hc->iobase, sc->scano); 883 884 /* XXX 885 * What about using AUTO mode in msci->md0 ??? 886 * And what about CTS/DCD etc... ? 887 */ 888 if(sc->hc->handshake & AR_SHSK_RTS) 889 msci->ctl &= ~SCA_CTL_RTS; 890 if(sc->hc->handshake & AR_SHSK_DTR) { 891 sc->hc->txc_dtr[sc->scano] &= sc->scachan ? 892 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0; 893 if(sc->hc->bustype == AR_BUS_PCI) 894 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 895 sc->hc->txc_dtr[sc->scano]; 896 else 897 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano], 898 sc->hc->txc_dtr[sc->scano]); 899 } 900 901 if(sc->scachan == 0) { 902 sca->ier0 |= 0x0F; 903 sca->ier1 |= 0x0F; 904 } else { 905 sca->ier0 |= 0xF0; 906 sca->ier1 |= 0xF0; 907 } 908 909 msci->cmd = SCA_CMD_RXENABLE; 910 if(sc->hc->bustype == AR_BUS_ISA) 911 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */ 912 msci->cmd = SCA_CMD_TXENABLE; 913 914 if(sc->hc->bustype == AR_BUS_ISA) 915 ARC_SET_OFF(sc->hc->iobase); 916 #ifdef NETGRAPH 917 untimeout(ngar_watchdog_frame, sc, sc->handle); 918 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 919 sc->running = 1; 920 #endif /* NETGRAPH */ 921 } 922 923 static void 924 ar_down(struct ar_softc *sc) 925 { 926 sca_regs *sca; 927 msci_channel *msci; 928 929 sca = sc->sca; 930 msci = &sca->msci[sc->scachan]; 931 932 #ifdef NETGRAPH 933 untimeout(ngar_watchdog_frame, sc, sc->handle); 934 sc->running = 0; 935 #endif /* NETGRAPH */ 936 /* 937 * Disable transmitter and receiver. 938 * Lower DTR and RTS. 939 * Disable interrupts. 940 */ 941 if(sc->hc->bustype == AR_BUS_ISA) 942 ARC_SET_SCA(sc->hc->iobase, sc->scano); 943 msci->cmd = SCA_CMD_RXDISABLE; 944 if(sc->hc->bustype == AR_BUS_ISA) 945 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */ 946 msci->cmd = SCA_CMD_TXDISABLE; 947 948 if(sc->hc->handshake & AR_SHSK_RTS) 949 msci->ctl |= SCA_CTL_RTS; 950 if(sc->hc->handshake & AR_SHSK_DTR) { 951 sc->hc->txc_dtr[sc->scano] |= sc->scachan ? 952 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0; 953 if(sc->hc->bustype == AR_BUS_PCI) 954 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 955 sc->hc->txc_dtr[sc->scano]; 956 else 957 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano], 958 sc->hc->txc_dtr[sc->scano]); 959 } 960 961 if(sc->scachan == 0) { 962 sca->ier0 &= ~0x0F; 963 sca->ier1 &= ~0x0F; 964 } else { 965 sca->ier0 &= ~0xF0; 966 sca->ier1 &= ~0xF0; 967 } 968 969 if(sc->hc->bustype == AR_BUS_ISA) 970 ARC_SET_OFF(sc->hc->iobase); 971 } 972 973 static int 974 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel) 975 { 976 int ctype, i, val, x; 977 volatile u_char *pimctrl; 978 979 ctype = 0; 980 val = 0; 981 982 pimctrl = hc->orbase + AR_PIMCTRL; 983 984 /* Reset the PIM */ 985 *pimctrl = 0x00; 986 *pimctrl = AR_PIM_STROBE; 987 988 /* Check if there is a PIM */ 989 *pimctrl = 0x00; 990 *pimctrl = AR_PIM_READ; 991 x = *pimctrl; 992 TRC(printf("x = %x", x)); 993 if(x & AR_PIM_DATA) { 994 printf("No PIM installed\n"); 995 return (AR_IFACE_UNKNOWN); 996 } 997 998 x = (x >> 1) & 0x01; 999 val |= x << 0; 1000 1001 /* Now read the next 15 bits */ 1002 for(i = 1; i < 16; i++) { 1003 *pimctrl = AR_PIM_READ; 1004 *pimctrl = AR_PIM_READ | AR_PIM_STROBE; 1005 x = *pimctrl; 1006 TRC(printf(" %x ", x)); 1007 x = (x >> 1) & 0x01; 1008 val |= x << i; 1009 if(i == 8 && (val & 0x000f) == 0x0004) { 1010 int ii; 1011 1012 /* Start bit */ 1013 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1014 *pimctrl = AR_PIM_A2D_DOUT; 1015 1016 /* Mode bit */ 1017 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1018 *pimctrl = AR_PIM_A2D_DOUT; 1019 1020 /* Sign bit */ 1021 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1022 *pimctrl = AR_PIM_A2D_DOUT; 1023 1024 /* Select channel */ 1025 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2); 1026 *pimctrl = ((channel & 2) << 2); 1027 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3); 1028 *pimctrl = ((channel & 1) << 3); 1029 1030 *pimctrl = AR_PIM_A2D_STROBE; 1031 1032 x = *pimctrl; 1033 if(x & AR_PIM_DATA) 1034 printf("\nOops A2D start bit not zero (%X)\n", x); 1035 1036 for(ii = 7; ii >= 0; ii--) { 1037 *pimctrl = 0x00; 1038 *pimctrl = AR_PIM_A2D_STROBE; 1039 x = *pimctrl; 1040 if(x & AR_PIM_DATA) 1041 ctype |= 1 << ii; 1042 } 1043 } 1044 } 1045 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype)); 1046 *pimctrl = AR_PIM_MODEG; 1047 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1048 if(ctype > 255) 1049 return (AR_IFACE_UNKNOWN); 1050 if(ctype > 239) 1051 return (AR_IFACE_V_35); 1052 if(ctype > 207) 1053 return (AR_IFACE_EIA_232); 1054 if(ctype > 178) 1055 return (AR_IFACE_X_21); 1056 if(ctype > 150) 1057 return (AR_IFACE_EIA_530); 1058 if(ctype > 25) 1059 return (AR_IFACE_UNKNOWN); 1060 if(ctype > 7) 1061 return (AR_IFACE_LOOPBACK); 1062 return (AR_IFACE_UNKNOWN); 1063 } 1064 1065 /* 1066 * Initialize the card, allocate memory for the ar_softc structures 1067 * and fill in the pointers. 1068 */ 1069 static void 1070 arc_init(struct ar_hardc *hc) 1071 { 1072 struct ar_softc *sc; 1073 int x; 1074 u_int chanmem; 1075 u_int bufmem; 1076 u_int next; 1077 u_int descneeded; 1078 u_char isr, mar; 1079 1080 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc), 1081 M_DEVBUF, M_WAITOK | M_ZERO); 1082 if (sc == NULL) 1083 return; 1084 hc->sc = sc; 1085 1086 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET | 1087 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1088 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1089 hc->txc_dtr_off[0] = AR_TXC_DTR0; 1090 hc->txc_dtr_off[1] = AR_TXC_DTR2; 1091 if(hc->bustype == AR_BUS_PCI) { 1092 hc->txc_dtr_off[0] *= 4; 1093 hc->txc_dtr_off[1] *= 4; 1094 } 1095 1096 /* 1097 * reset the card and wait at least 1uS. 1098 */ 1099 if(hc->bustype == AR_BUS_PCI) 1100 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET & 1101 hc->txc_dtr[0]; 1102 else 1103 outb(hc->iobase + AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & 1104 hc->txc_dtr[0]); 1105 DELAY(2); 1106 if(hc->bustype == AR_BUS_PCI) 1107 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1108 else 1109 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]); 1110 1111 if(hc->bustype == AR_BUS_ISA) { 1112 /* 1113 * Configure the card. 1114 * Mem address, irq, 1115 */ 1116 mar = kvtop(hc->mem_start) >> 16; 1117 isr = irqtable[hc->isa_irq] << 1; 1118 if(isr == 0) 1119 printf("ar%d: Warning illegal interrupt %d\n", 1120 hc->cunit, hc->isa_irq); 1121 isr = isr | ((kvtop(hc->mem_start) & 0xc000) >> 10); 1122 1123 hc->sca[0] = (sca_regs *)hc->mem_start; 1124 hc->sca[1] = (sca_regs *)hc->mem_start; 1125 1126 outb(hc->iobase + AR_MEM_SEL, mar); 1127 outb(hc->iobase + AR_INT_SEL, isr | AR_INTS_CEN); 1128 } 1129 1130 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM) 1131 for(x = 0; x < hc->numports; x++) 1132 hc->interface[x] = ar_read_pim_iface(hc, x); 1133 1134 /* 1135 * Set the TX clock direction and enable TX. 1136 */ 1137 for(x=0;x<hc->numports;x++) { 1138 switch(hc->interface[x]) { 1139 case AR_IFACE_V_35: 1140 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1141 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1142 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1143 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1; 1144 break; 1145 case AR_IFACE_EIA_530: 1146 case AR_IFACE_COMBO: 1147 case AR_IFACE_X_21: 1148 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1149 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1150 break; 1151 } 1152 } 1153 1154 if(hc->bustype == AR_BUS_PCI) 1155 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1156 else 1157 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]); 1158 if(hc->numports > NCHAN) { 1159 if(hc->bustype == AR_BUS_PCI) 1160 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1]; 1161 else 1162 outb(hc->iobase + AR_TXC_DTR2, hc->txc_dtr[1]); 1163 } 1164 1165 chanmem = hc->memsize / hc->numports; 1166 next = 0; 1167 1168 for(x=0;x<hc->numports;x++, sc++) { 1169 int blk; 1170 1171 sc->sca = hc->sca[x / NCHAN]; 1172 1173 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1174 sc->block[blk].txdesc = next; 1175 bufmem = (16 * 1024) / AR_TX_BLOCKS; 1176 descneeded = bufmem / AR_BUF_SIZ; 1177 sc->block[blk].txstart = sc->block[blk].txdesc + 1178 ((((descneeded * sizeof(sca_descriptor)) / 1179 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1180 sc->block[blk].txend = next + bufmem; 1181 sc->block[blk].txmax = 1182 (sc->block[blk].txend - sc->block[blk].txstart) 1183 / AR_BUF_SIZ; 1184 next += bufmem; 1185 1186 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, " 1187 "txend %x, txmax %d\n", 1188 x, 1189 blk, 1190 sc->block[blk].txdesc, 1191 sc->block[blk].txstart, 1192 sc->block[blk].txend, 1193 sc->block[blk].txmax)); 1194 } 1195 1196 sc->rxdesc = next; 1197 bufmem = chanmem - (bufmem * AR_TX_BLOCKS); 1198 descneeded = bufmem / AR_BUF_SIZ; 1199 sc->rxstart = sc->rxdesc + 1200 ((((descneeded * sizeof(sca_descriptor)) / 1201 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1202 sc->rxend = next + bufmem; 1203 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ; 1204 next += bufmem; 1205 TRC(printf("ar%d: rxdesc %x, rxstart %x, " 1206 "rxend %x, rxmax %d\n", 1207 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax)); 1208 } 1209 1210 if(hc->bustype == AR_BUS_PCI) 1211 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1212 } 1213 1214 1215 /* 1216 * The things done here are channel independent. 1217 * 1218 * Configure the sca waitstates. 1219 * Configure the global interrupt registers. 1220 * Enable master dma enable. 1221 */ 1222 static void 1223 ar_init_sca(struct ar_hardc *hc, int scano) 1224 { 1225 sca_regs *sca; 1226 1227 sca = hc->sca[scano]; 1228 if(hc->bustype == AR_BUS_ISA) 1229 ARC_SET_SCA(hc->iobase, scano); 1230 1231 /* 1232 * Do the wait registers. 1233 * Set everything to 0 wait states. 1234 */ 1235 sca->pabr0 = 0; 1236 sca->pabr1 = 0; 1237 sca->wcrl = 0; 1238 sca->wcrm = 0; 1239 sca->wcrh = 0; 1240 1241 /* 1242 * Configure the interrupt registers. 1243 * Most are cleared until the interface is configured. 1244 */ 1245 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */ 1246 sca->ier1 = 0x00; /* DMAC interrupts */ 1247 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */ 1248 sca->itcr = 0x00; /* Use ivr and no intr ack */ 1249 sca->ivr = 0x40; /* Fill in the interrupt vector. */ 1250 sca->imvr = 0x40; 1251 1252 /* 1253 * Configure the timers. 1254 * XXX Later 1255 */ 1256 1257 1258 /* 1259 * Set the DMA channel priority to rotate between 1260 * all four channels. 1261 * 1262 * Enable all dma channels. 1263 */ 1264 if(hc->bustype == AR_BUS_PCI) { 1265 u_char *t; 1266 1267 /* 1268 * Stupid problem with the PCI interface chip that break 1269 * things. 1270 * XXX 1271 */ 1272 t = (u_char *)sca; 1273 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2; 1274 t[AR_PCI_SCA_DMER] = SCA_DMER_EN; 1275 } else { 1276 sca->pcr = SCA_PCR_PR2; 1277 sca->dmer = SCA_DMER_EN; 1278 } 1279 } 1280 1281 1282 /* 1283 * Configure the msci 1284 * 1285 * NOTE: The serial port configuration is hardcoded at the moment. 1286 */ 1287 static void 1288 ar_init_msci(struct ar_softc *sc) 1289 { 1290 msci_channel *msci; 1291 1292 msci = &sc->sca->msci[sc->scachan]; 1293 1294 if(sc->hc->bustype == AR_BUS_ISA) 1295 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1296 1297 msci->cmd = SCA_CMD_RESET; 1298 1299 msci->md0 = SCA_MD0_CRC_1 | 1300 SCA_MD0_CRC_CCITT | 1301 SCA_MD0_CRC_ENABLE | 1302 SCA_MD0_MODE_HDLC; 1303 msci->md1 = SCA_MD1_NOADDRCHK; 1304 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ; 1305 1306 /* 1307 * Acording to the manual I should give a reset after changing the 1308 * mode registers. 1309 */ 1310 msci->cmd = SCA_CMD_RXRESET; 1311 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS; 1312 1313 /* 1314 * For now all interfaces are programmed to use the RX clock for 1315 * the TX clock. 1316 */ 1317 switch(sc->hc->interface[sc->subunit]) { 1318 case AR_IFACE_V_35: 1319 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1320 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1; 1321 break; 1322 case AR_IFACE_X_21: 1323 case AR_IFACE_EIA_530: 1324 case AR_IFACE_COMBO: 1325 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1326 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1; 1327 } 1328 1329 msci->tmc = 153; /* This give 64k for loopback */ 1330 1331 /* XXX 1332 * Disable all interrupts for now. I think if you are using 1333 * the dmac you don't use these interrupts. 1334 */ 1335 msci->ie0 = 0; 1336 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */ 1337 msci->ie2 = 0; 1338 msci->fie = 0; 1339 1340 msci->sa0 = 0; 1341 msci->sa1 = 0; 1342 1343 msci->idl = 0x7E; /* XXX This is what cisco does. */ 1344 1345 /* 1346 * This is what the ARNET diags use. 1347 */ 1348 msci->rrc = 0x0E; 1349 msci->trc0 = 0x12; 1350 msci->trc1 = 0x1F; 1351 } 1352 1353 /* 1354 * Configure the rx dma controller. 1355 */ 1356 static void 1357 ar_init_rx_dmac(struct ar_softc *sc) 1358 { 1359 dmac_channel *dmac; 1360 sca_descriptor *rxd; 1361 u_int rxbuf; 1362 u_int rxda; 1363 u_int rxda_d; 1364 int x = 0; 1365 1366 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1367 1368 if(sc->hc->bustype == AR_BUS_ISA) 1369 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1370 1371 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk)); 1372 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk); 1373 1374 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) { 1375 rxda = (u_int)&rxd[1] - rxda_d; 1376 rxd->cp = (u_short)(rxda & 0xfffful); 1377 1378 x++; 1379 if(x < 6) 1380 TRC(printf("Descrp %p, data pt %x, data %x, ", 1381 rxd, rxda, rxbuf)); 1382 1383 rxd->bp = (u_short)(rxbuf & 0xfffful); 1384 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff); 1385 rxd->len = 0; 1386 rxd->stat = 0xff; /* The sca write here when it is finished. */ 1387 1388 if(x < 6) 1389 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp)); 1390 } 1391 rxd--; 1392 rxd->cp = (u_short)(sc->rxdesc & 0xfffful); 1393 1394 sc->rxhind = 0; 1395 1396 if(sc->hc->bustype == AR_BUS_ISA) 1397 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1398 1399 dmac->dsr = 0; /* Disable DMA transfer */ 1400 dmac->dcr = SCA_DCR_ABRT; 1401 1402 /* XXX maybe also SCA_DMR_CNTE */ 1403 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1404 dmac->bfl = AR_BUF_SIZ; 1405 1406 dmac->cda = (u_short)(sc->rxdesc & 0xffff); 1407 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff); 1408 1409 rxd = (sca_descriptor *)sc->rxstart; 1410 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff); 1411 1412 dmac->dir = 0xF0; 1413 1414 dmac->dsr = SCA_DSR_DE; 1415 } 1416 1417 /* 1418 * Configure the TX DMA descriptors. 1419 * Initialize the needed values and chain the descriptors. 1420 */ 1421 static void 1422 ar_init_tx_dmac(struct ar_softc *sc) 1423 { 1424 dmac_channel *dmac; 1425 struct buf_block *blkp; 1426 int blk; 1427 sca_descriptor *txd; 1428 u_int txbuf; 1429 u_int txda; 1430 u_int txda_d; 1431 1432 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1433 1434 if(sc->hc->bustype == AR_BUS_ISA) 1435 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc); 1436 1437 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1438 blkp = &sc->block[blk]; 1439 txd = (sca_descriptor *)(sc->hc->mem_start + 1440 (blkp->txdesc&sc->hc->winmsk)); 1441 txda_d = (u_int)sc->hc->mem_start - 1442 (blkp->txdesc & ~sc->hc->winmsk); 1443 1444 txbuf=blkp->txstart; 1445 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) { 1446 txda = (u_int)&txd[1] - txda_d; 1447 txd->cp = (u_short)(txda & 0xfffful); 1448 1449 txd->bp = (u_short)(txbuf & 0xfffful); 1450 txd->bpb = (u_char)((txbuf >> 16) & 0xff); 1451 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n", 1452 sc->unit, txbuf, txd->bpb, txd->bp)); 1453 txd->len = 0; 1454 txd->stat = 0; 1455 } 1456 txd--; 1457 txd->cp = (u_short)(blkp->txdesc & 0xfffful); 1458 1459 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start; 1460 TRC(printf("TX Descriptors start %x, end %x.\n", 1461 blkp->txdesc, 1462 blkp->txtail)); 1463 } 1464 1465 if(sc->hc->bustype == AR_BUS_ISA) 1466 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1467 1468 dmac->dsr = 0; /* Disable DMA */ 1469 dmac->dcr = SCA_DCR_ABRT; 1470 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1471 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF; 1472 1473 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff); 1474 } 1475 1476 1477 /* 1478 * Look through the descriptors to see if there is a complete packet 1479 * available. Stop if we get to where the sca is busy. 1480 * 1481 * Return the length and status of the packet. 1482 * Return nonzero if there is a packet available. 1483 * 1484 * NOTE: 1485 * It seems that we get the interrupt a bit early. The updateing of 1486 * descriptor values is not always completed when this is called. 1487 */ 1488 static int 1489 ar_packet_avail(struct ar_softc *sc, 1490 int *len, 1491 u_char *rxstat) 1492 { 1493 dmac_channel *dmac; 1494 sca_descriptor *rxdesc; 1495 sca_descriptor *endp; 1496 sca_descriptor *cda; 1497 1498 if(sc->hc->bustype == AR_BUS_ISA) 1499 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1500 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1501 cda = (sca_descriptor *)(sc->hc->mem_start + 1502 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1503 1504 if(sc->hc->bustype == AR_BUS_ISA) 1505 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1506 rxdesc = (sca_descriptor *) 1507 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1508 endp = rxdesc; 1509 rxdesc = &rxdesc[sc->rxhind]; 1510 endp = &endp[sc->rxmax]; 1511 1512 *len = 0; 1513 1514 while(rxdesc != cda) { 1515 *len += rxdesc->len; 1516 1517 if(rxdesc->stat & SCA_DESC_EOM) { 1518 *rxstat = rxdesc->stat; 1519 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n", 1520 sc->unit, *len, *rxstat)); 1521 return (1); 1522 } 1523 1524 rxdesc++; 1525 if(rxdesc == endp) 1526 rxdesc = (sca_descriptor *) 1527 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1528 } 1529 1530 *len = 0; 1531 *rxstat = 0; 1532 return (0); 1533 } 1534 1535 1536 /* 1537 * Copy a packet from the on card memory into a provided mbuf. 1538 * Take into account that buffers wrap and that a packet may 1539 * be larger than a buffer. 1540 */ 1541 static void 1542 ar_copy_rxbuf(struct mbuf *m, 1543 struct ar_softc *sc, 1544 int len) 1545 { 1546 sca_descriptor *rxdesc; 1547 u_int rxdata; 1548 u_int rxmax; 1549 u_int off = 0; 1550 u_int tlen; 1551 1552 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ); 1553 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ); 1554 1555 rxdesc = (sca_descriptor *) 1556 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1557 rxdesc = &rxdesc[sc->rxhind]; 1558 1559 while(len) { 1560 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ; 1561 if(sc->hc->bustype == AR_BUS_ISA) 1562 ARC_SET_MEM(sc->hc->iobase, rxdata); 1563 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk), 1564 mtod(m, caddr_t) + off, 1565 tlen); 1566 1567 off += tlen; 1568 len -= tlen; 1569 1570 if(sc->hc->bustype == AR_BUS_ISA) 1571 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1572 rxdesc->len = 0; 1573 rxdesc->stat = 0xff; 1574 1575 rxdata += AR_BUF_SIZ; 1576 rxdesc++; 1577 if(rxdata == rxmax) { 1578 rxdata = sc->rxstart; 1579 rxdesc = (sca_descriptor *) 1580 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1581 } 1582 } 1583 } 1584 1585 /* 1586 * If single is set, just eat a packet. Otherwise eat everything up to 1587 * where cda points. Update pointers to point to the next packet. 1588 */ 1589 static void 1590 ar_eat_packet(struct ar_softc *sc, int single) 1591 { 1592 dmac_channel *dmac; 1593 sca_descriptor *rxdesc; 1594 sca_descriptor *endp; 1595 sca_descriptor *cda; 1596 int loopcnt = 0; 1597 u_char stat; 1598 1599 if(sc->hc->bustype == AR_BUS_ISA) 1600 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1601 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1602 cda = (sca_descriptor *)(sc->hc->mem_start + 1603 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1604 1605 /* 1606 * Loop until desc->stat == (0xff || EOM) 1607 * Clear the status and length in the descriptor. 1608 * Increment the descriptor. 1609 */ 1610 if(sc->hc->bustype == AR_BUS_ISA) 1611 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc); 1612 rxdesc = (sca_descriptor *) 1613 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1614 endp = rxdesc; 1615 rxdesc = &rxdesc[sc->rxhind]; 1616 endp = &endp[sc->rxmax]; 1617 1618 while(rxdesc != cda) { 1619 loopcnt++; 1620 if(loopcnt > sc->rxmax) { 1621 printf("ar%d: eat pkt %d loop, cda %p, " 1622 "rxdesc %p, stat %x.\n", 1623 sc->unit, 1624 loopcnt, 1625 (void *)cda, 1626 (void *)rxdesc, 1627 rxdesc->stat); 1628 break; 1629 } 1630 1631 stat = rxdesc->stat; 1632 1633 rxdesc->len = 0; 1634 rxdesc->stat = 0xff; 1635 1636 rxdesc++; 1637 sc->rxhind++; 1638 if(rxdesc == endp) { 1639 rxdesc = (sca_descriptor *) 1640 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1641 sc->rxhind = 0; 1642 } 1643 1644 if(single && (stat == SCA_DESC_EOM)) 1645 break; 1646 } 1647 1648 /* 1649 * Update the eda to the previous descriptor. 1650 */ 1651 if(sc->hc->bustype == AR_BUS_ISA) 1652 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1653 1654 rxdesc = (sca_descriptor *)sc->rxdesc; 1655 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1656 1657 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1658 (u_short)((u_int)rxdesc & 0xffff); 1659 } 1660 1661 1662 /* 1663 * While there is packets available in the rx buffer, read them out 1664 * into mbufs and ship them off. 1665 */ 1666 static void 1667 ar_get_packets(struct ar_softc *sc) 1668 { 1669 sca_descriptor *rxdesc; 1670 struct mbuf *m = NULL; 1671 int i; 1672 int len; 1673 u_char rxstat; 1674 #ifdef NETGRAPH 1675 int error; 1676 #endif 1677 1678 while(ar_packet_avail(sc, &len, &rxstat)) { 1679 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat)); 1680 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 1681 MGETHDR(m, M_DONTWAIT, MT_DATA); 1682 if(m == NULL) { 1683 /* eat packet if get mbuf fail!! */ 1684 ar_eat_packet(sc, 1); 1685 continue; 1686 } 1687 #ifndef NETGRAPH 1688 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if; 1689 #else /* NETGRAPH */ 1690 m->m_pkthdr.rcvif = NULL; 1691 sc->inbytes += len; 1692 sc->inlast = 0; 1693 #endif /* NETGRAPH */ 1694 m->m_pkthdr.len = m->m_len = len; 1695 if(len > MHLEN) { 1696 MCLGET(m, M_DONTWAIT); 1697 if((m->m_flags & M_EXT) == 0) { 1698 m_freem(m); 1699 ar_eat_packet(sc, 1); 1700 continue; 1701 } 1702 } 1703 ar_copy_rxbuf(m, sc, len); 1704 #ifndef NETGRAPH 1705 BPF_MTAP(&sc->ifsppp.pp_if, m); 1706 sppp_input(&sc->ifsppp.pp_if, m); 1707 sc->ifsppp.pp_if.if_ipackets++; 1708 #else /* NETGRAPH */ 1709 NG_SEND_DATA_ONLY(error, sc->hook, m); 1710 sc->ipackets++; 1711 #endif /* NETGRAPH */ 1712 1713 /* 1714 * Update the eda to the previous descriptor. 1715 */ 1716 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ; 1717 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 1718 1719 if(sc->hc->bustype == AR_BUS_ISA) 1720 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1721 1722 rxdesc = (sca_descriptor *)sc->rxdesc; 1723 rxdesc = 1724 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1725 1726 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1727 (u_short)((u_int)rxdesc & 0xffff); 1728 } else { 1729 int tries = 5; 1730 1731 while((rxstat == 0xff) && --tries) 1732 ar_packet_avail(sc, &len, &rxstat); 1733 1734 /* 1735 * It look like we get an interrupt early 1736 * sometimes and then the status is not 1737 * filled in yet. 1738 */ 1739 if(tries && (tries != 5)) 1740 continue; 1741 1742 ar_eat_packet(sc, 1); 1743 1744 #ifndef NETGRAPH 1745 sc->ifsppp.pp_if.if_ierrors++; 1746 #else /* NETGRAPH */ 1747 sc->ierrors[0]++; 1748 #endif /* NETGRAPH */ 1749 1750 if(sc->hc->bustype == AR_BUS_ISA) 1751 ARC_SET_SCA(sc->hc->iobase, sc->scano); 1752 1753 TRCL(printf("ar%d: Receive error chan %d, " 1754 "stat %x, msci st3 %x," 1755 "rxhind %d, cda %x, eda %x.\n", 1756 sc->unit, 1757 sc->scachan, 1758 rxstat, 1759 sc->sca->msci[sc->scachan].st3, 1760 sc->rxhind, 1761 sc->sca->dmac[ 1762 DMAC_RXCH(sc->scachan)].cda, 1763 sc->sca->dmac[ 1764 DMAC_RXCH(sc->scachan)].eda)); 1765 } 1766 } 1767 } 1768 1769 1770 /* 1771 * All DMA interrupts come here. 1772 * 1773 * Each channel has two interrupts. 1774 * Interrupt A for errors and Interrupt B for normal stuff like end 1775 * of transmit or receive dmas. 1776 */ 1777 static void 1778 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1) 1779 { 1780 u_char dsr; 1781 u_char dotxstart = isr1; 1782 int mch; 1783 struct ar_softc *sc; 1784 sca_regs *sca; 1785 dmac_channel *dmac; 1786 1787 sca = hc->sca[scano]; 1788 mch = 0; 1789 /* 1790 * Shortcut if there is no interrupts for dma channel 0 or 1 1791 */ 1792 if((isr1 & 0x0F) == 0) { 1793 mch = 1; 1794 isr1 >>= 4; 1795 } 1796 1797 do { 1798 sc = &hc->sc[mch + (NCHAN * scano)]; 1799 1800 /* 1801 * Transmit channel 1802 */ 1803 if(isr1 & 0x0C) { 1804 dmac = &sca->dmac[DMAC_TXCH(mch)]; 1805 1806 if(hc->bustype == AR_BUS_ISA) 1807 ARC_SET_SCA(hc->iobase, scano); 1808 1809 dsr = dmac->dsr; 1810 dmac->dsr = dsr; 1811 1812 /* Counter overflow */ 1813 if(dsr & SCA_DSR_COF) { 1814 printf("ar%d: TX DMA Counter overflow, " 1815 "txpacket no %lu.\n", 1816 sc->unit, 1817 #ifndef NETGRAPH 1818 sc->ifsppp.pp_if.if_opackets); 1819 sc->ifsppp.pp_if.if_oerrors++; 1820 #else /* NETGRAPH */ 1821 sc->opackets); 1822 sc->oerrors++; 1823 #endif /* NETGRAPH */ 1824 } 1825 1826 /* Buffer overflow */ 1827 if(dsr & SCA_DSR_BOF) { 1828 printf("ar%d: TX DMA Buffer overflow, " 1829 "txpacket no %lu, dsr %02x, " 1830 "cda %04x, eda %04x.\n", 1831 sc->unit, 1832 #ifndef NETGRAPH 1833 sc->ifsppp.pp_if.if_opackets, 1834 #else /* NETGRAPH */ 1835 sc->opackets, 1836 #endif /* NETGRAPH */ 1837 dsr, 1838 dmac->cda, 1839 dmac->eda); 1840 #ifndef NETGRAPH 1841 sc->ifsppp.pp_if.if_oerrors++; 1842 #else /* NETGRAPH */ 1843 sc->oerrors++; 1844 #endif /* NETGRAPH */ 1845 } 1846 1847 /* End of Transfer */ 1848 if(dsr & SCA_DSR_EOT) { 1849 /* 1850 * This should be the most common case. 1851 * 1852 * Clear the IFF_OACTIVE flag. 1853 * 1854 * Call arstart to start a new transmit if 1855 * there is data to transmit. 1856 */ 1857 sc->xmit_busy = 0; 1858 #ifndef NETGRAPH 1859 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 1860 sc->ifsppp.pp_if.if_timer = 0; 1861 #else /* NETGRAPH */ 1862 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */ 1863 sc->out_dog = 0; /* XXX */ 1864 #endif /* NETGRAPH */ 1865 1866 if(sc->txb_inuse && --sc->txb_inuse) 1867 ar_xmit(sc); 1868 } 1869 } 1870 1871 /* 1872 * Receive channel 1873 */ 1874 if(isr1 & 0x03) { 1875 dmac = &sca->dmac[DMAC_RXCH(mch)]; 1876 1877 if(hc->bustype == AR_BUS_ISA) 1878 ARC_SET_SCA(hc->iobase, scano); 1879 1880 dsr = dmac->dsr; 1881 dmac->dsr = dsr; 1882 1883 TRC(printf("AR: RX DSR %x\n", dsr)); 1884 1885 /* End of frame */ 1886 if(dsr & SCA_DSR_EOM) { 1887 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;) 1888 TRC(int ind = sc->rxhind;) 1889 1890 ar_get_packets(sc); 1891 #ifndef NETGRAPH 1892 #define IPACKETS sc->ifsppp.pp_if.if_ipackets 1893 #else /* NETGRAPH */ 1894 #define IPACKETS sc->ipackets 1895 #endif /* NETGRAPH */ 1896 TRC(if(tt == IPACKETS) { 1897 sca_descriptor *rxdesc; 1898 int i; 1899 1900 if(hc->bustype == AR_BUS_ISA) 1901 ARC_SET_SCA(hc->iobase, scano); 1902 printf("AR: RXINTR isr1 %x, dsr %x, " 1903 "no data %d pkts, orxhind %d.\n", 1904 dotxstart, 1905 dsr, 1906 tt, 1907 ind); 1908 printf("AR: rxdesc %x, rxstart %x, " 1909 "rxend %x, rxhind %d, " 1910 "rxmax %d.\n", 1911 sc->rxdesc, 1912 sc->rxstart, 1913 sc->rxend, 1914 sc->rxhind, 1915 sc->rxmax); 1916 printf("AR: cda %x, eda %x.\n", 1917 dmac->cda, 1918 dmac->eda); 1919 1920 if(sc->hc->bustype == AR_BUS_ISA) 1921 ARC_SET_MEM(sc->hc->iobase, 1922 sc->rxdesc); 1923 rxdesc = (sca_descriptor *) 1924 (sc->hc->mem_start + 1925 (sc->rxdesc & sc->hc->winmsk)); 1926 rxdesc = &rxdesc[sc->rxhind]; 1927 for(i=0;i<3;i++,rxdesc++) 1928 printf("AR: rxdesc->stat %x, " 1929 "len %d.\n", 1930 rxdesc->stat, 1931 rxdesc->len); 1932 }) 1933 } 1934 1935 /* Counter overflow */ 1936 if(dsr & SCA_DSR_COF) { 1937 printf("ar%d: RX DMA Counter overflow, " 1938 "rxpkts %lu.\n", 1939 sc->unit, 1940 #ifndef NETGRAPH 1941 sc->ifsppp.pp_if.if_ipackets); 1942 sc->ifsppp.pp_if.if_ierrors++; 1943 #else /* NETGRAPH */ 1944 sc->ipackets); 1945 sc->ierrors[1]++; 1946 #endif /* NETGRAPH */ 1947 } 1948 1949 /* Buffer overflow */ 1950 if(dsr & SCA_DSR_BOF) { 1951 if(hc->bustype == AR_BUS_ISA) 1952 ARC_SET_SCA(hc->iobase, scano); 1953 printf("ar%d: RX DMA Buffer overflow, " 1954 "rxpkts %lu, rxind %d, " 1955 "cda %x, eda %x, dsr %x.\n", 1956 sc->unit, 1957 #ifndef NETGRAPH 1958 sc->ifsppp.pp_if.if_ipackets, 1959 #else /* NETGRAPH */ 1960 sc->ipackets, 1961 #endif /* NETGRAPH */ 1962 sc->rxhind, 1963 dmac->cda, 1964 dmac->eda, 1965 dsr); 1966 /* 1967 * Make sure we eat as many as possible. 1968 * Then get the system running again. 1969 */ 1970 ar_eat_packet(sc, 0); 1971 #ifndef NETGRAPH 1972 sc->ifsppp.pp_if.if_ierrors++; 1973 #else /* NETGRAPH */ 1974 sc->ierrors[2]++; 1975 #endif /* NETGRAPH */ 1976 if(hc->bustype == AR_BUS_ISA) 1977 ARC_SET_SCA(hc->iobase, scano); 1978 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ; 1979 dmac->dsr = SCA_DSR_DE; 1980 1981 TRC(printf("ar%d: RX DMA Buffer overflow, " 1982 "rxpkts %lu, rxind %d, " 1983 "cda %x, eda %x, dsr %x. After\n", 1984 sc->unit, 1985 sc->ifsppp.pp_if.if_ipackets, 1986 sc->rxhind, 1987 dmac->cda, 1988 dmac->eda, 1989 dmac->dsr);) 1990 } 1991 1992 /* End of Transfer */ 1993 if(dsr & SCA_DSR_EOT) { 1994 /* 1995 * If this happen, it means that we are 1996 * receiving faster than what the processor 1997 * can handle. 1998 * 1999 * XXX We should enable the dma again. 2000 */ 2001 printf("ar%d: RX End of transfer, rxpkts %lu.\n", 2002 sc->unit, 2003 #ifndef NETGRAPH 2004 sc->ifsppp.pp_if.if_ipackets); 2005 sc->ifsppp.pp_if.if_ierrors++; 2006 #else /* NETGRAPH */ 2007 sc->ipackets); 2008 sc->ierrors[3]++; 2009 #endif /* NETGRAPH */ 2010 } 2011 } 2012 2013 isr1 >>= 4; 2014 2015 mch++; 2016 }while((mch<NCHAN) && isr1); 2017 2018 /* 2019 * Now that we have done all the urgent things, see if we 2020 * can fill the transmit buffers. 2021 */ 2022 for(mch = 0; mch < NCHAN; mch++) { 2023 if(dotxstart & 0x0C) { 2024 sc = &hc->sc[mch + (NCHAN * scano)]; 2025 #ifndef NETGRAPH 2026 arstart(&sc->ifsppp.pp_if); 2027 #else /* NETGRAPH */ 2028 arstart(sc); 2029 #endif /* NETGRAPH */ 2030 } 2031 dotxstart >>= 4; 2032 } 2033 } 2034 2035 static void 2036 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0) 2037 { 2038 printf("arc%d: ARINTR: MSCI\n", hc->cunit); 2039 } 2040 2041 static void 2042 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2) 2043 { 2044 printf("arc%d: ARINTR: TIMER\n", hc->cunit); 2045 } 2046 2047 2048 #ifdef NETGRAPH 2049 /***************************************** 2050 * Device timeout/watchdog routine. 2051 * called once per second. 2052 * checks to see that if activity was expected, that it hapenned. 2053 * At present we only look to see if expected output was completed. 2054 */ 2055 static void 2056 ngar_watchdog_frame(void * arg) 2057 { 2058 struct ar_softc * sc = arg; 2059 int s; 2060 int speed; 2061 2062 if(sc->running == 0) 2063 return; /* if we are not running let timeouts die */ 2064 /* 2065 * calculate the apparent throughputs 2066 * XXX a real hack 2067 */ 2068 s = splimp(); 2069 speed = sc->inbytes - sc->lastinbytes; 2070 sc->lastinbytes = sc->inbytes; 2071 if ( sc->inrate < speed ) 2072 sc->inrate = speed; 2073 speed = sc->outbytes - sc->lastoutbytes; 2074 sc->lastoutbytes = sc->outbytes; 2075 if ( sc->outrate < speed ) 2076 sc->outrate = speed; 2077 sc->inlast++; 2078 splx(s); 2079 2080 if ((sc->inlast > QUITE_A_WHILE) 2081 && (sc->out_deficit > LOTS_OF_PACKETS)) { 2082 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit); 2083 s = splimp(); 2084 ar_down(sc); 2085 ar_up(sc); 2086 sc->inlast = sc->out_deficit = 0; 2087 splx(s); 2088 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 2089 if (sc->out_dog == 0) { 2090 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n", 2091 sc->unit); 2092 s = splimp(); 2093 arwatchdog(sc); 2094 #if 0 2095 ar_down(sc); 2096 ar_up(sc); 2097 #endif 2098 splx(s); 2099 sc->inlast = sc->out_deficit = 0; 2100 } else { 2101 sc->out_dog--; 2102 } 2103 } 2104 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 2105 } 2106 2107 /*********************************************************************** 2108 * This section contains the methods for the Netgraph interface 2109 ***********************************************************************/ 2110 /* 2111 * It is not possible or allowable to create a node of this type. 2112 * If the hardware exists, it will already have created it. 2113 */ 2114 static int 2115 ngar_constructor(node_p node) 2116 { 2117 return (EINVAL); 2118 } 2119 2120 /* 2121 * give our ok for a hook to be added... 2122 * If we are not running this should kick the device into life. 2123 * The hook's private info points to our stash of info about that 2124 * channel. 2125 */ 2126 static int 2127 ngar_newhook(node_p node, hook_p hook, const char *name) 2128 { 2129 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2130 2131 /* 2132 * check if it's our friend the debug hook 2133 */ 2134 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) { 2135 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */ 2136 sc->debug_hook = hook; 2137 return (0); 2138 } 2139 2140 /* 2141 * Check for raw mode hook. 2142 */ 2143 if (strcmp(name, NG_AR_HOOK_RAW) != 0) { 2144 return (EINVAL); 2145 } 2146 NG_HOOK_SET_PRIVATE(hook, sc); 2147 sc->hook = hook; 2148 sc->datahooks++; 2149 ar_up(sc); 2150 return (0); 2151 } 2152 2153 /* 2154 * incoming messages. 2155 * Just respond to the generic TEXT_STATUS message 2156 */ 2157 static int 2158 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook) 2159 { 2160 struct ar_softc * sc; 2161 struct ng_mesg *resp = NULL; 2162 int error = 0; 2163 struct ng_mesg *msg; 2164 2165 NGI_GET_MSG(item, msg); 2166 sc = NG_NODE_PRIVATE(node); 2167 switch (msg->header.typecookie) { 2168 case NG_AR_COOKIE: 2169 error = EINVAL; 2170 break; 2171 case NGM_GENERIC_COOKIE: 2172 switch(msg->header.cmd) { 2173 case NGM_TEXT_STATUS: { 2174 char *arg; 2175 int pos = 0; 2176 2177 int resplen = sizeof(struct ng_mesg) + 512; 2178 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT); 2179 if (resp == NULL) { 2180 error = ENOMEM; 2181 break; 2182 } 2183 arg = (resp)->data; 2184 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 2185 "highest rate seen: %ld B/S in, %ld B/S out\n", 2186 sc->inbytes, sc->outbytes, 2187 sc->inrate, sc->outrate); 2188 pos += sprintf(arg + pos, 2189 "%ld output errors\n", 2190 sc->oerrors); 2191 pos += sprintf(arg + pos, 2192 "ierrors = %ld, %ld, %ld, %ld\n", 2193 sc->ierrors[0], 2194 sc->ierrors[1], 2195 sc->ierrors[2], 2196 sc->ierrors[3]); 2197 2198 resp->header.arglen = pos + 1; 2199 break; 2200 } 2201 default: 2202 error = EINVAL; 2203 break; 2204 } 2205 break; 2206 default: 2207 error = EINVAL; 2208 break; 2209 } 2210 /* Take care of synchronous response, if any */ 2211 NG_RESPOND_MSG(error, node, item, resp); 2212 NG_FREE_MSG(msg); 2213 return (error); 2214 } 2215 2216 /* 2217 * get data from another node and transmit it to the correct channel 2218 */ 2219 static int 2220 ngar_rcvdata(hook_p hook, item_p item) 2221 { 2222 int s; 2223 int error = 0; 2224 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2225 struct ifqueue *xmitq_p; 2226 struct mbuf *m; 2227 meta_p meta; 2228 2229 NGI_GET_M(item, m); 2230 NGI_GET_META(item, meta); 2231 NG_FREE_ITEM(item); 2232 /* 2233 * data doesn't come in from just anywhere (e.g control hook) 2234 */ 2235 if ( NG_HOOK_PRIVATE(hook) == NULL) { 2236 error = ENETDOWN; 2237 goto bad; 2238 } 2239 2240 /* 2241 * Now queue the data for when it can be sent 2242 */ 2243 if (meta && meta->priority > 0) { 2244 xmitq_p = (&sc->xmitq_hipri); 2245 } else { 2246 xmitq_p = (&sc->xmitq); 2247 } 2248 s = splimp(); 2249 IF_LOCK(xmitq_p); 2250 if (_IF_QFULL(xmitq_p)) { 2251 _IF_DROP(xmitq_p); 2252 IF_UNLOCK(xmitq_p); 2253 splx(s); 2254 error = ENOBUFS; 2255 goto bad; 2256 } 2257 _IF_ENQUEUE(xmitq_p, m); 2258 IF_UNLOCK(xmitq_p); 2259 arstart(sc); 2260 splx(s); 2261 return (0); 2262 2263 bad: 2264 /* 2265 * It was an error case. 2266 * check if we need to free the mbuf, and then return the error 2267 */ 2268 NG_FREE_M(m); 2269 NG_FREE_META(meta); 2270 return (error); 2271 } 2272 2273 /* 2274 * do local shutdown processing.. 2275 * this node will refuse to go away, unless the hardware says to.. 2276 * don't unref the node, or remove our name. just clear our links up. 2277 */ 2278 static int 2279 ngar_shutdown(node_p node) 2280 { 2281 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2282 2283 ar_down(sc); 2284 NG_NODE_UNREF(node); 2285 /* XXX need to drain the output queues! */ 2286 2287 /* The node is dead, long live the node! */ 2288 /* stolen from the attach routine */ 2289 if (ng_make_node_common(&typestruct, &sc->node) != 0) 2290 return (0); 2291 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 2292 if (ng_name_node(sc->node, sc->nodename)) { 2293 sc->node = NULL; 2294 printf("node naming failed\n"); 2295 NG_NODE_UNREF(sc->node); /* node dissappears */ 2296 return (0); 2297 } 2298 NG_NODE_SET_PRIVATE(sc->node, sc); 2299 sc->running = 0; 2300 return (0); 2301 } 2302 2303 /* already linked */ 2304 static int 2305 ngar_connect(hook_p hook) 2306 { 2307 /* probably not at splnet, force outward queueing */ 2308 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 2309 /* be really amiable and just say "YUP that's OK by me! " */ 2310 return (0); 2311 } 2312 2313 /* 2314 * notify on hook disconnection (destruction) 2315 * 2316 * Invalidate the private data associated with this dlci. 2317 * For this type, removal of the last link resets tries to destroy the node. 2318 * As the device still exists, the shutdown method will not actually 2319 * destroy the node, but reset the device and leave it 'fresh' :) 2320 * 2321 * The node removal code will remove all references except that owned by the 2322 * driver. 2323 */ 2324 static int 2325 ngar_disconnect(hook_p hook) 2326 { 2327 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2328 int s; 2329 /* 2330 * If it's the data hook, then free resources etc. 2331 */ 2332 if (NG_HOOK_PRIVATE(hook)) { 2333 s = splimp(); 2334 sc->datahooks--; 2335 if (sc->datahooks == 0) 2336 ar_down(sc); 2337 splx(s); 2338 } else { 2339 sc->debug_hook = NULL; 2340 } 2341 return (0); 2342 } 2343 2344 /* 2345 * called during bootup 2346 * or LKM loading to put this type into the list of known modules 2347 */ 2348 static void 2349 ngar_init(void *ignored) 2350 { 2351 if (ng_newtype(&typestruct)) 2352 printf("ngar install failed\n"); 2353 ngar_done_init = 1; 2354 } 2355 #endif /* NETGRAPH */ 2356 2357 /* 2358 ********************************* END ************************************ 2359 */
Cache object: d2cff91a53dcf9af3bf37b515faa1792
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]