Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ar/if_ar.c
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1 /* 2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: releng/5.1/sys/dev/ar/if_ar.c 113905 2003-04-23 15:40:11Z jhay $ 29 */ 30 31 /* 32 * Programming assumptions and other issues. 33 * 34 * The descriptors of a DMA channel will fit in a 16K memory window. 35 * 36 * The buffers of a transmit DMA channel will fit in a 16K memory window. 37 * 38 * Only the ISA bus cards with X.21 and V.35 is tested. 39 * 40 * When interface is going up, handshaking is set and it is only cleared 41 * when the interface is down'ed. 42 * 43 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 44 * internal/external clock, etc..... 45 * 46 */ 47 48 #include "opt_netgraph.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/mbuf.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/module.h> 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus_memio.h> 63 #include <sys/rman.h> 64 65 #include <net/if.h> 66 #ifdef NETGRAPH 67 #include <netgraph/ng_message.h> 68 #include <netgraph/netgraph.h> 69 #include <sys/syslog.h> 70 #include <dev/ar/if_ar.h> 71 #else /* NETGRAPH */ 72 #include <net/if_sppp.h> 73 #include <net/bpf.h> 74 #endif /* NETGRAPH */ 75 76 #include <machine/md_var.h> 77 78 #include <dev/ic/hd64570.h> 79 #include <dev/ar/if_arregs.h> 80 81 #ifdef TRACE 82 #define TRC(x) x 83 #else 84 #define TRC(x) 85 #endif 86 87 #define TRCL(x) x 88 89 #define PPP_HEADER_LEN 4 90 91 devclass_t ar_devclass; 92 93 struct ar_softc { 94 #ifndef NETGRAPH 95 struct sppp ifsppp; 96 #endif /* NETGRAPH */ 97 int unit; /* With regards to all ar devices */ 98 int subunit; /* With regards to this card */ 99 struct ar_hardc *hc; 100 101 struct buf_block { 102 u_int txdesc; /* On card address */ 103 u_int txstart; /* On card address */ 104 u_int txend; /* On card address */ 105 u_int txtail; /* Index of first unused buffer */ 106 u_int txmax; /* number of usable buffers/descriptors */ 107 u_int txeda; /* Error descriptor addresses */ 108 }block[AR_TX_BLOCKS]; 109 110 char xmit_busy; /* Transmitter is busy */ 111 char txb_inuse; /* Number of tx blocks currently in use */ 112 u_char txb_new; /* Index to where new buffer will be added */ 113 u_char txb_next_tx; /* Index to next block ready to tx */ 114 115 u_int rxdesc; /* On card address */ 116 u_int rxstart; /* On card address */ 117 u_int rxend; /* On card address */ 118 u_int rxhind; /* Index to the head of the rx buffers. */ 119 u_int rxmax; /* number of usable buffers/descriptors */ 120 121 int scano; 122 int scachan; 123 sca_regs *sca; 124 #ifdef NETGRAPH 125 int running; /* something is attached so we are running */ 126 int dcd; /* do we have dcd? */ 127 /* ---netgraph bits --- */ 128 char nodename[NG_NODELEN + 1]; /* store our node name */ 129 int datahooks; /* number of data hooks attached */ 130 node_p node; /* netgraph node */ 131 hook_p hook; /* data hook */ 132 hook_p debug_hook; 133 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 134 struct ifqueue xmitq; /* transmit queue */ 135 int flags; /* state */ 136 #define SCF_RUNNING 0x01 /* board is active */ 137 #define SCF_OACTIVE 0x02 /* output is active */ 138 int out_dog; /* watchdog cycles output count-down */ 139 struct callout_handle handle; /* timeout(9) handle */ 140 u_long inbytes, outbytes; /* stats */ 141 u_long lastinbytes, lastoutbytes; /* a second ago */ 142 u_long inrate, outrate; /* highest rate seen */ 143 u_long inlast; /* last input N secs ago */ 144 u_long out_deficit; /* output since last input */ 145 u_long oerrors, ierrors[6]; 146 u_long opackets, ipackets; 147 #endif /* NETGRAPH */ 148 }; 149 150 static int next_ar_unit = 0; 151 152 #ifdef NETGRAPH 153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 154 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 155 #define LOTS_OF_PACKETS 100 156 #endif /* NETGRAPH */ 157 158 /* 159 * This translate from irq numbers to 160 * the value that the arnet card needs 161 * in the lower part of the AR_INT_SEL 162 * register. 163 */ 164 static int irqtable[16] = { 165 0, /* 0 */ 166 0, /* 1 */ 167 0, /* 2 */ 168 1, /* 3 */ 169 0, /* 4 */ 170 2, /* 5 */ 171 0, /* 6 */ 172 3, /* 7 */ 173 0, /* 8 */ 174 0, /* 9 */ 175 4, /* 10 */ 176 5, /* 11 */ 177 6, /* 12 */ 178 0, /* 13 */ 179 0, /* 14 */ 180 7 /* 15 */ 181 }; 182 183 #ifndef NETGRAPH 184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1); 185 #else 186 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1); 187 #endif 188 189 static void arintr(void *arg); 190 static void ar_xmit(struct ar_softc *sc); 191 #ifndef NETGRAPH 192 static void arstart(struct ifnet *ifp); 193 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 194 static void arwatchdog(struct ifnet *ifp); 195 #else /* NETGRAPH */ 196 static void arstart(struct ar_softc *sc); 197 static void arwatchdog(struct ar_softc *sc); 198 #endif /* NETGRAPH */ 199 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat); 200 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len); 201 static void ar_eat_packet(struct ar_softc *sc, int single); 202 static void ar_get_packets(struct ar_softc *sc); 203 204 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel); 205 static void ar_up(struct ar_softc *sc); 206 static void ar_down(struct ar_softc *sc); 207 static void arc_init(struct ar_hardc *hc); 208 static void ar_init_sca(struct ar_hardc *hc, int scano); 209 static void ar_init_msci(struct ar_softc *sc); 210 static void ar_init_rx_dmac(struct ar_softc *sc); 211 static void ar_init_tx_dmac(struct ar_softc *sc); 212 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr); 213 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr); 214 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr); 215 216 #ifdef NETGRAPH 217 static void ngar_watchdog_frame(void * arg); 218 static void ngar_init(void* ignored); 219 220 static ng_constructor_t ngar_constructor; 221 static ng_rcvmsg_t ngar_rcvmsg; 222 static ng_shutdown_t ngar_shutdown; 223 static ng_newhook_t ngar_newhook; 224 /*static ng_findhook_t ngar_findhook; */ 225 static ng_connect_t ngar_connect; 226 static ng_rcvdata_t ngar_rcvdata; 227 static ng_disconnect_t ngar_disconnect; 228 229 static struct ng_type typestruct = { 230 NG_ABI_VERSION, 231 NG_AR_NODE_TYPE, 232 NULL, 233 ngar_constructor, 234 ngar_rcvmsg, 235 ngar_shutdown, 236 ngar_newhook, 237 NULL, 238 ngar_connect, 239 ngar_rcvdata, 240 ngar_disconnect, 241 NULL 242 }; 243 244 static int ngar_done_init = 0; 245 #endif /* NETGRAPH */ 246 247 int 248 ar_attach(device_t device) 249 { 250 struct ar_hardc *hc; 251 struct ar_softc *sc; 252 #ifndef NETGRAPH 253 struct ifnet *ifp; 254 char *iface; 255 #endif /* NETGRAPH */ 256 int unit; 257 258 hc = (struct ar_hardc *)device_get_softc(device); 259 260 printf("arc%d: %uK RAM, %u ports, rev %u.\n", 261 hc->cunit, 262 hc->memsize/1024, 263 hc->numports, 264 hc->revision); 265 266 arc_init(hc); 267 268 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, 269 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0) 270 return (1); 271 272 sc = hc->sc; 273 274 for(unit=0;unit<hc->numports;unit+=NCHAN) 275 ar_init_sca(hc, unit / NCHAN); 276 277 /* 278 * Now configure each port on the card. 279 */ 280 for(unit=0;unit<hc->numports;sc++,unit++) { 281 sc->hc = hc; 282 sc->subunit = unit; 283 sc->unit = next_ar_unit; 284 next_ar_unit++; 285 sc->scano = unit / NCHAN; 286 sc->scachan = unit%NCHAN; 287 288 ar_init_rx_dmac(sc); 289 ar_init_tx_dmac(sc); 290 ar_init_msci(sc); 291 292 #ifndef NETGRAPH 293 ifp = &sc->ifsppp.pp_if; 294 295 ifp->if_softc = sc; 296 ifp->if_unit = sc->unit; 297 ifp->if_name = "ar"; 298 ifp->if_mtu = PP_MTU; 299 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 300 ifp->if_ioctl = arioctl; 301 ifp->if_start = arstart; 302 ifp->if_watchdog = arwatchdog; 303 304 sc->ifsppp.pp_flags = PP_KEEPALIVE; 305 306 switch(hc->interface[unit]) { 307 default: iface = "UNKNOWN"; break; 308 case AR_IFACE_EIA_232: iface = "EIA-232"; break; 309 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break; 310 case AR_IFACE_EIA_530: iface = "EIA-530"; break; 311 case AR_IFACE_X_21: iface = "X.21"; break; 312 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break; 313 } 314 315 printf("ar%d: Adapter %d, port %d, interface %s.\n", 316 sc->unit, 317 hc->cunit, 318 sc->subunit, 319 iface); 320 321 sppp_attach((struct ifnet *)&sc->ifsppp); 322 if_attach(ifp); 323 324 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 325 #else /* NETGRAPH */ 326 /* 327 * we have found a node, make sure our 'type' is availabe. 328 */ 329 if (ngar_done_init == 0) ngar_init(NULL); 330 if (ng_make_node_common(&typestruct, &sc->node) != 0) 331 return (1); 332 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 333 if (ng_name_node(sc->node, sc->nodename)) { 334 NG_NODE_UNREF(sc->node); /* drop it again */ 335 return (1); 336 } 337 NG_NODE_SET_PRIVATE(sc->node, sc); 338 callout_handle_init(&sc->handle); 339 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 340 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 341 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF); 342 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL, 343 MTX_DEF); 344 sc->running = 0; 345 #endif /* NETGRAPH */ 346 } 347 348 if(hc->bustype == AR_BUS_ISA) 349 ARC_SET_OFF(hc); 350 351 return (0); 352 } 353 354 int 355 ar_detach(device_t device) 356 { 357 device_t parent = device_get_parent(device); 358 struct ar_hardc *hc = device_get_softc(device); 359 360 if (hc->intr_cookie != NULL) { 361 if (BUS_TEARDOWN_INTR(parent, device, 362 hc->res_irq, hc->intr_cookie) != 0) { 363 printf("intr teardown failed.. continuing\n"); 364 } 365 hc->intr_cookie = NULL; 366 } 367 368 /* 369 * deallocate any system resources we may have 370 * allocated on behalf of this driver. 371 */ 372 FREE(hc->sc, M_DEVBUF); 373 hc->sc = NULL; 374 hc->mem_start = NULL; 375 return (ar_deallocate_resources(device)); 376 } 377 378 int 379 ar_allocate_ioport(device_t device, int rid, u_long size) 380 { 381 struct ar_hardc *hc = device_get_softc(device); 382 383 hc->rid_ioport = rid; 384 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, 385 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); 386 if (hc->res_ioport == NULL) { 387 goto errexit; 388 } 389 hc->bt = rman_get_bustag(hc->res_ioport); 390 hc->bh = rman_get_bushandle(hc->res_ioport); 391 392 return (0); 393 394 errexit: 395 ar_deallocate_resources(device); 396 return (ENXIO); 397 } 398 399 int 400 ar_allocate_irq(device_t device, int rid, u_long size) 401 { 402 struct ar_hardc *hc = device_get_softc(device); 403 404 hc->rid_irq = rid; 405 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ, 406 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE); 407 if (hc->res_irq == NULL) { 408 goto errexit; 409 } 410 return (0); 411 412 errexit: 413 ar_deallocate_resources(device); 414 return (ENXIO); 415 } 416 417 int 418 ar_allocate_memory(device_t device, int rid, u_long size) 419 { 420 struct ar_hardc *hc = device_get_softc(device); 421 422 hc->rid_memory = rid; 423 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 424 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); 425 if (hc->res_memory == NULL) { 426 goto errexit; 427 } 428 return (0); 429 430 errexit: 431 ar_deallocate_resources(device); 432 return (ENXIO); 433 } 434 435 int 436 ar_allocate_plx_memory(device_t device, int rid, u_long size) 437 { 438 struct ar_hardc *hc = device_get_softc(device); 439 440 hc->rid_plx_memory = rid; 441 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 442 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); 443 if (hc->res_plx_memory == NULL) { 444 goto errexit; 445 } 446 return (0); 447 448 errexit: 449 ar_deallocate_resources(device); 450 return (ENXIO); 451 } 452 453 int 454 ar_deallocate_resources(device_t device) 455 { 456 struct ar_hardc *hc = device_get_softc(device); 457 458 if (hc->res_irq != 0) { 459 bus_deactivate_resource(device, SYS_RES_IRQ, 460 hc->rid_irq, hc->res_irq); 461 bus_release_resource(device, SYS_RES_IRQ, 462 hc->rid_irq, hc->res_irq); 463 hc->res_irq = 0; 464 } 465 if (hc->res_ioport != 0) { 466 bus_deactivate_resource(device, SYS_RES_IOPORT, 467 hc->rid_ioport, hc->res_ioport); 468 bus_release_resource(device, SYS_RES_IOPORT, 469 hc->rid_ioport, hc->res_ioport); 470 hc->res_ioport = 0; 471 } 472 if (hc->res_memory != 0) { 473 bus_deactivate_resource(device, SYS_RES_MEMORY, 474 hc->rid_memory, hc->res_memory); 475 bus_release_resource(device, SYS_RES_MEMORY, 476 hc->rid_memory, hc->res_memory); 477 hc->res_memory = 0; 478 } 479 if (hc->res_plx_memory != 0) { 480 bus_deactivate_resource(device, SYS_RES_MEMORY, 481 hc->rid_plx_memory, hc->res_plx_memory); 482 bus_release_resource(device, SYS_RES_MEMORY, 483 hc->rid_plx_memory, hc->res_plx_memory); 484 hc->res_plx_memory = 0; 485 } 486 return (0); 487 } 488 489 /* 490 * First figure out which SCA gave the interrupt. 491 * Process it. 492 * See if there is other interrupts pending. 493 * Repeat until there is no more interrupts. 494 */ 495 static void 496 arintr(void *arg) 497 { 498 struct ar_hardc *hc = (struct ar_hardc *)arg; 499 sca_regs *sca; 500 u_char isr0, isr1, isr2, arisr; 501 int scano; 502 503 /* XXX Use the PCI interrupt score board register later */ 504 if(hc->bustype == AR_BUS_PCI) 505 arisr = hc->orbase[AR_ISTAT * 4]; 506 else 507 arisr = ar_inb(hc, AR_ISTAT); 508 509 while(arisr & AR_BD_INT) { 510 TRC(printf("arisr = %x\n", arisr)); 511 if(arisr & AR_INT_0) 512 scano = 0; 513 else if(arisr & AR_INT_1) 514 scano = 1; 515 else { 516 /* XXX Oops this shouldn't happen. */ 517 printf("arc%d: Interrupted with no interrupt.\n", 518 hc->cunit); 519 return; 520 } 521 sca = hc->sca[scano]; 522 523 if(hc->bustype == AR_BUS_ISA) 524 ARC_SET_SCA(hc, scano); 525 526 isr0 = sca->isr0; 527 isr1 = sca->isr1; 528 isr2 = sca->isr2; 529 530 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n", 531 hc->cunit, 532 isr0, 533 isr1, 534 isr2)); 535 if(isr0) 536 ar_msci_intr(hc, scano, isr0); 537 538 if(isr1) 539 ar_dmac_intr(hc, scano, isr1); 540 541 if(isr2) 542 ar_timer_intr(hc, scano, isr2); 543 544 /* 545 * Proccess the second sca's interrupt if available. 546 * Else see if there are any new interrupts. 547 */ 548 if((arisr & AR_INT_0) && (arisr & AR_INT_1)) 549 arisr &= ~AR_INT_0; 550 else { 551 if(hc->bustype == AR_BUS_PCI) 552 arisr = hc->orbase[AR_ISTAT * 4]; 553 else 554 arisr = ar_inb(hc, AR_ISTAT); 555 } 556 } 557 558 if(hc->bustype == AR_BUS_ISA) 559 ARC_SET_OFF(hc); 560 } 561 562 563 /* 564 * This will only start the transmitter. It is assumed that the data 565 * is already there. It is normally called from arstart() or ar_dmac_intr(). 566 * 567 */ 568 static void 569 ar_xmit(struct ar_softc *sc) 570 { 571 #ifndef NETGRAPH 572 struct ifnet *ifp; 573 #endif /* NETGRAPH */ 574 dmac_channel *dmac; 575 576 #ifndef NETGRAPH 577 ifp = &sc->ifsppp.pp_if; 578 #endif /* NETGRAPH */ 579 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 580 581 if(sc->hc->bustype == AR_BUS_ISA) 582 ARC_SET_SCA(sc->hc, sc->scano); 583 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff); 584 585 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff); 586 dmac->dsr = SCA_DSR_DE; 587 588 sc->xmit_busy = 1; 589 590 sc->txb_next_tx++; 591 if(sc->txb_next_tx == AR_TX_BLOCKS) 592 sc->txb_next_tx = 0; 593 594 #ifndef NETGRAPH 595 ifp->if_timer = 2; /* Value in seconds. */ 596 #else /* NETGRAPH */ 597 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 598 #endif /* NETGRAPH */ 599 if(sc->hc->bustype == AR_BUS_ISA) 600 ARC_SET_OFF(sc->hc); 601 } 602 603 /* 604 * This function will be called from the upper level when a user add a 605 * packet to be send, and from the interrupt handler after a finished 606 * transmit. 607 * 608 * NOTE: it should run at spl_imp(). 609 * 610 * This function only place the data in the oncard buffers. It does not 611 * start the transmition. ar_xmit() does that. 612 * 613 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function 614 * that clears that should ensure that the transmitter and its DMA is 615 * in a "good" idle state. 616 */ 617 #ifndef NETGRAPH 618 static void 619 arstart(struct ifnet *ifp) 620 { 621 struct ar_softc *sc = ifp->if_softc; 622 #else /* NETGRAPH */ 623 static void 624 arstart(struct ar_softc *sc) 625 { 626 #endif /* NETGRAPH */ 627 int i, len, tlen; 628 struct mbuf *mtx; 629 u_char *txdata; 630 sca_descriptor *txdesc; 631 struct buf_block *blkp; 632 633 #ifndef NETGRAPH 634 if(!(ifp->if_flags & IFF_RUNNING)) 635 return; 636 #else /* NETGRAPH */ 637 /* XXX */ 638 #endif /* NETGRAPH */ 639 640 top_arstart: 641 642 /* 643 * See if we have space for more packets. 644 */ 645 if(sc->txb_inuse == AR_TX_BLOCKS) { 646 #ifndef NETGRAPH 647 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 648 #else /* NETGRAPH */ 649 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ 650 #endif /* NETGRAPH */ 651 return; 652 } 653 654 #ifndef NETGRAPH 655 mtx = sppp_dequeue(ifp); 656 #else /* NETGRAPH */ 657 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 658 if (mtx == NULL) { 659 IF_DEQUEUE(&sc->xmitq, mtx); 660 } 661 #endif /* NETGRAPH */ 662 if(!mtx) 663 return; 664 665 /* 666 * It is OK to set the memory window outside the loop because 667 * all tx buffers and descriptors are assumed to be in the same 668 * 16K window. 669 */ 670 if(sc->hc->bustype == AR_BUS_ISA) 671 ARC_SET_MEM(sc->hc, sc->block[0].txdesc); 672 673 /* 674 * We stay in this loop until there is nothing in the 675 * TX queue left or the tx buffer is full. 676 */ 677 i = 0; 678 blkp = &sc->block[sc->txb_new]; 679 txdesc = (sca_descriptor *) 680 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk)); 681 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk)); 682 for(;;) { 683 len = mtx->m_pkthdr.len; 684 685 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len)); 686 687 /* 688 * We can do this because the tx buffers don't wrap. 689 */ 690 m_copydata(mtx, 0, len, txdata); 691 tlen = len; 692 while(tlen > AR_BUF_SIZ) { 693 txdesc->stat = 0; 694 txdesc->len = AR_BUF_SIZ; 695 tlen -= AR_BUF_SIZ; 696 txdesc++; 697 txdata += AR_BUF_SIZ; 698 i++; 699 } 700 /* XXX Move into the loop? */ 701 txdesc->stat = SCA_DESC_EOM; 702 txdesc->len = tlen; 703 txdesc++; 704 txdata += AR_BUF_SIZ; 705 i++; 706 707 #ifndef NETGRAPH 708 BPF_MTAP(ifp, mtx); 709 m_freem(mtx); 710 ++sc->ifsppp.pp_if.if_opackets; 711 #else /* NETGRAPH */ 712 m_freem(mtx); 713 sc->outbytes += len; 714 ++sc->opackets; 715 #endif /* NETGRAPH */ 716 717 /* 718 * Check if we have space for another mbuf. 719 * XXX This is hardcoded. A packet won't be larger 720 * than 3 buffers (3 x 512). 721 */ 722 if((i + 3) >= blkp->txmax) 723 break; 724 725 #ifndef NETGRAPH 726 mtx = sppp_dequeue(ifp); 727 #else /* NETGRAPH */ 728 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 729 if (mtx == NULL) { 730 IF_DEQUEUE(&sc->xmitq, mtx); 731 } 732 #endif /* NETGRAPH */ 733 if(!mtx) 734 break; 735 } 736 737 blkp->txtail = i; 738 739 /* 740 * Mark the last descriptor, so that the SCA know where 741 * to stop. 742 */ 743 txdesc--; 744 txdesc->stat |= SCA_DESC_EOT; 745 746 txdesc = (sca_descriptor *)blkp->txdesc; 747 blkp->txeda = (u_short)((u_int)&txdesc[i]); 748 749 #if 0 750 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp); 751 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp); 752 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb); 753 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len); 754 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat); 755 #endif 756 757 sc->txb_inuse++; 758 sc->txb_new++; 759 if(sc->txb_new == AR_TX_BLOCKS) 760 sc->txb_new = 0; 761 762 if(sc->xmit_busy == 0) 763 ar_xmit(sc); 764 765 if(sc->hc->bustype == AR_BUS_ISA) 766 ARC_SET_OFF(sc->hc); 767 768 goto top_arstart; 769 } 770 771 #ifndef NETGRAPH 772 static int 773 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 774 { 775 int s, error; 776 int was_up, should_be_up; 777 struct ar_softc *sc = ifp->if_softc; 778 779 TRC(if_printf(ifp, "arioctl.\n");) 780 781 was_up = ifp->if_flags & IFF_RUNNING; 782 783 error = sppp_ioctl(ifp, cmd, data); 784 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n", 785 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);) 786 if(error) 787 return (error); 788 789 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR)) 790 return (0); 791 792 TRC(if_printf(ifp, "arioctl %s.\n", 793 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");) 794 795 s = splimp(); 796 should_be_up = ifp->if_flags & IFF_RUNNING; 797 798 if(!was_up && should_be_up) { 799 /* Interface should be up -- start it. */ 800 ar_up(sc); 801 arstart(ifp); 802 /* XXX Maybe clear the IFF_UP flag so that the link 803 * will only go up after sppp lcp and ipcp negotiation. 804 */ 805 } else if(was_up && !should_be_up) { 806 /* Interface should be down -- stop it. */ 807 ar_down(sc); 808 sppp_flush(ifp); 809 } 810 splx(s); 811 return (0); 812 } 813 #endif /* NETGRAPH */ 814 815 /* 816 * This is to catch lost tx interrupts. 817 */ 818 static void 819 #ifndef NETGRAPH 820 arwatchdog(struct ifnet *ifp) 821 { 822 struct ar_softc *sc = ifp->if_softc; 823 #else /* NETGRAPH */ 824 arwatchdog(struct ar_softc *sc) 825 { 826 #endif /* NETGRAPH */ 827 msci_channel *msci = &sc->sca->msci[sc->scachan]; 828 829 #ifndef NETGRAPH 830 if(!(ifp->if_flags & IFF_RUNNING)) 831 return; 832 #endif /* NETGRAPH */ 833 834 if(sc->hc->bustype == AR_BUS_ISA) 835 ARC_SET_SCA(sc->hc, sc->scano); 836 837 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */ 838 printf("ar%d: transmit failed, " 839 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n", 840 sc->unit, 841 msci->st0, 842 msci->st1, 843 msci->st3, 844 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr); 845 846 if(msci->st1 & SCA_ST1_UDRN) { 847 msci->cmd = SCA_CMD_TXABORT; 848 msci->cmd = SCA_CMD_TXENABLE; 849 msci->st1 = SCA_ST1_UDRN; 850 } 851 852 sc->xmit_busy = 0; 853 #ifndef NETGRAPH 854 ifp->if_flags &= ~IFF_OACTIVE; 855 #else /* NETGRAPH */ 856 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */ 857 #endif /* NETGRAPH */ 858 859 if(sc->txb_inuse && --sc->txb_inuse) 860 ar_xmit(sc); 861 862 #ifndef NETGRAPH 863 arstart(ifp); 864 #else /* NETGRAPH */ 865 arstart(sc); 866 #endif /* NETGRAPH */ 867 } 868 869 static void 870 ar_up(struct ar_softc *sc) 871 { 872 sca_regs *sca; 873 msci_channel *msci; 874 875 sca = sc->sca; 876 msci = &sca->msci[sc->scachan]; 877 878 TRC(printf("ar%d: sca %p, msci %p, ch %d\n", 879 sc->unit, sca, msci, sc->scachan)); 880 881 /* 882 * Enable transmitter and receiver. 883 * Raise DTR and RTS. 884 * Enable interrupts. 885 */ 886 if(sc->hc->bustype == AR_BUS_ISA) 887 ARC_SET_SCA(sc->hc, sc->scano); 888 889 /* XXX 890 * What about using AUTO mode in msci->md0 ??? 891 * And what about CTS/DCD etc... ? 892 */ 893 if(sc->hc->handshake & AR_SHSK_RTS) 894 msci->ctl &= ~SCA_CTL_RTS; 895 if(sc->hc->handshake & AR_SHSK_DTR) { 896 sc->hc->txc_dtr[sc->scano] &= sc->scachan ? 897 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0; 898 if(sc->hc->bustype == AR_BUS_PCI) 899 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 900 sc->hc->txc_dtr[sc->scano]; 901 else 902 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], 903 sc->hc->txc_dtr[sc->scano]); 904 } 905 906 if(sc->scachan == 0) { 907 sca->ier0 |= 0x0F; 908 sca->ier1 |= 0x0F; 909 } else { 910 sca->ier0 |= 0xF0; 911 sca->ier1 |= 0xF0; 912 } 913 914 msci->cmd = SCA_CMD_RXENABLE; 915 if(sc->hc->bustype == AR_BUS_ISA) 916 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ 917 msci->cmd = SCA_CMD_TXENABLE; 918 919 if(sc->hc->bustype == AR_BUS_ISA) 920 ARC_SET_OFF(sc->hc); 921 #ifdef NETGRAPH 922 untimeout(ngar_watchdog_frame, sc, sc->handle); 923 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 924 sc->running = 1; 925 #endif /* NETGRAPH */ 926 } 927 928 static void 929 ar_down(struct ar_softc *sc) 930 { 931 sca_regs *sca; 932 msci_channel *msci; 933 934 sca = sc->sca; 935 msci = &sca->msci[sc->scachan]; 936 937 #ifdef NETGRAPH 938 untimeout(ngar_watchdog_frame, sc, sc->handle); 939 sc->running = 0; 940 #endif /* NETGRAPH */ 941 /* 942 * Disable transmitter and receiver. 943 * Lower DTR and RTS. 944 * Disable interrupts. 945 */ 946 if(sc->hc->bustype == AR_BUS_ISA) 947 ARC_SET_SCA(sc->hc, sc->scano); 948 msci->cmd = SCA_CMD_RXDISABLE; 949 if(sc->hc->bustype == AR_BUS_ISA) 950 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ 951 msci->cmd = SCA_CMD_TXDISABLE; 952 953 if(sc->hc->handshake & AR_SHSK_RTS) 954 msci->ctl |= SCA_CTL_RTS; 955 if(sc->hc->handshake & AR_SHSK_DTR) { 956 sc->hc->txc_dtr[sc->scano] |= sc->scachan ? 957 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0; 958 if(sc->hc->bustype == AR_BUS_PCI) 959 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 960 sc->hc->txc_dtr[sc->scano]; 961 else 962 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], 963 sc->hc->txc_dtr[sc->scano]); 964 } 965 966 if(sc->scachan == 0) { 967 sca->ier0 &= ~0x0F; 968 sca->ier1 &= ~0x0F; 969 } else { 970 sca->ier0 &= ~0xF0; 971 sca->ier1 &= ~0xF0; 972 } 973 974 if(sc->hc->bustype == AR_BUS_ISA) 975 ARC_SET_OFF(sc->hc); 976 } 977 978 static int 979 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel) 980 { 981 int ctype, i, val, x; 982 volatile u_char *pimctrl; 983 984 ctype = 0; 985 val = 0; 986 987 pimctrl = hc->orbase + AR_PIMCTRL; 988 989 /* Reset the PIM */ 990 *pimctrl = 0x00; 991 *pimctrl = AR_PIM_STROBE; 992 993 /* Check if there is a PIM */ 994 *pimctrl = 0x00; 995 *pimctrl = AR_PIM_READ; 996 x = *pimctrl; 997 TRC(printf("x = %x", x)); 998 if(x & AR_PIM_DATA) { 999 printf("No PIM installed\n"); 1000 return (AR_IFACE_UNKNOWN); 1001 } 1002 1003 x = (x >> 1) & 0x01; 1004 val |= x << 0; 1005 1006 /* Now read the next 15 bits */ 1007 for(i = 1; i < 16; i++) { 1008 *pimctrl = AR_PIM_READ; 1009 *pimctrl = AR_PIM_READ | AR_PIM_STROBE; 1010 x = *pimctrl; 1011 TRC(printf(" %x ", x)); 1012 x = (x >> 1) & 0x01; 1013 val |= x << i; 1014 if(i == 8 && (val & 0x000f) == 0x0004) { 1015 int ii; 1016 1017 /* Start bit */ 1018 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1019 *pimctrl = AR_PIM_A2D_DOUT; 1020 1021 /* Mode bit */ 1022 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1023 *pimctrl = AR_PIM_A2D_DOUT; 1024 1025 /* Sign bit */ 1026 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1027 *pimctrl = AR_PIM_A2D_DOUT; 1028 1029 /* Select channel */ 1030 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2); 1031 *pimctrl = ((channel & 2) << 2); 1032 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3); 1033 *pimctrl = ((channel & 1) << 3); 1034 1035 *pimctrl = AR_PIM_A2D_STROBE; 1036 1037 x = *pimctrl; 1038 if(x & AR_PIM_DATA) 1039 printf("\nOops A2D start bit not zero (%X)\n", x); 1040 1041 for(ii = 7; ii >= 0; ii--) { 1042 *pimctrl = 0x00; 1043 *pimctrl = AR_PIM_A2D_STROBE; 1044 x = *pimctrl; 1045 if(x & AR_PIM_DATA) 1046 ctype |= 1 << ii; 1047 } 1048 } 1049 } 1050 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype)); 1051 *pimctrl = AR_PIM_MODEG; 1052 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1053 if(ctype > 255) 1054 return (AR_IFACE_UNKNOWN); 1055 if(ctype > 239) 1056 return (AR_IFACE_V_35); 1057 if(ctype > 207) 1058 return (AR_IFACE_EIA_232); 1059 if(ctype > 178) 1060 return (AR_IFACE_X_21); 1061 if(ctype > 150) 1062 return (AR_IFACE_EIA_530); 1063 if(ctype > 25) 1064 return (AR_IFACE_UNKNOWN); 1065 if(ctype > 7) 1066 return (AR_IFACE_LOOPBACK); 1067 return (AR_IFACE_UNKNOWN); 1068 } 1069 1070 /* 1071 * Initialize the card, allocate memory for the ar_softc structures 1072 * and fill in the pointers. 1073 */ 1074 static void 1075 arc_init(struct ar_hardc *hc) 1076 { 1077 struct ar_softc *sc; 1078 int x; 1079 u_int chanmem; 1080 u_int bufmem; 1081 u_int next; 1082 u_int descneeded; 1083 u_char isr, mar; 1084 u_long memst; 1085 1086 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc), 1087 M_DEVBUF, M_WAITOK | M_ZERO); 1088 if (sc == NULL) 1089 return; 1090 hc->sc = sc; 1091 1092 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET | 1093 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1094 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1095 hc->txc_dtr_off[0] = AR_TXC_DTR0; 1096 hc->txc_dtr_off[1] = AR_TXC_DTR2; 1097 if(hc->bustype == AR_BUS_PCI) { 1098 hc->txc_dtr_off[0] *= 4; 1099 hc->txc_dtr_off[1] *= 4; 1100 } 1101 1102 /* 1103 * reset the card and wait at least 1uS. 1104 */ 1105 if(hc->bustype == AR_BUS_PCI) 1106 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET & 1107 hc->txc_dtr[0]; 1108 else 1109 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & 1110 hc->txc_dtr[0]); 1111 DELAY(2); 1112 if(hc->bustype == AR_BUS_PCI) 1113 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1114 else 1115 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); 1116 1117 if(hc->bustype == AR_BUS_ISA) { 1118 /* 1119 * Configure the card. 1120 * Mem address, irq, 1121 */ 1122 memst = rman_get_start(hc->res_memory); 1123 mar = memst >> 16; 1124 isr = irqtable[hc->isa_irq] << 1; 1125 if(isr == 0) 1126 printf("ar%d: Warning illegal interrupt %d\n", 1127 hc->cunit, hc->isa_irq); 1128 isr = isr | ((memst & 0xc000) >> 10); 1129 1130 hc->sca[0] = (sca_regs *)hc->mem_start; 1131 hc->sca[1] = (sca_regs *)hc->mem_start; 1132 1133 ar_outb(hc, AR_MEM_SEL, mar); 1134 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN); 1135 } 1136 1137 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM) 1138 for(x = 0; x < hc->numports; x++) 1139 hc->interface[x] = ar_read_pim_iface(hc, x); 1140 1141 /* 1142 * Set the TX clock direction and enable TX. 1143 */ 1144 for(x=0;x<hc->numports;x++) { 1145 switch(hc->interface[x]) { 1146 case AR_IFACE_V_35: 1147 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1148 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1149 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1150 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1; 1151 break; 1152 case AR_IFACE_EIA_530: 1153 case AR_IFACE_COMBO: 1154 case AR_IFACE_X_21: 1155 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1156 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1157 break; 1158 } 1159 } 1160 1161 if(hc->bustype == AR_BUS_PCI) 1162 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1163 else 1164 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); 1165 if(hc->numports > NCHAN) { 1166 if(hc->bustype == AR_BUS_PCI) 1167 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1]; 1168 else 1169 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]); 1170 } 1171 1172 chanmem = hc->memsize / hc->numports; 1173 next = 0; 1174 1175 for(x=0;x<hc->numports;x++, sc++) { 1176 int blk; 1177 1178 sc->sca = hc->sca[x / NCHAN]; 1179 1180 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1181 sc->block[blk].txdesc = next; 1182 bufmem = (16 * 1024) / AR_TX_BLOCKS; 1183 descneeded = bufmem / AR_BUF_SIZ; 1184 sc->block[blk].txstart = sc->block[blk].txdesc + 1185 ((((descneeded * sizeof(sca_descriptor)) / 1186 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1187 sc->block[blk].txend = next + bufmem; 1188 sc->block[blk].txmax = 1189 (sc->block[blk].txend - sc->block[blk].txstart) 1190 / AR_BUF_SIZ; 1191 next += bufmem; 1192 1193 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, " 1194 "txend %x, txmax %d\n", 1195 x, 1196 blk, 1197 sc->block[blk].txdesc, 1198 sc->block[blk].txstart, 1199 sc->block[blk].txend, 1200 sc->block[blk].txmax)); 1201 } 1202 1203 sc->rxdesc = next; 1204 bufmem = chanmem - (bufmem * AR_TX_BLOCKS); 1205 descneeded = bufmem / AR_BUF_SIZ; 1206 sc->rxstart = sc->rxdesc + 1207 ((((descneeded * sizeof(sca_descriptor)) / 1208 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1209 sc->rxend = next + bufmem; 1210 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ; 1211 next += bufmem; 1212 TRC(printf("ar%d: rxdesc %x, rxstart %x, " 1213 "rxend %x, rxmax %d\n", 1214 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax)); 1215 } 1216 1217 if(hc->bustype == AR_BUS_PCI) 1218 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1219 } 1220 1221 1222 /* 1223 * The things done here are channel independent. 1224 * 1225 * Configure the sca waitstates. 1226 * Configure the global interrupt registers. 1227 * Enable master dma enable. 1228 */ 1229 static void 1230 ar_init_sca(struct ar_hardc *hc, int scano) 1231 { 1232 sca_regs *sca; 1233 1234 sca = hc->sca[scano]; 1235 if(hc->bustype == AR_BUS_ISA) 1236 ARC_SET_SCA(hc, scano); 1237 1238 /* 1239 * Do the wait registers. 1240 * Set everything to 0 wait states. 1241 */ 1242 sca->pabr0 = 0; 1243 sca->pabr1 = 0; 1244 sca->wcrl = 0; 1245 sca->wcrm = 0; 1246 sca->wcrh = 0; 1247 1248 /* 1249 * Configure the interrupt registers. 1250 * Most are cleared until the interface is configured. 1251 */ 1252 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */ 1253 sca->ier1 = 0x00; /* DMAC interrupts */ 1254 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */ 1255 sca->itcr = 0x00; /* Use ivr and no intr ack */ 1256 sca->ivr = 0x40; /* Fill in the interrupt vector. */ 1257 sca->imvr = 0x40; 1258 1259 /* 1260 * Configure the timers. 1261 * XXX Later 1262 */ 1263 1264 1265 /* 1266 * Set the DMA channel priority to rotate between 1267 * all four channels. 1268 * 1269 * Enable all dma channels. 1270 */ 1271 if(hc->bustype == AR_BUS_PCI) { 1272 u_char *t; 1273 1274 /* 1275 * Stupid problem with the PCI interface chip that break 1276 * things. 1277 * XXX 1278 */ 1279 t = (u_char *)sca; 1280 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2; 1281 t[AR_PCI_SCA_DMER] = SCA_DMER_EN; 1282 } else { 1283 sca->pcr = SCA_PCR_PR2; 1284 sca->dmer = SCA_DMER_EN; 1285 } 1286 } 1287 1288 1289 /* 1290 * Configure the msci 1291 * 1292 * NOTE: The serial port configuration is hardcoded at the moment. 1293 */ 1294 static void 1295 ar_init_msci(struct ar_softc *sc) 1296 { 1297 msci_channel *msci; 1298 1299 msci = &sc->sca->msci[sc->scachan]; 1300 1301 if(sc->hc->bustype == AR_BUS_ISA) 1302 ARC_SET_SCA(sc->hc, sc->scano); 1303 1304 msci->cmd = SCA_CMD_RESET; 1305 1306 msci->md0 = SCA_MD0_CRC_1 | 1307 SCA_MD0_CRC_CCITT | 1308 SCA_MD0_CRC_ENABLE | 1309 SCA_MD0_MODE_HDLC; 1310 msci->md1 = SCA_MD1_NOADDRCHK; 1311 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ; 1312 1313 /* 1314 * Acording to the manual I should give a reset after changing the 1315 * mode registers. 1316 */ 1317 msci->cmd = SCA_CMD_RXRESET; 1318 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS; 1319 1320 /* 1321 * For now all interfaces are programmed to use the RX clock for 1322 * the TX clock. 1323 */ 1324 switch(sc->hc->interface[sc->subunit]) { 1325 case AR_IFACE_V_35: 1326 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1327 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1; 1328 break; 1329 case AR_IFACE_X_21: 1330 case AR_IFACE_EIA_530: 1331 case AR_IFACE_COMBO: 1332 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1333 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1; 1334 } 1335 1336 msci->tmc = 153; /* This give 64k for loopback */ 1337 1338 /* XXX 1339 * Disable all interrupts for now. I think if you are using 1340 * the dmac you don't use these interrupts. 1341 */ 1342 msci->ie0 = 0; 1343 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */ 1344 msci->ie2 = 0; 1345 msci->fie = 0; 1346 1347 msci->sa0 = 0; 1348 msci->sa1 = 0; 1349 1350 msci->idl = 0x7E; /* XXX This is what cisco does. */ 1351 1352 /* 1353 * This is what the ARNET diags use. 1354 */ 1355 msci->rrc = 0x0E; 1356 msci->trc0 = 0x12; 1357 msci->trc1 = 0x1F; 1358 } 1359 1360 /* 1361 * Configure the rx dma controller. 1362 */ 1363 static void 1364 ar_init_rx_dmac(struct ar_softc *sc) 1365 { 1366 dmac_channel *dmac; 1367 sca_descriptor *rxd; 1368 u_int rxbuf; 1369 u_int rxda; 1370 u_int rxda_d; 1371 int x = 0; 1372 1373 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1374 1375 if(sc->hc->bustype == AR_BUS_ISA) 1376 ARC_SET_MEM(sc->hc, sc->rxdesc); 1377 1378 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk)); 1379 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk); 1380 1381 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) { 1382 rxda = (u_int)&rxd[1] - rxda_d; 1383 rxd->cp = (u_short)(rxda & 0xfffful); 1384 1385 x++; 1386 if(x < 6) 1387 TRC(printf("Descrp %p, data pt %x, data %x, ", 1388 rxd, rxda, rxbuf)); 1389 1390 rxd->bp = (u_short)(rxbuf & 0xfffful); 1391 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff); 1392 rxd->len = 0; 1393 rxd->stat = 0xff; /* The sca write here when it is finished. */ 1394 1395 if(x < 6) 1396 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp)); 1397 } 1398 rxd--; 1399 rxd->cp = (u_short)(sc->rxdesc & 0xfffful); 1400 1401 sc->rxhind = 0; 1402 1403 if(sc->hc->bustype == AR_BUS_ISA) 1404 ARC_SET_SCA(sc->hc, sc->scano); 1405 1406 dmac->dsr = 0; /* Disable DMA transfer */ 1407 dmac->dcr = SCA_DCR_ABRT; 1408 1409 /* XXX maybe also SCA_DMR_CNTE */ 1410 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1411 dmac->bfl = AR_BUF_SIZ; 1412 1413 dmac->cda = (u_short)(sc->rxdesc & 0xffff); 1414 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff); 1415 1416 rxd = (sca_descriptor *)sc->rxstart; 1417 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff); 1418 1419 dmac->dir = 0xF0; 1420 1421 dmac->dsr = SCA_DSR_DE; 1422 } 1423 1424 /* 1425 * Configure the TX DMA descriptors. 1426 * Initialize the needed values and chain the descriptors. 1427 */ 1428 static void 1429 ar_init_tx_dmac(struct ar_softc *sc) 1430 { 1431 dmac_channel *dmac; 1432 struct buf_block *blkp; 1433 int blk; 1434 sca_descriptor *txd; 1435 u_int txbuf; 1436 u_int txda; 1437 u_int txda_d; 1438 1439 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1440 1441 if(sc->hc->bustype == AR_BUS_ISA) 1442 ARC_SET_MEM(sc->hc, sc->block[0].txdesc); 1443 1444 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1445 blkp = &sc->block[blk]; 1446 txd = (sca_descriptor *)(sc->hc->mem_start + 1447 (blkp->txdesc&sc->hc->winmsk)); 1448 txda_d = (u_int)sc->hc->mem_start - 1449 (blkp->txdesc & ~sc->hc->winmsk); 1450 1451 txbuf=blkp->txstart; 1452 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) { 1453 txda = (u_int)&txd[1] - txda_d; 1454 txd->cp = (u_short)(txda & 0xfffful); 1455 1456 txd->bp = (u_short)(txbuf & 0xfffful); 1457 txd->bpb = (u_char)((txbuf >> 16) & 0xff); 1458 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n", 1459 sc->unit, txbuf, txd->bpb, txd->bp)); 1460 txd->len = 0; 1461 txd->stat = 0; 1462 } 1463 txd--; 1464 txd->cp = (u_short)(blkp->txdesc & 0xfffful); 1465 1466 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start; 1467 TRC(printf("TX Descriptors start %x, end %x.\n", 1468 blkp->txdesc, 1469 blkp->txtail)); 1470 } 1471 1472 if(sc->hc->bustype == AR_BUS_ISA) 1473 ARC_SET_SCA(sc->hc, sc->scano); 1474 1475 dmac->dsr = 0; /* Disable DMA */ 1476 dmac->dcr = SCA_DCR_ABRT; 1477 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1478 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF; 1479 1480 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff); 1481 } 1482 1483 1484 /* 1485 * Look through the descriptors to see if there is a complete packet 1486 * available. Stop if we get to where the sca is busy. 1487 * 1488 * Return the length and status of the packet. 1489 * Return nonzero if there is a packet available. 1490 * 1491 * NOTE: 1492 * It seems that we get the interrupt a bit early. The updateing of 1493 * descriptor values is not always completed when this is called. 1494 */ 1495 static int 1496 ar_packet_avail(struct ar_softc *sc, 1497 int *len, 1498 u_char *rxstat) 1499 { 1500 dmac_channel *dmac; 1501 sca_descriptor *rxdesc; 1502 sca_descriptor *endp; 1503 sca_descriptor *cda; 1504 1505 if(sc->hc->bustype == AR_BUS_ISA) 1506 ARC_SET_SCA(sc->hc, sc->scano); 1507 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1508 cda = (sca_descriptor *)(sc->hc->mem_start + 1509 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1510 1511 if(sc->hc->bustype == AR_BUS_ISA) 1512 ARC_SET_MEM(sc->hc, sc->rxdesc); 1513 rxdesc = (sca_descriptor *) 1514 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1515 endp = rxdesc; 1516 rxdesc = &rxdesc[sc->rxhind]; 1517 endp = &endp[sc->rxmax]; 1518 1519 *len = 0; 1520 1521 while(rxdesc != cda) { 1522 *len += rxdesc->len; 1523 1524 if(rxdesc->stat & SCA_DESC_EOM) { 1525 *rxstat = rxdesc->stat; 1526 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n", 1527 sc->unit, *len, *rxstat)); 1528 return (1); 1529 } 1530 1531 rxdesc++; 1532 if(rxdesc == endp) 1533 rxdesc = (sca_descriptor *) 1534 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1535 } 1536 1537 *len = 0; 1538 *rxstat = 0; 1539 return (0); 1540 } 1541 1542 1543 /* 1544 * Copy a packet from the on card memory into a provided mbuf. 1545 * Take into account that buffers wrap and that a packet may 1546 * be larger than a buffer. 1547 */ 1548 static void 1549 ar_copy_rxbuf(struct mbuf *m, 1550 struct ar_softc *sc, 1551 int len) 1552 { 1553 sca_descriptor *rxdesc; 1554 u_int rxdata; 1555 u_int rxmax; 1556 u_int off = 0; 1557 u_int tlen; 1558 1559 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ); 1560 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ); 1561 1562 rxdesc = (sca_descriptor *) 1563 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1564 rxdesc = &rxdesc[sc->rxhind]; 1565 1566 while(len) { 1567 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ; 1568 if(sc->hc->bustype == AR_BUS_ISA) 1569 ARC_SET_MEM(sc->hc, rxdata); 1570 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk), 1571 mtod(m, caddr_t) + off, 1572 tlen); 1573 1574 off += tlen; 1575 len -= tlen; 1576 1577 if(sc->hc->bustype == AR_BUS_ISA) 1578 ARC_SET_MEM(sc->hc, sc->rxdesc); 1579 rxdesc->len = 0; 1580 rxdesc->stat = 0xff; 1581 1582 rxdata += AR_BUF_SIZ; 1583 rxdesc++; 1584 if(rxdata == rxmax) { 1585 rxdata = sc->rxstart; 1586 rxdesc = (sca_descriptor *) 1587 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1588 } 1589 } 1590 } 1591 1592 /* 1593 * If single is set, just eat a packet. Otherwise eat everything up to 1594 * where cda points. Update pointers to point to the next packet. 1595 */ 1596 static void 1597 ar_eat_packet(struct ar_softc *sc, int single) 1598 { 1599 dmac_channel *dmac; 1600 sca_descriptor *rxdesc; 1601 sca_descriptor *endp; 1602 sca_descriptor *cda; 1603 int loopcnt = 0; 1604 u_char stat; 1605 1606 if(sc->hc->bustype == AR_BUS_ISA) 1607 ARC_SET_SCA(sc->hc, sc->scano); 1608 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1609 cda = (sca_descriptor *)(sc->hc->mem_start + 1610 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1611 1612 /* 1613 * Loop until desc->stat == (0xff || EOM) 1614 * Clear the status and length in the descriptor. 1615 * Increment the descriptor. 1616 */ 1617 if(sc->hc->bustype == AR_BUS_ISA) 1618 ARC_SET_MEM(sc->hc, sc->rxdesc); 1619 rxdesc = (sca_descriptor *) 1620 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1621 endp = rxdesc; 1622 rxdesc = &rxdesc[sc->rxhind]; 1623 endp = &endp[sc->rxmax]; 1624 1625 while(rxdesc != cda) { 1626 loopcnt++; 1627 if(loopcnt > sc->rxmax) { 1628 printf("ar%d: eat pkt %d loop, cda %p, " 1629 "rxdesc %p, stat %x.\n", 1630 sc->unit, 1631 loopcnt, 1632 (void *)cda, 1633 (void *)rxdesc, 1634 rxdesc->stat); 1635 break; 1636 } 1637 1638 stat = rxdesc->stat; 1639 1640 rxdesc->len = 0; 1641 rxdesc->stat = 0xff; 1642 1643 rxdesc++; 1644 sc->rxhind++; 1645 if(rxdesc == endp) { 1646 rxdesc = (sca_descriptor *) 1647 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1648 sc->rxhind = 0; 1649 } 1650 1651 if(single && (stat == SCA_DESC_EOM)) 1652 break; 1653 } 1654 1655 /* 1656 * Update the eda to the previous descriptor. 1657 */ 1658 if(sc->hc->bustype == AR_BUS_ISA) 1659 ARC_SET_SCA(sc->hc, sc->scano); 1660 1661 rxdesc = (sca_descriptor *)sc->rxdesc; 1662 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1663 1664 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1665 (u_short)((u_int)rxdesc & 0xffff); 1666 } 1667 1668 1669 /* 1670 * While there is packets available in the rx buffer, read them out 1671 * into mbufs and ship them off. 1672 */ 1673 static void 1674 ar_get_packets(struct ar_softc *sc) 1675 { 1676 sca_descriptor *rxdesc; 1677 struct mbuf *m = NULL; 1678 int i; 1679 int len; 1680 u_char rxstat; 1681 #ifdef NETGRAPH 1682 int error; 1683 #endif 1684 1685 while(ar_packet_avail(sc, &len, &rxstat)) { 1686 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat)); 1687 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 1688 MGETHDR(m, M_DONTWAIT, MT_DATA); 1689 if(m == NULL) { 1690 /* eat packet if get mbuf fail!! */ 1691 ar_eat_packet(sc, 1); 1692 continue; 1693 } 1694 #ifndef NETGRAPH 1695 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if; 1696 #else /* NETGRAPH */ 1697 m->m_pkthdr.rcvif = NULL; 1698 sc->inbytes += len; 1699 sc->inlast = 0; 1700 #endif /* NETGRAPH */ 1701 m->m_pkthdr.len = m->m_len = len; 1702 if(len > MHLEN) { 1703 MCLGET(m, M_DONTWAIT); 1704 if((m->m_flags & M_EXT) == 0) { 1705 m_freem(m); 1706 ar_eat_packet(sc, 1); 1707 continue; 1708 } 1709 } 1710 ar_copy_rxbuf(m, sc, len); 1711 #ifndef NETGRAPH 1712 BPF_MTAP(&sc->ifsppp.pp_if, m); 1713 sppp_input(&sc->ifsppp.pp_if, m); 1714 sc->ifsppp.pp_if.if_ipackets++; 1715 #else /* NETGRAPH */ 1716 NG_SEND_DATA_ONLY(error, sc->hook, m); 1717 sc->ipackets++; 1718 #endif /* NETGRAPH */ 1719 1720 /* 1721 * Update the eda to the previous descriptor. 1722 */ 1723 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ; 1724 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 1725 1726 if(sc->hc->bustype == AR_BUS_ISA) 1727 ARC_SET_SCA(sc->hc, sc->scano); 1728 1729 rxdesc = (sca_descriptor *)sc->rxdesc; 1730 rxdesc = 1731 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1732 1733 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1734 (u_short)((u_int)rxdesc & 0xffff); 1735 } else { 1736 int tries = 5; 1737 1738 while((rxstat == 0xff) && --tries) 1739 ar_packet_avail(sc, &len, &rxstat); 1740 1741 /* 1742 * It look like we get an interrupt early 1743 * sometimes and then the status is not 1744 * filled in yet. 1745 */ 1746 if(tries && (tries != 5)) 1747 continue; 1748 1749 ar_eat_packet(sc, 1); 1750 1751 #ifndef NETGRAPH 1752 sc->ifsppp.pp_if.if_ierrors++; 1753 #else /* NETGRAPH */ 1754 sc->ierrors[0]++; 1755 #endif /* NETGRAPH */ 1756 1757 if(sc->hc->bustype == AR_BUS_ISA) 1758 ARC_SET_SCA(sc->hc, sc->scano); 1759 1760 TRCL(printf("ar%d: Receive error chan %d, " 1761 "stat %x, msci st3 %x," 1762 "rxhind %d, cda %x, eda %x.\n", 1763 sc->unit, 1764 sc->scachan, 1765 rxstat, 1766 sc->sca->msci[sc->scachan].st3, 1767 sc->rxhind, 1768 sc->sca->dmac[ 1769 DMAC_RXCH(sc->scachan)].cda, 1770 sc->sca->dmac[ 1771 DMAC_RXCH(sc->scachan)].eda)); 1772 } 1773 } 1774 } 1775 1776 1777 /* 1778 * All DMA interrupts come here. 1779 * 1780 * Each channel has two interrupts. 1781 * Interrupt A for errors and Interrupt B for normal stuff like end 1782 * of transmit or receive dmas. 1783 */ 1784 static void 1785 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1) 1786 { 1787 u_char dsr; 1788 u_char dotxstart = isr1; 1789 int mch; 1790 struct ar_softc *sc; 1791 sca_regs *sca; 1792 dmac_channel *dmac; 1793 1794 sca = hc->sca[scano]; 1795 mch = 0; 1796 /* 1797 * Shortcut if there is no interrupts for dma channel 0 or 1 1798 */ 1799 if((isr1 & 0x0F) == 0) { 1800 mch = 1; 1801 isr1 >>= 4; 1802 } 1803 1804 do { 1805 sc = &hc->sc[mch + (NCHAN * scano)]; 1806 1807 /* 1808 * Transmit channel 1809 */ 1810 if(isr1 & 0x0C) { 1811 dmac = &sca->dmac[DMAC_TXCH(mch)]; 1812 1813 if(hc->bustype == AR_BUS_ISA) 1814 ARC_SET_SCA(hc, scano); 1815 1816 dsr = dmac->dsr; 1817 dmac->dsr = dsr; 1818 1819 /* Counter overflow */ 1820 if(dsr & SCA_DSR_COF) { 1821 printf("ar%d: TX DMA Counter overflow, " 1822 "txpacket no %lu.\n", 1823 sc->unit, 1824 #ifndef NETGRAPH 1825 sc->ifsppp.pp_if.if_opackets); 1826 sc->ifsppp.pp_if.if_oerrors++; 1827 #else /* NETGRAPH */ 1828 sc->opackets); 1829 sc->oerrors++; 1830 #endif /* NETGRAPH */ 1831 } 1832 1833 /* Buffer overflow */ 1834 if(dsr & SCA_DSR_BOF) { 1835 printf("ar%d: TX DMA Buffer overflow, " 1836 "txpacket no %lu, dsr %02x, " 1837 "cda %04x, eda %04x.\n", 1838 sc->unit, 1839 #ifndef NETGRAPH 1840 sc->ifsppp.pp_if.if_opackets, 1841 #else /* NETGRAPH */ 1842 sc->opackets, 1843 #endif /* NETGRAPH */ 1844 dsr, 1845 dmac->cda, 1846 dmac->eda); 1847 #ifndef NETGRAPH 1848 sc->ifsppp.pp_if.if_oerrors++; 1849 #else /* NETGRAPH */ 1850 sc->oerrors++; 1851 #endif /* NETGRAPH */ 1852 } 1853 1854 /* End of Transfer */ 1855 if(dsr & SCA_DSR_EOT) { 1856 /* 1857 * This should be the most common case. 1858 * 1859 * Clear the IFF_OACTIVE flag. 1860 * 1861 * Call arstart to start a new transmit if 1862 * there is data to transmit. 1863 */ 1864 sc->xmit_busy = 0; 1865 #ifndef NETGRAPH 1866 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 1867 sc->ifsppp.pp_if.if_timer = 0; 1868 #else /* NETGRAPH */ 1869 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */ 1870 sc->out_dog = 0; /* XXX */ 1871 #endif /* NETGRAPH */ 1872 1873 if(sc->txb_inuse && --sc->txb_inuse) 1874 ar_xmit(sc); 1875 } 1876 } 1877 1878 /* 1879 * Receive channel 1880 */ 1881 if(isr1 & 0x03) { 1882 dmac = &sca->dmac[DMAC_RXCH(mch)]; 1883 1884 if(hc->bustype == AR_BUS_ISA) 1885 ARC_SET_SCA(hc, scano); 1886 1887 dsr = dmac->dsr; 1888 dmac->dsr = dsr; 1889 1890 TRC(printf("AR: RX DSR %x\n", dsr)); 1891 1892 /* End of frame */ 1893 if(dsr & SCA_DSR_EOM) { 1894 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;) 1895 TRC(int ind = sc->rxhind;) 1896 1897 ar_get_packets(sc); 1898 #ifndef NETGRAPH 1899 #define IPACKETS sc->ifsppp.pp_if.if_ipackets 1900 #else /* NETGRAPH */ 1901 #define IPACKETS sc->ipackets 1902 #endif /* NETGRAPH */ 1903 TRC(if(tt == IPACKETS) { 1904 sca_descriptor *rxdesc; 1905 int i; 1906 1907 if(hc->bustype == AR_BUS_ISA) 1908 ARC_SET_SCA(hc, scano); 1909 printf("AR: RXINTR isr1 %x, dsr %x, " 1910 "no data %d pkts, orxhind %d.\n", 1911 dotxstart, 1912 dsr, 1913 tt, 1914 ind); 1915 printf("AR: rxdesc %x, rxstart %x, " 1916 "rxend %x, rxhind %d, " 1917 "rxmax %d.\n", 1918 sc->rxdesc, 1919 sc->rxstart, 1920 sc->rxend, 1921 sc->rxhind, 1922 sc->rxmax); 1923 printf("AR: cda %x, eda %x.\n", 1924 dmac->cda, 1925 dmac->eda); 1926 1927 if(sc->hc->bustype == AR_BUS_ISA) 1928 ARC_SET_MEM(sc->hc, 1929 sc->rxdesc); 1930 rxdesc = (sca_descriptor *) 1931 (sc->hc->mem_start + 1932 (sc->rxdesc & sc->hc->winmsk)); 1933 rxdesc = &rxdesc[sc->rxhind]; 1934 for(i=0;i<3;i++,rxdesc++) 1935 printf("AR: rxdesc->stat %x, " 1936 "len %d.\n", 1937 rxdesc->stat, 1938 rxdesc->len); 1939 }) 1940 } 1941 1942 /* Counter overflow */ 1943 if(dsr & SCA_DSR_COF) { 1944 printf("ar%d: RX DMA Counter overflow, " 1945 "rxpkts %lu.\n", 1946 sc->unit, 1947 #ifndef NETGRAPH 1948 sc->ifsppp.pp_if.if_ipackets); 1949 sc->ifsppp.pp_if.if_ierrors++; 1950 #else /* NETGRAPH */ 1951 sc->ipackets); 1952 sc->ierrors[1]++; 1953 #endif /* NETGRAPH */ 1954 } 1955 1956 /* Buffer overflow */ 1957 if(dsr & SCA_DSR_BOF) { 1958 if(hc->bustype == AR_BUS_ISA) 1959 ARC_SET_SCA(hc, scano); 1960 printf("ar%d: RX DMA Buffer overflow, " 1961 "rxpkts %lu, rxind %d, " 1962 "cda %x, eda %x, dsr %x.\n", 1963 sc->unit, 1964 #ifndef NETGRAPH 1965 sc->ifsppp.pp_if.if_ipackets, 1966 #else /* NETGRAPH */ 1967 sc->ipackets, 1968 #endif /* NETGRAPH */ 1969 sc->rxhind, 1970 dmac->cda, 1971 dmac->eda, 1972 dsr); 1973 /* 1974 * Make sure we eat as many as possible. 1975 * Then get the system running again. 1976 */ 1977 ar_eat_packet(sc, 0); 1978 #ifndef NETGRAPH 1979 sc->ifsppp.pp_if.if_ierrors++; 1980 #else /* NETGRAPH */ 1981 sc->ierrors[2]++; 1982 #endif /* NETGRAPH */ 1983 if(hc->bustype == AR_BUS_ISA) 1984 ARC_SET_SCA(hc, scano); 1985 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ; 1986 dmac->dsr = SCA_DSR_DE; 1987 1988 TRC(printf("ar%d: RX DMA Buffer overflow, " 1989 "rxpkts %lu, rxind %d, " 1990 "cda %x, eda %x, dsr %x. After\n", 1991 sc->unit, 1992 sc->ifsppp.pp_if.if_ipackets, 1993 sc->rxhind, 1994 dmac->cda, 1995 dmac->eda, 1996 dmac->dsr);) 1997 } 1998 1999 /* End of Transfer */ 2000 if(dsr & SCA_DSR_EOT) { 2001 /* 2002 * If this happen, it means that we are 2003 * receiving faster than what the processor 2004 * can handle. 2005 * 2006 * XXX We should enable the dma again. 2007 */ 2008 printf("ar%d: RX End of transfer, rxpkts %lu.\n", 2009 sc->unit, 2010 #ifndef NETGRAPH 2011 sc->ifsppp.pp_if.if_ipackets); 2012 sc->ifsppp.pp_if.if_ierrors++; 2013 #else /* NETGRAPH */ 2014 sc->ipackets); 2015 sc->ierrors[3]++; 2016 #endif /* NETGRAPH */ 2017 } 2018 } 2019 2020 isr1 >>= 4; 2021 2022 mch++; 2023 }while((mch<NCHAN) && isr1); 2024 2025 /* 2026 * Now that we have done all the urgent things, see if we 2027 * can fill the transmit buffers. 2028 */ 2029 for(mch = 0; mch < NCHAN; mch++) { 2030 if(dotxstart & 0x0C) { 2031 sc = &hc->sc[mch + (NCHAN * scano)]; 2032 #ifndef NETGRAPH 2033 arstart(&sc->ifsppp.pp_if); 2034 #else /* NETGRAPH */ 2035 arstart(sc); 2036 #endif /* NETGRAPH */ 2037 } 2038 dotxstart >>= 4; 2039 } 2040 } 2041 2042 static void 2043 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0) 2044 { 2045 printf("arc%d: ARINTR: MSCI\n", hc->cunit); 2046 } 2047 2048 static void 2049 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2) 2050 { 2051 printf("arc%d: ARINTR: TIMER\n", hc->cunit); 2052 } 2053 2054 2055 #ifdef NETGRAPH 2056 /***************************************** 2057 * Device timeout/watchdog routine. 2058 * called once per second. 2059 * checks to see that if activity was expected, that it hapenned. 2060 * At present we only look to see if expected output was completed. 2061 */ 2062 static void 2063 ngar_watchdog_frame(void * arg) 2064 { 2065 struct ar_softc * sc = arg; 2066 int s; 2067 int speed; 2068 2069 if(sc->running == 0) 2070 return; /* if we are not running let timeouts die */ 2071 /* 2072 * calculate the apparent throughputs 2073 * XXX a real hack 2074 */ 2075 s = splimp(); 2076 speed = sc->inbytes - sc->lastinbytes; 2077 sc->lastinbytes = sc->inbytes; 2078 if ( sc->inrate < speed ) 2079 sc->inrate = speed; 2080 speed = sc->outbytes - sc->lastoutbytes; 2081 sc->lastoutbytes = sc->outbytes; 2082 if ( sc->outrate < speed ) 2083 sc->outrate = speed; 2084 sc->inlast++; 2085 splx(s); 2086 2087 if ((sc->inlast > QUITE_A_WHILE) 2088 && (sc->out_deficit > LOTS_OF_PACKETS)) { 2089 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit); 2090 s = splimp(); 2091 ar_down(sc); 2092 ar_up(sc); 2093 sc->inlast = sc->out_deficit = 0; 2094 splx(s); 2095 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 2096 if (sc->out_dog == 0) { 2097 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n", 2098 sc->unit); 2099 s = splimp(); 2100 arwatchdog(sc); 2101 #if 0 2102 ar_down(sc); 2103 ar_up(sc); 2104 #endif 2105 splx(s); 2106 sc->inlast = sc->out_deficit = 0; 2107 } else { 2108 sc->out_dog--; 2109 } 2110 } 2111 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 2112 } 2113 2114 /*********************************************************************** 2115 * This section contains the methods for the Netgraph interface 2116 ***********************************************************************/ 2117 /* 2118 * It is not possible or allowable to create a node of this type. 2119 * If the hardware exists, it will already have created it. 2120 */ 2121 static int 2122 ngar_constructor(node_p node) 2123 { 2124 return (EINVAL); 2125 } 2126 2127 /* 2128 * give our ok for a hook to be added... 2129 * If we are not running this should kick the device into life. 2130 * The hook's private info points to our stash of info about that 2131 * channel. 2132 */ 2133 static int 2134 ngar_newhook(node_p node, hook_p hook, const char *name) 2135 { 2136 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2137 2138 /* 2139 * check if it's our friend the debug hook 2140 */ 2141 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) { 2142 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */ 2143 sc->debug_hook = hook; 2144 return (0); 2145 } 2146 2147 /* 2148 * Check for raw mode hook. 2149 */ 2150 if (strcmp(name, NG_AR_HOOK_RAW) != 0) { 2151 return (EINVAL); 2152 } 2153 NG_HOOK_SET_PRIVATE(hook, sc); 2154 sc->hook = hook; 2155 sc->datahooks++; 2156 ar_up(sc); 2157 return (0); 2158 } 2159 2160 /* 2161 * incoming messages. 2162 * Just respond to the generic TEXT_STATUS message 2163 */ 2164 static int 2165 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook) 2166 { 2167 struct ar_softc * sc; 2168 struct ng_mesg *resp = NULL; 2169 int error = 0; 2170 struct ng_mesg *msg; 2171 2172 NGI_GET_MSG(item, msg); 2173 sc = NG_NODE_PRIVATE(node); 2174 switch (msg->header.typecookie) { 2175 case NG_AR_COOKIE: 2176 error = EINVAL; 2177 break; 2178 case NGM_GENERIC_COOKIE: 2179 switch(msg->header.cmd) { 2180 case NGM_TEXT_STATUS: { 2181 char *arg; 2182 int pos = 0; 2183 2184 int resplen = sizeof(struct ng_mesg) + 512; 2185 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT); 2186 if (resp == NULL) { 2187 error = ENOMEM; 2188 break; 2189 } 2190 arg = (resp)->data; 2191 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 2192 "highest rate seen: %ld B/S in, %ld B/S out\n", 2193 sc->inbytes, sc->outbytes, 2194 sc->inrate, sc->outrate); 2195 pos += sprintf(arg + pos, 2196 "%ld output errors\n", 2197 sc->oerrors); 2198 pos += sprintf(arg + pos, 2199 "ierrors = %ld, %ld, %ld, %ld\n", 2200 sc->ierrors[0], 2201 sc->ierrors[1], 2202 sc->ierrors[2], 2203 sc->ierrors[3]); 2204 2205 resp->header.arglen = pos + 1; 2206 break; 2207 } 2208 default: 2209 error = EINVAL; 2210 break; 2211 } 2212 break; 2213 default: 2214 error = EINVAL; 2215 break; 2216 } 2217 /* Take care of synchronous response, if any */ 2218 NG_RESPOND_MSG(error, node, item, resp); 2219 NG_FREE_MSG(msg); 2220 return (error); 2221 } 2222 2223 /* 2224 * get data from another node and transmit it to the correct channel 2225 */ 2226 static int 2227 ngar_rcvdata(hook_p hook, item_p item) 2228 { 2229 int s; 2230 int error = 0; 2231 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2232 struct ifqueue *xmitq_p; 2233 struct mbuf *m; 2234 meta_p meta; 2235 2236 NGI_GET_M(item, m); 2237 NGI_GET_META(item, meta); 2238 NG_FREE_ITEM(item); 2239 /* 2240 * data doesn't come in from just anywhere (e.g control hook) 2241 */ 2242 if ( NG_HOOK_PRIVATE(hook) == NULL) { 2243 error = ENETDOWN; 2244 goto bad; 2245 } 2246 2247 /* 2248 * Now queue the data for when it can be sent 2249 */ 2250 if (meta && meta->priority > 0) { 2251 xmitq_p = (&sc->xmitq_hipri); 2252 } else { 2253 xmitq_p = (&sc->xmitq); 2254 } 2255 s = splimp(); 2256 IF_LOCK(xmitq_p); 2257 if (_IF_QFULL(xmitq_p)) { 2258 _IF_DROP(xmitq_p); 2259 IF_UNLOCK(xmitq_p); 2260 splx(s); 2261 error = ENOBUFS; 2262 goto bad; 2263 } 2264 _IF_ENQUEUE(xmitq_p, m); 2265 IF_UNLOCK(xmitq_p); 2266 arstart(sc); 2267 splx(s); 2268 return (0); 2269 2270 bad: 2271 /* 2272 * It was an error case. 2273 * check if we need to free the mbuf, and then return the error 2274 */ 2275 NG_FREE_M(m); 2276 NG_FREE_META(meta); 2277 return (error); 2278 } 2279 2280 /* 2281 * do local shutdown processing.. 2282 * this node will refuse to go away, unless the hardware says to.. 2283 * don't unref the node, or remove our name. just clear our links up. 2284 */ 2285 static int 2286 ngar_shutdown(node_p node) 2287 { 2288 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2289 2290 ar_down(sc); 2291 NG_NODE_UNREF(node); 2292 /* XXX need to drain the output queues! */ 2293 2294 /* The node is dead, long live the node! */ 2295 /* stolen from the attach routine */ 2296 if (ng_make_node_common(&typestruct, &sc->node) != 0) 2297 return (0); 2298 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 2299 if (ng_name_node(sc->node, sc->nodename)) { 2300 sc->node = NULL; 2301 printf("node naming failed\n"); 2302 NG_NODE_UNREF(sc->node); /* node dissappears */ 2303 return (0); 2304 } 2305 NG_NODE_SET_PRIVATE(sc->node, sc); 2306 sc->running = 0; 2307 return (0); 2308 } 2309 2310 /* already linked */ 2311 static int 2312 ngar_connect(hook_p hook) 2313 { 2314 /* probably not at splnet, force outward queueing */ 2315 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 2316 /* be really amiable and just say "YUP that's OK by me! " */ 2317 return (0); 2318 } 2319 2320 /* 2321 * notify on hook disconnection (destruction) 2322 * 2323 * Invalidate the private data associated with this dlci. 2324 * For this type, removal of the last link resets tries to destroy the node. 2325 * As the device still exists, the shutdown method will not actually 2326 * destroy the node, but reset the device and leave it 'fresh' :) 2327 * 2328 * The node removal code will remove all references except that owned by the 2329 * driver. 2330 */ 2331 static int 2332 ngar_disconnect(hook_p hook) 2333 { 2334 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2335 int s; 2336 /* 2337 * If it's the data hook, then free resources etc. 2338 */ 2339 if (NG_HOOK_PRIVATE(hook)) { 2340 s = splimp(); 2341 sc->datahooks--; 2342 if (sc->datahooks == 0) 2343 ar_down(sc); 2344 splx(s); 2345 } else { 2346 sc->debug_hook = NULL; 2347 } 2348 return (0); 2349 } 2350 2351 /* 2352 * called during bootup 2353 * or LKM loading to put this type into the list of known modules 2354 */ 2355 static void 2356 ngar_init(void *ignored) 2357 { 2358 if (ng_newtype(&typestruct)) 2359 printf("ngar install failed\n"); 2360 ngar_done_init = 1; 2361 } 2362 #endif /* NETGRAPH */ 2363 2364 /* 2365 ********************************* END ************************************ 2366 */
Cache object: 608245477f0053c304e91f339bae0010
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