Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ar/if_ar.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/5.3/sys/dev/ar/if_ar.c 133675 2004-08-13 22:52:11Z rwatson $"); 31 32 /* 33 * Programming assumptions and other issues. 34 * 35 * The descriptors of a DMA channel will fit in a 16K memory window. 36 * 37 * The buffers of a transmit DMA channel will fit in a 16K memory window. 38 * 39 * Only the ISA bus cards with X.21 and V.35 is tested. 40 * 41 * When interface is going up, handshaking is set and it is only cleared 42 * when the interface is down'ed. 43 * 44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 45 * internal/external clock, etc..... 46 */ 47 48 #include "opt_netgraph.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/mbuf.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/module.h> 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus_memio.h> 63 #include <sys/rman.h> 64 65 #include <net/if.h> 66 #ifdef NETGRAPH 67 #include <netgraph/ng_message.h> 68 #include <netgraph/netgraph.h> 69 #include <sys/syslog.h> 70 #include <dev/ar/if_ar.h> 71 #else /* NETGRAPH */ 72 #include <net/if_sppp.h> 73 #include <net/bpf.h> 74 #endif /* NETGRAPH */ 75 76 #include <machine/md_var.h> 77 78 #include <dev/ic/hd64570.h> 79 #include <dev/ar/if_arregs.h> 80 81 #ifdef TRACE 82 #define TRC(x) x 83 #else 84 #define TRC(x) 85 #endif 86 87 #define TRCL(x) x 88 89 #define PPP_HEADER_LEN 4 90 91 devclass_t ar_devclass; 92 93 struct ar_softc { 94 #ifndef NETGRAPH 95 struct sppp ifsppp; 96 #endif /* NETGRAPH */ 97 int unit; /* With regards to all ar devices */ 98 int subunit; /* With regards to this card */ 99 struct ar_hardc *hc; 100 101 struct buf_block { 102 u_int txdesc; /* On card address */ 103 u_int txstart; /* On card address */ 104 u_int txend; /* On card address */ 105 u_int txtail; /* Index of first unused buffer */ 106 u_int txmax; /* number of usable buffers/descriptors */ 107 u_int txeda; /* Error descriptor addresses */ 108 }block[AR_TX_BLOCKS]; 109 110 char xmit_busy; /* Transmitter is busy */ 111 char txb_inuse; /* Number of tx blocks currently in use */ 112 u_char txb_new; /* Index to where new buffer will be added */ 113 u_char txb_next_tx; /* Index to next block ready to tx */ 114 115 u_int rxdesc; /* On card address */ 116 u_int rxstart; /* On card address */ 117 u_int rxend; /* On card address */ 118 u_int rxhind; /* Index to the head of the rx buffers. */ 119 u_int rxmax; /* number of usable buffers/descriptors */ 120 121 int scano; 122 int scachan; 123 sca_regs *sca; 124 #ifdef NETGRAPH 125 int running; /* something is attached so we are running */ 126 int dcd; /* do we have dcd? */ 127 /* ---netgraph bits --- */ 128 char nodename[NG_NODESIZ]; /* store our node name */ 129 int datahooks; /* number of data hooks attached */ 130 node_p node; /* netgraph node */ 131 hook_p hook; /* data hook */ 132 hook_p debug_hook; 133 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 134 struct ifqueue xmitq; /* transmit queue */ 135 int flags; /* state */ 136 #define SCF_RUNNING 0x01 /* board is active */ 137 #define SCF_OACTIVE 0x02 /* output is active */ 138 int out_dog; /* watchdog cycles output count-down */ 139 struct callout_handle handle; /* timeout(9) handle */ 140 u_long inbytes, outbytes; /* stats */ 141 u_long lastinbytes, lastoutbytes; /* a second ago */ 142 u_long inrate, outrate; /* highest rate seen */ 143 u_long inlast; /* last input N secs ago */ 144 u_long out_deficit; /* output since last input */ 145 u_long oerrors, ierrors[6]; 146 u_long opackets, ipackets; 147 #endif /* NETGRAPH */ 148 }; 149 150 static int next_ar_unit = 0; 151 152 #ifdef NETGRAPH 153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 154 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 155 #define LOTS_OF_PACKETS 100 156 #endif /* NETGRAPH */ 157 158 /* 159 * This translate from irq numbers to 160 * the value that the arnet card needs 161 * in the lower part of the AR_INT_SEL 162 * register. 163 */ 164 static int irqtable[16] = { 165 0, /* 0 */ 166 0, /* 1 */ 167 0, /* 2 */ 168 1, /* 3 */ 169 0, /* 4 */ 170 2, /* 5 */ 171 0, /* 6 */ 172 3, /* 7 */ 173 0, /* 8 */ 174 0, /* 9 */ 175 4, /* 10 */ 176 5, /* 11 */ 177 6, /* 12 */ 178 0, /* 13 */ 179 0, /* 14 */ 180 7 /* 15 */ 181 }; 182 183 #ifndef NETGRAPH 184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1); 185 #else 186 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1); 187 #endif 188 189 static void arintr(void *arg); 190 static void ar_xmit(struct ar_softc *sc); 191 #ifndef NETGRAPH 192 static void arstart(struct ifnet *ifp); 193 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 194 static void arwatchdog(struct ifnet *ifp); 195 #else /* NETGRAPH */ 196 static void arstart(struct ar_softc *sc); 197 static void arwatchdog(struct ar_softc *sc); 198 #endif /* NETGRAPH */ 199 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat); 200 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len); 201 static void ar_eat_packet(struct ar_softc *sc, int single); 202 static void ar_get_packets(struct ar_softc *sc); 203 204 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel); 205 static void ar_up(struct ar_softc *sc); 206 static void ar_down(struct ar_softc *sc); 207 static void arc_init(struct ar_hardc *hc); 208 static void ar_init_sca(struct ar_hardc *hc, int scano); 209 static void ar_init_msci(struct ar_softc *sc); 210 static void ar_init_rx_dmac(struct ar_softc *sc); 211 static void ar_init_tx_dmac(struct ar_softc *sc); 212 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr); 213 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr); 214 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr); 215 216 #ifdef NETGRAPH 217 static void ngar_watchdog_frame(void * arg); 218 static void ngar_init(void* ignored); 219 220 static ng_constructor_t ngar_constructor; 221 static ng_rcvmsg_t ngar_rcvmsg; 222 static ng_shutdown_t ngar_shutdown; 223 static ng_newhook_t ngar_newhook; 224 /*static ng_findhook_t ngar_findhook; */ 225 static ng_connect_t ngar_connect; 226 static ng_rcvdata_t ngar_rcvdata; 227 static ng_disconnect_t ngar_disconnect; 228 229 static struct ng_type typestruct = { 230 .version = NG_ABI_VERSION, 231 .name = NG_AR_NODE_TYPE, 232 .constructor = ngar_constructor, 233 .rcvmsg = ngar_rcvmsg, 234 .shutdown = ngar_shutdown, 235 .newhook = ngar_newhook, 236 .connect = ngar_connect, 237 .rcvdata = ngar_rcvdata, 238 .disconnect = ngar_disconnect, 239 }; 240 241 static int ngar_done_init = 0; 242 #endif /* NETGRAPH */ 243 244 int 245 ar_attach(device_t device) 246 { 247 struct ar_hardc *hc; 248 struct ar_softc *sc; 249 #ifndef NETGRAPH 250 struct ifnet *ifp; 251 char *iface; 252 #endif /* NETGRAPH */ 253 int unit; 254 255 hc = (struct ar_hardc *)device_get_softc(device); 256 257 printf("arc%d: %uK RAM, %u ports, rev %u.\n", 258 hc->cunit, 259 hc->memsize/1024, 260 hc->numports, 261 hc->revision); 262 263 arc_init(hc); 264 265 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, 266 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0) 267 return (1); 268 269 sc = hc->sc; 270 271 for(unit=0;unit<hc->numports;unit+=NCHAN) 272 ar_init_sca(hc, unit / NCHAN); 273 274 /* 275 * Now configure each port on the card. 276 */ 277 for(unit=0;unit<hc->numports;sc++,unit++) { 278 sc->hc = hc; 279 sc->subunit = unit; 280 sc->unit = next_ar_unit; 281 next_ar_unit++; 282 sc->scano = unit / NCHAN; 283 sc->scachan = unit%NCHAN; 284 285 ar_init_rx_dmac(sc); 286 ar_init_tx_dmac(sc); 287 ar_init_msci(sc); 288 289 #ifndef NETGRAPH 290 ifp = &sc->ifsppp.pp_if; 291 292 ifp->if_softc = sc; 293 if_initname(ifp, device_get_name(device), 294 device_get_unit(device)); 295 ifp->if_mtu = PP_MTU; 296 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST | 297 IFF_NEEDSGIANT; 298 ifp->if_ioctl = arioctl; 299 ifp->if_start = arstart; 300 ifp->if_watchdog = arwatchdog; 301 302 sc->ifsppp.pp_flags = PP_KEEPALIVE; 303 304 switch(hc->interface[unit]) { 305 default: iface = "UNKNOWN"; break; 306 case AR_IFACE_EIA_232: iface = "EIA-232"; break; 307 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break; 308 case AR_IFACE_EIA_530: iface = "EIA-530"; break; 309 case AR_IFACE_X_21: iface = "X.21"; break; 310 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break; 311 } 312 313 printf("ar%d: Adapter %d, port %d, interface %s.\n", 314 sc->unit, 315 hc->cunit, 316 sc->subunit, 317 iface); 318 319 sppp_attach((struct ifnet *)&sc->ifsppp); 320 if_attach(ifp); 321 322 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 323 #else /* NETGRAPH */ 324 /* 325 * we have found a node, make sure our 'type' is availabe. 326 */ 327 if (ngar_done_init == 0) ngar_init(NULL); 328 if (ng_make_node_common(&typestruct, &sc->node) != 0) 329 return (1); 330 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 331 if (ng_name_node(sc->node, sc->nodename)) { 332 NG_NODE_UNREF(sc->node); /* drop it again */ 333 return (1); 334 } 335 NG_NODE_SET_PRIVATE(sc->node, sc); 336 callout_handle_init(&sc->handle); 337 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 338 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 339 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF); 340 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL, 341 MTX_DEF); 342 sc->running = 0; 343 #endif /* NETGRAPH */ 344 } 345 346 if(hc->bustype == AR_BUS_ISA) 347 ARC_SET_OFF(hc); 348 349 return (0); 350 } 351 352 int 353 ar_detach(device_t device) 354 { 355 device_t parent = device_get_parent(device); 356 struct ar_hardc *hc = device_get_softc(device); 357 358 if (hc->intr_cookie != NULL) { 359 if (BUS_TEARDOWN_INTR(parent, device, 360 hc->res_irq, hc->intr_cookie) != 0) { 361 printf("intr teardown failed.. continuing\n"); 362 } 363 hc->intr_cookie = NULL; 364 } 365 366 /* 367 * deallocate any system resources we may have 368 * allocated on behalf of this driver. 369 */ 370 FREE(hc->sc, M_DEVBUF); 371 hc->sc = NULL; 372 hc->mem_start = NULL; 373 return (ar_deallocate_resources(device)); 374 } 375 376 int 377 ar_allocate_ioport(device_t device, int rid, u_long size) 378 { 379 struct ar_hardc *hc = device_get_softc(device); 380 381 hc->rid_ioport = rid; 382 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, 383 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); 384 if (hc->res_ioport == NULL) { 385 goto errexit; 386 } 387 hc->bt = rman_get_bustag(hc->res_ioport); 388 hc->bh = rman_get_bushandle(hc->res_ioport); 389 390 return (0); 391 392 errexit: 393 ar_deallocate_resources(device); 394 return (ENXIO); 395 } 396 397 int 398 ar_allocate_irq(device_t device, int rid, u_long size) 399 { 400 struct ar_hardc *hc = device_get_softc(device); 401 402 hc->rid_irq = rid; 403 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ, 404 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE); 405 if (hc->res_irq == NULL) { 406 goto errexit; 407 } 408 return (0); 409 410 errexit: 411 ar_deallocate_resources(device); 412 return (ENXIO); 413 } 414 415 int 416 ar_allocate_memory(device_t device, int rid, u_long size) 417 { 418 struct ar_hardc *hc = device_get_softc(device); 419 420 hc->rid_memory = rid; 421 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 422 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); 423 if (hc->res_memory == NULL) { 424 goto errexit; 425 } 426 return (0); 427 428 errexit: 429 ar_deallocate_resources(device); 430 return (ENXIO); 431 } 432 433 int 434 ar_allocate_plx_memory(device_t device, int rid, u_long size) 435 { 436 struct ar_hardc *hc = device_get_softc(device); 437 438 hc->rid_plx_memory = rid; 439 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 440 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); 441 if (hc->res_plx_memory == NULL) { 442 goto errexit; 443 } 444 return (0); 445 446 errexit: 447 ar_deallocate_resources(device); 448 return (ENXIO); 449 } 450 451 int 452 ar_deallocate_resources(device_t device) 453 { 454 struct ar_hardc *hc = device_get_softc(device); 455 456 if (hc->res_irq != 0) { 457 bus_deactivate_resource(device, SYS_RES_IRQ, 458 hc->rid_irq, hc->res_irq); 459 bus_release_resource(device, SYS_RES_IRQ, 460 hc->rid_irq, hc->res_irq); 461 hc->res_irq = 0; 462 } 463 if (hc->res_ioport != 0) { 464 bus_deactivate_resource(device, SYS_RES_IOPORT, 465 hc->rid_ioport, hc->res_ioport); 466 bus_release_resource(device, SYS_RES_IOPORT, 467 hc->rid_ioport, hc->res_ioport); 468 hc->res_ioport = 0; 469 } 470 if (hc->res_memory != 0) { 471 bus_deactivate_resource(device, SYS_RES_MEMORY, 472 hc->rid_memory, hc->res_memory); 473 bus_release_resource(device, SYS_RES_MEMORY, 474 hc->rid_memory, hc->res_memory); 475 hc->res_memory = 0; 476 } 477 if (hc->res_plx_memory != 0) { 478 bus_deactivate_resource(device, SYS_RES_MEMORY, 479 hc->rid_plx_memory, hc->res_plx_memory); 480 bus_release_resource(device, SYS_RES_MEMORY, 481 hc->rid_plx_memory, hc->res_plx_memory); 482 hc->res_plx_memory = 0; 483 } 484 return (0); 485 } 486 487 /* 488 * First figure out which SCA gave the interrupt. 489 * Process it. 490 * See if there is other interrupts pending. 491 * Repeat until there is no more interrupts. 492 */ 493 static void 494 arintr(void *arg) 495 { 496 struct ar_hardc *hc = (struct ar_hardc *)arg; 497 sca_regs *sca; 498 u_char isr0, isr1, isr2, arisr; 499 int scano; 500 501 /* XXX Use the PCI interrupt score board register later */ 502 if(hc->bustype == AR_BUS_PCI) 503 arisr = hc->orbase[AR_ISTAT * 4]; 504 else 505 arisr = ar_inb(hc, AR_ISTAT); 506 507 while(arisr & AR_BD_INT) { 508 TRC(printf("arisr = %x\n", arisr)); 509 if(arisr & AR_INT_0) 510 scano = 0; 511 else if(arisr & AR_INT_1) 512 scano = 1; 513 else { 514 /* XXX Oops this shouldn't happen. */ 515 printf("arc%d: Interrupted with no interrupt.\n", 516 hc->cunit); 517 return; 518 } 519 sca = hc->sca[scano]; 520 521 if(hc->bustype == AR_BUS_ISA) 522 ARC_SET_SCA(hc, scano); 523 524 isr0 = sca->isr0; 525 isr1 = sca->isr1; 526 isr2 = sca->isr2; 527 528 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n", 529 hc->cunit, 530 isr0, 531 isr1, 532 isr2)); 533 if(isr0) 534 ar_msci_intr(hc, scano, isr0); 535 536 if(isr1) 537 ar_dmac_intr(hc, scano, isr1); 538 539 if(isr2) 540 ar_timer_intr(hc, scano, isr2); 541 542 /* 543 * Proccess the second sca's interrupt if available. 544 * Else see if there are any new interrupts. 545 */ 546 if((arisr & AR_INT_0) && (arisr & AR_INT_1)) 547 arisr &= ~AR_INT_0; 548 else { 549 if(hc->bustype == AR_BUS_PCI) 550 arisr = hc->orbase[AR_ISTAT * 4]; 551 else 552 arisr = ar_inb(hc, AR_ISTAT); 553 } 554 } 555 556 if(hc->bustype == AR_BUS_ISA) 557 ARC_SET_OFF(hc); 558 } 559 560 561 /* 562 * This will only start the transmitter. It is assumed that the data 563 * is already there. It is normally called from arstart() or ar_dmac_intr(). 564 * 565 */ 566 static void 567 ar_xmit(struct ar_softc *sc) 568 { 569 #ifndef NETGRAPH 570 struct ifnet *ifp; 571 #endif /* NETGRAPH */ 572 dmac_channel *dmac; 573 574 #ifndef NETGRAPH 575 ifp = &sc->ifsppp.pp_if; 576 #endif /* NETGRAPH */ 577 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 578 579 if(sc->hc->bustype == AR_BUS_ISA) 580 ARC_SET_SCA(sc->hc, sc->scano); 581 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff); 582 583 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff); 584 dmac->dsr = SCA_DSR_DE; 585 586 sc->xmit_busy = 1; 587 588 sc->txb_next_tx++; 589 if(sc->txb_next_tx == AR_TX_BLOCKS) 590 sc->txb_next_tx = 0; 591 592 #ifndef NETGRAPH 593 ifp->if_timer = 2; /* Value in seconds. */ 594 #else /* NETGRAPH */ 595 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 596 #endif /* NETGRAPH */ 597 if(sc->hc->bustype == AR_BUS_ISA) 598 ARC_SET_OFF(sc->hc); 599 } 600 601 /* 602 * This function will be called from the upper level when a user add a 603 * packet to be send, and from the interrupt handler after a finished 604 * transmit. 605 * 606 * NOTE: it should run at spl_imp(). 607 * 608 * This function only place the data in the oncard buffers. It does not 609 * start the transmition. ar_xmit() does that. 610 * 611 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function 612 * that clears that should ensure that the transmitter and its DMA is 613 * in a "good" idle state. 614 */ 615 #ifndef NETGRAPH 616 static void 617 arstart(struct ifnet *ifp) 618 { 619 struct ar_softc *sc = ifp->if_softc; 620 #else /* NETGRAPH */ 621 static void 622 arstart(struct ar_softc *sc) 623 { 624 #endif /* NETGRAPH */ 625 int i, len, tlen; 626 struct mbuf *mtx; 627 u_char *txdata; 628 sca_descriptor *txdesc; 629 struct buf_block *blkp; 630 631 #ifndef NETGRAPH 632 if(!(ifp->if_flags & IFF_RUNNING)) 633 return; 634 #else /* NETGRAPH */ 635 /* XXX */ 636 #endif /* NETGRAPH */ 637 638 top_arstart: 639 640 /* 641 * See if we have space for more packets. 642 */ 643 if(sc->txb_inuse == AR_TX_BLOCKS) { 644 #ifndef NETGRAPH 645 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 646 #else /* NETGRAPH */ 647 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ 648 #endif /* NETGRAPH */ 649 return; 650 } 651 652 #ifndef NETGRAPH 653 mtx = sppp_dequeue(ifp); 654 #else /* NETGRAPH */ 655 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 656 if (mtx == NULL) { 657 IF_DEQUEUE(&sc->xmitq, mtx); 658 } 659 #endif /* NETGRAPH */ 660 if(!mtx) 661 return; 662 663 /* 664 * It is OK to set the memory window outside the loop because 665 * all tx buffers and descriptors are assumed to be in the same 666 * 16K window. 667 */ 668 if(sc->hc->bustype == AR_BUS_ISA) 669 ARC_SET_MEM(sc->hc, sc->block[0].txdesc); 670 671 /* 672 * We stay in this loop until there is nothing in the 673 * TX queue left or the tx buffer is full. 674 */ 675 i = 0; 676 blkp = &sc->block[sc->txb_new]; 677 txdesc = (sca_descriptor *) 678 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk)); 679 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk)); 680 for(;;) { 681 len = mtx->m_pkthdr.len; 682 683 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len)); 684 685 /* 686 * We can do this because the tx buffers don't wrap. 687 */ 688 m_copydata(mtx, 0, len, txdata); 689 tlen = len; 690 while(tlen > AR_BUF_SIZ) { 691 txdesc->stat = 0; 692 txdesc->len = AR_BUF_SIZ; 693 tlen -= AR_BUF_SIZ; 694 txdesc++; 695 txdata += AR_BUF_SIZ; 696 i++; 697 } 698 /* XXX Move into the loop? */ 699 txdesc->stat = SCA_DESC_EOM; 700 txdesc->len = tlen; 701 txdesc++; 702 txdata += AR_BUF_SIZ; 703 i++; 704 705 #ifndef NETGRAPH 706 BPF_MTAP(ifp, mtx); 707 m_freem(mtx); 708 ++sc->ifsppp.pp_if.if_opackets; 709 #else /* NETGRAPH */ 710 m_freem(mtx); 711 sc->outbytes += len; 712 ++sc->opackets; 713 #endif /* NETGRAPH */ 714 715 /* 716 * Check if we have space for another mbuf. 717 * XXX This is hardcoded. A packet won't be larger 718 * than 3 buffers (3 x 512). 719 */ 720 if((i + 3) >= blkp->txmax) 721 break; 722 723 #ifndef NETGRAPH 724 mtx = sppp_dequeue(ifp); 725 #else /* NETGRAPH */ 726 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 727 if (mtx == NULL) { 728 IF_DEQUEUE(&sc->xmitq, mtx); 729 } 730 #endif /* NETGRAPH */ 731 if(!mtx) 732 break; 733 } 734 735 blkp->txtail = i; 736 737 /* 738 * Mark the last descriptor, so that the SCA know where 739 * to stop. 740 */ 741 txdesc--; 742 txdesc->stat |= SCA_DESC_EOT; 743 744 txdesc = (sca_descriptor *)blkp->txdesc; 745 blkp->txeda = (u_short)((u_int)&txdesc[i]); 746 747 #if 0 748 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp); 749 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp); 750 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb); 751 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len); 752 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat); 753 #endif 754 755 sc->txb_inuse++; 756 sc->txb_new++; 757 if(sc->txb_new == AR_TX_BLOCKS) 758 sc->txb_new = 0; 759 760 if(sc->xmit_busy == 0) 761 ar_xmit(sc); 762 763 if(sc->hc->bustype == AR_BUS_ISA) 764 ARC_SET_OFF(sc->hc); 765 766 goto top_arstart; 767 } 768 769 #ifndef NETGRAPH 770 static int 771 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 772 { 773 int s, error; 774 int was_up, should_be_up; 775 struct ar_softc *sc = ifp->if_softc; 776 777 TRC(if_printf(ifp, "arioctl.\n");) 778 779 was_up = ifp->if_flags & IFF_RUNNING; 780 781 error = sppp_ioctl(ifp, cmd, data); 782 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n", 783 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);) 784 if(error) 785 return (error); 786 787 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR)) 788 return (0); 789 790 TRC(if_printf(ifp, "arioctl %s.\n", 791 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");) 792 793 s = splimp(); 794 should_be_up = ifp->if_flags & IFF_RUNNING; 795 796 if(!was_up && should_be_up) { 797 /* Interface should be up -- start it. */ 798 ar_up(sc); 799 arstart(ifp); 800 /* XXX Maybe clear the IFF_UP flag so that the link 801 * will only go up after sppp lcp and ipcp negotiation. 802 */ 803 } else if(was_up && !should_be_up) { 804 /* Interface should be down -- stop it. */ 805 ar_down(sc); 806 sppp_flush(ifp); 807 } 808 splx(s); 809 return (0); 810 } 811 #endif /* NETGRAPH */ 812 813 /* 814 * This is to catch lost tx interrupts. 815 */ 816 static void 817 #ifndef NETGRAPH 818 arwatchdog(struct ifnet *ifp) 819 { 820 struct ar_softc *sc = ifp->if_softc; 821 #else /* NETGRAPH */ 822 arwatchdog(struct ar_softc *sc) 823 { 824 #endif /* NETGRAPH */ 825 msci_channel *msci = &sc->sca->msci[sc->scachan]; 826 827 #ifndef NETGRAPH 828 if(!(ifp->if_flags & IFF_RUNNING)) 829 return; 830 #endif /* NETGRAPH */ 831 832 if(sc->hc->bustype == AR_BUS_ISA) 833 ARC_SET_SCA(sc->hc, sc->scano); 834 835 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */ 836 printf("ar%d: transmit failed, " 837 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n", 838 sc->unit, 839 msci->st0, 840 msci->st1, 841 msci->st3, 842 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr); 843 844 if(msci->st1 & SCA_ST1_UDRN) { 845 msci->cmd = SCA_CMD_TXABORT; 846 msci->cmd = SCA_CMD_TXENABLE; 847 msci->st1 = SCA_ST1_UDRN; 848 } 849 850 sc->xmit_busy = 0; 851 #ifndef NETGRAPH 852 ifp->if_flags &= ~IFF_OACTIVE; 853 #else /* NETGRAPH */ 854 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */ 855 #endif /* NETGRAPH */ 856 857 if(sc->txb_inuse && --sc->txb_inuse) 858 ar_xmit(sc); 859 860 #ifndef NETGRAPH 861 arstart(ifp); 862 #else /* NETGRAPH */ 863 arstart(sc); 864 #endif /* NETGRAPH */ 865 } 866 867 static void 868 ar_up(struct ar_softc *sc) 869 { 870 sca_regs *sca; 871 msci_channel *msci; 872 873 sca = sc->sca; 874 msci = &sca->msci[sc->scachan]; 875 876 TRC(printf("ar%d: sca %p, msci %p, ch %d\n", 877 sc->unit, sca, msci, sc->scachan)); 878 879 /* 880 * Enable transmitter and receiver. 881 * Raise DTR and RTS. 882 * Enable interrupts. 883 */ 884 if(sc->hc->bustype == AR_BUS_ISA) 885 ARC_SET_SCA(sc->hc, sc->scano); 886 887 /* XXX 888 * What about using AUTO mode in msci->md0 ??? 889 * And what about CTS/DCD etc... ? 890 */ 891 if(sc->hc->handshake & AR_SHSK_RTS) 892 msci->ctl &= ~SCA_CTL_RTS; 893 if(sc->hc->handshake & AR_SHSK_DTR) { 894 sc->hc->txc_dtr[sc->scano] &= sc->scachan ? 895 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0; 896 if(sc->hc->bustype == AR_BUS_PCI) 897 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 898 sc->hc->txc_dtr[sc->scano]; 899 else 900 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], 901 sc->hc->txc_dtr[sc->scano]); 902 } 903 904 if(sc->scachan == 0) { 905 sca->ier0 |= 0x0F; 906 sca->ier1 |= 0x0F; 907 } else { 908 sca->ier0 |= 0xF0; 909 sca->ier1 |= 0xF0; 910 } 911 912 msci->cmd = SCA_CMD_RXENABLE; 913 if(sc->hc->bustype == AR_BUS_ISA) 914 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ 915 msci->cmd = SCA_CMD_TXENABLE; 916 917 if(sc->hc->bustype == AR_BUS_ISA) 918 ARC_SET_OFF(sc->hc); 919 #ifdef NETGRAPH 920 untimeout(ngar_watchdog_frame, sc, sc->handle); 921 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 922 sc->running = 1; 923 #endif /* NETGRAPH */ 924 } 925 926 static void 927 ar_down(struct ar_softc *sc) 928 { 929 sca_regs *sca; 930 msci_channel *msci; 931 932 sca = sc->sca; 933 msci = &sca->msci[sc->scachan]; 934 935 #ifdef NETGRAPH 936 untimeout(ngar_watchdog_frame, sc, sc->handle); 937 sc->running = 0; 938 #endif /* NETGRAPH */ 939 /* 940 * Disable transmitter and receiver. 941 * Lower DTR and RTS. 942 * Disable interrupts. 943 */ 944 if(sc->hc->bustype == AR_BUS_ISA) 945 ARC_SET_SCA(sc->hc, sc->scano); 946 msci->cmd = SCA_CMD_RXDISABLE; 947 if(sc->hc->bustype == AR_BUS_ISA) 948 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ 949 msci->cmd = SCA_CMD_TXDISABLE; 950 951 if(sc->hc->handshake & AR_SHSK_RTS) 952 msci->ctl |= SCA_CTL_RTS; 953 if(sc->hc->handshake & AR_SHSK_DTR) { 954 sc->hc->txc_dtr[sc->scano] |= sc->scachan ? 955 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0; 956 if(sc->hc->bustype == AR_BUS_PCI) 957 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 958 sc->hc->txc_dtr[sc->scano]; 959 else 960 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], 961 sc->hc->txc_dtr[sc->scano]); 962 } 963 964 if(sc->scachan == 0) { 965 sca->ier0 &= ~0x0F; 966 sca->ier1 &= ~0x0F; 967 } else { 968 sca->ier0 &= ~0xF0; 969 sca->ier1 &= ~0xF0; 970 } 971 972 if(sc->hc->bustype == AR_BUS_ISA) 973 ARC_SET_OFF(sc->hc); 974 } 975 976 static int 977 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel) 978 { 979 int ctype, i, val, x; 980 volatile u_char *pimctrl; 981 982 ctype = 0; 983 val = 0; 984 985 pimctrl = hc->orbase + AR_PIMCTRL; 986 987 /* Reset the PIM */ 988 *pimctrl = 0x00; 989 *pimctrl = AR_PIM_STROBE; 990 991 /* Check if there is a PIM */ 992 *pimctrl = 0x00; 993 *pimctrl = AR_PIM_READ; 994 x = *pimctrl; 995 TRC(printf("x = %x", x)); 996 if(x & AR_PIM_DATA) { 997 printf("No PIM installed\n"); 998 return (AR_IFACE_UNKNOWN); 999 } 1000 1001 x = (x >> 1) & 0x01; 1002 val |= x << 0; 1003 1004 /* Now read the next 15 bits */ 1005 for(i = 1; i < 16; i++) { 1006 *pimctrl = AR_PIM_READ; 1007 *pimctrl = AR_PIM_READ | AR_PIM_STROBE; 1008 x = *pimctrl; 1009 TRC(printf(" %x ", x)); 1010 x = (x >> 1) & 0x01; 1011 val |= x << i; 1012 if(i == 8 && (val & 0x000f) == 0x0004) { 1013 int ii; 1014 1015 /* Start bit */ 1016 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1017 *pimctrl = AR_PIM_A2D_DOUT; 1018 1019 /* Mode bit */ 1020 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1021 *pimctrl = AR_PIM_A2D_DOUT; 1022 1023 /* Sign bit */ 1024 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1025 *pimctrl = AR_PIM_A2D_DOUT; 1026 1027 /* Select channel */ 1028 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2); 1029 *pimctrl = ((channel & 2) << 2); 1030 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3); 1031 *pimctrl = ((channel & 1) << 3); 1032 1033 *pimctrl = AR_PIM_A2D_STROBE; 1034 1035 x = *pimctrl; 1036 if(x & AR_PIM_DATA) 1037 printf("\nOops A2D start bit not zero (%X)\n", x); 1038 1039 for(ii = 7; ii >= 0; ii--) { 1040 *pimctrl = 0x00; 1041 *pimctrl = AR_PIM_A2D_STROBE; 1042 x = *pimctrl; 1043 if(x & AR_PIM_DATA) 1044 ctype |= 1 << ii; 1045 } 1046 } 1047 } 1048 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype)); 1049 *pimctrl = AR_PIM_MODEG; 1050 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1051 if(ctype > 255) 1052 return (AR_IFACE_UNKNOWN); 1053 if(ctype > 239) 1054 return (AR_IFACE_V_35); 1055 if(ctype > 207) 1056 return (AR_IFACE_EIA_232); 1057 if(ctype > 178) 1058 return (AR_IFACE_X_21); 1059 if(ctype > 150) 1060 return (AR_IFACE_EIA_530); 1061 if(ctype > 25) 1062 return (AR_IFACE_UNKNOWN); 1063 if(ctype > 7) 1064 return (AR_IFACE_LOOPBACK); 1065 return (AR_IFACE_UNKNOWN); 1066 } 1067 1068 /* 1069 * Initialize the card, allocate memory for the ar_softc structures 1070 * and fill in the pointers. 1071 */ 1072 static void 1073 arc_init(struct ar_hardc *hc) 1074 { 1075 struct ar_softc *sc; 1076 int x; 1077 u_int chanmem; 1078 u_int bufmem; 1079 u_int next; 1080 u_int descneeded; 1081 u_char isr, mar; 1082 u_long memst; 1083 1084 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc), 1085 M_DEVBUF, M_WAITOK | M_ZERO); 1086 if (sc == NULL) 1087 return; 1088 hc->sc = sc; 1089 1090 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET | 1091 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1092 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1093 hc->txc_dtr_off[0] = AR_TXC_DTR0; 1094 hc->txc_dtr_off[1] = AR_TXC_DTR2; 1095 if(hc->bustype == AR_BUS_PCI) { 1096 hc->txc_dtr_off[0] *= 4; 1097 hc->txc_dtr_off[1] *= 4; 1098 } 1099 1100 /* 1101 * reset the card and wait at least 1uS. 1102 */ 1103 if(hc->bustype == AR_BUS_PCI) 1104 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET & 1105 hc->txc_dtr[0]; 1106 else 1107 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & 1108 hc->txc_dtr[0]); 1109 DELAY(2); 1110 if(hc->bustype == AR_BUS_PCI) 1111 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1112 else 1113 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); 1114 1115 if(hc->bustype == AR_BUS_ISA) { 1116 /* 1117 * Configure the card. 1118 * Mem address, irq, 1119 */ 1120 memst = rman_get_start(hc->res_memory); 1121 mar = memst >> 16; 1122 isr = irqtable[hc->isa_irq] << 1; 1123 if(isr == 0) 1124 printf("ar%d: Warning illegal interrupt %d\n", 1125 hc->cunit, hc->isa_irq); 1126 isr = isr | ((memst & 0xc000) >> 10); 1127 1128 hc->sca[0] = (sca_regs *)hc->mem_start; 1129 hc->sca[1] = (sca_regs *)hc->mem_start; 1130 1131 ar_outb(hc, AR_MEM_SEL, mar); 1132 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN); 1133 } 1134 1135 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM) 1136 for(x = 0; x < hc->numports; x++) 1137 hc->interface[x] = ar_read_pim_iface(hc, x); 1138 1139 /* 1140 * Set the TX clock direction and enable TX. 1141 */ 1142 for(x=0;x<hc->numports;x++) { 1143 switch(hc->interface[x]) { 1144 case AR_IFACE_V_35: 1145 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1146 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1147 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1148 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1; 1149 break; 1150 case AR_IFACE_EIA_530: 1151 case AR_IFACE_COMBO: 1152 case AR_IFACE_X_21: 1153 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1154 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1155 break; 1156 } 1157 } 1158 1159 if(hc->bustype == AR_BUS_PCI) 1160 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1161 else 1162 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); 1163 if(hc->numports > NCHAN) { 1164 if(hc->bustype == AR_BUS_PCI) 1165 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1]; 1166 else 1167 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]); 1168 } 1169 1170 chanmem = hc->memsize / hc->numports; 1171 next = 0; 1172 1173 for(x=0;x<hc->numports;x++, sc++) { 1174 int blk; 1175 1176 sc->sca = hc->sca[x / NCHAN]; 1177 1178 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1179 sc->block[blk].txdesc = next; 1180 bufmem = (16 * 1024) / AR_TX_BLOCKS; 1181 descneeded = bufmem / AR_BUF_SIZ; 1182 sc->block[blk].txstart = sc->block[blk].txdesc + 1183 ((((descneeded * sizeof(sca_descriptor)) / 1184 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1185 sc->block[blk].txend = next + bufmem; 1186 sc->block[blk].txmax = 1187 (sc->block[blk].txend - sc->block[blk].txstart) 1188 / AR_BUF_SIZ; 1189 next += bufmem; 1190 1191 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, " 1192 "txend %x, txmax %d\n", 1193 x, 1194 blk, 1195 sc->block[blk].txdesc, 1196 sc->block[blk].txstart, 1197 sc->block[blk].txend, 1198 sc->block[blk].txmax)); 1199 } 1200 1201 sc->rxdesc = next; 1202 bufmem = chanmem - (bufmem * AR_TX_BLOCKS); 1203 descneeded = bufmem / AR_BUF_SIZ; 1204 sc->rxstart = sc->rxdesc + 1205 ((((descneeded * sizeof(sca_descriptor)) / 1206 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1207 sc->rxend = next + bufmem; 1208 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ; 1209 next += bufmem; 1210 TRC(printf("ar%d: rxdesc %x, rxstart %x, " 1211 "rxend %x, rxmax %d\n", 1212 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax)); 1213 } 1214 1215 if(hc->bustype == AR_BUS_PCI) 1216 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1217 } 1218 1219 1220 /* 1221 * The things done here are channel independent. 1222 * 1223 * Configure the sca waitstates. 1224 * Configure the global interrupt registers. 1225 * Enable master dma enable. 1226 */ 1227 static void 1228 ar_init_sca(struct ar_hardc *hc, int scano) 1229 { 1230 sca_regs *sca; 1231 1232 sca = hc->sca[scano]; 1233 if(hc->bustype == AR_BUS_ISA) 1234 ARC_SET_SCA(hc, scano); 1235 1236 /* 1237 * Do the wait registers. 1238 * Set everything to 0 wait states. 1239 */ 1240 sca->pabr0 = 0; 1241 sca->pabr1 = 0; 1242 sca->wcrl = 0; 1243 sca->wcrm = 0; 1244 sca->wcrh = 0; 1245 1246 /* 1247 * Configure the interrupt registers. 1248 * Most are cleared until the interface is configured. 1249 */ 1250 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */ 1251 sca->ier1 = 0x00; /* DMAC interrupts */ 1252 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */ 1253 sca->itcr = 0x00; /* Use ivr and no intr ack */ 1254 sca->ivr = 0x40; /* Fill in the interrupt vector. */ 1255 sca->imvr = 0x40; 1256 1257 /* 1258 * Configure the timers. 1259 * XXX Later 1260 */ 1261 1262 1263 /* 1264 * Set the DMA channel priority to rotate between 1265 * all four channels. 1266 * 1267 * Enable all dma channels. 1268 */ 1269 if(hc->bustype == AR_BUS_PCI) { 1270 u_char *t; 1271 1272 /* 1273 * Stupid problem with the PCI interface chip that break 1274 * things. 1275 * XXX 1276 */ 1277 t = (u_char *)sca; 1278 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2; 1279 t[AR_PCI_SCA_DMER] = SCA_DMER_EN; 1280 } else { 1281 sca->pcr = SCA_PCR_PR2; 1282 sca->dmer = SCA_DMER_EN; 1283 } 1284 } 1285 1286 1287 /* 1288 * Configure the msci 1289 * 1290 * NOTE: The serial port configuration is hardcoded at the moment. 1291 */ 1292 static void 1293 ar_init_msci(struct ar_softc *sc) 1294 { 1295 msci_channel *msci; 1296 1297 msci = &sc->sca->msci[sc->scachan]; 1298 1299 if(sc->hc->bustype == AR_BUS_ISA) 1300 ARC_SET_SCA(sc->hc, sc->scano); 1301 1302 msci->cmd = SCA_CMD_RESET; 1303 1304 msci->md0 = SCA_MD0_CRC_1 | 1305 SCA_MD0_CRC_CCITT | 1306 SCA_MD0_CRC_ENABLE | 1307 SCA_MD0_MODE_HDLC; 1308 msci->md1 = SCA_MD1_NOADDRCHK; 1309 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ; 1310 1311 /* 1312 * Acording to the manual I should give a reset after changing the 1313 * mode registers. 1314 */ 1315 msci->cmd = SCA_CMD_RXRESET; 1316 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS; 1317 1318 /* 1319 * For now all interfaces are programmed to use the RX clock for 1320 * the TX clock. 1321 */ 1322 switch(sc->hc->interface[sc->subunit]) { 1323 case AR_IFACE_V_35: 1324 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1325 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1; 1326 break; 1327 case AR_IFACE_X_21: 1328 case AR_IFACE_EIA_530: 1329 case AR_IFACE_COMBO: 1330 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1331 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1; 1332 } 1333 1334 msci->tmc = 153; /* This give 64k for loopback */ 1335 1336 /* XXX 1337 * Disable all interrupts for now. I think if you are using 1338 * the dmac you don't use these interrupts. 1339 */ 1340 msci->ie0 = 0; 1341 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */ 1342 msci->ie2 = 0; 1343 msci->fie = 0; 1344 1345 msci->sa0 = 0; 1346 msci->sa1 = 0; 1347 1348 msci->idl = 0x7E; /* XXX This is what cisco does. */ 1349 1350 /* 1351 * This is what the ARNET diags use. 1352 */ 1353 msci->rrc = 0x0E; 1354 msci->trc0 = 0x12; 1355 msci->trc1 = 0x1F; 1356 } 1357 1358 /* 1359 * Configure the rx dma controller. 1360 */ 1361 static void 1362 ar_init_rx_dmac(struct ar_softc *sc) 1363 { 1364 dmac_channel *dmac; 1365 sca_descriptor *rxd; 1366 u_int rxbuf; 1367 u_int rxda; 1368 u_int rxda_d; 1369 int x = 0; 1370 1371 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1372 1373 if(sc->hc->bustype == AR_BUS_ISA) 1374 ARC_SET_MEM(sc->hc, sc->rxdesc); 1375 1376 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk)); 1377 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk); 1378 1379 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) { 1380 rxda = (u_int)&rxd[1] - rxda_d; 1381 rxd->cp = (u_short)(rxda & 0xfffful); 1382 1383 x++; 1384 if(x < 6) 1385 TRC(printf("Descrp %p, data pt %x, data %x, ", 1386 rxd, rxda, rxbuf)); 1387 1388 rxd->bp = (u_short)(rxbuf & 0xfffful); 1389 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff); 1390 rxd->len = 0; 1391 rxd->stat = 0xff; /* The sca write here when it is finished. */ 1392 1393 if(x < 6) 1394 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp)); 1395 } 1396 rxd--; 1397 rxd->cp = (u_short)(sc->rxdesc & 0xfffful); 1398 1399 sc->rxhind = 0; 1400 1401 if(sc->hc->bustype == AR_BUS_ISA) 1402 ARC_SET_SCA(sc->hc, sc->scano); 1403 1404 dmac->dsr = 0; /* Disable DMA transfer */ 1405 dmac->dcr = SCA_DCR_ABRT; 1406 1407 /* XXX maybe also SCA_DMR_CNTE */ 1408 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1409 dmac->bfl = AR_BUF_SIZ; 1410 1411 dmac->cda = (u_short)(sc->rxdesc & 0xffff); 1412 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff); 1413 1414 rxd = (sca_descriptor *)sc->rxstart; 1415 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff); 1416 1417 dmac->dir = 0xF0; 1418 1419 dmac->dsr = SCA_DSR_DE; 1420 } 1421 1422 /* 1423 * Configure the TX DMA descriptors. 1424 * Initialize the needed values and chain the descriptors. 1425 */ 1426 static void 1427 ar_init_tx_dmac(struct ar_softc *sc) 1428 { 1429 dmac_channel *dmac; 1430 struct buf_block *blkp; 1431 int blk; 1432 sca_descriptor *txd; 1433 u_int txbuf; 1434 u_int txda; 1435 u_int txda_d; 1436 1437 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1438 1439 if(sc->hc->bustype == AR_BUS_ISA) 1440 ARC_SET_MEM(sc->hc, sc->block[0].txdesc); 1441 1442 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1443 blkp = &sc->block[blk]; 1444 txd = (sca_descriptor *)(sc->hc->mem_start + 1445 (blkp->txdesc&sc->hc->winmsk)); 1446 txda_d = (u_int)sc->hc->mem_start - 1447 (blkp->txdesc & ~sc->hc->winmsk); 1448 1449 txbuf=blkp->txstart; 1450 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) { 1451 txda = (u_int)&txd[1] - txda_d; 1452 txd->cp = (u_short)(txda & 0xfffful); 1453 1454 txd->bp = (u_short)(txbuf & 0xfffful); 1455 txd->bpb = (u_char)((txbuf >> 16) & 0xff); 1456 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n", 1457 sc->unit, txbuf, txd->bpb, txd->bp)); 1458 txd->len = 0; 1459 txd->stat = 0; 1460 } 1461 txd--; 1462 txd->cp = (u_short)(blkp->txdesc & 0xfffful); 1463 1464 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start; 1465 TRC(printf("TX Descriptors start %x, end %x.\n", 1466 blkp->txdesc, 1467 blkp->txtail)); 1468 } 1469 1470 if(sc->hc->bustype == AR_BUS_ISA) 1471 ARC_SET_SCA(sc->hc, sc->scano); 1472 1473 dmac->dsr = 0; /* Disable DMA */ 1474 dmac->dcr = SCA_DCR_ABRT; 1475 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1476 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF; 1477 1478 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff); 1479 } 1480 1481 1482 /* 1483 * Look through the descriptors to see if there is a complete packet 1484 * available. Stop if we get to where the sca is busy. 1485 * 1486 * Return the length and status of the packet. 1487 * Return nonzero if there is a packet available. 1488 * 1489 * NOTE: 1490 * It seems that we get the interrupt a bit early. The updateing of 1491 * descriptor values is not always completed when this is called. 1492 */ 1493 static int 1494 ar_packet_avail(struct ar_softc *sc, 1495 int *len, 1496 u_char *rxstat) 1497 { 1498 dmac_channel *dmac; 1499 sca_descriptor *rxdesc; 1500 sca_descriptor *endp; 1501 sca_descriptor *cda; 1502 1503 if(sc->hc->bustype == AR_BUS_ISA) 1504 ARC_SET_SCA(sc->hc, sc->scano); 1505 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1506 cda = (sca_descriptor *)(sc->hc->mem_start + 1507 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1508 1509 if(sc->hc->bustype == AR_BUS_ISA) 1510 ARC_SET_MEM(sc->hc, sc->rxdesc); 1511 rxdesc = (sca_descriptor *) 1512 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1513 endp = rxdesc; 1514 rxdesc = &rxdesc[sc->rxhind]; 1515 endp = &endp[sc->rxmax]; 1516 1517 *len = 0; 1518 1519 while(rxdesc != cda) { 1520 *len += rxdesc->len; 1521 1522 if(rxdesc->stat & SCA_DESC_EOM) { 1523 *rxstat = rxdesc->stat; 1524 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n", 1525 sc->unit, *len, *rxstat)); 1526 return (1); 1527 } 1528 1529 rxdesc++; 1530 if(rxdesc == endp) 1531 rxdesc = (sca_descriptor *) 1532 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1533 } 1534 1535 *len = 0; 1536 *rxstat = 0; 1537 return (0); 1538 } 1539 1540 1541 /* 1542 * Copy a packet from the on card memory into a provided mbuf. 1543 * Take into account that buffers wrap and that a packet may 1544 * be larger than a buffer. 1545 */ 1546 static void 1547 ar_copy_rxbuf(struct mbuf *m, 1548 struct ar_softc *sc, 1549 int len) 1550 { 1551 sca_descriptor *rxdesc; 1552 u_int rxdata; 1553 u_int rxmax; 1554 u_int off = 0; 1555 u_int tlen; 1556 1557 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ); 1558 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ); 1559 1560 rxdesc = (sca_descriptor *) 1561 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1562 rxdesc = &rxdesc[sc->rxhind]; 1563 1564 while(len) { 1565 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ; 1566 if(sc->hc->bustype == AR_BUS_ISA) 1567 ARC_SET_MEM(sc->hc, rxdata); 1568 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk), 1569 mtod(m, caddr_t) + off, 1570 tlen); 1571 1572 off += tlen; 1573 len -= tlen; 1574 1575 if(sc->hc->bustype == AR_BUS_ISA) 1576 ARC_SET_MEM(sc->hc, sc->rxdesc); 1577 rxdesc->len = 0; 1578 rxdesc->stat = 0xff; 1579 1580 rxdata += AR_BUF_SIZ; 1581 rxdesc++; 1582 if(rxdata == rxmax) { 1583 rxdata = sc->rxstart; 1584 rxdesc = (sca_descriptor *) 1585 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1586 } 1587 } 1588 } 1589 1590 /* 1591 * If single is set, just eat a packet. Otherwise eat everything up to 1592 * where cda points. Update pointers to point to the next packet. 1593 */ 1594 static void 1595 ar_eat_packet(struct ar_softc *sc, int single) 1596 { 1597 dmac_channel *dmac; 1598 sca_descriptor *rxdesc; 1599 sca_descriptor *endp; 1600 sca_descriptor *cda; 1601 int loopcnt = 0; 1602 u_char stat; 1603 1604 if(sc->hc->bustype == AR_BUS_ISA) 1605 ARC_SET_SCA(sc->hc, sc->scano); 1606 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1607 cda = (sca_descriptor *)(sc->hc->mem_start + 1608 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1609 1610 /* 1611 * Loop until desc->stat == (0xff || EOM) 1612 * Clear the status and length in the descriptor. 1613 * Increment the descriptor. 1614 */ 1615 if(sc->hc->bustype == AR_BUS_ISA) 1616 ARC_SET_MEM(sc->hc, sc->rxdesc); 1617 rxdesc = (sca_descriptor *) 1618 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1619 endp = rxdesc; 1620 rxdesc = &rxdesc[sc->rxhind]; 1621 endp = &endp[sc->rxmax]; 1622 1623 while(rxdesc != cda) { 1624 loopcnt++; 1625 if(loopcnt > sc->rxmax) { 1626 printf("ar%d: eat pkt %d loop, cda %p, " 1627 "rxdesc %p, stat %x.\n", 1628 sc->unit, 1629 loopcnt, 1630 (void *)cda, 1631 (void *)rxdesc, 1632 rxdesc->stat); 1633 break; 1634 } 1635 1636 stat = rxdesc->stat; 1637 1638 rxdesc->len = 0; 1639 rxdesc->stat = 0xff; 1640 1641 rxdesc++; 1642 sc->rxhind++; 1643 if(rxdesc == endp) { 1644 rxdesc = (sca_descriptor *) 1645 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1646 sc->rxhind = 0; 1647 } 1648 1649 if(single && (stat == SCA_DESC_EOM)) 1650 break; 1651 } 1652 1653 /* 1654 * Update the eda to the previous descriptor. 1655 */ 1656 if(sc->hc->bustype == AR_BUS_ISA) 1657 ARC_SET_SCA(sc->hc, sc->scano); 1658 1659 rxdesc = (sca_descriptor *)sc->rxdesc; 1660 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1661 1662 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1663 (u_short)((u_int)rxdesc & 0xffff); 1664 } 1665 1666 1667 /* 1668 * While there is packets available in the rx buffer, read them out 1669 * into mbufs and ship them off. 1670 */ 1671 static void 1672 ar_get_packets(struct ar_softc *sc) 1673 { 1674 sca_descriptor *rxdesc; 1675 struct mbuf *m = NULL; 1676 int i; 1677 int len; 1678 u_char rxstat; 1679 #ifdef NETGRAPH 1680 int error; 1681 #endif 1682 1683 while(ar_packet_avail(sc, &len, &rxstat)) { 1684 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat)); 1685 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 1686 MGETHDR(m, M_DONTWAIT, MT_DATA); 1687 if(m == NULL) { 1688 /* eat packet if get mbuf fail!! */ 1689 ar_eat_packet(sc, 1); 1690 continue; 1691 } 1692 #ifndef NETGRAPH 1693 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if; 1694 #else /* NETGRAPH */ 1695 m->m_pkthdr.rcvif = NULL; 1696 sc->inbytes += len; 1697 sc->inlast = 0; 1698 #endif /* NETGRAPH */ 1699 m->m_pkthdr.len = m->m_len = len; 1700 if(len > MHLEN) { 1701 MCLGET(m, M_DONTWAIT); 1702 if((m->m_flags & M_EXT) == 0) { 1703 m_freem(m); 1704 ar_eat_packet(sc, 1); 1705 continue; 1706 } 1707 } 1708 ar_copy_rxbuf(m, sc, len); 1709 #ifndef NETGRAPH 1710 BPF_MTAP(&sc->ifsppp.pp_if, m); 1711 sppp_input(&sc->ifsppp.pp_if, m); 1712 sc->ifsppp.pp_if.if_ipackets++; 1713 #else /* NETGRAPH */ 1714 NG_SEND_DATA_ONLY(error, sc->hook, m); 1715 sc->ipackets++; 1716 #endif /* NETGRAPH */ 1717 1718 /* 1719 * Update the eda to the previous descriptor. 1720 */ 1721 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ; 1722 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 1723 1724 if(sc->hc->bustype == AR_BUS_ISA) 1725 ARC_SET_SCA(sc->hc, sc->scano); 1726 1727 rxdesc = (sca_descriptor *)sc->rxdesc; 1728 rxdesc = 1729 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1730 1731 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1732 (u_short)((u_int)rxdesc & 0xffff); 1733 } else { 1734 int tries = 5; 1735 1736 while((rxstat == 0xff) && --tries) 1737 ar_packet_avail(sc, &len, &rxstat); 1738 1739 /* 1740 * It look like we get an interrupt early 1741 * sometimes and then the status is not 1742 * filled in yet. 1743 */ 1744 if(tries && (tries != 5)) 1745 continue; 1746 1747 ar_eat_packet(sc, 1); 1748 1749 #ifndef NETGRAPH 1750 sc->ifsppp.pp_if.if_ierrors++; 1751 #else /* NETGRAPH */ 1752 sc->ierrors[0]++; 1753 #endif /* NETGRAPH */ 1754 1755 if(sc->hc->bustype == AR_BUS_ISA) 1756 ARC_SET_SCA(sc->hc, sc->scano); 1757 1758 TRCL(printf("ar%d: Receive error chan %d, " 1759 "stat %x, msci st3 %x," 1760 "rxhind %d, cda %x, eda %x.\n", 1761 sc->unit, 1762 sc->scachan, 1763 rxstat, 1764 sc->sca->msci[sc->scachan].st3, 1765 sc->rxhind, 1766 sc->sca->dmac[ 1767 DMAC_RXCH(sc->scachan)].cda, 1768 sc->sca->dmac[ 1769 DMAC_RXCH(sc->scachan)].eda)); 1770 } 1771 } 1772 } 1773 1774 1775 /* 1776 * All DMA interrupts come here. 1777 * 1778 * Each channel has two interrupts. 1779 * Interrupt A for errors and Interrupt B for normal stuff like end 1780 * of transmit or receive dmas. 1781 */ 1782 static void 1783 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1) 1784 { 1785 u_char dsr; 1786 u_char dotxstart = isr1; 1787 int mch; 1788 struct ar_softc *sc; 1789 sca_regs *sca; 1790 dmac_channel *dmac; 1791 1792 sca = hc->sca[scano]; 1793 mch = 0; 1794 /* 1795 * Shortcut if there is no interrupts for dma channel 0 or 1 1796 */ 1797 if((isr1 & 0x0F) == 0) { 1798 mch = 1; 1799 isr1 >>= 4; 1800 } 1801 1802 do { 1803 sc = &hc->sc[mch + (NCHAN * scano)]; 1804 1805 /* 1806 * Transmit channel 1807 */ 1808 if(isr1 & 0x0C) { 1809 dmac = &sca->dmac[DMAC_TXCH(mch)]; 1810 1811 if(hc->bustype == AR_BUS_ISA) 1812 ARC_SET_SCA(hc, scano); 1813 1814 dsr = dmac->dsr; 1815 dmac->dsr = dsr; 1816 1817 /* Counter overflow */ 1818 if(dsr & SCA_DSR_COF) { 1819 printf("ar%d: TX DMA Counter overflow, " 1820 "txpacket no %lu.\n", 1821 sc->unit, 1822 #ifndef NETGRAPH 1823 sc->ifsppp.pp_if.if_opackets); 1824 sc->ifsppp.pp_if.if_oerrors++; 1825 #else /* NETGRAPH */ 1826 sc->opackets); 1827 sc->oerrors++; 1828 #endif /* NETGRAPH */ 1829 } 1830 1831 /* Buffer overflow */ 1832 if(dsr & SCA_DSR_BOF) { 1833 printf("ar%d: TX DMA Buffer overflow, " 1834 "txpacket no %lu, dsr %02x, " 1835 "cda %04x, eda %04x.\n", 1836 sc->unit, 1837 #ifndef NETGRAPH 1838 sc->ifsppp.pp_if.if_opackets, 1839 #else /* NETGRAPH */ 1840 sc->opackets, 1841 #endif /* NETGRAPH */ 1842 dsr, 1843 dmac->cda, 1844 dmac->eda); 1845 #ifndef NETGRAPH 1846 sc->ifsppp.pp_if.if_oerrors++; 1847 #else /* NETGRAPH */ 1848 sc->oerrors++; 1849 #endif /* NETGRAPH */ 1850 } 1851 1852 /* End of Transfer */ 1853 if(dsr & SCA_DSR_EOT) { 1854 /* 1855 * This should be the most common case. 1856 * 1857 * Clear the IFF_OACTIVE flag. 1858 * 1859 * Call arstart to start a new transmit if 1860 * there is data to transmit. 1861 */ 1862 sc->xmit_busy = 0; 1863 #ifndef NETGRAPH 1864 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 1865 sc->ifsppp.pp_if.if_timer = 0; 1866 #else /* NETGRAPH */ 1867 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */ 1868 sc->out_dog = 0; /* XXX */ 1869 #endif /* NETGRAPH */ 1870 1871 if(sc->txb_inuse && --sc->txb_inuse) 1872 ar_xmit(sc); 1873 } 1874 } 1875 1876 /* 1877 * Receive channel 1878 */ 1879 if(isr1 & 0x03) { 1880 dmac = &sca->dmac[DMAC_RXCH(mch)]; 1881 1882 if(hc->bustype == AR_BUS_ISA) 1883 ARC_SET_SCA(hc, scano); 1884 1885 dsr = dmac->dsr; 1886 dmac->dsr = dsr; 1887 1888 TRC(printf("AR: RX DSR %x\n", dsr)); 1889 1890 /* End of frame */ 1891 if(dsr & SCA_DSR_EOM) { 1892 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;) 1893 TRC(int ind = sc->rxhind;) 1894 1895 ar_get_packets(sc); 1896 #ifndef NETGRAPH 1897 #define IPACKETS sc->ifsppp.pp_if.if_ipackets 1898 #else /* NETGRAPH */ 1899 #define IPACKETS sc->ipackets 1900 #endif /* NETGRAPH */ 1901 TRC(if(tt == IPACKETS) { 1902 sca_descriptor *rxdesc; 1903 int i; 1904 1905 if(hc->bustype == AR_BUS_ISA) 1906 ARC_SET_SCA(hc, scano); 1907 printf("AR: RXINTR isr1 %x, dsr %x, " 1908 "no data %d pkts, orxhind %d.\n", 1909 dotxstart, 1910 dsr, 1911 tt, 1912 ind); 1913 printf("AR: rxdesc %x, rxstart %x, " 1914 "rxend %x, rxhind %d, " 1915 "rxmax %d.\n", 1916 sc->rxdesc, 1917 sc->rxstart, 1918 sc->rxend, 1919 sc->rxhind, 1920 sc->rxmax); 1921 printf("AR: cda %x, eda %x.\n", 1922 dmac->cda, 1923 dmac->eda); 1924 1925 if(sc->hc->bustype == AR_BUS_ISA) 1926 ARC_SET_MEM(sc->hc, 1927 sc->rxdesc); 1928 rxdesc = (sca_descriptor *) 1929 (sc->hc->mem_start + 1930 (sc->rxdesc & sc->hc->winmsk)); 1931 rxdesc = &rxdesc[sc->rxhind]; 1932 for(i=0;i<3;i++,rxdesc++) 1933 printf("AR: rxdesc->stat %x, " 1934 "len %d.\n", 1935 rxdesc->stat, 1936 rxdesc->len); 1937 }) 1938 } 1939 1940 /* Counter overflow */ 1941 if(dsr & SCA_DSR_COF) { 1942 printf("ar%d: RX DMA Counter overflow, " 1943 "rxpkts %lu.\n", 1944 sc->unit, 1945 #ifndef NETGRAPH 1946 sc->ifsppp.pp_if.if_ipackets); 1947 sc->ifsppp.pp_if.if_ierrors++; 1948 #else /* NETGRAPH */ 1949 sc->ipackets); 1950 sc->ierrors[1]++; 1951 #endif /* NETGRAPH */ 1952 } 1953 1954 /* Buffer overflow */ 1955 if(dsr & SCA_DSR_BOF) { 1956 if(hc->bustype == AR_BUS_ISA) 1957 ARC_SET_SCA(hc, scano); 1958 printf("ar%d: RX DMA Buffer overflow, " 1959 "rxpkts %lu, rxind %d, " 1960 "cda %x, eda %x, dsr %x.\n", 1961 sc->unit, 1962 #ifndef NETGRAPH 1963 sc->ifsppp.pp_if.if_ipackets, 1964 #else /* NETGRAPH */ 1965 sc->ipackets, 1966 #endif /* NETGRAPH */ 1967 sc->rxhind, 1968 dmac->cda, 1969 dmac->eda, 1970 dsr); 1971 /* 1972 * Make sure we eat as many as possible. 1973 * Then get the system running again. 1974 */ 1975 ar_eat_packet(sc, 0); 1976 #ifndef NETGRAPH 1977 sc->ifsppp.pp_if.if_ierrors++; 1978 #else /* NETGRAPH */ 1979 sc->ierrors[2]++; 1980 #endif /* NETGRAPH */ 1981 if(hc->bustype == AR_BUS_ISA) 1982 ARC_SET_SCA(hc, scano); 1983 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ; 1984 dmac->dsr = SCA_DSR_DE; 1985 1986 TRC(printf("ar%d: RX DMA Buffer overflow, " 1987 "rxpkts %lu, rxind %d, " 1988 "cda %x, eda %x, dsr %x. After\n", 1989 sc->unit, 1990 sc->ifsppp.pp_if.if_ipackets, 1991 sc->rxhind, 1992 dmac->cda, 1993 dmac->eda, 1994 dmac->dsr);) 1995 } 1996 1997 /* End of Transfer */ 1998 if(dsr & SCA_DSR_EOT) { 1999 /* 2000 * If this happen, it means that we are 2001 * receiving faster than what the processor 2002 * can handle. 2003 * 2004 * XXX We should enable the dma again. 2005 */ 2006 printf("ar%d: RX End of transfer, rxpkts %lu.\n", 2007 sc->unit, 2008 #ifndef NETGRAPH 2009 sc->ifsppp.pp_if.if_ipackets); 2010 sc->ifsppp.pp_if.if_ierrors++; 2011 #else /* NETGRAPH */ 2012 sc->ipackets); 2013 sc->ierrors[3]++; 2014 #endif /* NETGRAPH */ 2015 } 2016 } 2017 2018 isr1 >>= 4; 2019 2020 mch++; 2021 }while((mch<NCHAN) && isr1); 2022 2023 /* 2024 * Now that we have done all the urgent things, see if we 2025 * can fill the transmit buffers. 2026 */ 2027 for(mch = 0; mch < NCHAN; mch++) { 2028 if(dotxstart & 0x0C) { 2029 sc = &hc->sc[mch + (NCHAN * scano)]; 2030 #ifndef NETGRAPH 2031 arstart(&sc->ifsppp.pp_if); 2032 #else /* NETGRAPH */ 2033 arstart(sc); 2034 #endif /* NETGRAPH */ 2035 } 2036 dotxstart >>= 4; 2037 } 2038 } 2039 2040 static void 2041 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0) 2042 { 2043 printf("arc%d: ARINTR: MSCI\n", hc->cunit); 2044 } 2045 2046 static void 2047 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2) 2048 { 2049 printf("arc%d: ARINTR: TIMER\n", hc->cunit); 2050 } 2051 2052 2053 #ifdef NETGRAPH 2054 /***************************************** 2055 * Device timeout/watchdog routine. 2056 * called once per second. 2057 * checks to see that if activity was expected, that it hapenned. 2058 * At present we only look to see if expected output was completed. 2059 */ 2060 static void 2061 ngar_watchdog_frame(void * arg) 2062 { 2063 struct ar_softc * sc = arg; 2064 int s; 2065 int speed; 2066 2067 if(sc->running == 0) 2068 return; /* if we are not running let timeouts die */ 2069 /* 2070 * calculate the apparent throughputs 2071 * XXX a real hack 2072 */ 2073 s = splimp(); 2074 speed = sc->inbytes - sc->lastinbytes; 2075 sc->lastinbytes = sc->inbytes; 2076 if ( sc->inrate < speed ) 2077 sc->inrate = speed; 2078 speed = sc->outbytes - sc->lastoutbytes; 2079 sc->lastoutbytes = sc->outbytes; 2080 if ( sc->outrate < speed ) 2081 sc->outrate = speed; 2082 sc->inlast++; 2083 splx(s); 2084 2085 if ((sc->inlast > QUITE_A_WHILE) 2086 && (sc->out_deficit > LOTS_OF_PACKETS)) { 2087 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit); 2088 s = splimp(); 2089 ar_down(sc); 2090 ar_up(sc); 2091 sc->inlast = sc->out_deficit = 0; 2092 splx(s); 2093 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 2094 if (sc->out_dog == 0) { 2095 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n", 2096 sc->unit); 2097 s = splimp(); 2098 arwatchdog(sc); 2099 #if 0 2100 ar_down(sc); 2101 ar_up(sc); 2102 #endif 2103 splx(s); 2104 sc->inlast = sc->out_deficit = 0; 2105 } else { 2106 sc->out_dog--; 2107 } 2108 } 2109 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 2110 } 2111 2112 /*********************************************************************** 2113 * This section contains the methods for the Netgraph interface 2114 ***********************************************************************/ 2115 /* 2116 * It is not possible or allowable to create a node of this type. 2117 * If the hardware exists, it will already have created it. 2118 */ 2119 static int 2120 ngar_constructor(node_p node) 2121 { 2122 return (EINVAL); 2123 } 2124 2125 /* 2126 * give our ok for a hook to be added... 2127 * If we are not running this should kick the device into life. 2128 * The hook's private info points to our stash of info about that 2129 * channel. 2130 */ 2131 static int 2132 ngar_newhook(node_p node, hook_p hook, const char *name) 2133 { 2134 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2135 2136 /* 2137 * check if it's our friend the debug hook 2138 */ 2139 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) { 2140 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */ 2141 sc->debug_hook = hook; 2142 return (0); 2143 } 2144 2145 /* 2146 * Check for raw mode hook. 2147 */ 2148 if (strcmp(name, NG_AR_HOOK_RAW) != 0) { 2149 return (EINVAL); 2150 } 2151 NG_HOOK_SET_PRIVATE(hook, sc); 2152 sc->hook = hook; 2153 sc->datahooks++; 2154 ar_up(sc); 2155 return (0); 2156 } 2157 2158 /* 2159 * incoming messages. 2160 * Just respond to the generic TEXT_STATUS message 2161 */ 2162 static int 2163 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook) 2164 { 2165 struct ar_softc * sc; 2166 struct ng_mesg *resp = NULL; 2167 int error = 0; 2168 struct ng_mesg *msg; 2169 2170 NGI_GET_MSG(item, msg); 2171 sc = NG_NODE_PRIVATE(node); 2172 switch (msg->header.typecookie) { 2173 case NG_AR_COOKIE: 2174 error = EINVAL; 2175 break; 2176 case NGM_GENERIC_COOKIE: 2177 switch(msg->header.cmd) { 2178 case NGM_TEXT_STATUS: { 2179 char *arg; 2180 int pos = 0; 2181 2182 int resplen = sizeof(struct ng_mesg) + 512; 2183 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT); 2184 if (resp == NULL) { 2185 error = ENOMEM; 2186 break; 2187 } 2188 arg = (resp)->data; 2189 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 2190 "highest rate seen: %ld B/S in, %ld B/S out\n", 2191 sc->inbytes, sc->outbytes, 2192 sc->inrate, sc->outrate); 2193 pos += sprintf(arg + pos, 2194 "%ld output errors\n", 2195 sc->oerrors); 2196 pos += sprintf(arg + pos, 2197 "ierrors = %ld, %ld, %ld, %ld\n", 2198 sc->ierrors[0], 2199 sc->ierrors[1], 2200 sc->ierrors[2], 2201 sc->ierrors[3]); 2202 2203 resp->header.arglen = pos + 1; 2204 break; 2205 } 2206 default: 2207 error = EINVAL; 2208 break; 2209 } 2210 break; 2211 default: 2212 error = EINVAL; 2213 break; 2214 } 2215 /* Take care of synchronous response, if any */ 2216 NG_RESPOND_MSG(error, node, item, resp); 2217 NG_FREE_MSG(msg); 2218 return (error); 2219 } 2220 2221 /* 2222 * get data from another node and transmit it to the correct channel 2223 */ 2224 static int 2225 ngar_rcvdata(hook_p hook, item_p item) 2226 { 2227 int s; 2228 int error = 0; 2229 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2230 struct ifqueue *xmitq_p; 2231 struct mbuf *m; 2232 struct ng_tag_prio *ptag; 2233 2234 NGI_GET_M(item, m); 2235 NG_FREE_ITEM(item); 2236 /* 2237 * data doesn't come in from just anywhere (e.g control hook) 2238 */ 2239 if ( NG_HOOK_PRIVATE(hook) == NULL) { 2240 error = ENETDOWN; 2241 goto bad; 2242 } 2243 2244 /* 2245 * Now queue the data for when it can be sent 2246 */ 2247 if ((ptag = (struct ng_tag_prio *)m_tag_locate(m, NGM_GENERIC_COOKIE, 2248 NG_TAG_PRIO, NULL)) != NULL && (ptag->priority > NG_PRIO_CUTOFF) ) 2249 xmitq_p = (&sc->xmitq_hipri); 2250 else 2251 xmitq_p = (&sc->xmitq); 2252 2253 s = splimp(); 2254 IF_LOCK(xmitq_p); 2255 if (_IF_QFULL(xmitq_p)) { 2256 _IF_DROP(xmitq_p); 2257 IF_UNLOCK(xmitq_p); 2258 splx(s); 2259 error = ENOBUFS; 2260 goto bad; 2261 } 2262 _IF_ENQUEUE(xmitq_p, m); 2263 IF_UNLOCK(xmitq_p); 2264 arstart(sc); 2265 splx(s); 2266 return (0); 2267 2268 bad: 2269 /* 2270 * It was an error case. 2271 * check if we need to free the mbuf, and then return the error 2272 */ 2273 NG_FREE_M(m); 2274 return (error); 2275 } 2276 2277 /* 2278 * do local shutdown processing.. 2279 * this node will refuse to go away, unless the hardware says to.. 2280 * don't unref the node, or remove our name. just clear our links up. 2281 */ 2282 static int 2283 ngar_shutdown(node_p node) 2284 { 2285 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2286 2287 ar_down(sc); 2288 NG_NODE_UNREF(node); 2289 /* XXX need to drain the output queues! */ 2290 2291 /* The node is dead, long live the node! */ 2292 /* stolen from the attach routine */ 2293 if (ng_make_node_common(&typestruct, &sc->node) != 0) 2294 return (0); 2295 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 2296 if (ng_name_node(sc->node, sc->nodename)) { 2297 sc->node = NULL; 2298 printf("node naming failed\n"); 2299 NG_NODE_UNREF(sc->node); /* node dissappears */ 2300 return (0); 2301 } 2302 NG_NODE_SET_PRIVATE(sc->node, sc); 2303 sc->running = 0; 2304 return (0); 2305 } 2306 2307 /* already linked */ 2308 static int 2309 ngar_connect(hook_p hook) 2310 { 2311 /* probably not at splnet, force outward queueing */ 2312 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 2313 /* be really amiable and just say "YUP that's OK by me! " */ 2314 return (0); 2315 } 2316 2317 /* 2318 * notify on hook disconnection (destruction) 2319 * 2320 * Invalidate the private data associated with this dlci. 2321 * For this type, removal of the last link resets tries to destroy the node. 2322 * As the device still exists, the shutdown method will not actually 2323 * destroy the node, but reset the device and leave it 'fresh' :) 2324 * 2325 * The node removal code will remove all references except that owned by the 2326 * driver. 2327 */ 2328 static int 2329 ngar_disconnect(hook_p hook) 2330 { 2331 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2332 int s; 2333 /* 2334 * If it's the data hook, then free resources etc. 2335 */ 2336 if (NG_HOOK_PRIVATE(hook)) { 2337 s = splimp(); 2338 sc->datahooks--; 2339 if (sc->datahooks == 0) 2340 ar_down(sc); 2341 splx(s); 2342 } else { 2343 sc->debug_hook = NULL; 2344 } 2345 return (0); 2346 } 2347 2348 /* 2349 * called during bootup 2350 * or LKM loading to put this type into the list of known modules 2351 */ 2352 static void 2353 ngar_init(void *ignored) 2354 { 2355 if (ng_newtype(&typestruct)) 2356 printf("ngar install failed\n"); 2357 ngar_done_init = 1; 2358 } 2359 #endif /* NETGRAPH */ 2360 2361 /* 2362 ********************************* END ************************************ 2363 */
Cache object: 48d18b9510762adbf0c24a832a2f6e92
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]