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sys/dev/ar/if_ar.c
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1 /*- 2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/6.2/sys/dev/ar/if_ar.c 149443 2005-08-25 05:01:24Z rwatson $"); 31 32 /* 33 * Programming assumptions and other issues. 34 * 35 * The descriptors of a DMA channel will fit in a 16K memory window. 36 * 37 * The buffers of a transmit DMA channel will fit in a 16K memory window. 38 * 39 * Only the ISA bus cards with X.21 and V.35 is tested. 40 * 41 * When interface is going up, handshaking is set and it is only cleared 42 * when the interface is down'ed. 43 * 44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 45 * internal/external clock, etc..... 46 */ 47 48 #include "opt_netgraph.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/mbuf.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/module.h> 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/rman.h> 62 63 #include <net/if.h> 64 #ifdef NETGRAPH 65 #include <netgraph/ng_message.h> 66 #include <netgraph/netgraph.h> 67 #include <sys/syslog.h> 68 #include <dev/ar/if_ar.h> 69 #else /* NETGRAPH */ 70 #include <net/if_sppp.h> 71 #include <net/if_types.h> 72 #include <net/bpf.h> 73 #endif /* NETGRAPH */ 74 75 #include <machine/md_var.h> 76 77 #include <dev/ic/hd64570.h> 78 #include <dev/ar/if_arregs.h> 79 80 #ifdef TRACE 81 #define TRC(x) x 82 #else 83 #define TRC(x) 84 #endif 85 86 #define TRCL(x) x 87 88 #define PPP_HEADER_LEN 4 89 90 devclass_t ar_devclass; 91 92 struct ar_softc { 93 #ifndef NETGRAPH 94 struct ifnet *ifp; 95 #endif /* NETGRAPH */ 96 int unit; /* With regards to all ar devices */ 97 int subunit; /* With regards to this card */ 98 struct ar_hardc *hc; 99 100 struct buf_block { 101 u_int txdesc; /* On card address */ 102 u_int txstart; /* On card address */ 103 u_int txend; /* On card address */ 104 u_int txtail; /* Index of first unused buffer */ 105 u_int txmax; /* number of usable buffers/descriptors */ 106 u_int txeda; /* Error descriptor addresses */ 107 }block[AR_TX_BLOCKS]; 108 109 char xmit_busy; /* Transmitter is busy */ 110 char txb_inuse; /* Number of tx blocks currently in use */ 111 u_char txb_new; /* Index to where new buffer will be added */ 112 u_char txb_next_tx; /* Index to next block ready to tx */ 113 114 u_int rxdesc; /* On card address */ 115 u_int rxstart; /* On card address */ 116 u_int rxend; /* On card address */ 117 u_int rxhind; /* Index to the head of the rx buffers. */ 118 u_int rxmax; /* number of usable buffers/descriptors */ 119 120 int scano; 121 int scachan; 122 sca_regs *sca; 123 #ifdef NETGRAPH 124 int running; /* something is attached so we are running */ 125 int dcd; /* do we have dcd? */ 126 /* ---netgraph bits --- */ 127 char nodename[NG_NODESIZ]; /* store our node name */ 128 int datahooks; /* number of data hooks attached */ 129 node_p node; /* netgraph node */ 130 hook_p hook; /* data hook */ 131 hook_p debug_hook; 132 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 133 struct ifqueue xmitq; /* transmit queue */ 134 int flags; /* state */ 135 #define SCF_RUNNING 0x01 /* board is active */ 136 #define SCF_OACTIVE 0x02 /* output is active */ 137 int out_dog; /* watchdog cycles output count-down */ 138 struct callout_handle handle; /* timeout(9) handle */ 139 u_long inbytes, outbytes; /* stats */ 140 u_long lastinbytes, lastoutbytes; /* a second ago */ 141 u_long inrate, outrate; /* highest rate seen */ 142 u_long inlast; /* last input N secs ago */ 143 u_long out_deficit; /* output since last input */ 144 u_long oerrors, ierrors[6]; 145 u_long opackets, ipackets; 146 #endif /* NETGRAPH */ 147 }; 148 #define SC2IFP(sc) (sc)->ifp 149 150 static int next_ar_unit = 0; 151 152 #ifdef NETGRAPH 153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 154 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 155 #define LOTS_OF_PACKETS 100 156 #endif /* NETGRAPH */ 157 158 /* 159 * This translate from irq numbers to 160 * the value that the arnet card needs 161 * in the lower part of the AR_INT_SEL 162 * register. 163 */ 164 static int irqtable[16] = { 165 0, /* 0 */ 166 0, /* 1 */ 167 0, /* 2 */ 168 1, /* 3 */ 169 0, /* 4 */ 170 2, /* 5 */ 171 0, /* 6 */ 172 3, /* 7 */ 173 0, /* 8 */ 174 0, /* 9 */ 175 4, /* 10 */ 176 5, /* 11 */ 177 6, /* 12 */ 178 0, /* 13 */ 179 0, /* 14 */ 180 7 /* 15 */ 181 }; 182 183 #ifndef NETGRAPH 184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1); 185 #endif 186 187 static void arintr(void *arg); 188 static void ar_xmit(struct ar_softc *sc); 189 #ifndef NETGRAPH 190 static void arstart(struct ifnet *ifp); 191 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 192 static void arwatchdog(struct ifnet *ifp); 193 #else /* NETGRAPH */ 194 static void arstart(struct ar_softc *sc); 195 static void arwatchdog(struct ar_softc *sc); 196 #endif /* NETGRAPH */ 197 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat); 198 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len); 199 static void ar_eat_packet(struct ar_softc *sc, int single); 200 static void ar_get_packets(struct ar_softc *sc); 201 202 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel); 203 static void ar_up(struct ar_softc *sc); 204 static void ar_down(struct ar_softc *sc); 205 static void arc_init(struct ar_hardc *hc); 206 static void ar_init_sca(struct ar_hardc *hc, int scano); 207 static void ar_init_msci(struct ar_softc *sc); 208 static void ar_init_rx_dmac(struct ar_softc *sc); 209 static void ar_init_tx_dmac(struct ar_softc *sc); 210 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr); 211 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr); 212 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr); 213 214 #ifdef NETGRAPH 215 static void ngar_watchdog_frame(void * arg); 216 217 static ng_constructor_t ngar_constructor; 218 static ng_rcvmsg_t ngar_rcvmsg; 219 static ng_shutdown_t ngar_shutdown; 220 static ng_newhook_t ngar_newhook; 221 /*static ng_findhook_t ngar_findhook; */ 222 static ng_connect_t ngar_connect; 223 static ng_rcvdata_t ngar_rcvdata; 224 static ng_disconnect_t ngar_disconnect; 225 226 static struct ng_type typestruct = { 227 .version = NG_ABI_VERSION, 228 .name = NG_AR_NODE_TYPE, 229 .constructor = ngar_constructor, 230 .rcvmsg = ngar_rcvmsg, 231 .shutdown = ngar_shutdown, 232 .newhook = ngar_newhook, 233 .connect = ngar_connect, 234 .rcvdata = ngar_rcvdata, 235 .disconnect = ngar_disconnect, 236 }; 237 NETGRAPH_INIT_ORDERED(sync_ar, &typestruct, SI_SUB_DRIVERS, SI_ORDER_FIRST); 238 #endif /* NETGRAPH */ 239 240 int 241 ar_attach(device_t device) 242 { 243 struct ar_hardc *hc; 244 struct ar_softc *sc; 245 #ifndef NETGRAPH 246 struct ifnet *ifp; 247 char *iface; 248 #endif /* NETGRAPH */ 249 int unit; 250 251 hc = (struct ar_hardc *)device_get_softc(device); 252 253 printf("arc%d: %uK RAM, %u ports, rev %u.\n", 254 hc->cunit, 255 hc->memsize/1024, 256 hc->numports, 257 hc->revision); 258 259 arc_init(hc); 260 261 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq, 262 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0) 263 return (1); 264 265 sc = hc->sc; 266 267 for(unit=0;unit<hc->numports;unit+=NCHAN) 268 ar_init_sca(hc, unit / NCHAN); 269 270 /* 271 * Now configure each port on the card. 272 */ 273 for(unit=0;unit<hc->numports;sc++,unit++) { 274 sc->hc = hc; 275 sc->subunit = unit; 276 sc->unit = next_ar_unit; 277 next_ar_unit++; 278 sc->scano = unit / NCHAN; 279 sc->scachan = unit%NCHAN; 280 281 ar_init_rx_dmac(sc); 282 ar_init_tx_dmac(sc); 283 ar_init_msci(sc); 284 285 #ifndef NETGRAPH 286 ifp = SC2IFP(sc) = if_alloc(IFT_PPP); 287 if (ifp == NULL) { 288 if (BUS_TEARDOWN_INTR(device_get_parent(device), device, 289 hc->res_irq, hc->intr_cookie) != 0) { 290 printf("intr teardown failed.. continuing\n"); 291 } 292 return (1); 293 } 294 295 ifp->if_softc = sc; 296 if_initname(ifp, device_get_name(device), 297 device_get_unit(device)); 298 ifp->if_mtu = PP_MTU; 299 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST | 300 IFF_NEEDSGIANT; 301 ifp->if_ioctl = arioctl; 302 ifp->if_start = arstart; 303 ifp->if_watchdog = arwatchdog; 304 305 IFP2SP(sc->ifp)->pp_flags = PP_KEEPALIVE; 306 307 switch(hc->interface[unit]) { 308 default: iface = "UNKNOWN"; break; 309 case AR_IFACE_EIA_232: iface = "EIA-232"; break; 310 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break; 311 case AR_IFACE_EIA_530: iface = "EIA-530"; break; 312 case AR_IFACE_X_21: iface = "X.21"; break; 313 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break; 314 } 315 316 printf("ar%d: Adapter %d, port %d, interface %s.\n", 317 sc->unit, 318 hc->cunit, 319 sc->subunit, 320 iface); 321 322 sppp_attach(SC2IFP(sc)); 323 if_attach(ifp); 324 325 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 326 #else /* NETGRAPH */ 327 if (ng_make_node_common(&typestruct, &sc->node) != 0) 328 return (1); 329 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 330 if (ng_name_node(sc->node, sc->nodename)) { 331 NG_NODE_UNREF(sc->node); /* drop it again */ 332 return (1); 333 } 334 NG_NODE_SET_PRIVATE(sc->node, sc); 335 callout_handle_init(&sc->handle); 336 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 337 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 338 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF); 339 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL, 340 MTX_DEF); 341 sc->running = 0; 342 #endif /* NETGRAPH */ 343 } 344 345 if(hc->bustype == AR_BUS_ISA) 346 ARC_SET_OFF(hc); 347 348 return (0); 349 } 350 351 int 352 ar_detach(device_t device) 353 { 354 device_t parent = device_get_parent(device); 355 struct ar_hardc *hc = device_get_softc(device); 356 357 if (hc->intr_cookie != NULL) { 358 if (BUS_TEARDOWN_INTR(parent, device, 359 hc->res_irq, hc->intr_cookie) != 0) { 360 printf("intr teardown failed.. continuing\n"); 361 } 362 hc->intr_cookie = NULL; 363 } 364 365 /* 366 * deallocate any system resources we may have 367 * allocated on behalf of this driver. 368 */ 369 FREE(hc->sc, M_DEVBUF); 370 hc->sc = NULL; 371 hc->mem_start = NULL; 372 return (ar_deallocate_resources(device)); 373 } 374 375 int 376 ar_allocate_ioport(device_t device, int rid, u_long size) 377 { 378 struct ar_hardc *hc = device_get_softc(device); 379 380 hc->rid_ioport = rid; 381 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT, 382 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE); 383 if (hc->res_ioport == NULL) { 384 goto errexit; 385 } 386 hc->bt = rman_get_bustag(hc->res_ioport); 387 hc->bh = rman_get_bushandle(hc->res_ioport); 388 389 return (0); 390 391 errexit: 392 ar_deallocate_resources(device); 393 return (ENXIO); 394 } 395 396 int 397 ar_allocate_irq(device_t device, int rid, u_long size) 398 { 399 struct ar_hardc *hc = device_get_softc(device); 400 401 hc->rid_irq = rid; 402 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ, 403 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE); 404 if (hc->res_irq == NULL) { 405 goto errexit; 406 } 407 return (0); 408 409 errexit: 410 ar_deallocate_resources(device); 411 return (ENXIO); 412 } 413 414 int 415 ar_allocate_memory(device_t device, int rid, u_long size) 416 { 417 struct ar_hardc *hc = device_get_softc(device); 418 419 hc->rid_memory = rid; 420 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 421 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE); 422 if (hc->res_memory == NULL) { 423 goto errexit; 424 } 425 return (0); 426 427 errexit: 428 ar_deallocate_resources(device); 429 return (ENXIO); 430 } 431 432 int 433 ar_allocate_plx_memory(device_t device, int rid, u_long size) 434 { 435 struct ar_hardc *hc = device_get_softc(device); 436 437 hc->rid_plx_memory = rid; 438 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY, 439 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE); 440 if (hc->res_plx_memory == NULL) { 441 goto errexit; 442 } 443 return (0); 444 445 errexit: 446 ar_deallocate_resources(device); 447 return (ENXIO); 448 } 449 450 int 451 ar_deallocate_resources(device_t device) 452 { 453 struct ar_hardc *hc = device_get_softc(device); 454 455 if (hc->res_irq != 0) { 456 bus_deactivate_resource(device, SYS_RES_IRQ, 457 hc->rid_irq, hc->res_irq); 458 bus_release_resource(device, SYS_RES_IRQ, 459 hc->rid_irq, hc->res_irq); 460 hc->res_irq = 0; 461 } 462 if (hc->res_ioport != 0) { 463 bus_deactivate_resource(device, SYS_RES_IOPORT, 464 hc->rid_ioport, hc->res_ioport); 465 bus_release_resource(device, SYS_RES_IOPORT, 466 hc->rid_ioport, hc->res_ioport); 467 hc->res_ioport = 0; 468 } 469 if (hc->res_memory != 0) { 470 bus_deactivate_resource(device, SYS_RES_MEMORY, 471 hc->rid_memory, hc->res_memory); 472 bus_release_resource(device, SYS_RES_MEMORY, 473 hc->rid_memory, hc->res_memory); 474 hc->res_memory = 0; 475 } 476 if (hc->res_plx_memory != 0) { 477 bus_deactivate_resource(device, SYS_RES_MEMORY, 478 hc->rid_plx_memory, hc->res_plx_memory); 479 bus_release_resource(device, SYS_RES_MEMORY, 480 hc->rid_plx_memory, hc->res_plx_memory); 481 hc->res_plx_memory = 0; 482 } 483 return (0); 484 } 485 486 /* 487 * First figure out which SCA gave the interrupt. 488 * Process it. 489 * See if there is other interrupts pending. 490 * Repeat until there is no more interrupts. 491 */ 492 static void 493 arintr(void *arg) 494 { 495 struct ar_hardc *hc = (struct ar_hardc *)arg; 496 sca_regs *sca; 497 u_char isr0, isr1, isr2, arisr; 498 int scano; 499 500 /* XXX Use the PCI interrupt score board register later */ 501 if(hc->bustype == AR_BUS_PCI) 502 arisr = hc->orbase[AR_ISTAT * 4]; 503 else 504 arisr = ar_inb(hc, AR_ISTAT); 505 506 while(arisr & AR_BD_INT) { 507 TRC(printf("arisr = %x\n", arisr)); 508 if(arisr & AR_INT_0) 509 scano = 0; 510 else if(arisr & AR_INT_1) 511 scano = 1; 512 else { 513 /* XXX Oops this shouldn't happen. */ 514 printf("arc%d: Interrupted with no interrupt.\n", 515 hc->cunit); 516 return; 517 } 518 sca = hc->sca[scano]; 519 520 if(hc->bustype == AR_BUS_ISA) 521 ARC_SET_SCA(hc, scano); 522 523 isr0 = sca->isr0; 524 isr1 = sca->isr1; 525 isr2 = sca->isr2; 526 527 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n", 528 hc->cunit, 529 isr0, 530 isr1, 531 isr2)); 532 if(isr0) 533 ar_msci_intr(hc, scano, isr0); 534 535 if(isr1) 536 ar_dmac_intr(hc, scano, isr1); 537 538 if(isr2) 539 ar_timer_intr(hc, scano, isr2); 540 541 /* 542 * Proccess the second sca's interrupt if available. 543 * Else see if there are any new interrupts. 544 */ 545 if((arisr & AR_INT_0) && (arisr & AR_INT_1)) 546 arisr &= ~AR_INT_0; 547 else { 548 if(hc->bustype == AR_BUS_PCI) 549 arisr = hc->orbase[AR_ISTAT * 4]; 550 else 551 arisr = ar_inb(hc, AR_ISTAT); 552 } 553 } 554 555 if(hc->bustype == AR_BUS_ISA) 556 ARC_SET_OFF(hc); 557 } 558 559 560 /* 561 * This will only start the transmitter. It is assumed that the data 562 * is already there. It is normally called from arstart() or ar_dmac_intr(). 563 * 564 */ 565 static void 566 ar_xmit(struct ar_softc *sc) 567 { 568 #ifndef NETGRAPH 569 struct ifnet *ifp; 570 #endif /* NETGRAPH */ 571 dmac_channel *dmac; 572 573 #ifndef NETGRAPH 574 ifp = SC2IFP(sc); 575 #endif /* NETGRAPH */ 576 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 577 578 if(sc->hc->bustype == AR_BUS_ISA) 579 ARC_SET_SCA(sc->hc, sc->scano); 580 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff); 581 582 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff); 583 dmac->dsr = SCA_DSR_DE; 584 585 sc->xmit_busy = 1; 586 587 sc->txb_next_tx++; 588 if(sc->txb_next_tx == AR_TX_BLOCKS) 589 sc->txb_next_tx = 0; 590 591 #ifndef NETGRAPH 592 ifp->if_timer = 2; /* Value in seconds. */ 593 #else /* NETGRAPH */ 594 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 595 #endif /* NETGRAPH */ 596 if(sc->hc->bustype == AR_BUS_ISA) 597 ARC_SET_OFF(sc->hc); 598 } 599 600 /* 601 * This function will be called from the upper level when a user add a 602 * packet to be send, and from the interrupt handler after a finished 603 * transmit. 604 * 605 * NOTE: it should run at spl_imp(). 606 * 607 * This function only place the data in the oncard buffers. It does not 608 * start the transmition. ar_xmit() does that. 609 * 610 * Transmitter idle state is indicated by the IFF_DRV_OACTIVE flag. The 611 * function that clears that should ensure that the transmitter and its 612 * DMA is in a "good" idle state. 613 */ 614 #ifndef NETGRAPH 615 static void 616 arstart(struct ifnet *ifp) 617 { 618 struct ar_softc *sc = ifp->if_softc; 619 #else /* NETGRAPH */ 620 static void 621 arstart(struct ar_softc *sc) 622 { 623 #endif /* NETGRAPH */ 624 int i, len, tlen; 625 struct mbuf *mtx; 626 u_char *txdata; 627 sca_descriptor *txdesc; 628 struct buf_block *blkp; 629 630 #ifndef NETGRAPH 631 if(!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 632 return; 633 #else /* NETGRAPH */ 634 /* XXX */ 635 #endif /* NETGRAPH */ 636 637 top_arstart: 638 639 /* 640 * See if we have space for more packets. 641 */ 642 if(sc->txb_inuse == AR_TX_BLOCKS) { 643 #ifndef NETGRAPH 644 ifp->if_drv_flags |= IFF_DRV_OACTIVE; /* yes, mark active */ 645 #else /* NETGRAPH */ 646 /*XXX*/ /*ifp->if_drv_flags |= IFF_DRV_OACTIVE;*/ /* yes, mark active */ 647 #endif /* NETGRAPH */ 648 return; 649 } 650 651 #ifndef NETGRAPH 652 mtx = sppp_dequeue(ifp); 653 #else /* NETGRAPH */ 654 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 655 if (mtx == NULL) { 656 IF_DEQUEUE(&sc->xmitq, mtx); 657 } 658 #endif /* NETGRAPH */ 659 if(!mtx) 660 return; 661 662 /* 663 * It is OK to set the memory window outside the loop because 664 * all tx buffers and descriptors are assumed to be in the same 665 * 16K window. 666 */ 667 if(sc->hc->bustype == AR_BUS_ISA) 668 ARC_SET_MEM(sc->hc, sc->block[0].txdesc); 669 670 /* 671 * We stay in this loop until there is nothing in the 672 * TX queue left or the tx buffer is full. 673 */ 674 i = 0; 675 blkp = &sc->block[sc->txb_new]; 676 txdesc = (sca_descriptor *) 677 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk)); 678 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk)); 679 for(;;) { 680 len = mtx->m_pkthdr.len; 681 682 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len)); 683 684 /* 685 * We can do this because the tx buffers don't wrap. 686 */ 687 m_copydata(mtx, 0, len, txdata); 688 tlen = len; 689 while(tlen > AR_BUF_SIZ) { 690 txdesc->stat = 0; 691 txdesc->len = AR_BUF_SIZ; 692 tlen -= AR_BUF_SIZ; 693 txdesc++; 694 txdata += AR_BUF_SIZ; 695 i++; 696 } 697 /* XXX Move into the loop? */ 698 txdesc->stat = SCA_DESC_EOM; 699 txdesc->len = tlen; 700 txdesc++; 701 txdata += AR_BUF_SIZ; 702 i++; 703 704 #ifndef NETGRAPH 705 BPF_MTAP(ifp, mtx); 706 m_freem(mtx); 707 ++SC2IFP(sc)->if_opackets; 708 #else /* NETGRAPH */ 709 m_freem(mtx); 710 sc->outbytes += len; 711 ++sc->opackets; 712 #endif /* NETGRAPH */ 713 714 /* 715 * Check if we have space for another mbuf. 716 * XXX This is hardcoded. A packet won't be larger 717 * than 3 buffers (3 x 512). 718 */ 719 if((i + 3) >= blkp->txmax) 720 break; 721 722 #ifndef NETGRAPH 723 mtx = sppp_dequeue(ifp); 724 #else /* NETGRAPH */ 725 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 726 if (mtx == NULL) { 727 IF_DEQUEUE(&sc->xmitq, mtx); 728 } 729 #endif /* NETGRAPH */ 730 if(!mtx) 731 break; 732 } 733 734 blkp->txtail = i; 735 736 /* 737 * Mark the last descriptor, so that the SCA know where 738 * to stop. 739 */ 740 txdesc--; 741 txdesc->stat |= SCA_DESC_EOT; 742 743 txdesc = (sca_descriptor *)blkp->txdesc; 744 blkp->txeda = (u_short)((u_int)&txdesc[i]); 745 746 #if 0 747 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp); 748 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp); 749 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb); 750 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len); 751 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat); 752 #endif 753 754 sc->txb_inuse++; 755 sc->txb_new++; 756 if(sc->txb_new == AR_TX_BLOCKS) 757 sc->txb_new = 0; 758 759 if(sc->xmit_busy == 0) 760 ar_xmit(sc); 761 762 if(sc->hc->bustype == AR_BUS_ISA) 763 ARC_SET_OFF(sc->hc); 764 765 goto top_arstart; 766 } 767 768 #ifndef NETGRAPH 769 static int 770 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 771 { 772 int s, error; 773 int was_up, should_be_up; 774 struct ar_softc *sc = ifp->if_softc; 775 776 TRC(if_printf(ifp, "arioctl.\n");) 777 778 was_up = ifp->if_drv_flags & IFF_DRV_RUNNING; 779 780 error = sppp_ioctl(ifp, cmd, data); 781 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n", 782 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);) 783 if(error) 784 return (error); 785 786 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR)) 787 return (0); 788 789 TRC(if_printf(ifp, "arioctl %s.\n", 790 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");) 791 792 s = splimp(); 793 should_be_up = ifp->if_drv_flags & IFF_DRV_RUNNING; 794 795 if(!was_up && should_be_up) { 796 /* Interface should be up -- start it. */ 797 ar_up(sc); 798 arstart(ifp); 799 /* XXX Maybe clear the IFF_UP flag so that the link 800 * will only go up after sppp lcp and ipcp negotiation. 801 */ 802 } else if(was_up && !should_be_up) { 803 /* Interface should be down -- stop it. */ 804 ar_down(sc); 805 sppp_flush(ifp); 806 } 807 splx(s); 808 return (0); 809 } 810 #endif /* NETGRAPH */ 811 812 /* 813 * This is to catch lost tx interrupts. 814 */ 815 static void 816 #ifndef NETGRAPH 817 arwatchdog(struct ifnet *ifp) 818 { 819 struct ar_softc *sc = ifp->if_softc; 820 #else /* NETGRAPH */ 821 arwatchdog(struct ar_softc *sc) 822 { 823 #endif /* NETGRAPH */ 824 msci_channel *msci = &sc->sca->msci[sc->scachan]; 825 826 #ifndef NETGRAPH 827 if(!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 828 return; 829 #endif /* NETGRAPH */ 830 831 if(sc->hc->bustype == AR_BUS_ISA) 832 ARC_SET_SCA(sc->hc, sc->scano); 833 834 /* XXX if(SC2IFP(sc)->if_flags & IFF_DEBUG) */ 835 printf("ar%d: transmit failed, " 836 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n", 837 sc->unit, 838 msci->st0, 839 msci->st1, 840 msci->st3, 841 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr); 842 843 if(msci->st1 & SCA_ST1_UDRN) { 844 msci->cmd = SCA_CMD_TXABORT; 845 msci->cmd = SCA_CMD_TXENABLE; 846 msci->st1 = SCA_ST1_UDRN; 847 } 848 849 sc->xmit_busy = 0; 850 #ifndef NETGRAPH 851 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 852 #else /* NETGRAPH */ 853 /* XXX ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; */ 854 #endif /* NETGRAPH */ 855 856 if(sc->txb_inuse && --sc->txb_inuse) 857 ar_xmit(sc); 858 859 #ifndef NETGRAPH 860 arstart(ifp); 861 #else /* NETGRAPH */ 862 arstart(sc); 863 #endif /* NETGRAPH */ 864 } 865 866 static void 867 ar_up(struct ar_softc *sc) 868 { 869 sca_regs *sca; 870 msci_channel *msci; 871 872 sca = sc->sca; 873 msci = &sca->msci[sc->scachan]; 874 875 TRC(printf("ar%d: sca %p, msci %p, ch %d\n", 876 sc->unit, sca, msci, sc->scachan)); 877 878 /* 879 * Enable transmitter and receiver. 880 * Raise DTR and RTS. 881 * Enable interrupts. 882 */ 883 if(sc->hc->bustype == AR_BUS_ISA) 884 ARC_SET_SCA(sc->hc, sc->scano); 885 886 /* XXX 887 * What about using AUTO mode in msci->md0 ??? 888 * And what about CTS/DCD etc... ? 889 */ 890 if(sc->hc->handshake & AR_SHSK_RTS) 891 msci->ctl &= ~SCA_CTL_RTS; 892 if(sc->hc->handshake & AR_SHSK_DTR) { 893 sc->hc->txc_dtr[sc->scano] &= sc->scachan ? 894 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0; 895 if(sc->hc->bustype == AR_BUS_PCI) 896 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 897 sc->hc->txc_dtr[sc->scano]; 898 else 899 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], 900 sc->hc->txc_dtr[sc->scano]); 901 } 902 903 if(sc->scachan == 0) { 904 sca->ier0 |= 0x0F; 905 sca->ier1 |= 0x0F; 906 } else { 907 sca->ier0 |= 0xF0; 908 sca->ier1 |= 0xF0; 909 } 910 911 msci->cmd = SCA_CMD_RXENABLE; 912 if(sc->hc->bustype == AR_BUS_ISA) 913 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ 914 msci->cmd = SCA_CMD_TXENABLE; 915 916 if(sc->hc->bustype == AR_BUS_ISA) 917 ARC_SET_OFF(sc->hc); 918 #ifdef NETGRAPH 919 untimeout(ngar_watchdog_frame, sc, sc->handle); 920 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 921 sc->running = 1; 922 #endif /* NETGRAPH */ 923 } 924 925 static void 926 ar_down(struct ar_softc *sc) 927 { 928 sca_regs *sca; 929 msci_channel *msci; 930 931 sca = sc->sca; 932 msci = &sca->msci[sc->scachan]; 933 934 #ifdef NETGRAPH 935 untimeout(ngar_watchdog_frame, sc, sc->handle); 936 sc->running = 0; 937 #endif /* NETGRAPH */ 938 /* 939 * Disable transmitter and receiver. 940 * Lower DTR and RTS. 941 * Disable interrupts. 942 */ 943 if(sc->hc->bustype == AR_BUS_ISA) 944 ARC_SET_SCA(sc->hc, sc->scano); 945 msci->cmd = SCA_CMD_RXDISABLE; 946 if(sc->hc->bustype == AR_BUS_ISA) 947 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */ 948 msci->cmd = SCA_CMD_TXDISABLE; 949 950 if(sc->hc->handshake & AR_SHSK_RTS) 951 msci->ctl |= SCA_CTL_RTS; 952 if(sc->hc->handshake & AR_SHSK_DTR) { 953 sc->hc->txc_dtr[sc->scano] |= sc->scachan ? 954 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0; 955 if(sc->hc->bustype == AR_BUS_PCI) 956 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] = 957 sc->hc->txc_dtr[sc->scano]; 958 else 959 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano], 960 sc->hc->txc_dtr[sc->scano]); 961 } 962 963 if(sc->scachan == 0) { 964 sca->ier0 &= ~0x0F; 965 sca->ier1 &= ~0x0F; 966 } else { 967 sca->ier0 &= ~0xF0; 968 sca->ier1 &= ~0xF0; 969 } 970 971 if(sc->hc->bustype == AR_BUS_ISA) 972 ARC_SET_OFF(sc->hc); 973 } 974 975 static int 976 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel) 977 { 978 int ctype, i, val, x; 979 volatile u_char *pimctrl; 980 981 ctype = 0; 982 val = 0; 983 984 pimctrl = hc->orbase + AR_PIMCTRL; 985 986 /* Reset the PIM */ 987 *pimctrl = 0x00; 988 *pimctrl = AR_PIM_STROBE; 989 990 /* Check if there is a PIM */ 991 *pimctrl = 0x00; 992 *pimctrl = AR_PIM_READ; 993 x = *pimctrl; 994 TRC(printf("x = %x", x)); 995 if(x & AR_PIM_DATA) { 996 printf("No PIM installed\n"); 997 return (AR_IFACE_UNKNOWN); 998 } 999 1000 x = (x >> 1) & 0x01; 1001 val |= x << 0; 1002 1003 /* Now read the next 15 bits */ 1004 for(i = 1; i < 16; i++) { 1005 *pimctrl = AR_PIM_READ; 1006 *pimctrl = AR_PIM_READ | AR_PIM_STROBE; 1007 x = *pimctrl; 1008 TRC(printf(" %x ", x)); 1009 x = (x >> 1) & 0x01; 1010 val |= x << i; 1011 if(i == 8 && (val & 0x000f) == 0x0004) { 1012 int ii; 1013 1014 /* Start bit */ 1015 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1016 *pimctrl = AR_PIM_A2D_DOUT; 1017 1018 /* Mode bit */ 1019 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1020 *pimctrl = AR_PIM_A2D_DOUT; 1021 1022 /* Sign bit */ 1023 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE; 1024 *pimctrl = AR_PIM_A2D_DOUT; 1025 1026 /* Select channel */ 1027 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2); 1028 *pimctrl = ((channel & 2) << 2); 1029 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3); 1030 *pimctrl = ((channel & 1) << 3); 1031 1032 *pimctrl = AR_PIM_A2D_STROBE; 1033 1034 x = *pimctrl; 1035 if(x & AR_PIM_DATA) 1036 printf("\nOops A2D start bit not zero (%X)\n", x); 1037 1038 for(ii = 7; ii >= 0; ii--) { 1039 *pimctrl = 0x00; 1040 *pimctrl = AR_PIM_A2D_STROBE; 1041 x = *pimctrl; 1042 if(x & AR_PIM_DATA) 1043 ctype |= 1 << ii; 1044 } 1045 } 1046 } 1047 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype)); 1048 *pimctrl = AR_PIM_MODEG; 1049 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1050 if(ctype > 255) 1051 return (AR_IFACE_UNKNOWN); 1052 if(ctype > 239) 1053 return (AR_IFACE_V_35); 1054 if(ctype > 207) 1055 return (AR_IFACE_EIA_232); 1056 if(ctype > 178) 1057 return (AR_IFACE_X_21); 1058 if(ctype > 150) 1059 return (AR_IFACE_EIA_530); 1060 if(ctype > 25) 1061 return (AR_IFACE_UNKNOWN); 1062 if(ctype > 7) 1063 return (AR_IFACE_LOOPBACK); 1064 return (AR_IFACE_UNKNOWN); 1065 } 1066 1067 /* 1068 * Initialize the card, allocate memory for the ar_softc structures 1069 * and fill in the pointers. 1070 */ 1071 static void 1072 arc_init(struct ar_hardc *hc) 1073 { 1074 struct ar_softc *sc; 1075 int x; 1076 u_int chanmem; 1077 u_int bufmem; 1078 u_int next; 1079 u_int descneeded; 1080 u_char isr, mar; 1081 u_long memst; 1082 1083 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc), 1084 M_DEVBUF, M_WAITOK | M_ZERO); 1085 if (sc == NULL) 1086 return; 1087 hc->sc = sc; 1088 1089 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET | 1090 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1091 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1; 1092 hc->txc_dtr_off[0] = AR_TXC_DTR0; 1093 hc->txc_dtr_off[1] = AR_TXC_DTR2; 1094 if(hc->bustype == AR_BUS_PCI) { 1095 hc->txc_dtr_off[0] *= 4; 1096 hc->txc_dtr_off[1] *= 4; 1097 } 1098 1099 /* 1100 * reset the card and wait at least 1uS. 1101 */ 1102 if(hc->bustype == AR_BUS_PCI) 1103 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET & 1104 hc->txc_dtr[0]; 1105 else 1106 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & 1107 hc->txc_dtr[0]); 1108 DELAY(2); 1109 if(hc->bustype == AR_BUS_PCI) 1110 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1111 else 1112 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); 1113 1114 if(hc->bustype == AR_BUS_ISA) { 1115 /* 1116 * Configure the card. 1117 * Mem address, irq, 1118 */ 1119 memst = rman_get_start(hc->res_memory); 1120 mar = memst >> 16; 1121 isr = irqtable[hc->isa_irq] << 1; 1122 if(isr == 0) 1123 printf("ar%d: Warning illegal interrupt %d\n", 1124 hc->cunit, hc->isa_irq); 1125 isr = isr | ((memst & 0xc000) >> 10); 1126 1127 hc->sca[0] = (sca_regs *)hc->mem_start; 1128 hc->sca[1] = (sca_regs *)hc->mem_start; 1129 1130 ar_outb(hc, AR_MEM_SEL, mar); 1131 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN); 1132 } 1133 1134 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM) 1135 for(x = 0; x < hc->numports; x++) 1136 hc->interface[x] = ar_read_pim_iface(hc, x); 1137 1138 /* 1139 * Set the TX clock direction and enable TX. 1140 */ 1141 for(x=0;x<hc->numports;x++) { 1142 switch(hc->interface[x]) { 1143 case AR_IFACE_V_35: 1144 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1145 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1146 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1147 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1; 1148 break; 1149 case AR_IFACE_EIA_530: 1150 case AR_IFACE_COMBO: 1151 case AR_IFACE_X_21: 1152 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ? 1153 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1; 1154 break; 1155 } 1156 } 1157 1158 if(hc->bustype == AR_BUS_PCI) 1159 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0]; 1160 else 1161 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]); 1162 if(hc->numports > NCHAN) { 1163 if(hc->bustype == AR_BUS_PCI) 1164 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1]; 1165 else 1166 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]); 1167 } 1168 1169 chanmem = hc->memsize / hc->numports; 1170 next = 0; 1171 1172 for(x=0;x<hc->numports;x++, sc++) { 1173 int blk; 1174 1175 sc->sca = hc->sca[x / NCHAN]; 1176 1177 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1178 sc->block[blk].txdesc = next; 1179 bufmem = (16 * 1024) / AR_TX_BLOCKS; 1180 descneeded = bufmem / AR_BUF_SIZ; 1181 sc->block[blk].txstart = sc->block[blk].txdesc + 1182 ((((descneeded * sizeof(sca_descriptor)) / 1183 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1184 sc->block[blk].txend = next + bufmem; 1185 sc->block[blk].txmax = 1186 (sc->block[blk].txend - sc->block[blk].txstart) 1187 / AR_BUF_SIZ; 1188 next += bufmem; 1189 1190 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, " 1191 "txend %x, txmax %d\n", 1192 x, 1193 blk, 1194 sc->block[blk].txdesc, 1195 sc->block[blk].txstart, 1196 sc->block[blk].txend, 1197 sc->block[blk].txmax)); 1198 } 1199 1200 sc->rxdesc = next; 1201 bufmem = chanmem - (bufmem * AR_TX_BLOCKS); 1202 descneeded = bufmem / AR_BUF_SIZ; 1203 sc->rxstart = sc->rxdesc + 1204 ((((descneeded * sizeof(sca_descriptor)) / 1205 AR_BUF_SIZ) + 1) * AR_BUF_SIZ); 1206 sc->rxend = next + bufmem; 1207 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ; 1208 next += bufmem; 1209 TRC(printf("ar%d: rxdesc %x, rxstart %x, " 1210 "rxend %x, rxmax %d\n", 1211 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax)); 1212 } 1213 1214 if(hc->bustype == AR_BUS_PCI) 1215 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED; 1216 } 1217 1218 1219 /* 1220 * The things done here are channel independent. 1221 * 1222 * Configure the sca waitstates. 1223 * Configure the global interrupt registers. 1224 * Enable master dma enable. 1225 */ 1226 static void 1227 ar_init_sca(struct ar_hardc *hc, int scano) 1228 { 1229 sca_regs *sca; 1230 1231 sca = hc->sca[scano]; 1232 if(hc->bustype == AR_BUS_ISA) 1233 ARC_SET_SCA(hc, scano); 1234 1235 /* 1236 * Do the wait registers. 1237 * Set everything to 0 wait states. 1238 */ 1239 sca->pabr0 = 0; 1240 sca->pabr1 = 0; 1241 sca->wcrl = 0; 1242 sca->wcrm = 0; 1243 sca->wcrh = 0; 1244 1245 /* 1246 * Configure the interrupt registers. 1247 * Most are cleared until the interface is configured. 1248 */ 1249 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */ 1250 sca->ier1 = 0x00; /* DMAC interrupts */ 1251 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */ 1252 sca->itcr = 0x00; /* Use ivr and no intr ack */ 1253 sca->ivr = 0x40; /* Fill in the interrupt vector. */ 1254 sca->imvr = 0x40; 1255 1256 /* 1257 * Configure the timers. 1258 * XXX Later 1259 */ 1260 1261 1262 /* 1263 * Set the DMA channel priority to rotate between 1264 * all four channels. 1265 * 1266 * Enable all dma channels. 1267 */ 1268 if(hc->bustype == AR_BUS_PCI) { 1269 u_char *t; 1270 1271 /* 1272 * Stupid problem with the PCI interface chip that break 1273 * things. 1274 * XXX 1275 */ 1276 t = (u_char *)sca; 1277 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2; 1278 t[AR_PCI_SCA_DMER] = SCA_DMER_EN; 1279 } else { 1280 sca->pcr = SCA_PCR_PR2; 1281 sca->dmer = SCA_DMER_EN; 1282 } 1283 } 1284 1285 1286 /* 1287 * Configure the msci 1288 * 1289 * NOTE: The serial port configuration is hardcoded at the moment. 1290 */ 1291 static void 1292 ar_init_msci(struct ar_softc *sc) 1293 { 1294 msci_channel *msci; 1295 1296 msci = &sc->sca->msci[sc->scachan]; 1297 1298 if(sc->hc->bustype == AR_BUS_ISA) 1299 ARC_SET_SCA(sc->hc, sc->scano); 1300 1301 msci->cmd = SCA_CMD_RESET; 1302 1303 msci->md0 = SCA_MD0_CRC_1 | 1304 SCA_MD0_CRC_CCITT | 1305 SCA_MD0_CRC_ENABLE | 1306 SCA_MD0_MODE_HDLC; 1307 msci->md1 = SCA_MD1_NOADDRCHK; 1308 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ; 1309 1310 /* 1311 * Acording to the manual I should give a reset after changing the 1312 * mode registers. 1313 */ 1314 msci->cmd = SCA_CMD_RXRESET; 1315 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS; 1316 1317 /* 1318 * For now all interfaces are programmed to use the RX clock for 1319 * the TX clock. 1320 */ 1321 switch(sc->hc->interface[sc->subunit]) { 1322 case AR_IFACE_V_35: 1323 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1324 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1; 1325 break; 1326 case AR_IFACE_X_21: 1327 case AR_IFACE_EIA_530: 1328 case AR_IFACE_COMBO: 1329 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1; 1330 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1; 1331 } 1332 1333 msci->tmc = 153; /* This give 64k for loopback */ 1334 1335 /* XXX 1336 * Disable all interrupts for now. I think if you are using 1337 * the dmac you don't use these interrupts. 1338 */ 1339 msci->ie0 = 0; 1340 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */ 1341 msci->ie2 = 0; 1342 msci->fie = 0; 1343 1344 msci->sa0 = 0; 1345 msci->sa1 = 0; 1346 1347 msci->idl = 0x7E; /* XXX This is what cisco does. */ 1348 1349 /* 1350 * This is what the ARNET diags use. 1351 */ 1352 msci->rrc = 0x0E; 1353 msci->trc0 = 0x12; 1354 msci->trc1 = 0x1F; 1355 } 1356 1357 /* 1358 * Configure the rx dma controller. 1359 */ 1360 static void 1361 ar_init_rx_dmac(struct ar_softc *sc) 1362 { 1363 dmac_channel *dmac; 1364 sca_descriptor *rxd; 1365 u_int rxbuf; 1366 u_int rxda; 1367 u_int rxda_d; 1368 int x = 0; 1369 1370 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1371 1372 if(sc->hc->bustype == AR_BUS_ISA) 1373 ARC_SET_MEM(sc->hc, sc->rxdesc); 1374 1375 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk)); 1376 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk); 1377 1378 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) { 1379 rxda = (u_int)&rxd[1] - rxda_d; 1380 rxd->cp = (u_short)(rxda & 0xfffful); 1381 1382 x++; 1383 if(x < 6) 1384 TRC(printf("Descrp %p, data pt %x, data %x, ", 1385 rxd, rxda, rxbuf)); 1386 1387 rxd->bp = (u_short)(rxbuf & 0xfffful); 1388 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff); 1389 rxd->len = 0; 1390 rxd->stat = 0xff; /* The sca write here when it is finished. */ 1391 1392 if(x < 6) 1393 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp)); 1394 } 1395 rxd--; 1396 rxd->cp = (u_short)(sc->rxdesc & 0xfffful); 1397 1398 sc->rxhind = 0; 1399 1400 if(sc->hc->bustype == AR_BUS_ISA) 1401 ARC_SET_SCA(sc->hc, sc->scano); 1402 1403 dmac->dsr = 0; /* Disable DMA transfer */ 1404 dmac->dcr = SCA_DCR_ABRT; 1405 1406 /* XXX maybe also SCA_DMR_CNTE */ 1407 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1408 dmac->bfl = AR_BUF_SIZ; 1409 1410 dmac->cda = (u_short)(sc->rxdesc & 0xffff); 1411 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff); 1412 1413 rxd = (sca_descriptor *)sc->rxstart; 1414 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff); 1415 1416 dmac->dir = 0xF0; 1417 1418 dmac->dsr = SCA_DSR_DE; 1419 } 1420 1421 /* 1422 * Configure the TX DMA descriptors. 1423 * Initialize the needed values and chain the descriptors. 1424 */ 1425 static void 1426 ar_init_tx_dmac(struct ar_softc *sc) 1427 { 1428 dmac_channel *dmac; 1429 struct buf_block *blkp; 1430 int blk; 1431 sca_descriptor *txd; 1432 u_int txbuf; 1433 u_int txda; 1434 u_int txda_d; 1435 1436 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1437 1438 if(sc->hc->bustype == AR_BUS_ISA) 1439 ARC_SET_MEM(sc->hc, sc->block[0].txdesc); 1440 1441 for(blk = 0; blk < AR_TX_BLOCKS; blk++) { 1442 blkp = &sc->block[blk]; 1443 txd = (sca_descriptor *)(sc->hc->mem_start + 1444 (blkp->txdesc&sc->hc->winmsk)); 1445 txda_d = (u_int)sc->hc->mem_start - 1446 (blkp->txdesc & ~sc->hc->winmsk); 1447 1448 txbuf=blkp->txstart; 1449 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) { 1450 txda = (u_int)&txd[1] - txda_d; 1451 txd->cp = (u_short)(txda & 0xfffful); 1452 1453 txd->bp = (u_short)(txbuf & 0xfffful); 1454 txd->bpb = (u_char)((txbuf >> 16) & 0xff); 1455 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n", 1456 sc->unit, txbuf, txd->bpb, txd->bp)); 1457 txd->len = 0; 1458 txd->stat = 0; 1459 } 1460 txd--; 1461 txd->cp = (u_short)(blkp->txdesc & 0xfffful); 1462 1463 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start; 1464 TRC(printf("TX Descriptors start %x, end %x.\n", 1465 blkp->txdesc, 1466 blkp->txtail)); 1467 } 1468 1469 if(sc->hc->bustype == AR_BUS_ISA) 1470 ARC_SET_SCA(sc->hc, sc->scano); 1471 1472 dmac->dsr = 0; /* Disable DMA */ 1473 dmac->dcr = SCA_DCR_ABRT; 1474 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF; 1475 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF; 1476 1477 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff); 1478 } 1479 1480 1481 /* 1482 * Look through the descriptors to see if there is a complete packet 1483 * available. Stop if we get to where the sca is busy. 1484 * 1485 * Return the length and status of the packet. 1486 * Return nonzero if there is a packet available. 1487 * 1488 * NOTE: 1489 * It seems that we get the interrupt a bit early. The updateing of 1490 * descriptor values is not always completed when this is called. 1491 */ 1492 static int 1493 ar_packet_avail(struct ar_softc *sc, 1494 int *len, 1495 u_char *rxstat) 1496 { 1497 dmac_channel *dmac; 1498 sca_descriptor *rxdesc; 1499 sca_descriptor *endp; 1500 sca_descriptor *cda; 1501 1502 if(sc->hc->bustype == AR_BUS_ISA) 1503 ARC_SET_SCA(sc->hc, sc->scano); 1504 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1505 cda = (sca_descriptor *)(sc->hc->mem_start + 1506 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1507 1508 if(sc->hc->bustype == AR_BUS_ISA) 1509 ARC_SET_MEM(sc->hc, sc->rxdesc); 1510 rxdesc = (sca_descriptor *) 1511 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1512 endp = rxdesc; 1513 rxdesc = &rxdesc[sc->rxhind]; 1514 endp = &endp[sc->rxmax]; 1515 1516 *len = 0; 1517 1518 while(rxdesc != cda) { 1519 *len += rxdesc->len; 1520 1521 if(rxdesc->stat & SCA_DESC_EOM) { 1522 *rxstat = rxdesc->stat; 1523 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n", 1524 sc->unit, *len, *rxstat)); 1525 return (1); 1526 } 1527 1528 rxdesc++; 1529 if(rxdesc == endp) 1530 rxdesc = (sca_descriptor *) 1531 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1532 } 1533 1534 *len = 0; 1535 *rxstat = 0; 1536 return (0); 1537 } 1538 1539 1540 /* 1541 * Copy a packet from the on card memory into a provided mbuf. 1542 * Take into account that buffers wrap and that a packet may 1543 * be larger than a buffer. 1544 */ 1545 static void 1546 ar_copy_rxbuf(struct mbuf *m, 1547 struct ar_softc *sc, 1548 int len) 1549 { 1550 sca_descriptor *rxdesc; 1551 u_int rxdata; 1552 u_int rxmax; 1553 u_int off = 0; 1554 u_int tlen; 1555 1556 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ); 1557 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ); 1558 1559 rxdesc = (sca_descriptor *) 1560 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1561 rxdesc = &rxdesc[sc->rxhind]; 1562 1563 while(len) { 1564 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ; 1565 if(sc->hc->bustype == AR_BUS_ISA) 1566 ARC_SET_MEM(sc->hc, rxdata); 1567 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk), 1568 mtod(m, caddr_t) + off, 1569 tlen); 1570 1571 off += tlen; 1572 len -= tlen; 1573 1574 if(sc->hc->bustype == AR_BUS_ISA) 1575 ARC_SET_MEM(sc->hc, sc->rxdesc); 1576 rxdesc->len = 0; 1577 rxdesc->stat = 0xff; 1578 1579 rxdata += AR_BUF_SIZ; 1580 rxdesc++; 1581 if(rxdata == rxmax) { 1582 rxdata = sc->rxstart; 1583 rxdesc = (sca_descriptor *) 1584 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1585 } 1586 } 1587 } 1588 1589 /* 1590 * If single is set, just eat a packet. Otherwise eat everything up to 1591 * where cda points. Update pointers to point to the next packet. 1592 */ 1593 static void 1594 ar_eat_packet(struct ar_softc *sc, int single) 1595 { 1596 dmac_channel *dmac; 1597 sca_descriptor *rxdesc; 1598 sca_descriptor *endp; 1599 sca_descriptor *cda; 1600 int loopcnt = 0; 1601 u_char stat; 1602 1603 if(sc->hc->bustype == AR_BUS_ISA) 1604 ARC_SET_SCA(sc->hc, sc->scano); 1605 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)]; 1606 cda = (sca_descriptor *)(sc->hc->mem_start + 1607 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk)); 1608 1609 /* 1610 * Loop until desc->stat == (0xff || EOM) 1611 * Clear the status and length in the descriptor. 1612 * Increment the descriptor. 1613 */ 1614 if(sc->hc->bustype == AR_BUS_ISA) 1615 ARC_SET_MEM(sc->hc, sc->rxdesc); 1616 rxdesc = (sca_descriptor *) 1617 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1618 endp = rxdesc; 1619 rxdesc = &rxdesc[sc->rxhind]; 1620 endp = &endp[sc->rxmax]; 1621 1622 while(rxdesc != cda) { 1623 loopcnt++; 1624 if(loopcnt > sc->rxmax) { 1625 printf("ar%d: eat pkt %d loop, cda %p, " 1626 "rxdesc %p, stat %x.\n", 1627 sc->unit, 1628 loopcnt, 1629 (void *)cda, 1630 (void *)rxdesc, 1631 rxdesc->stat); 1632 break; 1633 } 1634 1635 stat = rxdesc->stat; 1636 1637 rxdesc->len = 0; 1638 rxdesc->stat = 0xff; 1639 1640 rxdesc++; 1641 sc->rxhind++; 1642 if(rxdesc == endp) { 1643 rxdesc = (sca_descriptor *) 1644 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk)); 1645 sc->rxhind = 0; 1646 } 1647 1648 if(single && (stat == SCA_DESC_EOM)) 1649 break; 1650 } 1651 1652 /* 1653 * Update the eda to the previous descriptor. 1654 */ 1655 if(sc->hc->bustype == AR_BUS_ISA) 1656 ARC_SET_SCA(sc->hc, sc->scano); 1657 1658 rxdesc = (sca_descriptor *)sc->rxdesc; 1659 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1660 1661 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1662 (u_short)((u_int)rxdesc & 0xffff); 1663 } 1664 1665 1666 /* 1667 * While there is packets available in the rx buffer, read them out 1668 * into mbufs and ship them off. 1669 */ 1670 static void 1671 ar_get_packets(struct ar_softc *sc) 1672 { 1673 sca_descriptor *rxdesc; 1674 struct mbuf *m = NULL; 1675 int i; 1676 int len; 1677 u_char rxstat; 1678 #ifdef NETGRAPH 1679 int error; 1680 #endif 1681 1682 while(ar_packet_avail(sc, &len, &rxstat)) { 1683 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat)); 1684 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 1685 MGETHDR(m, M_DONTWAIT, MT_DATA); 1686 if(m == NULL) { 1687 /* eat packet if get mbuf fail!! */ 1688 ar_eat_packet(sc, 1); 1689 continue; 1690 } 1691 #ifndef NETGRAPH 1692 m->m_pkthdr.rcvif = SC2IFP(sc); 1693 #else /* NETGRAPH */ 1694 m->m_pkthdr.rcvif = NULL; 1695 sc->inbytes += len; 1696 sc->inlast = 0; 1697 #endif /* NETGRAPH */ 1698 m->m_pkthdr.len = m->m_len = len; 1699 if(len > MHLEN) { 1700 MCLGET(m, M_DONTWAIT); 1701 if((m->m_flags & M_EXT) == 0) { 1702 m_freem(m); 1703 ar_eat_packet(sc, 1); 1704 continue; 1705 } 1706 } 1707 ar_copy_rxbuf(m, sc, len); 1708 #ifndef NETGRAPH 1709 BPF_MTAP(SC2IFP(sc), m); 1710 sppp_input(SC2IFP(sc), m); 1711 SC2IFP(sc)->if_ipackets++; 1712 #else /* NETGRAPH */ 1713 NG_SEND_DATA_ONLY(error, sc->hook, m); 1714 sc->ipackets++; 1715 #endif /* NETGRAPH */ 1716 1717 /* 1718 * Update the eda to the previous descriptor. 1719 */ 1720 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ; 1721 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 1722 1723 if(sc->hc->bustype == AR_BUS_ISA) 1724 ARC_SET_SCA(sc->hc, sc->scano); 1725 1726 rxdesc = (sca_descriptor *)sc->rxdesc; 1727 rxdesc = 1728 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax]; 1729 1730 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda = 1731 (u_short)((u_int)rxdesc & 0xffff); 1732 } else { 1733 int tries = 5; 1734 1735 while((rxstat == 0xff) && --tries) 1736 ar_packet_avail(sc, &len, &rxstat); 1737 1738 /* 1739 * It look like we get an interrupt early 1740 * sometimes and then the status is not 1741 * filled in yet. 1742 */ 1743 if(tries && (tries != 5)) 1744 continue; 1745 1746 ar_eat_packet(sc, 1); 1747 1748 #ifndef NETGRAPH 1749 SC2IFP(sc)->if_ierrors++; 1750 #else /* NETGRAPH */ 1751 sc->ierrors[0]++; 1752 #endif /* NETGRAPH */ 1753 1754 if(sc->hc->bustype == AR_BUS_ISA) 1755 ARC_SET_SCA(sc->hc, sc->scano); 1756 1757 TRCL(printf("ar%d: Receive error chan %d, " 1758 "stat %x, msci st3 %x," 1759 "rxhind %d, cda %x, eda %x.\n", 1760 sc->unit, 1761 sc->scachan, 1762 rxstat, 1763 sc->sca->msci[sc->scachan].st3, 1764 sc->rxhind, 1765 sc->sca->dmac[ 1766 DMAC_RXCH(sc->scachan)].cda, 1767 sc->sca->dmac[ 1768 DMAC_RXCH(sc->scachan)].eda)); 1769 } 1770 } 1771 } 1772 1773 1774 /* 1775 * All DMA interrupts come here. 1776 * 1777 * Each channel has two interrupts. 1778 * Interrupt A for errors and Interrupt B for normal stuff like end 1779 * of transmit or receive dmas. 1780 */ 1781 static void 1782 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1) 1783 { 1784 u_char dsr; 1785 u_char dotxstart = isr1; 1786 int mch; 1787 struct ar_softc *sc; 1788 sca_regs *sca; 1789 dmac_channel *dmac; 1790 1791 sca = hc->sca[scano]; 1792 mch = 0; 1793 /* 1794 * Shortcut if there is no interrupts for dma channel 0 or 1 1795 */ 1796 if((isr1 & 0x0F) == 0) { 1797 mch = 1; 1798 isr1 >>= 4; 1799 } 1800 1801 do { 1802 sc = &hc->sc[mch + (NCHAN * scano)]; 1803 1804 /* 1805 * Transmit channel 1806 */ 1807 if(isr1 & 0x0C) { 1808 dmac = &sca->dmac[DMAC_TXCH(mch)]; 1809 1810 if(hc->bustype == AR_BUS_ISA) 1811 ARC_SET_SCA(hc, scano); 1812 1813 dsr = dmac->dsr; 1814 dmac->dsr = dsr; 1815 1816 /* Counter overflow */ 1817 if(dsr & SCA_DSR_COF) { 1818 printf("ar%d: TX DMA Counter overflow, " 1819 "txpacket no %lu.\n", 1820 sc->unit, 1821 #ifndef NETGRAPH 1822 SC2IFP(sc)->if_opackets); 1823 SC2IFP(sc)->if_oerrors++; 1824 #else /* NETGRAPH */ 1825 sc->opackets); 1826 sc->oerrors++; 1827 #endif /* NETGRAPH */ 1828 } 1829 1830 /* Buffer overflow */ 1831 if(dsr & SCA_DSR_BOF) { 1832 printf("ar%d: TX DMA Buffer overflow, " 1833 "txpacket no %lu, dsr %02x, " 1834 "cda %04x, eda %04x.\n", 1835 sc->unit, 1836 #ifndef NETGRAPH 1837 SC2IFP(sc)->if_opackets, 1838 #else /* NETGRAPH */ 1839 sc->opackets, 1840 #endif /* NETGRAPH */ 1841 dsr, 1842 dmac->cda, 1843 dmac->eda); 1844 #ifndef NETGRAPH 1845 SC2IFP(sc)->if_oerrors++; 1846 #else /* NETGRAPH */ 1847 sc->oerrors++; 1848 #endif /* NETGRAPH */ 1849 } 1850 1851 /* End of Transfer */ 1852 if(dsr & SCA_DSR_EOT) { 1853 /* 1854 * This should be the most common case. 1855 * 1856 * Clear the IFF_DRV_OACTIVE flag. 1857 * 1858 * Call arstart to start a new transmit if 1859 * there is data to transmit. 1860 */ 1861 sc->xmit_busy = 0; 1862 #ifndef NETGRAPH 1863 SC2IFP(sc)->if_drv_flags &= ~IFF_DRV_OACTIVE; 1864 SC2IFP(sc)->if_timer = 0; 1865 #else /* NETGRAPH */ 1866 /* XXX SC2IFP(sc)->if_drv_flags &= ~IFF_DRV_OACTIVE; */ 1867 sc->out_dog = 0; /* XXX */ 1868 #endif /* NETGRAPH */ 1869 1870 if(sc->txb_inuse && --sc->txb_inuse) 1871 ar_xmit(sc); 1872 } 1873 } 1874 1875 /* 1876 * Receive channel 1877 */ 1878 if(isr1 & 0x03) { 1879 dmac = &sca->dmac[DMAC_RXCH(mch)]; 1880 1881 if(hc->bustype == AR_BUS_ISA) 1882 ARC_SET_SCA(hc, scano); 1883 1884 dsr = dmac->dsr; 1885 dmac->dsr = dsr; 1886 1887 TRC(printf("AR: RX DSR %x\n", dsr)); 1888 1889 /* End of frame */ 1890 if(dsr & SCA_DSR_EOM) { 1891 TRC(int tt = SC2IFP(sc)->if_ipackets;) 1892 TRC(int ind = sc->rxhind;) 1893 1894 ar_get_packets(sc); 1895 #ifndef NETGRAPH 1896 #define IPACKETS SC2IFP(sc)->if_ipackets 1897 #else /* NETGRAPH */ 1898 #define IPACKETS sc->ipackets 1899 #endif /* NETGRAPH */ 1900 TRC(if(tt == IPACKETS) { 1901 sca_descriptor *rxdesc; 1902 int i; 1903 1904 if(hc->bustype == AR_BUS_ISA) 1905 ARC_SET_SCA(hc, scano); 1906 printf("AR: RXINTR isr1 %x, dsr %x, " 1907 "no data %d pkts, orxhind %d.\n", 1908 dotxstart, 1909 dsr, 1910 tt, 1911 ind); 1912 printf("AR: rxdesc %x, rxstart %x, " 1913 "rxend %x, rxhind %d, " 1914 "rxmax %d.\n", 1915 sc->rxdesc, 1916 sc->rxstart, 1917 sc->rxend, 1918 sc->rxhind, 1919 sc->rxmax); 1920 printf("AR: cda %x, eda %x.\n", 1921 dmac->cda, 1922 dmac->eda); 1923 1924 if(sc->hc->bustype == AR_BUS_ISA) 1925 ARC_SET_MEM(sc->hc, 1926 sc->rxdesc); 1927 rxdesc = (sca_descriptor *) 1928 (sc->hc->mem_start + 1929 (sc->rxdesc & sc->hc->winmsk)); 1930 rxdesc = &rxdesc[sc->rxhind]; 1931 for(i=0;i<3;i++,rxdesc++) 1932 printf("AR: rxdesc->stat %x, " 1933 "len %d.\n", 1934 rxdesc->stat, 1935 rxdesc->len); 1936 }) 1937 } 1938 1939 /* Counter overflow */ 1940 if(dsr & SCA_DSR_COF) { 1941 printf("ar%d: RX DMA Counter overflow, " 1942 "rxpkts %lu.\n", 1943 sc->unit, 1944 #ifndef NETGRAPH 1945 SC2IFP(sc)->if_ipackets); 1946 SC2IFP(sc)->if_ierrors++; 1947 #else /* NETGRAPH */ 1948 sc->ipackets); 1949 sc->ierrors[1]++; 1950 #endif /* NETGRAPH */ 1951 } 1952 1953 /* Buffer overflow */ 1954 if(dsr & SCA_DSR_BOF) { 1955 if(hc->bustype == AR_BUS_ISA) 1956 ARC_SET_SCA(hc, scano); 1957 printf("ar%d: RX DMA Buffer overflow, " 1958 "rxpkts %lu, rxind %d, " 1959 "cda %x, eda %x, dsr %x.\n", 1960 sc->unit, 1961 #ifndef NETGRAPH 1962 SC2IFP(sc)->if_ipackets, 1963 #else /* NETGRAPH */ 1964 sc->ipackets, 1965 #endif /* NETGRAPH */ 1966 sc->rxhind, 1967 dmac->cda, 1968 dmac->eda, 1969 dsr); 1970 /* 1971 * Make sure we eat as many as possible. 1972 * Then get the system running again. 1973 */ 1974 ar_eat_packet(sc, 0); 1975 #ifndef NETGRAPH 1976 SC2IFP(sc)->if_ierrors++; 1977 #else /* NETGRAPH */ 1978 sc->ierrors[2]++; 1979 #endif /* NETGRAPH */ 1980 if(hc->bustype == AR_BUS_ISA) 1981 ARC_SET_SCA(hc, scano); 1982 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ; 1983 dmac->dsr = SCA_DSR_DE; 1984 1985 TRC(printf("ar%d: RX DMA Buffer overflow, " 1986 "rxpkts %lu, rxind %d, " 1987 "cda %x, eda %x, dsr %x. After\n", 1988 sc->unit, 1989 SC2IFP(sc)->if_ipackets, 1990 sc->rxhind, 1991 dmac->cda, 1992 dmac->eda, 1993 dmac->dsr);) 1994 } 1995 1996 /* End of Transfer */ 1997 if(dsr & SCA_DSR_EOT) { 1998 /* 1999 * If this happen, it means that we are 2000 * receiving faster than what the processor 2001 * can handle. 2002 * 2003 * XXX We should enable the dma again. 2004 */ 2005 printf("ar%d: RX End of transfer, rxpkts %lu.\n", 2006 sc->unit, 2007 #ifndef NETGRAPH 2008 SC2IFP(sc)->if_ipackets); 2009 SC2IFP(sc)->if_ierrors++; 2010 #else /* NETGRAPH */ 2011 sc->ipackets); 2012 sc->ierrors[3]++; 2013 #endif /* NETGRAPH */ 2014 } 2015 } 2016 2017 isr1 >>= 4; 2018 2019 mch++; 2020 }while((mch<NCHAN) && isr1); 2021 2022 /* 2023 * Now that we have done all the urgent things, see if we 2024 * can fill the transmit buffers. 2025 */ 2026 for(mch = 0; mch < NCHAN; mch++) { 2027 if(dotxstart & 0x0C) { 2028 sc = &hc->sc[mch + (NCHAN * scano)]; 2029 #ifndef NETGRAPH 2030 arstart(SC2IFP(sc)); 2031 #else /* NETGRAPH */ 2032 arstart(sc); 2033 #endif /* NETGRAPH */ 2034 } 2035 dotxstart >>= 4; 2036 } 2037 } 2038 2039 static void 2040 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0) 2041 { 2042 printf("arc%d: ARINTR: MSCI\n", hc->cunit); 2043 } 2044 2045 static void 2046 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2) 2047 { 2048 printf("arc%d: ARINTR: TIMER\n", hc->cunit); 2049 } 2050 2051 2052 #ifdef NETGRAPH 2053 /***************************************** 2054 * Device timeout/watchdog routine. 2055 * called once per second. 2056 * checks to see that if activity was expected, that it hapenned. 2057 * At present we only look to see if expected output was completed. 2058 */ 2059 static void 2060 ngar_watchdog_frame(void * arg) 2061 { 2062 struct ar_softc * sc = arg; 2063 int s; 2064 int speed; 2065 2066 if(sc->running == 0) 2067 return; /* if we are not running let timeouts die */ 2068 /* 2069 * calculate the apparent throughputs 2070 * XXX a real hack 2071 */ 2072 s = splimp(); 2073 speed = sc->inbytes - sc->lastinbytes; 2074 sc->lastinbytes = sc->inbytes; 2075 if ( sc->inrate < speed ) 2076 sc->inrate = speed; 2077 speed = sc->outbytes - sc->lastoutbytes; 2078 sc->lastoutbytes = sc->outbytes; 2079 if ( sc->outrate < speed ) 2080 sc->outrate = speed; 2081 sc->inlast++; 2082 splx(s); 2083 2084 if ((sc->inlast > QUITE_A_WHILE) 2085 && (sc->out_deficit > LOTS_OF_PACKETS)) { 2086 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit); 2087 s = splimp(); 2088 ar_down(sc); 2089 ar_up(sc); 2090 sc->inlast = sc->out_deficit = 0; 2091 splx(s); 2092 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 2093 if (sc->out_dog == 0) { 2094 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n", 2095 sc->unit); 2096 s = splimp(); 2097 arwatchdog(sc); 2098 #if 0 2099 ar_down(sc); 2100 ar_up(sc); 2101 #endif 2102 splx(s); 2103 sc->inlast = sc->out_deficit = 0; 2104 } else { 2105 sc->out_dog--; 2106 } 2107 } 2108 sc->handle = timeout(ngar_watchdog_frame, sc, hz); 2109 } 2110 2111 /*********************************************************************** 2112 * This section contains the methods for the Netgraph interface 2113 ***********************************************************************/ 2114 /* 2115 * It is not possible or allowable to create a node of this type. 2116 * If the hardware exists, it will already have created it. 2117 */ 2118 static int 2119 ngar_constructor(node_p node) 2120 { 2121 return (EINVAL); 2122 } 2123 2124 /* 2125 * give our ok for a hook to be added... 2126 * If we are not running this should kick the device into life. 2127 * The hook's private info points to our stash of info about that 2128 * channel. 2129 */ 2130 static int 2131 ngar_newhook(node_p node, hook_p hook, const char *name) 2132 { 2133 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2134 2135 /* 2136 * check if it's our friend the debug hook 2137 */ 2138 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) { 2139 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */ 2140 sc->debug_hook = hook; 2141 return (0); 2142 } 2143 2144 /* 2145 * Check for raw mode hook. 2146 */ 2147 if (strcmp(name, NG_AR_HOOK_RAW) != 0) { 2148 return (EINVAL); 2149 } 2150 NG_HOOK_SET_PRIVATE(hook, sc); 2151 sc->hook = hook; 2152 sc->datahooks++; 2153 ar_up(sc); 2154 return (0); 2155 } 2156 2157 /* 2158 * incoming messages. 2159 * Just respond to the generic TEXT_STATUS message 2160 */ 2161 static int 2162 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook) 2163 { 2164 struct ar_softc * sc; 2165 struct ng_mesg *resp = NULL; 2166 int error = 0; 2167 struct ng_mesg *msg; 2168 2169 NGI_GET_MSG(item, msg); 2170 sc = NG_NODE_PRIVATE(node); 2171 switch (msg->header.typecookie) { 2172 case NG_AR_COOKIE: 2173 error = EINVAL; 2174 break; 2175 case NGM_GENERIC_COOKIE: 2176 switch(msg->header.cmd) { 2177 case NGM_TEXT_STATUS: { 2178 char *arg; 2179 int pos = 0; 2180 2181 int resplen = sizeof(struct ng_mesg) + 512; 2182 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT); 2183 if (resp == NULL) { 2184 error = ENOMEM; 2185 break; 2186 } 2187 arg = (resp)->data; 2188 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 2189 "highest rate seen: %ld B/S in, %ld B/S out\n", 2190 sc->inbytes, sc->outbytes, 2191 sc->inrate, sc->outrate); 2192 pos += sprintf(arg + pos, 2193 "%ld output errors\n", 2194 sc->oerrors); 2195 pos += sprintf(arg + pos, 2196 "ierrors = %ld, %ld, %ld, %ld\n", 2197 sc->ierrors[0], 2198 sc->ierrors[1], 2199 sc->ierrors[2], 2200 sc->ierrors[3]); 2201 2202 resp->header.arglen = pos + 1; 2203 break; 2204 } 2205 default: 2206 error = EINVAL; 2207 break; 2208 } 2209 break; 2210 default: 2211 error = EINVAL; 2212 break; 2213 } 2214 /* Take care of synchronous response, if any */ 2215 NG_RESPOND_MSG(error, node, item, resp); 2216 NG_FREE_MSG(msg); 2217 return (error); 2218 } 2219 2220 /* 2221 * get data from another node and transmit it to the correct channel 2222 */ 2223 static int 2224 ngar_rcvdata(hook_p hook, item_p item) 2225 { 2226 int s; 2227 int error = 0; 2228 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2229 struct ifqueue *xmitq_p; 2230 struct mbuf *m; 2231 struct ng_tag_prio *ptag; 2232 2233 NGI_GET_M(item, m); 2234 NG_FREE_ITEM(item); 2235 /* 2236 * data doesn't come in from just anywhere (e.g control hook) 2237 */ 2238 if ( NG_HOOK_PRIVATE(hook) == NULL) { 2239 error = ENETDOWN; 2240 goto bad; 2241 } 2242 2243 /* 2244 * Now queue the data for when it can be sent 2245 */ 2246 if ((ptag = (struct ng_tag_prio *)m_tag_locate(m, NGM_GENERIC_COOKIE, 2247 NG_TAG_PRIO, NULL)) != NULL && (ptag->priority > NG_PRIO_CUTOFF) ) 2248 xmitq_p = (&sc->xmitq_hipri); 2249 else 2250 xmitq_p = (&sc->xmitq); 2251 2252 s = splimp(); 2253 IF_LOCK(xmitq_p); 2254 if (_IF_QFULL(xmitq_p)) { 2255 _IF_DROP(xmitq_p); 2256 IF_UNLOCK(xmitq_p); 2257 splx(s); 2258 error = ENOBUFS; 2259 goto bad; 2260 } 2261 _IF_ENQUEUE(xmitq_p, m); 2262 IF_UNLOCK(xmitq_p); 2263 arstart(sc); 2264 splx(s); 2265 return (0); 2266 2267 bad: 2268 /* 2269 * It was an error case. 2270 * check if we need to free the mbuf, and then return the error 2271 */ 2272 NG_FREE_M(m); 2273 return (error); 2274 } 2275 2276 /* 2277 * do local shutdown processing.. 2278 * this node will refuse to go away, unless the hardware says to.. 2279 * don't unref the node, or remove our name. just clear our links up. 2280 */ 2281 static int 2282 ngar_shutdown(node_p node) 2283 { 2284 struct ar_softc * sc = NG_NODE_PRIVATE(node); 2285 2286 ar_down(sc); 2287 NG_NODE_UNREF(node); 2288 /* XXX need to drain the output queues! */ 2289 2290 /* The node is dead, long live the node! */ 2291 /* stolen from the attach routine */ 2292 if (ng_make_node_common(&typestruct, &sc->node) != 0) 2293 return (0); 2294 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit); 2295 if (ng_name_node(sc->node, sc->nodename)) { 2296 sc->node = NULL; 2297 printf("node naming failed\n"); 2298 NG_NODE_UNREF(sc->node); /* node dissappears */ 2299 return (0); 2300 } 2301 NG_NODE_SET_PRIVATE(sc->node, sc); 2302 sc->running = 0; 2303 return (0); 2304 } 2305 2306 /* already linked */ 2307 static int 2308 ngar_connect(hook_p hook) 2309 { 2310 /* probably not at splnet, force outward queueing */ 2311 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 2312 /* be really amiable and just say "YUP that's OK by me! " */ 2313 return (0); 2314 } 2315 2316 /* 2317 * notify on hook disconnection (destruction) 2318 * 2319 * Invalidate the private data associated with this dlci. 2320 * For this type, removal of the last link resets tries to destroy the node. 2321 * As the device still exists, the shutdown method will not actually 2322 * destroy the node, but reset the device and leave it 'fresh' :) 2323 * 2324 * The node removal code will remove all references except that owned by the 2325 * driver. 2326 */ 2327 static int 2328 ngar_disconnect(hook_p hook) 2329 { 2330 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); 2331 int s; 2332 /* 2333 * If it's the data hook, then free resources etc. 2334 */ 2335 if (NG_HOOK_PRIVATE(hook)) { 2336 s = splimp(); 2337 sc->datahooks--; 2338 if (sc->datahooks == 0) 2339 ar_down(sc); 2340 splx(s); 2341 } else { 2342 sc->debug_hook = NULL; 2343 } 2344 return (0); 2345 } 2346 #endif /* NETGRAPH */ 2347 2348 /* 2349 ********************************* END ************************************ 2350 */
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