The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ar/if_arregs.h

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    1 /*
    2  * Copyright (c) 1995 - 2001 John Hay.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  * 3. Neither the name of the author nor the names of any co-contributors
   13  *    may be used to endorse or promote products derived from this software
   14  *    without specific prior written permission.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD: releng/5.0/sys/dev/ar/if_arregs.h 71599 2001-01-24 18:45:29Z jhay $
   29  */
   30 #ifndef _IF_ARREGS_H_
   31 #define _IF_ARREGS_H_
   32 
   33 #define NCHAN                   2    /* A HD64570 chip have 2 channels */
   34 #define NPORT                   4    /* A ArNet board can have 4 ports or */
   35                                      /* channels */
   36 
   37 #define AR_BUF_SIZ              512
   38 #define AR_TX_BLOCKS            2
   39 #define ARC_IO_SIZ              0x10
   40 #define ARC_WIN_SIZ             0x00004000
   41 #define ARC_WIN_MSK             (ARC_WIN_SIZ - 1)
   42 #define ARC_WIN_SHFT            14
   43 
   44 /* Some PCI specific offsets. */
   45 #define AR_PCI_SCA_1_OFFSET     0x00040000
   46 #define AR_PCI_SCA_2_OFFSET     0x00040400
   47 #define AR_PCI_ORBASE_OFFSET    0x00041000
   48 #define AR_PCI_SCA_PCR          0x0208
   49 #define AR_PCI_SCA_DMER         0x0309
   50 /* PCI Legacy (below 1M) offsets. */
   51 #define AR_PCI_L_SCA_1_OFFSET   0x00004000
   52 #define AR_PCI_L_SCA_2_OFFSET   0x00004400
   53 #define AR_PCI_L_ORBASE_OFFSET  0x00005000
   54 
   55 #define AR_ID_5                 0x00 /* RO, Card probe '5' */
   56 #define AR_ID_7                 0x01 /* RO, Card probe '7' */
   57 #define AR_ID_0                 0x02 /* RO, Card probe '' */
   58 #define AR_BMI                  0x03 /* RO, Bus, mem and interface type */
   59 #define AR_REV                  0x04 /* RO, Adapter revision */
   60 #define AR_PNUM                 0x05 /* RO, Port number */
   61 #define AR_HNDSH                0x06 /* RO, Supported handshake */
   62 #define AR_ISTAT                0x07 /* RO, DCD and Interrupt status */
   63 #define AR_MSCA_EN              0x08 /* WO, Memory and SCA enable */
   64 #define AR_TXC_DTR0             0x09 /* WO, Tx Clock and DTR control 0 + 1 */
   65 #define AR_SEC_PAL              0x0A /* RW, Security PAL */
   66 #define AR_INT_ACK0             0x0B /* RO, Interrupt Acknowledge 0 + 1 */
   67 #define AR_INT_SEL              0x0C /* RW, Interrupt Select */
   68 #define AR_MEM_SEL              0x0D /* RW, Memory Select */
   69 #define AR_INT_ACK2             0x0E /* RO, Interrupt Acknowledge 2 + 3 */
   70 #define AR_TXC_DTR2             0x0E /* WO, Tx Clock and DTR control 2 + 3 */
   71 /* PCI only */
   72 #define AR_PIMCTRL              0x4C /* RW, PIM and LEDs */
   73 #define AR_INT_SCB              0x50 /* RO, Interrupt Scoreboard */
   74 
   75 #define AR_REV_MSK              0x0F
   76 #define AR_WSIZ_MSK             0xE0
   77 #define AR_WSIZ_SHFT            5
   78 /* Bus memory and interface type */
   79 #define AR_BUS_MSK              0x03
   80 #define AR_BUS_ISA              0x00
   81 #define AR_BUS_MCA              0x01
   82 #define AR_BUS_EISA             0x02
   83 #define AR_BUS_PCI              0x03
   84 
   85 #define AR_MEM_MSK              0x1C
   86 #define AR_MEM_SHFT             0x02
   87 #define AR_MEM_64K              0x00
   88 #define AR_MEM_128K             0x04
   89 #define AR_MEM_256K             0x08
   90 #define AR_MEM_512K             0x0C
   91 
   92 /*
   93  * EIA-232
   94  * V.35/EIA-232
   95  * EIA-530
   96  * X.21
   97  * EIA-530/X.21 Combo
   98  */
   99 #define AR_IFACE_MSK            0xE0
  100 #define AR_IFACE_SHFT           0x05
  101 #define AR_IFACE_EIA_232        0x00  /* Only on the 570 card, not 570i */
  102 #define AR_IFACE_V_35           0x20  /* Selectable between V.35 and EIA-232 */
  103 #define AR_IFACE_EIA_530        0x40
  104 #define AR_IFACE_X_21           0x60
  105 #define AR_IFACE_COMBO          0xC0  /* X.21 / EIA-530 */
  106 #define AR_IFACE_PIM            0xE0  /* PIM module */
  107 #define AR_IFACE_LOOPBACK       0xFE
  108 #define AR_IFACE_UNKNOWN        0xFF
  109 
  110 /* Supported Handshake signals */
  111 #define AR_SHSK_DTR             0x01
  112 #define AR_SHSK_RTS             0x02
  113 #define AR_SHSK_CTS             0x10
  114 #define AR_SHSK_DSR             0x20
  115 #define AR_SHSK_RI              0x40
  116 #define AR_SHSK_DCD             0x80
  117 
  118 /* DCD and Interrupt status */
  119 #define AR_BD_INT               0x01
  120 #define AR_INT_0                0x20
  121 #define AR_INT_1                0x40
  122 
  123 #define AR_DCD_MSK              0x1E
  124 #define AR_DCD_SHFT             0x01
  125 #define AR_DCD_0                0x02
  126 #define AR_DCD_1                0x04
  127 #define AR_DCD_2                0x08
  128 #define AR_DCD_3                0x10
  129 
  130 /* Memory and SCA enable */
  131 #define AR_WIN_MSK              0x1F
  132 
  133 #define AR_SEL_SCA_0            0x00
  134 #define AR_SEL_SCA_1            0x20
  135 #define AR_ENA_SCA              0x40
  136 #define AR_ENA_MEM              0x80
  137 
  138 /* Transmit Clock and DTR and RESET */
  139 #define AR_TXC_DTR_TX0          0x01
  140 #define AR_TXC_DTR_TX1          0x02
  141 #define AR_TXC_DTR_DTR0         0x04
  142 #define AR_TXC_DTR_DTR1         0x08
  143 #define AR_TXC_DTR_TXCS0        0x10
  144 #define AR_TXC_DTR_TXCS1        0x20
  145 #define AR_TXC_DTR_NOTRESET     0x40
  146 #define AR_TXC_DTR_RESET        0x00
  147 
  148 /* Interrupt select register */
  149 #define AR_INTS_CEN             0x01
  150 #define AR_INTS_ISEL0           0x02
  151 #define AR_INTS_ISEL1           0x04
  152 #define AR_INTS_ISEL2           0x08
  153 #define AR_INTS_CMA14           0x10
  154 #define AR_INTS_CMA15           0x20
  155 
  156 /* Advanced PIM Control */
  157 #define AR_PIM_STROBE           0x01
  158 #define AR_PIM_DATA             0x02
  159 #define AR_PIM_MODEG            0x04
  160 #define AR_PIM_A2D_STROBE       0x04
  161 #define AR_PIM_MODEY            0x08
  162 #define AR_PIM_A2D_DOUT         0x08
  163 #define AR_PIM_AUTO_LED         0x10
  164 #define AR_PIM_INT              0x20
  165 
  166 #define AR_PIM_RESET            0x00 /* MODEG and MODEY 0 */
  167 #define AR_PIM_READ             AR_PIM_MODEG
  168 #define AR_PIM_WRITE            AR_PIM_MODEY
  169 
  170 #define ARC_GET_WIN(addr)       ((addr >> ARC_WIN_SHFT) & AR_WIN_MSK)
  171 
  172 #define ARC_SET_MEM(iobase,win) outb(iobase+AR_MSCA_EN, AR_ENA_MEM | \
  173                                 ARC_GET_WIN(win))
  174 #define ARC_SET_SCA(iobase,ch)  outb(iobase+AR_MSCA_EN, AR_ENA_MEM | \
  175                                 AR_ENA_SCA | (ch ? AR_SEL_SCA_1:AR_SEL_SCA_0))
  176 #define ARC_SET_OFF(iobase)     outb(iobase+AR_MSCA_EN, 0)
  177 
  178 struct ar_hardc {
  179         int cunit;
  180         struct ar_softc *sc;
  181         u_short iobase;
  182         int isa_irq;
  183         int numports;
  184         caddr_t mem_start;
  185         caddr_t mem_end;
  186         caddr_t plx_mem;
  187         u_char *orbase;
  188 
  189         u_int memsize;          /* in bytes */
  190         u_int winsize;          /* in bytes */
  191         u_int winmsk;
  192         u_char bustype;         /* ISA, MCA, PCI.... */
  193         u_char interface[NPORT];/* X21, V.35, EIA-530.... */
  194         u_char revision;
  195         u_char handshake;       /* handshake lines supported by card. */
  196 
  197         u_char txc_dtr[NPORT/NCHAN]; /* the register is write only */
  198         u_int txc_dtr_off[NPORT/NCHAN];
  199 
  200         sca_regs *sca[NPORT/NCHAN];
  201 
  202         bus_space_tag_t bt;
  203         bus_space_handle_t bh;
  204         int rid_ioport;
  205         int rid_memory;
  206         int rid_plx_memory;
  207         int rid_irq;
  208         int rid_drq;
  209         struct resource* res_ioport;    /* resource for port range */
  210         struct resource* res_memory;    /* resource for mem range */
  211         struct resource* res_plx_memory;
  212         struct resource* res_irq;       /* resource for irq range */
  213         struct resource* res_drq;       /* resource for dma channel */
  214         void    *intr_cookie;
  215 };
  216 
  217 extern devclass_t ar_devclass;
  218 
  219 int ar_allocate_ioport(device_t device, int rid, u_long size);
  220 int ar_allocate_irq(device_t device, int rid, u_long size);
  221 int ar_allocate_memory(device_t device, int rid, u_long size);
  222 int ar_allocate_plx_memory(device_t device, int rid, u_long size);
  223 int ar_deallocate_resources(device_t device);
  224 int ar_attach(device_t device);
  225 int ar_detach (device_t);
  226 
  227 #endif /* _IF_ARREGS_H_ */

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