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sys/dev/arcmsr/arcmsr.c
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1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886 89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created 90 ****************************************************************************************** 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 #if 0 97 #define ARCMSR_DEBUG1 1 98 #endif 99 #include <sys/param.h> 100 #include <sys/systm.h> 101 #include <sys/malloc.h> 102 #include <sys/kernel.h> 103 #include <sys/bus.h> 104 #include <sys/queue.h> 105 #include <sys/stat.h> 106 #include <sys/devicestat.h> 107 #include <sys/kthread.h> 108 #include <sys/module.h> 109 #include <sys/proc.h> 110 #include <sys/lock.h> 111 #include <sys/sysctl.h> 112 #include <sys/poll.h> 113 #include <sys/ioccom.h> 114 #include <vm/vm.h> 115 #include <vm/vm_param.h> 116 #include <vm/pmap.h> 117 118 #include <isa/rtc.h> 119 120 #include <machine/bus.h> 121 #include <machine/resource.h> 122 #include <machine/atomic.h> 123 #include <sys/conf.h> 124 #include <sys/rman.h> 125 126 #include <cam/cam.h> 127 #include <cam/cam_ccb.h> 128 #include <cam/cam_sim.h> 129 #include <cam/cam_periph.h> 130 #include <cam/cam_xpt_periph.h> 131 #include <cam/cam_xpt_sim.h> 132 #include <cam/cam_debug.h> 133 #include <cam/scsi/scsi_all.h> 134 #include <cam/scsi/scsi_message.h> 135 /* 136 ************************************************************************** 137 ************************************************************************** 138 */ 139 #include <sys/selinfo.h> 140 #include <sys/mutex.h> 141 #include <sys/endian.h> 142 #include <dev/pci/pcivar.h> 143 #include <dev/pci/pcireg.h> 144 145 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 146 147 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.04 2021-12-08" 148 #include <dev/arcmsr/arcmsr.h> 149 /* 150 ************************************************************************** 151 ************************************************************************** 152 */ 153 static void arcmsr_free_srb(struct CommandControlBlock *srb); 154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 156 static int arcmsr_probe(device_t dev); 157 static int arcmsr_attach(device_t dev); 158 static int arcmsr_detach(device_t dev); 159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 161 static int arcmsr_shutdown(device_t dev); 162 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 164 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 178 static int arcmsr_resume(device_t dev); 179 static int arcmsr_suspend(device_t dev); 180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 181 static void arcmsr_polling_devmap(void *arg); 182 static void arcmsr_srb_timeout(void *arg); 183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 184 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 185 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 186 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 187 #ifdef ARCMSR_DEBUG1 188 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 189 #endif 190 /* 191 ************************************************************************** 192 ************************************************************************** 193 */ 194 static void UDELAY(u_int32_t us) { DELAY(us); } 195 /* 196 ************************************************************************** 197 ************************************************************************** 198 */ 199 static bus_dmamap_callback_t arcmsr_map_free_srb; 200 static bus_dmamap_callback_t arcmsr_execute_srb; 201 /* 202 ************************************************************************** 203 ************************************************************************** 204 */ 205 static d_open_t arcmsr_open; 206 static d_close_t arcmsr_close; 207 static d_ioctl_t arcmsr_ioctl; 208 209 static device_method_t arcmsr_methods[]={ 210 DEVMETHOD(device_probe, arcmsr_probe), 211 DEVMETHOD(device_attach, arcmsr_attach), 212 DEVMETHOD(device_detach, arcmsr_detach), 213 DEVMETHOD(device_shutdown, arcmsr_shutdown), 214 DEVMETHOD(device_suspend, arcmsr_suspend), 215 DEVMETHOD(device_resume, arcmsr_resume), 216 DEVMETHOD_END 217 }; 218 219 static driver_t arcmsr_driver={ 220 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 221 }; 222 223 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, 0, 0); 224 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 225 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 226 #ifndef BUS_DMA_COHERENT 227 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 228 #endif 229 static struct cdevsw arcmsr_cdevsw={ 230 .d_version = D_VERSION, 231 .d_open = arcmsr_open, /* open */ 232 .d_close = arcmsr_close, /* close */ 233 .d_ioctl = arcmsr_ioctl, /* ioctl */ 234 .d_name = "arcmsr", /* name */ 235 }; 236 /* 237 ************************************************************************** 238 ************************************************************************** 239 */ 240 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 241 { 242 return (0); 243 } 244 /* 245 ************************************************************************** 246 ************************************************************************** 247 */ 248 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 249 { 250 return 0; 251 } 252 /* 253 ************************************************************************** 254 ************************************************************************** 255 */ 256 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 257 { 258 struct AdapterControlBlock *acb = dev->si_drv1; 259 260 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 261 } 262 /* 263 ********************************************************************** 264 ********************************************************************** 265 */ 266 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 267 { 268 u_int32_t intmask_org = 0; 269 270 switch (acb->adapter_type) { 271 case ACB_ADAPTER_TYPE_A: { 272 /* disable all outbound interrupt */ 273 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 274 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 275 } 276 break; 277 case ACB_ADAPTER_TYPE_B: { 278 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 279 /* disable all outbound interrupt */ 280 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 281 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 282 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 283 } 284 break; 285 case ACB_ADAPTER_TYPE_C: { 286 /* disable all outbound interrupt */ 287 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 288 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 289 } 290 break; 291 case ACB_ADAPTER_TYPE_D: { 292 /* disable all outbound interrupt */ 293 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 294 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 295 } 296 break; 297 case ACB_ADAPTER_TYPE_E: 298 case ACB_ADAPTER_TYPE_F: { 299 /* disable all outbound interrupt */ 300 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 301 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 302 } 303 break; 304 } 305 return (intmask_org); 306 } 307 /* 308 ********************************************************************** 309 ********************************************************************** 310 */ 311 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 312 { 313 u_int32_t mask; 314 315 switch (acb->adapter_type) { 316 case ACB_ADAPTER_TYPE_A: { 317 /* enable outbound Post Queue, outbound doorbell Interrupt */ 318 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 319 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 320 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 321 } 322 break; 323 case ACB_ADAPTER_TYPE_B: { 324 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 325 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 326 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 327 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 328 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 329 } 330 break; 331 case ACB_ADAPTER_TYPE_C: { 332 /* enable outbound Post Queue, outbound doorbell Interrupt */ 333 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 334 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 335 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 336 } 337 break; 338 case ACB_ADAPTER_TYPE_D: { 339 /* enable outbound Post Queue, outbound doorbell Interrupt */ 340 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 341 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 342 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 343 acb->outbound_int_enable = mask; 344 } 345 break; 346 case ACB_ADAPTER_TYPE_E: 347 case ACB_ADAPTER_TYPE_F: { 348 /* enable outbound Post Queue, outbound doorbell Interrupt */ 349 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 350 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 351 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 352 } 353 break; 354 } 355 } 356 /* 357 ********************************************************************** 358 ********************************************************************** 359 */ 360 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 361 { 362 u_int32_t Index; 363 u_int8_t Retries = 0x00; 364 365 do { 366 for(Index=0; Index < 100; Index++) { 367 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 368 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 369 return TRUE; 370 } 371 UDELAY(10000); 372 }/*max 1 seconds*/ 373 }while(Retries++ < 20);/*max 20 sec*/ 374 return (FALSE); 375 } 376 /* 377 ********************************************************************** 378 ********************************************************************** 379 */ 380 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 381 { 382 u_int32_t Index; 383 u_int8_t Retries = 0x00; 384 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 385 386 do { 387 for(Index=0; Index < 100; Index++) { 388 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 389 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 390 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 391 return TRUE; 392 } 393 UDELAY(10000); 394 }/*max 1 seconds*/ 395 }while(Retries++ < 20);/*max 20 sec*/ 396 return (FALSE); 397 } 398 /* 399 ********************************************************************** 400 ********************************************************************** 401 */ 402 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 403 { 404 u_int32_t Index; 405 u_int8_t Retries = 0x00; 406 407 do { 408 for(Index=0; Index < 100; Index++) { 409 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 410 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 411 return TRUE; 412 } 413 UDELAY(10000); 414 }/*max 1 seconds*/ 415 }while(Retries++ < 20);/*max 20 sec*/ 416 return (FALSE); 417 } 418 /* 419 ********************************************************************** 420 ********************************************************************** 421 */ 422 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 423 { 424 u_int32_t Index; 425 u_int8_t Retries = 0x00; 426 427 do { 428 for(Index=0; Index < 100; Index++) { 429 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 430 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 431 return TRUE; 432 } 433 UDELAY(10000); 434 }/*max 1 seconds*/ 435 }while(Retries++ < 20);/*max 20 sec*/ 436 return (FALSE); 437 } 438 /* 439 ********************************************************************** 440 ********************************************************************** 441 */ 442 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 443 { 444 u_int32_t Index, read_doorbell; 445 u_int8_t Retries = 0x00; 446 447 do { 448 for(Index=0; Index < 100; Index++) { 449 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 450 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 451 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 452 acb->in_doorbell = read_doorbell; 453 return TRUE; 454 } 455 UDELAY(10000); 456 }/*max 1 seconds*/ 457 }while(Retries++ < 20);/*max 20 sec*/ 458 return (FALSE); 459 } 460 /* 461 ************************************************************************ 462 ************************************************************************ 463 */ 464 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 465 { 466 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 467 468 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 469 do { 470 if(arcmsr_hba_wait_msgint_ready(acb)) { 471 break; 472 } else { 473 retry_count--; 474 } 475 }while(retry_count != 0); 476 } 477 /* 478 ************************************************************************ 479 ************************************************************************ 480 */ 481 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 482 { 483 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 484 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 485 486 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 487 do { 488 if(arcmsr_hbb_wait_msgint_ready(acb)) { 489 break; 490 } else { 491 retry_count--; 492 } 493 }while(retry_count != 0); 494 } 495 /* 496 ************************************************************************ 497 ************************************************************************ 498 */ 499 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 500 { 501 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 502 503 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 504 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 505 do { 506 if(arcmsr_hbc_wait_msgint_ready(acb)) { 507 break; 508 } else { 509 retry_count--; 510 } 511 }while(retry_count != 0); 512 } 513 /* 514 ************************************************************************ 515 ************************************************************************ 516 */ 517 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 518 { 519 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 520 521 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 522 do { 523 if(arcmsr_hbd_wait_msgint_ready(acb)) { 524 break; 525 } else { 526 retry_count--; 527 } 528 }while(retry_count != 0); 529 } 530 /* 531 ************************************************************************ 532 ************************************************************************ 533 */ 534 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 535 { 536 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 537 538 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 539 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 540 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 541 do { 542 if(arcmsr_hbe_wait_msgint_ready(acb)) { 543 break; 544 } else { 545 retry_count--; 546 } 547 }while(retry_count != 0); 548 } 549 /* 550 ************************************************************************ 551 ************************************************************************ 552 */ 553 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 554 { 555 switch (acb->adapter_type) { 556 case ACB_ADAPTER_TYPE_A: { 557 arcmsr_flush_hba_cache(acb); 558 } 559 break; 560 case ACB_ADAPTER_TYPE_B: { 561 arcmsr_flush_hbb_cache(acb); 562 } 563 break; 564 case ACB_ADAPTER_TYPE_C: { 565 arcmsr_flush_hbc_cache(acb); 566 } 567 break; 568 case ACB_ADAPTER_TYPE_D: { 569 arcmsr_flush_hbd_cache(acb); 570 } 571 break; 572 case ACB_ADAPTER_TYPE_E: 573 case ACB_ADAPTER_TYPE_F: { 574 arcmsr_flush_hbe_cache(acb); 575 } 576 break; 577 } 578 } 579 /* 580 ******************************************************************************* 581 ******************************************************************************* 582 */ 583 static int arcmsr_suspend(device_t dev) 584 { 585 struct AdapterControlBlock *acb = device_get_softc(dev); 586 587 /* flush controller */ 588 arcmsr_iop_parking(acb); 589 /* disable all outbound interrupt */ 590 arcmsr_disable_allintr(acb); 591 return(0); 592 } 593 /* 594 ******************************************************************************* 595 ******************************************************************************* 596 */ 597 static int arcmsr_resume(device_t dev) 598 { 599 struct AdapterControlBlock *acb = device_get_softc(dev); 600 601 arcmsr_iop_init(acb); 602 return(0); 603 } 604 /* 605 ********************************************************************************* 606 ********************************************************************************* 607 */ 608 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 609 { 610 u_int8_t target_id, target_lun; 611 612 switch (code) { 613 case AC_LOST_DEVICE: 614 target_id = xpt_path_target_id(path); 615 target_lun = xpt_path_lun_id(path); 616 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 617 break; 618 } 619 break; 620 default: 621 break; 622 } 623 } 624 /* 625 ********************************************************************** 626 ********************************************************************** 627 */ 628 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 629 { 630 union ccb *pccb = srb->pccb; 631 632 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 633 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 634 if(pccb->csio.sense_len) { 635 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 636 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 637 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 638 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 639 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 640 } 641 } 642 /* 643 ********************************************************************* 644 ********************************************************************* 645 */ 646 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 647 { 648 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 649 if(!arcmsr_hba_wait_msgint_ready(acb)) { 650 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 651 } 652 } 653 /* 654 ********************************************************************* 655 ********************************************************************* 656 */ 657 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 658 { 659 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 660 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 661 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 662 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 663 } 664 } 665 /* 666 ********************************************************************* 667 ********************************************************************* 668 */ 669 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 670 { 671 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 672 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 673 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 674 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 675 } 676 } 677 /* 678 ********************************************************************* 679 ********************************************************************* 680 */ 681 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 682 { 683 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 684 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 685 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 686 } 687 } 688 /* 689 ********************************************************************* 690 ********************************************************************* 691 */ 692 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 693 { 694 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 695 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 696 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 697 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 698 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 699 } 700 } 701 /* 702 ********************************************************************* 703 ********************************************************************* 704 */ 705 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 706 { 707 switch (acb->adapter_type) { 708 case ACB_ADAPTER_TYPE_A: { 709 arcmsr_abort_hba_allcmd(acb); 710 } 711 break; 712 case ACB_ADAPTER_TYPE_B: { 713 arcmsr_abort_hbb_allcmd(acb); 714 } 715 break; 716 case ACB_ADAPTER_TYPE_C: { 717 arcmsr_abort_hbc_allcmd(acb); 718 } 719 break; 720 case ACB_ADAPTER_TYPE_D: { 721 arcmsr_abort_hbd_allcmd(acb); 722 } 723 break; 724 case ACB_ADAPTER_TYPE_E: 725 case ACB_ADAPTER_TYPE_F: { 726 arcmsr_abort_hbe_allcmd(acb); 727 } 728 break; 729 } 730 } 731 /* 732 ********************************************************************** 733 ********************************************************************** 734 */ 735 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 736 { 737 struct AdapterControlBlock *acb = srb->acb; 738 union ccb *pccb = srb->pccb; 739 740 if(srb->srb_flags & SRB_FLAG_TIMER_START) 741 callout_stop(&srb->ccb_callout); 742 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 743 bus_dmasync_op_t op; 744 745 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 746 op = BUS_DMASYNC_POSTREAD; 747 } else { 748 op = BUS_DMASYNC_POSTWRITE; 749 } 750 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 751 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 752 } 753 if(stand_flag == 1) { 754 atomic_subtract_int(&acb->srboutstandingcount, 1); 755 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 756 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 757 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 758 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 759 } 760 } 761 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 762 arcmsr_free_srb(srb); 763 acb->pktReturnCount++; 764 xpt_done(pccb); 765 } 766 /* 767 ************************************************************************** 768 ************************************************************************** 769 */ 770 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 771 { 772 int target, lun; 773 774 target = srb->pccb->ccb_h.target_id; 775 lun = srb->pccb->ccb_h.target_lun; 776 if(error == FALSE) { 777 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 778 acb->devstate[target][lun] = ARECA_RAID_GOOD; 779 } 780 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 781 arcmsr_srb_complete(srb, 1); 782 } else { 783 switch(srb->arcmsr_cdb.DeviceStatus) { 784 case ARCMSR_DEV_SELECT_TIMEOUT: { 785 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 786 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 787 } 788 acb->devstate[target][lun] = ARECA_RAID_GONE; 789 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 790 arcmsr_srb_complete(srb, 1); 791 } 792 break; 793 case ARCMSR_DEV_ABORTED: 794 case ARCMSR_DEV_INIT_FAIL: { 795 acb->devstate[target][lun] = ARECA_RAID_GONE; 796 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 797 arcmsr_srb_complete(srb, 1); 798 } 799 break; 800 case SCSISTAT_CHECK_CONDITION: { 801 acb->devstate[target][lun] = ARECA_RAID_GOOD; 802 arcmsr_report_sense_info(srb); 803 arcmsr_srb_complete(srb, 1); 804 } 805 break; 806 default: 807 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 808 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 809 acb->devstate[target][lun] = ARECA_RAID_GONE; 810 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 811 /*unknown error or crc error just for retry*/ 812 arcmsr_srb_complete(srb, 1); 813 break; 814 } 815 } 816 } 817 /* 818 ************************************************************************** 819 ************************************************************************** 820 */ 821 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 822 { 823 struct CommandControlBlock *srb; 824 825 /* check if command done with no error*/ 826 switch (acb->adapter_type) { 827 case ACB_ADAPTER_TYPE_A: 828 case ACB_ADAPTER_TYPE_B: 829 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 830 break; 831 case ACB_ADAPTER_TYPE_C: 832 case ACB_ADAPTER_TYPE_D: 833 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 834 break; 835 case ACB_ADAPTER_TYPE_E: 836 case ACB_ADAPTER_TYPE_F: 837 srb = acb->psrb_pool[flag_srb]; 838 break; 839 default: 840 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 841 break; 842 } 843 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 844 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 845 arcmsr_free_srb(srb); 846 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 847 return; 848 } 849 printf("arcmsr%d: return srb has been completed\n" 850 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 851 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 852 return; 853 } 854 arcmsr_report_srb_state(acb, srb, error); 855 } 856 /* 857 ************************************************************************** 858 ************************************************************************** 859 */ 860 static void arcmsr_srb_timeout(void *arg) 861 { 862 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 863 struct AdapterControlBlock *acb; 864 int target, lun; 865 u_int8_t cmd; 866 867 target = srb->pccb->ccb_h.target_id; 868 lun = srb->pccb->ccb_h.target_lun; 869 acb = srb->acb; 870 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 871 if(srb->srb_state == ARCMSR_SRB_START) 872 { 873 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 874 srb->srb_state = ARCMSR_SRB_TIMEOUT; 875 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 876 arcmsr_srb_complete(srb, 1); 877 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 878 acb->pci_unit, target, lun, cmd, srb); 879 } 880 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 881 #ifdef ARCMSR_DEBUG1 882 arcmsr_dump_data(acb); 883 #endif 884 } 885 886 /* 887 ********************************************************************** 888 ********************************************************************** 889 */ 890 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 891 { 892 int i=0; 893 u_int32_t flag_srb; 894 u_int16_t error; 895 896 switch (acb->adapter_type) { 897 case ACB_ADAPTER_TYPE_A: { 898 u_int32_t outbound_intstatus; 899 900 /*clear and abort all outbound posted Q*/ 901 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 902 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 903 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 904 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 905 arcmsr_drain_donequeue(acb, flag_srb, error); 906 } 907 } 908 break; 909 case ACB_ADAPTER_TYPE_B: { 910 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 911 912 /*clear all outbound posted Q*/ 913 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 914 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 915 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 916 phbbmu->done_qbuffer[i] = 0; 917 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 918 arcmsr_drain_donequeue(acb, flag_srb, error); 919 } 920 phbbmu->post_qbuffer[i] = 0; 921 }/*drain reply FIFO*/ 922 phbbmu->doneq_index = 0; 923 phbbmu->postq_index = 0; 924 } 925 break; 926 case ACB_ADAPTER_TYPE_C: { 927 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 928 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 929 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 930 arcmsr_drain_donequeue(acb, flag_srb, error); 931 } 932 } 933 break; 934 case ACB_ADAPTER_TYPE_D: 935 arcmsr_hbd_postqueue_isr(acb); 936 break; 937 case ACB_ADAPTER_TYPE_E: 938 arcmsr_hbe_postqueue_isr(acb); 939 break; 940 case ACB_ADAPTER_TYPE_F: 941 arcmsr_hbf_postqueue_isr(acb); 942 break; 943 } 944 } 945 /* 946 **************************************************************************** 947 **************************************************************************** 948 */ 949 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 950 { 951 struct CommandControlBlock *srb; 952 u_int32_t intmask_org; 953 u_int32_t i=0; 954 955 if(acb->srboutstandingcount>0) { 956 /* disable all outbound interrupt */ 957 intmask_org = arcmsr_disable_allintr(acb); 958 /*clear and abort all outbound posted Q*/ 959 arcmsr_done4abort_postqueue(acb); 960 /* talk to iop 331 outstanding command aborted*/ 961 arcmsr_abort_allcmd(acb); 962 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 963 srb = acb->psrb_pool[i]; 964 if(srb->srb_state == ARCMSR_SRB_START) { 965 srb->srb_state = ARCMSR_SRB_ABORTED; 966 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 967 arcmsr_srb_complete(srb, 1); 968 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 969 , acb->pci_unit, srb->pccb->ccb_h.target_id 970 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 971 } 972 } 973 /* enable all outbound interrupt */ 974 arcmsr_enable_allintr(acb, intmask_org); 975 } 976 acb->srboutstandingcount = 0; 977 acb->workingsrb_doneindex = 0; 978 acb->workingsrb_startindex = 0; 979 acb->pktRequestCount = 0; 980 acb->pktReturnCount = 0; 981 } 982 /* 983 ********************************************************************** 984 ********************************************************************** 985 */ 986 static void arcmsr_build_srb(struct CommandControlBlock *srb, 987 bus_dma_segment_t *dm_segs, u_int32_t nseg) 988 { 989 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 990 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 991 u_int32_t address_lo, address_hi; 992 union ccb *pccb = srb->pccb; 993 struct ccb_scsiio *pcsio = &pccb->csio; 994 u_int32_t arccdbsize = 0x30; 995 996 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 997 arcmsr_cdb->Bus = 0; 998 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 999 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1000 arcmsr_cdb->Function = 1; 1001 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1002 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1003 if(nseg != 0) { 1004 struct AdapterControlBlock *acb = srb->acb; 1005 bus_dmasync_op_t op; 1006 u_int32_t length, i, cdb_sgcount = 0; 1007 1008 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1009 op = BUS_DMASYNC_PREREAD; 1010 } else { 1011 op = BUS_DMASYNC_PREWRITE; 1012 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1013 srb->srb_flags |= SRB_FLAG_WRITE; 1014 } 1015 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1016 for(i=0; i < nseg; i++) { 1017 /* Get the physical address of the current data pointer */ 1018 length = arcmsr_htole32(dm_segs[i].ds_len); 1019 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1020 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1021 if(address_hi == 0) { 1022 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1023 pdma_sg->address = address_lo; 1024 pdma_sg->length = length; 1025 psge += sizeof(struct SG32ENTRY); 1026 arccdbsize += sizeof(struct SG32ENTRY); 1027 } else { 1028 u_int32_t sg64s_size = 0, tmplength = length; 1029 1030 while(1) { 1031 u_int64_t span4G, length0; 1032 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1033 1034 span4G = (u_int64_t)address_lo + tmplength; 1035 pdma_sg->addresshigh = address_hi; 1036 pdma_sg->address = address_lo; 1037 if(span4G > 0x100000000) { 1038 /*see if cross 4G boundary*/ 1039 length0 = 0x100000000-address_lo; 1040 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1041 address_hi = address_hi+1; 1042 address_lo = 0; 1043 tmplength = tmplength - (u_int32_t)length0; 1044 sg64s_size += sizeof(struct SG64ENTRY); 1045 psge += sizeof(struct SG64ENTRY); 1046 cdb_sgcount++; 1047 } else { 1048 pdma_sg->length = tmplength | IS_SG64_ADDR; 1049 sg64s_size += sizeof(struct SG64ENTRY); 1050 psge += sizeof(struct SG64ENTRY); 1051 break; 1052 } 1053 } 1054 arccdbsize += sg64s_size; 1055 } 1056 cdb_sgcount++; 1057 } 1058 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1059 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1060 if( arccdbsize > 256) { 1061 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1062 } 1063 } else { 1064 arcmsr_cdb->DataLength = 0; 1065 } 1066 srb->arc_cdb_size = arccdbsize; 1067 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1068 } 1069 /* 1070 ************************************************************************** 1071 ************************************************************************** 1072 */ 1073 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1074 { 1075 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1076 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1077 1078 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1079 atomic_add_int(&acb->srboutstandingcount, 1); 1080 srb->srb_state = ARCMSR_SRB_START; 1081 1082 switch (acb->adapter_type) { 1083 case ACB_ADAPTER_TYPE_A: { 1084 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1085 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1086 } else { 1087 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1088 } 1089 } 1090 break; 1091 case ACB_ADAPTER_TYPE_B: { 1092 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1093 int ending_index, index; 1094 1095 index = phbbmu->postq_index; 1096 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1097 phbbmu->post_qbuffer[ending_index] = 0; 1098 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1099 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1100 } else { 1101 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1102 } 1103 index++; 1104 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1105 phbbmu->postq_index = index; 1106 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1107 } 1108 break; 1109 case ACB_ADAPTER_TYPE_C: { 1110 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1111 1112 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1113 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1114 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1115 if(cdb_phyaddr_hi32) 1116 { 1117 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1118 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1119 } 1120 else 1121 { 1122 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1123 } 1124 } 1125 break; 1126 case ACB_ADAPTER_TYPE_D: { 1127 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1128 u_int16_t index_stripped; 1129 u_int16_t postq_index; 1130 struct InBound_SRB *pinbound_srb; 1131 1132 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1133 postq_index = phbdmu->postq_index; 1134 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1135 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1136 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1137 pinbound_srb->length = srb->arc_cdb_size >> 2; 1138 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1139 if (postq_index & 0x4000) { 1140 index_stripped = postq_index & 0xFF; 1141 index_stripped += 1; 1142 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1143 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1144 } else { 1145 index_stripped = postq_index; 1146 index_stripped += 1; 1147 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1148 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1149 } 1150 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1151 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1152 } 1153 break; 1154 case ACB_ADAPTER_TYPE_E: { 1155 u_int32_t ccb_post_stamp, arc_cdb_size; 1156 1157 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1158 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1159 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1160 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1161 } 1162 break; 1163 case ACB_ADAPTER_TYPE_F: { 1164 u_int32_t ccb_post_stamp, arc_cdb_size; 1165 1166 if (srb->arc_cdb_size <= 0x300) 1167 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1168 else { 1169 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1170 if (arc_cdb_size > 0xF) 1171 arc_cdb_size = 0xF; 1172 arc_cdb_size = (arc_cdb_size << 1) | 1; 1173 } 1174 ccb_post_stamp = (srb->smid | arc_cdb_size); 1175 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1176 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1177 } 1178 break; 1179 } 1180 } 1181 /* 1182 ************************************************************************ 1183 ************************************************************************ 1184 */ 1185 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1186 { 1187 struct QBUFFER *qbuffer=NULL; 1188 1189 switch (acb->adapter_type) { 1190 case ACB_ADAPTER_TYPE_A: { 1191 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1192 1193 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1194 } 1195 break; 1196 case ACB_ADAPTER_TYPE_B: { 1197 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1198 1199 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1200 } 1201 break; 1202 case ACB_ADAPTER_TYPE_C: { 1203 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1204 1205 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1206 } 1207 break; 1208 case ACB_ADAPTER_TYPE_D: { 1209 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1210 1211 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1212 } 1213 break; 1214 case ACB_ADAPTER_TYPE_E: { 1215 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1216 1217 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1218 } 1219 break; 1220 case ACB_ADAPTER_TYPE_F: 1221 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1222 break; 1223 } 1224 return(qbuffer); 1225 } 1226 /* 1227 ************************************************************************ 1228 ************************************************************************ 1229 */ 1230 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1231 { 1232 struct QBUFFER *qbuffer = NULL; 1233 1234 switch (acb->adapter_type) { 1235 case ACB_ADAPTER_TYPE_A: { 1236 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1237 1238 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1239 } 1240 break; 1241 case ACB_ADAPTER_TYPE_B: { 1242 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1243 1244 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1245 } 1246 break; 1247 case ACB_ADAPTER_TYPE_C: { 1248 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1249 1250 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1251 } 1252 break; 1253 case ACB_ADAPTER_TYPE_D: { 1254 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1255 1256 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1257 } 1258 break; 1259 case ACB_ADAPTER_TYPE_E: { 1260 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1261 1262 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1263 } 1264 break; 1265 case ACB_ADAPTER_TYPE_F: 1266 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1267 break; 1268 } 1269 return(qbuffer); 1270 } 1271 /* 1272 ************************************************************************** 1273 ************************************************************************** 1274 */ 1275 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1276 { 1277 switch (acb->adapter_type) { 1278 case ACB_ADAPTER_TYPE_A: { 1279 /* let IOP know data has been read */ 1280 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1281 } 1282 break; 1283 case ACB_ADAPTER_TYPE_B: { 1284 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1285 /* let IOP know data has been read */ 1286 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1287 } 1288 break; 1289 case ACB_ADAPTER_TYPE_C: { 1290 /* let IOP know data has been read */ 1291 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1292 } 1293 break; 1294 case ACB_ADAPTER_TYPE_D: { 1295 /* let IOP know data has been read */ 1296 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1297 } 1298 break; 1299 case ACB_ADAPTER_TYPE_E: 1300 case ACB_ADAPTER_TYPE_F: { 1301 /* let IOP know data has been read */ 1302 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1303 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1304 } 1305 break; 1306 } 1307 } 1308 /* 1309 ************************************************************************** 1310 ************************************************************************** 1311 */ 1312 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1313 { 1314 switch (acb->adapter_type) { 1315 case ACB_ADAPTER_TYPE_A: { 1316 /* 1317 ** push inbound doorbell tell iop, driver data write ok 1318 ** and wait reply on next hwinterrupt for next Qbuffer post 1319 */ 1320 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1321 } 1322 break; 1323 case ACB_ADAPTER_TYPE_B: { 1324 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1325 /* 1326 ** push inbound doorbell tell iop, driver data write ok 1327 ** and wait reply on next hwinterrupt for next Qbuffer post 1328 */ 1329 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1330 } 1331 break; 1332 case ACB_ADAPTER_TYPE_C: { 1333 /* 1334 ** push inbound doorbell tell iop, driver data write ok 1335 ** and wait reply on next hwinterrupt for next Qbuffer post 1336 */ 1337 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1338 } 1339 break; 1340 case ACB_ADAPTER_TYPE_D: { 1341 /* 1342 ** push inbound doorbell tell iop, driver data write ok 1343 ** and wait reply on next hwinterrupt for next Qbuffer post 1344 */ 1345 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1346 } 1347 break; 1348 case ACB_ADAPTER_TYPE_E: 1349 case ACB_ADAPTER_TYPE_F: { 1350 /* 1351 ** push inbound doorbell tell iop, driver data write ok 1352 ** and wait reply on next hwinterrupt for next Qbuffer post 1353 */ 1354 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1355 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1356 } 1357 break; 1358 } 1359 } 1360 /* 1361 ************************************************************************ 1362 ************************************************************************ 1363 */ 1364 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1365 { 1366 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1367 CHIP_REG_WRITE32(HBA_MessageUnit, 1368 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1369 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1370 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1371 , acb->pci_unit); 1372 } 1373 } 1374 /* 1375 ************************************************************************ 1376 ************************************************************************ 1377 */ 1378 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1379 { 1380 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1381 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1382 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1383 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1384 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1385 , acb->pci_unit); 1386 } 1387 } 1388 /* 1389 ************************************************************************ 1390 ************************************************************************ 1391 */ 1392 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1393 { 1394 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1395 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1396 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1397 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1398 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1399 } 1400 } 1401 /* 1402 ************************************************************************ 1403 ************************************************************************ 1404 */ 1405 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1406 { 1407 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1408 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1409 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1410 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1411 } 1412 } 1413 /* 1414 ************************************************************************ 1415 ************************************************************************ 1416 */ 1417 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1418 { 1419 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1420 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1421 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1422 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1423 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1424 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1425 } 1426 } 1427 /* 1428 ************************************************************************ 1429 ************************************************************************ 1430 */ 1431 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1432 { 1433 switch (acb->adapter_type) { 1434 case ACB_ADAPTER_TYPE_A: { 1435 arcmsr_stop_hba_bgrb(acb); 1436 } 1437 break; 1438 case ACB_ADAPTER_TYPE_B: { 1439 arcmsr_stop_hbb_bgrb(acb); 1440 } 1441 break; 1442 case ACB_ADAPTER_TYPE_C: { 1443 arcmsr_stop_hbc_bgrb(acb); 1444 } 1445 break; 1446 case ACB_ADAPTER_TYPE_D: { 1447 arcmsr_stop_hbd_bgrb(acb); 1448 } 1449 break; 1450 case ACB_ADAPTER_TYPE_E: 1451 case ACB_ADAPTER_TYPE_F: { 1452 arcmsr_stop_hbe_bgrb(acb); 1453 } 1454 break; 1455 } 1456 } 1457 /* 1458 ************************************************************************ 1459 ************************************************************************ 1460 */ 1461 static void arcmsr_poll(struct cam_sim *psim) 1462 { 1463 struct AdapterControlBlock *acb; 1464 int mutex; 1465 1466 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1467 mutex = mtx_owned(&acb->isr_lock); 1468 if( mutex == 0 ) 1469 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1470 arcmsr_interrupt(acb); 1471 if( mutex == 0 ) 1472 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1473 } 1474 /* 1475 ************************************************************************** 1476 ************************************************************************** 1477 */ 1478 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1479 struct QBUFFER *prbuffer) { 1480 u_int8_t *pQbuffer; 1481 u_int8_t *buf1 = NULL; 1482 u_int32_t *iop_data, *buf2 = NULL; 1483 u_int32_t iop_len, data_len; 1484 1485 iop_data = (u_int32_t *)prbuffer->data; 1486 iop_len = (u_int32_t)prbuffer->data_len; 1487 if ( iop_len > 0 ) 1488 { 1489 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1490 buf2 = (u_int32_t *)buf1; 1491 if( buf1 == NULL) 1492 return (0); 1493 data_len = iop_len; 1494 while(data_len >= 4) 1495 { 1496 *buf2++ = *iop_data++; 1497 data_len -= 4; 1498 } 1499 if(data_len) 1500 *buf2 = *iop_data; 1501 buf2 = (u_int32_t *)buf1; 1502 } 1503 while (iop_len > 0) { 1504 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1505 *pQbuffer = *buf1; 1506 acb->rqbuf_lastindex++; 1507 /* if last, index number set it to 0 */ 1508 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1509 buf1++; 1510 iop_len--; 1511 } 1512 if(buf2) 1513 free( (u_int8_t *)buf2, M_DEVBUF); 1514 /* let IOP know data has been read */ 1515 arcmsr_iop_message_read(acb); 1516 return (1); 1517 } 1518 /* 1519 ************************************************************************** 1520 ************************************************************************** 1521 */ 1522 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1523 struct QBUFFER *prbuffer) { 1524 u_int8_t *pQbuffer; 1525 u_int8_t *iop_data; 1526 u_int32_t iop_len; 1527 1528 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1529 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1530 } 1531 iop_data = (u_int8_t *)prbuffer->data; 1532 iop_len = (u_int32_t)prbuffer->data_len; 1533 while (iop_len > 0) { 1534 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1535 *pQbuffer = *iop_data; 1536 acb->rqbuf_lastindex++; 1537 /* if last, index number set it to 0 */ 1538 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1539 iop_data++; 1540 iop_len--; 1541 } 1542 /* let IOP know data has been read */ 1543 arcmsr_iop_message_read(acb); 1544 return (1); 1545 } 1546 /* 1547 ************************************************************************** 1548 ************************************************************************** 1549 */ 1550 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1551 { 1552 struct QBUFFER *prbuffer; 1553 int my_empty_len; 1554 1555 /*check this iop data if overflow my rqbuffer*/ 1556 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1557 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1558 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1559 (ARCMSR_MAX_QBUFFER-1); 1560 if(my_empty_len >= prbuffer->data_len) { 1561 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1562 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1563 } else { 1564 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1565 } 1566 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1567 } 1568 /* 1569 ********************************************************************** 1570 ********************************************************************** 1571 */ 1572 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1573 { 1574 u_int8_t *pQbuffer; 1575 struct QBUFFER *pwbuffer; 1576 u_int8_t *buf1 = NULL; 1577 u_int32_t *iop_data, *buf2 = NULL; 1578 u_int32_t allxfer_len = 0, data_len; 1579 1580 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1581 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1582 buf2 = (u_int32_t *)buf1; 1583 if( buf1 == NULL) 1584 return; 1585 1586 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1587 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1588 iop_data = (u_int32_t *)pwbuffer->data; 1589 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1590 && (allxfer_len < 124)) { 1591 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1592 *buf1 = *pQbuffer; 1593 acb->wqbuf_firstindex++; 1594 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1595 buf1++; 1596 allxfer_len++; 1597 } 1598 pwbuffer->data_len = allxfer_len; 1599 data_len = allxfer_len; 1600 buf1 = (u_int8_t *)buf2; 1601 while(data_len >= 4) 1602 { 1603 *iop_data++ = *buf2++; 1604 data_len -= 4; 1605 } 1606 if(data_len) 1607 *iop_data = *buf2; 1608 free( buf1, M_DEVBUF); 1609 arcmsr_iop_message_wrote(acb); 1610 } 1611 } 1612 /* 1613 ********************************************************************** 1614 ********************************************************************** 1615 */ 1616 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1617 { 1618 u_int8_t *pQbuffer; 1619 struct QBUFFER *pwbuffer; 1620 u_int8_t *iop_data; 1621 int32_t allxfer_len=0; 1622 1623 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1624 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1625 return; 1626 } 1627 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1628 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1629 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1630 iop_data = (u_int8_t *)pwbuffer->data; 1631 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1632 && (allxfer_len < 124)) { 1633 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1634 *iop_data = *pQbuffer; 1635 acb->wqbuf_firstindex++; 1636 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1637 iop_data++; 1638 allxfer_len++; 1639 } 1640 pwbuffer->data_len = allxfer_len; 1641 arcmsr_iop_message_wrote(acb); 1642 } 1643 } 1644 /* 1645 ************************************************************************** 1646 ************************************************************************** 1647 */ 1648 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1649 { 1650 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1651 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1652 /* 1653 ***************************************************************** 1654 ** check if there are any mail packages from user space program 1655 ** in my post bag, now is the time to send them into Areca's firmware 1656 ***************************************************************** 1657 */ 1658 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1659 arcmsr_Write_data_2iop_wqbuffer(acb); 1660 } 1661 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1662 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1663 } 1664 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1665 } 1666 /* 1667 ************************************************************************** 1668 ************************************************************************** 1669 */ 1670 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1671 { 1672 /* 1673 if (ccb->ccb_h.status != CAM_REQ_CMP) 1674 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1675 "failure status=%x\n", ccb->ccb_h.target_id, 1676 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1677 else 1678 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1679 */ 1680 xpt_free_path(ccb->ccb_h.path); 1681 xpt_free_ccb(ccb); 1682 } 1683 1684 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1685 { 1686 struct cam_path *path; 1687 union ccb *ccb; 1688 1689 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1690 return; 1691 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1692 { 1693 xpt_free_ccb(ccb); 1694 return; 1695 } 1696 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1697 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1698 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1699 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1700 ccb->crcn.flags = CAM_FLAG_NONE; 1701 xpt_action(ccb); 1702 } 1703 1704 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1705 { 1706 struct CommandControlBlock *srb; 1707 u_int32_t intmask_org; 1708 int i; 1709 1710 /* disable all outbound interrupts */ 1711 intmask_org = arcmsr_disable_allintr(acb); 1712 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1713 { 1714 srb = acb->psrb_pool[i]; 1715 if (srb->srb_state == ARCMSR_SRB_START) 1716 { 1717 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1718 { 1719 srb->srb_state = ARCMSR_SRB_ABORTED; 1720 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1721 arcmsr_srb_complete(srb, 1); 1722 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1723 } 1724 } 1725 } 1726 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1727 arcmsr_enable_allintr(acb, intmask_org); 1728 } 1729 /* 1730 ************************************************************************** 1731 ************************************************************************** 1732 */ 1733 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1734 u_int32_t devicemap; 1735 u_int32_t target, lun; 1736 u_int32_t deviceMapCurrent[4]={0}; 1737 u_int8_t *pDevMap; 1738 1739 switch (acb->adapter_type) { 1740 case ACB_ADAPTER_TYPE_A: 1741 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1742 for (target = 0; target < 4; target++) 1743 { 1744 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1745 devicemap += 4; 1746 } 1747 break; 1748 1749 case ACB_ADAPTER_TYPE_B: 1750 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1751 for (target = 0; target < 4; target++) 1752 { 1753 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1754 devicemap += 4; 1755 } 1756 break; 1757 1758 case ACB_ADAPTER_TYPE_C: 1759 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1760 for (target = 0; target < 4; target++) 1761 { 1762 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1763 devicemap += 4; 1764 } 1765 break; 1766 case ACB_ADAPTER_TYPE_D: 1767 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1768 for (target = 0; target < 4; target++) 1769 { 1770 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1771 devicemap += 4; 1772 } 1773 break; 1774 case ACB_ADAPTER_TYPE_E: 1775 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1776 for (target = 0; target < 4; target++) 1777 { 1778 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1779 devicemap += 4; 1780 } 1781 break; 1782 case ACB_ADAPTER_TYPE_F: 1783 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1784 for (target = 0; target < 4; target++) 1785 { 1786 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1787 devicemap += 1; 1788 } 1789 break; 1790 } 1791 1792 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1793 { 1794 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1795 } 1796 /* 1797 ** adapter posted CONFIG message 1798 ** copy the new map, note if there are differences with the current map 1799 */ 1800 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1801 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1802 { 1803 if (*pDevMap != acb->device_map[target]) 1804 { 1805 u_int8_t difference, bit_check; 1806 1807 difference = *pDevMap ^ acb->device_map[target]; 1808 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1809 { 1810 bit_check = (1 << lun); /*check bit from 0....31*/ 1811 if(difference & bit_check) 1812 { 1813 if(acb->device_map[target] & bit_check) 1814 {/* unit departed */ 1815 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1816 arcmsr_abort_dr_ccbs(acb, target, lun); 1817 arcmsr_rescan_lun(acb, target, lun); 1818 acb->devstate[target][lun] = ARECA_RAID_GONE; 1819 } 1820 else 1821 {/* unit arrived */ 1822 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1823 arcmsr_rescan_lun(acb, target, lun); 1824 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1825 } 1826 } 1827 } 1828 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1829 acb->device_map[target] = *pDevMap; 1830 } 1831 pDevMap++; 1832 } 1833 } 1834 /* 1835 ************************************************************************** 1836 ************************************************************************** 1837 */ 1838 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1839 u_int32_t outbound_message; 1840 1841 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1842 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1843 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1844 arcmsr_dr_handle( acb ); 1845 } 1846 /* 1847 ************************************************************************** 1848 ************************************************************************** 1849 */ 1850 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1851 u_int32_t outbound_message; 1852 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1853 1854 /* clear interrupts */ 1855 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1856 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1857 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1858 arcmsr_dr_handle( acb ); 1859 } 1860 /* 1861 ************************************************************************** 1862 ************************************************************************** 1863 */ 1864 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1865 u_int32_t outbound_message; 1866 1867 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1868 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1869 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1870 arcmsr_dr_handle( acb ); 1871 } 1872 /* 1873 ************************************************************************** 1874 ************************************************************************** 1875 */ 1876 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1877 u_int32_t outbound_message; 1878 1879 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1880 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1881 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1882 arcmsr_dr_handle( acb ); 1883 } 1884 /* 1885 ************************************************************************** 1886 ************************************************************************** 1887 */ 1888 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1889 u_int32_t outbound_message; 1890 1891 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1892 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1893 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1894 else 1895 outbound_message = acb->msgcode_rwbuffer[0]; 1896 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1897 arcmsr_dr_handle( acb ); 1898 } 1899 /* 1900 ************************************************************************** 1901 ************************************************************************** 1902 */ 1903 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1904 { 1905 u_int32_t doorbell_status; 1906 1907 /* 1908 ******************************************************************* 1909 ** Maybe here we need to check wrqbuffer_lock is lock or not 1910 ** DOORBELL: din! don! 1911 ** check if there are any mail need to pack from firmware 1912 ******************************************************************* 1913 */ 1914 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1915 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1916 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1917 arcmsr_iop2drv_data_wrote_handle(acb); 1918 } 1919 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1920 arcmsr_iop2drv_data_read_handle(acb); 1921 } 1922 } 1923 /* 1924 ************************************************************************** 1925 ************************************************************************** 1926 */ 1927 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1928 { 1929 u_int32_t doorbell_status; 1930 1931 /* 1932 ******************************************************************* 1933 ** Maybe here we need to check wrqbuffer_lock is lock or not 1934 ** DOORBELL: din! don! 1935 ** check if there are any mail need to pack from firmware 1936 ******************************************************************* 1937 */ 1938 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1939 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1940 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1941 arcmsr_iop2drv_data_wrote_handle(acb); 1942 } 1943 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1944 arcmsr_iop2drv_data_read_handle(acb); 1945 } 1946 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1947 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1948 } 1949 } 1950 /* 1951 ************************************************************************** 1952 ************************************************************************** 1953 */ 1954 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1955 { 1956 u_int32_t doorbell_status; 1957 1958 /* 1959 ******************************************************************* 1960 ** Maybe here we need to check wrqbuffer_lock is lock or not 1961 ** DOORBELL: din! don! 1962 ** check if there are any mail need to pack from firmware 1963 ******************************************************************* 1964 */ 1965 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1966 if(doorbell_status) 1967 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1968 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1969 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1970 arcmsr_iop2drv_data_wrote_handle(acb); 1971 } 1972 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1973 arcmsr_iop2drv_data_read_handle(acb); 1974 } 1975 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1976 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1977 } 1978 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1979 if(doorbell_status) 1980 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1981 } 1982 } 1983 /* 1984 ************************************************************************** 1985 ************************************************************************** 1986 */ 1987 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 1988 { 1989 u_int32_t doorbell_status, in_doorbell; 1990 1991 /* 1992 ******************************************************************* 1993 ** Maybe here we need to check wrqbuffer_lock is lock or not 1994 ** DOORBELL: din! don! 1995 ** check if there are any mail need to pack from firmware 1996 ******************************************************************* 1997 */ 1998 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 1999 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2000 doorbell_status = in_doorbell ^ acb->in_doorbell; 2001 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2002 arcmsr_iop2drv_data_wrote_handle(acb); 2003 } 2004 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2005 arcmsr_iop2drv_data_read_handle(acb); 2006 } 2007 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2008 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2009 } 2010 acb->in_doorbell = in_doorbell; 2011 } 2012 /* 2013 ************************************************************************** 2014 ************************************************************************** 2015 */ 2016 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb) 2017 { 2018 u_int32_t doorbell_status, in_doorbell; 2019 2020 /* 2021 ******************************************************************* 2022 ** Maybe here we need to check wrqbuffer_lock is lock or not 2023 ** DOORBELL: din! don! 2024 ** check if there are any mail need to pack from firmware 2025 ******************************************************************* 2026 */ 2027 while(1) { 2028 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2029 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF)) 2030 break; 2031 } 2032 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2033 doorbell_status = in_doorbell ^ acb->in_doorbell; 2034 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2035 arcmsr_iop2drv_data_wrote_handle(acb); 2036 } 2037 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2038 arcmsr_iop2drv_data_read_handle(acb); 2039 } 2040 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2041 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2042 } 2043 acb->in_doorbell = in_doorbell; 2044 } 2045 /* 2046 ************************************************************************** 2047 ************************************************************************** 2048 */ 2049 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2050 { 2051 u_int32_t flag_srb; 2052 u_int16_t error; 2053 2054 /* 2055 ***************************************************************************** 2056 ** areca cdb command done 2057 ***************************************************************************** 2058 */ 2059 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2060 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2061 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2062 0, outbound_queueport)) != 0xFFFFFFFF) { 2063 /* check if command done with no error*/ 2064 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2065 arcmsr_drain_donequeue(acb, flag_srb, error); 2066 } /*drain reply FIFO*/ 2067 } 2068 /* 2069 ************************************************************************** 2070 ************************************************************************** 2071 */ 2072 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2073 { 2074 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2075 u_int32_t flag_srb; 2076 int index; 2077 u_int16_t error; 2078 2079 /* 2080 ***************************************************************************** 2081 ** areca cdb command done 2082 ***************************************************************************** 2083 */ 2084 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2085 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2086 index = phbbmu->doneq_index; 2087 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2088 phbbmu->done_qbuffer[index] = 0; 2089 index++; 2090 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2091 phbbmu->doneq_index = index; 2092 /* check if command done with no error*/ 2093 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2094 arcmsr_drain_donequeue(acb, flag_srb, error); 2095 } /*drain reply FIFO*/ 2096 } 2097 /* 2098 ************************************************************************** 2099 ************************************************************************** 2100 */ 2101 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2102 { 2103 u_int32_t flag_srb,throttling = 0; 2104 u_int16_t error; 2105 2106 /* 2107 ***************************************************************************** 2108 ** areca cdb command done 2109 ***************************************************************************** 2110 */ 2111 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2112 do { 2113 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2114 if (flag_srb == 0xFFFFFFFF) 2115 break; 2116 /* check if command done with no error*/ 2117 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2118 arcmsr_drain_donequeue(acb, flag_srb, error); 2119 throttling++; 2120 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2121 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2122 throttling = 0; 2123 } 2124 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2125 } 2126 /* 2127 ********************************************************************** 2128 ** 2129 ********************************************************************** 2130 */ 2131 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2132 { 2133 uint16_t doneq_index, index_stripped; 2134 2135 doneq_index = phbdmu->doneq_index; 2136 if (doneq_index & 0x4000) { 2137 index_stripped = doneq_index & 0xFF; 2138 index_stripped += 1; 2139 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2140 phbdmu->doneq_index = index_stripped ? 2141 (index_stripped | 0x4000) : index_stripped; 2142 } else { 2143 index_stripped = doneq_index; 2144 index_stripped += 1; 2145 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2146 phbdmu->doneq_index = index_stripped ? 2147 index_stripped : (index_stripped | 0x4000); 2148 } 2149 return (phbdmu->doneq_index); 2150 } 2151 /* 2152 ************************************************************************** 2153 ************************************************************************** 2154 */ 2155 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2156 { 2157 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2158 u_int32_t outbound_write_pointer; 2159 u_int32_t addressLow; 2160 uint16_t doneq_index; 2161 u_int16_t error; 2162 /* 2163 ***************************************************************************** 2164 ** areca cdb command done 2165 ***************************************************************************** 2166 */ 2167 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2168 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2169 return; 2170 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2172 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2173 doneq_index = phbdmu->doneq_index; 2174 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2175 doneq_index = arcmsr_get_doneq_index(phbdmu); 2176 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2177 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2178 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2179 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2180 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2181 } 2182 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2183 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2184 } 2185 /* 2186 ************************************************************************** 2187 ************************************************************************** 2188 */ 2189 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2190 { 2191 u_int16_t error; 2192 uint32_t doneq_index; 2193 uint16_t cmdSMID; 2194 2195 /* 2196 ***************************************************************************** 2197 ** areca cdb command done 2198 ***************************************************************************** 2199 */ 2200 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2201 doneq_index = acb->doneq_index; 2202 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2203 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2204 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2205 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2206 doneq_index++; 2207 if (doneq_index >= acb->completionQ_entry) 2208 doneq_index = 0; 2209 } 2210 acb->doneq_index = doneq_index; 2211 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2212 } 2213 2214 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2215 { 2216 uint16_t error; 2217 uint32_t doneq_index; 2218 uint16_t cmdSMID; 2219 2220 /* 2221 ***************************************************************************** 2222 ** areca cdb command done 2223 ***************************************************************************** 2224 */ 2225 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2226 doneq_index = acb->doneq_index; 2227 while (1) { 2228 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2229 if (cmdSMID == 0xffff) 2230 break; 2231 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2232 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2233 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2234 doneq_index++; 2235 if (doneq_index >= acb->completionQ_entry) 2236 doneq_index = 0; 2237 } 2238 acb->doneq_index = doneq_index; 2239 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2240 } 2241 2242 /* 2243 ********************************************************************** 2244 ********************************************************************** 2245 */ 2246 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2247 { 2248 u_int32_t outbound_intStatus; 2249 /* 2250 ********************************************* 2251 ** check outbound intstatus 2252 ********************************************* 2253 */ 2254 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2255 if(!outbound_intStatus) { 2256 /*it must be share irq*/ 2257 return; 2258 } 2259 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2260 /* MU doorbell interrupts*/ 2261 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2262 arcmsr_hba_doorbell_isr(acb); 2263 } 2264 /* MU post queue interrupts*/ 2265 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2266 arcmsr_hba_postqueue_isr(acb); 2267 } 2268 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2269 arcmsr_hba_message_isr(acb); 2270 } 2271 } 2272 /* 2273 ********************************************************************** 2274 ********************************************************************** 2275 */ 2276 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2277 { 2278 u_int32_t outbound_doorbell; 2279 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2280 /* 2281 ********************************************* 2282 ** check outbound intstatus 2283 ********************************************* 2284 */ 2285 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2286 if(!outbound_doorbell) { 2287 /*it must be share irq*/ 2288 return; 2289 } 2290 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2291 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2292 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2293 /* MU ioctl transfer doorbell interrupts*/ 2294 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2295 arcmsr_iop2drv_data_wrote_handle(acb); 2296 } 2297 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2298 arcmsr_iop2drv_data_read_handle(acb); 2299 } 2300 /* MU post queue interrupts*/ 2301 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2302 arcmsr_hbb_postqueue_isr(acb); 2303 } 2304 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2305 arcmsr_hbb_message_isr(acb); 2306 } 2307 } 2308 /* 2309 ********************************************************************** 2310 ********************************************************************** 2311 */ 2312 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2313 { 2314 u_int32_t host_interrupt_status; 2315 /* 2316 ********************************************* 2317 ** check outbound intstatus 2318 ********************************************* 2319 */ 2320 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2321 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2322 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2323 if(!host_interrupt_status) { 2324 /*it must be share irq*/ 2325 return; 2326 } 2327 do { 2328 /* MU doorbell interrupts*/ 2329 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2330 arcmsr_hbc_doorbell_isr(acb); 2331 } 2332 /* MU post queue interrupts*/ 2333 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2334 arcmsr_hbc_postqueue_isr(acb); 2335 } 2336 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2337 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2338 } 2339 /* 2340 ********************************************************************** 2341 ********************************************************************** 2342 */ 2343 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2344 { 2345 u_int32_t host_interrupt_status; 2346 u_int32_t intmask_org; 2347 /* 2348 ********************************************* 2349 ** check outbound intstatus 2350 ********************************************* 2351 */ 2352 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2353 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2354 /*it must be share irq*/ 2355 return; 2356 } 2357 /* disable outbound interrupt */ 2358 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2359 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2360 /* MU doorbell interrupts*/ 2361 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2362 arcmsr_hbd_doorbell_isr(acb); 2363 } 2364 /* MU post queue interrupts*/ 2365 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2366 arcmsr_hbd_postqueue_isr(acb); 2367 } 2368 /* enable all outbound interrupt */ 2369 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2370 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2371 } 2372 /* 2373 ********************************************************************** 2374 ********************************************************************** 2375 */ 2376 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2377 { 2378 u_int32_t host_interrupt_status; 2379 /* 2380 ********************************************* 2381 ** check outbound intstatus 2382 ********************************************* 2383 */ 2384 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2385 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2386 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2387 if(!host_interrupt_status) { 2388 /*it must be share irq*/ 2389 return; 2390 } 2391 do { 2392 /* MU doorbell interrupts*/ 2393 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2394 arcmsr_hbe_doorbell_isr(acb); 2395 } 2396 /* MU post queue interrupts*/ 2397 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2398 arcmsr_hbe_postqueue_isr(acb); 2399 } 2400 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2401 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2402 } 2403 2404 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2405 { 2406 u_int32_t host_interrupt_status; 2407 /* 2408 ********************************************* 2409 ** check outbound intstatus 2410 ********************************************* 2411 */ 2412 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2413 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2414 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2415 if(!host_interrupt_status) { 2416 /*it must be share irq*/ 2417 return; 2418 } 2419 do { 2420 /* MU doorbell interrupts*/ 2421 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2422 arcmsr_hbf_doorbell_isr(acb); 2423 } 2424 /* MU post queue interrupts*/ 2425 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2426 arcmsr_hbf_postqueue_isr(acb); 2427 } 2428 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2429 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2430 } 2431 /* 2432 ****************************************************************************** 2433 ****************************************************************************** 2434 */ 2435 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2436 { 2437 switch (acb->adapter_type) { 2438 case ACB_ADAPTER_TYPE_A: 2439 arcmsr_handle_hba_isr(acb); 2440 break; 2441 case ACB_ADAPTER_TYPE_B: 2442 arcmsr_handle_hbb_isr(acb); 2443 break; 2444 case ACB_ADAPTER_TYPE_C: 2445 arcmsr_handle_hbc_isr(acb); 2446 break; 2447 case ACB_ADAPTER_TYPE_D: 2448 arcmsr_handle_hbd_isr(acb); 2449 break; 2450 case ACB_ADAPTER_TYPE_E: 2451 arcmsr_handle_hbe_isr(acb); 2452 break; 2453 case ACB_ADAPTER_TYPE_F: 2454 arcmsr_handle_hbf_isr(acb); 2455 break; 2456 default: 2457 printf("arcmsr%d: interrupt service," 2458 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2459 break; 2460 } 2461 } 2462 /* 2463 ********************************************************************** 2464 ********************************************************************** 2465 */ 2466 static void arcmsr_intr_handler(void *arg) 2467 { 2468 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2469 2470 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2471 arcmsr_interrupt(acb); 2472 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2473 } 2474 /* 2475 ****************************************************************************** 2476 ****************************************************************************** 2477 */ 2478 static void arcmsr_polling_devmap(void *arg) 2479 { 2480 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2481 switch (acb->adapter_type) { 2482 case ACB_ADAPTER_TYPE_A: 2483 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2484 break; 2485 2486 case ACB_ADAPTER_TYPE_B: { 2487 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2488 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2489 } 2490 break; 2491 2492 case ACB_ADAPTER_TYPE_C: 2493 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2494 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2495 break; 2496 2497 case ACB_ADAPTER_TYPE_D: 2498 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2499 break; 2500 2501 case ACB_ADAPTER_TYPE_E: 2502 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2503 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2504 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2505 break; 2506 2507 case ACB_ADAPTER_TYPE_F: { 2508 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2509 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2510 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2511 goto nxt6s; 2512 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2513 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2514 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2515 break; 2516 } 2517 } 2518 nxt6s: 2519 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2520 { 2521 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2522 } 2523 } 2524 2525 /* 2526 ******************************************************************************* 2527 ** 2528 ******************************************************************************* 2529 */ 2530 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2531 { 2532 u_int32_t intmask_org; 2533 2534 if(acb != NULL) { 2535 /* stop adapter background rebuild */ 2536 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2537 intmask_org = arcmsr_disable_allintr(acb); 2538 arcmsr_stop_adapter_bgrb(acb); 2539 arcmsr_flush_adapter_cache(acb); 2540 arcmsr_enable_allintr(acb, intmask_org); 2541 } 2542 } 2543 } 2544 /* 2545 *********************************************************************** 2546 ** 2547 ************************************************************************ 2548 */ 2549 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2550 { 2551 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2552 u_int32_t retvalue = EINVAL; 2553 2554 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2555 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2556 return retvalue; 2557 } 2558 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2559 switch(ioctl_cmd) { 2560 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2561 u_int8_t *pQbuffer; 2562 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2563 u_int32_t allxfer_len=0; 2564 2565 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2566 && (allxfer_len < 1031)) { 2567 /*copy READ QBUFFER to srb*/ 2568 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2569 *ptmpQbuffer = *pQbuffer; 2570 acb->rqbuf_firstindex++; 2571 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2572 /*if last index number set it to 0 */ 2573 ptmpQbuffer++; 2574 allxfer_len++; 2575 } 2576 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2577 struct QBUFFER *prbuffer; 2578 2579 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2580 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2581 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2582 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2583 } 2584 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2585 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2586 retvalue = ARCMSR_MESSAGE_SUCCESS; 2587 } 2588 break; 2589 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2590 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2591 u_int8_t *pQbuffer; 2592 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2593 2594 user_len = pcmdmessagefld->cmdmessage.Length; 2595 /*check if data xfer length of this request will overflow my array qbuffer */ 2596 wqbuf_lastindex = acb->wqbuf_lastindex; 2597 wqbuf_firstindex = acb->wqbuf_firstindex; 2598 if(wqbuf_lastindex != wqbuf_firstindex) { 2599 arcmsr_Write_data_2iop_wqbuffer(acb); 2600 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2601 } else { 2602 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2603 (ARCMSR_MAX_QBUFFER - 1); 2604 if(my_empty_len >= user_len) { 2605 while(user_len > 0) { 2606 /*copy srb data to wqbuffer*/ 2607 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2608 *pQbuffer = *ptmpuserbuffer; 2609 acb->wqbuf_lastindex++; 2610 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2611 /*if last index number set it to 0 */ 2612 ptmpuserbuffer++; 2613 user_len--; 2614 } 2615 /*post fist Qbuffer*/ 2616 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2617 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2618 arcmsr_Write_data_2iop_wqbuffer(acb); 2619 } 2620 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2621 } else { 2622 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2623 } 2624 } 2625 retvalue = ARCMSR_MESSAGE_SUCCESS; 2626 } 2627 break; 2628 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2629 u_int8_t *pQbuffer = acb->rqbuffer; 2630 2631 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2632 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2633 arcmsr_iop_message_read(acb); 2634 /*signature, let IOP know data has been readed */ 2635 } 2636 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2637 acb->rqbuf_firstindex = 0; 2638 acb->rqbuf_lastindex = 0; 2639 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2640 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2641 retvalue = ARCMSR_MESSAGE_SUCCESS; 2642 } 2643 break; 2644 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2645 { 2646 u_int8_t *pQbuffer = acb->wqbuffer; 2647 2648 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2649 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2650 arcmsr_iop_message_read(acb); 2651 /*signature, let IOP know data has been readed */ 2652 } 2653 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2654 acb->wqbuf_firstindex = 0; 2655 acb->wqbuf_lastindex = 0; 2656 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2657 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2658 retvalue = ARCMSR_MESSAGE_SUCCESS; 2659 } 2660 break; 2661 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2662 u_int8_t *pQbuffer; 2663 2664 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2665 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2666 arcmsr_iop_message_read(acb); 2667 /*signature, let IOP know data has been readed */ 2668 } 2669 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2670 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2671 |ACB_F_MESSAGE_WQBUFFER_READ); 2672 acb->rqbuf_firstindex = 0; 2673 acb->rqbuf_lastindex = 0; 2674 acb->wqbuf_firstindex = 0; 2675 acb->wqbuf_lastindex = 0; 2676 pQbuffer = acb->rqbuffer; 2677 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2678 pQbuffer = acb->wqbuffer; 2679 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2680 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2681 retvalue = ARCMSR_MESSAGE_SUCCESS; 2682 } 2683 break; 2684 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2685 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2686 retvalue = ARCMSR_MESSAGE_SUCCESS; 2687 } 2688 break; 2689 case ARCMSR_MESSAGE_SAY_HELLO: { 2690 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2691 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2692 2693 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2694 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2695 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2696 return ENOIOCTL; 2697 } 2698 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2699 retvalue = ARCMSR_MESSAGE_SUCCESS; 2700 } 2701 break; 2702 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2703 arcmsr_iop_parking(acb); 2704 retvalue = ARCMSR_MESSAGE_SUCCESS; 2705 } 2706 break; 2707 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2708 arcmsr_flush_adapter_cache(acb); 2709 retvalue = ARCMSR_MESSAGE_SUCCESS; 2710 } 2711 break; 2712 } 2713 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2714 return (retvalue); 2715 } 2716 /* 2717 ************************************************************************** 2718 ************************************************************************** 2719 */ 2720 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2721 { 2722 struct AdapterControlBlock *acb; 2723 2724 acb = srb->acb; 2725 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2726 srb->srb_state = ARCMSR_SRB_DONE; 2727 srb->srb_flags = 0; 2728 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2729 acb->workingsrb_doneindex++; 2730 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2731 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2732 } 2733 /* 2734 ************************************************************************** 2735 ************************************************************************** 2736 */ 2737 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2738 { 2739 struct CommandControlBlock *srb = NULL; 2740 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2741 2742 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2743 workingsrb_doneindex = acb->workingsrb_doneindex; 2744 workingsrb_startindex = acb->workingsrb_startindex; 2745 srb = acb->srbworkingQ[workingsrb_startindex]; 2746 workingsrb_startindex++; 2747 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2748 if(workingsrb_doneindex != workingsrb_startindex) { 2749 acb->workingsrb_startindex = workingsrb_startindex; 2750 } else { 2751 srb = NULL; 2752 } 2753 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2754 return(srb); 2755 } 2756 /* 2757 ************************************************************************** 2758 ************************************************************************** 2759 */ 2760 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2761 { 2762 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2763 int retvalue = 0, transfer_len = 0; 2764 char *buffer; 2765 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2766 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2767 (u_int32_t ) ptr[6] << 16 | 2768 (u_int32_t ) ptr[7] << 8 | 2769 (u_int32_t ) ptr[8]; 2770 /* 4 bytes: Areca io control code */ 2771 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2772 buffer = pccb->csio.data_ptr; 2773 transfer_len = pccb->csio.dxfer_len; 2774 } else { 2775 retvalue = ARCMSR_MESSAGE_FAIL; 2776 goto message_out; 2777 } 2778 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2779 retvalue = ARCMSR_MESSAGE_FAIL; 2780 goto message_out; 2781 } 2782 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2783 switch(controlcode) { 2784 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2785 u_int8_t *pQbuffer; 2786 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2787 int32_t allxfer_len = 0; 2788 2789 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2790 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2791 && (allxfer_len < 1031)) { 2792 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2793 *ptmpQbuffer = *pQbuffer; 2794 acb->rqbuf_firstindex++; 2795 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2796 ptmpQbuffer++; 2797 allxfer_len++; 2798 } 2799 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2800 struct QBUFFER *prbuffer; 2801 2802 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2803 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2804 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2805 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2806 } 2807 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2808 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2809 retvalue = ARCMSR_MESSAGE_SUCCESS; 2810 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2811 } 2812 break; 2813 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2814 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2815 u_int8_t *pQbuffer; 2816 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2817 2818 user_len = pcmdmessagefld->cmdmessage.Length; 2819 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2820 wqbuf_lastindex = acb->wqbuf_lastindex; 2821 wqbuf_firstindex = acb->wqbuf_firstindex; 2822 if (wqbuf_lastindex != wqbuf_firstindex) { 2823 arcmsr_Write_data_2iop_wqbuffer(acb); 2824 /* has error report sensedata */ 2825 if(pccb->csio.sense_len) { 2826 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2827 /* Valid,ErrorCode */ 2828 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2829 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2830 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2831 /* AdditionalSenseLength */ 2832 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2833 /* AdditionalSenseCode */ 2834 } 2835 retvalue = ARCMSR_MESSAGE_FAIL; 2836 } else { 2837 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2838 &(ARCMSR_MAX_QBUFFER - 1); 2839 if (my_empty_len >= user_len) { 2840 while (user_len > 0) { 2841 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2842 *pQbuffer = *ptmpuserbuffer; 2843 acb->wqbuf_lastindex++; 2844 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2845 ptmpuserbuffer++; 2846 user_len--; 2847 } 2848 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2849 acb->acb_flags &= 2850 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2851 arcmsr_Write_data_2iop_wqbuffer(acb); 2852 } 2853 } else { 2854 /* has error report sensedata */ 2855 if(pccb->csio.sense_len) { 2856 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2857 /* Valid,ErrorCode */ 2858 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2859 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2860 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2861 /* AdditionalSenseLength */ 2862 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2863 /* AdditionalSenseCode */ 2864 } 2865 retvalue = ARCMSR_MESSAGE_FAIL; 2866 } 2867 } 2868 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2869 } 2870 break; 2871 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2872 u_int8_t *pQbuffer = acb->rqbuffer; 2873 2874 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2875 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2876 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2877 arcmsr_iop_message_read(acb); 2878 } 2879 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2880 acb->rqbuf_firstindex = 0; 2881 acb->rqbuf_lastindex = 0; 2882 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2883 pcmdmessagefld->cmdmessage.ReturnCode = 2884 ARCMSR_MESSAGE_RETURNCODE_OK; 2885 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2886 } 2887 break; 2888 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2889 u_int8_t *pQbuffer = acb->wqbuffer; 2890 2891 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2892 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2893 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2894 arcmsr_iop_message_read(acb); 2895 } 2896 acb->acb_flags |= 2897 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2898 ACB_F_MESSAGE_WQBUFFER_READ); 2899 acb->wqbuf_firstindex = 0; 2900 acb->wqbuf_lastindex = 0; 2901 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2902 pcmdmessagefld->cmdmessage.ReturnCode = 2903 ARCMSR_MESSAGE_RETURNCODE_OK; 2904 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2905 } 2906 break; 2907 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2908 u_int8_t *pQbuffer; 2909 2910 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2911 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2912 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2913 arcmsr_iop_message_read(acb); 2914 } 2915 acb->acb_flags |= 2916 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2917 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2918 | ACB_F_MESSAGE_WQBUFFER_READ); 2919 acb->rqbuf_firstindex = 0; 2920 acb->rqbuf_lastindex = 0; 2921 acb->wqbuf_firstindex = 0; 2922 acb->wqbuf_lastindex = 0; 2923 pQbuffer = acb->rqbuffer; 2924 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2925 pQbuffer = acb->wqbuffer; 2926 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2927 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2928 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2929 } 2930 break; 2931 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2932 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2933 } 2934 break; 2935 case ARCMSR_MESSAGE_SAY_HELLO: { 2936 int8_t *hello_string = "Hello! I am ARCMSR"; 2937 2938 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2939 , (int16_t)strlen(hello_string)); 2940 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2941 } 2942 break; 2943 case ARCMSR_MESSAGE_SAY_GOODBYE: 2944 arcmsr_iop_parking(acb); 2945 break; 2946 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2947 arcmsr_flush_adapter_cache(acb); 2948 break; 2949 default: 2950 retvalue = ARCMSR_MESSAGE_FAIL; 2951 } 2952 message_out: 2953 return (retvalue); 2954 } 2955 /* 2956 ********************************************************************* 2957 ********************************************************************* 2958 */ 2959 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2960 { 2961 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2962 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2963 union ccb *pccb; 2964 int target, lun; 2965 2966 pccb = srb->pccb; 2967 target = pccb->ccb_h.target_id; 2968 lun = pccb->ccb_h.target_lun; 2969 acb->pktRequestCount++; 2970 if(error != 0) { 2971 if(error != EFBIG) { 2972 printf("arcmsr%d: unexpected error %x" 2973 " returned from 'bus_dmamap_load' \n" 2974 , acb->pci_unit, error); 2975 } 2976 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2977 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2978 } 2979 arcmsr_srb_complete(srb, 0); 2980 return; 2981 } 2982 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2983 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2984 arcmsr_srb_complete(srb, 0); 2985 return; 2986 } 2987 if(acb->acb_flags & ACB_F_BUS_RESET) { 2988 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2989 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2990 arcmsr_srb_complete(srb, 0); 2991 return; 2992 } 2993 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2994 u_int8_t block_cmd, cmd; 2995 2996 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2997 block_cmd = cmd & 0x0f; 2998 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2999 printf("arcmsr%d:block 'read/write' command " 3000 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 3001 , acb->pci_unit, cmd, target, lun); 3002 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3003 arcmsr_srb_complete(srb, 0); 3004 return; 3005 } 3006 } 3007 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3008 if(nseg != 0) { 3009 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 3010 } 3011 arcmsr_srb_complete(srb, 0); 3012 return; 3013 } 3014 if(acb->srboutstandingcount >= acb->maxOutstanding) { 3015 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 3016 { 3017 xpt_freeze_simq(acb->psim, 1); 3018 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3019 } 3020 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3021 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3022 arcmsr_srb_complete(srb, 0); 3023 return; 3024 } 3025 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3026 arcmsr_build_srb(srb, dm_segs, nseg); 3027 arcmsr_post_srb(acb, srb); 3028 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3029 { 3030 arcmsr_callout_init(&srb->ccb_callout); 3031 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3032 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3033 arcmsr_srb_timeout, srb, 0); 3034 srb->srb_flags |= SRB_FLAG_TIMER_START; 3035 } 3036 } 3037 /* 3038 ***************************************************************************************** 3039 ***************************************************************************************** 3040 */ 3041 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3042 { 3043 struct CommandControlBlock *srb; 3044 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3045 u_int32_t intmask_org; 3046 int i = 0; 3047 3048 acb->num_aborts++; 3049 /* 3050 *************************************************************************** 3051 ** It is the upper layer do abort command this lock just prior to calling us. 3052 ** First determine if we currently own this command. 3053 ** Start by searching the device queue. If not found 3054 ** at all, and the system wanted us to just abort the 3055 ** command return success. 3056 *************************************************************************** 3057 */ 3058 if(acb->srboutstandingcount != 0) { 3059 /* disable all outbound interrupt */ 3060 intmask_org = arcmsr_disable_allintr(acb); 3061 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3062 srb = acb->psrb_pool[i]; 3063 if(srb->srb_state == ARCMSR_SRB_START) { 3064 if(srb->pccb == abortccb) { 3065 srb->srb_state = ARCMSR_SRB_ABORTED; 3066 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3067 "outstanding command \n" 3068 , acb->pci_unit, abortccb->ccb_h.target_id 3069 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3070 arcmsr_polling_srbdone(acb, srb); 3071 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3072 arcmsr_enable_allintr(acb, intmask_org); 3073 return (TRUE); 3074 } 3075 } 3076 } 3077 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3078 arcmsr_enable_allintr(acb, intmask_org); 3079 } 3080 return(FALSE); 3081 } 3082 /* 3083 **************************************************************************** 3084 **************************************************************************** 3085 */ 3086 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3087 { 3088 int retry = 0; 3089 3090 acb->num_resets++; 3091 acb->acb_flags |= ACB_F_BUS_RESET; 3092 while(acb->srboutstandingcount != 0 && retry < 400) { 3093 arcmsr_interrupt(acb); 3094 UDELAY(25000); 3095 retry++; 3096 } 3097 arcmsr_iop_reset(acb); 3098 acb->acb_flags &= ~ACB_F_BUS_RESET; 3099 } 3100 /* 3101 ************************************************************************** 3102 ************************************************************************** 3103 */ 3104 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3105 union ccb *pccb) 3106 { 3107 if (pccb->ccb_h.target_lun) { 3108 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3109 xpt_done(pccb); 3110 return; 3111 } 3112 pccb->ccb_h.status |= CAM_REQ_CMP; 3113 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3114 case INQUIRY: { 3115 unsigned char inqdata[36]; 3116 char *buffer = pccb->csio.data_ptr; 3117 3118 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3119 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3120 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3121 inqdata[3] = 0; 3122 inqdata[4] = 31; /* length of additional data */ 3123 inqdata[5] = 0; 3124 inqdata[6] = 0; 3125 inqdata[7] = 0; 3126 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3127 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3128 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3129 memcpy(buffer, inqdata, sizeof(inqdata)); 3130 xpt_done(pccb); 3131 } 3132 break; 3133 case WRITE_BUFFER: 3134 case READ_BUFFER: { 3135 if (arcmsr_iop_message_xfer(acb, pccb)) { 3136 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3137 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3138 } 3139 xpt_done(pccb); 3140 } 3141 break; 3142 default: 3143 xpt_done(pccb); 3144 } 3145 } 3146 /* 3147 ********************************************************************* 3148 ********************************************************************* 3149 */ 3150 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3151 { 3152 struct AdapterControlBlock *acb; 3153 3154 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3155 if(acb == NULL) { 3156 pccb->ccb_h.status |= CAM_REQ_INVALID; 3157 xpt_done(pccb); 3158 return; 3159 } 3160 switch (pccb->ccb_h.func_code) { 3161 case XPT_SCSI_IO: { 3162 struct CommandControlBlock *srb; 3163 int target = pccb->ccb_h.target_id; 3164 int error; 3165 3166 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3167 pccb->ccb_h.status = CAM_REQ_INVALID; 3168 xpt_done(pccb); 3169 return; 3170 } 3171 3172 if(target == 16) { 3173 /* virtual device for iop message transfer */ 3174 arcmsr_handle_virtual_command(acb, pccb); 3175 return; 3176 } 3177 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3178 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3179 xpt_done(pccb); 3180 return; 3181 } 3182 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3183 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3184 srb->pccb = pccb; 3185 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3186 , srb->dm_segs_dmamap 3187 , pccb 3188 , arcmsr_execute_srb, srb, /*flags*/0); 3189 if(error == EINPROGRESS) { 3190 xpt_freeze_simq(acb->psim, 1); 3191 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3192 } 3193 break; 3194 } 3195 case XPT_PATH_INQ: { 3196 struct ccb_pathinq *cpi = &pccb->cpi; 3197 3198 cpi->version_num = 1; 3199 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3200 cpi->target_sprt = 0; 3201 cpi->hba_misc = 0; 3202 cpi->hba_eng_cnt = 0; 3203 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3204 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3205 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3206 cpi->bus_id = cam_sim_bus(psim); 3207 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3208 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3209 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3210 cpi->unit_number = cam_sim_unit(psim); 3211 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3212 cpi->base_transfer_speed = 1200000; 3213 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3214 cpi->base_transfer_speed = 600000; 3215 else 3216 cpi->base_transfer_speed = 300000; 3217 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3218 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3219 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3220 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3221 { 3222 cpi->transport = XPORT_SAS; 3223 cpi->transport_version = 0; 3224 cpi->protocol_version = SCSI_REV_SPC2; 3225 } 3226 else 3227 { 3228 cpi->transport = XPORT_SPI; 3229 cpi->transport_version = 2; 3230 cpi->protocol_version = SCSI_REV_2; 3231 } 3232 cpi->protocol = PROTO_SCSI; 3233 cpi->ccb_h.status |= CAM_REQ_CMP; 3234 xpt_done(pccb); 3235 break; 3236 } 3237 case XPT_ABORT: { 3238 union ccb *pabort_ccb; 3239 3240 pabort_ccb = pccb->cab.abort_ccb; 3241 switch (pabort_ccb->ccb_h.func_code) { 3242 case XPT_ACCEPT_TARGET_IO: 3243 case XPT_CONT_TARGET_IO: 3244 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3245 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3246 xpt_done(pabort_ccb); 3247 pccb->ccb_h.status |= CAM_REQ_CMP; 3248 } else { 3249 xpt_print_path(pabort_ccb->ccb_h.path); 3250 printf("Not found\n"); 3251 pccb->ccb_h.status |= CAM_PATH_INVALID; 3252 } 3253 break; 3254 case XPT_SCSI_IO: 3255 pccb->ccb_h.status |= CAM_UA_ABORT; 3256 break; 3257 default: 3258 pccb->ccb_h.status |= CAM_REQ_INVALID; 3259 break; 3260 } 3261 xpt_done(pccb); 3262 break; 3263 } 3264 case XPT_RESET_BUS: 3265 case XPT_RESET_DEV: { 3266 u_int32_t i; 3267 3268 arcmsr_bus_reset(acb); 3269 for (i=0; i < 500; i++) { 3270 DELAY(1000); 3271 } 3272 pccb->ccb_h.status |= CAM_REQ_CMP; 3273 xpt_done(pccb); 3274 break; 3275 } 3276 case XPT_TERM_IO: { 3277 pccb->ccb_h.status |= CAM_REQ_INVALID; 3278 xpt_done(pccb); 3279 break; 3280 } 3281 case XPT_GET_TRAN_SETTINGS: { 3282 struct ccb_trans_settings *cts; 3283 3284 if(pccb->ccb_h.target_id == 16) { 3285 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3286 xpt_done(pccb); 3287 break; 3288 } 3289 cts = &pccb->cts; 3290 { 3291 struct ccb_trans_settings_scsi *scsi; 3292 struct ccb_trans_settings_spi *spi; 3293 struct ccb_trans_settings_sas *sas; 3294 3295 scsi = &cts->proto_specific.scsi; 3296 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3297 scsi->valid = CTS_SCSI_VALID_TQ; 3298 cts->protocol = PROTO_SCSI; 3299 3300 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3301 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3302 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3303 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3304 { 3305 cts->protocol_version = SCSI_REV_SPC2; 3306 cts->transport_version = 0; 3307 cts->transport = XPORT_SAS; 3308 sas = &cts->xport_specific.sas; 3309 sas->valid = CTS_SAS_VALID_SPEED; 3310 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3311 sas->bitrate = 1200000; 3312 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3313 sas->bitrate = 600000; 3314 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3315 sas->bitrate = 300000; 3316 } 3317 else 3318 { 3319 cts->protocol_version = SCSI_REV_2; 3320 cts->transport_version = 2; 3321 cts->transport = XPORT_SPI; 3322 spi = &cts->xport_specific.spi; 3323 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3324 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3325 spi->sync_period = 1; 3326 else 3327 spi->sync_period = 2; 3328 spi->sync_offset = 32; 3329 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3330 spi->valid = CTS_SPI_VALID_DISC 3331 | CTS_SPI_VALID_SYNC_RATE 3332 | CTS_SPI_VALID_SYNC_OFFSET 3333 | CTS_SPI_VALID_BUS_WIDTH; 3334 } 3335 } 3336 pccb->ccb_h.status |= CAM_REQ_CMP; 3337 xpt_done(pccb); 3338 break; 3339 } 3340 case XPT_SET_TRAN_SETTINGS: { 3341 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3342 xpt_done(pccb); 3343 break; 3344 } 3345 case XPT_CALC_GEOMETRY: 3346 if(pccb->ccb_h.target_id == 16) { 3347 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3348 xpt_done(pccb); 3349 break; 3350 } 3351 cam_calc_geometry(&pccb->ccg, 1); 3352 xpt_done(pccb); 3353 break; 3354 default: 3355 pccb->ccb_h.status |= CAM_REQ_INVALID; 3356 xpt_done(pccb); 3357 break; 3358 } 3359 } 3360 /* 3361 ********************************************************************** 3362 ********************************************************************** 3363 */ 3364 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3365 { 3366 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3367 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3368 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3369 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3370 } 3371 } 3372 /* 3373 ********************************************************************** 3374 ********************************************************************** 3375 */ 3376 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3377 { 3378 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3379 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3380 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3381 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3382 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3383 } 3384 } 3385 /* 3386 ********************************************************************** 3387 ********************************************************************** 3388 */ 3389 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3390 { 3391 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3392 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3393 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3394 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3395 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3396 } 3397 } 3398 /* 3399 ********************************************************************** 3400 ********************************************************************** 3401 */ 3402 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3403 { 3404 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3405 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3406 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3407 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3408 } 3409 } 3410 /* 3411 ********************************************************************** 3412 ********************************************************************** 3413 */ 3414 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3415 { 3416 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3417 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3418 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3419 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3420 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3421 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3422 } 3423 } 3424 /* 3425 ********************************************************************** 3426 ********************************************************************** 3427 */ 3428 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3429 { 3430 switch (acb->adapter_type) { 3431 case ACB_ADAPTER_TYPE_A: 3432 arcmsr_start_hba_bgrb(acb); 3433 break; 3434 case ACB_ADAPTER_TYPE_B: 3435 arcmsr_start_hbb_bgrb(acb); 3436 break; 3437 case ACB_ADAPTER_TYPE_C: 3438 arcmsr_start_hbc_bgrb(acb); 3439 break; 3440 case ACB_ADAPTER_TYPE_D: 3441 arcmsr_start_hbd_bgrb(acb); 3442 break; 3443 case ACB_ADAPTER_TYPE_E: 3444 case ACB_ADAPTER_TYPE_F: 3445 arcmsr_start_hbe_bgrb(acb); 3446 break; 3447 } 3448 } 3449 /* 3450 ********************************************************************** 3451 ** 3452 ********************************************************************** 3453 */ 3454 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3455 { 3456 struct CommandControlBlock *srb; 3457 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3458 u_int16_t error; 3459 3460 polling_ccb_retry: 3461 poll_count++; 3462 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3463 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3464 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3465 while(1) { 3466 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3467 0, outbound_queueport)) == 0xFFFFFFFF) { 3468 if(poll_srb_done) { 3469 break;/*chip FIFO no ccb for completion already*/ 3470 } else { 3471 UDELAY(25000); 3472 if ((poll_count > 100) && (poll_srb != NULL)) { 3473 break; 3474 } 3475 goto polling_ccb_retry; 3476 } 3477 } 3478 /* check if command done with no error*/ 3479 srb = (struct CommandControlBlock *) 3480 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3481 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3482 poll_srb_done = (srb == poll_srb) ? 1:0; 3483 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3484 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3485 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3486 "poll command abort successfully \n" 3487 , acb->pci_unit 3488 , srb->pccb->ccb_h.target_id 3489 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3490 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3491 arcmsr_srb_complete(srb, 1); 3492 continue; 3493 } 3494 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3495 "srboutstandingcount=%d \n" 3496 , acb->pci_unit 3497 , srb, acb->srboutstandingcount); 3498 continue; 3499 } 3500 arcmsr_report_srb_state(acb, srb, error); 3501 } /*drain reply FIFO*/ 3502 } 3503 /* 3504 ********************************************************************** 3505 ** 3506 ********************************************************************** 3507 */ 3508 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3509 { 3510 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3511 struct CommandControlBlock *srb; 3512 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3513 int index; 3514 u_int16_t error; 3515 3516 polling_ccb_retry: 3517 poll_count++; 3518 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3519 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3520 while(1) { 3521 index = phbbmu->doneq_index; 3522 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3523 if(poll_srb_done) { 3524 break;/*chip FIFO no ccb for completion already*/ 3525 } else { 3526 UDELAY(25000); 3527 if ((poll_count > 100) && (poll_srb != NULL)) { 3528 break; 3529 } 3530 goto polling_ccb_retry; 3531 } 3532 } 3533 phbbmu->done_qbuffer[index] = 0; 3534 index++; 3535 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3536 phbbmu->doneq_index = index; 3537 /* check if command done with no error*/ 3538 srb = (struct CommandControlBlock *) 3539 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3540 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3541 poll_srb_done = (srb == poll_srb) ? 1:0; 3542 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3543 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3544 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3545 "poll command abort successfully \n" 3546 , acb->pci_unit 3547 , srb->pccb->ccb_h.target_id 3548 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3549 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3550 arcmsr_srb_complete(srb, 1); 3551 continue; 3552 } 3553 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3554 "srboutstandingcount=%d \n" 3555 , acb->pci_unit 3556 , srb, acb->srboutstandingcount); 3557 continue; 3558 } 3559 arcmsr_report_srb_state(acb, srb, error); 3560 } /*drain reply FIFO*/ 3561 } 3562 /* 3563 ********************************************************************** 3564 ** 3565 ********************************************************************** 3566 */ 3567 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3568 { 3569 struct CommandControlBlock *srb; 3570 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3571 u_int16_t error; 3572 3573 polling_ccb_retry: 3574 poll_count++; 3575 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3576 while(1) { 3577 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3578 if(poll_srb_done) { 3579 break;/*chip FIFO no ccb for completion already*/ 3580 } else { 3581 UDELAY(25000); 3582 if ((poll_count > 100) && (poll_srb != NULL)) { 3583 break; 3584 } 3585 if (acb->srboutstandingcount == 0) { 3586 break; 3587 } 3588 goto polling_ccb_retry; 3589 } 3590 } 3591 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3592 /* check if command done with no error*/ 3593 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3594 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3595 if (poll_srb != NULL) 3596 poll_srb_done = (srb == poll_srb) ? 1:0; 3597 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3598 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3599 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3600 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3601 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3602 arcmsr_srb_complete(srb, 1); 3603 continue; 3604 } 3605 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3606 , acb->pci_unit, srb, acb->srboutstandingcount); 3607 continue; 3608 } 3609 arcmsr_report_srb_state(acb, srb, error); 3610 } /*drain reply FIFO*/ 3611 } 3612 /* 3613 ********************************************************************** 3614 ** 3615 ********************************************************************** 3616 */ 3617 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3618 { 3619 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3620 struct CommandControlBlock *srb; 3621 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3622 u_int32_t outbound_write_pointer; 3623 u_int16_t error, doneq_index; 3624 3625 polling_ccb_retry: 3626 poll_count++; 3627 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3628 while(1) { 3629 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3630 doneq_index = phbdmu->doneq_index; 3631 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3632 if(poll_srb_done) { 3633 break;/*chip FIFO no ccb for completion already*/ 3634 } else { 3635 UDELAY(25000); 3636 if ((poll_count > 100) && (poll_srb != NULL)) { 3637 break; 3638 } 3639 if (acb->srboutstandingcount == 0) { 3640 break; 3641 } 3642 goto polling_ccb_retry; 3643 } 3644 } 3645 doneq_index = arcmsr_get_doneq_index(phbdmu); 3646 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3647 /* check if command done with no error*/ 3648 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3649 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3650 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3651 if (poll_srb != NULL) 3652 poll_srb_done = (srb == poll_srb) ? 1:0; 3653 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3654 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3655 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3656 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3657 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3658 arcmsr_srb_complete(srb, 1); 3659 continue; 3660 } 3661 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3662 , acb->pci_unit, srb, acb->srboutstandingcount); 3663 continue; 3664 } 3665 arcmsr_report_srb_state(acb, srb, error); 3666 } /*drain reply FIFO*/ 3667 } 3668 /* 3669 ********************************************************************** 3670 ** 3671 ********************************************************************** 3672 */ 3673 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3674 { 3675 struct CommandControlBlock *srb; 3676 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3677 u_int16_t error, cmdSMID; 3678 3679 polling_ccb_retry: 3680 poll_count++; 3681 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3682 while(1) { 3683 doneq_index = acb->doneq_index; 3684 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3685 if(poll_srb_done) { 3686 break;/*chip FIFO no ccb for completion already*/ 3687 } else { 3688 UDELAY(25000); 3689 if ((poll_count > 100) && (poll_srb != NULL)) { 3690 break; 3691 } 3692 if (acb->srboutstandingcount == 0) { 3693 break; 3694 } 3695 goto polling_ccb_retry; 3696 } 3697 } 3698 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3699 doneq_index++; 3700 if (doneq_index >= acb->completionQ_entry) 3701 doneq_index = 0; 3702 acb->doneq_index = doneq_index; 3703 srb = acb->psrb_pool[cmdSMID]; 3704 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3705 if (poll_srb != NULL) 3706 poll_srb_done = (srb == poll_srb) ? 1:0; 3707 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3708 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3709 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3710 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3711 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3712 arcmsr_srb_complete(srb, 1); 3713 continue; 3714 } 3715 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3716 , acb->pci_unit, srb, acb->srboutstandingcount); 3717 continue; 3718 } 3719 arcmsr_report_srb_state(acb, srb, error); 3720 } /*drain reply FIFO*/ 3721 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3722 } 3723 /* 3724 ********************************************************************** 3725 ********************************************************************** 3726 */ 3727 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3728 { 3729 switch (acb->adapter_type) { 3730 case ACB_ADAPTER_TYPE_A: 3731 arcmsr_polling_hba_srbdone(acb, poll_srb); 3732 break; 3733 case ACB_ADAPTER_TYPE_B: 3734 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3735 break; 3736 case ACB_ADAPTER_TYPE_C: 3737 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3738 break; 3739 case ACB_ADAPTER_TYPE_D: 3740 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3741 break; 3742 case ACB_ADAPTER_TYPE_E: 3743 case ACB_ADAPTER_TYPE_F: 3744 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3745 break; 3746 } 3747 } 3748 /* 3749 ********************************************************************** 3750 ********************************************************************** 3751 */ 3752 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3753 { 3754 char *acb_firm_model = acb->firm_model; 3755 char *acb_firm_version = acb->firm_version; 3756 char *acb_device_map = acb->device_map; 3757 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3758 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3759 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3760 int i; 3761 3762 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3763 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3764 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3765 } 3766 i = 0; 3767 while(i < 8) { 3768 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3769 /* 8 bytes firm_model, 15, 60-67*/ 3770 acb_firm_model++; 3771 i++; 3772 } 3773 i=0; 3774 while(i < 16) { 3775 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3776 /* 16 bytes firm_version, 17, 68-83*/ 3777 acb_firm_version++; 3778 i++; 3779 } 3780 i=0; 3781 while(i < 16) { 3782 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3783 acb_device_map++; 3784 i++; 3785 } 3786 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3787 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3788 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3789 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3790 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3791 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3792 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3793 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3794 else 3795 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3796 } 3797 /* 3798 ********************************************************************** 3799 ********************************************************************** 3800 */ 3801 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3802 { 3803 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3804 char *acb_firm_model = acb->firm_model; 3805 char *acb_firm_version = acb->firm_version; 3806 char *acb_device_map = acb->device_map; 3807 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3808 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3809 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3810 int i; 3811 3812 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3813 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3814 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3815 } 3816 i = 0; 3817 while(i < 8) { 3818 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3819 /* 8 bytes firm_model, 15, 60-67*/ 3820 acb_firm_model++; 3821 i++; 3822 } 3823 i = 0; 3824 while(i < 16) { 3825 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3826 /* 16 bytes firm_version, 17, 68-83*/ 3827 acb_firm_version++; 3828 i++; 3829 } 3830 i = 0; 3831 while(i < 16) { 3832 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3833 acb_device_map++; 3834 i++; 3835 } 3836 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3837 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3838 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3839 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3840 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3841 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3842 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3843 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3844 else 3845 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3846 } 3847 /* 3848 ********************************************************************** 3849 ********************************************************************** 3850 */ 3851 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3852 { 3853 char *acb_firm_model = acb->firm_model; 3854 char *acb_firm_version = acb->firm_version; 3855 char *acb_device_map = acb->device_map; 3856 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3857 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3858 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3859 int i; 3860 3861 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3862 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3863 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3864 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3865 } 3866 i = 0; 3867 while(i < 8) { 3868 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3869 /* 8 bytes firm_model, 15, 60-67*/ 3870 acb_firm_model++; 3871 i++; 3872 } 3873 i = 0; 3874 while(i < 16) { 3875 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3876 /* 16 bytes firm_version, 17, 68-83*/ 3877 acb_firm_version++; 3878 i++; 3879 } 3880 i = 0; 3881 while(i < 16) { 3882 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3883 acb_device_map++; 3884 i++; 3885 } 3886 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3887 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3888 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3889 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3890 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3891 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3892 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3893 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3894 else 3895 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3896 } 3897 /* 3898 ********************************************************************** 3899 ********************************************************************** 3900 */ 3901 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3902 { 3903 char *acb_firm_model = acb->firm_model; 3904 char *acb_firm_version = acb->firm_version; 3905 char *acb_device_map = acb->device_map; 3906 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3907 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3908 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3909 int i; 3910 3911 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3912 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3913 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3914 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3915 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3916 } 3917 i = 0; 3918 while(i < 8) { 3919 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3920 /* 8 bytes firm_model, 15, 60-67*/ 3921 acb_firm_model++; 3922 i++; 3923 } 3924 i = 0; 3925 while(i < 16) { 3926 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3927 /* 16 bytes firm_version, 17, 68-83*/ 3928 acb_firm_version++; 3929 i++; 3930 } 3931 i = 0; 3932 while(i < 16) { 3933 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3934 acb_device_map++; 3935 i++; 3936 } 3937 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3938 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3939 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3940 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3941 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3942 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3943 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3944 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3945 else 3946 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3947 } 3948 /* 3949 ********************************************************************** 3950 ********************************************************************** 3951 */ 3952 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3953 { 3954 char *acb_firm_model = acb->firm_model; 3955 char *acb_firm_version = acb->firm_version; 3956 char *acb_device_map = acb->device_map; 3957 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3958 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3959 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3960 int i; 3961 3962 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3963 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3964 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3965 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3966 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3967 } 3968 3969 i = 0; 3970 while(i < 8) { 3971 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3972 /* 8 bytes firm_model, 15, 60-67*/ 3973 acb_firm_model++; 3974 i++; 3975 } 3976 i = 0; 3977 while(i < 16) { 3978 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3979 /* 16 bytes firm_version, 17, 68-83*/ 3980 acb_firm_version++; 3981 i++; 3982 } 3983 i = 0; 3984 while(i < 16) { 3985 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3986 acb_device_map++; 3987 i++; 3988 } 3989 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3990 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3991 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3992 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3993 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3994 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3995 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3996 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3997 else 3998 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3999 } 4000 /* 4001 ********************************************************************** 4002 ********************************************************************** 4003 */ 4004 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 4005 { 4006 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 4007 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 4008 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 4009 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 4010 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 4011 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 4012 int i; 4013 4014 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4015 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4016 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4017 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4018 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4019 4020 i = 0; 4021 while(i < 2) { 4022 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4023 /* 8 bytes firm_model, 15, 60-67*/ 4024 acb_firm_model++; 4025 iop_firm_model++; 4026 i++; 4027 } 4028 i = 0; 4029 while(i < 4) { 4030 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4031 /* 16 bytes firm_version, 17, 68-83*/ 4032 acb_firm_version++; 4033 iop_firm_version++; 4034 i++; 4035 } 4036 i = 0; 4037 while(i < 4) { 4038 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4039 acb_device_map++; 4040 iop_device_map++; 4041 i++; 4042 } 4043 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4044 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4045 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4046 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4047 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4048 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4049 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4050 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4051 else 4052 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4053 } 4054 /* 4055 ********************************************************************** 4056 ********************************************************************** 4057 */ 4058 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4059 { 4060 switch (acb->adapter_type) { 4061 case ACB_ADAPTER_TYPE_A: 4062 arcmsr_get_hba_config(acb); 4063 break; 4064 case ACB_ADAPTER_TYPE_B: 4065 arcmsr_get_hbb_config(acb); 4066 break; 4067 case ACB_ADAPTER_TYPE_C: 4068 arcmsr_get_hbc_config(acb); 4069 break; 4070 case ACB_ADAPTER_TYPE_D: 4071 arcmsr_get_hbd_config(acb); 4072 break; 4073 case ACB_ADAPTER_TYPE_E: 4074 arcmsr_get_hbe_config(acb); 4075 break; 4076 case ACB_ADAPTER_TYPE_F: 4077 arcmsr_get_hbf_config(acb); 4078 break; 4079 } 4080 } 4081 /* 4082 ********************************************************************** 4083 ********************************************************************** 4084 */ 4085 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4086 { 4087 int timeout=0; 4088 4089 switch (acb->adapter_type) { 4090 case ACB_ADAPTER_TYPE_A: { 4091 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4092 { 4093 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4094 { 4095 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4096 return; 4097 } 4098 UDELAY(15000); /* wait 15 milli-seconds */ 4099 } 4100 } 4101 break; 4102 case ACB_ADAPTER_TYPE_B: { 4103 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4104 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4105 { 4106 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4107 { 4108 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4109 return; 4110 } 4111 UDELAY(15000); /* wait 15 milli-seconds */ 4112 } 4113 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4114 } 4115 break; 4116 case ACB_ADAPTER_TYPE_C: { 4117 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4118 { 4119 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4120 { 4121 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4122 return; 4123 } 4124 UDELAY(15000); /* wait 15 milli-seconds */ 4125 } 4126 } 4127 break; 4128 case ACB_ADAPTER_TYPE_D: { 4129 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4130 { 4131 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4132 { 4133 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4134 return; 4135 } 4136 UDELAY(15000); /* wait 15 milli-seconds */ 4137 } 4138 } 4139 break; 4140 case ACB_ADAPTER_TYPE_E: 4141 case ACB_ADAPTER_TYPE_F: { 4142 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4143 { 4144 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4145 { 4146 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4147 return; 4148 } 4149 UDELAY(15000); /* wait 15 milli-seconds */ 4150 } 4151 } 4152 break; 4153 } 4154 } 4155 /* 4156 ********************************************************************** 4157 ********************************************************************** 4158 */ 4159 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4160 { 4161 u_int32_t outbound_doorbell; 4162 4163 switch (acb->adapter_type) { 4164 case ACB_ADAPTER_TYPE_A: { 4165 /* empty doorbell Qbuffer if door bell ringed */ 4166 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4167 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4168 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4169 } 4170 break; 4171 case ACB_ADAPTER_TYPE_B: { 4172 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4173 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4174 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4175 /* let IOP know data has been read */ 4176 } 4177 break; 4178 case ACB_ADAPTER_TYPE_C: { 4179 /* empty doorbell Qbuffer if door bell ringed */ 4180 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4181 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4182 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4183 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4184 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4185 } 4186 break; 4187 case ACB_ADAPTER_TYPE_D: { 4188 /* empty doorbell Qbuffer if door bell ringed */ 4189 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4190 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4191 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4192 } 4193 break; 4194 case ACB_ADAPTER_TYPE_E: 4195 case ACB_ADAPTER_TYPE_F: { 4196 /* empty doorbell Qbuffer if door bell ringed */ 4197 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4198 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4199 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4200 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4201 } 4202 break; 4203 } 4204 } 4205 /* 4206 ************************************************************************ 4207 ************************************************************************ 4208 */ 4209 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4210 { 4211 unsigned long srb_phyaddr; 4212 u_int32_t srb_phyaddr_hi32; 4213 u_int32_t srb_phyaddr_lo32; 4214 4215 /* 4216 ******************************************************************** 4217 ** here we need to tell iop 331 our freesrb.HighPart 4218 ** if freesrb.HighPart is not zero 4219 ******************************************************************** 4220 */ 4221 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4222 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4223 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4224 switch (acb->adapter_type) { 4225 case ACB_ADAPTER_TYPE_A: { 4226 if(srb_phyaddr_hi32 != 0) { 4227 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4228 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4229 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4230 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4231 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4232 return FALSE; 4233 } 4234 } 4235 } 4236 break; 4237 /* 4238 *********************************************************************** 4239 ** if adapter type B, set window of "post command Q" 4240 *********************************************************************** 4241 */ 4242 case ACB_ADAPTER_TYPE_B: { 4243 u_int32_t post_queue_phyaddr; 4244 struct HBB_MessageUnit *phbbmu; 4245 4246 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4247 phbbmu->postq_index = 0; 4248 phbbmu->doneq_index = 0; 4249 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4250 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4251 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4252 return FALSE; 4253 } 4254 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4255 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4256 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4257 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4258 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4259 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4260 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4261 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4262 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4263 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4264 return FALSE; 4265 } 4266 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4267 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4268 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4269 return FALSE; 4270 } 4271 } 4272 break; 4273 case ACB_ADAPTER_TYPE_C: { 4274 if(srb_phyaddr_hi32 != 0) { 4275 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4276 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4277 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4278 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4279 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4280 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4281 return FALSE; 4282 } 4283 } 4284 } 4285 break; 4286 case ACB_ADAPTER_TYPE_D: { 4287 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4288 struct HBD_MessageUnit0 *phbdmu; 4289 4290 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4291 phbdmu->postq_index = 0; 4292 phbdmu->doneq_index = 0x40FF; 4293 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4294 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4295 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4296 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4297 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4298 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4299 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4300 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4301 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4302 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4303 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4304 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4305 return FALSE; 4306 } 4307 } 4308 break; 4309 case ACB_ADAPTER_TYPE_E: { 4310 u_int32_t cdb_phyaddr_lo32; 4311 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4312 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4313 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4314 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4315 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4316 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4317 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4318 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4319 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4320 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4321 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4322 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4323 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4324 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4325 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4326 return FALSE; 4327 } 4328 } 4329 break; 4330 case ACB_ADAPTER_TYPE_F: { 4331 u_int32_t cdb_phyaddr_lo32; 4332 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4333 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4334 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4335 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4336 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4337 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4338 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4339 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4340 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4341 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4342 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4343 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4344 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4345 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4346 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4347 return FALSE; 4348 } 4349 } 4350 break; 4351 } 4352 return (TRUE); 4353 } 4354 /* 4355 ************************************************************************ 4356 ************************************************************************ 4357 */ 4358 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4359 { 4360 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4361 { 4362 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4363 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4364 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4365 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4366 return; 4367 } 4368 } 4369 } 4370 /* 4371 ********************************************************************** 4372 ********************************************************************** 4373 */ 4374 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4375 { 4376 u_int32_t intmask_org; 4377 4378 /* disable all outbound interrupt */ 4379 intmask_org = arcmsr_disable_allintr(acb); 4380 arcmsr_wait_firmware_ready(acb); 4381 arcmsr_iop_confirm(acb); 4382 arcmsr_get_firmware_spec(acb); 4383 /*start background rebuild*/ 4384 arcmsr_start_adapter_bgrb(acb); 4385 /* empty doorbell Qbuffer if door bell ringed */ 4386 arcmsr_clear_doorbell_queue_buffer(acb); 4387 arcmsr_enable_eoi_mode(acb); 4388 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4389 arcmsr_enable_allintr(acb, intmask_org); 4390 acb->acb_flags |= ACB_F_IOP_INITED; 4391 } 4392 /* 4393 ********************************************************************** 4394 ********************************************************************** 4395 */ 4396 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4397 { 4398 struct AdapterControlBlock *acb = arg; 4399 struct CommandControlBlock *srb_tmp; 4400 u_int32_t i; 4401 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4402 4403 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4404 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4405 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4406 if(bus_dmamap_create(acb->dm_segs_dmat, 4407 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4408 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4409 printf("arcmsr%d:" 4410 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4411 return; 4412 } 4413 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4414 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4415 { 4416 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4417 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4418 } 4419 else 4420 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4421 srb_tmp->acb = acb; 4422 srb_tmp->smid = i << 16; 4423 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4424 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4425 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4426 } 4427 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4428 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4429 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4430 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4431 acb->completeQ_phys = srb_phyaddr; 4432 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4433 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4434 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4435 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4436 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4437 } 4438 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4439 } 4440 /* 4441 ************************************************************************ 4442 ************************************************************************ 4443 */ 4444 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4445 { 4446 /* remove the control device */ 4447 if(acb->ioctl_dev != NULL) { 4448 destroy_dev(acb->ioctl_dev); 4449 } 4450 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4451 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4452 bus_dma_tag_destroy(acb->srb_dmat); 4453 bus_dma_tag_destroy(acb->dm_segs_dmat); 4454 bus_dma_tag_destroy(acb->parent_dmat); 4455 } 4456 /* 4457 ************************************************************************ 4458 ************************************************************************ 4459 */ 4460 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4461 { 4462 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4463 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4464 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4465 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4466 } 4467 /* 4468 ************************************************************************ 4469 ************************************************************************ 4470 */ 4471 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4472 { 4473 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4474 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4475 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4476 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4477 } 4478 /* 4479 ************************************************************************ 4480 ************************************************************************ 4481 */ 4482 static u_int32_t arcmsr_initialize(device_t dev) 4483 { 4484 struct AdapterControlBlock *acb = device_get_softc(dev); 4485 u_int16_t pci_command; 4486 int i, j,max_coherent_size; 4487 u_int32_t vendor_dev_id; 4488 4489 vendor_dev_id = pci_get_devid(dev); 4490 acb->vendor_device_id = vendor_dev_id; 4491 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4492 switch (vendor_dev_id) { 4493 case PCIDevVenIDARC1880: 4494 case PCIDevVenIDARC1882: 4495 case PCIDevVenIDARC1213: 4496 case PCIDevVenIDARC1223: { 4497 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4498 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4499 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4500 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4501 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4502 else 4503 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4504 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4505 } 4506 break; 4507 case PCIDevVenIDARC1884: 4508 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4509 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4510 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4511 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4512 break; 4513 case PCIDevVenIDARC1886_: 4514 case PCIDevVenIDARC1886: 4515 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4516 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4517 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4518 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4519 break; 4520 case PCIDevVenIDARC1214: { 4521 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4522 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4523 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4524 } 4525 break; 4526 case PCIDevVenIDARC1200: 4527 case PCIDevVenIDARC1201: { 4528 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4529 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4530 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4531 } 4532 break; 4533 case PCIDevVenIDARC1203: { 4534 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4535 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4536 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4537 } 4538 break; 4539 case PCIDevVenIDARC1110: 4540 case PCIDevVenIDARC1120: 4541 case PCIDevVenIDARC1130: 4542 case PCIDevVenIDARC1160: 4543 case PCIDevVenIDARC1170: 4544 case PCIDevVenIDARC1210: 4545 case PCIDevVenIDARC1220: 4546 case PCIDevVenIDARC1230: 4547 case PCIDevVenIDARC1231: 4548 case PCIDevVenIDARC1260: 4549 case PCIDevVenIDARC1261: 4550 case PCIDevVenIDARC1270: 4551 case PCIDevVenIDARC1280: 4552 case PCIDevVenIDARC1212: 4553 case PCIDevVenIDARC1222: 4554 case PCIDevVenIDARC1380: 4555 case PCIDevVenIDARC1381: 4556 case PCIDevVenIDARC1680: 4557 case PCIDevVenIDARC1681: { 4558 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4559 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4560 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4561 } 4562 break; 4563 default: { 4564 printf("arcmsr%d:" 4565 " unknown RAID adapter type \n", device_get_unit(dev)); 4566 return ENOMEM; 4567 } 4568 } 4569 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4570 /*alignemnt*/ 1, 4571 /*boundary*/ 0, 4572 /*lowaddr*/ BUS_SPACE_MAXADDR, 4573 /*highaddr*/ BUS_SPACE_MAXADDR, 4574 /*filter*/ NULL, 4575 /*filterarg*/ NULL, 4576 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4577 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4578 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4579 /*flags*/ 0, 4580 /*lockfunc*/ NULL, 4581 /*lockarg*/ NULL, 4582 &acb->parent_dmat) != 0) 4583 { 4584 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4585 return ENOMEM; 4586 } 4587 4588 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4589 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4590 /*alignment*/ 1, 4591 /*boundary*/ 0, 4592 #ifdef PAE 4593 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4594 #else 4595 /*lowaddr*/ BUS_SPACE_MAXADDR, 4596 #endif 4597 /*highaddr*/ BUS_SPACE_MAXADDR, 4598 /*filter*/ NULL, 4599 /*filterarg*/ NULL, 4600 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4601 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4602 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4603 /*flags*/ 0, 4604 /*lockfunc*/ busdma_lock_mutex, 4605 /*lockarg*/ &acb->isr_lock, 4606 &acb->dm_segs_dmat) != 0) 4607 { 4608 bus_dma_tag_destroy(acb->parent_dmat); 4609 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4610 return ENOMEM; 4611 } 4612 4613 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4614 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4615 /*alignment*/ 0x20, 4616 /*boundary*/ 0, 4617 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4618 /*highaddr*/ BUS_SPACE_MAXADDR, 4619 /*filter*/ NULL, 4620 /*filterarg*/ NULL, 4621 /*maxsize*/ max_coherent_size, 4622 /*nsegments*/ 1, 4623 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4624 /*flags*/ 0, 4625 /*lockfunc*/ NULL, 4626 /*lockarg*/ NULL, 4627 &acb->srb_dmat) != 0) 4628 { 4629 bus_dma_tag_destroy(acb->dm_segs_dmat); 4630 bus_dma_tag_destroy(acb->parent_dmat); 4631 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4632 return ENXIO; 4633 } 4634 /* Allocation for our srbs */ 4635 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4636 bus_dma_tag_destroy(acb->srb_dmat); 4637 bus_dma_tag_destroy(acb->dm_segs_dmat); 4638 bus_dma_tag_destroy(acb->parent_dmat); 4639 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4640 return ENXIO; 4641 } 4642 /* And permanently map them */ 4643 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4644 bus_dma_tag_destroy(acb->srb_dmat); 4645 bus_dma_tag_destroy(acb->dm_segs_dmat); 4646 bus_dma_tag_destroy(acb->parent_dmat); 4647 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4648 return ENXIO; 4649 } 4650 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4651 pci_command |= PCIM_CMD_BUSMASTEREN; 4652 pci_command |= PCIM_CMD_PERRESPEN; 4653 pci_command |= PCIM_CMD_MWRICEN; 4654 /* Enable Busmaster */ 4655 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4656 switch(acb->adapter_type) { 4657 case ACB_ADAPTER_TYPE_A: { 4658 u_int32_t rid0 = PCIR_BAR(0); 4659 vm_offset_t mem_base0; 4660 4661 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4662 if(acb->sys_res_arcmsr[0] == NULL) { 4663 arcmsr_free_resource(acb); 4664 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4665 return ENOMEM; 4666 } 4667 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4668 arcmsr_free_resource(acb); 4669 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4670 return ENXIO; 4671 } 4672 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4673 if(mem_base0 == 0) { 4674 arcmsr_free_resource(acb); 4675 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4676 return ENXIO; 4677 } 4678 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4679 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4680 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4681 acb->rid[0] = rid0; 4682 } 4683 break; 4684 case ACB_ADAPTER_TYPE_B: { 4685 struct HBB_MessageUnit *phbbmu; 4686 struct CommandControlBlock *freesrb; 4687 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4688 vm_offset_t mem_base[]={0,0}; 4689 for(i=0; i < 2; i++) { 4690 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4691 if(acb->sys_res_arcmsr[i] == NULL) { 4692 arcmsr_free_resource(acb); 4693 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4694 return ENOMEM; 4695 } 4696 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4697 arcmsr_free_resource(acb); 4698 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4699 return ENXIO; 4700 } 4701 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4702 if(mem_base[i] == 0) { 4703 arcmsr_free_resource(acb); 4704 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4705 return ENXIO; 4706 } 4707 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4708 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4709 } 4710 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4711 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4712 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4713 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4714 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4715 if (vendor_dev_id == PCIDevVenIDARC1203) { 4716 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4717 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4718 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4719 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4720 } else { 4721 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4722 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4723 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4724 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4725 } 4726 acb->rid[0] = rid[0]; 4727 acb->rid[1] = rid[1]; 4728 } 4729 break; 4730 case ACB_ADAPTER_TYPE_C: { 4731 u_int32_t rid0 = PCIR_BAR(1); 4732 vm_offset_t mem_base0; 4733 4734 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4735 if(acb->sys_res_arcmsr[0] == NULL) { 4736 arcmsr_free_resource(acb); 4737 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4738 return ENOMEM; 4739 } 4740 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4741 arcmsr_free_resource(acb); 4742 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4743 return ENXIO; 4744 } 4745 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4746 if(mem_base0 == 0) { 4747 arcmsr_free_resource(acb); 4748 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4749 return ENXIO; 4750 } 4751 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4752 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4753 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4754 acb->rid[0] = rid0; 4755 } 4756 break; 4757 case ACB_ADAPTER_TYPE_D: { 4758 struct HBD_MessageUnit0 *phbdmu; 4759 u_int32_t rid0 = PCIR_BAR(0); 4760 vm_offset_t mem_base0; 4761 4762 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4763 if(acb->sys_res_arcmsr[0] == NULL) { 4764 arcmsr_free_resource(acb); 4765 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4766 return ENOMEM; 4767 } 4768 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4769 arcmsr_free_resource(acb); 4770 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4771 return ENXIO; 4772 } 4773 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4774 if(mem_base0 == 0) { 4775 arcmsr_free_resource(acb); 4776 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4777 return ENXIO; 4778 } 4779 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4780 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4781 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4782 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4783 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4784 acb->rid[0] = rid0; 4785 } 4786 break; 4787 case ACB_ADAPTER_TYPE_E: { 4788 u_int32_t rid0 = PCIR_BAR(1); 4789 vm_offset_t mem_base0; 4790 4791 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4792 if(acb->sys_res_arcmsr[0] == NULL) { 4793 arcmsr_free_resource(acb); 4794 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4795 return ENOMEM; 4796 } 4797 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4798 arcmsr_free_resource(acb); 4799 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4800 return ENXIO; 4801 } 4802 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4803 if(mem_base0 == 0) { 4804 arcmsr_free_resource(acb); 4805 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4806 return ENXIO; 4807 } 4808 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4809 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4810 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4811 acb->doneq_index = 0; 4812 acb->in_doorbell = 0; 4813 acb->out_doorbell = 0; 4814 acb->rid[0] = rid0; 4815 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4816 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4817 } 4818 break; 4819 case ACB_ADAPTER_TYPE_F: { 4820 u_int32_t rid0 = PCIR_BAR(0); 4821 vm_offset_t mem_base0; 4822 unsigned long host_buffer_dma; 4823 4824 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4825 if(acb->sys_res_arcmsr[0] == NULL) { 4826 arcmsr_free_resource(acb); 4827 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4828 return ENOMEM; 4829 } 4830 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4831 arcmsr_free_resource(acb); 4832 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4833 return ENXIO; 4834 } 4835 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4836 if(mem_base0 == 0) { 4837 arcmsr_free_resource(acb); 4838 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4839 return ENXIO; 4840 } 4841 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4842 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4843 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4844 acb->doneq_index = 0; 4845 acb->in_doorbell = 0; 4846 acb->out_doorbell = 0; 4847 acb->rid[0] = rid0; 4848 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4849 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4850 arcmsr_wait_firmware_ready(acb); 4851 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4852 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4853 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4854 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4855 } 4856 break; 4857 } 4858 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4859 arcmsr_free_resource(acb); 4860 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4861 return ENXIO; 4862 } 4863 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4864 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4865 /* 4866 ******************************************************************** 4867 ** init raid volume state 4868 ******************************************************************** 4869 */ 4870 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4871 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4872 acb->devstate[i][j] = ARECA_RAID_GONE; 4873 } 4874 } 4875 arcmsr_iop_init(acb); 4876 return(0); 4877 } 4878 4879 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4880 { 4881 int i; 4882 4883 for (i = 0; i < acb->msix_vectors; i++) { 4884 acb->irq_id[i] = 1 + i; 4885 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4886 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4887 if (acb->irqres[i] == NULL) { 4888 printf("arcmsr: Can't allocate MSI-X resource\n"); 4889 goto irq_alloc_failed; 4890 } 4891 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4892 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4893 acb, &acb->ih[i])) { 4894 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4895 goto irq_alloc_failed; 4896 } 4897 } 4898 printf("arcmsr: MSI-X INT enabled\n"); 4899 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4900 return TRUE; 4901 4902 irq_alloc_failed: 4903 arcmsr_teardown_intr(acb->pci_dev, acb); 4904 return FALSE; 4905 } 4906 4907 /* 4908 ************************************************************************ 4909 ************************************************************************ 4910 */ 4911 static int arcmsr_attach(device_t dev) 4912 { 4913 struct make_dev_args args; 4914 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4915 u_int32_t unit=device_get_unit(dev); 4916 struct ccb_setasync csa; 4917 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4918 struct resource *irqres; 4919 4920 if(acb == NULL) { 4921 printf("arcmsr%d: cannot allocate softc\n", unit); 4922 return (ENOMEM); 4923 } 4924 arcmsr_mutex_init(acb); 4925 acb->pci_dev = dev; 4926 acb->pci_unit = unit; 4927 if(arcmsr_initialize(dev)) { 4928 printf("arcmsr%d: initialize failure!\n", unit); 4929 goto initialize_failed; 4930 } 4931 /* After setting up the adapter, map our interrupt */ 4932 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4933 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4934 if (arcmsr_setup_msix(acb) == TRUE) 4935 goto irqx; 4936 } 4937 acb->irq_id[0] = 0; 4938 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4939 if(irqres == NULL || 4940 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4941 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4942 goto setup_intr_failed; 4943 } 4944 acb->irqres[0] = irqres; 4945 irqx: 4946 /* 4947 * Now let the CAM generic SCSI layer find the SCSI devices on 4948 * the bus * start queue to reset to the idle loop. * 4949 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4950 * max_sim_transactions 4951 */ 4952 devq = cam_simq_alloc(acb->maxOutstanding); 4953 if(devq == NULL) { 4954 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4955 goto simq_alloc_failed; 4956 } 4957 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4958 if(acb->psim == NULL) { 4959 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4960 goto sim_alloc_failed; 4961 } 4962 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4963 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4964 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4965 goto xpt_bus_failed; 4966 } 4967 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4968 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4969 goto xpt_path_failed; 4970 } 4971 /* 4972 **************************************************** 4973 */ 4974 memset(&csa, 0, sizeof(csa)); 4975 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4976 csa.ccb_h.func_code = XPT_SASYNC_CB; 4977 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4978 csa.callback = arcmsr_async; 4979 csa.callback_arg = acb->psim; 4980 xpt_action((union ccb *)&csa); 4981 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4982 /* Create the control device. */ 4983 make_dev_args_init(&args); 4984 args.mda_devsw = &arcmsr_cdevsw; 4985 args.mda_uid = UID_ROOT; 4986 args.mda_gid = GID_WHEEL /* GID_OPERATOR */; 4987 args.mda_mode = S_IRUSR | S_IWUSR; 4988 args.mda_si_drv1 = acb; 4989 (void)make_dev_s(&args, &acb->ioctl_dev, "arcmsr%d", unit); 4990 4991 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4992 arcmsr_callout_init(&acb->devmap_callout); 4993 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4994 return (0); 4995 xpt_path_failed: 4996 xpt_bus_deregister(cam_sim_path(acb->psim)); 4997 xpt_bus_failed: 4998 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4999 sim_alloc_failed: 5000 cam_simq_free(devq); 5001 simq_alloc_failed: 5002 arcmsr_teardown_intr(dev, acb); 5003 setup_intr_failed: 5004 arcmsr_free_resource(acb); 5005 initialize_failed: 5006 arcmsr_mutex_destroy(acb); 5007 return ENXIO; 5008 } 5009 5010 /* 5011 ************************************************************************ 5012 ************************************************************************ 5013 */ 5014 static int arcmsr_probe(device_t dev) 5015 { 5016 u_int32_t id; 5017 u_int16_t sub_device_id; 5018 static char buf[256]; 5019 char x_type[]={"unknown"}; 5020 char *type; 5021 int raid6 = 1; 5022 5023 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 5024 return (ENXIO); 5025 } 5026 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5027 switch(id = pci_get_devid(dev)) { 5028 case PCIDevVenIDARC1110: 5029 case PCIDevVenIDARC1200: 5030 case PCIDevVenIDARC1201: 5031 case PCIDevVenIDARC1210: 5032 raid6 = 0; 5033 /*FALLTHRU*/ 5034 case PCIDevVenIDARC1120: 5035 case PCIDevVenIDARC1130: 5036 case PCIDevVenIDARC1160: 5037 case PCIDevVenIDARC1170: 5038 case PCIDevVenIDARC1220: 5039 case PCIDevVenIDARC1230: 5040 case PCIDevVenIDARC1231: 5041 case PCIDevVenIDARC1260: 5042 case PCIDevVenIDARC1261: 5043 case PCIDevVenIDARC1270: 5044 case PCIDevVenIDARC1280: 5045 type = "SATA 3G"; 5046 break; 5047 case PCIDevVenIDARC1212: 5048 case PCIDevVenIDARC1222: 5049 case PCIDevVenIDARC1380: 5050 case PCIDevVenIDARC1381: 5051 case PCIDevVenIDARC1680: 5052 case PCIDevVenIDARC1681: 5053 type = "SAS 3G"; 5054 break; 5055 case PCIDevVenIDARC1880: 5056 case PCIDevVenIDARC1882: 5057 case PCIDevVenIDARC1213: 5058 case PCIDevVenIDARC1223: 5059 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5060 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5061 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5062 type = "SAS 12G"; 5063 else 5064 type = "SAS 6G"; 5065 break; 5066 case PCIDevVenIDARC1884: 5067 type = "SAS 12G"; 5068 break; 5069 case PCIDevVenIDARC1886_: 5070 case PCIDevVenIDARC1886: 5071 type = "NVME,SAS-12G,SATA-6G"; 5072 break; 5073 case PCIDevVenIDARC1214: 5074 case PCIDevVenIDARC1203: 5075 type = "SATA 6G"; 5076 break; 5077 default: 5078 type = x_type; 5079 raid6 = 0; 5080 break; 5081 } 5082 if(type == x_type) 5083 return(ENXIO); 5084 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5085 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5086 device_set_desc_copy(dev, buf); 5087 return (BUS_PROBE_DEFAULT); 5088 } 5089 /* 5090 ************************************************************************ 5091 ************************************************************************ 5092 */ 5093 static int arcmsr_shutdown(device_t dev) 5094 { 5095 u_int32_t i; 5096 struct CommandControlBlock *srb; 5097 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5098 5099 /* stop adapter background rebuild */ 5100 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5101 /* disable all outbound interrupt */ 5102 arcmsr_disable_allintr(acb); 5103 arcmsr_stop_adapter_bgrb(acb); 5104 arcmsr_flush_adapter_cache(acb); 5105 /* abort all outstanding command */ 5106 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5107 acb->acb_flags &= ~ACB_F_IOP_INITED; 5108 if(acb->srboutstandingcount != 0) { 5109 /*clear and abort all outbound posted Q*/ 5110 arcmsr_done4abort_postqueue(acb); 5111 /* talk to iop 331 outstanding command aborted*/ 5112 arcmsr_abort_allcmd(acb); 5113 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5114 srb = acb->psrb_pool[i]; 5115 if(srb->srb_state == ARCMSR_SRB_START) { 5116 srb->srb_state = ARCMSR_SRB_ABORTED; 5117 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5118 arcmsr_srb_complete(srb, 1); 5119 } 5120 } 5121 } 5122 acb->srboutstandingcount = 0; 5123 acb->workingsrb_doneindex = 0; 5124 acb->workingsrb_startindex = 0; 5125 acb->pktRequestCount = 0; 5126 acb->pktReturnCount = 0; 5127 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5128 return (0); 5129 } 5130 /* 5131 ************************************************************************ 5132 ************************************************************************ 5133 */ 5134 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5135 { 5136 int i; 5137 5138 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5139 for (i = 0; i < acb->msix_vectors; i++) { 5140 if (acb->ih[i]) 5141 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5142 if (acb->irqres[i] != NULL) 5143 bus_release_resource(dev, SYS_RES_IRQ, 5144 acb->irq_id[i], acb->irqres[i]); 5145 5146 acb->ih[i] = NULL; 5147 } 5148 pci_release_msi(dev); 5149 } else { 5150 if (acb->ih[0]) 5151 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5152 if (acb->irqres[0] != NULL) 5153 bus_release_resource(dev, SYS_RES_IRQ, 5154 acb->irq_id[0], acb->irqres[0]); 5155 acb->ih[0] = NULL; 5156 } 5157 5158 } 5159 /* 5160 ************************************************************************ 5161 ************************************************************************ 5162 */ 5163 static int arcmsr_detach(device_t dev) 5164 { 5165 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5166 int i; 5167 5168 callout_stop(&acb->devmap_callout); 5169 arcmsr_teardown_intr(dev, acb); 5170 arcmsr_shutdown(dev); 5171 arcmsr_free_resource(acb); 5172 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5173 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5174 } 5175 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5176 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5177 xpt_free_path(acb->ppath); 5178 xpt_bus_deregister(cam_sim_path(acb->psim)); 5179 cam_sim_free(acb->psim, TRUE); 5180 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5181 arcmsr_mutex_destroy(acb); 5182 return (0); 5183 } 5184 5185 #ifdef ARCMSR_DEBUG1 5186 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5187 { 5188 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5189 return; 5190 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5191 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5192 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5193 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5194 } 5195 #endif
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