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sys/dev/arcmsr/arcmsr.c
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1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 13 ** 14 ** Redistribution and use in source and binary forms, with or without 15 ** modification, are permitted provided that the following conditions 16 ** are met: 17 ** 1. Redistributions of source code must retain the above copyright 18 ** notice, this list of conditions and the following disclaimer. 19 ** 2. Redistributions in binary form must reproduce the above copyright 20 ** notice, this list of conditions and the following disclaimer in the 21 ** documentation and/or other materials provided with the distribution. 22 ** 3. The name of the author may not be used to endorse or promote products 23 ** derived from this software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ******************************************************************************** 36 ** History 37 ** 38 ** REV# DATE NAME DESCRIPTION 39 ** 1.00.00.00 03/31/2004 Erich Chen First release 40 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 41 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 42 ** clean unused function 43 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 44 ** firmware version check 45 ** and firmware update notify for hardware bug fix 46 ** handling if none zero high part physical address 47 ** of srb resource 48 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 49 ** add iop message xfer 50 ** with scsi pass-through command 51 ** add new device id of sas raid adapters 52 ** code fit for SPARC64 & PPC 53 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 54 ** and cause g_vfs_done() read write error 55 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 56 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 57 ** bus_dmamem_alloc() with BUS_DMA_ZERO 58 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 59 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 60 ** prevent cam_periph_error removing all LUN devices of one Target id 61 ** for any one LUN device failed 62 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 63 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 64 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 65 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 66 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 67 ** 02/14/2011 Ching Huang Modified pktRequestCount 68 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 69 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 70 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 71 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 72 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 73 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 74 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 75 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 76 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 77 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 78 ****************************************************************************************** 79 */ 80 81 #include <sys/cdefs.h> 82 __FBSDID("$FreeBSD$"); 83 84 #if 0 85 #define ARCMSR_DEBUG1 1 86 #endif 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/bus.h> 92 #include <sys/queue.h> 93 #include <sys/stat.h> 94 #include <sys/devicestat.h> 95 #include <sys/kthread.h> 96 #include <sys/module.h> 97 #include <sys/proc.h> 98 #include <sys/lock.h> 99 #include <sys/sysctl.h> 100 #include <sys/poll.h> 101 #include <sys/ioccom.h> 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/pmap.h> 105 106 #include <isa/rtc.h> 107 108 #include <machine/bus.h> 109 #include <machine/resource.h> 110 #include <machine/atomic.h> 111 #include <sys/conf.h> 112 #include <sys/rman.h> 113 114 #include <cam/cam.h> 115 #include <cam/cam_ccb.h> 116 #include <cam/cam_sim.h> 117 #include <cam/cam_periph.h> 118 #include <cam/cam_xpt_periph.h> 119 #include <cam/cam_xpt_sim.h> 120 #include <cam/cam_debug.h> 121 #include <cam/scsi/scsi_all.h> 122 #include <cam/scsi/scsi_message.h> 123 /* 124 ************************************************************************** 125 ************************************************************************** 126 */ 127 #if __FreeBSD_version >= 500005 128 #include <sys/selinfo.h> 129 #include <sys/mutex.h> 130 #include <sys/endian.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/pcireg.h> 133 #else 134 #include <sys/select.h> 135 #include <pci/pcivar.h> 136 #include <pci/pcireg.h> 137 #endif 138 139 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 140 #define CAM_NEW_TRAN_CODE 1 141 #endif 142 143 #if __FreeBSD_version > 500000 144 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 145 #else 146 #define arcmsr_callout_init(a) callout_init(a); 147 #endif 148 149 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.20.00.28 2013-09-13" 150 #include <dev/arcmsr/arcmsr.h> 151 /* 152 ************************************************************************** 153 ************************************************************************** 154 */ 155 static void arcmsr_free_srb(struct CommandControlBlock *srb); 156 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 157 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 158 static int arcmsr_probe(device_t dev); 159 static int arcmsr_attach(device_t dev); 160 static int arcmsr_detach(device_t dev); 161 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 162 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 163 static int arcmsr_shutdown(device_t dev); 164 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 165 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 166 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 167 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 168 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 169 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 170 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 171 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 172 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 173 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 174 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 175 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 176 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 177 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 178 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 179 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 180 static int arcmsr_resume(device_t dev); 181 static int arcmsr_suspend(device_t dev); 182 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 183 static void arcmsr_polling_devmap(void *arg); 184 static void arcmsr_srb_timeout(void *arg); 185 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 186 #ifdef ARCMSR_DEBUG1 187 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 188 #endif 189 /* 190 ************************************************************************** 191 ************************************************************************** 192 */ 193 static void UDELAY(u_int32_t us) { DELAY(us); } 194 /* 195 ************************************************************************** 196 ************************************************************************** 197 */ 198 static bus_dmamap_callback_t arcmsr_map_free_srb; 199 static bus_dmamap_callback_t arcmsr_execute_srb; 200 /* 201 ************************************************************************** 202 ************************************************************************** 203 */ 204 static d_open_t arcmsr_open; 205 static d_close_t arcmsr_close; 206 static d_ioctl_t arcmsr_ioctl; 207 208 static device_method_t arcmsr_methods[]={ 209 DEVMETHOD(device_probe, arcmsr_probe), 210 DEVMETHOD(device_attach, arcmsr_attach), 211 DEVMETHOD(device_detach, arcmsr_detach), 212 DEVMETHOD(device_shutdown, arcmsr_shutdown), 213 DEVMETHOD(device_suspend, arcmsr_suspend), 214 DEVMETHOD(device_resume, arcmsr_resume), 215 216 #if __FreeBSD_version >= 803000 217 DEVMETHOD_END 218 #else 219 { 0, 0 } 220 #endif 221 }; 222 223 static driver_t arcmsr_driver={ 224 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 225 }; 226 227 static devclass_t arcmsr_devclass; 228 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 229 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 230 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 231 #ifndef BUS_DMA_COHERENT 232 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 233 #endif 234 #if __FreeBSD_version >= 501000 235 static struct cdevsw arcmsr_cdevsw={ 236 #if __FreeBSD_version >= 503000 237 .d_version = D_VERSION, 238 #endif 239 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 240 .d_flags = D_NEEDGIANT, 241 #endif 242 .d_open = arcmsr_open, /* open */ 243 .d_close = arcmsr_close, /* close */ 244 .d_ioctl = arcmsr_ioctl, /* ioctl */ 245 .d_name = "arcmsr", /* name */ 246 }; 247 #else 248 #define ARCMSR_CDEV_MAJOR 180 249 250 static struct cdevsw arcmsr_cdevsw = { 251 arcmsr_open, /* open */ 252 arcmsr_close, /* close */ 253 noread, /* read */ 254 nowrite, /* write */ 255 arcmsr_ioctl, /* ioctl */ 256 nopoll, /* poll */ 257 nommap, /* mmap */ 258 nostrategy, /* strategy */ 259 "arcmsr", /* name */ 260 ARCMSR_CDEV_MAJOR, /* major */ 261 nodump, /* dump */ 262 nopsize, /* psize */ 263 0 /* flags */ 264 }; 265 #endif 266 /* 267 ************************************************************************** 268 ************************************************************************** 269 */ 270 #if __FreeBSD_version < 500005 271 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 272 #else 273 #if __FreeBSD_version < 503000 274 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 275 #else 276 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 277 #endif 278 #endif 279 { 280 #if __FreeBSD_version < 503000 281 struct AdapterControlBlock *acb = dev->si_drv1; 282 #else 283 int unit = dev2unit(dev); 284 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 285 #endif 286 if(acb == NULL) { 287 return ENXIO; 288 } 289 return (0); 290 } 291 /* 292 ************************************************************************** 293 ************************************************************************** 294 */ 295 #if __FreeBSD_version < 500005 296 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 297 #else 298 #if __FreeBSD_version < 503000 299 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 300 #else 301 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 302 #endif 303 #endif 304 { 305 #if __FreeBSD_version < 503000 306 struct AdapterControlBlock *acb = dev->si_drv1; 307 #else 308 int unit = dev2unit(dev); 309 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 310 #endif 311 if(acb == NULL) { 312 return ENXIO; 313 } 314 return 0; 315 } 316 /* 317 ************************************************************************** 318 ************************************************************************** 319 */ 320 #if __FreeBSD_version < 500005 321 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 322 #else 323 #if __FreeBSD_version < 503000 324 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 325 #else 326 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 327 #endif 328 #endif 329 { 330 #if __FreeBSD_version < 503000 331 struct AdapterControlBlock *acb = dev->si_drv1; 332 #else 333 int unit = dev2unit(dev); 334 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 335 #endif 336 337 if(acb == NULL) { 338 return ENXIO; 339 } 340 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 341 } 342 /* 343 ********************************************************************** 344 ********************************************************************** 345 */ 346 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 347 { 348 u_int32_t intmask_org = 0; 349 350 switch (acb->adapter_type) { 351 case ACB_ADAPTER_TYPE_A: { 352 /* disable all outbound interrupt */ 353 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 354 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 355 } 356 break; 357 case ACB_ADAPTER_TYPE_B: { 358 /* disable all outbound interrupt */ 359 intmask_org = CHIP_REG_READ32(HBB_DOORBELL, 360 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 361 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 362 } 363 break; 364 case ACB_ADAPTER_TYPE_C: { 365 /* disable all outbound interrupt */ 366 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 367 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 368 } 369 break; 370 case ACB_ADAPTER_TYPE_D: { 371 /* disable all outbound interrupt */ 372 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 373 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 374 } 375 break; 376 } 377 return (intmask_org); 378 } 379 /* 380 ********************************************************************** 381 ********************************************************************** 382 */ 383 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 384 { 385 u_int32_t mask; 386 387 switch (acb->adapter_type) { 388 case ACB_ADAPTER_TYPE_A: { 389 /* enable outbound Post Queue, outbound doorbell Interrupt */ 390 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 391 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 392 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 393 } 394 break; 395 case ACB_ADAPTER_TYPE_B: { 396 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 397 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 398 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 399 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 400 } 401 break; 402 case ACB_ADAPTER_TYPE_C: { 403 /* enable outbound Post Queue, outbound doorbell Interrupt */ 404 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 405 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 406 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 407 } 408 break; 409 case ACB_ADAPTER_TYPE_D: { 410 /* enable outbound Post Queue, outbound doorbell Interrupt */ 411 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 412 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 413 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 414 acb->outbound_int_enable = mask; 415 } 416 break; 417 } 418 } 419 /* 420 ********************************************************************** 421 ********************************************************************** 422 */ 423 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 424 { 425 u_int32_t Index; 426 u_int8_t Retries = 0x00; 427 428 do { 429 for(Index=0; Index < 100; Index++) { 430 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 431 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 432 return TRUE; 433 } 434 UDELAY(10000); 435 }/*max 1 seconds*/ 436 }while(Retries++ < 20);/*max 20 sec*/ 437 return (FALSE); 438 } 439 /* 440 ********************************************************************** 441 ********************************************************************** 442 */ 443 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 444 { 445 u_int32_t Index; 446 u_int8_t Retries = 0x00; 447 448 do { 449 for(Index=0; Index < 100; Index++) { 450 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 451 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 452 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 453 return TRUE; 454 } 455 UDELAY(10000); 456 }/*max 1 seconds*/ 457 }while(Retries++ < 20);/*max 20 sec*/ 458 return (FALSE); 459 } 460 /* 461 ********************************************************************** 462 ********************************************************************** 463 */ 464 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 465 { 466 u_int32_t Index; 467 u_int8_t Retries = 0x00; 468 469 do { 470 for(Index=0; Index < 100; Index++) { 471 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 472 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 473 return TRUE; 474 } 475 UDELAY(10000); 476 }/*max 1 seconds*/ 477 }while(Retries++ < 20);/*max 20 sec*/ 478 return (FALSE); 479 } 480 /* 481 ********************************************************************** 482 ********************************************************************** 483 */ 484 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 485 { 486 u_int32_t Index; 487 u_int8_t Retries = 0x00; 488 489 do { 490 for(Index=0; Index < 100; Index++) { 491 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 492 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 493 return TRUE; 494 } 495 UDELAY(10000); 496 }/*max 1 seconds*/ 497 }while(Retries++ < 20);/*max 20 sec*/ 498 return (FALSE); 499 } 500 /* 501 ************************************************************************ 502 ************************************************************************ 503 */ 504 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 505 { 506 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 507 508 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 509 do { 510 if(arcmsr_hba_wait_msgint_ready(acb)) { 511 break; 512 } else { 513 retry_count--; 514 } 515 }while(retry_count != 0); 516 } 517 /* 518 ************************************************************************ 519 ************************************************************************ 520 */ 521 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 522 { 523 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 524 525 CHIP_REG_WRITE32(HBB_DOORBELL, 526 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 527 do { 528 if(arcmsr_hbb_wait_msgint_ready(acb)) { 529 break; 530 } else { 531 retry_count--; 532 } 533 }while(retry_count != 0); 534 } 535 /* 536 ************************************************************************ 537 ************************************************************************ 538 */ 539 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 540 { 541 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 542 543 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 544 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 545 do { 546 if(arcmsr_hbc_wait_msgint_ready(acb)) { 547 break; 548 } else { 549 retry_count--; 550 } 551 }while(retry_count != 0); 552 } 553 /* 554 ************************************************************************ 555 ************************************************************************ 556 */ 557 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 558 { 559 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 560 561 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 562 do { 563 if(arcmsr_hbd_wait_msgint_ready(acb)) { 564 break; 565 } else { 566 retry_count--; 567 } 568 }while(retry_count != 0); 569 } 570 /* 571 ************************************************************************ 572 ************************************************************************ 573 */ 574 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 575 { 576 switch (acb->adapter_type) { 577 case ACB_ADAPTER_TYPE_A: { 578 arcmsr_flush_hba_cache(acb); 579 } 580 break; 581 case ACB_ADAPTER_TYPE_B: { 582 arcmsr_flush_hbb_cache(acb); 583 } 584 break; 585 case ACB_ADAPTER_TYPE_C: { 586 arcmsr_flush_hbc_cache(acb); 587 } 588 break; 589 case ACB_ADAPTER_TYPE_D: { 590 arcmsr_flush_hbd_cache(acb); 591 } 592 break; 593 } 594 } 595 /* 596 ******************************************************************************* 597 ******************************************************************************* 598 */ 599 static int arcmsr_suspend(device_t dev) 600 { 601 struct AdapterControlBlock *acb = device_get_softc(dev); 602 603 /* flush controller */ 604 arcmsr_iop_parking(acb); 605 /* disable all outbound interrupt */ 606 arcmsr_disable_allintr(acb); 607 return(0); 608 } 609 /* 610 ******************************************************************************* 611 ******************************************************************************* 612 */ 613 static int arcmsr_resume(device_t dev) 614 { 615 struct AdapterControlBlock *acb = device_get_softc(dev); 616 617 arcmsr_iop_init(acb); 618 return(0); 619 } 620 /* 621 ********************************************************************************* 622 ********************************************************************************* 623 */ 624 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 625 { 626 struct AdapterControlBlock *acb; 627 u_int8_t target_id, target_lun; 628 struct cam_sim *sim; 629 630 sim = (struct cam_sim *) cb_arg; 631 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 632 switch (code) { 633 case AC_LOST_DEVICE: 634 target_id = xpt_path_target_id(path); 635 target_lun = xpt_path_lun_id(path); 636 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 637 break; 638 } 639 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 640 break; 641 default: 642 break; 643 } 644 } 645 /* 646 ********************************************************************** 647 ********************************************************************** 648 */ 649 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 650 { 651 union ccb *pccb = srb->pccb; 652 653 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 654 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 655 if(pccb->csio.sense_len) { 656 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 657 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 658 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 659 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 660 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 661 } 662 } 663 /* 664 ********************************************************************* 665 ********************************************************************* 666 */ 667 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 668 { 669 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 670 if(!arcmsr_hba_wait_msgint_ready(acb)) { 671 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 672 } 673 } 674 /* 675 ********************************************************************* 676 ********************************************************************* 677 */ 678 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 679 { 680 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 681 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 682 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 683 } 684 } 685 /* 686 ********************************************************************* 687 ********************************************************************* 688 */ 689 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 690 { 691 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 692 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 693 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 694 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 695 } 696 } 697 /* 698 ********************************************************************* 699 ********************************************************************* 700 */ 701 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 702 { 703 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 704 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 705 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 706 } 707 } 708 /* 709 ********************************************************************* 710 ********************************************************************* 711 */ 712 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 713 { 714 switch (acb->adapter_type) { 715 case ACB_ADAPTER_TYPE_A: { 716 arcmsr_abort_hba_allcmd(acb); 717 } 718 break; 719 case ACB_ADAPTER_TYPE_B: { 720 arcmsr_abort_hbb_allcmd(acb); 721 } 722 break; 723 case ACB_ADAPTER_TYPE_C: { 724 arcmsr_abort_hbc_allcmd(acb); 725 } 726 break; 727 case ACB_ADAPTER_TYPE_D: { 728 arcmsr_abort_hbd_allcmd(acb); 729 } 730 break; 731 } 732 } 733 /* 734 ********************************************************************** 735 ********************************************************************** 736 */ 737 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 738 { 739 struct AdapterControlBlock *acb = srb->acb; 740 union ccb *pccb = srb->pccb; 741 742 if(srb->srb_flags & SRB_FLAG_TIMER_START) 743 callout_stop(&srb->ccb_callout); 744 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 745 bus_dmasync_op_t op; 746 747 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 748 op = BUS_DMASYNC_POSTREAD; 749 } else { 750 op = BUS_DMASYNC_POSTWRITE; 751 } 752 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 753 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 754 } 755 if(stand_flag == 1) { 756 atomic_subtract_int(&acb->srboutstandingcount, 1); 757 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 758 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 759 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 760 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 761 } 762 } 763 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 764 arcmsr_free_srb(srb); 765 acb->pktReturnCount++; 766 xpt_done(pccb); 767 } 768 /* 769 ************************************************************************** 770 ************************************************************************** 771 */ 772 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 773 { 774 int target, lun; 775 776 target = srb->pccb->ccb_h.target_id; 777 lun = srb->pccb->ccb_h.target_lun; 778 if(error == FALSE) { 779 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 780 acb->devstate[target][lun] = ARECA_RAID_GOOD; 781 } 782 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 783 arcmsr_srb_complete(srb, 1); 784 } else { 785 switch(srb->arcmsr_cdb.DeviceStatus) { 786 case ARCMSR_DEV_SELECT_TIMEOUT: { 787 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 788 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 789 } 790 acb->devstate[target][lun] = ARECA_RAID_GONE; 791 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 792 arcmsr_srb_complete(srb, 1); 793 } 794 break; 795 case ARCMSR_DEV_ABORTED: 796 case ARCMSR_DEV_INIT_FAIL: { 797 acb->devstate[target][lun] = ARECA_RAID_GONE; 798 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 799 arcmsr_srb_complete(srb, 1); 800 } 801 break; 802 case SCSISTAT_CHECK_CONDITION: { 803 acb->devstate[target][lun] = ARECA_RAID_GOOD; 804 arcmsr_report_sense_info(srb); 805 arcmsr_srb_complete(srb, 1); 806 } 807 break; 808 default: 809 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknow DeviceStatus=0x%x \n" 810 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 811 acb->devstate[target][lun] = ARECA_RAID_GONE; 812 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 813 /*unknow error or crc error just for retry*/ 814 arcmsr_srb_complete(srb, 1); 815 break; 816 } 817 } 818 } 819 /* 820 ************************************************************************** 821 ************************************************************************** 822 */ 823 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 824 { 825 struct CommandControlBlock *srb; 826 827 /* check if command done with no error*/ 828 switch (acb->adapter_type) { 829 case ACB_ADAPTER_TYPE_C: 830 case ACB_ADAPTER_TYPE_D: 831 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 832 break; 833 case ACB_ADAPTER_TYPE_A: 834 case ACB_ADAPTER_TYPE_B: 835 default: 836 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 837 break; 838 } 839 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 840 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 841 arcmsr_free_srb(srb); 842 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 843 return; 844 } 845 printf("arcmsr%d: return srb has been completed\n" 846 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 847 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 848 return; 849 } 850 arcmsr_report_srb_state(acb, srb, error); 851 } 852 /* 853 ************************************************************************** 854 ************************************************************************** 855 */ 856 static void arcmsr_srb_timeout(void *arg) 857 { 858 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 859 struct AdapterControlBlock *acb; 860 int target, lun; 861 u_int8_t cmd; 862 863 target = srb->pccb->ccb_h.target_id; 864 lun = srb->pccb->ccb_h.target_lun; 865 acb = srb->acb; 866 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 867 if(srb->srb_state == ARCMSR_SRB_START) 868 { 869 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0]; 870 srb->srb_state = ARCMSR_SRB_TIMEOUT; 871 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 872 arcmsr_srb_complete(srb, 1); 873 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 874 acb->pci_unit, target, lun, cmd, srb); 875 } 876 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 877 #ifdef ARCMSR_DEBUG1 878 arcmsr_dump_data(acb); 879 #endif 880 } 881 882 /* 883 ********************************************************************** 884 ********************************************************************** 885 */ 886 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 887 { 888 int i=0; 889 u_int32_t flag_srb; 890 u_int16_t error; 891 892 switch (acb->adapter_type) { 893 case ACB_ADAPTER_TYPE_A: { 894 u_int32_t outbound_intstatus; 895 896 /*clear and abort all outbound posted Q*/ 897 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 898 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 899 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 900 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 901 arcmsr_drain_donequeue(acb, flag_srb, error); 902 } 903 } 904 break; 905 case ACB_ADAPTER_TYPE_B: { 906 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 907 908 /*clear all outbound posted Q*/ 909 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 910 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 911 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 912 phbbmu->done_qbuffer[i] = 0; 913 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 914 arcmsr_drain_donequeue(acb, flag_srb, error); 915 } 916 phbbmu->post_qbuffer[i] = 0; 917 }/*drain reply FIFO*/ 918 phbbmu->doneq_index = 0; 919 phbbmu->postq_index = 0; 920 } 921 break; 922 case ACB_ADAPTER_TYPE_C: { 923 924 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 925 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 926 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 927 arcmsr_drain_donequeue(acb, flag_srb, error); 928 } 929 } 930 break; 931 case ACB_ADAPTER_TYPE_D: { 932 arcmsr_hbd_postqueue_isr(acb); 933 } 934 break; 935 } 936 } 937 /* 938 **************************************************************************** 939 **************************************************************************** 940 */ 941 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 942 { 943 struct CommandControlBlock *srb; 944 u_int32_t intmask_org; 945 u_int32_t i=0; 946 947 if(acb->srboutstandingcount>0) { 948 /* disable all outbound interrupt */ 949 intmask_org = arcmsr_disable_allintr(acb); 950 /*clear and abort all outbound posted Q*/ 951 arcmsr_done4abort_postqueue(acb); 952 /* talk to iop 331 outstanding command aborted*/ 953 arcmsr_abort_allcmd(acb); 954 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 955 srb = acb->psrb_pool[i]; 956 if(srb->srb_state == ARCMSR_SRB_START) { 957 srb->srb_state = ARCMSR_SRB_ABORTED; 958 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 959 arcmsr_srb_complete(srb, 1); 960 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n" 961 , acb->pci_unit, srb->pccb->ccb_h.target_id 962 , srb->pccb->ccb_h.target_lun, srb); 963 } 964 } 965 /* enable all outbound interrupt */ 966 arcmsr_enable_allintr(acb, intmask_org); 967 } 968 acb->srboutstandingcount = 0; 969 acb->workingsrb_doneindex = 0; 970 acb->workingsrb_startindex = 0; 971 acb->pktRequestCount = 0; 972 acb->pktReturnCount = 0; 973 } 974 /* 975 ********************************************************************** 976 ********************************************************************** 977 */ 978 static void arcmsr_build_srb(struct CommandControlBlock *srb, 979 bus_dma_segment_t *dm_segs, u_int32_t nseg) 980 { 981 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 982 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 983 u_int32_t address_lo, address_hi; 984 union ccb *pccb = srb->pccb; 985 struct ccb_scsiio *pcsio = &pccb->csio; 986 u_int32_t arccdbsize = 0x30; 987 988 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 989 arcmsr_cdb->Bus = 0; 990 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 991 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 992 arcmsr_cdb->Function = 1; 993 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 994 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 995 if(nseg != 0) { 996 struct AdapterControlBlock *acb = srb->acb; 997 bus_dmasync_op_t op; 998 u_int32_t length, i, cdb_sgcount = 0; 999 1000 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1001 op = BUS_DMASYNC_PREREAD; 1002 } else { 1003 op = BUS_DMASYNC_PREWRITE; 1004 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1005 srb->srb_flags |= SRB_FLAG_WRITE; 1006 } 1007 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1008 for(i=0; i < nseg; i++) { 1009 /* Get the physical address of the current data pointer */ 1010 length = arcmsr_htole32(dm_segs[i].ds_len); 1011 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1012 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1013 if(address_hi == 0) { 1014 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1015 pdma_sg->address = address_lo; 1016 pdma_sg->length = length; 1017 psge += sizeof(struct SG32ENTRY); 1018 arccdbsize += sizeof(struct SG32ENTRY); 1019 } else { 1020 u_int32_t sg64s_size = 0, tmplength = length; 1021 1022 while(1) { 1023 u_int64_t span4G, length0; 1024 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1025 1026 span4G = (u_int64_t)address_lo + tmplength; 1027 pdma_sg->addresshigh = address_hi; 1028 pdma_sg->address = address_lo; 1029 if(span4G > 0x100000000) { 1030 /*see if cross 4G boundary*/ 1031 length0 = 0x100000000-address_lo; 1032 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1033 address_hi = address_hi+1; 1034 address_lo = 0; 1035 tmplength = tmplength - (u_int32_t)length0; 1036 sg64s_size += sizeof(struct SG64ENTRY); 1037 psge += sizeof(struct SG64ENTRY); 1038 cdb_sgcount++; 1039 } else { 1040 pdma_sg->length = tmplength | IS_SG64_ADDR; 1041 sg64s_size += sizeof(struct SG64ENTRY); 1042 psge += sizeof(struct SG64ENTRY); 1043 break; 1044 } 1045 } 1046 arccdbsize += sg64s_size; 1047 } 1048 cdb_sgcount++; 1049 } 1050 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1051 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1052 if( arccdbsize > 256) { 1053 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1054 } 1055 } else { 1056 arcmsr_cdb->DataLength = 0; 1057 } 1058 srb->arc_cdb_size = arccdbsize; 1059 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1060 } 1061 /* 1062 ************************************************************************** 1063 ************************************************************************** 1064 */ 1065 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1066 { 1067 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1068 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1069 1070 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1071 atomic_add_int(&acb->srboutstandingcount, 1); 1072 srb->srb_state = ARCMSR_SRB_START; 1073 1074 switch (acb->adapter_type) { 1075 case ACB_ADAPTER_TYPE_A: { 1076 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1077 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1078 } else { 1079 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1080 } 1081 } 1082 break; 1083 case ACB_ADAPTER_TYPE_B: { 1084 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1085 int ending_index, index; 1086 1087 index = phbbmu->postq_index; 1088 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1089 phbbmu->post_qbuffer[ending_index] = 0; 1090 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1091 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1092 } else { 1093 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1094 } 1095 index++; 1096 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1097 phbbmu->postq_index = index; 1098 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1099 } 1100 break; 1101 case ACB_ADAPTER_TYPE_C: { 1102 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1103 1104 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1105 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1106 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1107 if(cdb_phyaddr_hi32) 1108 { 1109 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1110 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1111 } 1112 else 1113 { 1114 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1115 } 1116 } 1117 break; 1118 case ACB_ADAPTER_TYPE_D: { 1119 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1120 u_int16_t index_stripped; 1121 u_int16_t postq_index; 1122 struct InBound_SRB *pinbound_srb; 1123 1124 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1125 postq_index = phbdmu->postq_index; 1126 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1127 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1128 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1129 pinbound_srb->length = srb->arc_cdb_size >> 2; 1130 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1131 if (postq_index & 0x4000) { 1132 index_stripped = postq_index & 0xFF; 1133 index_stripped += 1; 1134 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1135 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1136 } else { 1137 index_stripped = postq_index; 1138 index_stripped += 1; 1139 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1140 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1141 } 1142 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1143 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1144 } 1145 break; 1146 } 1147 } 1148 /* 1149 ************************************************************************ 1150 ************************************************************************ 1151 */ 1152 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1153 { 1154 struct QBUFFER *qbuffer=NULL; 1155 1156 switch (acb->adapter_type) { 1157 case ACB_ADAPTER_TYPE_A: { 1158 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1159 1160 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1161 } 1162 break; 1163 case ACB_ADAPTER_TYPE_B: { 1164 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1165 1166 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1167 } 1168 break; 1169 case ACB_ADAPTER_TYPE_C: { 1170 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1171 1172 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1173 } 1174 break; 1175 case ACB_ADAPTER_TYPE_D: { 1176 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1177 1178 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1179 } 1180 break; 1181 } 1182 return(qbuffer); 1183 } 1184 /* 1185 ************************************************************************ 1186 ************************************************************************ 1187 */ 1188 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1189 { 1190 struct QBUFFER *qbuffer = NULL; 1191 1192 switch (acb->adapter_type) { 1193 case ACB_ADAPTER_TYPE_A: { 1194 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1195 1196 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1197 } 1198 break; 1199 case ACB_ADAPTER_TYPE_B: { 1200 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1201 1202 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1203 } 1204 break; 1205 case ACB_ADAPTER_TYPE_C: { 1206 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1207 1208 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1209 } 1210 break; 1211 case ACB_ADAPTER_TYPE_D: { 1212 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1213 1214 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1215 } 1216 break; 1217 } 1218 return(qbuffer); 1219 } 1220 /* 1221 ************************************************************************** 1222 ************************************************************************** 1223 */ 1224 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1225 { 1226 switch (acb->adapter_type) { 1227 case ACB_ADAPTER_TYPE_A: { 1228 /* let IOP know data has been read */ 1229 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1230 } 1231 break; 1232 case ACB_ADAPTER_TYPE_B: { 1233 /* let IOP know data has been read */ 1234 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1235 } 1236 break; 1237 case ACB_ADAPTER_TYPE_C: { 1238 /* let IOP know data has been read */ 1239 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1240 } 1241 break; 1242 case ACB_ADAPTER_TYPE_D: { 1243 /* let IOP know data has been read */ 1244 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1245 } 1246 break; 1247 } 1248 } 1249 /* 1250 ************************************************************************** 1251 ************************************************************************** 1252 */ 1253 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1254 { 1255 switch (acb->adapter_type) { 1256 case ACB_ADAPTER_TYPE_A: { 1257 /* 1258 ** push inbound doorbell tell iop, driver data write ok 1259 ** and wait reply on next hwinterrupt for next Qbuffer post 1260 */ 1261 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1262 } 1263 break; 1264 case ACB_ADAPTER_TYPE_B: { 1265 /* 1266 ** push inbound doorbell tell iop, driver data write ok 1267 ** and wait reply on next hwinterrupt for next Qbuffer post 1268 */ 1269 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1270 } 1271 break; 1272 case ACB_ADAPTER_TYPE_C: { 1273 /* 1274 ** push inbound doorbell tell iop, driver data write ok 1275 ** and wait reply on next hwinterrupt for next Qbuffer post 1276 */ 1277 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1278 } 1279 break; 1280 case ACB_ADAPTER_TYPE_D: { 1281 /* 1282 ** push inbound doorbell tell iop, driver data write ok 1283 ** and wait reply on next hwinterrupt for next Qbuffer post 1284 */ 1285 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1286 } 1287 break; 1288 } 1289 } 1290 /* 1291 ************************************************************************ 1292 ************************************************************************ 1293 */ 1294 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1295 { 1296 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1297 CHIP_REG_WRITE32(HBA_MessageUnit, 1298 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1299 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1300 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1301 , acb->pci_unit); 1302 } 1303 } 1304 /* 1305 ************************************************************************ 1306 ************************************************************************ 1307 */ 1308 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1309 { 1310 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1311 CHIP_REG_WRITE32(HBB_DOORBELL, 1312 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1313 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1314 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1315 , acb->pci_unit); 1316 } 1317 } 1318 /* 1319 ************************************************************************ 1320 ************************************************************************ 1321 */ 1322 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1323 { 1324 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1325 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1326 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1327 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1328 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1329 } 1330 } 1331 /* 1332 ************************************************************************ 1333 ************************************************************************ 1334 */ 1335 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1336 { 1337 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1338 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1339 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1340 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1341 } 1342 } 1343 /* 1344 ************************************************************************ 1345 ************************************************************************ 1346 */ 1347 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1348 { 1349 switch (acb->adapter_type) { 1350 case ACB_ADAPTER_TYPE_A: { 1351 arcmsr_stop_hba_bgrb(acb); 1352 } 1353 break; 1354 case ACB_ADAPTER_TYPE_B: { 1355 arcmsr_stop_hbb_bgrb(acb); 1356 } 1357 break; 1358 case ACB_ADAPTER_TYPE_C: { 1359 arcmsr_stop_hbc_bgrb(acb); 1360 } 1361 break; 1362 case ACB_ADAPTER_TYPE_D: { 1363 arcmsr_stop_hbd_bgrb(acb); 1364 } 1365 break; 1366 } 1367 } 1368 /* 1369 ************************************************************************ 1370 ************************************************************************ 1371 */ 1372 static void arcmsr_poll(struct cam_sim *psim) 1373 { 1374 struct AdapterControlBlock *acb; 1375 int mutex; 1376 1377 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1378 mutex = mtx_owned(&acb->isr_lock); 1379 if( mutex == 0 ) 1380 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1381 arcmsr_interrupt(acb); 1382 if( mutex == 0 ) 1383 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1384 } 1385 /* 1386 ************************************************************************** 1387 ************************************************************************** 1388 */ 1389 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1390 struct QBUFFER *prbuffer) { 1391 1392 u_int8_t *pQbuffer; 1393 u_int8_t *buf1 = 0; 1394 u_int32_t *iop_data, *buf2 = 0; 1395 u_int32_t iop_len, data_len; 1396 1397 iop_data = (u_int32_t *)prbuffer->data; 1398 iop_len = (u_int32_t)prbuffer->data_len; 1399 if ( iop_len > 0 ) 1400 { 1401 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1402 buf2 = (u_int32_t *)buf1; 1403 if( buf1 == NULL) 1404 return (0); 1405 data_len = iop_len; 1406 while(data_len >= 4) 1407 { 1408 *buf2++ = *iop_data++; 1409 data_len -= 4; 1410 } 1411 if(data_len) 1412 *buf2 = *iop_data; 1413 buf2 = (u_int32_t *)buf1; 1414 } 1415 while (iop_len > 0) { 1416 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1417 *pQbuffer = *buf1; 1418 acb->rqbuf_lastindex++; 1419 /* if last, index number set it to 0 */ 1420 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1421 buf1++; 1422 iop_len--; 1423 } 1424 if(buf2) 1425 free( (u_int8_t *)buf2, M_DEVBUF); 1426 /* let IOP know data has been read */ 1427 arcmsr_iop_message_read(acb); 1428 return (1); 1429 } 1430 /* 1431 ************************************************************************** 1432 ************************************************************************** 1433 */ 1434 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1435 struct QBUFFER *prbuffer) { 1436 1437 u_int8_t *pQbuffer; 1438 u_int8_t *iop_data; 1439 u_int32_t iop_len; 1440 1441 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) { 1442 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1443 } 1444 iop_data = (u_int8_t *)prbuffer->data; 1445 iop_len = (u_int32_t)prbuffer->data_len; 1446 while (iop_len > 0) { 1447 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1448 *pQbuffer = *iop_data; 1449 acb->rqbuf_lastindex++; 1450 /* if last, index number set it to 0 */ 1451 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1452 iop_data++; 1453 iop_len--; 1454 } 1455 /* let IOP know data has been read */ 1456 arcmsr_iop_message_read(acb); 1457 return (1); 1458 } 1459 /* 1460 ************************************************************************** 1461 ************************************************************************** 1462 */ 1463 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1464 { 1465 struct QBUFFER *prbuffer; 1466 int my_empty_len; 1467 1468 /*check this iop data if overflow my rqbuffer*/ 1469 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1470 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1471 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1472 (ARCMSR_MAX_QBUFFER-1); 1473 if(my_empty_len >= prbuffer->data_len) { 1474 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1475 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1476 } else { 1477 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1478 } 1479 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1480 } 1481 /* 1482 ********************************************************************** 1483 ********************************************************************** 1484 */ 1485 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1486 { 1487 u_int8_t *pQbuffer; 1488 struct QBUFFER *pwbuffer; 1489 u_int8_t *buf1 = 0; 1490 u_int32_t *iop_data, *buf2 = 0; 1491 u_int32_t allxfer_len = 0, data_len; 1492 1493 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1494 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1495 buf2 = (u_int32_t *)buf1; 1496 if( buf1 == NULL) 1497 return; 1498 1499 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1500 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1501 iop_data = (u_int32_t *)pwbuffer->data; 1502 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1503 && (allxfer_len < 124)) { 1504 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1505 *buf1 = *pQbuffer; 1506 acb->wqbuf_firstindex++; 1507 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1508 buf1++; 1509 allxfer_len++; 1510 } 1511 pwbuffer->data_len = allxfer_len; 1512 data_len = allxfer_len; 1513 buf1 = (u_int8_t *)buf2; 1514 while(data_len >= 4) 1515 { 1516 *iop_data++ = *buf2++; 1517 data_len -= 4; 1518 } 1519 if(data_len) 1520 *iop_data = *buf2; 1521 free( buf1, M_DEVBUF); 1522 arcmsr_iop_message_wrote(acb); 1523 } 1524 } 1525 /* 1526 ********************************************************************** 1527 ********************************************************************** 1528 */ 1529 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1530 { 1531 u_int8_t *pQbuffer; 1532 struct QBUFFER *pwbuffer; 1533 u_int8_t *iop_data; 1534 int32_t allxfer_len=0; 1535 1536 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) { 1537 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1538 return; 1539 } 1540 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1541 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1542 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1543 iop_data = (u_int8_t *)pwbuffer->data; 1544 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1545 && (allxfer_len < 124)) { 1546 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1547 *iop_data = *pQbuffer; 1548 acb->wqbuf_firstindex++; 1549 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1550 iop_data++; 1551 allxfer_len++; 1552 } 1553 pwbuffer->data_len = allxfer_len; 1554 arcmsr_iop_message_wrote(acb); 1555 } 1556 } 1557 /* 1558 ************************************************************************** 1559 ************************************************************************** 1560 */ 1561 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1562 { 1563 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1564 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1565 /* 1566 ***************************************************************** 1567 ** check if there are any mail packages from user space program 1568 ** in my post bag, now is the time to send them into Areca's firmware 1569 ***************************************************************** 1570 */ 1571 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1572 arcmsr_Write_data_2iop_wqbuffer(acb); 1573 } 1574 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1575 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1576 } 1577 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1578 } 1579 /* 1580 ************************************************************************** 1581 ************************************************************************** 1582 */ 1583 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1584 { 1585 /* 1586 if (ccb->ccb_h.status != CAM_REQ_CMP) 1587 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1588 "failure status=%x\n", ccb->ccb_h.target_id, 1589 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1590 else 1591 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1592 */ 1593 xpt_free_path(ccb->ccb_h.path); 1594 xpt_free_ccb(ccb); 1595 } 1596 1597 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1598 { 1599 struct cam_path *path; 1600 union ccb *ccb; 1601 1602 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1603 return; 1604 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) 1605 != CAM_REQ_CMP) 1606 { 1607 xpt_free_ccb(ccb); 1608 return; 1609 } 1610 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1611 bzero(ccb, sizeof(union ccb)); 1612 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1613 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1614 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1615 ccb->crcn.flags = CAM_FLAG_NONE; 1616 xpt_action(ccb); 1617 } 1618 1619 1620 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1621 { 1622 struct CommandControlBlock *srb; 1623 u_int32_t intmask_org; 1624 int i; 1625 1626 /* disable all outbound interrupts */ 1627 intmask_org = arcmsr_disable_allintr(acb); 1628 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1629 { 1630 srb = acb->psrb_pool[i]; 1631 if (srb->srb_state == ARCMSR_SRB_START) 1632 { 1633 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1634 { 1635 srb->srb_state = ARCMSR_SRB_ABORTED; 1636 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1637 arcmsr_srb_complete(srb, 1); 1638 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1639 } 1640 } 1641 } 1642 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1643 arcmsr_enable_allintr(acb, intmask_org); 1644 } 1645 /* 1646 ************************************************************************** 1647 ************************************************************************** 1648 */ 1649 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1650 u_int32_t devicemap; 1651 u_int32_t target, lun; 1652 u_int32_t deviceMapCurrent[4]={0}; 1653 u_int8_t *pDevMap; 1654 1655 switch (acb->adapter_type) { 1656 case ACB_ADAPTER_TYPE_A: 1657 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1658 for (target = 0; target < 4; target++) 1659 { 1660 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1661 devicemap += 4; 1662 } 1663 break; 1664 1665 case ACB_ADAPTER_TYPE_B: 1666 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1667 for (target = 0; target < 4; target++) 1668 { 1669 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1670 devicemap += 4; 1671 } 1672 break; 1673 1674 case ACB_ADAPTER_TYPE_C: 1675 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1676 for (target = 0; target < 4; target++) 1677 { 1678 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1679 devicemap += 4; 1680 } 1681 break; 1682 case ACB_ADAPTER_TYPE_D: 1683 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1684 for (target = 0; target < 4; target++) 1685 { 1686 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1687 devicemap += 4; 1688 } 1689 break; 1690 } 1691 1692 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1693 { 1694 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1695 } 1696 /* 1697 ** adapter posted CONFIG message 1698 ** copy the new map, note if there are differences with the current map 1699 */ 1700 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1701 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1702 { 1703 if (*pDevMap != acb->device_map[target]) 1704 { 1705 u_int8_t difference, bit_check; 1706 1707 difference = *pDevMap ^ acb->device_map[target]; 1708 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1709 { 1710 bit_check = (1 << lun); /*check bit from 0....31*/ 1711 if(difference & bit_check) 1712 { 1713 if(acb->device_map[target] & bit_check) 1714 {/* unit departed */ 1715 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1716 arcmsr_abort_dr_ccbs(acb, target, lun); 1717 arcmsr_rescan_lun(acb, target, lun); 1718 acb->devstate[target][lun] = ARECA_RAID_GONE; 1719 } 1720 else 1721 {/* unit arrived */ 1722 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1723 arcmsr_rescan_lun(acb, target, lun); 1724 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1725 } 1726 } 1727 } 1728 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1729 acb->device_map[target] = *pDevMap; 1730 } 1731 pDevMap++; 1732 } 1733 } 1734 /* 1735 ************************************************************************** 1736 ************************************************************************** 1737 */ 1738 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1739 u_int32_t outbound_message; 1740 1741 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1742 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1743 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1744 arcmsr_dr_handle( acb ); 1745 } 1746 /* 1747 ************************************************************************** 1748 ************************************************************************** 1749 */ 1750 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1751 u_int32_t outbound_message; 1752 1753 /* clear interrupts */ 1754 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1755 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1756 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1757 arcmsr_dr_handle( acb ); 1758 } 1759 /* 1760 ************************************************************************** 1761 ************************************************************************** 1762 */ 1763 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1764 u_int32_t outbound_message; 1765 1766 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1767 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1768 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1769 arcmsr_dr_handle( acb ); 1770 } 1771 /* 1772 ************************************************************************** 1773 ************************************************************************** 1774 */ 1775 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1776 u_int32_t outbound_message; 1777 1778 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1779 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1780 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1781 arcmsr_dr_handle( acb ); 1782 } 1783 /* 1784 ************************************************************************** 1785 ************************************************************************** 1786 */ 1787 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1788 { 1789 u_int32_t outbound_doorbell; 1790 1791 /* 1792 ******************************************************************* 1793 ** Maybe here we need to check wrqbuffer_lock is lock or not 1794 ** DOORBELL: din! don! 1795 ** check if there are any mail need to pack from firmware 1796 ******************************************************************* 1797 */ 1798 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 1799 0, outbound_doorbell); 1800 CHIP_REG_WRITE32(HBA_MessageUnit, 1801 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */ 1802 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1803 arcmsr_iop2drv_data_wrote_handle(acb); 1804 } 1805 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1806 arcmsr_iop2drv_data_read_handle(acb); 1807 } 1808 } 1809 /* 1810 ************************************************************************** 1811 ************************************************************************** 1812 */ 1813 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1814 { 1815 u_int32_t outbound_doorbell; 1816 1817 /* 1818 ******************************************************************* 1819 ** Maybe here we need to check wrqbuffer_lock is lock or not 1820 ** DOORBELL: din! don! 1821 ** check if there are any mail need to pack from firmware 1822 ******************************************************************* 1823 */ 1824 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1825 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */ 1826 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1827 arcmsr_iop2drv_data_wrote_handle(acb); 1828 } 1829 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1830 arcmsr_iop2drv_data_read_handle(acb); 1831 } 1832 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1833 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1834 } 1835 } 1836 /* 1837 ************************************************************************** 1838 ************************************************************************** 1839 */ 1840 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1841 { 1842 u_int32_t outbound_Doorbell; 1843 1844 /* 1845 ******************************************************************* 1846 ** Maybe here we need to check wrqbuffer_lock is lock or not 1847 ** DOORBELL: din! don! 1848 ** check if there are any mail need to pack from firmware 1849 ******************************************************************* 1850 */ 1851 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1852 if(outbound_Doorbell) 1853 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1854 while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1855 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1856 arcmsr_iop2drv_data_wrote_handle(acb); 1857 } 1858 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1859 arcmsr_iop2drv_data_read_handle(acb); 1860 } 1861 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1862 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1863 } 1864 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1865 if(outbound_Doorbell) 1866 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1867 } 1868 } 1869 /* 1870 ************************************************************************** 1871 ************************************************************************** 1872 */ 1873 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1874 { 1875 u_int32_t flag_srb; 1876 u_int16_t error; 1877 1878 /* 1879 ***************************************************************************** 1880 ** areca cdb command done 1881 ***************************************************************************** 1882 */ 1883 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1884 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1885 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 1886 0, outbound_queueport)) != 0xFFFFFFFF) { 1887 /* check if command done with no error*/ 1888 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 1889 arcmsr_drain_donequeue(acb, flag_srb, error); 1890 } /*drain reply FIFO*/ 1891 } 1892 /* 1893 ************************************************************************** 1894 ************************************************************************** 1895 */ 1896 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1897 { 1898 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1899 u_int32_t flag_srb; 1900 int index; 1901 u_int16_t error; 1902 1903 /* 1904 ***************************************************************************** 1905 ** areca cdb command done 1906 ***************************************************************************** 1907 */ 1908 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1909 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1910 index = phbbmu->doneq_index; 1911 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 1912 phbbmu->done_qbuffer[index] = 0; 1913 index++; 1914 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1915 phbbmu->doneq_index = index; 1916 /* check if command done with no error*/ 1917 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1918 arcmsr_drain_donequeue(acb, flag_srb, error); 1919 } /*drain reply FIFO*/ 1920 } 1921 /* 1922 ************************************************************************** 1923 ************************************************************************** 1924 */ 1925 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1926 { 1927 u_int32_t flag_srb,throttling = 0; 1928 u_int16_t error; 1929 1930 /* 1931 ***************************************************************************** 1932 ** areca cdb command done 1933 ***************************************************************************** 1934 */ 1935 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1936 1937 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1938 1939 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1940 /* check if command done with no error*/ 1941 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1942 arcmsr_drain_donequeue(acb, flag_srb, error); 1943 throttling++; 1944 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1945 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1946 throttling = 0; 1947 } 1948 } /*drain reply FIFO*/ 1949 } 1950 /* 1951 ********************************************************************** 1952 ** 1953 ********************************************************************** 1954 */ 1955 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 1956 { 1957 uint16_t doneq_index, index_stripped; 1958 1959 doneq_index = phbdmu->doneq_index; 1960 if (doneq_index & 0x4000) { 1961 index_stripped = doneq_index & 0xFF; 1962 index_stripped += 1; 1963 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1964 phbdmu->doneq_index = index_stripped ? 1965 (index_stripped | 0x4000) : index_stripped; 1966 } else { 1967 index_stripped = doneq_index; 1968 index_stripped += 1; 1969 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1970 phbdmu->doneq_index = index_stripped ? 1971 index_stripped : (index_stripped | 0x4000); 1972 } 1973 return (phbdmu->doneq_index); 1974 } 1975 /* 1976 ************************************************************************** 1977 ************************************************************************** 1978 */ 1979 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 1980 { 1981 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1982 u_int32_t outbound_write_pointer; 1983 u_int32_t addressLow; 1984 uint16_t doneq_index; 1985 u_int16_t error; 1986 /* 1987 ***************************************************************************** 1988 ** areca cdb command done 1989 ***************************************************************************** 1990 */ 1991 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 1992 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 1993 return; 1994 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1995 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1996 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 1997 doneq_index = phbdmu->doneq_index; 1998 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 1999 doneq_index = arcmsr_get_doneq_index(phbdmu); 2000 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2001 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2002 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2003 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2004 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2005 } 2006 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2007 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2008 } 2009 /* 2010 ********************************************************************** 2011 ********************************************************************** 2012 */ 2013 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2014 { 2015 u_int32_t outbound_intStatus; 2016 /* 2017 ********************************************* 2018 ** check outbound intstatus 2019 ********************************************* 2020 */ 2021 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2022 if(!outbound_intStatus) { 2023 /*it must be share irq*/ 2024 return; 2025 } 2026 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2027 /* MU doorbell interrupts*/ 2028 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2029 arcmsr_hba_doorbell_isr(acb); 2030 } 2031 /* MU post queue interrupts*/ 2032 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2033 arcmsr_hba_postqueue_isr(acb); 2034 } 2035 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2036 arcmsr_hba_message_isr(acb); 2037 } 2038 } 2039 /* 2040 ********************************************************************** 2041 ********************************************************************** 2042 */ 2043 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2044 { 2045 u_int32_t outbound_doorbell; 2046 /* 2047 ********************************************* 2048 ** check outbound intstatus 2049 ********************************************* 2050 */ 2051 outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 2052 if(!outbound_doorbell) { 2053 /*it must be share irq*/ 2054 return; 2055 } 2056 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2057 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 2058 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2059 /* MU ioctl transfer doorbell interrupts*/ 2060 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2061 arcmsr_iop2drv_data_wrote_handle(acb); 2062 } 2063 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2064 arcmsr_iop2drv_data_read_handle(acb); 2065 } 2066 /* MU post queue interrupts*/ 2067 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2068 arcmsr_hbb_postqueue_isr(acb); 2069 } 2070 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2071 arcmsr_hbb_message_isr(acb); 2072 } 2073 } 2074 /* 2075 ********************************************************************** 2076 ********************************************************************** 2077 */ 2078 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2079 { 2080 u_int32_t host_interrupt_status; 2081 /* 2082 ********************************************* 2083 ** check outbound intstatus 2084 ********************************************* 2085 */ 2086 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2087 if(!host_interrupt_status) { 2088 /*it must be share irq*/ 2089 return; 2090 } 2091 /* MU doorbell interrupts*/ 2092 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2093 arcmsr_hbc_doorbell_isr(acb); 2094 } 2095 /* MU post queue interrupts*/ 2096 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2097 arcmsr_hbc_postqueue_isr(acb); 2098 } 2099 } 2100 /* 2101 ********************************************************************** 2102 ********************************************************************** 2103 */ 2104 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2105 { 2106 u_int32_t host_interrupt_status; 2107 u_int32_t intmask_org; 2108 /* 2109 ********************************************* 2110 ** check outbound intstatus 2111 ********************************************* 2112 */ 2113 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2114 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2115 /*it must be share irq*/ 2116 return; 2117 } 2118 /* disable outbound interrupt */ 2119 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2120 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2121 /* MU doorbell interrupts*/ 2122 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2123 arcmsr_hbd_doorbell_isr(acb); 2124 } 2125 /* MU post queue interrupts*/ 2126 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2127 arcmsr_hbd_postqueue_isr(acb); 2128 } 2129 /* enable all outbound interrupt */ 2130 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2131 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2132 } 2133 /* 2134 ****************************************************************************** 2135 ****************************************************************************** 2136 */ 2137 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2138 { 2139 switch (acb->adapter_type) { 2140 case ACB_ADAPTER_TYPE_A: 2141 arcmsr_handle_hba_isr(acb); 2142 break; 2143 case ACB_ADAPTER_TYPE_B: 2144 arcmsr_handle_hbb_isr(acb); 2145 break; 2146 case ACB_ADAPTER_TYPE_C: 2147 arcmsr_handle_hbc_isr(acb); 2148 break; 2149 case ACB_ADAPTER_TYPE_D: 2150 arcmsr_handle_hbd_isr(acb); 2151 break; 2152 default: 2153 printf("arcmsr%d: interrupt service," 2154 " unknow adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2155 break; 2156 } 2157 } 2158 /* 2159 ********************************************************************** 2160 ********************************************************************** 2161 */ 2162 static void arcmsr_intr_handler(void *arg) 2163 { 2164 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2165 2166 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2167 arcmsr_interrupt(acb); 2168 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2169 } 2170 /* 2171 ****************************************************************************** 2172 ****************************************************************************** 2173 */ 2174 static void arcmsr_polling_devmap(void *arg) 2175 { 2176 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2177 switch (acb->adapter_type) { 2178 case ACB_ADAPTER_TYPE_A: 2179 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2180 break; 2181 2182 case ACB_ADAPTER_TYPE_B: 2183 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2184 break; 2185 2186 case ACB_ADAPTER_TYPE_C: 2187 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2188 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2189 break; 2190 2191 case ACB_ADAPTER_TYPE_D: 2192 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2193 break; 2194 } 2195 2196 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2197 { 2198 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2199 } 2200 } 2201 2202 /* 2203 ******************************************************************************* 2204 ** 2205 ******************************************************************************* 2206 */ 2207 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2208 { 2209 u_int32_t intmask_org; 2210 2211 if(acb != NULL) { 2212 /* stop adapter background rebuild */ 2213 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2214 intmask_org = arcmsr_disable_allintr(acb); 2215 arcmsr_stop_adapter_bgrb(acb); 2216 arcmsr_flush_adapter_cache(acb); 2217 arcmsr_enable_allintr(acb, intmask_org); 2218 } 2219 } 2220 } 2221 /* 2222 *********************************************************************** 2223 ** 2224 ************************************************************************ 2225 */ 2226 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2227 { 2228 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2229 u_int32_t retvalue = EINVAL; 2230 2231 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2232 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2233 return retvalue; 2234 } 2235 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2236 switch(ioctl_cmd) { 2237 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2238 u_int8_t *pQbuffer; 2239 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2240 u_int32_t allxfer_len=0; 2241 2242 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2243 && (allxfer_len < 1031)) { 2244 /*copy READ QBUFFER to srb*/ 2245 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2246 *ptmpQbuffer = *pQbuffer; 2247 acb->rqbuf_firstindex++; 2248 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2249 /*if last index number set it to 0 */ 2250 ptmpQbuffer++; 2251 allxfer_len++; 2252 } 2253 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2254 struct QBUFFER *prbuffer; 2255 2256 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2257 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2258 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2259 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2260 } 2261 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2262 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2263 retvalue = ARCMSR_MESSAGE_SUCCESS; 2264 } 2265 break; 2266 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2267 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2268 u_int8_t *pQbuffer; 2269 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2270 2271 user_len = pcmdmessagefld->cmdmessage.Length; 2272 /*check if data xfer length of this request will overflow my array qbuffer */ 2273 wqbuf_lastindex = acb->wqbuf_lastindex; 2274 wqbuf_firstindex = acb->wqbuf_firstindex; 2275 if(wqbuf_lastindex != wqbuf_firstindex) { 2276 arcmsr_Write_data_2iop_wqbuffer(acb); 2277 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2278 } else { 2279 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2280 (ARCMSR_MAX_QBUFFER - 1); 2281 if(my_empty_len >= user_len) { 2282 while(user_len > 0) { 2283 /*copy srb data to wqbuffer*/ 2284 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2285 *pQbuffer = *ptmpuserbuffer; 2286 acb->wqbuf_lastindex++; 2287 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2288 /*if last index number set it to 0 */ 2289 ptmpuserbuffer++; 2290 user_len--; 2291 } 2292 /*post fist Qbuffer*/ 2293 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2294 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2295 arcmsr_Write_data_2iop_wqbuffer(acb); 2296 } 2297 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2298 } else { 2299 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2300 } 2301 } 2302 retvalue = ARCMSR_MESSAGE_SUCCESS; 2303 } 2304 break; 2305 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2306 u_int8_t *pQbuffer = acb->rqbuffer; 2307 2308 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2309 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2310 arcmsr_iop_message_read(acb); 2311 /*signature, let IOP know data has been readed */ 2312 } 2313 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2314 acb->rqbuf_firstindex = 0; 2315 acb->rqbuf_lastindex = 0; 2316 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2317 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2318 retvalue = ARCMSR_MESSAGE_SUCCESS; 2319 } 2320 break; 2321 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2322 { 2323 u_int8_t *pQbuffer = acb->wqbuffer; 2324 2325 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2326 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2327 arcmsr_iop_message_read(acb); 2328 /*signature, let IOP know data has been readed */ 2329 } 2330 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2331 acb->wqbuf_firstindex = 0; 2332 acb->wqbuf_lastindex = 0; 2333 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2334 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2335 retvalue = ARCMSR_MESSAGE_SUCCESS; 2336 } 2337 break; 2338 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2339 u_int8_t *pQbuffer; 2340 2341 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2342 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2343 arcmsr_iop_message_read(acb); 2344 /*signature, let IOP know data has been readed */ 2345 } 2346 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2347 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2348 |ACB_F_MESSAGE_WQBUFFER_READ); 2349 acb->rqbuf_firstindex = 0; 2350 acb->rqbuf_lastindex = 0; 2351 acb->wqbuf_firstindex = 0; 2352 acb->wqbuf_lastindex = 0; 2353 pQbuffer = acb->rqbuffer; 2354 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2355 pQbuffer = acb->wqbuffer; 2356 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2357 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2358 retvalue = ARCMSR_MESSAGE_SUCCESS; 2359 } 2360 break; 2361 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2362 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2363 retvalue = ARCMSR_MESSAGE_SUCCESS; 2364 } 2365 break; 2366 case ARCMSR_MESSAGE_SAY_HELLO: { 2367 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2368 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2369 2370 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2371 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2372 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2373 return ENOIOCTL; 2374 } 2375 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2376 retvalue = ARCMSR_MESSAGE_SUCCESS; 2377 } 2378 break; 2379 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2380 arcmsr_iop_parking(acb); 2381 retvalue = ARCMSR_MESSAGE_SUCCESS; 2382 } 2383 break; 2384 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2385 arcmsr_flush_adapter_cache(acb); 2386 retvalue = ARCMSR_MESSAGE_SUCCESS; 2387 } 2388 break; 2389 } 2390 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2391 return (retvalue); 2392 } 2393 /* 2394 ************************************************************************** 2395 ************************************************************************** 2396 */ 2397 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2398 { 2399 struct AdapterControlBlock *acb; 2400 2401 acb = srb->acb; 2402 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2403 srb->srb_state = ARCMSR_SRB_DONE; 2404 srb->srb_flags = 0; 2405 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2406 acb->workingsrb_doneindex++; 2407 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2408 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2409 } 2410 /* 2411 ************************************************************************** 2412 ************************************************************************** 2413 */ 2414 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2415 { 2416 struct CommandControlBlock *srb = NULL; 2417 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2418 2419 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2420 workingsrb_doneindex = acb->workingsrb_doneindex; 2421 workingsrb_startindex = acb->workingsrb_startindex; 2422 srb = acb->srbworkingQ[workingsrb_startindex]; 2423 workingsrb_startindex++; 2424 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2425 if(workingsrb_doneindex != workingsrb_startindex) { 2426 acb->workingsrb_startindex = workingsrb_startindex; 2427 } else { 2428 srb = NULL; 2429 } 2430 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2431 return(srb); 2432 } 2433 /* 2434 ************************************************************************** 2435 ************************************************************************** 2436 */ 2437 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2438 { 2439 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2440 int retvalue = 0, transfer_len = 0; 2441 char *buffer; 2442 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2443 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2444 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2445 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2446 /* 4 bytes: Areca io control code */ 2447 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2448 buffer = pccb->csio.data_ptr; 2449 transfer_len = pccb->csio.dxfer_len; 2450 } else { 2451 retvalue = ARCMSR_MESSAGE_FAIL; 2452 goto message_out; 2453 } 2454 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2455 retvalue = ARCMSR_MESSAGE_FAIL; 2456 goto message_out; 2457 } 2458 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2459 switch(controlcode) { 2460 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2461 u_int8_t *pQbuffer; 2462 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2463 int32_t allxfer_len = 0; 2464 2465 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2466 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2467 && (allxfer_len < 1031)) { 2468 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2469 *ptmpQbuffer = *pQbuffer; 2470 acb->rqbuf_firstindex++; 2471 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2472 ptmpQbuffer++; 2473 allxfer_len++; 2474 } 2475 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2476 struct QBUFFER *prbuffer; 2477 2478 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2479 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2480 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2481 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2482 } 2483 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2484 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2485 retvalue = ARCMSR_MESSAGE_SUCCESS; 2486 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2487 } 2488 break; 2489 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2490 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2491 u_int8_t *pQbuffer; 2492 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2493 2494 user_len = pcmdmessagefld->cmdmessage.Length; 2495 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2496 wqbuf_lastindex = acb->wqbuf_lastindex; 2497 wqbuf_firstindex = acb->wqbuf_firstindex; 2498 if (wqbuf_lastindex != wqbuf_firstindex) { 2499 arcmsr_Write_data_2iop_wqbuffer(acb); 2500 /* has error report sensedata */ 2501 if(pccb->csio.sense_len) { 2502 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2503 /* Valid,ErrorCode */ 2504 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2505 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2506 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2507 /* AdditionalSenseLength */ 2508 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2509 /* AdditionalSenseCode */ 2510 } 2511 retvalue = ARCMSR_MESSAGE_FAIL; 2512 } else { 2513 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2514 &(ARCMSR_MAX_QBUFFER - 1); 2515 if (my_empty_len >= user_len) { 2516 while (user_len > 0) { 2517 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2518 *pQbuffer = *ptmpuserbuffer; 2519 acb->wqbuf_lastindex++; 2520 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2521 ptmpuserbuffer++; 2522 user_len--; 2523 } 2524 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2525 acb->acb_flags &= 2526 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2527 arcmsr_Write_data_2iop_wqbuffer(acb); 2528 } 2529 } else { 2530 /* has error report sensedata */ 2531 if(pccb->csio.sense_len) { 2532 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2533 /* Valid,ErrorCode */ 2534 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2535 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2536 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2537 /* AdditionalSenseLength */ 2538 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2539 /* AdditionalSenseCode */ 2540 } 2541 retvalue = ARCMSR_MESSAGE_FAIL; 2542 } 2543 } 2544 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2545 } 2546 break; 2547 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2548 u_int8_t *pQbuffer = acb->rqbuffer; 2549 2550 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2551 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2552 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2553 arcmsr_iop_message_read(acb); 2554 } 2555 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2556 acb->rqbuf_firstindex = 0; 2557 acb->rqbuf_lastindex = 0; 2558 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2559 pcmdmessagefld->cmdmessage.ReturnCode = 2560 ARCMSR_MESSAGE_RETURNCODE_OK; 2561 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2562 } 2563 break; 2564 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2565 u_int8_t *pQbuffer = acb->wqbuffer; 2566 2567 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2568 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2569 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2570 arcmsr_iop_message_read(acb); 2571 } 2572 acb->acb_flags |= 2573 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2574 ACB_F_MESSAGE_WQBUFFER_READ); 2575 acb->wqbuf_firstindex = 0; 2576 acb->wqbuf_lastindex = 0; 2577 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2578 pcmdmessagefld->cmdmessage.ReturnCode = 2579 ARCMSR_MESSAGE_RETURNCODE_OK; 2580 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2581 } 2582 break; 2583 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2584 u_int8_t *pQbuffer; 2585 2586 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2587 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2588 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2589 arcmsr_iop_message_read(acb); 2590 } 2591 acb->acb_flags |= 2592 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2593 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2594 | ACB_F_MESSAGE_WQBUFFER_READ); 2595 acb->rqbuf_firstindex = 0; 2596 acb->rqbuf_lastindex = 0; 2597 acb->wqbuf_firstindex = 0; 2598 acb->wqbuf_lastindex = 0; 2599 pQbuffer = acb->rqbuffer; 2600 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2601 pQbuffer = acb->wqbuffer; 2602 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2603 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2604 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2605 } 2606 break; 2607 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2608 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2609 } 2610 break; 2611 case ARCMSR_MESSAGE_SAY_HELLO: { 2612 int8_t *hello_string = "Hello! I am ARCMSR"; 2613 2614 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2615 , (int16_t)strlen(hello_string)); 2616 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2617 } 2618 break; 2619 case ARCMSR_MESSAGE_SAY_GOODBYE: 2620 arcmsr_iop_parking(acb); 2621 break; 2622 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2623 arcmsr_flush_adapter_cache(acb); 2624 break; 2625 default: 2626 retvalue = ARCMSR_MESSAGE_FAIL; 2627 } 2628 message_out: 2629 return (retvalue); 2630 } 2631 /* 2632 ********************************************************************* 2633 ********************************************************************* 2634 */ 2635 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2636 { 2637 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2638 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2639 union ccb *pccb; 2640 int target, lun; 2641 2642 pccb = srb->pccb; 2643 target = pccb->ccb_h.target_id; 2644 lun = pccb->ccb_h.target_lun; 2645 acb->pktRequestCount++; 2646 if(error != 0) { 2647 if(error != EFBIG) { 2648 printf("arcmsr%d: unexpected error %x" 2649 " returned from 'bus_dmamap_load' \n" 2650 , acb->pci_unit, error); 2651 } 2652 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2653 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2654 } 2655 arcmsr_srb_complete(srb, 0); 2656 return; 2657 } 2658 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2659 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2660 arcmsr_srb_complete(srb, 0); 2661 return; 2662 } 2663 if(acb->acb_flags & ACB_F_BUS_RESET) { 2664 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2665 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2666 arcmsr_srb_complete(srb, 0); 2667 return; 2668 } 2669 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2670 u_int8_t block_cmd, cmd; 2671 2672 cmd = pccb->csio.cdb_io.cdb_bytes[0]; 2673 block_cmd = cmd & 0x0f; 2674 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2675 printf("arcmsr%d:block 'read/write' command " 2676 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2677 , acb->pci_unit, cmd, target, lun); 2678 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2679 arcmsr_srb_complete(srb, 0); 2680 return; 2681 } 2682 } 2683 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2684 if(nseg != 0) { 2685 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2686 } 2687 arcmsr_srb_complete(srb, 0); 2688 return; 2689 } 2690 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2691 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2692 { 2693 xpt_freeze_simq(acb->psim, 1); 2694 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2695 } 2696 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2697 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2698 arcmsr_srb_complete(srb, 0); 2699 return; 2700 } 2701 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2702 arcmsr_build_srb(srb, dm_segs, nseg); 2703 arcmsr_post_srb(acb, srb); 2704 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2705 { 2706 arcmsr_callout_init(&srb->ccb_callout); 2707 callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb); 2708 srb->srb_flags |= SRB_FLAG_TIMER_START; 2709 } 2710 } 2711 /* 2712 ***************************************************************************************** 2713 ***************************************************************************************** 2714 */ 2715 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2716 { 2717 struct CommandControlBlock *srb; 2718 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2719 u_int32_t intmask_org; 2720 int i = 0; 2721 2722 acb->num_aborts++; 2723 /* 2724 *************************************************************************** 2725 ** It is the upper layer do abort command this lock just prior to calling us. 2726 ** First determine if we currently own this command. 2727 ** Start by searching the device queue. If not found 2728 ** at all, and the system wanted us to just abort the 2729 ** command return success. 2730 *************************************************************************** 2731 */ 2732 if(acb->srboutstandingcount != 0) { 2733 /* disable all outbound interrupt */ 2734 intmask_org = arcmsr_disable_allintr(acb); 2735 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 2736 srb = acb->psrb_pool[i]; 2737 if(srb->srb_state == ARCMSR_SRB_START) { 2738 if(srb->pccb == abortccb) { 2739 srb->srb_state = ARCMSR_SRB_ABORTED; 2740 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2741 "outstanding command \n" 2742 , acb->pci_unit, abortccb->ccb_h.target_id 2743 , abortccb->ccb_h.target_lun, srb); 2744 arcmsr_polling_srbdone(acb, srb); 2745 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2746 arcmsr_enable_allintr(acb, intmask_org); 2747 return (TRUE); 2748 } 2749 } 2750 } 2751 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2752 arcmsr_enable_allintr(acb, intmask_org); 2753 } 2754 return(FALSE); 2755 } 2756 /* 2757 **************************************************************************** 2758 **************************************************************************** 2759 */ 2760 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2761 { 2762 int retry = 0; 2763 2764 acb->num_resets++; 2765 acb->acb_flags |= ACB_F_BUS_RESET; 2766 while(acb->srboutstandingcount != 0 && retry < 400) { 2767 arcmsr_interrupt(acb); 2768 UDELAY(25000); 2769 retry++; 2770 } 2771 arcmsr_iop_reset(acb); 2772 acb->acb_flags &= ~ACB_F_BUS_RESET; 2773 } 2774 /* 2775 ************************************************************************** 2776 ************************************************************************** 2777 */ 2778 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2779 union ccb *pccb) 2780 { 2781 if (pccb->ccb_h.target_lun) { 2782 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2783 xpt_done(pccb); 2784 return; 2785 } 2786 pccb->ccb_h.status |= CAM_REQ_CMP; 2787 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2788 case INQUIRY: { 2789 unsigned char inqdata[36]; 2790 char *buffer = pccb->csio.data_ptr; 2791 2792 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2793 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2794 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2795 inqdata[3] = 0; 2796 inqdata[4] = 31; /* length of additional data */ 2797 inqdata[5] = 0; 2798 inqdata[6] = 0; 2799 inqdata[7] = 0; 2800 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2801 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2802 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2803 memcpy(buffer, inqdata, sizeof(inqdata)); 2804 xpt_done(pccb); 2805 } 2806 break; 2807 case WRITE_BUFFER: 2808 case READ_BUFFER: { 2809 if (arcmsr_iop_message_xfer(acb, pccb)) { 2810 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2811 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2812 } 2813 xpt_done(pccb); 2814 } 2815 break; 2816 default: 2817 xpt_done(pccb); 2818 } 2819 } 2820 /* 2821 ********************************************************************* 2822 ********************************************************************* 2823 */ 2824 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 2825 { 2826 struct AdapterControlBlock *acb; 2827 2828 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 2829 if(acb == NULL) { 2830 pccb->ccb_h.status |= CAM_REQ_INVALID; 2831 xpt_done(pccb); 2832 return; 2833 } 2834 switch (pccb->ccb_h.func_code) { 2835 case XPT_SCSI_IO: { 2836 struct CommandControlBlock *srb; 2837 int target = pccb->ccb_h.target_id; 2838 int error; 2839 2840 if(target == 16) { 2841 /* virtual device for iop message transfer */ 2842 arcmsr_handle_virtual_command(acb, pccb); 2843 return; 2844 } 2845 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 2846 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2847 xpt_done(pccb); 2848 return; 2849 } 2850 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 2851 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 2852 srb->pccb = pccb; 2853 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 2854 , srb->dm_segs_dmamap 2855 , pccb 2856 , arcmsr_execute_srb, srb, /*flags*/0); 2857 if(error == EINPROGRESS) { 2858 xpt_freeze_simq(acb->psim, 1); 2859 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2860 } 2861 break; 2862 } 2863 case XPT_TARGET_IO: { 2864 /* target mode not yet support vendor specific commands. */ 2865 pccb->ccb_h.status |= CAM_REQ_CMP; 2866 xpt_done(pccb); 2867 break; 2868 } 2869 case XPT_PATH_INQ: { 2870 struct ccb_pathinq *cpi = &pccb->cpi; 2871 2872 cpi->version_num = 1; 2873 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2874 cpi->target_sprt = 0; 2875 cpi->hba_misc = 0; 2876 cpi->hba_eng_cnt = 0; 2877 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 2878 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2879 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2880 cpi->bus_id = cam_sim_bus(psim); 2881 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2882 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2883 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2884 cpi->unit_number = cam_sim_unit(psim); 2885 #ifdef CAM_NEW_TRAN_CODE 2886 if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 2887 cpi->base_transfer_speed = 600000; 2888 else 2889 cpi->base_transfer_speed = 300000; 2890 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2891 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2892 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2893 { 2894 cpi->transport = XPORT_SAS; 2895 cpi->transport_version = 0; 2896 cpi->protocol_version = SCSI_REV_SPC2; 2897 } 2898 else 2899 { 2900 cpi->transport = XPORT_SPI; 2901 cpi->transport_version = 2; 2902 cpi->protocol_version = SCSI_REV_2; 2903 } 2904 cpi->protocol = PROTO_SCSI; 2905 #endif 2906 cpi->ccb_h.status |= CAM_REQ_CMP; 2907 xpt_done(pccb); 2908 break; 2909 } 2910 case XPT_ABORT: { 2911 union ccb *pabort_ccb; 2912 2913 pabort_ccb = pccb->cab.abort_ccb; 2914 switch (pabort_ccb->ccb_h.func_code) { 2915 case XPT_ACCEPT_TARGET_IO: 2916 case XPT_IMMED_NOTIFY: 2917 case XPT_CONT_TARGET_IO: 2918 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2919 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2920 xpt_done(pabort_ccb); 2921 pccb->ccb_h.status |= CAM_REQ_CMP; 2922 } else { 2923 xpt_print_path(pabort_ccb->ccb_h.path); 2924 printf("Not found\n"); 2925 pccb->ccb_h.status |= CAM_PATH_INVALID; 2926 } 2927 break; 2928 case XPT_SCSI_IO: 2929 pccb->ccb_h.status |= CAM_UA_ABORT; 2930 break; 2931 default: 2932 pccb->ccb_h.status |= CAM_REQ_INVALID; 2933 break; 2934 } 2935 xpt_done(pccb); 2936 break; 2937 } 2938 case XPT_RESET_BUS: 2939 case XPT_RESET_DEV: { 2940 u_int32_t i; 2941 2942 arcmsr_bus_reset(acb); 2943 for (i=0; i < 500; i++) { 2944 DELAY(1000); 2945 } 2946 pccb->ccb_h.status |= CAM_REQ_CMP; 2947 xpt_done(pccb); 2948 break; 2949 } 2950 case XPT_TERM_IO: { 2951 pccb->ccb_h.status |= CAM_REQ_INVALID; 2952 xpt_done(pccb); 2953 break; 2954 } 2955 case XPT_GET_TRAN_SETTINGS: { 2956 struct ccb_trans_settings *cts; 2957 2958 if(pccb->ccb_h.target_id == 16) { 2959 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2960 xpt_done(pccb); 2961 break; 2962 } 2963 cts = &pccb->cts; 2964 #ifdef CAM_NEW_TRAN_CODE 2965 { 2966 struct ccb_trans_settings_scsi *scsi; 2967 struct ccb_trans_settings_spi *spi; 2968 struct ccb_trans_settings_sas *sas; 2969 2970 scsi = &cts->proto_specific.scsi; 2971 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2972 scsi->valid = CTS_SCSI_VALID_TQ; 2973 cts->protocol = PROTO_SCSI; 2974 2975 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2976 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2977 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2978 { 2979 cts->protocol_version = SCSI_REV_SPC2; 2980 cts->transport_version = 0; 2981 cts->transport = XPORT_SAS; 2982 sas = &cts->xport_specific.sas; 2983 sas->valid = CTS_SAS_VALID_SPEED; 2984 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2985 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2986 sas->bitrate = 600000; 2987 else if(acb->vendor_device_id == PCIDevVenIDARC1680) 2988 sas->bitrate = 300000; 2989 } 2990 else 2991 { 2992 cts->protocol_version = SCSI_REV_2; 2993 cts->transport_version = 2; 2994 cts->transport = XPORT_SPI; 2995 spi = &cts->xport_specific.spi; 2996 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 2997 spi->sync_period = 2; 2998 spi->sync_offset = 32; 2999 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3000 spi->valid = CTS_SPI_VALID_DISC 3001 | CTS_SPI_VALID_SYNC_RATE 3002 | CTS_SPI_VALID_SYNC_OFFSET 3003 | CTS_SPI_VALID_BUS_WIDTH; 3004 } 3005 } 3006 #else 3007 { 3008 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 3009 cts->sync_period = 2; 3010 cts->sync_offset = 32; 3011 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3012 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 3013 CCB_TRANS_SYNC_OFFSET_VALID | 3014 CCB_TRANS_BUS_WIDTH_VALID | 3015 CCB_TRANS_DISC_VALID | 3016 CCB_TRANS_TQ_VALID; 3017 } 3018 #endif 3019 pccb->ccb_h.status |= CAM_REQ_CMP; 3020 xpt_done(pccb); 3021 break; 3022 } 3023 case XPT_SET_TRAN_SETTINGS: { 3024 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3025 xpt_done(pccb); 3026 break; 3027 } 3028 case XPT_CALC_GEOMETRY: 3029 if(pccb->ccb_h.target_id == 16) { 3030 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3031 xpt_done(pccb); 3032 break; 3033 } 3034 #if __FreeBSD_version >= 500000 3035 cam_calc_geometry(&pccb->ccg, 1); 3036 #else 3037 { 3038 struct ccb_calc_geometry *ccg; 3039 u_int32_t size_mb; 3040 u_int32_t secs_per_cylinder; 3041 3042 ccg = &pccb->ccg; 3043 if (ccg->block_size == 0) { 3044 pccb->ccb_h.status = CAM_REQ_INVALID; 3045 xpt_done(pccb); 3046 break; 3047 } 3048 if(((1024L * 1024L)/ccg->block_size) < 0) { 3049 pccb->ccb_h.status = CAM_REQ_INVALID; 3050 xpt_done(pccb); 3051 break; 3052 } 3053 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 3054 if(size_mb > 1024 ) { 3055 ccg->heads = 255; 3056 ccg->secs_per_track = 63; 3057 } else { 3058 ccg->heads = 64; 3059 ccg->secs_per_track = 32; 3060 } 3061 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3062 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3063 pccb->ccb_h.status |= CAM_REQ_CMP; 3064 } 3065 #endif 3066 xpt_done(pccb); 3067 break; 3068 default: 3069 pccb->ccb_h.status |= CAM_REQ_INVALID; 3070 xpt_done(pccb); 3071 break; 3072 } 3073 } 3074 /* 3075 ********************************************************************** 3076 ********************************************************************** 3077 */ 3078 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3079 { 3080 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3081 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3082 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3083 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3084 } 3085 } 3086 /* 3087 ********************************************************************** 3088 ********************************************************************** 3089 */ 3090 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3091 { 3092 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3093 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3094 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3095 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3096 } 3097 } 3098 /* 3099 ********************************************************************** 3100 ********************************************************************** 3101 */ 3102 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3103 { 3104 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3105 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3106 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3107 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3108 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3109 } 3110 } 3111 /* 3112 ********************************************************************** 3113 ********************************************************************** 3114 */ 3115 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3116 { 3117 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3118 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3119 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3120 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3121 } 3122 } 3123 /* 3124 ********************************************************************** 3125 ********************************************************************** 3126 */ 3127 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3128 { 3129 switch (acb->adapter_type) { 3130 case ACB_ADAPTER_TYPE_A: 3131 arcmsr_start_hba_bgrb(acb); 3132 break; 3133 case ACB_ADAPTER_TYPE_B: 3134 arcmsr_start_hbb_bgrb(acb); 3135 break; 3136 case ACB_ADAPTER_TYPE_C: 3137 arcmsr_start_hbc_bgrb(acb); 3138 break; 3139 case ACB_ADAPTER_TYPE_D: 3140 arcmsr_start_hbd_bgrb(acb); 3141 break; 3142 } 3143 } 3144 /* 3145 ********************************************************************** 3146 ** 3147 ********************************************************************** 3148 */ 3149 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3150 { 3151 struct CommandControlBlock *srb; 3152 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3153 u_int16_t error; 3154 3155 polling_ccb_retry: 3156 poll_count++; 3157 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3158 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3159 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3160 while(1) { 3161 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3162 0, outbound_queueport)) == 0xFFFFFFFF) { 3163 if(poll_srb_done) { 3164 break;/*chip FIFO no ccb for completion already*/ 3165 } else { 3166 UDELAY(25000); 3167 if ((poll_count > 100) && (poll_srb != NULL)) { 3168 break; 3169 } 3170 goto polling_ccb_retry; 3171 } 3172 } 3173 /* check if command done with no error*/ 3174 srb = (struct CommandControlBlock *) 3175 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3176 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3177 poll_srb_done = (srb == poll_srb) ? 1:0; 3178 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3179 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3180 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3181 "poll command abort successfully \n" 3182 , acb->pci_unit 3183 , srb->pccb->ccb_h.target_id 3184 , srb->pccb->ccb_h.target_lun, srb); 3185 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3186 arcmsr_srb_complete(srb, 1); 3187 continue; 3188 } 3189 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3190 "srboutstandingcount=%d \n" 3191 , acb->pci_unit 3192 , srb, acb->srboutstandingcount); 3193 continue; 3194 } 3195 arcmsr_report_srb_state(acb, srb, error); 3196 } /*drain reply FIFO*/ 3197 } 3198 /* 3199 ********************************************************************** 3200 ** 3201 ********************************************************************** 3202 */ 3203 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3204 { 3205 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3206 struct CommandControlBlock *srb; 3207 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3208 int index; 3209 u_int16_t error; 3210 3211 polling_ccb_retry: 3212 poll_count++; 3213 CHIP_REG_WRITE32(HBB_DOORBELL, 3214 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3215 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3216 while(1) { 3217 index = phbbmu->doneq_index; 3218 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3219 if(poll_srb_done) { 3220 break;/*chip FIFO no ccb for completion already*/ 3221 } else { 3222 UDELAY(25000); 3223 if ((poll_count > 100) && (poll_srb != NULL)) { 3224 break; 3225 } 3226 goto polling_ccb_retry; 3227 } 3228 } 3229 phbbmu->done_qbuffer[index] = 0; 3230 index++; 3231 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3232 phbbmu->doneq_index = index; 3233 /* check if command done with no error*/ 3234 srb = (struct CommandControlBlock *) 3235 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3236 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3237 poll_srb_done = (srb == poll_srb) ? 1:0; 3238 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3239 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3240 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3241 "poll command abort successfully \n" 3242 , acb->pci_unit 3243 , srb->pccb->ccb_h.target_id 3244 , srb->pccb->ccb_h.target_lun, srb); 3245 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3246 arcmsr_srb_complete(srb, 1); 3247 continue; 3248 } 3249 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3250 "srboutstandingcount=%d \n" 3251 , acb->pci_unit 3252 , srb, acb->srboutstandingcount); 3253 continue; 3254 } 3255 arcmsr_report_srb_state(acb, srb, error); 3256 } /*drain reply FIFO*/ 3257 } 3258 /* 3259 ********************************************************************** 3260 ** 3261 ********************************************************************** 3262 */ 3263 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3264 { 3265 struct CommandControlBlock *srb; 3266 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3267 u_int16_t error; 3268 3269 polling_ccb_retry: 3270 poll_count++; 3271 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3272 while(1) { 3273 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3274 if(poll_srb_done) { 3275 break;/*chip FIFO no ccb for completion already*/ 3276 } else { 3277 UDELAY(25000); 3278 if ((poll_count > 100) && (poll_srb != NULL)) { 3279 break; 3280 } 3281 if (acb->srboutstandingcount == 0) { 3282 break; 3283 } 3284 goto polling_ccb_retry; 3285 } 3286 } 3287 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3288 /* check if command done with no error*/ 3289 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3290 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3291 if (poll_srb != NULL) 3292 poll_srb_done = (srb == poll_srb) ? 1:0; 3293 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3294 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3295 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3296 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3297 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3298 arcmsr_srb_complete(srb, 1); 3299 continue; 3300 } 3301 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3302 , acb->pci_unit, srb, acb->srboutstandingcount); 3303 continue; 3304 } 3305 arcmsr_report_srb_state(acb, srb, error); 3306 } /*drain reply FIFO*/ 3307 } 3308 /* 3309 ********************************************************************** 3310 ** 3311 ********************************************************************** 3312 */ 3313 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3314 { 3315 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3316 struct CommandControlBlock *srb; 3317 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3318 u_int32_t outbound_write_pointer; 3319 u_int16_t error, doneq_index; 3320 3321 polling_ccb_retry: 3322 poll_count++; 3323 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3324 while(1) { 3325 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3326 doneq_index = phbdmu->doneq_index; 3327 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3328 if(poll_srb_done) { 3329 break;/*chip FIFO no ccb for completion already*/ 3330 } else { 3331 UDELAY(25000); 3332 if ((poll_count > 100) && (poll_srb != NULL)) { 3333 break; 3334 } 3335 if (acb->srboutstandingcount == 0) { 3336 break; 3337 } 3338 goto polling_ccb_retry; 3339 } 3340 } 3341 doneq_index = arcmsr_get_doneq_index(phbdmu); 3342 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3343 /* check if command done with no error*/ 3344 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3345 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3347 if (poll_srb != NULL) 3348 poll_srb_done = (srb == poll_srb) ? 1:0; 3349 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3350 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3351 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3352 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3353 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3354 arcmsr_srb_complete(srb, 1); 3355 continue; 3356 } 3357 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3358 , acb->pci_unit, srb, acb->srboutstandingcount); 3359 continue; 3360 } 3361 arcmsr_report_srb_state(acb, srb, error); 3362 } /*drain reply FIFO*/ 3363 } 3364 /* 3365 ********************************************************************** 3366 ********************************************************************** 3367 */ 3368 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3369 { 3370 switch (acb->adapter_type) { 3371 case ACB_ADAPTER_TYPE_A: { 3372 arcmsr_polling_hba_srbdone(acb, poll_srb); 3373 } 3374 break; 3375 case ACB_ADAPTER_TYPE_B: { 3376 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3377 } 3378 break; 3379 case ACB_ADAPTER_TYPE_C: { 3380 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3381 } 3382 break; 3383 case ACB_ADAPTER_TYPE_D: { 3384 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3385 } 3386 break; 3387 } 3388 } 3389 /* 3390 ********************************************************************** 3391 ********************************************************************** 3392 */ 3393 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3394 { 3395 char *acb_firm_model = acb->firm_model; 3396 char *acb_firm_version = acb->firm_version; 3397 char *acb_device_map = acb->device_map; 3398 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3399 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3400 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3401 int i; 3402 3403 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3404 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3405 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3406 } 3407 i = 0; 3408 while(i < 8) { 3409 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3410 /* 8 bytes firm_model, 15, 60-67*/ 3411 acb_firm_model++; 3412 i++; 3413 } 3414 i=0; 3415 while(i < 16) { 3416 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3417 /* 16 bytes firm_version, 17, 68-83*/ 3418 acb_firm_version++; 3419 i++; 3420 } 3421 i=0; 3422 while(i < 16) { 3423 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3424 acb_device_map++; 3425 i++; 3426 } 3427 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3428 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3429 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3430 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3431 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3432 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3433 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3434 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3435 else 3436 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3437 } 3438 /* 3439 ********************************************************************** 3440 ********************************************************************** 3441 */ 3442 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3443 { 3444 char *acb_firm_model = acb->firm_model; 3445 char *acb_firm_version = acb->firm_version; 3446 char *acb_device_map = acb->device_map; 3447 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3448 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3449 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3450 int i; 3451 3452 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3453 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3454 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3455 } 3456 i = 0; 3457 while(i < 8) { 3458 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3459 /* 8 bytes firm_model, 15, 60-67*/ 3460 acb_firm_model++; 3461 i++; 3462 } 3463 i = 0; 3464 while(i < 16) { 3465 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3466 /* 16 bytes firm_version, 17, 68-83*/ 3467 acb_firm_version++; 3468 i++; 3469 } 3470 i = 0; 3471 while(i < 16) { 3472 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3473 acb_device_map++; 3474 i++; 3475 } 3476 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3477 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3478 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3479 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3480 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3481 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3482 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3483 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3484 else 3485 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3486 } 3487 /* 3488 ********************************************************************** 3489 ********************************************************************** 3490 */ 3491 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3492 { 3493 char *acb_firm_model = acb->firm_model; 3494 char *acb_firm_version = acb->firm_version; 3495 char *acb_device_map = acb->device_map; 3496 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3497 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3498 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3499 int i; 3500 3501 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3502 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3503 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3504 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3505 } 3506 i = 0; 3507 while(i < 8) { 3508 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3509 /* 8 bytes firm_model, 15, 60-67*/ 3510 acb_firm_model++; 3511 i++; 3512 } 3513 i = 0; 3514 while(i < 16) { 3515 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3516 /* 16 bytes firm_version, 17, 68-83*/ 3517 acb_firm_version++; 3518 i++; 3519 } 3520 i = 0; 3521 while(i < 16) { 3522 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3523 acb_device_map++; 3524 i++; 3525 } 3526 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3527 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3528 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3529 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3530 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3531 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3532 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3533 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3534 else 3535 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3536 } 3537 /* 3538 ********************************************************************** 3539 ********************************************************************** 3540 */ 3541 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3542 { 3543 char *acb_firm_model = acb->firm_model; 3544 char *acb_firm_version = acb->firm_version; 3545 char *acb_device_map = acb->device_map; 3546 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3547 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3548 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3549 int i; 3550 3551 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3552 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3553 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3554 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3555 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3556 } 3557 i = 0; 3558 while(i < 8) { 3559 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3560 /* 8 bytes firm_model, 15, 60-67*/ 3561 acb_firm_model++; 3562 i++; 3563 } 3564 i = 0; 3565 while(i < 16) { 3566 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3567 /* 16 bytes firm_version, 17, 68-83*/ 3568 acb_firm_version++; 3569 i++; 3570 } 3571 i = 0; 3572 while(i < 16) { 3573 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3574 acb_device_map++; 3575 i++; 3576 } 3577 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3578 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_request_len, 1, 04-07*/ 3579 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_numbers_queue, 2, 08-11*/ 3580 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_sdram_size, 3, 12-15*/ 3581 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]); /*firm_ide_channels, 4, 16-19*/ 3582 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3583 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3584 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3585 else 3586 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3587 } 3588 /* 3589 ********************************************************************** 3590 ********************************************************************** 3591 */ 3592 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3593 { 3594 switch (acb->adapter_type) { 3595 case ACB_ADAPTER_TYPE_A: { 3596 arcmsr_get_hba_config(acb); 3597 } 3598 break; 3599 case ACB_ADAPTER_TYPE_B: { 3600 arcmsr_get_hbb_config(acb); 3601 } 3602 break; 3603 case ACB_ADAPTER_TYPE_C: { 3604 arcmsr_get_hbc_config(acb); 3605 } 3606 break; 3607 case ACB_ADAPTER_TYPE_D: { 3608 arcmsr_get_hbd_config(acb); 3609 } 3610 break; 3611 } 3612 } 3613 /* 3614 ********************************************************************** 3615 ********************************************************************** 3616 */ 3617 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3618 { 3619 int timeout=0; 3620 3621 switch (acb->adapter_type) { 3622 case ACB_ADAPTER_TYPE_A: { 3623 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3624 { 3625 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3626 { 3627 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3628 return; 3629 } 3630 UDELAY(15000); /* wait 15 milli-seconds */ 3631 } 3632 } 3633 break; 3634 case ACB_ADAPTER_TYPE_B: { 3635 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3636 { 3637 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3638 { 3639 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3640 return; 3641 } 3642 UDELAY(15000); /* wait 15 milli-seconds */ 3643 } 3644 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3645 } 3646 break; 3647 case ACB_ADAPTER_TYPE_C: { 3648 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3649 { 3650 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3651 { 3652 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3653 return; 3654 } 3655 UDELAY(15000); /* wait 15 milli-seconds */ 3656 } 3657 } 3658 break; 3659 case ACB_ADAPTER_TYPE_D: { 3660 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 3661 { 3662 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3663 { 3664 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3665 return; 3666 } 3667 UDELAY(15000); /* wait 15 milli-seconds */ 3668 } 3669 } 3670 break; 3671 } 3672 } 3673 /* 3674 ********************************************************************** 3675 ********************************************************************** 3676 */ 3677 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3678 { 3679 u_int32_t outbound_doorbell; 3680 3681 switch (acb->adapter_type) { 3682 case ACB_ADAPTER_TYPE_A: { 3683 /* empty doorbell Qbuffer if door bell ringed */ 3684 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3685 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3686 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3687 3688 } 3689 break; 3690 case ACB_ADAPTER_TYPE_B: { 3691 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3692 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3693 /* let IOP know data has been read */ 3694 } 3695 break; 3696 case ACB_ADAPTER_TYPE_C: { 3697 /* empty doorbell Qbuffer if door bell ringed */ 3698 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3699 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3700 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3701 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 3702 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 3703 } 3704 break; 3705 case ACB_ADAPTER_TYPE_D: { 3706 /* empty doorbell Qbuffer if door bell ringed */ 3707 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 3708 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3709 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 3710 3711 } 3712 break; 3713 } 3714 } 3715 /* 3716 ************************************************************************ 3717 ************************************************************************ 3718 */ 3719 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3720 { 3721 unsigned long srb_phyaddr; 3722 u_int32_t srb_phyaddr_hi32; 3723 u_int32_t srb_phyaddr_lo32; 3724 3725 /* 3726 ******************************************************************** 3727 ** here we need to tell iop 331 our freesrb.HighPart 3728 ** if freesrb.HighPart is not zero 3729 ******************************************************************** 3730 */ 3731 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 3732 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 3733 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 3734 switch (acb->adapter_type) { 3735 case ACB_ADAPTER_TYPE_A: { 3736 if(srb_phyaddr_hi32 != 0) { 3737 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3738 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3739 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3740 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3741 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3742 return FALSE; 3743 } 3744 } 3745 } 3746 break; 3747 /* 3748 *********************************************************************** 3749 ** if adapter type B, set window of "post command Q" 3750 *********************************************************************** 3751 */ 3752 case ACB_ADAPTER_TYPE_B: { 3753 u_int32_t post_queue_phyaddr; 3754 struct HBB_MessageUnit *phbbmu; 3755 3756 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3757 phbbmu->postq_index = 0; 3758 phbbmu->doneq_index = 0; 3759 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3760 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3761 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3762 return FALSE; 3763 } 3764 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3765 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3766 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3767 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3768 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3769 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3770 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3771 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3772 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3773 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3774 return FALSE; 3775 } 3776 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3777 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3778 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3779 return FALSE; 3780 } 3781 } 3782 break; 3783 case ACB_ADAPTER_TYPE_C: { 3784 if(srb_phyaddr_hi32 != 0) { 3785 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3786 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3787 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3788 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3789 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3790 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3791 return FALSE; 3792 } 3793 } 3794 } 3795 break; 3796 case ACB_ADAPTER_TYPE_D: { 3797 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 3798 struct HBD_MessageUnit0 *phbdmu; 3799 3800 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3801 phbdmu->postq_index = 0; 3802 phbdmu->doneq_index = 0x40FF; 3803 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3804 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 3805 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3806 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 3807 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3808 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3809 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 3810 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 3811 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 3812 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3813 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3814 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3815 return FALSE; 3816 } 3817 } 3818 break; 3819 } 3820 return (TRUE); 3821 } 3822 /* 3823 ************************************************************************ 3824 ************************************************************************ 3825 */ 3826 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3827 { 3828 switch (acb->adapter_type) 3829 { 3830 case ACB_ADAPTER_TYPE_A: 3831 case ACB_ADAPTER_TYPE_C: 3832 case ACB_ADAPTER_TYPE_D: 3833 break; 3834 case ACB_ADAPTER_TYPE_B: { 3835 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3836 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3837 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3838 return; 3839 } 3840 } 3841 break; 3842 } 3843 } 3844 /* 3845 ********************************************************************** 3846 ********************************************************************** 3847 */ 3848 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3849 { 3850 u_int32_t intmask_org; 3851 3852 /* disable all outbound interrupt */ 3853 intmask_org = arcmsr_disable_allintr(acb); 3854 arcmsr_wait_firmware_ready(acb); 3855 arcmsr_iop_confirm(acb); 3856 arcmsr_get_firmware_spec(acb); 3857 /*start background rebuild*/ 3858 arcmsr_start_adapter_bgrb(acb); 3859 /* empty doorbell Qbuffer if door bell ringed */ 3860 arcmsr_clear_doorbell_queue_buffer(acb); 3861 arcmsr_enable_eoi_mode(acb); 3862 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3863 arcmsr_enable_allintr(acb, intmask_org); 3864 acb->acb_flags |= ACB_F_IOP_INITED; 3865 } 3866 /* 3867 ********************************************************************** 3868 ********************************************************************** 3869 */ 3870 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3871 { 3872 struct AdapterControlBlock *acb = arg; 3873 struct CommandControlBlock *srb_tmp; 3874 u_int32_t i; 3875 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 3876 3877 acb->srb_phyaddr.phyaddr = srb_phyaddr; 3878 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 3879 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3880 if(bus_dmamap_create(acb->dm_segs_dmat, 3881 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 3882 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3883 printf("arcmsr%d:" 3884 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3885 return; 3886 } 3887 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)) 3888 { 3889 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 3890 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 3891 } 3892 else 3893 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 3894 srb_tmp->acb = acb; 3895 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 3896 srb_phyaddr = srb_phyaddr + SRB_SIZE; 3897 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 3898 } 3899 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 3900 } 3901 /* 3902 ************************************************************************ 3903 ************************************************************************ 3904 */ 3905 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3906 { 3907 /* remove the control device */ 3908 if(acb->ioctl_dev != NULL) { 3909 destroy_dev(acb->ioctl_dev); 3910 } 3911 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3912 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3913 bus_dma_tag_destroy(acb->srb_dmat); 3914 bus_dma_tag_destroy(acb->dm_segs_dmat); 3915 bus_dma_tag_destroy(acb->parent_dmat); 3916 } 3917 /* 3918 ************************************************************************ 3919 ************************************************************************ 3920 */ 3921 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 3922 { 3923 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 3924 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 3925 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 3926 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 3927 } 3928 /* 3929 ************************************************************************ 3930 ************************************************************************ 3931 */ 3932 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 3933 { 3934 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3935 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 3936 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 3937 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 3938 } 3939 /* 3940 ************************************************************************ 3941 ************************************************************************ 3942 */ 3943 static u_int32_t arcmsr_initialize(device_t dev) 3944 { 3945 struct AdapterControlBlock *acb = device_get_softc(dev); 3946 u_int16_t pci_command; 3947 int i, j,max_coherent_size; 3948 u_int32_t vendor_dev_id; 3949 3950 vendor_dev_id = pci_get_devid(dev); 3951 acb->vendor_device_id = vendor_dev_id; 3952 switch (vendor_dev_id) { 3953 case PCIDevVenIDARC1880: 3954 case PCIDevVenIDARC1882: 3955 case PCIDevVenIDARC1213: 3956 case PCIDevVenIDARC1223: { 3957 acb->adapter_type = ACB_ADAPTER_TYPE_C; 3958 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3959 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3960 } 3961 break; 3962 case PCIDevVenIDARC1214: { 3963 acb->adapter_type = ACB_ADAPTER_TYPE_D; 3964 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3965 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 3966 } 3967 break; 3968 case PCIDevVenIDARC1200: 3969 case PCIDevVenIDARC1201: { 3970 acb->adapter_type = ACB_ADAPTER_TYPE_B; 3971 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3972 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 3973 } 3974 break; 3975 case PCIDevVenIDARC1110: 3976 case PCIDevVenIDARC1120: 3977 case PCIDevVenIDARC1130: 3978 case PCIDevVenIDARC1160: 3979 case PCIDevVenIDARC1170: 3980 case PCIDevVenIDARC1210: 3981 case PCIDevVenIDARC1220: 3982 case PCIDevVenIDARC1230: 3983 case PCIDevVenIDARC1231: 3984 case PCIDevVenIDARC1260: 3985 case PCIDevVenIDARC1261: 3986 case PCIDevVenIDARC1270: 3987 case PCIDevVenIDARC1280: 3988 case PCIDevVenIDARC1212: 3989 case PCIDevVenIDARC1222: 3990 case PCIDevVenIDARC1380: 3991 case PCIDevVenIDARC1381: 3992 case PCIDevVenIDARC1680: 3993 case PCIDevVenIDARC1681: { 3994 acb->adapter_type = ACB_ADAPTER_TYPE_A; 3995 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3996 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3997 } 3998 break; 3999 default: { 4000 printf("arcmsr%d:" 4001 " unknown RAID adapter type \n", device_get_unit(dev)); 4002 return ENOMEM; 4003 } 4004 } 4005 #if __FreeBSD_version >= 700000 4006 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4007 #else 4008 if(bus_dma_tag_create( /*PCI parent*/ NULL, 4009 #endif 4010 /*alignemnt*/ 1, 4011 /*boundary*/ 0, 4012 /*lowaddr*/ BUS_SPACE_MAXADDR, 4013 /*highaddr*/ BUS_SPACE_MAXADDR, 4014 /*filter*/ NULL, 4015 /*filterarg*/ NULL, 4016 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4017 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4018 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4019 /*flags*/ 0, 4020 #if __FreeBSD_version >= 501102 4021 /*lockfunc*/ NULL, 4022 /*lockarg*/ NULL, 4023 #endif 4024 &acb->parent_dmat) != 0) 4025 { 4026 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4027 return ENOMEM; 4028 } 4029 4030 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4031 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4032 /*alignment*/ 1, 4033 /*boundary*/ 0, 4034 #ifdef PAE 4035 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4036 #else 4037 /*lowaddr*/ BUS_SPACE_MAXADDR, 4038 #endif 4039 /*highaddr*/ BUS_SPACE_MAXADDR, 4040 /*filter*/ NULL, 4041 /*filterarg*/ NULL, 4042 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4043 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4044 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4045 /*flags*/ 0, 4046 #if __FreeBSD_version >= 501102 4047 /*lockfunc*/ busdma_lock_mutex, 4048 /*lockarg*/ &acb->isr_lock, 4049 #endif 4050 &acb->dm_segs_dmat) != 0) 4051 { 4052 bus_dma_tag_destroy(acb->parent_dmat); 4053 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4054 return ENOMEM; 4055 } 4056 4057 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4058 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4059 /*alignment*/ 0x20, 4060 /*boundary*/ 0, 4061 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4062 /*highaddr*/ BUS_SPACE_MAXADDR, 4063 /*filter*/ NULL, 4064 /*filterarg*/ NULL, 4065 /*maxsize*/ max_coherent_size, 4066 /*nsegments*/ 1, 4067 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4068 /*flags*/ 0, 4069 #if __FreeBSD_version >= 501102 4070 /*lockfunc*/ NULL, 4071 /*lockarg*/ NULL, 4072 #endif 4073 &acb->srb_dmat) != 0) 4074 { 4075 bus_dma_tag_destroy(acb->dm_segs_dmat); 4076 bus_dma_tag_destroy(acb->parent_dmat); 4077 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4078 return ENXIO; 4079 } 4080 /* Allocation for our srbs */ 4081 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4082 bus_dma_tag_destroy(acb->srb_dmat); 4083 bus_dma_tag_destroy(acb->dm_segs_dmat); 4084 bus_dma_tag_destroy(acb->parent_dmat); 4085 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4086 return ENXIO; 4087 } 4088 /* And permanently map them */ 4089 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4090 bus_dma_tag_destroy(acb->srb_dmat); 4091 bus_dma_tag_destroy(acb->dm_segs_dmat); 4092 bus_dma_tag_destroy(acb->parent_dmat); 4093 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4094 return ENXIO; 4095 } 4096 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4097 pci_command |= PCIM_CMD_BUSMASTEREN; 4098 pci_command |= PCIM_CMD_PERRESPEN; 4099 pci_command |= PCIM_CMD_MWRICEN; 4100 /* Enable Busmaster */ 4101 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4102 switch(acb->adapter_type) { 4103 case ACB_ADAPTER_TYPE_A: { 4104 u_int32_t rid0 = PCIR_BAR(0); 4105 vm_offset_t mem_base0; 4106 4107 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 4108 if(acb->sys_res_arcmsr[0] == NULL) { 4109 arcmsr_free_resource(acb); 4110 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4111 return ENOMEM; 4112 } 4113 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4114 arcmsr_free_resource(acb); 4115 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4116 return ENXIO; 4117 } 4118 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4119 if(mem_base0 == 0) { 4120 arcmsr_free_resource(acb); 4121 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4122 return ENXIO; 4123 } 4124 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4125 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4126 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4127 } 4128 break; 4129 case ACB_ADAPTER_TYPE_B: { 4130 struct HBB_MessageUnit *phbbmu; 4131 struct CommandControlBlock *freesrb; 4132 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4133 vm_offset_t mem_base[]={0,0}; 4134 for(i=0; i < 2; i++) { 4135 if(i == 0) { 4136 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 4137 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE); 4138 } else { 4139 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 4140 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 4141 } 4142 if(acb->sys_res_arcmsr[i] == NULL) { 4143 arcmsr_free_resource(acb); 4144 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4145 return ENOMEM; 4146 } 4147 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4148 arcmsr_free_resource(acb); 4149 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4150 return ENXIO; 4151 } 4152 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4153 if(mem_base[i] == 0) { 4154 arcmsr_free_resource(acb); 4155 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4156 return ENXIO; 4157 } 4158 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4159 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4160 } 4161 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4162 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4163 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4164 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4165 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4166 } 4167 break; 4168 case ACB_ADAPTER_TYPE_C: { 4169 u_int32_t rid0 = PCIR_BAR(1); 4170 vm_offset_t mem_base0; 4171 4172 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 4173 if(acb->sys_res_arcmsr[0] == NULL) { 4174 arcmsr_free_resource(acb); 4175 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4176 return ENOMEM; 4177 } 4178 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4179 arcmsr_free_resource(acb); 4180 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4181 return ENXIO; 4182 } 4183 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4184 if(mem_base0 == 0) { 4185 arcmsr_free_resource(acb); 4186 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4187 return ENXIO; 4188 } 4189 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4190 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4191 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4192 } 4193 break; 4194 case ACB_ADAPTER_TYPE_D: { 4195 struct HBD_MessageUnit0 *phbdmu; 4196 u_int32_t rid0 = PCIR_BAR(0); 4197 vm_offset_t mem_base0; 4198 4199 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE); 4200 if(acb->sys_res_arcmsr[0] == NULL) { 4201 arcmsr_free_resource(acb); 4202 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4203 return ENOMEM; 4204 } 4205 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4206 arcmsr_free_resource(acb); 4207 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4208 return ENXIO; 4209 } 4210 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4211 if(mem_base0 == 0) { 4212 arcmsr_free_resource(acb); 4213 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4214 return ENXIO; 4215 } 4216 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4217 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4218 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4219 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4220 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4221 } 4222 break; 4223 } 4224 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4225 arcmsr_free_resource(acb); 4226 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4227 return ENXIO; 4228 } 4229 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4230 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4231 /* 4232 ******************************************************************** 4233 ** init raid volume state 4234 ******************************************************************** 4235 */ 4236 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4237 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4238 acb->devstate[i][j] = ARECA_RAID_GONE; 4239 } 4240 } 4241 arcmsr_iop_init(acb); 4242 return(0); 4243 } 4244 /* 4245 ************************************************************************ 4246 ************************************************************************ 4247 */ 4248 static int arcmsr_attach(device_t dev) 4249 { 4250 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4251 u_int32_t unit=device_get_unit(dev); 4252 struct ccb_setasync csa; 4253 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4254 struct resource *irqres; 4255 int rid; 4256 4257 if(acb == NULL) { 4258 printf("arcmsr%d: cannot allocate softc\n", unit); 4259 return (ENOMEM); 4260 } 4261 arcmsr_mutex_init(acb); 4262 acb->pci_dev = dev; 4263 acb->pci_unit = unit; 4264 if(arcmsr_initialize(dev)) { 4265 printf("arcmsr%d: initialize failure!\n", unit); 4266 arcmsr_mutex_destroy(acb); 4267 return ENXIO; 4268 } 4269 /* After setting up the adapter, map our interrupt */ 4270 rid = 0; 4271 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 4272 if(irqres == NULL || 4273 #if __FreeBSD_version >= 700025 4274 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 4275 #else 4276 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 4277 #endif 4278 arcmsr_free_resource(acb); 4279 arcmsr_mutex_destroy(acb); 4280 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4281 return ENXIO; 4282 } 4283 acb->irqres = irqres; 4284 /* 4285 * Now let the CAM generic SCSI layer find the SCSI devices on 4286 * the bus * start queue to reset to the idle loop. * 4287 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4288 * max_sim_transactions 4289 */ 4290 devq = cam_simq_alloc(ARCMSR_MAX_START_JOB); 4291 if(devq == NULL) { 4292 arcmsr_free_resource(acb); 4293 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4294 arcmsr_mutex_destroy(acb); 4295 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4296 return ENXIO; 4297 } 4298 #if __FreeBSD_version >= 700025 4299 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4300 #else 4301 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4302 #endif 4303 if(acb->psim == NULL) { 4304 arcmsr_free_resource(acb); 4305 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4306 cam_simq_free(devq); 4307 arcmsr_mutex_destroy(acb); 4308 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4309 return ENXIO; 4310 } 4311 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4312 #if __FreeBSD_version >= 700044 4313 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4314 #else 4315 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4316 #endif 4317 arcmsr_free_resource(acb); 4318 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4319 cam_sim_free(acb->psim, /*free_devq*/TRUE); 4320 arcmsr_mutex_destroy(acb); 4321 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4322 return ENXIO; 4323 } 4324 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4325 arcmsr_free_resource(acb); 4326 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4327 xpt_bus_deregister(cam_sim_path(acb->psim)); 4328 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4329 arcmsr_mutex_destroy(acb); 4330 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4331 return ENXIO; 4332 } 4333 /* 4334 **************************************************** 4335 */ 4336 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4337 csa.ccb_h.func_code = XPT_SASYNC_CB; 4338 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4339 csa.callback = arcmsr_async; 4340 csa.callback_arg = acb->psim; 4341 xpt_action((union ccb *)&csa); 4342 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4343 /* Create the control device. */ 4344 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4345 4346 #if __FreeBSD_version < 503000 4347 acb->ioctl_dev->si_drv1 = acb; 4348 #endif 4349 #if __FreeBSD_version > 500005 4350 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4351 #endif 4352 arcmsr_callout_init(&acb->devmap_callout); 4353 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4354 return (0); 4355 } 4356 4357 /* 4358 ************************************************************************ 4359 ************************************************************************ 4360 */ 4361 static int arcmsr_probe(device_t dev) 4362 { 4363 u_int32_t id; 4364 static char buf[256]; 4365 char x_type[]={"unknown"}; 4366 char *type; 4367 int raid6 = 1; 4368 4369 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4370 return (ENXIO); 4371 } 4372 switch(id = pci_get_devid(dev)) { 4373 case PCIDevVenIDARC1110: 4374 case PCIDevVenIDARC1200: 4375 case PCIDevVenIDARC1201: 4376 case PCIDevVenIDARC1210: 4377 raid6 = 0; 4378 /*FALLTHRU*/ 4379 case PCIDevVenIDARC1120: 4380 case PCIDevVenIDARC1130: 4381 case PCIDevVenIDARC1160: 4382 case PCIDevVenIDARC1170: 4383 case PCIDevVenIDARC1220: 4384 case PCIDevVenIDARC1230: 4385 case PCIDevVenIDARC1231: 4386 case PCIDevVenIDARC1260: 4387 case PCIDevVenIDARC1261: 4388 case PCIDevVenIDARC1270: 4389 case PCIDevVenIDARC1280: 4390 type = "SATA 3G"; 4391 break; 4392 case PCIDevVenIDARC1212: 4393 case PCIDevVenIDARC1222: 4394 case PCIDevVenIDARC1380: 4395 case PCIDevVenIDARC1381: 4396 case PCIDevVenIDARC1680: 4397 case PCIDevVenIDARC1681: 4398 type = "SAS 3G"; 4399 break; 4400 case PCIDevVenIDARC1880: 4401 case PCIDevVenIDARC1882: 4402 case PCIDevVenIDARC1213: 4403 case PCIDevVenIDARC1223: 4404 type = "SAS 6G"; 4405 break; 4406 case PCIDevVenIDARC1214: 4407 type = "SATA 6G"; 4408 break; 4409 default: 4410 type = x_type; 4411 raid6 = 0; 4412 break; 4413 } 4414 if(type == x_type) 4415 return(ENXIO); 4416 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 4417 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4418 device_set_desc_copy(dev, buf); 4419 return 0; 4420 } 4421 /* 4422 ************************************************************************ 4423 ************************************************************************ 4424 */ 4425 static int arcmsr_shutdown(device_t dev) 4426 { 4427 u_int32_t i; 4428 u_int32_t intmask_org; 4429 struct CommandControlBlock *srb; 4430 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4431 4432 /* stop adapter background rebuild */ 4433 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4434 /* disable all outbound interrupt */ 4435 intmask_org = arcmsr_disable_allintr(acb); 4436 arcmsr_stop_adapter_bgrb(acb); 4437 arcmsr_flush_adapter_cache(acb); 4438 /* abort all outstanding command */ 4439 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4440 acb->acb_flags &= ~ACB_F_IOP_INITED; 4441 if(acb->srboutstandingcount != 0) { 4442 /*clear and abort all outbound posted Q*/ 4443 arcmsr_done4abort_postqueue(acb); 4444 /* talk to iop 331 outstanding command aborted*/ 4445 arcmsr_abort_allcmd(acb); 4446 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4447 srb = acb->psrb_pool[i]; 4448 if(srb->srb_state == ARCMSR_SRB_START) { 4449 srb->srb_state = ARCMSR_SRB_ABORTED; 4450 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 4451 arcmsr_srb_complete(srb, 1); 4452 } 4453 } 4454 } 4455 acb->srboutstandingcount = 0; 4456 acb->workingsrb_doneindex = 0; 4457 acb->workingsrb_startindex = 0; 4458 acb->pktRequestCount = 0; 4459 acb->pktReturnCount = 0; 4460 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4461 return (0); 4462 } 4463 /* 4464 ************************************************************************ 4465 ************************************************************************ 4466 */ 4467 static int arcmsr_detach(device_t dev) 4468 { 4469 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4470 int i; 4471 4472 callout_stop(&acb->devmap_callout); 4473 bus_teardown_intr(dev, acb->irqres, acb->ih); 4474 arcmsr_shutdown(dev); 4475 arcmsr_free_resource(acb); 4476 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 4477 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 4478 } 4479 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4480 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4481 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 4482 xpt_free_path(acb->ppath); 4483 xpt_bus_deregister(cam_sim_path(acb->psim)); 4484 cam_sim_free(acb->psim, TRUE); 4485 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4486 arcmsr_mutex_destroy(acb); 4487 return (0); 4488 } 4489 4490 #ifdef ARCMSR_DEBUG1 4491 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 4492 { 4493 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 4494 return; 4495 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 4496 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 4497 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 4498 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 4499 } 4500 #endif 4501
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