The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/arcmsr/arcmsr.h

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    1 /*
    2 ********************************************************************************
    3 **        OS    : FreeBSD
    4 **   FILE NAME  : arcmsr.h
    5 **        BY    : Erich Chen, Ching Huang
    6 **   Description: SCSI RAID Device Driver for 
    7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
    8 **                SATA/SAS RAID HOST Adapter
    9 ********************************************************************************
   10 ********************************************************************************
   11 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
   12 **
   13 ** Redistribution and use in source and binary forms,with or without
   14 ** modification,are permitted provided that the following conditions
   15 ** are met:
   16 ** 1. Redistributions of source code must retain the above copyright
   17 **    notice,this list of conditions and the following disclaimer.
   18 ** 2. Redistributions in binary form must reproduce the above copyright
   19 **    notice,this list of conditions and the following disclaimer in the
   20 **    documentation and/or other materials provided with the distribution.
   21 ** 3. The name of the author may not be used to endorse or promote products
   22 **    derived from this software without specific prior written permission.
   23 **
   24 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   25 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES
   26 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   27 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT,
   28 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
   29 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   30 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
   31 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT
   32 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
   33 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   34 **************************************************************************
   35 * $FreeBSD: stable/11/sys/dev/arcmsr/arcmsr.h 331722 2018-03-29 02:50:57Z eadler $
   36 */
   37 #define ARCMSR_SCSI_INITIATOR_ID        255
   38 #define ARCMSR_DEV_SECTOR_SIZE          512
   39 #define ARCMSR_MAX_XFER_SECTORS         4096
   40 #define ARCMSR_MAX_TARGETID             17      /*16 max target id + 1*/
   41 #define ARCMSR_MAX_TARGETLUN            8       /*8*/
   42 #define ARCMSR_MAX_CHIPTYPE_NUM         4
   43 #define ARCMSR_MAX_OUTSTANDING_CMD      256
   44 #define ARCMSR_MAX_START_JOB            256
   45 #define ARCMSR_MAX_CMD_PERLUN           ARCMSR_MAX_OUTSTANDING_CMD
   46 #define ARCMSR_MAX_FREESRB_NUM          384
   47 #define ARCMSR_MAX_QBUFFER              4096    /* ioctl QBUFFER */
   48 #define ARCMSR_MAX_SG_ENTRIES           38      /* max 38*/
   49 #define ARCMSR_MAX_ADAPTER              4
   50 #define ARCMSR_RELEASE_SIMQ_LEVEL       230
   51 #define ARCMSR_MAX_HBB_POSTQUEUE        264     /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
   52 #define ARCMSR_MAX_HBD_POSTQUEUE        256
   53 #define ARCMSR_TIMEOUT_DELAY            60      /* in sec */
   54 #define ARCMSR_NUM_MSIX_VECTORS         4
   55 /*
   56 *********************************************************************
   57 */
   58 #ifndef TRUE
   59         #define TRUE  1
   60 #endif
   61 #ifndef FALSE
   62         #define FALSE 0
   63 #endif
   64 #ifndef INTR_ENTROPY
   65         # define INTR_ENTROPY 0
   66 #endif
   67 
   68 #ifndef offsetof
   69         #define offsetof(type, member)  ((size_t)(&((type *)0)->member))
   70 #endif
   71 
   72 #if __FreeBSD_version >= 500005
   73     #define ARCMSR_LOCK_INIT(l, s)      mtx_init(l, s, NULL, MTX_DEF)
   74     #define ARCMSR_LOCK_DESTROY(l)      mtx_destroy(l)
   75     #define ARCMSR_LOCK_ACQUIRE(l)      mtx_lock(l)
   76     #define ARCMSR_LOCK_RELEASE(l)      mtx_unlock(l)
   77     #define ARCMSR_LOCK_TRY(l)          mtx_trylock(l)
   78     #define arcmsr_htole32(x)           htole32(x)
   79     typedef struct mtx                  arcmsr_lock_t;
   80 #else
   81     #define ARCMSR_LOCK_INIT(l, s)      simple_lock_init(l)
   82     #define ARCMSR_LOCK_DESTROY(l)
   83     #define ARCMSR_LOCK_ACQUIRE(l)      simple_lock(l)
   84     #define ARCMSR_LOCK_RELEASE(l)      simple_unlock(l)
   85     #define ARCMSR_LOCK_TRY(l)          simple_lock_try(l)
   86     #define arcmsr_htole32(x)           (x)
   87     typedef struct simplelock           arcmsr_lock_t;
   88 #endif
   89 
   90 /*
   91 **********************************************************************************
   92 **
   93 **********************************************************************************
   94 */
   95 #define PCI_VENDOR_ID_ARECA             0x17D3 /* Vendor ID     */
   96 #define PCI_DEVICE_ID_ARECA_1110        0x1110 /* Device ID     */
   97 #define PCI_DEVICE_ID_ARECA_1120        0x1120 /* Device ID     */
   98 #define PCI_DEVICE_ID_ARECA_1130        0x1130 /* Device ID     */
   99 #define PCI_DEVICE_ID_ARECA_1160        0x1160 /* Device ID     */
  100 #define PCI_DEVICE_ID_ARECA_1170        0x1170 /* Device ID     */
  101 #define PCI_DEVICE_ID_ARECA_1200        0x1200 /* Device ID     */
  102 #define PCI_DEVICE_ID_ARECA_1201        0x1201 /* Device ID     */
  103 #define PCI_DEVICE_ID_ARECA_1203        0x1203 /* Device ID     */
  104 #define PCI_DEVICE_ID_ARECA_1210        0x1210 /* Device ID     */
  105 #define PCI_DEVICE_ID_ARECA_1212        0x1212 /* Device ID     */
  106 #define PCI_DEVICE_ID_ARECA_1214        0x1214 /* Device ID     */
  107 #define PCI_DEVICE_ID_ARECA_1220        0x1220 /* Device ID     */
  108 #define PCI_DEVICE_ID_ARECA_1222        0x1222 /* Device ID     */
  109 #define PCI_DEVICE_ID_ARECA_1230        0x1230 /* Device ID     */
  110 #define PCI_DEVICE_ID_ARECA_1231        0x1231 /* Device ID     */
  111 #define PCI_DEVICE_ID_ARECA_1260        0x1260 /* Device ID     */
  112 #define PCI_DEVICE_ID_ARECA_1261        0x1261 /* Device ID     */
  113 #define PCI_DEVICE_ID_ARECA_1270        0x1270 /* Device ID     */
  114 #define PCI_DEVICE_ID_ARECA_1280        0x1280 /* Device ID     */
  115 #define PCI_DEVICE_ID_ARECA_1380        0x1380 /* Device ID     */
  116 #define PCI_DEVICE_ID_ARECA_1381        0x1381 /* Device ID     */
  117 #define PCI_DEVICE_ID_ARECA_1680        0x1680 /* Device ID     */
  118 #define PCI_DEVICE_ID_ARECA_1681        0x1681 /* Device ID     */
  119 #define PCI_DEVICE_ID_ARECA_1880        0x1880 /* Device ID     */
  120 #define PCI_DEVICE_ID_ARECA_1884        0x1884 /* Device ID     */
  121 
  122 #define ARECA_SUB_DEV_ID_1880   0x1880 /* Subsystem Device ID   */
  123 #define ARECA_SUB_DEV_ID_1882   0x1882 /* Subsystem Device ID   */
  124 #define ARECA_SUB_DEV_ID_1883   0x1883 /* Subsystem Device ID   */
  125 #define ARECA_SUB_DEV_ID_1884   0x1884 /* Subsystem Device ID   */
  126 #define ARECA_SUB_DEV_ID_1212   0x1212 /* Subsystem Device ID   */
  127 #define ARECA_SUB_DEV_ID_1213   0x1213 /* Subsystem Device ID   */
  128 #define ARECA_SUB_DEV_ID_1216   0x1216 /* Subsystem Device ID   */
  129 #define ARECA_SUB_DEV_ID_1222   0x1222 /* Subsystem Device ID   */
  130 #define ARECA_SUB_DEV_ID_1223   0x1223 /* Subsystem Device ID   */
  131 #define ARECA_SUB_DEV_ID_1226   0x1226 /* Subsystem Device ID   */
  132 
  133 #define PCIDevVenIDARC1110              0x111017D3 /* Vendor Device ID  */
  134 #define PCIDevVenIDARC1120              0x112017D3 /* Vendor Device ID  */
  135 #define PCIDevVenIDARC1130              0x113017D3 /* Vendor Device ID  */
  136 #define PCIDevVenIDARC1160              0x116017D3 /* Vendor Device ID  */
  137 #define PCIDevVenIDARC1170              0x117017D3 /* Vendor Device ID  */
  138 #define PCIDevVenIDARC1200              0x120017D3 /* Vendor Device ID  */
  139 #define PCIDevVenIDARC1201              0x120117D3 /* Vendor Device ID  */
  140 #define PCIDevVenIDARC1203              0x120317D3 /* Vendor Device ID  */
  141 #define PCIDevVenIDARC1210              0x121017D3 /* Vendor Device ID  */
  142 #define PCIDevVenIDARC1212              0x121217D3 /* Vendor Device ID  */
  143 #define PCIDevVenIDARC1213              0x121317D3 /* Vendor Device ID  */
  144 #define PCIDevVenIDARC1214              0x121417D3 /* Vendor Device ID  */
  145 #define PCIDevVenIDARC1220              0x122017D3 /* Vendor Device ID  */
  146 #define PCIDevVenIDARC1222              0x122217D3 /* Vendor Device ID  */
  147 #define PCIDevVenIDARC1223              0x122317D3 /* Vendor Device ID  */
  148 #define PCIDevVenIDARC1230              0x123017D3 /* Vendor Device ID  */
  149 #define PCIDevVenIDARC1231              0x123117D3 /* Vendor Device ID  */
  150 #define PCIDevVenIDARC1260              0x126017D3 /* Vendor Device ID  */
  151 #define PCIDevVenIDARC1261              0x126117D3 /* Vendor Device ID  */
  152 #define PCIDevVenIDARC1270              0x127017D3 /* Vendor Device ID  */
  153 #define PCIDevVenIDARC1280              0x128017D3 /* Vendor Device ID  */
  154 #define PCIDevVenIDARC1380              0x138017D3 /* Vendor Device ID  */
  155 #define PCIDevVenIDARC1381              0x138117D3 /* Vendor Device ID  */
  156 #define PCIDevVenIDARC1680              0x168017D3 /* Vendor Device ID  */
  157 #define PCIDevVenIDARC1681              0x168117D3 /* Vendor Device ID  */
  158 #define PCIDevVenIDARC1880              0x188017D3 /* Vendor Device ID  */
  159 #define PCIDevVenIDARC1882              0x188217D3 /* Vendor Device ID  */
  160 #define PCIDevVenIDARC1884              0x188417D3 /* Vendor Device ID  */
  161 
  162 #ifndef PCIR_BARS
  163         #define PCIR_BARS       0x10
  164         #define PCIR_BAR(x)     (PCIR_BARS + (x) * 4)
  165 #endif
  166 
  167 #define PCI_BASE_ADDR0                  0x10
  168 #define PCI_BASE_ADDR1                  0x14
  169 #define PCI_BASE_ADDR2                  0x18
  170 #define PCI_BASE_ADDR3                  0x1C
  171 #define PCI_BASE_ADDR4                  0x20
  172 #define PCI_BASE_ADDR5                  0x24
  173 /*
  174 **********************************************************************************
  175 **
  176 **********************************************************************************
  177 */
  178 #define ARCMSR_SCSICMD_IOCTL            0x77
  179 #define ARCMSR_CDEVSW_IOCTL             0x88
  180 #define ARCMSR_MESSAGE_FAIL             0x0001
  181 #define ARCMSR_MESSAGE_SUCCESS          0x0000
  182 /*
  183 **********************************************************************************
  184 **
  185 **********************************************************************************
  186 */
  187 #define arcmsr_ccbsrb_ptr       spriv_ptr0
  188 #define arcmsr_ccbacb_ptr       spriv_ptr1
  189 #define dma_addr_hi32(addr)     (u_int32_t) ((addr>>16)>>16)
  190 #define dma_addr_lo32(addr)     (u_int32_t) (addr & 0xffffffff)
  191 #define get_min(x,y)            ((x) < (y) ? (x) : (y))
  192 #define get_max(x,y)            ((x) < (y) ? (y) : (x))
  193 /*
  194 **************************************************************************
  195 **************************************************************************
  196 */
  197 #define CHIP_REG_READ32(s, b, r)        bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
  198 #define CHIP_REG_WRITE32(s, b, r, d)    bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
  199 #define READ_CHIP_REG32(b, r)           bus_space_read_4(acb->btag[b], acb->bhandle[b], r)
  200 #define WRITE_CHIP_REG32(b, r, d)       bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d)
  201 /*
  202 **********************************************************************************
  203 **    IOCTL CONTROL Mail Box
  204 **********************************************************************************
  205 */
  206 struct CMD_MESSAGE {
  207       u_int32_t HeaderLength;
  208       u_int8_t Signature[8];
  209       u_int32_t Timeout;
  210       u_int32_t ControlCode;
  211       u_int32_t ReturnCode;
  212       u_int32_t Length;
  213 };
  214 
  215 struct CMD_MESSAGE_FIELD {
  216     struct CMD_MESSAGE cmdmessage; /* ioctl header */
  217     u_int8_t           messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */
  218 };
  219 
  220 /************************************************************************/
  221 /************************************************************************/
  222 
  223 #define ARCMSR_IOP_ERROR_ILLEGALPCI             0x0001
  224 #define ARCMSR_IOP_ERROR_VENDORID               0x0002
  225 #define ARCMSR_IOP_ERROR_DEVICEID               0x0002
  226 #define ARCMSR_IOP_ERROR_ILLEGALCDB             0x0003
  227 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR          0x0004
  228 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE        0x0005
  229 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G         0x0006
  230 #define ARCMSR_SYS_ERROR_MEMORY_LACK            0x0007
  231 #define ARCMSR_SYS_ERROR_MEMORY_RANGE           0x0008
  232 #define ARCMSR_SYS_ERROR_DEVICE_BASE            0x0009
  233 #define ARCMSR_SYS_ERROR_PORT_VALIDATE          0x000A
  234 
  235 /*DeviceType*/
  236 #define ARECA_SATA_RAID                         0x90000000
  237 
  238 /*FunctionCode*/
  239 #define FUNCTION_READ_RQBUFFER                  0x0801
  240 #define FUNCTION_WRITE_WQBUFFER                 0x0802
  241 #define FUNCTION_CLEAR_RQBUFFER                 0x0803
  242 #define FUNCTION_CLEAR_WQBUFFER                 0x0804
  243 #define FUNCTION_CLEAR_ALLQBUFFER               0x0805
  244 #define FUNCTION_REQUEST_RETURNCODE_3F          0x0806
  245 #define FUNCTION_SAY_HELLO                      0x0807
  246 #define FUNCTION_SAY_GOODBYE                    0x0808
  247 #define FUNCTION_FLUSH_ADAPTER_CACHE            0x0809
  248 /*
  249 ************************************************************************
  250 **      IOCTL CONTROL CODE
  251 ************************************************************************
  252 */
  253 /* ARECA IO CONTROL CODE*/
  254 #define ARCMSR_MESSAGE_READ_RQBUFFER            _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD)
  255 #define ARCMSR_MESSAGE_WRITE_WQBUFFER           _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD)
  256 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER           _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD)
  257 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER           _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD)
  258 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER         _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD)
  259 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F    _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD)
  260 #define ARCMSR_MESSAGE_SAY_HELLO                _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 
  261 #define ARCMSR_MESSAGE_SAY_GOODBYE              _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD)
  262 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE      _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
  263 
  264 /* ARECA IOCTL ReturnCode */
  265 #define ARCMSR_MESSAGE_RETURNCODE_OK            0x00000001
  266 #define ARCMSR_MESSAGE_RETURNCODE_ERROR         0x00000006
  267 #define ARCMSR_MESSAGE_RETURNCODE_3F            0x0000003F
  268 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON     0x00000088
  269 /* 
  270 ************************************************************************
  271 **                SPEC. for Areca HBA adapter
  272 ************************************************************************
  273 */
  274 /* signature of set and get firmware config */
  275 #define ARCMSR_SIGNATURE_GET_CONFIG             0x87974060
  276 #define ARCMSR_SIGNATURE_SET_CONFIG             0x87974063
  277 /* message code of inbound message register */
  278 #define ARCMSR_INBOUND_MESG0_NOP                0x00000000
  279 #define ARCMSR_INBOUND_MESG0_GET_CONFIG         0x00000001
  280 #define ARCMSR_INBOUND_MESG0_SET_CONFIG         0x00000002
  281 #define ARCMSR_INBOUND_MESG0_ABORT_CMD          0x00000003
  282 #define ARCMSR_INBOUND_MESG0_STOP_BGRB          0x00000004
  283 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE        0x00000005
  284 #define ARCMSR_INBOUND_MESG0_START_BGRB         0x00000006
  285 #define ARCMSR_INBOUND_MESG0_CHK331PENDING      0x00000007
  286 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER         0x00000008
  287 /* doorbell interrupt generator */
  288 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK     0x00000001
  289 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK      0x00000002
  290 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK    0x00000001
  291 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK     0x00000002
  292 /* srb areca cdb flag */
  293 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE           0x80000000
  294 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS            0x40000000
  295 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS           0x40000000
  296 #define ARCMSR_SRBREPLY_FLAG_ERROR              0x10000000
  297 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0        0x10000000
  298 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1        0x00000001
  299 /* outbound firmware ok */
  300 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK       0x80000000
  301 
  302 #define ARCMSR_ARC1680_BUS_RESET                0x00000003
  303 /* 
  304 ************************************************************************
  305 **                SPEC. for Areca HBB adapter
  306 ************************************************************************
  307 */
  308 /* ARECA HBB COMMAND for its FIRMWARE */
  309 #define ARCMSR_DRV2IOP_DOORBELL                 0x00020400    /* window of "instruction flags" from driver to iop */
  310 #define ARCMSR_DRV2IOP_DOORBELL_MASK            0x00020404
  311 #define ARCMSR_IOP2DRV_DOORBELL                 0x00020408    /* window of "instruction flags" from iop to driver */
  312 #define ARCMSR_IOP2DRV_DOORBELL_MASK            0x0002040C
  313 
  314 #define ARCMSR_IOP2DRV_DOORBELL_1203            0x00021870    /* window of "instruction flags" from iop to driver */
  315 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203       0x00021874
  316 #define ARCMSR_DRV2IOP_DOORBELL_1203            0x00021878    /* window of "instruction flags" from driver to iop */
  317 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203       0x0002187C
  318 
  319 /* ARECA FLAG LANGUAGE */
  320 #define ARCMSR_IOP2DRV_DATA_WRITE_OK            0x00000001        /* ioctl transfer */
  321 #define ARCMSR_IOP2DRV_DATA_READ_OK             0x00000002        /* ioctl transfer */
  322 #define ARCMSR_IOP2DRV_CDB_DONE                 0x00000004
  323 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE         0x00000008
  324 
  325 #define ARCMSR_DOORBELL_HANDLE_INT              0x0000000F
  326 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN       0xFF00FFF0
  327 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN        0xFF00FFF7
  328 
  329 #define ARCMSR_MESSAGE_GET_CONFIG               0x00010008      /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
  330 #define ARCMSR_MESSAGE_SET_CONFIG               0x00020008      /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
  331 #define ARCMSR_MESSAGE_ABORT_CMD                0x00030008      /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
  332 #define ARCMSR_MESSAGE_STOP_BGRB                0x00040008      /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
  333 #define ARCMSR_MESSAGE_FLUSH_CACHE              0x00050008      /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
  334 #define ARCMSR_MESSAGE_START_BGRB               0x00060008      /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
  335 #define ARCMSR_MESSAGE_START_DRIVER_MODE        0x000E0008      
  336 #define ARCMSR_MESSAGE_SET_POST_WINDOW          0x000F0008      
  337 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE          0x00100008
  338 #define ARCMSR_MESSAGE_FIRMWARE_OK              0x80000000      /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
  339 
  340 #define ARCMSR_DRV2IOP_DATA_WRITE_OK            0x00000001      /* ioctl transfer */
  341 #define ARCMSR_DRV2IOP_DATA_READ_OK             0x00000002      /* ioctl transfer */
  342 #define ARCMSR_DRV2IOP_CDB_POSTED               0x00000004
  343 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED       0x00000008
  344 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT         0x00000010  /*  */
  345 
  346 /* data tunnel buffer between user space program and its firmware */
  347 #define ARCMSR_MSGCODE_RWBUFFER                 0x0000fa00    /* iop msgcode_rwbuffer for message command */
  348 #define ARCMSR_IOCTL_WBUFFER                    0x0000fe00    /* user space data to iop 128bytes */
  349 #define ARCMSR_IOCTL_RBUFFER                    0x0000ff00    /* iop data to user space 128bytes */
  350 #define ARCMSR_HBB_BASE0_OFFSET                 0x00000010
  351 #define ARCMSR_HBB_BASE1_OFFSET                 0x00000018
  352 #define ARCMSR_HBB_BASE0_LEN                    0x00021000
  353 #define ARCMSR_HBB_BASE1_LEN                    0x00010000
  354 /* 
  355 ************************************************************************
  356 **                SPEC. for Areca HBC adapter
  357 ************************************************************************
  358 */
  359 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL                 12
  360 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE                   20
  361 /* Host Interrupt Mask */
  362 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK                 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
  363 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK         0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
  364 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK        0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
  365 #define ARCMSR_HBCMU_ALL_INTMASKENABLE                  0x0000000D /* disable all ISR */
  366 /* Host Interrupt Status */
  367 #define ARCMSR_HBCMU_UTILITY_A_ISR                      0x00000001
  368         /*
  369         ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 
  370         ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
  371         */
  372 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR              0x00000004
  373         /*
  374         ** Set if Outbound Doorbell register bits 30:1 have a non-zero
  375         ** value. This bit clears only when Outbound Doorbell bits
  376         ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
  377         ** Clear register clears bits in the Outbound Doorbell register.
  378         */
  379 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR             0x00000008
  380         /*
  381         ** Set whenever the Outbound Post List Producer/Consumer
  382         ** Register (FIFO) is not empty. It clears when the Outbound
  383         ** Post List FIFO is empty.
  384         */
  385 #define ARCMSR_HBCMU_SAS_ALL_INT                        0x00000010
  386         /*
  387         ** This bit indicates a SAS interrupt from a source external to
  388         ** the PCIe core. This bit is not maskable.
  389         */
  390 /* DoorBell*/
  391 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK                      0x00000002/**/
  392 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK                       0x00000004/**/
  393 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE                   0x00000008/*inbound message 0 ready*/
  394 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING               0x00000010/*more than 12 request completed in a time*/
  395 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK                      0x00000002/**/
  396 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR          0x00000002/*outbound DATA WRITE isr door bell clear*/
  397 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK                       0x00000004/**/
  398 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR           0x00000004/*outbound DATA READ isr door bell clear*/
  399 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE                   0x00000008/*outbound message 0 ready*/
  400 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR    0x00000008/*outbound message cmd isr door bell clear*/
  401 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK                        0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
  402 #define ARCMSR_HBCMU_RESET_ADAPTER                              0x00000024
  403 #define ARCMSR_HBCMU_DiagWrite_ENABLE                           0x00000080
  404 
  405 /* 
  406 ************************************************************************
  407 **                SPEC. for Areca HBD adapter
  408 ************************************************************************
  409 */
  410 #define ARCMSR_HBDMU_CHIP_ID                            0x00004
  411 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION           0x00008
  412 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK             0x00034
  413 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS              0x00200
  414 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE           0x0020C
  415 #define ARCMSR_HBDMU_INBOUND_MESSAGE0                   0x00400
  416 #define ARCMSR_HBDMU_INBOUND_MESSAGE1                   0x00404
  417 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0                  0x00420
  418 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1                  0x00424
  419 #define ARCMSR_HBDMU_INBOUND_DOORBELL                   0x00460
  420 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL                  0x00480
  421 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE           0x00484
  422 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW              0x01000
  423 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH             0x01004
  424 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER         0x01018
  425 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW             0x01060
  426 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH            0x01064
  427 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER         0x0106C
  428 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER         0x01070
  429 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE           0x01088
  430 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE          0x0108C
  431 
  432 #define ARCMSR_HBDMU_MESSAGE_WBUFFER                    0x02000
  433 #define ARCMSR_HBDMU_MESSAGE_RBUFFER                    0x02100
  434 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER                   0x02200
  435 
  436 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL               16
  437 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE                 20
  438 
  439 /* Host Interrupt Mask */
  440 #define ARCMSR_HBDMU_ALL_INT_ENABLE                     0x00001010      /* enable all ISR */
  441 #define ARCMSR_HBDMU_ALL_INT_DISABLE                    0x00000000      /* disable all ISR */
  442 
  443 /* Host Interrupt Status */
  444 #define ARCMSR_HBDMU_OUTBOUND_INT                       0x00001010
  445 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT              0x00001000
  446 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT             0x00000010
  447 
  448 /* DoorBell*/
  449 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY              0x00000001
  450 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ              0x00000002
  451 
  452 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK              0x00000001
  453 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK               0x00000002
  454 
  455 /*outbound message 0 ready*/
  456 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE           0x02000000
  457 
  458 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE                  0x02000003
  459 
  460 /*outbound message cmd isr door bell clear*/
  461 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR     0x02000000
  462 
  463 /*outbound list */
  464 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT            0x00000001
  465 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR      0x00000001
  466 
  467 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
  468 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK                0x80000000
  469 /* 
  470 *******************************************************************************
  471 **                SPEC. for Areca HBE adapter
  472 *******************************************************************************
  473 */
  474 #define ARCMSR_SIGNATURE_1884                           0x188417D3
  475 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR              0x00000001
  476 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR             0x00000008
  477 #define ARCMSR_HBEMU_ALL_INTMASKENABLE                  0x00000009 /* disable all ISR */
  478 
  479 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK              0x00000002
  480 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK               0x00000004
  481 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE           0x00000008 /* inbound message 0 ready */
  482 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK              0x00000002
  483 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK               0x00000004
  484 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE           0x00000008 /* outbound message 0 ready */
  485 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK                0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
  486 /* ARC-1884 doorbell sync */
  487 #define ARCMSR_HBEMU_DOORBELL_SYNC                      0x100
  488 #define ARCMSR_ARC188X_RESET_ADAPTER                    0x00000004
  489 /*
  490 *********************************************************************
  491 ** Message Unit structure
  492 *********************************************************************
  493 */
  494 struct HBA_MessageUnit
  495 {
  496         u_int32_t       resrved0[4];            /*0000 000F*/
  497         u_int32_t       inbound_msgaddr0;       /*0010 0013*/
  498         u_int32_t       inbound_msgaddr1;       /*0014 0017*/
  499         u_int32_t       outbound_msgaddr0;      /*0018 001B*/
  500         u_int32_t       outbound_msgaddr1;      /*001C 001F*/
  501         u_int32_t       inbound_doorbell;       /*0020 0023*/
  502         u_int32_t       inbound_intstatus;      /*0024 0027*/
  503         u_int32_t       inbound_intmask;        /*0028 002B*/
  504         u_int32_t       outbound_doorbell;      /*002C 002F*/
  505         u_int32_t       outbound_intstatus;     /*0030 0033*/
  506         u_int32_t       outbound_intmask;       /*0034 0037*/
  507         u_int32_t       reserved1[2];           /*0038 003F*/
  508         u_int32_t       inbound_queueport;      /*0040 0043*/
  509         u_int32_t       outbound_queueport;     /*0044 0047*/
  510         u_int32_t       reserved2[2];           /*0048 004F*/
  511         u_int32_t       reserved3[492];         /*0050 07FF ......local_buffer 492*/
  512         u_int32_t       reserved4[128];         /*0800 09FF                    128*/
  513         u_int32_t       msgcode_rwbuffer[256];  /*0a00 0DFF                    256*/
  514         u_int32_t       message_wbuffer[32];    /*0E00 0E7F                     32*/
  515         u_int32_t       reserved5[32];          /*0E80 0EFF                     32*/
  516         u_int32_t       message_rbuffer[32];    /*0F00 0F7F                     32*/
  517         u_int32_t       reserved6[32];          /*0F80 0FFF                     32*/
  518 };
  519 /*
  520 *********************************************************************
  521 ** 
  522 *********************************************************************
  523 */
  524 struct HBB_DOORBELL_1203
  525 {
  526         u_int8_t        doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */
  527         u_int32_t       iop2drv_doorbell;          /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */
  528         u_int32_t       iop2drv_doorbell_mask;     /*                  04,05,06,07: doorbell mask */
  529         u_int32_t       drv2iop_doorbell;          /*                  08,09,10,11: window of "instruction flags" from driver to iop */
  530         u_int32_t       drv2iop_doorbell_mask;     /*                  12,13,14,15: doorbell mask */
  531 };
  532 struct HBB_DOORBELL
  533 {
  534         u_int8_t        doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
  535         u_int32_t       drv2iop_doorbell;          /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
  536         u_int32_t       drv2iop_doorbell_mask;     /*                  04,05,06,07: doorbell mask */
  537         u_int32_t       iop2drv_doorbell;          /*                  08,09,10,11: window of "instruction flags" from iop to driver */
  538         u_int32_t       iop2drv_doorbell_mask;     /*                  12,13,14,15: doorbell mask */
  539 };
  540 /*
  541 *********************************************************************
  542 ** 
  543 *********************************************************************
  544 */
  545 struct HBB_RWBUFFER
  546 {
  547         u_int8_t        message_reserved0[ARCMSR_MSGCODE_RWBUFFER];   /*reserved */
  548         u_int32_t       msgcode_rwbuffer[256];      /*offset 0x0000fa00:   0,   1,   2,   3,...,1023: message code read write 1024bytes */
  549         u_int32_t       message_wbuffer[32];        /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
  550         u_int32_t       message_reserved1[32];      /*                  1152,1153,1154,1155,...,1279: message reserved*/
  551         u_int32_t       message_rbuffer[32];        /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 
  552 };
  553 /*
  554 *********************************************************************
  555 ** 
  556 *********************************************************************
  557 */
  558 struct HBB_MessageUnit
  559 {
  560         u_int32_t               post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];       /* post queue buffer for iop */
  561         u_int32_t               done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];       /* done queue buffer for iop */
  562         int32_t                 postq_index;                                  /* post queue index */
  563         int32_t                 doneq_index;                                                               /* done queue index */
  564         struct HBB_DOORBELL    *hbb_doorbell;
  565         struct HBB_RWBUFFER    *hbb_rwbuffer;
  566         bus_size_t              drv2iop_doorbell;          /* window of "instruction flags" from driver to iop */
  567         bus_size_t              drv2iop_doorbell_mask;     /* doorbell mask */
  568         bus_size_t              iop2drv_doorbell;          /* window of "instruction flags" from iop to driver */
  569         bus_size_t              iop2drv_doorbell_mask;     /* doorbell mask */
  570 };
  571 
  572 /*
  573 *********************************************************************
  574 ** 
  575 *********************************************************************
  576 */
  577 struct HBC_MessageUnit {
  578         u_int32_t       message_unit_status;                        /*0000 0003*/
  579         u_int32_t       slave_error_attribute;                      /*0004 0007*/
  580         u_int32_t       slave_error_address;                        /*0008 000B*/
  581         u_int32_t       posted_outbound_doorbell;                   /*000C 000F*/
  582         u_int32_t       master_error_attribute;                     /*0010 0013*/
  583         u_int32_t       master_error_address_low;                   /*0014 0017*/
  584         u_int32_t       master_error_address_high;                  /*0018 001B*/
  585         u_int32_t       hcb_size;                                   /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
  586         u_int32_t       inbound_doorbell;                           /*0020 0023*/
  587         u_int32_t       diagnostic_rw_data;                         /*0024 0027*/
  588         u_int32_t       diagnostic_rw_address_low;                  /*0028 002B*/
  589         u_int32_t       diagnostic_rw_address_high;                 /*002C 002F*/
  590         u_int32_t       host_int_status;                            /*0030 0033 host interrupt status*/
  591         u_int32_t       host_int_mask;                              /*0034 0037 host interrupt mask*/
  592         u_int32_t       dcr_data;                                   /*0038 003B*/
  593         u_int32_t       dcr_address;                                /*003C 003F*/
  594         u_int32_t       inbound_queueport;                          /*0040 0043 port32 host inbound queue port*/
  595         u_int32_t       outbound_queueport;                         /*0044 0047 port32 host outbound queue port*/
  596         u_int32_t       hcb_pci_address_low;                        /*0048 004B*/
  597         u_int32_t       hcb_pci_address_high;                       /*004C 004F*/
  598         u_int32_t       iop_int_status;                             /*0050 0053*/
  599         u_int32_t       iop_int_mask;                               /*0054 0057*/
  600         u_int32_t       iop_inbound_queue_port;                     /*0058 005B*/
  601         u_int32_t       iop_outbound_queue_port;                    /*005C 005F*/
  602         u_int32_t       inbound_free_list_index;                    /*0060 0063 inbound free list producer consumer index*/
  603         u_int32_t       inbound_post_list_index;                    /*0064 0067 inbound post list producer consumer index*/
  604         u_int32_t       outbound_free_list_index;                   /*0068 006B outbound free list producer consumer index*/
  605         u_int32_t       outbound_post_list_index;                   /*006C 006F outbound post list producer consumer index*/
  606         u_int32_t       inbound_doorbell_clear;                     /*0070 0073*/
  607         u_int32_t       i2o_message_unit_control;                   /*0074 0077*/
  608         u_int32_t       last_used_message_source_address_low;       /*0078 007B*/
  609         u_int32_t       last_used_message_source_address_high;      /*007C 007F*/
  610         u_int32_t       pull_mode_data_byte_count[4];               /*0080 008F pull mode data byte count0..count7*/
  611         u_int32_t       message_dest_address_index;                 /*0090 0093*/
  612         u_int32_t       done_queue_not_empty_int_counter_timer;     /*0094 0097*/
  613         u_int32_t       utility_A_int_counter_timer;                /*0098 009B*/
  614         u_int32_t       outbound_doorbell;                          /*009C 009F*/
  615         u_int32_t       outbound_doorbell_clear;                    /*00A0 00A3*/
  616         u_int32_t       message_source_address_index;               /*00A4 00A7 message accelerator source address consumer producer index*/
  617         u_int32_t       message_done_queue_index;                   /*00A8 00AB message accelerator completion queue consumer producer index*/
  618         u_int32_t       reserved0;                                  /*00AC 00AF*/
  619         u_int32_t       inbound_msgaddr0;                           /*00B0 00B3 scratchpad0*/
  620         u_int32_t       inbound_msgaddr1;                           /*00B4 00B7 scratchpad1*/
  621         u_int32_t       outbound_msgaddr0;                          /*00B8 00BB scratchpad2*/
  622         u_int32_t       outbound_msgaddr1;                          /*00BC 00BF scratchpad3*/
  623         u_int32_t       inbound_queueport_low;                      /*00C0 00C3 port64 host inbound queue port low*/
  624         u_int32_t       inbound_queueport_high;                     /*00C4 00C7 port64 host inbound queue port high*/
  625         u_int32_t       outbound_queueport_low;                     /*00C8 00CB port64 host outbound queue port low*/
  626         u_int32_t       outbound_queueport_high;                    /*00CC 00CF port64 host outbound queue port high*/
  627         u_int32_t       iop_inbound_queue_port_low;                 /*00D0 00D3*/
  628         u_int32_t       iop_inbound_queue_port_high;                /*00D4 00D7*/
  629         u_int32_t       iop_outbound_queue_port_low;                /*00D8 00DB*/
  630         u_int32_t       iop_outbound_queue_port_high;               /*00DC 00DF*/
  631         u_int32_t       message_dest_queue_port_low;                /*00E0 00E3 message accelerator destination queue port low*/
  632         u_int32_t       message_dest_queue_port_high;               /*00E4 00E7 message accelerator destination queue port high*/
  633         u_int32_t       last_used_message_dest_address_low;         /*00E8 00EB last used message accelerator destination address low*/
  634         u_int32_t       last_used_message_dest_address_high;        /*00EC 00EF last used message accelerator destination address high*/
  635         u_int32_t       message_done_queue_base_address_low;        /*00F0 00F3 message accelerator completion queue base address low*/
  636         u_int32_t       message_done_queue_base_address_high;       /*00F4 00F7 message accelerator completion queue base address high*/
  637         u_int32_t       host_diagnostic;                            /*00F8 00FB*/
  638         u_int32_t       write_sequence;                             /*00FC 00FF*/
  639         u_int32_t       reserved1[34];                              /*0100 0187*/
  640         u_int32_t       reserved2[1950];                            /*0188 1FFF*/
  641         u_int32_t       message_wbuffer[32];                        /*2000 207F*/
  642         u_int32_t       reserved3[32];                              /*2080 20FF*/
  643         u_int32_t       message_rbuffer[32];                        /*2100 217F*/
  644         u_int32_t       reserved4[32];                              /*2180 21FF*/
  645         u_int32_t       msgcode_rwbuffer[256];                      /*2200 23FF*/
  646 };
  647 /*
  648 *********************************************************************
  649 ** 
  650 *********************************************************************
  651 */
  652 struct InBound_SRB {
  653         uint32_t addressLow; //pointer to SRB block
  654         uint32_t addressHigh;
  655         uint32_t length; // in DWORDs
  656         uint32_t reserved0;
  657 };
  658 
  659 struct OutBound_SRB {
  660         uint32_t addressLow; //pointer to SRB block
  661         uint32_t addressHigh;
  662 };
  663 
  664 struct HBD_MessageUnit {
  665         uint32_t reserved0;
  666         uint32_t chip_id;                       //0x0004
  667         uint32_t cpu_mem_config;                //0x0008
  668         uint32_t reserved1[10];                 //0x000C
  669         uint32_t i2o_host_interrupt_mask;       //0x0034
  670         uint32_t reserved2[114];                //0x0038
  671         uint32_t host_int_status;               //0x0200
  672         uint32_t host_int_enable;               //0x0204
  673         uint32_t reserved3[1];                  //0x0208
  674         uint32_t pcief0_int_enable;             //0x020C
  675         uint32_t reserved4[124];                //0x0210
  676         uint32_t inbound_msgaddr0;              //0x0400
  677         uint32_t inbound_msgaddr1;              //0x0404
  678         uint32_t reserved5[6];                  //0x0408
  679         uint32_t outbound_msgaddr0;             //0x0420
  680         uint32_t outbound_msgaddr1;             //0x0424
  681         uint32_t reserved6[14];                 //0x0428
  682         uint32_t inbound_doorbell;              //0x0460
  683         uint32_t reserved7[7];                  //0x0464
  684         uint32_t outbound_doorbell;             //0x0480
  685         uint32_t outbound_doorbell_enable;      //0x0484
  686         uint32_t reserved8[734];                //0x0488
  687         uint32_t inboundlist_base_low;          //0x1000
  688         uint32_t inboundlist_base_high;         //0x1004
  689         uint32_t reserved9[4];                  //0x1008
  690         uint32_t inboundlist_write_pointer;     //0x1018
  691         uint32_t inboundlist_read_pointer;      //0x101C
  692         uint32_t reserved10[16];                //0x1020
  693         uint32_t outboundlist_base_low;         //0x1060
  694         uint32_t outboundlist_base_high;        //0x1064
  695         uint32_t reserved11;                    //0x1068
  696         uint32_t outboundlist_copy_pointer;     //0x106C
  697         uint32_t outboundlist_read_pointer;     //0x1070 0x1072
  698         uint32_t reserved12[5];                 //0x1074
  699         uint32_t outboundlist_interrupt_cause;  //0x1088
  700         uint32_t outboundlist_interrupt_enable; //0x108C
  701         uint32_t reserved13[988];               //0x1090
  702         uint32_t message_wbuffer[32];           //0x2000
  703         uint32_t reserved14[32];                //0x2080
  704         uint32_t message_rbuffer[32];           //0x2100
  705         uint32_t reserved15[32];                //0x2180
  706         uint32_t msgcode_rwbuffer[256];         //0x2200
  707 };
  708 
  709 struct HBD_MessageUnit0 {
  710         struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
  711         struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
  712         uint16_t postq_index;
  713         uint16_t doneq_index;
  714         struct HBD_MessageUnit  *phbdmu;
  715 };
  716 /*
  717 *********************************************************************
  718 ** 
  719 *********************************************************************
  720 */
  721 struct HBE_MessageUnit {
  722         u_int32_t       iobound_doorbell;                           /*0000 0003*/
  723         u_int32_t       write_sequence_3xxx;                        /*0004 0007*/
  724         u_int32_t       host_diagnostic_3xxx;                       /*0008 000B*/
  725         u_int32_t       posted_outbound_doorbell;                   /*000C 000F*/
  726         u_int32_t       master_error_attribute;                     /*0010 0013*/
  727         u_int32_t       master_error_address_low;                   /*0014 0017*/
  728         u_int32_t       master_error_address_high;                  /*0018 001B*/
  729         u_int32_t       hcb_size;                                   /*001C 001F*/
  730         u_int32_t       inbound_doorbell;                           /*0020 0023*/
  731         u_int32_t       diagnostic_rw_data;                         /*0024 0027*/
  732         u_int32_t       diagnostic_rw_address_low;                  /*0028 002B*/
  733         u_int32_t       diagnostic_rw_address_high;                 /*002C 002F*/
  734         u_int32_t       host_int_status;                            /*0030 0033 host interrupt status*/
  735         u_int32_t       host_int_mask;                              /*0034 0037 host interrupt mask*/
  736         u_int32_t       dcr_data;                                   /*0038 003B*/
  737         u_int32_t       dcr_address;                                /*003C 003F*/
  738         u_int32_t       inbound_queueport;                          /*0040 0043 port32 host inbound queue port*/
  739         u_int32_t       outbound_queueport;                         /*0044 0047 port32 host outbound queue port*/
  740         u_int32_t       hcb_pci_address_low;                        /*0048 004B*/
  741         u_int32_t       hcb_pci_address_high;                       /*004C 004F*/
  742         u_int32_t       iop_int_status;                             /*0050 0053*/
  743         u_int32_t       iop_int_mask;                               /*0054 0057*/
  744         u_int32_t       iop_inbound_queue_port;                     /*0058 005B*/
  745         u_int32_t       iop_outbound_queue_port;                    /*005C 005F*/
  746         u_int32_t       inbound_free_list_index;                    /*0060 0063*/
  747         u_int32_t       inbound_post_list_index;                    /*0064 0067*/
  748         u_int32_t       outbound_free_list_index;                   /*0068 006B*/
  749         u_int32_t       outbound_post_list_index;                   /*006C 006F*/
  750         u_int32_t       inbound_doorbell_clear;                     /*0070 0073*/
  751         u_int32_t       i2o_message_unit_control;                   /*0074 0077*/
  752         u_int32_t       last_used_message_source_address_low;       /*0078 007B*/
  753         u_int32_t       last_used_message_source_address_high;      /*007C 007F*/
  754         u_int32_t       pull_mode_data_byte_count[4];               /*0080 008F*/
  755         u_int32_t       message_dest_address_index;                 /*0090 0093*/
  756         u_int32_t       done_queue_not_empty_int_counter_timer;     /*0094 0097*/
  757         u_int32_t       utility_A_int_counter_timer;                /*0098 009B*/
  758         u_int32_t       outbound_doorbell;                          /*009C 009F*/
  759         u_int32_t       outbound_doorbell_clear;                    /*00A0 00A3*/
  760         u_int32_t       message_source_address_index;               /*00A4 00A7*/
  761         u_int32_t       message_done_queue_index;                   /*00A8 00AB*/
  762         u_int32_t       reserved0;                                  /*00AC 00AF*/
  763         u_int32_t       inbound_msgaddr0;                           /*00B0 00B3 scratchpad0*/
  764         u_int32_t       inbound_msgaddr1;                           /*00B4 00B7 scratchpad1*/
  765         u_int32_t       outbound_msgaddr0;                          /*00B8 00BB scratchpad2*/
  766         u_int32_t       outbound_msgaddr1;                          /*00BC 00BF scratchpad3*/
  767         u_int32_t       inbound_queueport_low;                      /*00C0 00C3 port64 host inbound queue port low*/
  768         u_int32_t       inbound_queueport_high;                     /*00C4 00C7 port64 host inbound queue port high*/
  769         u_int32_t       outbound_queueport_low;                     /*00C8 00CB port64 host outbound queue port low*/
  770         u_int32_t       outbound_queueport_high;                    /*00CC 00CF port64 host outbound queue port high*/
  771         u_int32_t       iop_inbound_queue_port_low;                 /*00D0 00D3*/
  772         u_int32_t       iop_inbound_queue_port_high;                /*00D4 00D7*/
  773         u_int32_t       iop_outbound_queue_port_low;                /*00D8 00DB*/
  774         u_int32_t       iop_outbound_queue_port_high;               /*00DC 00DF*/
  775         u_int32_t       message_dest_queue_port_low;                /*00E0 00E3*/
  776         u_int32_t       message_dest_queue_port_high;               /*00E4 00E7*/
  777         u_int32_t       last_used_message_dest_address_low;         /*00E8 00EB*/
  778         u_int32_t       last_used_message_dest_address_high;        /*00EC 00EF*/
  779         u_int32_t       message_done_queue_base_address_low;        /*00F0 00F3*/
  780         u_int32_t       message_done_queue_base_address_high;       /*00F4 00F7*/
  781         u_int32_t       host_diagnostic;                            /*00F8 00FB*/
  782         u_int32_t       write_sequence;                             /*00FC 00FF*/
  783         u_int32_t       reserved1[46];                              /*0100 01B7*/
  784         u_int32_t       reply_post_producer_index;                  /*01B8 01BB*/
  785         u_int32_t       reply_post_consumer_index;                  /*01BC 01BF*/
  786         u_int32_t       reserved2[1936];                            /*01C0 1FFF*/
  787         u_int32_t       message_wbuffer[32];                        /*2000 207F*/
  788         u_int32_t       reserved3[32];                              /*2080 20FF*/
  789         u_int32_t       message_rbuffer[32];                        /*2100 217F*/
  790         u_int32_t       reserved4[32];                              /*2180 21FF*/
  791         u_int32_t       msgcode_rwbuffer[256];                      /*2200 23FF*/
  792 };
  793 
  794 typedef struct deliver_completeQ {
  795         u_int16_t       cmdFlag;
  796         u_int16_t       cmdSMID;
  797         u_int16_t       cmdLMID;        // reserved (0)
  798         u_int16_t       cmdFlag2;       // reserved (0)
  799 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
  800 
  801 #define COMPLETION_Q_POOL_SIZE  (sizeof(struct deliver_completeQ) * 512 + 128)
  802 
  803 /*
  804 *********************************************************************
  805 ** 
  806 *********************************************************************
  807 */
  808 struct MessageUnit_UNION
  809 {
  810         union   {
  811                 struct HBA_MessageUnit          hbamu;
  812                 struct HBB_MessageUnit          hbbmu;
  813                 struct HBC_MessageUnit          hbcmu;
  814                 struct HBD_MessageUnit0         hbdmu;
  815                 struct HBE_MessageUnit          hbemu;
  816         } muu;
  817 };
  818 /* 
  819 *************************************************************
  820 **   structure for holding DMA address data 
  821 *************************************************************
  822 */
  823 #define IS_SG64_ADDR    0x01000000 /* bit24 */
  824 /*
  825 ************************************************************************************************
  826 **                            ARECA FIRMWARE SPEC
  827 ************************************************************************************************
  828 **              Usage of IOP331 adapter
  829 **              (All In/Out is in IOP331's view)
  830 **              1. Message 0 --> InitThread message and retrun code
  831 **              2. Doorbell is used for RS-232 emulation
  832 **                      inDoorBell :    bit0 -- data in ready            (DRIVER DATA WRITE OK)
  833 **                                      bit1 -- data out has been read   (DRIVER DATA READ OK)
  834 **                      outDooeBell:    bit0 -- data out ready           (IOP331 DATA WRITE OK)
  835 **                                      bit1 -- data in has been read    (IOP331 DATA READ OK)
  836 **              3. Index Memory Usage
  837 **                      offset 0xf00 : for RS232 out (request buffer)
  838 **                      offset 0xe00 : for RS232 in  (scratch buffer)
  839 **                      offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
  840 **                      offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
  841 **              4. RS-232 emulation
  842 **                      Currently 128 byte buffer is used
  843 **                                1st u_int32_t : Data length (1--124)
  844 **                              Byte 4--127 : Max 124 bytes of data
  845 **              5. PostQ
  846 **              All SCSI Command must be sent through postQ:
  847 **              (inbound queue port)    Request frame must be 32 bytes aligned 
  848 **                      #   bit27--bit31 => flag for post ccb 
  849 **                      #   bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb  
  850 **                                      bit31 : 0 : 256 bytes frame
  851 **                                              1 : 512 bytes frame
  852 **                                      bit30 : 0 : normal request
  853 **                                              1 : BIOS request
  854 **                                      bit29 : reserved
  855 **                                      bit28 : reserved
  856 **                                      bit27 : reserved
  857 **  -------------------------------------------------------------------------------
  858 **              (outbount queue port)   Request reply                          
  859 **                      #   bit27--bit31 => flag for reply
  860 **                      #   bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 
  861 **                      bit31 : must be 0 (for this type of reply)
  862 **                      bit30 : reserved for BIOS handshake
  863 **                      bit29 : reserved
  864 **                      bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
  865 **                              1 : Error, error code in AdapStatus/DevStatus/SenseData
  866 **                      bit27 : reserved
  867 **              6. BIOS request
  868 **                      All BIOS request is the same with request from PostQ
  869 **                      Except :
  870 **                              Request frame is sent from configuration space
  871 **                                      offset: 0x78 : Request Frame (bit30 == 1)
  872 **                                      offset: 0x18 : writeonly to generate IRQ to IOP331
  873 **                              Completion of request:
  874 **                                      (bit30 == 0, bit28==err flag)
  875 **              7. Definition of SGL entry (structure)
  876 **              8. Message1 Out - Diag Status Code (????)
  877 **              9. Message0 message code :
  878 **                      0x00 : NOP
  879 **                      0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
  880 **                                      Signature             0x87974060(4)
  881 **                                      Request len           0x00000200(4)
  882 **                                      numbers of queue      0x00000100(4)
  883 **                                      SDRAM Size            0x00000100(4)-->256 MB
  884 **                                      IDE Channels          0x00000008(4)
  885 **                                      vendor                40 bytes char
  886 **                                      model                  8 bytes char
  887 **                                      FirmVer               16 bytes char
  888 **                                      Device Map            16 bytes char
  889 **      
  890 **                                      FirmwareVersion DWORD <== Added for checking of new firmware capability
  891 **                      0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
  892 **                                      Signature             0x87974063(4)
  893 **                                      UPPER32 of Request Frame  (4)-->Driver Only
  894 **                      0x03 : Reset (Abort all queued Command)
  895 **                      0x04 : Stop Background Activity
  896 **                      0x05 : Flush Cache
  897 **                      0x06 : Start Background Activity (re-start if background is halted)
  898 **                      0x07 : Check If Host Command Pending (Novell May Need This Function)
  899 **                      0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
  900 **                                      byte 0 : 0xaa <-- signature
  901 **                                      byte 1 : 0x55 <-- signature
  902 **                                      byte 2 : year (04)
  903 **                                      byte 3 : month (1..12)
  904 **                                      byte 4 : date (1..31)
  905 **                                      byte 5 : hour (0..23)
  906 **                                      byte 6 : minute (0..59)
  907 **                                      byte 7 : second (0..59)
  908 **      *********************************************************************************
  909 **      Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter
  910 **      ==> Difference from IOP348
  911 **      <1> Message Register 0,1 (the same usage) Init Thread message and retrun code
  912 **           Inbound Message 0  (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP)
  913 **           Inbound Message 1  (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 
  914 **           Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 
  915 **           Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver)
  916 **           <A> use doorbell to generate interrupt
  917 **
  918 **               inbound doorbell: bit3 --  inbound message 0 ready (driver to iop)
  919 **              outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
  920 **
  921 **                      a. Message1: Out - Diag Status Code (????)
  922 **
  923 **                      b. Message0: message code 
  924 **                                  0x00 : NOP
  925 **                                  0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver)
  926 **                                                      Signature             0x87974060(4)
  927 **                                                      Request len           0x00000200(4)
  928 **                                                      numbers of queue      0x00000100(4)
  929 **                                                      SDRAM Size            0x00000100(4)-->256 MB
  930 **                                                      IDE Channels          0x00000008(4)
  931 **                                                      vendor                40 bytes char
  932 **                                                      model                  8 bytes char
  933 **                                                      FirmVer               16 bytes char
  934 **                                         Device Map            16 bytes char
  935 **                                         cfgVersion    ULONG <== Added for checking of new firmware capability
  936 **                                  0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP)
  937 **                                                      Signature             0x87974063(4)
  938 **                                                      UPPER32 of Request Frame  (4)-->Driver Only
  939 **                                  0x03 : Reset (Abort all queued Command)
  940 **                                  0x04 : Stop Background Activity
  941 **                                  0x05 : Flush Cache
  942 **                                  0x06 : Start Background Activity (re-start if background is halted)
  943 **                                  0x07 : Check If Host Command Pending (Novell May Need This Function)
  944 **                                  0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP)
  945 **                                                      byte 0 : 0xaa <-- signature
  946 **                                                      byte 1 : 0x55 <-- signature
  947 **                                                      byte 2 : year (04)
  948 **                                                      byte 3 : month (1..12)
  949 **                                                      byte 4 : date (1..31)
  950 **                                                      byte 5 : hour (0..23)
  951 **                                                      byte 6 : minute (0..59)
  952 **                                                      byte 7 : second (0..59)
  953 **
  954 **      <2> Doorbell Register is used for RS-232 emulation
  955 **           <A> different clear register
  956 **           <B> different bit0 definition (bit0 is reserved)
  957 **
  958 **           inbound doorbell        : at offset 0x20
  959 **           inbound doorbell clear  : at offset 0x70
  960 **
  961 **           inbound doorbell        : bit0 -- reserved
  962 **                                     bit1 -- data in ready             (DRIVER DATA WRITE OK)
  963 **                                     bit2 -- data out has been read    (DRIVER DATA READ OK)
  964 **                                     bit3 -- inbound message 0 ready
  965 **                                     bit4 -- more than 12 request completed in a time
  966 **
  967 **           outbound doorbell       : at offset 0x9C
  968 **           outbound doorbell clear : at offset 0xA0
  969 **
  970 **           outbound doorbell       : bit0 -- reserved
  971 **                                     bit1 -- data out ready            (IOP DATA WRITE OK)
  972 **                                     bit2 -- data in has been read     (IOP DATA READ OK)
  973 **                                     bit3 -- outbound message 0 ready
  974 **
  975 **      <3> Index Memory Usage (Buffer Area)
  976 **           COMPORT_IN     at  0x2000: message_wbuffer  --  128 bytes (to be sent to ROC) : for RS232 in  (scratch buffer)
  977 **           COMPORT_OUT    at  0x2100: message_rbuffer  --  128 bytes (to be sent to host): for RS232 out (request buffer)
  978 **           BIOS_CFG_AREA  at  0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver)
  979 **           BIOS_CFG_AREA  at  0x2200: msgcode_rwbuffer -- 1024 bytes for  inbound message code msgcode_rwbuffer (driver send to IOP)
  980 **
  981 **      <4> PostQ (Command Post Address)
  982 **          All SCSI Command must be sent through postQ:
  983 **              inbound  queue port32 at offset 0x40 , 0x41, 0x42, 0x43
  984 **              inbound  queue port64 at offset 0xC0 (lower)/0xC4 (upper)
  985 **              outbound queue port32 at offset 0x44
  986 **              outbound queue port64 at offset 0xC8 (lower)/0xCC (upper)
  987 **              <A> For 32bit queue, access low part is enough to send/receive request
  988 **                  i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the
  989 **                  same for outbound queue port
  990 **              <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction
  991 **                  to post inbound request in a single instruction, and use 64bit instruction
  992 **                  to retrieve outbound request in a single instruction.
  993 **                  If in 32bit environment, when sending inbound queue, write high part first
  994 **                  then write low part. For receiving outbound request, read high part first
  995 **                  then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF.
  996 **                  If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the
  997 **                  consistency of the FIFO. Another way to check empty is to check status flag
  998 **                  at 0x30 bit3.
  999 **              <C> Post Address IS NOT shifted (must be 16 bytes aligned)
 1000 **                  For   BIOS, 16bytes aligned   is OK
 1001 **                  For Driver, 32bytes alignment is recommended.
 1002 **                  POST Command bit0 to bit3 is defined differently
 1003 **                  ----------------------------
 1004 **                  bit0:1 for PULL mode (must be 1)
 1005 **                  ----------------------------
 1006 **                  bit3/2/1: for arcmsr cdb size (arccdbsize)
 1007 **                      000: <= 0x0080 (128)
 1008 **                      001: <= 0x0100 (256)
 1009 **                      010: <= 0x0180 (384)
 1010 **                      011: <= 0x0200 (512)
 1011 **                      100: <= 0x0280 (640)
 1012 **                      101: <= 0x0300 (768)
 1013 **                      110: <= 0x0300 (reserved)
 1014 **                      111: <= 0x0300 (reserved)
 1015 **                  -----------------------------
 1016 **                  if len > 0x300 the len always set as 0x300
 1017 **                  -----------------------------   
 1018 **                  post addr = addr | ((len-1) >> 6) | 1
 1019 **                  -----------------------------
 1020 **                  page length in command buffer still required, 
 1021 **
 1022 **                  if page length > 3, 
 1023 **                     firmware will assume more request data need to be retrieved 
 1024 **
 1025 **              <D> Outbound Posting
 1026 **                  bit0:0 , no error, 1 with error, refer to status buffer
 1027 **                  bit1:0 , reserved (will be 0)
 1028 **                  bit2:0 , reserved (will be 0)
 1029 **                  bit3:0 , reserved (will be 0)
 1030 **                  bit63-4: Completed command address
 1031 **
 1032 **              <E> BIOS support, no special support is required. 
 1033 **                  LSI2108 support I/O register
 1034 **                  All driver functionality is supported through I/O address
 1035 **
 1036 ************************************************************************************************
 1037 */
 1038 /*
 1039 **********************************
 1040 **
 1041 **********************************
 1042 */
 1043 /* size 8 bytes */
 1044 /* 32bit Scatter-Gather list */
 1045 struct SG32ENTRY {                 /* length bit 24 == 0 */
 1046         u_int32_t       length;    /* high 8 bit == flag,low 24 bit == length */
 1047         u_int32_t       address;
 1048 };
 1049 /* size 12 bytes */
 1050 /* 64bit Scatter-Gather list */
 1051 struct SG64ENTRY {                 /* length bit 24 == 1 */
 1052         u_int32_t       length;    /* high 8 bit == flag,low 24 bit == length */
 1053         u_int32_t       address; 
 1054         u_int32_t       addresshigh;
 1055 };
 1056 struct SGENTRY_UNION {
 1057         union {
 1058                 struct SG32ENTRY        sg32entry;   /* 30h   Scatter gather address  */
 1059                 struct SG64ENTRY        sg64entry;   /* 30h */
 1060         }u;
 1061 };
 1062 /*
 1063 **********************************
 1064 **
 1065 **********************************
 1066 */
 1067 struct QBUFFER {
 1068         u_int32_t     data_len;
 1069         u_int8_t      data[124];
 1070 };
 1071 /*
 1072 **********************************
 1073 */
 1074 typedef struct PHYS_ADDR64 {
 1075         u_int32_t       phyadd_low;
 1076         u_int32_t       phyadd_high;
 1077 }PHYSADDR64;
 1078 /*
 1079 ************************************************************************************************
 1080 **      FIRMWARE INFO
 1081 ************************************************************************************************
 1082 */
 1083 #define ARCMSR_FW_MODEL_OFFSET          15
 1084 #define ARCMSR_FW_VERS_OFFSET           17
 1085 #define ARCMSR_FW_DEVMAP_OFFSET         21
 1086 #define ARCMSR_FW_CFGVER_OFFSET         25
 1087 
 1088 struct FIRMWARE_INFO {
 1089         u_int32_t      signature;           /*0,00-03*/
 1090         u_int32_t      request_len;         /*1,04-07*/
 1091         u_int32_t      numbers_queue;       /*2,08-11*/
 1092         u_int32_t      sdram_size;          /*3,12-15*/
 1093         u_int32_t      ide_channels;        /*4,16-19*/
 1094         char           vendor[40];          /*5,20-59*/
 1095         char           model[8];            /*15,60-67*/
 1096         char           firmware_ver[16];    /*17,68-83*/
 1097         char           device_map[16];      /*21,84-99*/
 1098         u_int32_t      cfgVersion;          /*25,100-103 Added for checking of new firmware capability*/
 1099         char           cfgSerial[16];       /*26,104-119*/
 1100         u_int32_t      cfgPicStatus;        /*30,120-123*/
 1101 };
 1102 /*   (A) For cfgVersion in FIRMWARE_INFO
 1103 **        if low BYTE (byte#0) >= 3 (version 3)
 1104 **        then byte#1 report the capability of the firmware can xfer in a single request
 1105 **        
 1106 **        byte#1
 1107 **        0         256K
 1108 **        1         512K
 1109 **        2         1M
 1110 **        3         2M
 1111 **        4         4M
 1112 **        5         8M
 1113 **        6         16M
 1114 **    (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages
 1115 **        Driver support new xfer method need to set this field to indicate
 1116 **        large CDB block in 0x100 unit (we use 0x100 byte as one page)
 1117 **        e.g. If the length of CDB including MSG header and SGL is 0x1508
 1118 **        driver need to set the msgPages to 0x16
 1119 **    (C) REQ_LEN_512BYTE must be used also to indicate SRB length
 1120 **        e.g. CDB len      msgPages    REQ_LEN_512BYTE flag
 1121 **             <= 0x100     1               0
 1122 **             <= 0x200     2               1
 1123 **             <= 0x300     3               1
 1124 **             <= 0x400     4               1
 1125 **             .
 1126 **             .
 1127 */
 1128 
 1129 /*
 1130 ************************************************************************************************
 1131 **    size 0x1F8 (504)
 1132 ************************************************************************************************
 1133 */
 1134 struct ARCMSR_CDB {
 1135         u_int8_t        Bus;              /* 00h   should be 0            */
 1136         u_int8_t        TargetID;         /* 01h   should be 0--15        */
 1137         u_int8_t        LUN;              /* 02h   should be 0--7         */
 1138         u_int8_t        Function;         /* 03h   should be 1            */
 1139         
 1140         u_int8_t        CdbLength;        /* 04h   not used now           */
 1141         u_int8_t        sgcount;          /* 05h                          */
 1142         u_int8_t        Flags;            /* 06h                          */
 1143         u_int8_t        msgPages;         /* 07h                          */
 1144         
 1145         u_int32_t       Context;          /* 08h   Address of this request */
 1146         u_int32_t       DataLength;       /* 0ch   not used now           */
 1147         
 1148         u_int8_t        Cdb[16];          /* 10h   SCSI CDB               */
 1149         /*
 1150         ********************************************************
 1151         ** Device Status : the same from SCSI bus if error occur 
 1152         ** SCSI bus status codes.
 1153         ********************************************************
 1154         */
 1155         u_int8_t        DeviceStatus;     /* 20h   if error                */
 1156         
 1157         u_int8_t        SenseData[15];    /* 21h   output                  */        
 1158         
 1159         union {
 1160                 struct SG32ENTRY        sg32entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h   Scatter gather address  */
 1161                 struct SG64ENTRY        sg64entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h                           */
 1162         } u;
 1163 };
 1164 /* CDB flag */
 1165 #define ARCMSR_CDB_FLAG_SGL_BSIZE               0x01    /* bit 0: 0(256) / 1(512) bytes         */
 1166 #define ARCMSR_CDB_FLAG_BIOS                    0x02    /* bit 1: 0(from driver) / 1(from BIOS) */
 1167 #define ARCMSR_CDB_FLAG_WRITE                   0x04    /* bit 2: 0(Data in) / 1(Data out)      */
 1168 #define ARCMSR_CDB_FLAG_SIMPLEQ                 0x00    /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
 1169 #define ARCMSR_CDB_FLAG_HEADQ                   0x08
 1170 #define ARCMSR_CDB_FLAG_ORDEREDQ                0x10
 1171 /* scsi status */
 1172 #define SCSISTAT_GOOD                           0x00
 1173 #define SCSISTAT_CHECK_CONDITION                0x02
 1174 #define SCSISTAT_CONDITION_MET                  0x04
 1175 #define SCSISTAT_BUSY                           0x08
 1176 #define SCSISTAT_INTERMEDIATE                   0x10
 1177 #define SCSISTAT_INTERMEDIATE_COND_MET          0x14
 1178 #define SCSISTAT_RESERVATION_CONFLICT           0x18
 1179 #define SCSISTAT_COMMAND_TERMINATED             0x22
 1180 #define SCSISTAT_QUEUE_FULL                     0x28
 1181 /* DeviceStatus */
 1182 #define ARCMSR_DEV_SELECT_TIMEOUT               0xF0
 1183 #define ARCMSR_DEV_ABORTED                      0xF1
 1184 #define ARCMSR_DEV_INIT_FAIL                    0xF2
 1185 /*
 1186 *********************************************************************
 1187 **                   Command Control Block (SrbExtension)
 1188 ** SRB must be not cross page boundary,and the order from offset 0
 1189 **         structure describing an ATA disk request
 1190 **             this SRB length must be 32 bytes boundary
 1191 *********************************************************************
 1192 */
 1193 struct CommandControlBlock {
 1194         struct ARCMSR_CDB       arcmsr_cdb;             /* 0  -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
 1195         u_int32_t               cdb_phyaddr_low;        /* 504-507 */
 1196         u_int32_t               arc_cdb_size;           /* 508-511 */
 1197         /*  ======================512+32 bytes============================  */
 1198         union ccb               *pccb;                  /* 512-515 516-519 pointer of freebsd scsi command */
 1199         struct AdapterControlBlock      *acb;           /* 520-523 524-527 */
 1200         bus_dmamap_t            dm_segs_dmamap;         /* 528-531 532-535 */
 1201         u_int16_t               srb_flags;              /* 536-537 */
 1202         u_int16_t               srb_state;              /* 538-539 */
 1203         u_int32_t               cdb_phyaddr_high;       /* 540-543 */
 1204         struct  callout         ccb_callout;
 1205         u_int32_t               smid;
 1206     /*  ==========================================================  */
 1207 };
 1208 /*      srb_flags */
 1209 #define         SRB_FLAG_READ                   0x0000
 1210 #define         SRB_FLAG_WRITE                  0x0001
 1211 #define         SRB_FLAG_ERROR                  0x0002
 1212 #define         SRB_FLAG_FLUSHCACHE             0x0004
 1213 #define         SRB_FLAG_MASTER_ABORTED         0x0008
 1214 #define         SRB_FLAG_DMAVALID               0x0010
 1215 #define         SRB_FLAG_DMACONSISTENT          0x0020
 1216 #define         SRB_FLAG_DMAWRITE               0x0040
 1217 #define         SRB_FLAG_PKTBIND                0x0080
 1218 #define         SRB_FLAG_TIMER_START            0x0080
 1219 /*      srb_state */
 1220 #define         ARCMSR_SRB_DONE                 0x0000
 1221 #define         ARCMSR_SRB_UNBUILD              0x0000
 1222 #define         ARCMSR_SRB_TIMEOUT              0x1111
 1223 #define         ARCMSR_SRB_RETRY                0x2222
 1224 #define         ARCMSR_SRB_START                0x55AA
 1225 #define         ARCMSR_SRB_PENDING              0xAA55
 1226 #define         ARCMSR_SRB_RESET                0xA5A5
 1227 #define         ARCMSR_SRB_ABORTED              0x5A5A
 1228 #define         ARCMSR_SRB_ILLEGAL              0xFFFF
 1229 
 1230 #define         SRB_SIZE        ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
 1231 #define         ARCMSR_SRBS_POOL_SIZE   (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
 1232 
 1233 /*
 1234 *********************************************************************
 1235 **                 Adapter Control Block
 1236 *********************************************************************
 1237 */
 1238 #define ACB_ADAPTER_TYPE_A      0x00000000      /* hba I IOP */
 1239 #define ACB_ADAPTER_TYPE_B      0x00000001      /* hbb M IOP */
 1240 #define ACB_ADAPTER_TYPE_C      0x00000002      /* hbc L IOP */
 1241 #define ACB_ADAPTER_TYPE_D      0x00000003      /* hbd M IOP */
 1242 #define ACB_ADAPTER_TYPE_E      0x00000004      /* hbd L IOP */
 1243 
 1244 struct AdapterControlBlock {
 1245         u_int32_t               adapter_type;           /* adapter A,B..... */
 1246         
 1247         bus_space_tag_t         btag[2];
 1248         bus_space_handle_t      bhandle[2];
 1249         bus_dma_tag_t           parent_dmat;
 1250         bus_dma_tag_t           dm_segs_dmat;           /* dmat for buffer I/O */  
 1251         bus_dma_tag_t           srb_dmat;               /* dmat for freesrb */
 1252         bus_dmamap_t            srb_dmamap;
 1253         device_t                pci_dev;
 1254 #if __FreeBSD_version < 503000
 1255         dev_t                   ioctl_dev;
 1256 #else
 1257         struct cdev             *ioctl_dev;
 1258 #endif
 1259         int                     pci_unit;
 1260         
 1261         struct resource         *sys_res_arcmsr[2];
 1262         struct resource         *irqres[ARCMSR_NUM_MSIX_VECTORS];
 1263         void                    *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */
 1264         int                     irq_id[ARCMSR_NUM_MSIX_VECTORS];
 1265         
 1266         /* Hooks into the CAM XPT */
 1267         struct                  cam_sim *psim;
 1268         struct                  cam_path *ppath;
 1269         u_int8_t                *uncacheptr;
 1270         unsigned long           vir2phy_offset;
 1271         union   {
 1272                 unsigned long   phyaddr;
 1273                 struct {
 1274                         u_int32_t       phyadd_low;
 1275                         u_int32_t       phyadd_high;
 1276                 }B;
 1277         }srb_phyaddr;
 1278 //      unsigned long                           srb_phyaddr;
 1279         /* Offset is used in making arc cdb physical to virtual calculations */
 1280         u_int32_t               outbound_int_enable;
 1281         
 1282         struct MessageUnit_UNION        *pmu;           /* message unit ATU inbound base address0 */
 1283         
 1284         u_int8_t                adapter_index;
 1285         u_int8_t                irq;
 1286         u_int16_t               acb_flags;
 1287         
 1288         struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM];     /* serial srb pointer array */
 1289         struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM];   /* working srb pointer array */
 1290         int32_t                 workingsrb_doneindex;           /* done srb array index */
 1291         int32_t                 workingsrb_startindex;          /* start srb array index  */
 1292         int32_t                 srboutstandingcount;
 1293         
 1294         u_int8_t                rqbuffer[ARCMSR_MAX_QBUFFER];   /* data collection buffer for read from 80331 */
 1295         u_int32_t               rqbuf_firstindex;               /* first of read buffer  */
 1296         u_int32_t               rqbuf_lastindex;                /* last of read buffer   */
 1297         
 1298         u_int8_t                wqbuffer[ARCMSR_MAX_QBUFFER];   /* data collection buffer for write to 80331  */
 1299         u_int32_t               wqbuf_firstindex;               /* first of write buffer */
 1300         u_int32_t               wqbuf_lastindex;                /* last of write buffer  */
 1301         
 1302         arcmsr_lock_t           isr_lock;
 1303         arcmsr_lock_t           srb_lock;
 1304         arcmsr_lock_t           postDone_lock;
 1305         arcmsr_lock_t           qbuffer_lock;
 1306         
 1307         u_int8_t                devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
 1308         u_int32_t               num_resets;
 1309         u_int32_t               num_aborts;
 1310         u_int32_t               firm_request_len;       /*1,04-07*/
 1311         u_int32_t               firm_numbers_queue;     /*2,08-11*/
 1312         u_int32_t               firm_sdram_size;        /*3,12-15*/
 1313         u_int32_t               firm_ide_channels;      /*4,16-19*/
 1314         u_int32_t               firm_cfg_version;
 1315         char                    firm_model[12];         /*15,60-67*/
 1316         char                    firm_version[20];       /*17,68-83*/
 1317         char                    device_map[20];         /*21,84-99 */
 1318         struct  callout         devmap_callout;
 1319         u_int32_t               pktRequestCount;
 1320         u_int32_t               pktReturnCount;
 1321         u_int32_t               vendor_device_id;
 1322         u_int32_t               adapter_bus_speed;
 1323         u_int32_t               maxOutstanding;
 1324         u_int16_t               sub_device_id;
 1325         u_int32_t               doneq_index;
 1326         u_int32_t               in_doorbell;
 1327         u_int32_t               out_doorbell;
 1328         u_int32_t               completionQ_entry;
 1329         pCompletion_Q           pCompletionQ;
 1330         int                     msix_vectors;
 1331         int                     rid[2];
 1332 };/* HW_DEVICE_EXTENSION */
 1333 /* acb_flags */
 1334 #define ACB_F_SCSISTOPADAPTER           0x0001
 1335 #define ACB_F_MSG_STOP_BGRB             0x0002          /* stop RAID background rebuild */
 1336 #define ACB_F_MSG_START_BGRB            0x0004          /* stop RAID background rebuild */
 1337 #define ACB_F_IOPDATA_OVERFLOW          0x0008          /* iop ioctl data rqbuffer overflow */
 1338 #define ACB_F_MESSAGE_WQBUFFER_CLEARED  0x0010          /* ioctl clear wqbuffer */
 1339 #define ACB_F_MESSAGE_RQBUFFER_CLEARED  0x0020          /* ioctl clear rqbuffer */
 1340 #define ACB_F_MESSAGE_WQBUFFER_READ     0x0040
 1341 #define ACB_F_BUS_RESET                 0x0080
 1342 #define ACB_F_IOP_INITED                0x0100          /* iop init */
 1343 #define ACB_F_MAPFREESRB_FAILD          0x0200          /* arcmsr_map_freesrb faild */
 1344 #define ACB_F_CAM_DEV_QFRZN             0x0400
 1345 #define ACB_F_BUS_HANG_ON               0x0800          /* need hardware reset bus */
 1346 #define ACB_F_SRB_FUNCTION_POWER        0x1000
 1347 #define ACB_F_MSIX_ENABLED              0x2000
 1348 /* devstate */
 1349 #define ARECA_RAID_GONE                 0x55
 1350 #define ARECA_RAID_GOOD                 0xaa
 1351 /* adapter_bus_speed */
 1352 #define ACB_BUS_SPEED_3G        0
 1353 #define ACB_BUS_SPEED_6G        1
 1354 #define ACB_BUS_SPEED_12G       2
 1355 /*
 1356 *************************************************************
 1357 *************************************************************
 1358 */
 1359 struct SENSE_DATA {
 1360     u_int8_t    ErrorCode:7;
 1361     u_int8_t    Valid:1;
 1362     u_int8_t    SegmentNumber;
 1363     u_int8_t    SenseKey:4;
 1364     u_int8_t    Reserved:1;
 1365     u_int8_t    IncorrectLength:1;
 1366     u_int8_t    EndOfMedia:1;
 1367     u_int8_t    FileMark:1;
 1368     u_int8_t    Information[4];
 1369     u_int8_t    AdditionalSenseLength;
 1370     u_int8_t    CommandSpecificInformation[4];
 1371     u_int8_t    AdditionalSenseCode;
 1372     u_int8_t    AdditionalSenseCodeQualifier;
 1373     u_int8_t    FieldReplaceableUnitCode;
 1374     u_int8_t    SenseKeySpecific[3];
 1375 };
 1376 /* 
 1377 **********************************
 1378 **  Peripheral Device Type definitions 
 1379 **********************************
 1380 */
 1381 #define SCSI_DASD               0x00       /* Direct-access Device         */
 1382 #define SCSI_SEQACESS           0x01       /* Sequential-access device     */
 1383 #define SCSI_PRINTER            0x02       /* Printer device               */
 1384 #define SCSI_PROCESSOR          0x03       /* Processor device             */
 1385 #define SCSI_WRITEONCE          0x04       /* Write-once device            */
 1386 #define SCSI_CDROM              0x05       /* CD-ROM device                */
 1387 #define SCSI_SCANNER            0x06       /* Scanner device               */
 1388 #define SCSI_OPTICAL            0x07       /* Optical memory device        */
 1389 #define SCSI_MEDCHGR            0x08       /* Medium changer device        */
 1390 #define SCSI_COMM               0x09       /* Communications device        */
 1391 #define SCSI_NODEV              0x1F       /* Unknown or no device type    */
 1392 /*
 1393 ************************************************************************************************************
 1394 **                                       @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 1395 **                                                        80331 PCI-to-PCI Bridge
 1396 **                                                        PCI Configuration Space 
 1397 **                              
 1398 **                                       @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 1399 **                                                          Programming Interface
 1400 **                                                        ========================
 1401 **                                          Configuration Register Address Space Groupings and Ranges
 1402 **                                       =============================================================
 1403 **                                               Register Group                      Configuration  Offset
 1404 **                                       -------------------------------------------------------------
 1405 **                                          Standard PCI Configuration                      00-3Fh
 1406 **                                       -------------------------------------------------------------
 1407 **                                           Device Specific Registers                      40-A7h
 1408 **                                       -------------------------------------------------------------
 1409 **                                                 Reserved                                 A8-CBh
 1410 **                                       -------------------------------------------------------------
 1411 **                                            Enhanced Capability List                      CC-FFh
 1412 ** ==========================================================================================================
 1413 **                         Standard PCI [Type 1] Configuration Space Address Map
 1414 ** **********************************************************************************************************
 1415 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              |   Configu-ration Byte Offset
 1416 ** ----------------------------------------------------------------------------------------------------------
 1417 ** |                    Device ID                    |                     Vendor ID                      | 00h
 1418 ** ----------------------------------------------------------------------------------------------------------
 1419 ** |                 Primary Status                  |                  Primary Command                   | 04h
 1420 ** ----------------------------------------------------------------------------------------------------------
 1421 ** |                   Class Code                                             |        RevID              | 08h
 1422 ** ----------------------------------------------------------------------------------------------------------
 1423 ** |        reserved        |      Header Type       |      Primary MLT       |      Primary CLS          | 0Ch
 1424 ** ----------------------------------------------------------------------------------------------------------
 1425 ** |                                             Reserved                                                 | 10h
 1426 ** ----------------------------------------------------------------------------------------------------------
 1427 ** |                                             Reserved                                                 | 14h
 1428 ** ----------------------------------------------------------------------------------------------------------
 1429 ** |     Secondary MLT      | Subordinate Bus Number |  Secondary Bus Number  |     Primary Bus Number    | 18h
 1430 ** ----------------------------------------------------------------------------------------------------------
 1431 ** |                 Secondary Status                |       I/O Limit        |        I/O Base           | 1Ch
 1432 ** ----------------------------------------------------------------------------------------------------------
 1433 ** |      Non-prefetchable Memory Limit Address      |       Non-prefetchable Memory Base Address         | 20h
 1434 ** ----------------------------------------------------------------------------------------------------------
 1435 ** |        Prefetchable Memory Limit Address        |           Prefetchable Memory Base Address         | 24h
 1436 ** ----------------------------------------------------------------------------------------------------------
 1437 ** |                          Prefetchable Memory Base Address Upper 32 Bits                              | 28h
 1438 ** ----------------------------------------------------------------------------------------------------------
 1439 ** |                          Prefetchable Memory Limit Address Upper 32 Bits                             | 2Ch
 1440 ** ----------------------------------------------------------------------------------------------------------
 1441 ** |             I/O Limit Upper 16 Bits             |                 I/O Base Upper 16                  | 30h
 1442 ** ----------------------------------------------------------------------------------------------------------
 1443 ** |                                Reserved                                  |   Capabilities Pointer    | 34h
 1444 ** ----------------------------------------------------------------------------------------------------------
 1445 ** |                                             Reserved                                                 | 38h
 1446 ** ----------------------------------------------------------------------------------------------------------
 1447 ** |                   Bridge Control                |  Primary Interrupt Pin | Primary Interrupt Line    | 3Ch
 1448 **=============================================================================================================
 1449 */
 1450 /*
 1451 **=============================================================================================================
 1452 **  0x03-0x00 : 
 1453 ** Bit       Default             Description
 1454 **31:16       0335h            Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
 1455 **                             ID is unique per product speed as indicated.
 1456 **15:00       8086h            Vendor ID (VID): 16-bit field which indicates that Intel is the vendor.
 1457 **=============================================================================================================
 1458 */
 1459 #define     ARCMSR_PCI2PCI_VENDORID_REG                  0x00    /*word*/
 1460 #define     ARCMSR_PCI2PCI_DEVICEID_REG                  0x02    /*word*/
 1461 /*
 1462 **==============================================================================
 1463 **  0x05-0x04 : command register 
 1464 ** Bit       Default                           Description
 1465 **15:11        00h                                           Reserved
 1466 ** 10          0                                           Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 
 1467 **                                                                            The bridge does not support interrupts.
 1468 ** 09          0                                                 FB2B Enable: Enables/Disables the generation of fast back to back 
 1469 **                                                                              transactions on the primary bus. 
 1470 **                                                                            The bridge does not generate fast back to back 
 1471 **                                                                              transactions on the primary bus.
 1472 ** 08          0                                          SERR# Enable (SEE): Enables primary bus SERR# assertions.
 1473 **                                                                            0=The bridge does not assert P_SERR#.
 1474 **                                                                            1=The bridge may assert P_SERR#, subject to other programmable criteria.
 1475 ** 07          0                                    Wait Cycle Control (WCC): Always returns 0bzero indicating 
 1476 **                                                                              that bridge does not perform address or data stepping,
 1477 ** 06          0                                 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
 1478 **                                                                            0=When a data parity error is detected bridge does not assert S_PERR#. 
 1479 **                                                                                Also bridge does not assert P_SERR# in response to 
 1480 **                                                                                      a detected address or attribute parity error.
 1481 **                                                                            1=When a data parity error is detected bridge asserts S_PERR#. 
 1482 **                                                                                The bridge also asserts P_SERR# 
 1483 **                                                                                      (when enabled globally via bit(8) of this register) 
 1484 **                                                                                      in response to a detected address or attribute parity error.
 1485 ** 05          0                  VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 
 1486 **                                                                    VGA palette write transactions are I/O transactions
 1487 **                                                                               whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
 1488 **                                                                    P_AD[15:10] are not decoded (i.e. aliases are claimed), 
 1489 **                                                                              or are fully decoding 
 1490 **                                                                              (i.e., must be all 0's depending upon the VGA 
 1491 **                                                                              aliasing bit in the Bridge Control Register, offset 3Eh.
 1492 **                                                                    P_AD[31:16] equal to 0000h
 1493 **                                                                    0=The bridge ignores VGA palette write transactions, 
 1494 **                                                                              unless decoded by the standard I/O address range window.
 1495 **                                                                    1=The bridge responds to VGA palette write transactions 
 1496 **                                                                              with medium DEVSEL# timing and forwards them to the secondary bus.
 1497 ** 04          0   Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 
 1498 **                                                            MWI transactions targeting resources on the opposite side of the bridge, 
 1499 **                                                                              however, are forwarded as MWI transactions.
 1500 ** 03          0                  Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 
 1501 **                                                            This bit is read only and always returns 0 when read
 1502 ** 02          0                     Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
 1503 **                                                            Initiation of configuration transactions is not affected by the state of this bit.
 1504 **                                                            0=The bridge does not initiate memory or I/O transactions on the primary interface.
 1505 **                                                            1=The bridge is enabled to function as an initiator on the primary interface.
 1506 ** 01          0                   Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface.
 1507 **                                                            0=The bridge target response to memory transactions on the primary interface is disabled.
 1508 **                                                            1=The bridge target response to memory transactions on the primary interface is enabled.
 1509 ** 00          0                     I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface.
 1510 **                                                            0=The bridge target response to I/O transactions on the primary interface is disabled.
 1511 **                                                            1=The bridge target response to I/O transactions on the primary interface is enabled.
 1512 **==============================================================================
 1513 */
 1514 #define     ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG          0x04    /*word*/
 1515 #define     PCI_DISABLE_INTERRUPT                                       0x0400
 1516 /*
 1517 **==============================================================================
 1518 **  0x07-0x06 : status register 
 1519 ** Bit       Default                       Description
 1520 ** 15          0                       Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 
 1521 **                                                                      attribute or data parity error. 
 1522 **                                                            This bit is set regardless of the state of the PER bit in the command register.
 1523 ** 14          0                       Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
 1524 ** 13          0                       Received Master Abort: The bridge sets this bit to a 1b when, 
 1525 **                                                                      acting as the initiator on the primary bus, 
 1526 **                                                                      its transaction (with the exception of special cycles) 
 1527 **                                                                      has been terminated with a Master Abort.
 1528 ** 12          0                       Received Target Abort: The bridge sets this bit to a 1b when, 
 1529 **                                                                      acting as the initiator on the primary bus, 
 1530 **                                                                      its transaction has been terminated with a Target Abort.
 1531 ** 11          0                       Signaled Target Abort: The bridge sets this bit to a 1b when it, 
 1532 **                                                                      as the target of a transaction, terminates it with a Target Abort. 
 1533 **                                                            In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
 1534 ** 10:09       01                             DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 
 1535 **                                                            Returns ˇ§01bˇ¨ when read, indicating that bridge responds no slower than with medium timing.
 1536 ** 08          0                    Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 
 1537 **                                                                      The bridge is the current master on the primary bus
 1538 **                                                            S_PERR# is detected asserted or is asserted by bridge
 1539 **                                                            The Parity Error Response bit is set in the Command register
 1540 ** 07          1                   Fast Back to Back Capable: Returns a 1b when read indicating that bridge 
 1541 **                                                                      is able to respond to fast back to back transactions on its primary interface.
 1542 ** 06          0                             Reserved
 1543 ** 05          1                   66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
 1544 **                                                            1 =
 1545 ** 04          1                    Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 
 1546 **                                                            Offset 34h (Capability Pointer register) 
 1547 **                                                                              provides the offset for the first entry 
 1548 **                                                                              in the linked list of enhanced capabilities.
 1549 ** 03          0                            Interrupt Status: Reflects the state of the interrupt in the device/function.
 1550 **                                                            The bridge does not support interrupts.
 1551 ** 02:00       000                           Reserved
 1552 **==============================================================================
 1553 */
 1554 #define     ARCMSR_PCI2PCI_PRIMARY_STATUS_REG        0x06    /*word: 06,07 */
 1555 #define          ARCMSR_ADAP_66MHZ                   0x20
 1556 /*
 1557 **==============================================================================
 1558 **  0x08 : revision ID 
 1559 ** Bit       Default                       Description
 1560 ** 07:00       00000000                  Revision ID (RID): '00h' indicating bridge A-0 stepping.
 1561 **==============================================================================
 1562 */
 1563 #define     ARCMSR_PCI2PCI_REVISIONID_REG                    0x08    /*byte*/
 1564 /*
 1565 **==============================================================================
 1566 **  0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 
 1567 ** Bit       Default                       Description
 1568 ** 23:16       06h                     Base Class Code (BCC): Indicates that this is a bridge device.
 1569 ** 15:08       04h                      Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
 1570 ** 07:00       00h               Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
 1571 **==============================================================================
 1572 */
 1573 #define     ARCMSR_PCI2PCI_CLASSCODE_REG                 0x09    /*3bytes*/
 1574 /*
 1575 **==============================================================================
 1576 **  0x0c : cache line size 
 1577 ** Bit       Default                       Description
 1578 ** 07:00       00h                     Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
 1579 **                                                            The contents of this register are factored into 
 1580 **                                                                      internal policy decisions associated with memory read prefetching, 
 1581 **                                                                      and the promotion of Memory Write transactions to MWI transactions.
 1582 **                                                            Valid cache line sizes are 8 and 16 dwords. 
 1583 **                                                            When the cache line size is set to an invalid value, 
 1584 **                                                                      bridge behaves as though the cache line size was set to 00h.
 1585 **==============================================================================
 1586 */
 1587 #define     ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C    /*byte*/
 1588 /*
 1589 **==============================================================================
 1590 **  0x0d : latency timer (number of pci clock 00-ff ) 
 1591 ** Bit       Default                       Description
 1592 **                                   Primary Latency Timer (PTV):
 1593 ** 07:00      00h (Conventional PCI)   Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
 1594 **                                                            referenced from the assertion of FRAME# to the expiration of the timer, 
 1595 **                                                            when bridge may continue as master of the current transaction. All bits are writable, 
 1596 **                                                            resulting in a granularity of 1 PCI clock cycle. 
 1597 **                                                            When the timer expires (i.e., equals 00h) 
 1598 **                                                                      bridge relinquishes the bus after the first data transfer 
 1599 **                                                                      when its PCI bus grant has been deasserted.
 1600 **         or 40h (PCI-X)                         PCI-X Mode: Primary bus Master latency timer. 
 1601 **                                                            Indicates the number of PCI clock cycles,
 1602 **                                                            referenced from the assertion of FRAME# to the expiration of the timer, 
 1603 **                                                            when bridge may continue as master of the current transaction. 
 1604 **                                                            All bits are writable, resulting in a granularity of 1 PCI clock cycle. 
 1605 **                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 
 1606 **                                                            (Except in the case where MLT expires within 3 data phases 
 1607 **                                                              of an ADB.In this case bridge continues on 
 1608 **                                                              until it reaches the next ADB before relinquishing the bus.)
 1609 **==============================================================================
 1610 */
 1611 #define     ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG      0x0D    /*byte*/
 1612 /*
 1613 **==============================================================================
 1614 **  0x0e : (header type,single function ) 
 1615 ** Bit       Default                       Description
 1616 ** 07           0                Multi-function device (MVD): 80331 is a single-function device.
 1617 ** 06:00       01h                       Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 
 1618 **                                                            Returns ˇ§01hˇ¨ when read indicating 
 1619 **                                                              that the register layout conforms to the standard PCI-to-PCI bridge layout.
 1620 **==============================================================================
 1621 */
 1622 #define     ARCMSR_PCI2PCI_HEADERTYPE_REG                0x0E    /*byte*/
 1623 /*
 1624 **==============================================================================
 1625 **     0x0f   : 
 1626 **==============================================================================
 1627 */
 1628 /*
 1629 **==============================================================================
 1630 **  0x13-0x10 : 
 1631 **  PCI CFG Base Address #0 (0x10) 
 1632 **==============================================================================
 1633 */
 1634 /*
 1635 **==============================================================================
 1636 **  0x17-0x14 : 
 1637 **  PCI CFG Base Address #1 (0x14) 
 1638 **==============================================================================
 1639 */
 1640 /*
 1641 **==============================================================================
 1642 **  0x1b-0x18 : 
 1643 **  PCI CFG Base Address #2 (0x18) 
 1644 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
 1645 ** Bit       Default                       Description
 1646 ** 23:16       00h             Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 
 1647 **                                                            Any Type 1 configuration cycle 
 1648 **                                                                      on the primary bus whose bus number is greater than the secondary bus number,
 1649 **                                                            and less than or equal to the subordinate bus number 
 1650 **                                                                      is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
 1651 ** 15:08       00h               Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 
 1652 **                                                            Any Type 1 configuration cycle matching this bus number 
 1653 **                                                                      is translated to a Type 0 configuration cycle (or a Special Cycle) 
 1654 **                                                                      before being executed on bridge's secondary PCI bus.
 1655 ** 07:00       00h                  Primary Bus Number (PBN): Indicates bridge primary bus number. 
 1656 **                                                            Any Type 1 configuration cycle on the primary interface 
 1657 **                                                                      with a bus number that is less than the contents 
 1658 **                                                                      of this register field does not be claimed by bridge.
 1659 **-----------------0x1B--Secondary Latency Timer Register - SLTR
 1660 ** Bit       Default                       Description
 1661 **                             Secondary Latency Timer (STV):
 1662 ** 07:00       00h (Conventional PCI)  Conventional PCI Mode: Secondary bus Master latency timer. 
 1663 **                                                            Indicates the number of PCI clock cycles,
 1664 **                                                                      referenced from the assertion of FRAME# to the expiration of the timer, 
 1665 **                                                            when bridge may continue as master of the current transaction. All bits are writable, 
 1666 **                                                            resulting in a granularity of 1 PCI clock cycle.
 1667 **                                                            When the timer expires (i.e., equals 00h) 
 1668 **                                                              bridge relinquishes the bus after the first data transfer 
 1669 **                                                              when its PCI bus grant has been deasserted.
 1670 **          or 40h (PCI-X)                        PCI-X Mode: Secondary bus Master latency timer. 
 1671 **                                                            Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 
 1672 **                                                              to the expiration of the timer, 
 1673 **                                                            when bridge may continue as master of the current transaction. All bits are writable, 
 1674 **                                                            resulting in a granularity of 1 PCI clock cycle.
 1675 **                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 
 1676 **                                                            (Except in the case where MLT expires within 3 data phases of an ADB. 
 1677 **                                                              In this case bridge continues on until it reaches the next ADB 
 1678 **                                                              before relinquishing the bus)
 1679 **==============================================================================
 1680 */
 1681 #define     ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG                 0x18    /*3byte 0x1A,0x19,0x18*/
 1682 #define     ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG               0x19    /*byte*/
 1683 #define     ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG             0x1A    /*byte*/
 1684 #define     ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG            0x1B    /*byte*/
 1685 /*
 1686 **==============================================================================
 1687 **  0x1f-0x1c : 
 1688 **  PCI CFG Base Address #3 (0x1C) 
 1689 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
 1690 ** Bit       Default                       Description
 1691 ** 15:12        0h            I/O Limit Address Bits [15:12]: Defines the top address of an address range to 
 1692 **                                                              determine when to forward I/O transactions from one interface to the other. 
 1693 **                                                            These bits correspond to address lines 15:12 for 4KB alignment. 
 1694 **                                                            Bits 11:0 are assumed to be FFFh.
 1695 ** 11:08        1h           I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
 1696 ** 07:04        0h             I/O Base Address Bits [15:12]: Defines the bottom address of 
 1697 **                                                              an address range to determine when to forward I/O transactions 
 1698 **                                                              from one interface to the other. 
 1699 **                                                            These bits correspond to address lines 15:12 for 4KB alignment. 
 1700 **                                                              Bits 11:0 are assumed to be 000h.
 1701 ** 03:00        1h            I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
 1702 **-----------------0x1F,0x1E--Secondary Status Register - SSR
 1703 ** Bit       Default                       Description
 1704 ** 15           0b                     Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 
 1705 **                                                              attribute or data parity error on its secondary interface.
 1706 ** 14           0b                     Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
 1707 ** 13           0b                     Received Master Abort: The bridge sets this bit to a 1b when, 
 1708 **                                                              acting as the initiator on the secondary bus, 
 1709 **                                                              it's transaction (with the exception of special cycles) 
 1710 **                                                              has been terminated with a Master Abort.
 1711 ** 12           0b                     Received Target Abort: The bridge sets this bit to a 1b when, 
 1712 **                                                              acting as the initiator on the secondary bus, 
 1713 **                                                              it's transaction has been terminated with a Target Abort.
 1714 ** 11           0b                     Signaled Target Abort: The bridge sets this bit to a 1b when it, 
 1715 **                                                              as the target of a transaction, terminates it with a Target Abort. 
 1716 **                                                            In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
 1717 ** 10:09       01b                            DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 
 1718 **                                                            Returns ˇ§01bˇ¨ when read, indicating that bridge responds no slower than with medium timing.
 1719 ** 08           0b                  Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
 1720 **                                                            The bridge is the current master on the secondary bus
 1721 **                                                            S_PERR# is detected asserted or is asserted by bridge
 1722 **                                                            The Parity Error Response bit is set in the Command register 
 1723 ** 07           1b           Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
 1724 ** 06           0b                           Reserved
 1725 ** 05           1b                      66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
 1726 **                                                            1 =
 1727 ** 04:00       00h                           Reserved
 1728 **==============================================================================
 1729 */
 1730 #define     ARCMSR_PCI2PCI_IO_BASE_REG                       0x1C    /*byte*/
 1731 #define     ARCMSR_PCI2PCI_IO_LIMIT_REG                      0x1D    /*byte*/
 1732 #define     ARCMSR_PCI2PCI_SECONDARY_STATUS_REG              0x1E    /*word: 0x1F,0x1E */
 1733 /*
 1734 **==============================================================================
 1735 **  0x23-0x20 : 
 1736 **  PCI CFG Base Address #4 (0x20)
 1737 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
 1738 ** Bit       Default                       Description
 1739 ** 31:20      000h                              Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
 1740 **                                                            the upper 1MB aligned value (exclusive) of the range. 
 1741 **                                                            The incoming address must be less than or equal to this value. 
 1742 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 
 1743 **                                                                      are assumed to be F FFFFh.
 1744 ** 19:16        0h                            Reserved.
 1745 ** 15:04      000h                               Memory Base: These 12 bits are compared with bits P_AD[31:20] 
 1746 **                                                              of the incoming address to determine the lower 1MB 
 1747 **                                                              aligned value (inclusive) of the range. 
 1748 **                                                            The incoming address must be greater than or equal to this value.
 1749 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 
 1750 **                                                              are assumed to be 0 0000h.
 1751 ** 03:00        0h                            Reserved.
 1752 **==============================================================================
 1753 */
 1754 #define     ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG   0x20    /*word: 0x21,0x20 */
 1755 #define     ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG  0x22    /*word: 0x23,0x22 */
 1756 /*
 1757 **==============================================================================
 1758 **  0x27-0x24 : 
 1759 **  PCI CFG Base Address #5 (0x24) 
 1760 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
 1761 ** Bit       Default                       Description
 1762 ** 31:20      000h                 Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
 1763 **                                                            the upper 1MB aligned value (exclusive) of the range. 
 1764 **                                                            The incoming address must be less than or equal to this value. 
 1765 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 
 1766 **                                                                      are assumed to be F FFFFh.
 1767 ** 19:16        1h                          64-bit Indicator: Indicates that 64-bit addressing is supported.
 1768 ** 15:04      000h                  Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 
 1769 **                                                              of the incoming address to determine the lower 1MB aligned value (inclusive) 
 1770 **                                                              of the range. 
 1771 **                                                            The incoming address must be greater than or equal to this value. 
 1772 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
 1773 **                                                               are assumed to be 0 0000h.
 1774 ** 03:00        1h                          64-bit Indicator: Indicates that 64-bit addressing is supported.
 1775 **==============================================================================
 1776 */
 1777 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG      0x24    /*word: 0x25,0x24 */
 1778 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG     0x26    /*word: 0x27,0x26 */
 1779 /*
 1780 **==============================================================================
 1781 **  0x2b-0x28 : 
 1782 ** Bit       Default                       Description
 1783 ** 31:00    00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable  
 1784 **                                                            bridge supports full 64-bit addressing.
 1785 **==============================================================================
 1786 */
 1787 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG     0x28    /*dword: 0x2b,0x2a,0x29,0x28 */
 1788 /*
 1789 **==============================================================================
 1790 **  0x2f-0x2c : 
 1791 ** Bit       Default                       Description
 1792 ** 31:00    00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 
 1793 **                                                             bridge supports full 64-bit addressing.
 1794 **==============================================================================
 1795 */
 1796 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG    0x2C    /*dword: 0x2f,0x2e,0x2d,0x2c */
 1797 /*
 1798 **==============================================================================
 1799 **  0x33-0x30 : 
 1800 ** Bit       Default                       Description
 1801 ** 07:00       DCh                      Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
 1802 **                                                            space. (Power Management Capability Registers)
 1803 **==============================================================================
 1804 */
 1805 #define     ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG                      0x34    /*byte*/ 
 1806 /*
 1807 **==============================================================================
 1808 **  0x3b-0x35 : reserved
 1809 **==============================================================================
 1810 */
 1811 /*
 1812 **==============================================================================
 1813 **  0x3d-0x3c : 
 1814 **
 1815 ** Bit       Default                       Description
 1816 ** 15:08       00h                       Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
 1817 ** 07:00       00h                     Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
 1818 **==============================================================================
 1819 */
 1820 #define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG                0x3C    /*byte*/ 
 1821 #define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG                 0x3D    /*byte*/ 
 1822 /*
 1823 **==============================================================================
 1824 **  0x3f-0x3e : 
 1825 ** Bit       Default                       Description
 1826 ** 15:12        0h                          Reserved
 1827 ** 11           0b                Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
 1828 **                                                            to a timer discard on either the primary or secondary interface.
 1829 **                                                            0b=SERR# is not asserted.
 1830 **                                                            1b=SERR# is asserted.
 1831 ** 10           0b                Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
 1832 **                                                            The delayed completion is then discarded.
 1833 ** 09           0b             Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 
 1834 **                                                                      that bridge waits for an initiator on the secondary bus 
 1835 **                                                                      to repeat a delayed transaction request. 
 1836 **                                                            The counter starts when the delayed transaction completion is ready 
 1837 **                                                                      to be returned to the initiator. 
 1838 **                                                            When the initiator has not repeated the transaction 
 1839 **                                                                      at least once before the counter expires,bridge 
 1840 **                                                                              discards the delayed transaction from its queues.
 1841 **                                                            0b=The secondary master time-out counter is 2 15 PCI clock cycles.
 1842 **                                                            1b=The secondary master time-out counter is 2 10 PCI clock cycles.
 1843 ** 08           0b               Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 
 1844 **                                                                      that bridge waits for an initiator on the primary bus 
 1845 **                                                                      to repeat a delayed transaction request. 
 1846 **                                                            The counter starts when the delayed transaction completion 
 1847 **                                                                      is ready to be returned to the initiator. 
 1848 **                                                            When the initiator has not repeated the transaction 
 1849 **                                                                      at least once before the counter expires, 
 1850 **                                                                      bridge discards the delayed transaction from its queues.
 1851 **                                                            0b=The primary master time-out counter is 2 15 PCI clock cycles.
 1852 **                                                            1b=The primary master time-out counter is 2 10 PCI clock cycles.
 1853 ** 07           0b            Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
 1854 ** 06           0b                 Secondary Bus Reset (SBR): 
 1855 **                                                            When cleared to 0b: The bridge deasserts S_RST#, 
 1856 **                                                                      when it had been asserted by writing this bit to a 1b.
 1857 **                                                                When set to 1b: The bridge asserts S_RST#.
 1858 ** 05           0b                   Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 
 1859 **                                                                      when a master abort termination occurs in response to 
 1860 **                                                                              a delayed transaction initiated by bridge on the target bus.
 1861 **                                                            0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,
 1862 **                                                                              and returns FFFF FFFFh when a read.
 1863 **                                                            1b=When the transaction had not yet been completed on the initiator bus 
 1864 **                                                                              (e.g.,delayed reads, or non-posted writes), 
 1865 **                                                                 then bridge returns a Target Abort in response to the original requester 
 1866 **                                                                 when it returns looking for its delayed completion on the initiator bus. 
 1867 **                                                                 When the transaction had completed on the initiator bus (e.g., a PMW), 
 1868 **                                                                              then bridge asserts P_SERR# (when enabled).
 1869 **                                   For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 
 1870 **                                                              while attempting to deliver a posted memory write on the destination bus.
 1871 ** 04           0b                   VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 
 1872 **                                                              (also of this register), 
 1873 **                                                            and the VGA Palette Snoop Enable bit (Command Register). 
 1874 **                                                            When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 
 1875 **                                                                      the VGA Aliasing bit for the corresponding enabled functionality,:
 1876 **                                                            0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
 1877 **                                                            1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
 1878 **                                   When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 
 1879 **                                                                      then this bit has no impact on bridge behavior.
 1880 ** 03           0b                                VGA Enable: Setting this bit enables address decoding
 1881 **                                                               and transaction forwarding of the following VGA transactions from the primary bus 
 1882 **                                                                      to the secondary bus:
 1883 **                                                            frame buffer memory addresses 000A0000h:000BFFFFh, 
 1884 **                                                                      VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=ˇ§0000h?**                                                                    ?and AD[15:10] are either not decoded (i.e., don't cares),
 1885 **                                                                               or must be ˇ§000000bˇ¨
 1886 **                                                            depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
 1887 **                                                            I/O and Memory Enable bits must be set in the Command register 
 1888 **                                                                              to enable forwarding of VGA cycles.
 1889 ** 02           0b                                ISA Enable: Setting this bit enables special handling 
 1890 **                                                              for the forwarding of ISA I/O transactions that fall within the address range 
 1891 **                                                                      specified by the I/O Base and Limit registers, 
 1892 **                                                                              and are within the lowest 64Kbyte of the I/O address map 
 1893 **                                                                                      (i.e., 0000 0000h - 0000 FFFFh).
 1894 **                                                            0b=All I/O transactions that fall within the I/O Base 
 1895 **                                                                              and Limit registers' specified range are forwarded 
 1896 **                                                                                      from primary to secondary unfiltered.
 1897 **                                                            1b=Blocks the forwarding from primary to secondary 
 1898 **                                                                                      of the top 768 bytes of each 1Kbyte alias. 
 1899 **                                                                                              On the secondary the top 768 bytes of each 1K alias 
 1900 **                                                                                                      are inversely decoded and forwarded 
 1901 **                                                                                                              from secondary to primary.
 1902 ** 01           0b                      SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
 1903 **                                                            1b=The bridge asserts P_SERR# whenever S_SERR# is detected 
 1904 **                                                                      asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
 1905 ** 00           0b                     Parity Error Response: This bit controls bridge response to a parity error 
 1906 **                                                                              that is detected on its secondary interface.
 1907 **                                                            0b=When a data parity error is detected bridge does not assert S_PERR#. 
 1908 **                                                            Also bridge does not assert P_SERR# in response to a detected address 
 1909 **                                                                              or attribute parity error.
 1910 **                                                            1b=When a data parity error is detected bridge asserts S_PERR#. 
 1911 **                                                                              The bridge also asserts P_SERR# (when enabled globally via bit(8) 
 1912 **                                                                                      of the Command register)
 1913 **                                                            in response to a detected address or attribute parity error.
 1914 **==============================================================================
 1915 */
 1916 #define     ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG                        0x3E    /*word*/ 
 1917 /*
 1918 **************************************************************************
 1919 **                  Device Specific Registers 40-A7h
 1920 **************************************************************************
 1921 ** ----------------------------------------------------------------------------------------------------------
 1922 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              | Configu-ration Byte Offset
 1923 ** ----------------------------------------------------------------------------------------------------------
 1924 ** |    Bridge Control 0    |             Arbiter Control/Status              |      Reserved             | 40h
 1925 ** ----------------------------------------------------------------------------------------------------------
 1926 ** |                 Bridge Control 2                |                 Bridge Control 1                   | 44h
 1927 ** ----------------------------------------------------------------------------------------------------------
 1928 ** |                    Reserved                     |                 Bridge Status                      | 48h
 1929 ** ----------------------------------------------------------------------------------------------------------
 1930 ** |                                             Reserved                                                 | 4Ch
 1931 ** ----------------------------------------------------------------------------------------------------------
 1932 ** |                 Prefetch Policy                 |               Multi-Transaction Timer              | 50h
 1933 ** ----------------------------------------------------------------------------------------------------------
 1934 ** |       Reserved         |      Pre-boot Status   |             P_SERR# Assertion Control              | 54h
 1935 ** ----------------------------------------------------------------------------------------------------------
 1936 ** |       Reserved         |        Reserved        |             Secondary Decode Enable                | 58h
 1937 ** ----------------------------------------------------------------------------------------------------------
 1938 ** |                    Reserved                     |                 Secondary IDSEL                    | 5Ch
 1939 ** ----------------------------------------------------------------------------------------------------------
 1940 ** |                                              Reserved                                                | 5Ch
 1941 ** ----------------------------------------------------------------------------------------------------------
 1942 ** |                                              Reserved                                                | 68h:CBh
 1943 ** ----------------------------------------------------------------------------------------------------------
 1944 **************************************************************************
 1945 **==============================================================================
 1946 **  0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
 1947 ** Bit       Default                       Description
 1948 ** 15:12      1111b                  Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 
 1949 **                                                      (PCI=16 clocks,PCI-X=6 clocks). 
 1950 **                                   Note that this field is only meaningful when:
 1951 **                                                              # Bit[11] of this register is set to 1b, 
 1952 **                                                                      indicating that a Grant Time-out violation had occurred. 
 1953 **                                                              # bridge internal arbiter is enabled.
 1954 **                                           Bits[15:12] Violating Agent (REQ#/GNT# pair number)
 1955 **                                                 0000b REQ#/GNT#[0]
 1956 **                                                 0001b REQ#/GNT#[1]
 1957 **                                                 0010b REQ#/GNT#[2]
 1958 **                                                 0011b REQ#/GNT#[3]
 1959 **                                                 1111b Default Value (no violation detected)
 1960 **                                   When bit[11] is cleared by software, this field reverts back to its default value.
 1961 **                                   All other values are Reserved
 1962 ** 11            0b                  Grant Time-out Occurred: When set to 1b, 
 1963 **                                   this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
 1964 **                                   Software clears this bit by writing a 1b to it.
 1965 ** 10            0b                      Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
 1966 **                                                            1=During bus idle, bridge parks the bus on itself. 
 1967 **                                                                      The bus grant is removed from the last master and internally asserted to bridge.
 1968 ** 09:08        00b                          Reserved
 1969 ** 07:00      0000 0000b  Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 
 1970 **                                                                      Each bit of this field assigns its corresponding secondary 
 1971 **                                                                              bus master to either the high priority arbiter ring (1b) 
 1972 **                                                                                      or to the low priority arbiter ring (0b). 
 1973 **                                                                      Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 
 1974 **                                                                      Bit [6] corresponds to the bridge internal secondary bus request 
 1975 **                                                                              while Bit [7] corresponds to the SATU secondary bus request. 
 1976 **                                                                      Bits [5:4] are unused.
 1977 **                                                                      0b=Indicates that the master belongs to the low priority group.
 1978 **                                                                      1b=Indicates that the master belongs to the high priority group
 1979 **=================================================================================
 1980 **  0x43: Bridge Control Register 0 - BCR0
 1981 ** Bit       Default                       Description
 1982 ** 07           0b                  Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 
 1983 **                                                                      and the Posted Write data is limited to 4KB.
 1984 **                                                            1=Operation in fully dynamic queue mode. The bridge enqueues up to 
 1985 **                                                                      14 Posted Memory Write transactions and 8KB of posted write data.
 1986 ** 06:03        0H                          Reserved.
 1987 ** 02           0b                 Upstream Prefetch Disable: This bit disables bridge ability 
 1988 **                                                                      to perform upstream prefetch operations for Memory 
 1989 **                                                                              Read requests received on its secondary interface. 
 1990 **                                 This bit also controls the bridge's ability to generate advanced read commands 
 1991 **                                                              when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 
 1992 **                                                                              to a Conventional PCI bus.
 1993 **                                 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory.
 1994 **                                                                              The use of Memory Read Line and Memory Read
 1995 **                                      Multiple is enabled when forwarding a PCI-X Memory Read Block request 
 1996 **                                                                              to an upstream bus operating in Conventional PCI mode.
 1997 **                                 1b=bridge treats upstream PCI Memory Read requests as though 
 1998 **                                                                      they target non-prefetchable memory and forwards upstream PCI-X Memory 
 1999 **                                                                                      Read Block commands as Memory Read 
 2000 **                                                                                              when the primary bus is operating 
 2001 **                                                                                                      in Conventional PCI mode.
 2002 **                                 NOTE: This bit does not affect bridge ability to perform read prefetching 
 2003 **                                                                      when the received command is Memory Read Line or Memory Read Multiple.
 2004 **=================================================================================
 2005 **  0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
 2006 ** Bit       Default                       Description
 2007 ** 15:08    0000000b                         Reserved
 2008 ** 07:06         00b                   Alias Command Mapping: This two bit field determines how bridge handles PCI-X ˇ§Aliasˇ¨ commands, 
 2009 **                                                              specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 
 2010 **                                                            The three options for handling these alias commands are to either pass it as is, 
 2011 **                                                                      re-map to the actual block memory read/write command encoding, or ignore
 2012 **                                                                              the transaction forcing a Master Abort to occur on the Origination Bus.
 2013 **                                                   Bit (7:6) Handling of command
 2014 **                                                        0 0 Re-map to Memory Read/Write Block before forwarding
 2015 **                                                        0 1 Enqueue and forward the alias command code unaltered
 2016 **                                                        1 0 Ignore the transaction, forcing Master Abort
 2017 **                                                        1 1 Reserved
 2018 ** 05            1b                  Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 
 2019 **                                                            The watchdog timers are used to detect prohibitively long latencies in the system. 
 2020 **                                                            The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 
 2021 **                                                            or Split Requests (PCI-X mode) is not completed within 2 24 events 
 2022 **                                                            (ˇ§eventsˇ¨ are defined as PCI Clocks when operating in PCI-X mode, 
 2023 **                                                              and as the number of times being retried when operating in Conventional PCI mode)
 2024 **                                                            0b=All 2 24 watchdog timers are enabled.
 2025 **                                                            1b=All 2 24 watchdog timers are disabled and there is no limits to 
 2026 **                                                                      the number of attempts bridge makes when initiating a PMW, 
 2027 **                                                                 transacting a Delayed Transaction, or how long it waits for 
 2028 **                                                                      a split completion corresponding to one of its requests.
 2029 ** 04            0b                  GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 
 2030 **                                                            Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
 2031 **                                                            0b=The Secondary bus arbiter times out an agent 
 2032 **                                                                      that does not assert FRAME# within 16/6 clocks of receiving its grant, 
 2033 **                                                                              once the bus has gone idle. 
 2034 **                                                                 The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 
 2035 **                                                                 An infringing agent does not receive a subsequent GNT# 
 2036 **                                                                      until it de-asserts its REQ# for at least one clock cycle.
 2037 **                                                            1b=GNT# time-out mechanism is disabled.
 2038 ** 03           00b                           Reserved.
 2039 ** 02            0b          Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
 2040 **                                                            The time out mechanism is used to ensure that initiators 
 2041 **                                                                      of delayed transactions return for their delayed completion data/status 
 2042 **                                                                              within a reasonable amount of time after it is available from bridge.
 2043 **                                                            0b=The secondary master time-out counter is enabled 
 2044 **                                                                              and uses the value specified by the Secondary Discard Timer bit 
 2045 **                                                                                      (see Bridge Control Register).
 2046 **                                                            1b=The secondary master time-out counter is disabled. 
 2047 **                                                                                      The bridge waits indefinitely for a secondary bus master 
 2048 **                                                                                              to repeat a delayed transaction.
 2049 ** 01            0b            Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 
 2050 **                                                              The time out mechanism is used to ensure that initiators 
 2051 **                                                                      of delayed transactions return for their delayed completion data/status 
 2052 **                                                                              within a reasonable amount of time after it is available from bridge.
 2053 **                                                            0b=The primary master time-out counter is enabled and uses the value specified 
 2054 **                                                                      by the Primary Discard Timer bit (see Bridge Control Register).
 2055 **                                                            1b=The secondary master time-out counter is disabled. 
 2056 **                                                                      The bridge waits indefinitely for a secondary bus master 
 2057 **                                                                              to repeat a delayed transaction.
 2058 ** 00            0b                           Reserved
 2059 **=================================================================================
 2060 **  0x47-0x46: Bridge Control Register 2 - BCR2
 2061 ** Bit       Default                       Description
 2062 ** 15:07      0000b                          Reserved.
 2063 ** 06            0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 
 2064 **                                                                      This bit disables all of the secondary PCI clock outputs including 
 2065 **                                                                              the feedback clock S_CLKOUT. 
 2066 **                                                            This means that the user is required to provide an S_CLKIN input source.
 2067 ** 05:04        11 (66 MHz)                  Preserved.
 2068 **              01 (100 MHz)
 2069 **              00 (133 MHz)
 2070 ** 03:00        Fh (100 MHz & 66 MHz)
 2071 **              7h (133 MHz)
 2072 **                                        This 4 bit field provides individual enable/disable mask bits for each of bridge
 2073 **                                        secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
 2074 **                                        default to being enabled following the rising edge of P_RST#, depending on the
 2075 **                                        frequency of the secondary bus clock:
 2076 **                                               ˇE Designs with 100 MHz (or lower) Secondary PCI clock power up with 
 2077 **                                                              all four S_CLKOs enabled by default. (SCLKO[3:0])ˇP
 2078 **                                               ˇE Designs with 133 MHz Secondary PCI clock power up 
 2079 **                                                              with the lower order 3 S_CLKOs enabled by default. 
 2080 **                                                              (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 
 2081 **                                                              to downstream device clock inputs.
 2082 **=================================================================================
 2083 **  0x49-0x48: Bridge Status Register - BSR
 2084 ** Bit       Default                       Description
 2085 ** 15           0b  Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 
 2086 **                                                                      is conditionally asserted when the secondary discard timer expires.
 2087 ** 14           0b  Upstream Delayed/Split Read Watchdog Timer Expired: 
 2088 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR#
 2089 **                                                                      is conditionally asserted when bridge discards an upstream delayed read **      **                                                                      transaction request after 2 24 retries following the initial retry.
 2090 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 
 2091 **                                                                      when bridge discards an upstream split read request 
 2092 **                                                                      after waiting in excess of 2 24 clocks for the corresponding 
 2093 **                                                                      Split Completion to arrive.
 2094 ** 13           0b Upstream Delayed/Split Write Watchdog Timer Expired: 
 2095 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# 
 2096 **                                                                      is conditionally asserted when bridge discards an upstream delayed write **     **                                                                      transaction request after 2 24 retries following the initial retry.
 2097 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# 
 2098 **                                                                      is conditionally asserted when bridge discards an upstream split write request **                                                                       after waiting in excess of 2 24 clocks for the corresponding 
 2099 **                                                                      Split Completion to arrive.
 2100 ** 12           0b           Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 
 2101 **                                                                      is conditionally asserted when a Master Abort occurs as a result of an attempt, 
 2102 **                                                                      by bridge, to retire a PMW upstream.
 2103 ** 11           0b           Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 
 2104 **                                                                      is conditionally asserted when a Target Abort occurs as a result of an attempt,
 2105 **                                                                      by bridge, to retire a PMW upstream.
 2106 ** 10           0b                Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 
 2107 **                                                                      is conditionally asserted when bridge discards an upstream PMW transaction 
 2108 **                                                                      after receiving 2 24 target retries from the primary bus target
 2109 ** 09           0b             Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 
 2110 **                                                                      is conditionally asserted when a data parity error is detected by bridge 
 2111 **                                                                      while attempting to retire a PMW upstream
 2112 ** 08           0b                  Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 
 2113 **                                                                      is conditionally asserted when bridge detects an address parity error on 
 2114 **                                                                      the secondary bus.
 2115 ** 07           0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 
 2116 **                                                                      is conditionally asserted when the primary bus discard timer expires.
 2117 ** 06           0b Downstream Delayed/Split Read Watchdog Timer Expired:
 2118 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# 
 2119 **                                                                      is conditionally asserted when bridge discards a downstream delayed read **     **                                                                              transaction request after receiving 2 24 target retries
 2120 **                                                                                       from the secondary bus target.
 2121 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 
 2122 **                                                                              when bridge discards a downstream split read request 
 2123 **                                                                                      after waiting in excess of 2 24 clocks for the corresponding 
 2124 **                                                                                              Split Completion to arrive.
 2125 ** 05           0b Downstream Delayed Write/Split Watchdog Timer Expired:
 2126 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 
 2127 **                                                                      when bridge discards a downstream delayed write transaction request 
 2128 **                                                                              after receiving 2 24 target retries from the secondary bus target.
 2129 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# 
 2130 **                                                                      is conditionally asserted when bridge discards a downstream 
 2131 **                                                                              split write request after waiting in excess of 2 24 clocks 
 2132 **                                                                                      for the corresponding Split Completion to arrive.
 2133 ** 04           0b          Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 
 2134 **                                                                      is conditionally asserted when a Master Abort occurs as a result of an attempt, 
 2135 **                                                                              by bridge, to retire a PMW downstream.
 2136 ** 03           0b          Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 
 2137 **                                                                              when a Target Abort occurs as a result of an attempt, by bridge, 
 2138 **                                                                                      to retire a PMW downstream.
 2139 ** 02           0b               Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
 2140 **                                                                      is conditionally asserted when bridge discards a downstream PMW transaction 
 2141 **                                                                              after receiving 2 24 target retries from the secondary bus target
 2142 ** 01           0b            Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 
 2143 **                                                                      is conditionally asserted when a data parity error is detected by bridge 
 2144 **                                                                              while attempting to retire a PMW downstream.
 2145 ** 00           0b                     Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 
 2146 **                                                                              when bridge detects an address parity error on the primary bus.
 2147 **==================================================================================
 2148 **  0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
 2149 ** Bit       Default                       Description
 2150 ** 15:13       000b                          Reserved
 2151 ** 12:10       000b                          GRANT# Duration: This field specifies the count (PCI clocks) 
 2152 **                                                      that a secondary bus master has its grant maintained in order to enable 
 2153 **                                                              multiple transactions to execute within the same arbitration cycle.
 2154 **                                                    Bit[02:00] GNT# Extended Duration
 2155 **                                                               000 MTT Disabled (Default=no GNT# extension)
 2156 **                                                               001 16 clocks
 2157 **                                                               010 32 clocks
 2158 **                                                               011 64 clocks
 2159 **                                                               100 128 clocks
 2160 **                                                               101 256 clocks
 2161 **                                                               110 Invalid (treated as 000)
 2162 **                                                               111 Invalid (treated as 000)
 2163 ** 09:08        00b                          Reserved
 2164 ** 07:00        FFh                                 MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 
 2165 **                                                              pair supported by bridge secondary arbiter. 
 2166 **                                                            Bit(7) corresponds to SATU internal REQ#/GNT# pair,
 2167 **                                                            bit(6) corresponds to bridge internal REQ#/GNT# pair, 
 2168 **                                                            bit(5) corresponds to REQ#/GNT#(5) pair, etc.
 2169 **                                                  When a given bit is set to 1b, its corresponding REQ#/GNT# 
 2170 **                                                              pair is enabled for MTT functionality as determined by bits(12:10) of this register.
 2171 **                                                  When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
 2172 **==================================================================================
 2173 **  0x53-0x52: Read Prefetch Policy Register - RPPR
 2174 ** Bit       Default                       Description
 2175 ** 15:13       000b                    ReRead_Primary Bus: 3-bit field indicating the multiplication factor 
 2176 **                                                      to be used in calculating the number of bytes to prefetch from the secondary bus interface on **                                                                subsequent PreFetch operations given that the read demands were not satisfied 
 2177 **                                                                      using the FirstRead parameter.
 2178 **                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 
 2179 **                                                      Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
 2180 ** 12:10       000b                 FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 
 2181 **                                                      the number of bytes to prefetch from the secondary bus interface 
 2182 **                                                              on the initial PreFetch operation.
 2183 **                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 
 2184 **                                                              Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
 2185 ** 09:07       010b                  ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 
 2186 **                                                              in calculating the number of bytes to prefetch from the primary 
 2187 **                                                                      bus interface on subsequent PreFetch operations given 
 2188 **                                                                              that the read demands were not satisfied using 
 2189 **                                                                                      the FirstRead parameter.
 2190 **                                           The default value of 010b correlates to: Command Type Hardwired pre-fetch a
 2191 **                                                      mount Memory Read 3 cache lines Memory Read Line 3 cache lines 
 2192 **                                                              Memory Read Multiple 6 cache lines
 2193 ** 06:04       000b               FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 
 2194 **                                                      in calculating the number of bytes to prefetch from 
 2195 **                                                              the primary bus interface on the initial PreFetch operation.
 2196 **                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 
 2197 **                                                      Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
 2198 ** 03:00      1111b                Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 
 2199 **                                                      algorithm for the secondary and the primary bus interfaces.
 2200 **                                                         Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
 2201 **                                                                            enable bits for REQ#/GNT#[2:0]. 
 2202 **                                                        (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
 2203 **                                                                            1b: enables the staged pre-fetch feature
 2204 **                                                                            0b: disables staged pre-fetch,
 2205 **                                                         and hardwires read pre-fetch policy to the following for 
 2206 **                                                         Memory Read, 
 2207 **                                                         Memory Read Line, 
 2208 **                                                     and Memory Read Multiple commands: 
 2209 **                                                     Command Type Hardwired Pre-Fetch Amount...
 2210 **                                                                                      Memory Read 4 DWORDs
 2211 **                                                                                      Memory Read Line 1 cache line
 2212 **                                                                                      Memory Read Multiple 2 cache lines
 2213 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 
 2214 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 
 2215 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
 2216 **==================================================================================
 2217 **  0x55-0x54: P_SERR# Assertion Control - SERR_CTL
 2218 ** Bit       Default                       Description
 2219 **  15          0b   Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 
 2220 **                                              in response to its discarding of a delayed transaction that was initiated from the primary bus.
 2221 **                                                                       0b=bridge asserts P_SERR#.
 2222 **                                                                       1b=bridge does not assert P_SERR#
 2223 **  14          0b   Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 2224 **                                                                       0b=bridge asserts P_SERR#.
 2225 **                                                                       1b=bridge does not assert P_SERR#
 2226 **  13          0b   Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 2227 **                                                                       0b=bridge asserts P_SERR#.
 2228 **                                                                       1b=bridge does not assert P_SERR#
 2229 **  12          0b             Master Abort during Upstream Posted Write: Dictates bridge behavior following 
 2230 **                                              its having detected a Master Abort while attempting to retire one of its PMWs upstream.
 2231 **                                                                       0b=bridge asserts P_SERR#.
 2232 **                                                                       1b=bridge does not assert P_SERR#
 2233 **  11          0b             Target Abort during Upstream Posted Write: Dictates bridge behavior following 
 2234 **                                              its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
 2235 **                                                                       0b=bridge asserts P_SERR#.
 2236 **                                                                       1b=bridge does not assert P_SERR#
 2237 **  10          0b                  Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 
 2238 **                                              it discards an upstream posted write transaction.
 2239 **                                                                       0b=bridge asserts P_SERR#.
 2240 **                                                                       1b=bridge does not assert P_SERR#
 2241 **  09          0b               Upstream Posted Write Data Parity Error: Dictates bridge behavior 
 2242 **                                              when a data parity error is detected while attempting to retire on of its PMWs upstream.
 2243 **                                                                       0b=bridge asserts P_SERR#.
 2244 **                                                                       1b=bridge does not assert P_SERR#
 2245 **  08          0b                    Secondary Bus Address Parity Error: This bit dictates bridge behavior 
 2246 **                                              when it detects an address parity error on the secondary bus.
 2247 **                                                                       0b=bridge asserts P_SERR#.
 2248 **                                                                       1b=bridge does not assert P_SERR#
 2249 **  07          0b  Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 
 2250 **                                              its discarding of a delayed transaction that was initiated on the secondary bus.
 2251 **                                                                       0b=bridge asserts P_SERR#.
 2252 **                                                                       1b=bridge does not assert P_SERR#
 2253 **  06          0b  Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 2254 **                                                                       0b=bridge asserts P_SERR#.
 2255 **                                                                       1b=bridge does not assert P_SERR#
 2256 **  05          0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 2257 **                                                                       0b=bridge asserts P_SERR#.
 2258 **                                                                       1b=bridge does not assert P_SERR#
 2259 **  04          0b           Master Abort during Downstream Posted Write: Dictates bridge behavior following 
 2260 **                                              its having detected a Master Abort while attempting to retire one of its PMWs downstream.
 2261 **                                                                       0b=bridge asserts P_SERR#.
 2262 **                                                                       1b=bridge does not assert P_SERR#
 2263 **  03          0b           Target Abort during Downstream Posted Write: Dictates bridge behavior following 
 2264 **                                              its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
 2265 **                                                                       0b=bridge asserts P_SERR#.
 2266 **                                                                       1b=bridge does not assert P_SERR#
 2267 **  02          0b                Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 
 2268 **                                              that it discards a downstream posted write transaction.
 2269 **                                                                       0b=bridge asserts P_SERR#.
 2270 **                                                                       1b=bridge does not assert P_SERR#
 2271 **  01          0b             Downstream Posted Write Data Parity Error: Dictates bridge behavior 
 2272 **                                              when a data parity error is detected while attempting to retire on of its PMWs downstream.
 2273 **                                                                       0b=bridge asserts P_SERR#.
 2274 **                                                                       1b=bridge does not assert P_SERR#
 2275 **  00          0b                      Primary Bus Address Parity Error: This bit dictates bridge behavior 
 2276 **                                              when it detects an address parity error on the primary bus.
 2277 **                                                                       0b=bridge asserts P_SERR#.
 2278 **                                                                       1b=bridge does not assert P_SERR#
 2279 **===============================================================================
 2280 **  0x56: Pre-Boot Status Register - PBSR
 2281 ** Bit       Default                                                                            Description
 2282 ** 07           1                                                                                Reserved
 2283 ** 06           -                                                                                Reserved - value indeterminate
 2284 ** 05:02        0                                                                                Reserved
 2285 ** 01      Varies with External State of S_133EN at PCI Bus Reset    Secondary Bus Max Frequency Setting:
 2286 **                                                                       This bit reflect captured S_133EN strap, 
 2287 **                                                                              indicating the maximum secondary bus clock frequency when in PCI-X mode.
 2288 **                                                                   Max Allowable Secondary Bus Frequency
 2289 **                                                                                                                                                      **                                              S_133EN PCI-X Mode
 2290 **                                                                                                                                                      **                                              0 100 MHz
 2291 **                                                                                                                                                      **                                              1 133 MH
 2292 ** 00          0b                                                    Reserved
 2293 **===============================================================================
 2294 **  0x59-0x58: Secondary Decode Enable Register - SDER
 2295 ** Bit       Default                                                                            Description
 2296 ** 15:03      FFF1h                                                                              Preserved.
 2297 ** 02     Varies with External State of PRIVMEM at PCI Bus Reset   Private Memory Space Enable - when set, 
 2298 **                                                                      bridge overrides its secondary inverse decode logic and not
 2299 **                                                                 forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
 2300 **                                                                 This creates a private memory space on the Secondary PCI bus 
 2301 **                                                                      that allows peer-to-peer transactions.
 2302 ** 01:00      10 2                                                   Preserved.
 2303 **===============================================================================
 2304 **  0x5D-0x5C: Secondary IDSEL Select Register - SISR
 2305 ** Bit       Default                                                                            Description
 2306 ** 15:10     000000 2                                                                            Reserved.
 2307 ** 09    Varies with External State of PRIVDEV at PCI Bus Reset     AD25- IDSEL Disable - When this bit is set, 
 2308 **                                                      AD25 is deasserted for any possible Type 1 to Type 0 conversion.
 2309 **                                                                                        When this bit is clear, 
 2310 **                                                      AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
 2311 ** 08    Varies with External State of PRIVDEV at PCI Bus Reset     AD24- IDSEL Disable - When this bit is set, 
 2312 **                                                      AD24 is deasserted for any possible Type 1 to Type 0 conversion.
 2313 **                                                                                        When this bit is clear, 
 2314 **                                                      AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
 2315 ** 07    Varies with External State of PRIVDEV at PCI Bus Reset     AD23- IDSEL Disable - When this bit is set, 
 2316 **                                                      AD23 is deasserted for any possible Type 1 to Type 0 conversion. 
 2317 **                                                                                        When this bit is clear, 
 2318 **                                                      AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
 2319 ** 06    Varies with External State of PRIVDEV at PCI Bus Reset     AD22- IDSEL Disable - When this bit is set, 
 2320 **                                                      AD22 is deasserted for any possible Type 1 to Type 0 conversion.
 2321 **                                                                                        When this bit is clear, 
 2322 **                                                      AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
 2323 ** 05    Varies with External State of PRIVDEV at PCI Bus Reset     AD21- IDSEL Disable - When this bit is set, 
 2324 **                                                      AD21 is deasserted for any possible Type 1 to Type 0 conversion.
 2325 **                                                                                        When this bit is clear, 
 2326 **                                                      AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
 2327 ** 04    Varies with External State of PRIVDEV at PCI Bus Reset     AD20- IDSEL Disable - When this bit is set, 
 2328 **                                                      AD20 is deasserted for any possible Type 1 to Type 0 conversion.
 2329 **                                                                                        When this bit is clear, 
 2330 **                                                      AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
 2331 ** 03    Varies with External State of PRIVDEV at PCI Bus Reset     AD19- IDSEL Disable - When this bit is set, 
 2332 **                                                      AD19 is deasserted for any possible Type 1 to Type 0 conversion.
 2333 **                                                                                        When this bit is clear,
 2334 **                                                      AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
 2335 ** 02    Varies with External State of PRIVDEV at PCI Bus Reset     AD18- IDSEL Disable - When this bit is set, 
 2336 **                                                      AD18 is deasserted for any possible Type 1 to Type 0 conversion.
 2337 **                                                                                        When this bit is clear,
 2338 **                                                      AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
 2339 ** 01    Varies with External State of PRIVDEV at PCI Bus Reset     AD17- IDSEL Disable - When this bit is set, 
 2340 **                                                      AD17 is deasserted for any possible Type 1 to Type 0 conversion.
 2341 **                                                                                        When this bit is clear, 
 2342 **                                                      AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
 2343 ** 00    Varies with External State of PRIVDEV at PCI Bus Reset     AD16- IDSEL Disable - When this bit is set, 
 2344 **                                                      AD16 is deasserted for any possible Type 1 to Type 0 conversion.
 2345 **                                                                                        When this bit is clear, 
 2346 **                                                      AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
 2347 **************************************************************************
 2348 */
 2349 /*
 2350 **************************************************************************
 2351 **                 Reserved      A8-CBh           
 2352 **************************************************************************
 2353 */
 2354 /*
 2355 **************************************************************************
 2356 **                  PCI Extended Enhanced Capabilities List CC-FFh
 2357 **************************************************************************
 2358 ** ----------------------------------------------------------------------------------------------------------
 2359 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              | Configu-ration Byte Offset
 2360 ** ----------------------------------------------------------------------------------------------------------
 2361 ** |           Power Management Capabilities         |        Next Item Ptr   |     Capability ID         | DCh
 2362 ** ----------------------------------------------------------------------------------------------------------
 2363 ** |        PM Data         |       PPB Support      |            Extensions Power Management CSR         | E0h
 2364 ** ----------------------------------------------------------------------------------------------------------
 2365 ** |                    Reserved                     |        Reserved        |        Reserved           | E4h
 2366 ** ----------------------------------------------------------------------------------------------------------
 2367 ** |                                              Reserved                                                | E8h
 2368 ** ----------------------------------------------------------------------------------------------------------
 2369 ** |       Reserved         |        Reserved        |        Reserved        |         Reserved          | ECh
 2370 ** ----------------------------------------------------------------------------------------------------------
 2371 ** |              PCI-X Secondary Status             |       Next Item Ptr    |       Capability ID       | F0h
 2372 ** ----------------------------------------------------------------------------------------------------------
 2373 ** |                                         PCI-X Bridge Status                                          | F4h
 2374 ** ----------------------------------------------------------------------------------------------------------
 2375 ** |                                PCI-X Upstream Split Transaction Control                              | F8h
 2376 ** ----------------------------------------------------------------------------------------------------------
 2377 ** |                               PCI-X Downstream Split Transaction Control                             | FCh
 2378 ** ----------------------------------------------------------------------------------------------------------
 2379 **===============================================================================
 2380 **  0xDC: Power Management Capabilities Identifier - PM_CAPID
 2381 ** Bit       Default                       Description
 2382 ** 07:00       01h                        Identifier (ID): PCI SIG assigned ID for PCI-PM register block
 2383 **===============================================================================
 2384 **  0xDD: Next Item Pointer - PM_NXTP
 2385 ** Bit       Default                       Description
 2386 ** 07:00       F0H                Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header.
 2387 **===============================================================================
 2388 **  0xDF-0xDE: Power Management Capabilities Register - PMCR
 2389 ** Bit       Default                       Description
 2390 ** 15:11       00h                     PME Supported (PME): PME# cannot be asserted by bridge.
 2391 ** 10           0h                 State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
 2392 ** 09           1h                 State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
 2393 ** 08:06        0h                Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 
 2394 **                                                          This returns 000b as PME# wake-up for bridge is not implemented.
 2395 ** 05           0   Special Initialization Required (SINT): Special initialization is not required for bridge.
 2396 ** 04:03       00                            Reserved
 2397 ** 02:00       010                            Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1.
 2398 **===============================================================================
 2399 **  0xE1-0xE0: Power Management Control / Status - Register - PMCSR
 2400 ** Bit       Default                       Description
 2401 ** 15:09       00h                          Reserved
 2402 ** 08          0b                          PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 
 2403 **      Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
 2404 ** 07:02       00h                          Reserved
 2405 ** 01:00       00                Power State (PSTATE): This 2-bit field is used both to determine the current power state of 
 2406 **                                                                      a function and to set the Function into a new power state.
 2407 **                                                                                                      00 - D0 state
 2408 **                                                                                                      01 - D1 state
 2409 **                                                                                                      10 - D2 state
 2410 **                                                                                                      11 - D3 hot state
 2411 **===============================================================================
 2412 **  0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
 2413 ** Bit       Default                       Description
 2414 ** 07          0         Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
 2415 ** 06          0                B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 
 2416 **                                                                      is to occur as a direct result of programming the function to D3 hot.
 2417 **                                                                 This bit is only meaningful when bit 7 (BPCC_En) is a ˇ§1ˇ¨.
 2418 ** 05:00     00h                            Reserved
 2419 **===============================================================================
 2420 **  0xE3: Power Management Data Register - PMDR
 2421 ** Bit       Default                       Description
 2422 ** 07:00       00h                          Reserved
 2423 **===============================================================================
 2424 **  0xF0: PCI-X Capabilities Identifier - PX_CAPID
 2425 ** Bit       Default                       Description
 2426 ** 07:00       07h                       Identifier (ID): Indicates this is a PCI-X capabilities list.
 2427 **===============================================================================
 2428 **  0xF1: Next Item Pointer - PX_NXTP
 2429 ** Bit       Default                       Description
 2430 ** 07:00       00h                     Next Item Pointer: Points to the next capability in the linked list The power on default value of this
 2431 **                                                        register is 00h indicating that this is the last entry in the linked list of capabilities.
 2432 **===============================================================================
 2433 **  0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
 2434 ** Bit       Default                       Description
 2435 ** 15:09       00h                          Reserved
 2436 ** 08:06       Xxx                Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 
 2437 **                                                                 The values are:
 2438 **                                                                                                                                                      **              BitsMax FrequencyClock Period
 2439 **                                                                                                                                                      **              000PCI ModeN/A
 2440 **                                                                                                                                                      **              00166 15
 2441 **                                                                                                                                                      **              01010010
 2442 **                                                                                                                                                      **              0111337.5
 2443 **                                                                                                                                                      **              1xxreservedreserved
 2444 **                                                                                                                                                      **              The default value for this register is the operating frequency of the secondary bus
 2445 ** 05           0b                   Split Request Delayed. (SRD):  This bit is supposed to be set by a bridge when it cannot forward a transaction on the
 2446 **                                              secondary bus to the primary bus because there is not enough room within the limit
 2447 **                                              specified in the Split Transaction Commitment Limit field in the Downstream Split
 2448 **                                              Transaction Control register. The bridge does not set this bit.
 2449 ** 04           0b                 Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** **                                              secondary bus with retry or Disconnect at next ADB because its buffers are full. 
 2450 **                                              The bridge does not set this bit.
 2451 ** 03           0b              Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 
 2452 **                                              equal to bridge secondary bus number, device number 00h,
 2453 **                                              and function number 0 is received on the secondary interface. 
 2454 **                                              This bit is cleared by software writing a '1'.
 2455 ** 02           0b               Split Completion Discarded (SCD): This bit is set 
 2456 **                                              when bridge discards a split completion moving toward the secondary bus 
 2457 **                                              because the requester would not accept it. This bit cleared by software writing a '1'.
 2458 ** 01           1b                                133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
 2459 ** 00           1b                            64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
 2460 **===============================================================================
 2461 **  0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
 2462 ** Bit       Default                                                                                     Description
 2463 ** 31:22        0                                                                                         Reserved
 2464 ** 21           0                                                               Split Request Delayed (SRD): This bit does not be set by bridge.
 2465 ** 20           0                                                               Split Completion Overrun (SCO): This bit does not be set by bridge
 2466 **                                                                              because bridge throttles traffic on the completion side.
 2467 ** 19           0                                                               Unexpected Split Completion (USC): The bridge sets this bit to 1b 
 2468 **                                                                              when it encounters a corrupted Split Completion, possibly with an **    **                                                                              inconsistent remaining byte count.Software clears 
 2469 **                                                                              this bit by writing a 1b to it.
 2470 ** 18           0                                                               Split Completion Discarded (SCD): The bridge sets this bit to 1b 
 2471 **                                                                              when it has discarded a Split Completion.Software clears this bit by ** **                                                                              writing a 1b to it.
 2472 ** 17           1                                                               133 MHz Capable: This bit indicates that the bridge primary interface is **                                                                             capable of 133 MHz operation in PCI-X mode.
 2473 **                                                                              0=The maximum operating frequency is 66 MHz.
 2474 **                                                                              1=The maximum operating frequency is 133 MHz.
 2475 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset    64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
 2476 **                                                                               0=Primary Interface is connected as a 32-bit PCI bus.
 2477 **                                                                               1=Primary Interface is connected as a 64-bit PCI bus.
 2478 ** 15:08       00h                                                              Bus Number (BNUM): This field is simply an alias to the PBN field 
 2479 **                                                                                      of the BNUM register at offset 18h.
 2480 **                                                              Apparently it was deemed necessary reflect it here for diagnostic purposes.
 2481 ** 07:03       1fh                                              Device Number (DNUM): Indicates which IDSEL bridge consumes. 
 2482 **                                                              May be updated whenever a PCI-X
 2483 **                                                               configuration write cycle that targets bridge scores a hit.
 2484 ** 02:00        0h                                                   Function Number (FNUM): The bridge Function #
 2485 **===============================================================================
 2486 **  0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
 2487 ** Bit       Default                       Description
 2488 ** 31:16      003Eh                 Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
 2489 **                                                                 Software is permitted to program this register to any value greater than or equal to
 2490 **                                                                 the contents of the Split Transaction Capacity register. A value less than the contents
 2491 **                                                                 of the Split Transaction Capacity register causes unspecified results.
 2492 **                                                                 A value of 003Eh or greater enables the bridge to forward all Split Requests of any
 2493 **                                                                 size regardless of the amount of buffer space available.
 2494 ** 15:00      003Eh              Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
 2495 **                                 split completions. This register controls behavior of the bridge buffers for forwarding
 2496 **                                 Split Transactions from a primary bus requester to a secondary bus completer.
 2497 **                                 The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
 2498 **===============================================================================
 2499 **  0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
 2500 ** Bit       Default                       Description
 2501 ** 31:16      003Eh                 Split Transaction Limit (STL):  This register indicates the size of the commitment limit in units of ADQs.
 2502 **                                                      Software is permitted to program this register to any value greater than or equal to
 2503 **                                                      the contents of the Split Transaction Capacity register. A value less than the contents
 2504 **                                                      of the Split Transaction Capacity register causes unspecified results.
 2505 **                                                      A value of 003Eh or greater enables the bridge to forward all Split Requests of any
 2506 **                                                      size regardless of the amount of buffer space available.
 2507 ** 15:00      003Eh              Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
 2508 **                                                                 split completions. This register controls behavior of the bridge buffers for forwarding
 2509 **                                                                 Split Transactions from a primary bus requester to a secondary bus completer.
 2510 **                                                                 The default value of 003Eh indicates there is available buffer space for 62 ADQs 
 2511 **                                                                      (7936 bytes).
 2512 **************************************************************************
 2513 */
 2514 
 2515 
 2516 
 2517 
 2518 /*
 2519 *************************************************************************************************************************************
 2520 **                       80331 Address Translation Unit Register Definitions
 2521 **                               ATU Interface Configuration Header Format
 2522 **               The ATU is programmed via a [Type 0] configuration command on the PCI interface.
 2523 *************************************************************************************************************************************
 2524 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              | Configuration Byte Offset
 2525 **===================================================================================================================================
 2526 ** |                ATU Device ID                    |                     Vendor ID                      | 00h
 2527 ** ----------------------------------------------------------------------------------------------------------
 2528 ** |                     Status                      |                     Command                        | 04H
 2529 ** ----------------------------------------------------------------------------------------------------------
 2530 ** |                              ATU Class Code                              |       Revision ID         | 08H
 2531 ** ----------------------------------------------------------------------------------------------------------
 2532 ** |         ATUBISTR       |     Header Type        |      Latency Timer     |      Cacheline Size       | 0CH
 2533 ** ----------------------------------------------------------------------------------------------------------
 2534 ** |                                     Inbound ATU Base Address 0                                       | 10H
 2535 ** ----------------------------------------------------------------------------------------------------------
 2536 ** |                               Inbound ATU Upper Base Address 0                                       | 14H
 2537 ** ----------------------------------------------------------------------------------------------------------
 2538 ** |                                     Inbound ATU Base Address 1                                       | 18H
 2539 ** ----------------------------------------------------------------------------------------------------------
 2540 ** |                               Inbound ATU Upper Base Address 1                                       | 1CH
 2541 ** ----------------------------------------------------------------------------------------------------------
 2542 ** |                                     Inbound ATU Base Address 2                                       | 20H
 2543 ** ----------------------------------------------------------------------------------------------------------
 2544 ** |                               Inbound ATU Upper Base Address 2                                       | 24H
 2545 ** ----------------------------------------------------------------------------------------------------------
 2546 ** |                                             Reserved                                                 | 28H   
 2547 ** ----------------------------------------------------------------------------------------------------------
 2548 ** |                ATU Subsystem ID                 |                ATU Subsystem Vendor ID             | 2CH
 2549 ** ----------------------------------------------------------------------------------------------------------
 2550 ** |                                       Expansion ROM Base Address                                     | 30H
 2551 ** ----------------------------------------------------------------------------------------------------------
 2552 ** |                                    Reserved Capabilities Pointer                                     | 34H
 2553 ** ----------------------------------------------------------------------------------------------------------
 2554 ** |                                             Reserved                                                 | 38H
 2555 ** ----------------------------------------------------------------------------------------------------------
 2556 ** |     Maximum Latency    |     Minimum Grant      |       Interrupt Pin    |      Interrupt Line       | 3CH
 2557 ** ----------------------------------------------------------------------------------------------------------
 2558 *********************************************************************************************************************
 2559 */
 2560 /*
 2561 ***********************************************************************************
 2562 **  ATU Vendor ID Register - ATUVID
 2563 **  -----------------------------------------------------------------
 2564 **  Bit       Default                       Description
 2565 **  15:00      8086H (0x17D3)               ATU Vendor ID - This is a 16-bit value assigned to Intel. 
 2566 **                                              This register, combined with the DID, uniquely identify the PCI device. 
 2567 **      Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 
 2568 **      to simulate the interface of a standard mechanism currently used by existing application software.
 2569 ***********************************************************************************
 2570 */
 2571 #define     ARCMSR_ATU_VENDOR_ID_REG                     0x00    /*word*/
 2572 /*
 2573 ***********************************************************************************
 2574 **  ATU Device ID Register - ATUDID
 2575 **  -----------------------------------------------------------------
 2576 **  Bit       Default                       Description
 2577 **  15:00      0336H (0x1110)               ATU Device ID - This is a 16-bit value assigned to the ATU. 
 2578 **      This ID, combined with the VID, uniquely identify any PCI device.
 2579 ***********************************************************************************
 2580 */
 2581 #define     ARCMSR_ATU_DEVICE_ID_REG                     0x02    /*word*/
 2582 /*
 2583 ***********************************************************************************
 2584 **  ATU Command Register - ATUCMD
 2585 **  -----------------------------------------------------------------
 2586 **  Bit       Default                       Description
 2587 **  15:11      000000 2                     Reserved
 2588 **  10           0                          Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
 2589 **                                                              0=enables the assertion of interrupt signal.
 2590 **                                                              1=disables the assertion of its interrupt signal.
 2591 **  09          0 2                         Fast Back to Back Enable - When cleared, 
 2592 **                                              the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
 2593 **                                              Ignored when operating in the PCI-X mode.
 2594 **  08          0 2                         SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
 2595 **  07          1 2                         Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
 2596 **                                          ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 
 2597 **                                              of address stepping for PCI-X mode.
 2598 **  06          0 2                         Parity Error Response - When set, the ATU takes normal action when a parity error 
 2599 **                                              is detected. When cleared, parity checking is disabled.
 2600 **  05          0 2                         VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 
 2601 **                                              does not perform VGA palette snooping.
 2602 **  04          0 2                         Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 
 2603 **                                              When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
 2604 **  03          0 2                         Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 
 2605 **                                              Not implemented and a reserved bit field.
 2606 **  02          0 2                         Bus Master Enable - The ATU interface can act as a master on the PCI bus. 
 2607 **                                              When cleared, disables the device from generating PCI accesses. 
 2608 **                                              When set, allows the device to behave as a PCI bus master.
 2609 **                                          When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 
 2610 **                                              of the state of this bit.
 2611 **  01          0 2                         Memory Enable - Controls the ATU interfaceˇ¦s response to PCI memory addresses. 
 2612 **                                              When cleared, the ATU interface does not respond to any memory access on the PCI bus.
 2613 **  00          0 2                         I/O Space Enable - Controls the ATU interface response to I/O transactions. 
 2614 **                                              Not implemented and a reserved bit field.
 2615 ***********************************************************************************
 2616 */
 2617 #define     ARCMSR_ATU_COMMAND_REG                       0x04    /*word*/
 2618 /*
 2619 ***********************************************************************************
 2620 **  ATU Status Register - ATUSR (Sheet 1 of 2)
 2621 **  -----------------------------------------------------------------
 2622 **  Bit       Default                       Description
 2623 **  15          0 2                         Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
 2624 **                                      when the ATUCMD registerˇ¦s Parity Error Response bit is cleared. Set under the following conditions:
 2625 **                                                                              ˇE Write Data Parity Error when the ATU is a target (inbound write).
 2626 **                                                                              ˇE Read Data Parity Error when the ATU is a requester (outbound read).
 2627 **                                                                              ˇE Any Address or Attribute (PCI-X Only) Parity Error on the Bus **     ** **                                                           (including one generated by the ATU).
 2628 **  14          0 2                         SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
 2629 **  13          0 2                         Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
 2630 **                                          or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
 2631 **  12          0 2                         Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
 2632 **                                          abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
 2633 **  11          0 2                         Target Abort (target) - set when the ATU interface, acting as a target, 
 2634 **                                              terminates the transaction on the PCI bus with a target abort.
 2635 **  10:09       01 2                        DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 
 2636 **                                              timing for a target device in Conventional PCI Mode regardless of the operating mode 
 2637 **                                                      (except configuration accesses).
 2638 **                                                                              00 2=Fast
 2639 **                                                                              01 2=Medium
 2640 **                                                                              10 2=Slow
 2641 **                                                                              11 2=Reserved
 2642 **                                          The ATU interface uses Medium timing.
 2643 **  08           0 2                        Master Parity Error - The ATU interface sets this bit under the following conditions:
 2644 **                                                                              ˇE The ATU asserted PERR# itself or the ATU observed PERR# asserted.
 2645 **                                                                              ˇE And the ATU acted as the requester 
 2646 **                                                                                      for the operation in which the error occurred.
 2647 **                                                                              ˇE And the ATUCMD registerˇ¦s Parity Error Response bit is set
 2648 **                                                                              ˇE Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
 2649 **                                                                              ˇE And the ATUCMD registerˇ¦s Parity Error Response bit is set
 2650 **  07           1 2  (Conventional mode)
 2651 **               0 2  (PCI-X mode)
 2652 **                                                      Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back
 2653 **                                                      transactions in Conventional PCI mode when the transactions are not to the same target. Since fast
 2654 **                                                      back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
 2655 **  06           0 2                        UDF Supported - User Definable Features are not supported
 2656 **  05           1 2                        66 MHz. Capable - 66 MHz operation is supported.
 2657 **  04           1 2                        Capabilities - When set, this function implements extended capabilities.
 2658 **  03             0                        Interrupt Status - reflects the state of the ATU interrupt 
 2659 **                                              when the Interrupt Disable bit in the command register is a 0.
 2660 **                                                                              0=ATU interrupt signal deasserted.
 2661 **                                                                              1=ATU interrupt signal asserted.
 2662 **              NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to
 2663 **              Section 3.10.23, ˇ§ATU Interrupt Pin Register - ATUIPRˇ¨ on page 236 for details on the ATU
 2664 **                                                                              interrupt signal.
 2665 **  02:00      00000 2                      Reserved.
 2666 ***********************************************************************************
 2667 */
 2668 #define     ARCMSR_ATU_STATUS_REG                        0x06    /*word*/
 2669 /*
 2670 ***********************************************************************************
 2671 **  ATU Revision ID Register - ATURID
 2672 **  -----------------------------------------------------------------
 2673 **  Bit       Default                       Description
 2674 **  07:00        00H                        ATU Revision - identifies the 80331 revision number.
 2675 ***********************************************************************************
 2676 */
 2677 #define     ARCMSR_ATU_REVISION_REG                      0x08    /*byte*/
 2678 /*
 2679 ***********************************************************************************
 2680 **  ATU Class Code Register - ATUCCR
 2681 **  -----------------------------------------------------------------
 2682 **  Bit       Default                       Description
 2683 **  23:16        05H                        Base Class - Memory Controller
 2684 **  15:08        80H                        Sub Class - Other Memory Controller
 2685 **  07:00        00H                        Programming Interface - None defined
 2686 ***********************************************************************************
 2687 */
 2688 #define     ARCMSR_ATU_CLASS_CODE_REG                    0x09    /*3bytes 0x0B,0x0A,0x09*/
 2689 /*
 2690 ***********************************************************************************
 2691 **  ATU Cacheline Size Register - ATUCLSR
 2692 **  -----------------------------------------------------------------
 2693 **  Bit       Default                       Description
 2694 **  07:00        00H                        ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs.
 2695 ***********************************************************************************
 2696 */
 2697 #define     ARCMSR_ATU_CACHELINE_SIZE_REG                        0x0C    /*byte*/
 2698 /*
 2699 ***********************************************************************************
 2700 **  ATU Latency Timer Register - ATULT
 2701 **  -----------------------------------------------------------------
 2702 **  Bit       Default                       Description
 2703 **  07:03     00000 2   (for Conventional mode)
 2704 **            01000 2   (for PCI-X mode)
 2705 **                      Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks.
 2706 **                      The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
 2707 **  02:00       000 2   Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer.
 2708 ***********************************************************************************
 2709 */
 2710 #define     ARCMSR_ATU_LATENCY_TIMER_REG                         0x0D    /*byte*/
 2711 /*
 2712 ***********************************************************************************
 2713 **  ATU Header Type Register - ATUHTR
 2714 **  -----------------------------------------------------------------
 2715 **  Bit       Default                       Description
 2716 **  07           0 2                        Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device.
 2717 **  06:00   000000 2                        PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface
 2718 **                                          header conforms to PCI Local Bus Specification, Revision 2.3.
 2719 ***********************************************************************************
 2720 */
 2721 #define     ARCMSR_ATU_HEADER_TYPE_REG                   0x0E    /*byte*/
 2722 /*
 2723 ***********************************************************************************
 2724 **  ATU BIST Register - ATUBISTR
 2725 **
 2726 **  The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
 2727 **  initiated. This register is the interface between the host processor requesting BIST functions and
 2728 **  the 80331 replying with the results from the software implementation of the BIST functionality.
 2729 **  -----------------------------------------------------------------
 2730 **  Bit       Default                       Description
 2731 **  07           0 2                        BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 
 2732 **  06           0 2                        Start BIST - When the ATUCR BIST Interrupt Enable bit is set:
 2733 **                               Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
 2734 **                               The Intel XScale core clears this bit when the BIST software has completed with the BIST results
 2735 **                               found in ATUBISTR register bits [3:0].
 2736 **                               When the ATUCR BIST Interrupt Enable bit is clear:
 2737 **                               Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 
 2738 **                                                       The Intel XScale core does not clear this bit.
 2739 **  05:04       00 2             Reserved
 2740 **  03:00     0000 2             BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6):
 2741 **                               The Intel XScale  core places the results of the software BIST in these bits. 
 2742 **                               A nonzero value indicates a device-specific error.
 2743 ***********************************************************************************
 2744 */
 2745 #define     ARCMSR_ATU_BIST_REG                  0x0F    /*byte*/
 2746 
 2747 /*
 2748 ***************************************************************************************  
 2749 **            ATU Base Registers and Associated Limit Registers
 2750 ***************************************************************************************
 2751 **           Base Address                         Register Limit                          Register Description
 2752 **  Inbound ATU Base Address Register 0           Inbound ATU Limit Register 0            Defines the inbound translation window 0 from the PCI bus.
 2753 **  Inbound ATU Upper Base Address Register 0     N/A                                     Together with ATU Base Address Register 0 defines the inbound **                                                              translation window 0 from the PCI bus for DACs.
 2754 **  Inbound ATU Base Address Register 1           Inbound ATU Limit Register 1            Defines inbound window 1 from the PCI bus.
 2755 **  Inbound ATU Upper Base Address Register 1     N/A                                     Together with ATU Base Address Register 1 defines inbound window **  1 from the PCI bus for DACs.
 2756 **  Inbound ATU Base Address Register 2           Inbound ATU Limit Register 2            Defines the inbound translation window 2 from the PCI bus.
 2757 **  Inbound ATU Upper Base Address Register 2     N/A                                     Together with ATU Base Address Register 2 defines the inbound ** **  translation window 2 from the PCI bus for DACs.
 2758 **  Inbound ATU Base Address Register 3           Inbound ATU Limit Register 3            Defines the inbound translation window 3 from the PCI bus.
 2759 **  Inbound ATU Upper Base Address Register 3     N/A                                     Together with ATU Base Address Register 3 defines the inbound ** **  translation window 3 from the PCI bus for DACs.
 2760 **     NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
 2761 **  Expansion ROM Base Address Register           Expansion ROM Limit Register            Defines the window of addresses used by a bus master for reading **  from an Expansion ROM.
 2762 **--------------------------------------------------------------------------------------
 2763 **  ATU Inbound Window 1 is not a translate window. 
 2764 **  The ATU does not claim any PCI accesses that fall within this range. 
 2765 **  This window is used to allocate host memory for use by Private Devices. 
 2766 **  When enabled, the ATU interrupts the Intel  XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 
 2767 ***********************************************************************************
 2768 */
 2769 
 2770 /*
 2771 ***********************************************************************************
 2772 **  Inbound ATU Base Address Register 0 - IABAR0
 2773 **
 2774 **  . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 
 2775 **    defines the block of memory addresses where the inbound translation window 0 begins. 
 2776 **  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 2777 **  . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size.
 2778 **  . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 
 2779 **    depending on the value located within the IALR0. 
 2780 **    This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
 2781 **    The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
 2782 **    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 2783 **  Warning: 
 2784 **    When IALR0 is cleared prior to host configuration:
 2785 **                          the user should also clear the Prefetchable Indicator and the Type Indicator. 
 2786 **    Assuming IALR0 is not cleared:
 2787 **                          a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
 2788 **                             when the Prefetchable Indicator is cleared prior to host configuration, 
 2789 **                             the user should also set the Type Indicator for 32 bit addressability.
 2790 **                          b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification,
 2791 **                             when the Prefetchable Indicator is set prior to host configuration, the user
 2792 **                             should also set the Type Indicator for 64 bit addressability. 
 2793 **                             This is the default for IABAR0.
 2794 **  -----------------------------------------------------------------
 2795 **  Bit       Default                       Description
 2796 **  31:12     00000H                        Translation Base Address 0 - These bits define the actual location 
 2797 **                                              the translation function is to respond to when addressed from the PCI bus.
 2798 **  11:04        00H                        Reserved.
 2799 **  03           1 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 2800 **  02:01       10 2                        Type Indicator - Defines the width of the addressability for this memory window:
 2801 **                                              00 - Memory Window is locatable anywhere in 32 bit address space
 2802 **                                              10 - Memory Window is locatable anywhere in 64 bit address space
 2803 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
 2804 **                                                                   The ATU does not occupy I/O space, 
 2805 **                                                                   thus this bit must be zero.
 2806 ***********************************************************************************
 2807 */
 2808 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG                         0x10    /*dword 0x13,0x12,0x11,0x10*/
 2809 #define     ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE                       0x08
 2810 #define     ARCMSR_INBOUND_ATU_MEMORY_WINDOW64                           0x04
 2811 /*
 2812 ***********************************************************************************
 2813 **  Inbound ATU Upper Base Address Register 0 - IAUBAR0
 2814 **
 2815 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 2816 **  Together with the Translation Base Address this register defines the actual location the translation
 2817 **  function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 2818 **  The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 2819 **  Note: 
 2820 **      When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 
 2821 **      the IAUBAR0 register attributes are read-only.
 2822 **  -----------------------------------------------------------------
 2823 **  Bit       Default                       Description
 2824 **  31:0      00000H                        Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the
 2825 **                           actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
 2826 ***********************************************************************************
 2827 */
 2828 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG               0x14    /*dword 0x17,0x16,0x15,0x14*/
 2829 /*
 2830 ***********************************************************************************
 2831 **  Inbound ATU Base Address Register 1 - IABAR1
 2832 **
 2833 **  . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 
 2834 **    defines the block of memory addresses where the inbound translation window 1 begins. 
 2835 **  . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
 2836 **  . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 2837 **  . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 
 2838 **    Warning: 
 2839 **    When a non-zero value is not written to IALR1 prior to host configuration, 
 2840 **                          the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 
 2841 **                          This is the default for IABAR1.
 2842 **    Assuming a non-zero value is written to IALR1, 
 2843 **                                      the user may set the Prefetchable Indicator 
 2844 **                                                    or the Type         Indicator:
 2845 **                                              a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address
 2846 **                                                 boundary, when the Prefetchable Indicator is not set prior to host configuration, 
 2847 **                             the user should also leave the Type Indicator set for 32 bit addressability. 
 2848 **                             This is the default for IABAR1.
 2849 **                                              b. when the Prefetchable Indicator is set prior to host configuration, 
 2850 **                             the user should also set the Type Indicator for 64 bit addressability.
 2851 **  -----------------------------------------------------------------
 2852 **  Bit       Default                       Description
 2853 **  31:12     00000H                        Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus.
 2854 **  11:04        00H                        Reserved.
 2855 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 2856 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 2857 **                      00 - Memory Window is locatable anywhere in 32 bit address space
 2858 **                      10 - Memory Window is locatable anywhere in 64 bit address space
 2859 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
 2860 **                                                                   The ATU does not occupy I/O space, 
 2861 **                                                                   thus this bit must be zero.
 2862 ***********************************************************************************
 2863 */
 2864 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG                         0x18    /*dword 0x1B,0x1A,0x19,0x18*/
 2865 /*
 2866 ***********************************************************************************
 2867 **  Inbound ATU Upper Base Address Register 1 - IAUBAR1
 2868 **
 2869 **  This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 
 2870 **  Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 
 2871 **  This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
 2872 **  The programmed value within the base address register must comply with the PCI programming
 2873 **  requirements for address alignment. 
 2874 **  When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
 2875 **  from the PCI bus. 
 2876 **  Note: 
 2877 **      When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 
 2878 **      the IAUBAR1 register attributes are read-only. 
 2879 **      This is the default for IABAR1.
 2880 **  -----------------------------------------------------------------
 2881 **  Bit       Default                       Description
 2882 **  31:0      00000H                        Translation Upper Base Address 1 - Together with the Translation Base Address 1 
 2883 **                                              these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes.
 2884 ***********************************************************************************
 2885 */
 2886 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG                   0x1C    /*dword 0x1F,0x1E,0x1D,0x1C*/
 2887 /*
 2888 ***********************************************************************************
 2889 **  Inbound ATU Base Address Register 2 - IABAR2
 2890 **
 2891 **  . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 
 2892 **           defines the block of memory addresses where the inbound translation window 2 begins. 
 2893 **  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 2894 **  . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size
 2895 **  . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2.
 2896 **    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 2897 **  Warning: 
 2898 **    When a non-zero value is not written to IALR2 prior to host configuration, 
 2899 **                          the user should not set either the Prefetchable Indicator 
 2900 **                                                      or the Type         Indicator for 64 bit addressability. 
 2901 **                          This is the default for IABAR2.
 2902 **  Assuming a non-zero value is written to IALR2, 
 2903 **                          the user may set the Prefetchable Indicator 
 2904 **                                        or the Type         Indicator:
 2905 **                                              a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 
 2906 **                             when the Prefetchable Indicator is not set prior to host configuration, 
 2907 **                             the user should also leave the Type Indicator set for 32 bit addressability. 
 2908 **                             This is the default for IABAR2.
 2909 **                                              b. when the Prefetchable Indicator is set prior to host configuration, 
 2910 **                             the user should also set the Type Indicator for 64 bit addressability.
 2911 **  -----------------------------------------------------------------
 2912 **  Bit       Default                       Description
 2913 **  31:12     00000H                        Translation Base Address 2 - These bits define the actual location 
 2914 **                                              the translation function is to respond to when addressed from the PCI bus.
 2915 **  11:04        00H                        Reserved.
 2916 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 2917 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 2918 **                      00 - Memory Window is locatable anywhere in 32 bit address space
 2919 **                      10 - Memory Window is locatable anywhere in 64 bit address space
 2920 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
 2921 **                                                                   The ATU does not occupy I/O space, 
 2922 **                                                                   thus this bit must be zero.
 2923 ***********************************************************************************
 2924 */
 2925 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG                         0x20    /*dword 0x23,0x22,0x21,0x20*/
 2926 /*
 2927 ***********************************************************************************
 2928 **  Inbound ATU Upper Base Address Register 2 - IAUBAR2
 2929 **
 2930 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 2931 **  Together with the Translation Base Address this register defines the actual location 
 2932 **  the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 2933 **  The programmed value within the base address register must comply with the PCI programming
 2934 **  requirements for address alignment.
 2935 **  Note: 
 2936 **      When the Type indicator of IABAR2 is set to indicate 32 bit addressability,
 2937 **      the IAUBAR2 register attributes are read-only. 
 2938 **      This is the default for IABAR2.
 2939 **  -----------------------------------------------------------------
 2940 **  Bit       Default                       Description
 2941 **  31:0      00000H                        Translation Upper Base Address 2 - Together with the Translation Base Address 2 
 2942 **                                          these bits define the actual location the translation function is to respond to 
 2943 **                                          when addressed from the PCI bus for addresses > 4GBytes.
 2944 ***********************************************************************************
 2945 */
 2946 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG                   0x24    /*dword 0x27,0x26,0x25,0x24*/
 2947 /*
 2948 ***********************************************************************************
 2949 **  ATU Subsystem Vendor ID Register - ASVIR
 2950 **  -----------------------------------------------------------------
 2951 **  Bit       Default                       Description
 2952 **  15:0      0000H                         Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor.
 2953 ***********************************************************************************
 2954 */
 2955 #define     ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG                   0x2C    /*word 0x2D,0x2C*/
 2956 /*
 2957 ***********************************************************************************
 2958 **  ATU Subsystem ID Register - ASIR
 2959 **  -----------------------------------------------------------------
 2960 **  Bit       Default                       Description
 2961 **  15:0      0000H                         Subsystem ID - uniquely identifies the add-in board or subsystem.
 2962 ***********************************************************************************
 2963 */
 2964 #define     ARCMSR_ATU_SUBSYSTEM_ID_REG                  0x2E    /*word 0x2F,0x2E*/
 2965 /*
 2966 ***********************************************************************************
 2967 **  Expansion ROM Base Address Register -ERBAR
 2968 **  -----------------------------------------------------------------
 2969 **  Bit       Default                       Description
 2970 **  31:12     00000H                        Expansion ROM Base Address - These bits define the actual location 
 2971 **                                              where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary.
 2972 **  11:01     000H                          Reserved
 2973 **  00        0 2                           Address Decode Enable - This bit field shows the ROM address 
 2974 **                                              decoder is enabled or disabled. When cleared, indicates the address decoder is disabled.
 2975 ***********************************************************************************
 2976 */
 2977 #define     ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG                        0x30    /*dword 0x33,0x32,0v31,0x30*/
 2978 #define     ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE                       0x01    
 2979 /*
 2980 ***********************************************************************************
 2981 **  ATU Capabilities Pointer Register - ATU_CAP_PTR
 2982 **  -----------------------------------------------------------------
 2983 **  Bit Default Description
 2984 **  07:00     C0H                           Capability List Pointer - This provides an offset in this functionˇ¦s configuration space 
 2985 **                                              that points to the 80331 PCl Bus Power Management extended capability.
 2986 ***********************************************************************************
 2987 */
 2988 #define     ARCMSR_ATU_CAPABILITY_PTR_REG                    0x34    /*byte*/
 2989 /*
 2990 ***********************************************************************************  
 2991 **  Determining Block Sizes for Base Address Registers
 2992 **  The required address size and type can be determined by writing ones to a base address register and
 2993 **  reading from the registers. By scanning the returned value from the least-significant bit of the base
 2994 **  address registers upwards, the programmer can determine the required address space size. The
 2995 **  binary-weighted value of the first non-zero bit found indicates the required amount of space.
 2996 **  Table 105 describes the relationship between the values read back and the byte sizes the base
 2997 **  address register requires.
 2998 **  As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
 2999 **  (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires
 3000 **  memory address space. Bit three is one, so the memory does supports prefetching. Scanning
 3001 **  upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this
 3002 **  bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space.
 3003 **  The ATU Base Address Registers and the Expansion ROM Base Address Register use their
 3004 **  associated limit registers to enable which bits within the base address register are read/write and
 3005 **  which bits are read only (0). This allows the programming of these registers in a manner similar to
 3006 **  other PCI devices even though the limit is variable.
 3007 **  Table 105. Memory Block Size Read Response
 3008 **  Response After Writing all 1s
 3009 **  to the Base Address Register
 3010 **  Size
 3011 **  (Bytes)
 3012 **  Response After Writing all 1s
 3013 **  to the Base Address Register
 3014 **  Size
 3015 **  (Bytes)
 3016 **  FFFFFFF0H 16 FFF00000H 1 M
 3017 **  FFFFFFE0H 32 FFE00000H 2 M
 3018 **  FFFFFFC0H 64 FFC00000H 4 M
 3019 **  FFFFFF80H 128 FF800000H 8 M
 3020 **  FFFFFF00H 256 FF000000H 16 M
 3021 **  FFFFFE00H 512 FE000000H 32 M
 3022 **  FFFFFC00H 1K FC000000H 64 M
 3023 **  FFFFF800H 2K F8000000H 128 M
 3024 **  FFFFF000H 4K F0000000H 256 M
 3025 **  FFFFE000H 8K E0000000H 512 M
 3026 **  FFFFC000H 16K C0000000H 1 G
 3027 **  FFFF8000H 32K 80000000H 2 G
 3028 **  FFFF0000H 64K
 3029 **  00000000H
 3030 **  Register not
 3031 **  imple-mented,
 3032 **  no
 3033 **  address
 3034 **  space
 3035 **  required.
 3036 **  FFFE0000H 128K
 3037 **  FFFC0000H 256K
 3038 **  FFF80000H 512K
 3039 **
 3040 ***************************************************************************************  
 3041 */
 3042 
 3043 
 3044 
 3045 /*
 3046 ***********************************************************************************
 3047 **  ATU Interrupt Line Register - ATUILR
 3048 **  -----------------------------------------------------------------
 3049 **  Bit       Default                       Description
 3050 **  07:00       FFH                         Interrupt Assigned - system-assigned value identifies which system interrupt controllerˇ¦s interrupt
 3051 **                                                               request line connects to the device's PCI interrupt request lines 
 3052 **                                                              (as specified in the interrupt pin register).
 3053 **                                                               A value of FFH signifies ˇ§no connectionˇ¨ or ˇ§unknownˇ¨.
 3054 ***********************************************************************************
 3055 */
 3056 #define     ARCMSR_ATU_INTERRUPT_LINE_REG                    0x3C    /*byte*/
 3057 /*
 3058 ***********************************************************************************
 3059 **  ATU Interrupt Pin Register - ATUIPR
 3060 **  -----------------------------------------------------------------
 3061 **  Bit       Default                       Description
 3062 **  07:00       01H                         Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin.
 3063 ***********************************************************************************
 3064 */
 3065 #define     ARCMSR_ATU_INTERRUPT_PIN_REG                     0x3D    /*byte*/
 3066 /*
 3067 ***********************************************************************************
 3068 **  ATU Minimum Grant Register - ATUMGNT
 3069 **  -----------------------------------------------------------------
 3070 **  Bit       Default                       Description
 3071 **  07:00       80H                         This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
 3072 ***********************************************************************************
 3073 */
 3074 #define     ARCMSR_ATU_MINIMUM_GRANT_REG                     0x3E    /*byte*/
 3075 /*
 3076 ***********************************************************************************
 3077 **  ATU Maximum Latency Register - ATUMLAT
 3078 **  -----------------------------------------------------------------
 3079 **  Bit       Default                       Description
 3080 **  07:00       00H                         Specifies frequency (how often) the device needs to access the PCI bus 
 3081 **                                              in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement.
 3082 ***********************************************************************************
 3083 */
 3084 #define     ARCMSR_ATU_MAXIMUM_LATENCY_REG                   0x3F    /*byte*/
 3085 /*
 3086 ***********************************************************************************
 3087 **  Inbound Address Translation
 3088 **  
 3089 **  The ATU allows external PCI bus initiators to directly access the internal bus. 
 3090 **  These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 
 3091 **  The process of inbound address translation involves two steps:
 3092 **  1. Address Detection.
 3093 **             ˇE Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
 3094 **                within the address windows defined for the inbound ATU.
 3095 **             ˇE Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
 3096 **                mode and with Decode A DEVSEL# timing in the PCI-X mode.
 3097 **  2. Address Translation.
 3098 **             ˇE Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address.
 3099 **                              The ATU uses the following registers in inbound address window 0 translation:
 3100 **                              ˇE Inbound ATU Base Address Register 0
 3101 **                              ˇE Inbound ATU Limit Register 0
 3102 **                              ˇE Inbound ATU Translate Value Register 0
 3103 **                              The ATU uses the following registers in inbound address window 2 translation:
 3104 **                              ˇE Inbound ATU Base Address Register 2
 3105 **                              ˇE Inbound ATU Limit Register 2
 3106 **                              ˇE Inbound ATU Translate Value Register 2
 3107 **                              The ATU uses the following registers in inbound address window 3 translation:
 3108 **                              ˇE Inbound ATU Base Address Register 3
 3109 **                              ˇE Inbound ATU Limit Register 3
 3110 **                              ˇE Inbound ATU Translate Value Register 3
 3111 **    Note: Inbound Address window 1 is not a translate window. 
 3112 **          Instead, window 1 may be used to allocate host memory for Private Devices.
 3113 **          Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 
 3114 **          thus the host BIOS does not configure window 3.
 3115 **          Window 3 is intended to be used as a special window into local memory for private PCI
 3116 **          agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge.
 3117 **          PCI-to-PCI Bridge in 80331 or
 3118 **          Inbound address detection is determined from the 32-bit PCI address, 
 3119 **          (64-bit PCI address during DACs) the base address register and the limit register. 
 3120 **          In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 
 3121 **  
 3122 **  The algorithm for detection is:
 3123 **  
 3124 **  Equation 1. Inbound Address Detection
 3125 **              When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 
 3126 **              the PCI Address is claimed by the Inbound ATU.
 3127 **  
 3128 **                      The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed
 3129 **                      with the associated inbound limit register. 
 3130 **              When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 
 3131 **              the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU.
 3132 **
 3133 **                      Note:   The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 
 3134 **                                      Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
 3135 **                                      internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the
 3136 **                                      lower 32-bits are used during address translation. 
 3137 **                              The algorithm is:
 3138 **  
 3139 **  
 3140 **  Equation 2. Inbound Translation
 3141 **              Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0].
 3142 **  
 3143 **                      The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the
 3144 **                      bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and
 3145 **                      the result is the internal bus address. This translation mechanism is used for all inbound memory
 3146 **                      read and write commands excluding inbound configuration read and writes. 
 3147 **                      In the PCI mode for inbound memory transactions, the only burst order supported is Linear
 3148 **                      Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase.
 3149 **                      The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode.
 3150 **  example:
 3151 **          Register Values
 3152 **                       Base_Register=3A00 0000H
 3153 **                      Limit_Register=FF80 0000H (8 Mbyte limit value)
 3154 **                      Value_Register=B100 0000H
 3155 **                      Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
 3156 **              
 3157 **              Address Detection (32-bit address)
 3158 **
 3159 **                                              PCI_Address & Limit_Register == Base_Register
 3160 **                                              3A45 012CH  &   FF80 0000H   ==  3A00 0000H
 3161 **
 3162 **                                      ANS: PCI_Address is in the Inbound Translation Window
 3163 **              Address Translation (to get internal bus address)
 3164 **
 3165 **                                              IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg
 3166 **                                              IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H
 3167 **
 3168 **                                      ANS:IB_Address=B145 012CH
 3169 ***********************************************************************************
 3170 */
 3171 
 3172 
 3173 
 3174 /*
 3175 ***********************************************************************************
 3176 **  Inbound ATU Limit Register 0 - IALR0
 3177 **
 3178 **  Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
 3179 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 3180 **  PCI addresses to internal bus addresses.
 3181 **  The 80331 translate value registerˇ¦s programmed value must be naturally aligned with the base
 3182 **  address registerˇ¦s programmed value. The limit register is used as a mask; thus, the lower address
 3183 **  bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
 3184 **  Specification, Revision 2.3 for additional information on programming base address registers.
 3185 **  Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a
 3186 **  one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit
 3187 **  within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0
 3188 **  makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of
 3189 **  this programming scheme is that unless a valid value exists within the IALR0, all writes to the
 3190 **  IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only  register.
 3191 **  -----------------------------------------------------------------
 3192 **  Bit       Default                       Description
 3193 **  31:12     FF000H                        Inbound Translation Limit 0 - This readback value determines the memory block size required for
 3194 **                                          inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB.
 3195 **  11:00       000H                        Reserved
 3196 ***********************************************************************************
 3197 */
 3198 #define     ARCMSR_INBOUND_ATU_LIMIT0_REG                    0x40    /*dword 0x43,0x42,0x41,0x40*/
 3199 /*
 3200 ***********************************************************************************
 3201 **  Inbound ATU Translate Value Register 0 - IATVR0
 3202 **
 3203 **  The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
 3204 **  convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
 3205 **  inbound ATU address translation.
 3206 **  -----------------------------------------------------------------
 3207 **  Bit       Default                       Description
 3208 **  31:12     FF000H                        Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 
 3209 **                                          This value must be 64-bit aligned on the internal bus. 
 3210 **                                              The default address allows the ATU to access the internal 80331 memory-mapped registers.
 3211 **  11:00       000H                        Reserved
 3212 ***********************************************************************************
 3213 */
 3214 #define     ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG                  0x44    /*dword 0x47,0x46,0x45,0x44*/
 3215 /*
 3216 ***********************************************************************************
 3217 **  Expansion ROM Limit Register - ERLR
 3218 **
 3219 **  The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines
 3220 **  as Expansion ROM address space. The block size is programmed by writing a value into the ERLR.
 3221 **  Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one
 3222 **  to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within
 3223 **  the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes
 3224 **  the corresponding bit within the ERBAR read/write from PCI.
 3225 **  -----------------------------------------------------------------
 3226 **  Bit       Default                       Description
 3227 **  31:12     000000H                       Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default
 3228 **                         value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0.
 3229 **  11:00        000H                       Reserved.
 3230 ***********************************************************************************
 3231 */
 3232 #define     ARCMSR_EXPANSION_ROM_LIMIT_REG                        0x48    /*dword 0x4B,0x4A,0x49,0x48*/
 3233 /*
 3234 ***********************************************************************************
 3235 **  Expansion ROM Translate Value Register - ERTVR
 3236 **
 3237 **  The Expansion ROM Translate Value Register contains the 80331 internal bus address which the
 3238 **  ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
 3239 **  Expansion ROM address translation.
 3240 **  -----------------------------------------------------------------
 3241 **  Bit       Default                       Description
 3242 **  31:12     00000H                        Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses
 3243 **                          for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus.
 3244 **  11:00       000H                        Reserved
 3245 ***********************************************************************************
 3246 */
 3247 #define     ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG                      0x4C    /*dword 0x4F,0x4E,0x4D,0x4C*/
 3248 /*
 3249 ***********************************************************************************
 3250 **  Inbound ATU Limit Register 1 - IALR1
 3251 **
 3252 **  Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a
 3253 **  one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit
 3254 **  within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1
 3255 **  makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of
 3256 **  this programming scheme is that unless a valid value exists within the IALR1, all writes to the
 3257 **  IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only
 3258 **  register.
 3259 **  The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
 3260 **  not process any PCI bus transactions to this memory range.
 3261 **  Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
 3262 **  IAUBAR1, and IALR1.
 3263 **  -----------------------------------------------------------------
 3264 **  Bit       Default                       Description
 3265 **  31:12     00000H                        Inbound Translation Limit 1 - This readback value determines the memory block size 
 3266 **                                              required for the ATUs memory window 1.
 3267 **  11:00 000H Reserved
 3268 ***********************************************************************************
 3269 */
 3270 #define     ARCMSR_INBOUND_ATU_LIMIT1_REG                         0x50    /*dword 0x53,0x52,0x51,0x50*/
 3271 /*
 3272 ***********************************************************************************
 3273 **  Inbound ATU Limit Register 2 - IALR2
 3274 **  
 3275 **  Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
 3276 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 3277 **  PCI addresses to internal bus addresses.
 3278 **  The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When
 3279 **  determining block size requirements ˇX as described in Section 3.10.21 ˇX the translation limit
 3280 **  register provides the block size requirements for the base address register. The remaining registers
 3281 **  used for performing address translation are discussed in Section 3.2.1.1.
 3282 **  The 80331 translate value registerˇ¦s programmed value must be naturally aligned with the base
 3283 **  address registerˇ¦s programmed value. The limit register is used as a mask; thus, the lower address
 3284 **  bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
 3285 **  Specification, Revision 2.3 for additional information on programming base address registers.
 3286 **  Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a
 3287 **  one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit
 3288 **  within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2
 3289 **  makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of
 3290 **  this programming scheme is that unless a valid value exists within the IALR2, all writes to the
 3291 **  IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only
 3292 **  register.
 3293 **  -----------------------------------------------------------------
 3294 **  Bit       Default                       Description
 3295 **  31:12     00000H                        Inbound Translation Limit 2 - This readback value determines the memory block size 
 3296 **                                              required for the ATUs memory window 2.
 3297 **  11:00       000H                        Reserved
 3298 ***********************************************************************************
 3299 */
 3300 #define     ARCMSR_INBOUND_ATU_LIMIT2_REG                         0x54    /*dword 0x57,0x56,0x55,0x54*/
 3301 /*
 3302 ***********************************************************************************
 3303 **  Inbound ATU Translate Value Register 2 - IATVR2
 3304 **
 3305 **  The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
 3306 **  convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
 3307 **  inbound ATU address translation.
 3308 **  -----------------------------------------------------------------
 3309 **  Bit       Default                       Description
 3310 **  31:12     00000H                        Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 
 3311 **                                                                            This value must be 64-bit aligned on the internal bus. 
 3312 **                                                                              The default address allows the ATU to access the internal 80331 **      **                                                                              memory-mapped registers.
 3313 **  11:00       000H                        Reserved
 3314 ***********************************************************************************
 3315 */
 3316 #define     ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG                       0x58    /*dword 0x5B,0x5A,0x59,0x58*/
 3317 /*
 3318 ***********************************************************************************
 3319 **  Outbound I/O Window Translate Value Register - OIOWTVR
 3320 **
 3321 **  The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
 3322 **  used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a
 3323 **  result of the outbound ATU address translation. 
 3324 **  The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed
 3325 **  length of 64 Kbytes.
 3326 **  -----------------------------------------------------------------
 3327 **  Bit       Default                       Description
 3328 **  31:16     0000H                         Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses.
 3329 **  15:00     0000H                         Reserved
 3330 ***********************************************************************************
 3331 */
 3332 #define     ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG                         0x5C    /*dword 0x5F,0x5E,0x5D,0x5C*/
 3333 /*
 3334 ***********************************************************************************
 3335 **  Outbound Memory Window Translate Value Register 0 -OMWTVR0
 3336 **
 3337 **  The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
 3338 **  address used to convert 80331 internal bus addresses for outbound transactions. This address is
 3339 **  driven on the PCI bus as a result of the outbound ATU address translation. 
 3340 **  The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length
 3341 **  of 64 Mbytes.
 3342 **  -----------------------------------------------------------------
 3343 **  Bit       Default                       Description
 3344 **  31:26       00H                         Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
 3345 **  25:02     00 0000H                      Reserved
 3346 **  01:00      00 2                         Burst Order - This bit field shows the address sequence during a memory burst. 
 3347 **                                                              Only linear incrementing mode is supported.
 3348 ***********************************************************************************
 3349 */
 3350 #define     ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG                    0x60    /*dword 0x63,0x62,0x61,0x60*/
 3351 /*
 3352 ***********************************************************************************
 3353 **  Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
 3354 **
 3355 **  The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
 3356 **  the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
 3357 **  directly address anywhere within the 64-bit host address space. When this register is all-zero, then
 3358 **  a SAC is generated on the PCI bus.
 3359 **  The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed
 3360 **  length of 64 Mbytes.
 3361 **  -----------------------------------------------------------------
 3362 **  Bit       Default                       Description
 3363 **  31:00     0000 0000H                    These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
 3364 ***********************************************************************************
 3365 */
 3366 #define     ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG                    0x64    /*dword 0x67,0x66,0x65,0x64*/
 3367 /*
 3368 ***********************************************************************************
 3369 **  Outbound Memory Window Translate Value Register 1 -OMWTVR1
 3370 **
 3371 **  The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
 3372 **  address used to convert 80331 internal bus addresses for outbound transactions. This address is
 3373 **  driven on the PCI bus as a result of the outbound ATU address translation. 
 3374 **  The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
 3375 **  of 64 Mbytes.
 3376 **  -----------------------------------------------------------------
 3377 **  Bit       Default                       Description
 3378 **  31:26       00H                         Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
 3379 **  25:02     00 0000H                      Reserved
 3380 **  01:00       00 2                        Burst Order - This bit field shows the address sequence during a memory burst. 
 3381 **                                              Only linear incrementing mode is supported.
 3382 ***********************************************************************************
 3383 */
 3384 #define     ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG                    0x68    /*dword 0x6B,0x6A,0x69,0x68*/
 3385 /*
 3386 ***********************************************************************************
 3387 **  Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
 3388 **
 3389 **  The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
 3390 **  the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
 3391 **  directly address anywhere within the 64-bit host address space. When this register is all-zero, then
 3392 **  a SAC is generated on the PCI bus.
 3393 **  The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
 3394 **  of 64 Mbytes.
 3395 **  -----------------------------------------------------------------
 3396 **  Bit       Default                       Description
 3397 **  31:00    0000 0000H                     These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
 3398 ***********************************************************************************
 3399 */
 3400 #define     ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG                    0x6C    /*dword 0x6F,0x6E,0x6D,0x6C*/
 3401 /*
 3402 ***********************************************************************************
 3403 **  Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
 3404 **
 3405 **  The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
 3406 **  upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing
 3407 **  Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
 3408 **  address space. When this register is all-zero, then a SAC is generated on the PCI bus.
 3409 **  -----------------------------------------------------------------
 3410 **  Bit       Default                       Description
 3411 **  31:00    0000 0000H                     These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
 3412 ***********************************************************************************
 3413 */
 3414 #define     ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG                     0x78    /*dword 0x7B,0x7A,0x79,0x78*/
 3415 /*
 3416 ***********************************************************************************
 3417 **  ATU Configuration Register - ATUCR
 3418 **
 3419 **  The ATU Configuration Register controls the outbound address translation for address translation
 3420 **  unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard
 3421 **  timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
 3422 **  interrupt enabling.
 3423 **  -----------------------------------------------------------------
 3424 **  Bit       Default                       Description
 3425 **  31:20       00H                         Reserved
 3426 **  19          0 2                         ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a
 3427 **                      current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read
 3428 **                      transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not
 3429 **                      applicable in the PCI-X mode.
 3430 **  18          0 2                         Direct Addressing Upper 2Gbytes Translation Enable - When set, 
 3431 **                                              with Direct Addressing enabled (bit 7 of the ATUCR set), 
 3432 **                                                      the ATU forwards internal bus cycles with an address between 0000.0040H and
 3433 **                                                              7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
 3434 **                                                                       When clear, no translation occurs.
 3435 **  17          0 2                         Reserved
 3436 **  16          0 2                         SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until
 3437 **                                              cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified.
 3438 **  15          0 2                         ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and
 3439 **                                              discarded the delayed completion transaction within the queue. When clear, no timer has expired.
 3440 **  14:10    00000 2                        Reserved
 3441 **  09          0 2                         SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt
 3442 **                                              when the ATU detects that SERR# was asserted. When clear, 
 3443 **                                                      the Intel XScale core is not interrupted when SERR# is detected.
 3444 **  08          0 2                         Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
 3445 **                                              Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to
 3446 **                                              the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 
 3447 **                                                      the ATUCR.
 3448 **  07:04    0000 2                         Reserved
 3449 **  03          0 2                         ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start
 3450 **                                              BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 
 3451 **                                                      in the ATUBISTR register.
 3452 **  02          0 2                         Reserved
 3453 **  01          0 2                         Outbound ATU Enable - When set, enables the outbound address translation unit.
 3454 **                                              When cleared, disables the outbound ATU.
 3455 **  00          0 2                         Reserved
 3456 ***********************************************************************************
 3457 */
 3458 #define     ARCMSR_ATU_CONFIGURATION_REG                          0x80    /*dword 0x83,0x82,0x81,0x80*/
 3459 /*
 3460 ***********************************************************************************
 3461 **  PCI Configuration and Status Register - PCSR
 3462 **  
 3463 **  The PCI Configuration and Status Register has additional bits for controlling and monitoring
 3464 **  various features of the PCI bus interface.
 3465 **  -----------------------------------------------------------------
 3466 **  Bit       Default                       Description
 3467 **  31:19      0000H                        Reserved
 3468 **  18          0 2                         Detected Address or Attribute Parity Error - set when a parity error is detected during either the address
 3469 **                                      or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error
 3470 **                                      Response bit is cleared. Set under the following conditions:
 3471 **                                      ˇE Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
 3472 **  17:16  Varies with
 3473 **                                                                              external state
 3474 **                                                                              of DEVSEL#,
 3475 **                                                                              STOP#, and
 3476 **                                                                              TRDY#,
 3477 **                                                                              during
 3478 **                                                                              P_RST#
 3479 **                                                                              PCI-X capability - These two bits define the mode of 
 3480 **                                                                              the PCI bus (conventional or PCI-X) as well as the
 3481 **                                                                              operating frequency in the case of PCI-X mode.
 3482 **                                                                              00 - Conventional PCI mode
 3483 **                                                                              01 - PCI-X 66
 3484 **                                                                              10 - PCI-X 100
 3485 **                                                                              11 - PCI-X 133
 3486 **                                                                              As defined by the PCI-X Addendum to the PCI Local Bus Specification,
 3487 **                                                                              Revision 1.0a, the operating
 3488 **                                                                              mode is determined by an initialization pattern on the PCI bus during
 3489 **                                                                              P_RST# assertion:
 3490 **                                                                              DEVSEL# STOP# TRDY# Mode
 3491 **                                                                              Deasserted Deasserted Deasserted Conventional
 3492 **                                                                              Deasserted Deasserted Asserted PCI-X 66
 3493 **                                                                              Deasserted Asserted Deasserted PCI-X 100
 3494 **                                                                              Deasserted Asserted Asserted PCI-X 133
 3495 **                                                                              All other patterns are reserved.
 3496 **  15          0 2
 3497 **                                                                              Outbound Transaction Queue Busy:
 3498 **                                                                                  0=Outbound Transaction Queue Empty
 3499 **                                                                                  1=Outbound Transaction Queue Busy
 3500 **  14          0 2
 3501 **                                                                              Inbound Transaction Queue Busy:
 3502 **                                                                                  0=Inbound Transaction Queue Empty
 3503 **                                                                                  1=Inbound Transaction Queue Busy
 3504 **  13          0 2                         Reserved.
 3505 **  12          0 2                                                             Discard Timer Value - This bit controls the time-out value 
 3506 **                                                                              for the four discard timers attached to the queues holding read data. 
 3507 **                                                         A value of 0 indicates the time-out value is 2 15 clocks. 
 3508 **                                                         A value of 1 indicates the time-out value is 2 10 clocks.
 3509 **  11          0 2                         Reserved.
 3510 **  10      Varies with
 3511 **                                                                              external state
 3512 **                                                                              of M66EN
 3513 **                                                                              during
 3514 **                                                                              P_RST#
 3515 **                                                      Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in
 3516 **                                                                              Conventional PCI mode by the assertion of M66EN during bus initialization.
 3517 **                                                                              When clear, the interface
 3518 **                                                                              has been initialized as a 33 MHz bus.
 3519 **              NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode.
 3520 **  09          0 2                         Reserved
 3521 **  08      Varies with
 3522 **                                                                              external state
 3523 **                                                                              of REQ64#
 3524 **                                                                              during
 3525 **                                                                              P_RST#
 3526 **                                                                              PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
 3527 **                                                                              configured as 64-bit capable by
 3528 **                                                                              the assertion of REQ64# on the rising edge of P_RST#. When set, 
 3529 **                                                                              the PCI interface is configured as
 3530 **                                                                              32-bit only.
 3531 **  07:06      00 2                         Reserved.
 3532 **  05         0 2                                              Reset Internal Bus - This bit controls the reset of the Intel XScale core 
 3533 **                                                              and all units on the internal
 3534 **                                                              bus. In addition to the internal bus initialization, 
 3535 **                                                              this bit triggers the assertion of the M_RST# pin for
 3536 **                                                              initialization of registered DIMMs. When set:
 3537 **                                                              When operating in the conventional PCI mode:
 3538 **                                                              ˇE All current PCI transactions being mastered by the ATU completes, 
 3539 **                                                              and the ATU master interfaces
 3540 **                                                              proceeds to an idle state. No additional transactions is mastered by these units
 3541 **                                                              until the internal bus reset is complete.
 3542 **                                                              ˇE All current transactions being slaved by the ATU on either the PCI bus 
 3543 **                                                              or the internal bus
 3544 **                                                              completes, and the ATU target interfaces proceeds to an idle state. 
 3545 **                                                              All future slave transactions master aborts, 
 3546 **                                                              with the exception of the completion cycle for the transaction that set the Reset
 3547 **                                                              Internal Bus bit in the PCSR.
 3548 **                                                              ˇE When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 
 3549 **                                                              is set, the Intel XScale core is held in reset when the internal bus reset is complete.
 3550 **                                                              ˇE The ATU ignores configuration cycles, and they appears as master aborts for: 32 
 3551 **                                                              Internal Bus clocks.
 3552 **                                                              ˇE The 80331 hardware clears this bit after the reset operation completes.
 3553 **                                                              When operating in the PCI-X mode:
 3554 **                                                              The ATU hardware responds the same as in Conventional PCI-X mode. 
 3555 **                                                              However, this may create a problem in PCI-X mode for split requests in 
 3556 **                                                              that there may still be an outstanding split completion that the
 3557 **                                                              ATU is either waiting to receive (Outbound Request) or initiate 
 3558 **                                                              (Inbound Read Request). For a cleaner
 3559 **                                                              internal bus reset, host software can take the following steps prior 
 3560 **                                                              to asserting Reset Internal bus:
 3561 **                                      1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in
 3562 **                                              the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued.
 3563 **                                      2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction
 3564 **                                              queue busy bits to be clear.
 3565 **                                      3. Set the Reset Internal Bus bit
 3566 **      As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode,
 3567 **      however the user is now assured that the ATU no longer has any pending inbound or outbound split
 3568 **      completion transactions.
 3569 **      NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is
 3570 **      guaranteed that any prior configuration cycles have properly completed since there is only a one
 3571 **      deep transaction queue for configuration transaction requests. The ATU sends the appropriate
 3572 **      Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset.
 3573 **  04      0 2                                                 Bus Master Indicator Enable: Provides software control for the
 3574 **                                                              Bus Master Indicator signal P_BMI used
 3575 **              for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and
 3576 **              central resource/arbiter disabled (BRG_EN =low, ARB_EN=low).
 3577 **  03          Varies with external state of PRIVDEV during
 3578 **                                                      P_RST#
 3579 **                      Private Device Enable - This bit indicates the state of the reset strap which enables the private device
 3580 **                      control mechanism within the PCI-to-PCI Bridge SISR configuration register.
 3581 **                      0=Private Device control Disabled - SISR register bits default to zero
 3582 **                      1=Private Device control Enabled - SISR register bits default to one
 3583 **      02      Varies with external state of RETRY during P_RST#
 3584 **                      Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all
 3585 **                      configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate
 3586 **                      configuration cycles.
 3587 **              The default condition for this bit is based on the external state of the RETRY pin at the rising edge of
 3588 **                      P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is
 3589 **                      low, the bit is cleared.
 3590 **  01          Varies with external state of CORE_RST# during P_RST#
 3591 **                      Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is
 3592 **                      asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is
 3593 **                      being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 
 3594 **                      XScale  core reset.
 3595 **                      The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge
 3596 **                      of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is
 3597 **                      high, the bit is clear.
 3598 **  00          Varies with external state of PRIVMEM during P_RST#
 3599 **                      Private Memory Enable - This bit indicates the state of the reset strap which enables the private device
 3600 **                      control mechanism within the PCI-to-PCI Bridge SDER configuration register.
 3601 **                      0=Private Memory control Disabled - SDER register bit 2 default to zero
 3602 **                      1=Private Memory control Enabled - SDER register bits 2 default to one
 3603 ***********************************************************************************
 3604 */
 3605 #define     ARCMSR_PCI_CONFIGURATION_STATUS_REG                   0x84    /*dword 0x87,0x86,0x85,0x84*/
 3606 /*
 3607 ***********************************************************************************
 3608 **  ATU Interrupt Status Register - ATUISR
 3609 **  
 3610 **  The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
 3611 **  interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit
 3612 **  of the 80331. All bits in this register are Read/Clear.
 3613 **  Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register
 3614 **  (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set
 3615 **  by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The
 3616 **  conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this
 3617 **  register.
 3618 **  Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core.
 3619 **  -----------------------------------------------------------------
 3620 **  Bit       Default                       Description
 3621 **  31:18      0000H                        Reserved
 3622 **  17          0 2                         VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR
 3623 **                                                                                                              register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set,
 3624 **                                                                                                              this bit results in the assertion of the ATU Configure Register Write Interrupt.
 3625 **  16          0 2                         Reserved
 3626 **  15          0 2                         ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register.
 3627 **                                                          When set, this bit results in the assertion of the ATU Configure Register Write Interrupt.
 3628 **  14          0 2                         ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write
 3629 **                                                                                                              occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these
 3630 **                                                                                                              registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU
 3631 **                                                                                                              Configure Register Write Interrupt.
 3632 **  13          0 2                         Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion
 3633 **                                                          Message on the PCI Bus with the Split Completion Error attribute bit set.
 3634 **  12          0 2                         Received Split Completion Error Message - This bit is set when the device receives a Split Completion
 3635 **                                                          Message from the PCI Bus with the Split Completion Error attribute bit set.
 3636 **  11          0 2                         Power State Transition - When the Power State Field of the ATU Power Management Control/Status
 3637 **                                                                                                              Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and
 3638 **                                                                                                              the ATU Power State Transition Interrupt mask bit is cleared, this bit is set.
 3639 **  10          0 2                         P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU.
 3640 **  09          0 2                         Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD
 3641 **                                                                                                              registerˇ¦s Parity Error Response bit is cleared. Set under the following conditions:
 3642 **                                                                                                              ˇE Write Data Parity Error when the ATU is a target (inbound write).
 3643 **                                                                                                              ˇE Read Data Parity Error when the ATU is an initiator (outbound read).
 3644 **                                                                                                              ˇE Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
 3645 **  08          0 2                         ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor
 3646 **                                                                                                              has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR
 3647 **                                                                                                              register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR
 3648 **                                                                                                              register bits 3:0.
 3649 **                                                                                                              Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion
 3650 **                                                                                                              of the ATU Configure Register Write Interrupt.
 3651 **  07          0 2                         Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort.
 3652 **  06:05      00 2                         Reserved.
 3653 **  04          0 2                         P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU.
 3654 **  03          0 2                         PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort.
 3655 **  02          0 2                         PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort.
 3656 **  01          0 2                         PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort.
 3657 **  00          0 2                         PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following
 3658 **                                                                                                              conditions:
 3659 **                                                                                                              ˇE The ATU asserted PERR# itself or the ATU observed PERR# asserted.
 3660 **                                                                                                              ˇE And the ATU acted as the requester for the operation in which the error occurred.
 3661 **                                                                                                              ˇE And the ATUCMD registerˇ¦s Parity Error Response bit is set
 3662 **                                                                                                              ˇE Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
 3663 **                                                                                                              ˇE And the ATUCMD registerˇ¦s Parity Error Response bit is set
 3664 ***********************************************************************************
 3665 */
 3666 #define     ARCMSR_ATU_INTERRUPT_STATUS_REG                       0x88    /*dword 0x8B,0x8A,0x89,0x88*/
 3667 /*
 3668 ***********************************************************************************
 3669 **  ATU Interrupt Mask Register - ATUIMR
 3670 **
 3671 **  The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts
 3672 **  generated by the ATU.
 3673 **  -----------------------------------------------------------------
 3674 **  Bit       Default                       Description
 3675 **  31:15     0 0000H                       Reserved
 3676 **  14        0 2                           VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the
 3677 **                                      ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register.
 3678 **                                      0=Not Masked
 3679 **                                      1=Masked
 3680 **  13        0 2                           Reserved
 3681 **  12        0 2                           Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the
 3682 **                                      ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register
 3683 **                                      except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR.
 3684 **                                                                              0=Not Masked
 3685 **                                                                              1=Masked
 3686 **  11        1 2                           ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and
 3687 **                                      generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the
 3688 **                                                                                                              IABAR1 register or the IAUBAR1 register.
 3689 **                                                                                                              0=Not Masked
 3690 **                                                                                                              1=Masked
 3691 **  10        0 2                           Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and
 3692 **                                      generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message.
 3693 **                                                                                                              0=Not Masked
 3694 **                                                                                                              1=Masked
 3695 **  09        0 2                           Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR
 3696 **                                      and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the
 3697 **                                      PCIXSR being set.
 3698 **                                      0=Not Masked
 3699 **                                      1=Masked
 3700 **  08        1 2                           Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the
 3701 **                                      ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the
 3702 **                                      ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
 3703 **                                                                                                              0=Not Masked
 3704 **                                                                                                              1=Masked
 3705 **  07        0 2                           ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of
 3706 **                                      the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR.
 3707 **                                                                                                              0=Not Masked
 3708 **                                                                                                              1=Masked
 3709 **  06        0 2                           ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the
 3710 **                                      ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set.
 3711 **                                                                                                              0=Not Masked
 3712 **                                                                                                              1=Masked
 3713 **              NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master.
 3714 **  05        0 2                           ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the
 3715 **                                      ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set.
 3716 **                                                                                                              0=Not Masked
 3717 **                                                                                                              1=Masked
 3718 **  04        0 2                           ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error
 3719 **                                      generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set
 3720 **                                                                                                              0=Not Masked
 3721 **                                                                                                              1=Masked
 3722 **  03        0 2                           ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation
 3723 **                                      of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set.
 3724 **                                                                                                              0=Not Masked
 3725 **                                                                                                              1=Masked
 3726 **  02        0 2                           ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation
 3727 **                                      of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set.
 3728 **                                                                                                              0=Not Masked
 3729 **                                                                                                              1=Masked
 3730 **  01        0 2                           ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the
 3731 **                                      ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an
 3732 **                                                                                                              inbound write transaction.
 3733 **                                                                                                              0=SERR# Not Asserted due to error
 3734 **                                                                                                              1=SERR# Asserted due to error
 3735 **  00        0 2                           ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC
 3736 **                                      error) from the memory controller on the internal bus. In conventional mode, this action only occurs
 3737 **                                      during an inbound read transaction where the data phase that was target aborted on the internal bus is
 3738 **                                      actually requested from the inbound read queue.
 3739 **                                                                                                              0=Disconnect with data 
 3740 **                                                                                                              (the data being up to 64 bits of 1ˇ¦s)
 3741 **                                                                                                              1=Target Abort
 3742 **              NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h -
 3743 **                      completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
 3744 **                      independent of the setting of this bit.
 3745 *********************************************************************************** 
 3746 */
 3747 #define     ARCMSR_ATU_INTERRUPT_MASK_REG                         0x8C    /*dword 0x8F,0x8E,0x8D,0x8C*/
 3748 /*
 3749 ***********************************************************************************
 3750 **  Inbound ATU Base Address Register 3 - IABAR3
 3751 **
 3752 **  . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 
 3753 **    of memory addresses where the inbound translation window 3 begins. 
 3754 **  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 3755 **  . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size.
 3756 **  . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 
 3757 **    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 3758 **  Note: 
 3759 **      Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 
 3760 **      IABAR3 is not configured by the host during normal system initialization.
 3761 **  Warning: 
 3762 **    When a non-zero value is not written to IALR3, 
 3763 **                          the user should not set either the Prefetchable Indicator 
 3764 **                                                      or the Type         Indicator for 64 bit addressability.
 3765 **                          This is the default for IABAR3. 
 3766 **  Assuming a non-zero value is written to IALR3,
 3767 **                          the user may set the Prefetchable Indicator 
 3768 **                                        or the Type         Indicator:
 3769 **                                              a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
 3770 **                             when the Prefetchable Indicator is not set, 
 3771 **                             the user should also leave the Type Indicator set for 32 bit addressability.
 3772 **                             This is the default for IABAR3.
 3773 **                                              b. when the Prefetchable Indicator is set, 
 3774 **                             the user should also set the Type Indicator for 64 bit addressability.
 3775 **  -----------------------------------------------------------------
 3776 **  Bit       Default                       Description
 3777 **  31:12     00000H                        Translation Base Address 3 - These bits define the actual location 
 3778 **                                          the translation function is to respond to when addressed from the PCI bus.
 3779 **  11:04        00H                        Reserved.
 3780 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 3781 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 3782 **                                              00 - Memory Window is locatable anywhere in 32 bit address space
 3783 **                                              10 - Memory Window is locatable anywhere in 64 bit address space
 3784 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address.
 3785 **                                                                   The ATU does not occupy I/O space, 
 3786 **                                                                   thus this bit must be zero.
 3787 ***********************************************************************************
 3788 */
 3789 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG                          0x90    /*dword 0x93,0x92,0x91,0x90*/
 3790 /*
 3791 ***********************************************************************************
 3792 **  Inbound ATU Upper Base Address Register 3 - IAUBAR3
 3793 **
 3794 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 3795 **  Together with the Translation Base Address this register defines the actual location
 3796 **  the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 3797 **  The programmed value within the base address register must comply with the PCI programming
 3798 **  requirements for address alignment.
 3799 **  Note: 
 3800 **      When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 
 3801 **      the IAUBAR3 register attributes are read-only. 
 3802 **      This is the default for IABAR3.
 3803 **  -----------------------------------------------------------------
 3804 **  Bit       Default                       Description
 3805 **  31:0      00000H                        Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 
 3806 **                        the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
 3807 ***********************************************************************************
 3808 */
 3809 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG                    0x94    /*dword 0x97,0x96,0x95,0x94*/
 3810 /*
 3811 ***********************************************************************************
 3812 **  Inbound ATU Limit Register 3 - IALR3
 3813 **
 3814 **  Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
 3815 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 3816 **  PCI addresses to internal bus addresses.
 3817 **  The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When
 3818 **  determining block size requirements ˇX as described in Section 3.10.21 ˇX the translation limit
 3819 **  register provides the block size requirements for the base address register. The remaining registers
 3820 **  used for performing address translation are discussed in Section 3.2.1.1.
 3821 **  The 80331 translate value registerˇ¦s programmed value must be naturally aligned with the base
 3822 **  address registerˇ¦s programmed value. The limit register is used as a mask; thus, the lower address
 3823 **  bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
 3824 **  Specification, Revision 2.3 for additional information on programming base address registers.
 3825 **  Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a
 3826 **  one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit
 3827 **  within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3
 3828 **  makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of
 3829 **  this programming scheme is that unless a valid value exists within the IALR3, all writes to the
 3830 **  IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only
 3831 **  register.
 3832 **  -----------------------------------------------------------------
 3833 **  Bit       Default                       Description
 3834 **  31:12     00000H                        Inbound Translation Limit 3 - This readback value determines the memory block size required 
 3835 **                                          for the ATUs memory window 3.
 3836 **  11:00       000H                        Reserved
 3837 ***********************************************************************************
 3838 */
 3839 #define     ARCMSR_INBOUND_ATU_LIMIT3_REG                         0x98    /*dword 0x9B,0x9A,0x99,0x98*/
 3840 /*
 3841 ***********************************************************************************
 3842 **  Inbound ATU Translate Value Register 3 - IATVR3
 3843 **
 3844 **  The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
 3845 **  convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
 3846 **  inbound ATU address translation.
 3847 **  -----------------------------------------------------------------
 3848 **  Bit       Default                       Description
 3849 **  31:12     00000H                        Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 
 3850 **                                                          This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
 3851 **                                                          access the internal 80331 memory-mapped registers.
 3852 **  11:00       000H                        Reserved
 3853 ***********************************************************************************
 3854 */
 3855 #define     ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG                       0x9C    /*dword 0x9F,0x9E,0x9D,0x9C*/
 3856 /*
 3857 ***********************************************************************************
 3858 **  Outbound Configuration Cycle Address Register - OCCAR
 3859 **  
 3860 **  The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
 3861 **  cycle address. The Intel XScale core writes the PCI configuration cycles address which then
 3862 **  enables the outbound configuration read or write. The Intel XScale core then performs a read or
 3863 **  write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the
 3864 **  PCI bus.
 3865 **  Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently
 3866 **  for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
 3867 **  Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
 3868 **  the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears
 3869 **  bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
 3870 **  Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
 3871 **  -----------------------------------------------------------------
 3872 **  Bit       Default                       Description
 3873 **  31:00    0000 0000H                     Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 
 3874 **                                          configuration read or write cycle.
 3875 ***********************************************************************************
 3876 */
 3877 #define     ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG                       0xA4    /*dword 0xA7,0xA6,0xA5,0xA4*/
 3878 /*
 3879 ***********************************************************************************
 3880 **  Outbound Configuration Cycle Data Register - OCCDR
 3881 **
 3882 **  The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write
 3883 **  on the PCI bus. The register is logical rather than physical meaning that it is an address not a
 3884 **  register. The Intel XScale core reads or writes the data registers memory-mapped address to
 3885 **  initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a
 3886 **  configuration write, the data is latched from the internal bus and forwarded directly to the OWQ.
 3887 **  For a read, the data is returned directly from the ORQ to the Intel XScale core and is never
 3888 **  actually entered into the data register (which does not physically exist).
 3889 **  The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value
 3890 **  within the ATU configuration space.
 3891 **  -----------------------------------------------------------------
 3892 **  Bit       Default                       Description
 3893 **  31:00    0000 0000H                     Configuration Cycle Data - These bits define the data used during an outbound configuration read 
 3894 **                                          or write cycle.
 3895 ***********************************************************************************
 3896 */
 3897 #define     ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG                          0xAC    /*dword 0xAF,0xAE,0xAD,0xAC*/
 3898 /*
 3899 ***********************************************************************************
 3900 **  VPD Capability Identifier Register - VPD_CAPID
 3901 **  
 3902 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 3903 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 3904 **  Capability contained in that header. In the case of the 80331, this is the VPD extended capability
 3905 **  with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3.
 3906 **  -----------------------------------------------------------------
 3907 **  Bit       Default                       Description
 3908 **  07:00       03H               Cap_Id - This field with itsˇ¦ 03H value identifies this item in the linked list of Extended Capability
 3909 **                                Headers as being the VPD capability registers.
 3910 ***********************************************************************************
 3911 */
 3912 #define     ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG                      0xB8    /*byte*/
 3913 /*
 3914 ***********************************************************************************
 3915 **  VPD Next Item Pointer Register - VPD_NXTP
 3916 **  
 3917 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 3918 **  Revision 2.3. This register describes the location of the next item in the functionˇ¦s capability list.
 3919 **  For the 80331, this the final capability list, and hence, this register is set to 00H.
 3920 **  -----------------------------------------------------------------
 3921 **  Bit       Default                       Description
 3922 **  07:00       00H               Next_ Item_ Pointer - This field provides an offset into the functionˇ¦s configuration space pointing to the
 3923 **                                next item in the functionˇ¦s capability list. Since the VPD capabilities are the last in the linked list of
 3924 **                                extended capabilities in the 80331, the register is set to 00H.
 3925 ***********************************************************************************
 3926 */
 3927 #define     ARCMSR_VPD_NEXT_ITEM_PTR_REG                          0xB9    /*byte*/
 3928 /*
 3929 ***********************************************************************************
 3930 **  VPD Address Register - VPD_AR
 3931 **
 3932 **  The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
 3933 **  accessed. The register is read/write and the initial value at power-up is indeterminate.
 3934 **  A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use
 3935 **  the Flag setting to determine whether the configuration write was intended to initiate a read or
 3936 **  write of the VPD through the VPD Data Register.
 3937 **  -----------------------------------------------------------------
 3938 **  Bit       Default                       Description
 3939 **  15          0 2          Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage
 3940 **                           component has completed. Please see Section 3.9, ˇ§Vital Product Dataˇ¨ on page 201 for more details on
 3941 **                           how the 80331 handles the data transfer.
 3942 **  14:0       0000H         VPD Address - This register is written to set the DWORD-aligned byte address used to read or write
 3943 **                           Vital Product Data from the VPD storage component.
 3944 ***********************************************************************************
 3945 */
 3946 #define     ARCMSR_VPD_ADDRESS_REG                        0xBA    /*word 0xBB,0xBA*/
 3947 /*
 3948 ***********************************************************************************
 3949 **  VPD Data Register - VPD_DR
 3950 **
 3951 **  This register is used to transfer data between the 80331 and the VPD storage component.
 3952 **  -----------------------------------------------------------------
 3953 **  Bit       Default                       Description
 3954 **  31:00      0000H                        VPD Data - Four bytes are always read or written through this register to/from the VPD storage component.
 3955 ***********************************************************************************
 3956 */
 3957 #define     ARCMSR_VPD_DATA_REG                   0xBC    /*dword 0xBF,0xBE,0xBD,0xBC*/
 3958 /*
 3959 ***********************************************************************************
 3960 **  Power Management Capability Identifier Register -PM_CAPID
 3961 **
 3962 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 3963 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 3964 **  Capability contained in that header. In the case of the 80331, this is the PCI Bus Power
 3965 **  Management extended capability with an ID of 01H as defined by the PCI Bus Power Management
 3966 **  Interface Specification, Revision 1.1.
 3967 **  -----------------------------------------------------------------
 3968 **  Bit       Default                       Description
 3969 **  07:00       01H                         Cap_Id - This field with itsˇ¦ 01H value identifies this item in the linked list of Extended Capability
 3970 **                                          Headers as being the PCI Power Management Registers.
 3971 ***********************************************************************************
 3972 */
 3973 #define     ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG                     0xC0    /*byte*/
 3974 /*
 3975 ***********************************************************************************
 3976 **  Power Management Next Item Pointer Register - PM_NXTP
 3977 **
 3978 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 3979 **  Revision 2.3. This register describes the location of the next item in the functionˇ¦s capability list.
 3980 **  For the 80331, the next capability (MSI capability list) is located at off-set D0H.
 3981 **  -----------------------------------------------------------------
 3982 **  Bit       Default                       Description
 3983 **  07:00       D0H                         Next_ Item_ Pointer - This field provides an offset into the functionˇ¦s configuration space pointing to the
 3984 **                          next item in the functionˇ¦s capability list which in the 80331 is the MSI extended capabilities header.
 3985 ***********************************************************************************
 3986 */
 3987 #define     ARCMSR_POWER_NEXT_ITEM_PTR_REG                        0xC1    /*byte*/
 3988 /*
 3989 ***********************************************************************************
 3990 **  Power Management Capabilities Register - PM_CAP
 3991 **  
 3992 **  Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
 3993 **  Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
 3994 **  information on the capabilities of the ATU function related to power management.
 3995 **  -----------------------------------------------------------------
 3996 **  Bit       Default                       Description
 3997 **  15:11   00000 2                         PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 
 3998 **                                          is not supported by the 80331.
 3999 **  10          0 2                         D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State
 4000 **  9           1 2                         D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State
 4001 **  8:6       000 2                         Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the
 4002 **                                                          3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1
 4003 **  5           0 2                         DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence
 4004 **                                                          following the transition to the D0 uninitialized state.
 4005 **  4           0 2                         Reserved.
 4006 **  3           0 2                         PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 .
 4007 **  2:0       010 2                         Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 
 4008 **                                          Interface Specification, Revision 1.1
 4009 ***********************************************************************************
 4010 */
 4011 #define     ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG                        0xC2    /*word 0xC3,0xC2*/
 4012 /*
 4013 ***********************************************************************************
 4014 **  Power Management Control/Status Register - PM_CSR
 4015 **
 4016 **  Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
 4017 **  Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
 4018 **  interface for the power management extended capability.
 4019 **  -----------------------------------------------------------------
 4020 **  Bit       Default                       Description
 4021 **  15          0 2                         PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not
 4022 **                                          supported by the 80331.
 4023 **  14:9        00H                         Reserved
 4024 **  8           0 2                         PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 
 4025 **                                          generation from any power state.
 4026 **  7:2    000000 2                         Reserved
 4027 **  1:0        00 2                         Power State - This 2-bit field is used both to determine the current power state 
 4028 **                                          of a function and to set the function into a new power state. The definition of the values is:
 4029 **                                                      00 2 - D0
 4030 **                                                      01 2 - D1
 4031 **                                                      10 2 - D2 (Unsupported)
 4032 **                                                      11 2 - D3 hot
 4033 **                                                      The 80331 supports only the D0 and D3 hot states.
 4034 **
 4035 ***********************************************************************************
 4036 */
 4037 #define     ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG                    0xC4    /*word 0xC5,0xC4*/
 4038 /*
 4039 ***********************************************************************************
 4040 **  PCI-X Capability Identifier Register - PX_CAPID
 4041 **  
 4042 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 4043 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 4044 **  Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with
 4045 **  an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
 4046 **  -----------------------------------------------------------------
 4047 **  Bit       Default                       Description
 4048 **  07:00       07H                         Cap_Id - This field with itsˇ¦ 07H value identifies this item in the linked list of Extended Capability
 4049 **                                          Headers as being the PCI-X capability registers.
 4050 ***********************************************************************************
 4051 */
 4052 #define     ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG                         0xE0    /*byte*/
 4053 /*
 4054 ***********************************************************************************
 4055 **  PCI-X Next Item Pointer Register - PX_NXTP
 4056 **  
 4057 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 4058 **  Revision 2.3. This register describes the location of the next item in the functionˇ¦s capability list.
 4059 **  By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults
 4060 **  to 00H.
 4061 **  However, this register may be written to B8H prior to host configuration to include the VPD
 4062 **  capability located at off-set B8H.
 4063 **  Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may
 4064 **  produce unpredictable system behavior.
 4065 **  In order to guarantee that this register is written prior to host configuration, the 80331 must be
 4066 **  initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically,
 4067 **  the Intel XScale core would be enabled to boot immediately following P_RST# assertion in
 4068 **  this case (bit 1 of PCSR), as well. Please see Table 125, ˇ§PCI Configuration and Status Register -
 4069 **  PCSRˇ¨ on page 253 for more details on the 80331 initialization modes.
 4070 **  -----------------------------------------------------------------
 4071 **  Bit       Default                       Description
 4072 **  07:00       00H                         Next_ Item_ Pointer - This field provides an offset into the functionˇ¦s configuration space pointing to the
 4073 **                      next item in the functionˇ¦s capability list. Since the PCI-X capabilities are the last in the linked list of
 4074 **                      extended capabilities in the 80331, the register is set to 00H.
 4075 **                      However, this field may be written prior to host configuration with B8H to extend the list to include the
 4076 **                      VPD extended capabilities header.
 4077 ***********************************************************************************
 4078 */
 4079 #define     ARCMSR_PCIX_NEXT_ITEM_PTR_REG                         0xE1    /*byte*/
 4080 /*
 4081 ***********************************************************************************
 4082 **  PCI-X Command Register - PX_CMD
 4083 **  
 4084 **  This register controls various modes and features of ATU and Message Unit when operating in the
 4085 **  PCI-X mode.
 4086 **  -----------------------------------------------------------------
 4087 **  Bit       Default                       Description
 4088 **  15:7     000000000 2                    Reserved.
 4089 **  6:4        011 2                        Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
 4090 **                      the device is permitted to have outstanding at one time.
 4091 **                      Register Maximum Outstanding
 4092 **                                      0 1
 4093 **                                      1 2
 4094 **                                      2 3
 4095 **                                      3 4
 4096 **                                      4 8
 4097 **                                      5 12
 4098 **                                      6 16
 4099 **                                      7 32
 4100 **  3:2        00 2                         Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
 4101 **                      initiating a Sequence with one of the burst memory read commands.
 4102 **                      Register Maximum Byte Count
 4103 **                                      0 512
 4104 **                                      1 1024
 4105 **                                      2 2048
 4106 **                                      3 4096
 4107 **                                      1 0 2
 4108 **                      Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes
 4109 **                      of Transactions.
 4110 **  0          0 2                          Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to
 4111 **                      recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts
 4112 **                      SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set.
 4113 ***********************************************************************************
 4114 */
 4115 #define     ARCMSR_PCIX_COMMAND_REG                       0xE2    /*word 0xE3,0xE2*/
 4116 /*
 4117 ***********************************************************************************
 4118 **  PCI-X Status Register - PX_SR
 4119 **  
 4120 **  This register identifies the capabilities and current operating mode of ATU, DMAs and Message
 4121 **  Unit when operating in the PCI-X mode.
 4122 **  -----------------------------------------------------------------
 4123 **  Bit       Default                       Description
 4124 **  31:30       00 2                        Reserved
 4125 **  29           0 2                        Received Split Completion Error Message - This bit is set when the device receives a Split Completion
 4126 **                                      Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
 4127 **                                      writes a 1 to this location.
 4128 **                                      0=no Split Completion error message received.
 4129 **                                      1=a Split Completion error message has been received.
 4130 **  28:26      001 2                        Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
 4131 **                                      of the Maximum Memory Read Byte Count field of the PCIXCMD register:
 4132 **                                      DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
 4133 **                                      1 16 512 (Default)
 4134 **                                      2 32 1024
 4135 **                                      2 32 2048
 4136 **                                      2 32 4096
 4137 **  25:23      011 2                        Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions.
 4138 **  22:21       01 2                        Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 
 4139 **                                          to 1024 bytes.
 4140 **  20           1 2                        80331 is a complex device.
 4141 **  19           0 2                        Unexpected Split Completion - This bit is set when an unexpected Split Completion with this deviceˇ¦s
 4142 **                                      Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
 4143 **                                      0=no unexpected Split Completion has been received.
 4144 **                                      1=an unexpected Split Completion has been received.
 4145 **  18           0 2                        Split Completion Discarded - This bit is set when the device discards a Split Completion because the
 4146 **                                      requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
 4147 **                                      Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this
 4148 **                                      location.
 4149 **                                      0=no Split Completion has been discarded.
 4150 **                                      1=a Split Completion has been discarded.
 4151 **              NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read
 4152 **                      Requests with Split Responses (Memory or Register) that has ˇ§read side effects.ˇ¨
 4153 **  17           1 2                        80331 is a 133 MHz capable device.
 4154 **  16           1 2 or P_32BITPCI#     80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 
 4155 **                                      therefore this bit is always set.
 4156 **                      80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 
 4157 **                      use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 
 4158 **                      This strap, by default, identifies the add in card based on 80331 with bridge disabled 
 4159 **                      as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
 4160 **                      0=The bus is 32 bits wide.
 4161 **                      1=The bus is 64 bits wide.
 4162 **  15:8         FFH                        Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus
 4163 **                      segment for the device containing this function. The function uses this number as part of its Requester
 4164 **                      ID and Completer ID. For all devices other than the source bridge, each time the function is addressed
 4165 **                      by a Configuration Write transaction, the function must update this register with the contents of AD[7::0]
 4166 **                      of the attribute phase of the Configuration Write, regardless of which register in the function is
 4167 **                      addressed by the transaction. The function is addressed by a Configuration Write transaction when all of
 4168 **                      the following are true:
 4169 **                      1. The transaction uses a Configuration Write command.
 4170 **                      2. IDSEL is asserted during the address phase.
 4171 **                      3. AD[1::0] are 00b (Type 0 configuration transaction).
 4172 **                      4. AD[10::08] of the configuration address contain the appropriate function number.
 4173 **  7:3          1FH                        Device Number - This register is read for diagnostic purposes only. It indicates the number of the device
 4174 **                      containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a
 4175 **                      Type 0 configuration transaction that is assigned to the device containing this function by the connection
 4176 **                      of the system hardware. The system must assign a device number other than 00h (00h is reserved for
 4177 **                      the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each
 4178 **                      time the function is addressed by a Configuration Write transaction, the device must update this register
 4179 **                      with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which
 4180 **                      register in the function is addressed by the transaction. The function is addressed by a Configuration
 4181 **                      Write transaction when all of the following are true:
 4182 **                      1. The transaction uses a Configuration Write command.
 4183 **                      2. IDSEL is asserted during the address phase.
 4184 **                      3. AD[1::0] are 00b (Type 0 configuration transaction).
 4185 **                      4. AD[10::08] of the configuration address contain the appropriate function number.
 4186 **  2:0        000 2                        Function Number - This register is read for diagnostic purposes only. It indicates the number of this
 4187 **                      function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0
 4188 **                      configuration transaction to which this function responds. The function uses this number as part of its
 4189 **                      Requester ID and Completer ID.
 4190 **
 4191 **************************************************************************
 4192 */
 4193 #define     ARCMSR_PCIX_STATUS_REG                        0xE4    /*dword 0xE7,0xE6,0xE5,0xE4*/
 4194 
 4195 /*
 4196 **************************************************************************
 4197 **                 Inbound Read Transaction
 4198 **  ========================================================================
 4199 **      An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
 4200 **      memory or a 80331 memory-mapped register space. The read transaction is propagated through
 4201 **      the inbound transaction queue (ITQ) and read data is returned through the inbound read queue
 4202 **      (IRQ).
 4203 **      When operating in the conventional PCI mode, all inbound read transactions are processed as
 4204 **      delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
 4205 **      processed as split transactions. The ATUs PCI interface claims the read transaction and forwards
 4206 **      the read request through to the internal bus and returns the read data to the PCI bus. Data flow for
 4207 **      an inbound read transaction on the PCI bus is summarized in the following statements:
 4208 **      ˇE The ATU claims the PCI read transaction when the PCI address is within the inbound
 4209 **      translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
 4210 **      Address Register during DACs) and Inbound Limit Register.
 4211 **      ˇE When operating in the conventional PCI mode, when the ITQ is currently holding transaction
 4212 **      information from a previous delayed read, the current transaction information is compared to
 4213 **      the previous transaction information (based on the setting of the DRC Alias bit in
 4214 **      Section 3.10.39, ˇ§ATU Configuration Register - ATUCRˇ¨ on page 252). When there is a
 4215 **      match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a
 4216 **      match and the data is not available, a Retry is signaled with no other action taken. When there
 4217 **      is not a match and when the ITQ has less than eight entries, capture the transaction
 4218 **      information, signal a Retry and initiate a delayed transaction. When there is not a match and
 4219 **      when the ITQ is full, then signal a Retry with no other action taken.
 4220 **      ˇX When an address parity error is detected, the address parity response defined in
 4221 **      Section 3.7 is used.
 4222 **      ˇE When operating in the conventional PCI mode, once read data is driven onto the PCI bus from
 4223 **      the IRQ, it continues until one of the following is true:
 4224 **      ˇX The initiator completes the PCI transaction. When there is data left unread in the IRQ, the
 4225 **      data is flushed.
 4226 **      ˇX An internal bus Target Abort was detected. In this case, the QWORD associated with the
 4227 **      Target Abort is never entered into the IRQ, and therefore is never returned.
 4228 **      ˇX Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error.
 4229 **      ˇX The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to
 4230 **      the initiator on the last data word available.
 4231 **      ˇE When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
 4232 **      command are latched into the available ITQ and a Split Response Termination is signalled to
 4233 **      the initiator.
 4234 **      ˇE When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
 4235 **      boundary, then the ATU waits until it receives the full byte count from the internal bus target
 4236 **      before returning read data by generating the split completion transaction on the PCI-X bus.
 4237 **      When the read requested crosses at least one 1024 byte boundary, then ATU completes the
 4238 **      transfer by returning data in 1024 byte aligned chunks.
 4239 **      ˇE When operating in the PCI-X mode, once a split completion transaction has started, it
 4240 **      continues until one of the following is true:
 4241 **      ˇX The requester (now the target) generates a Retry Termination, or a Disconnection at Next
 4242 **      ADB (when the requester is a bridge)
 4243 **      ˇX The byte count is satisfied.
 4244 **      ˇX An internal bus Target Abort was detected. The ATU generates a Split Completion
 4245 **      Message (message class=2h - completer error, and message index=81h - target abort) to
 4246 **      inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
 4247 **      Refer to Section 3.7.1.
 4248 **      ˇX An internal bus Master Abort was detected. The ATU generates a Split Completion
 4249 **      Message (message class=2h - completer error, and message index=80h - Master abort) to
 4250 **      inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
 4251 **      Refer to Section 3.7.1
 4252 **      ˇE When operating in the conventional PCI mode, when the master inserts wait states on the PCI
 4253 **      bus, the ATU PCI slave interface waits with no premature disconnects.
 4254 **      ˇE When a data parity error occurs signified by PERR# asserted from the initiator, no action is
 4255 **      taken by the target interface. Refer to Section 3.7.2.5.
 4256 **      ˇE When operating in the conventional PCI mode, when the read on the internal bus is
 4257 **      target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is
 4258 **      based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
 4259 **      target abort is used, when clear, a disconnect is used.
 4260 **      ˇE When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
 4261 **      and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates
 4262 **      a Split Completion Message (message class=2h - completer error, and message index=81h -
 4263 **      internal bus target abort) to inform the requester about the abnormal condition. For the MU
 4264 **      queue ports, the ATU returns either a target abort or a single data phase disconnect depending
 4265 **      on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
 4266 **      transaction is flushed. Refer to Section 3.7.1.
 4267 **      ˇE When operating in the conventional PCI mode, when the transaction on the internal bus
 4268 **      resulted in a master abort, the ATU returns a target abort to inform the requester about the
 4269 **      abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1
 4270 **      ˇE When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
 4271 **      master abort, the ATU generates a Split Completion Message (message class=2h - completer
 4272 **      error, and message index=80h - internal bus master abort) to inform the requester about the
 4273 **      abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1.
 4274 **      ˇE When operating in the PCI-X mode, when the Split Completion transaction completes with
 4275 **      either Master-Abort or Target-Abort, the requester is indicating a failure condition that
 4276 **      prevents it from accepting the completion it requested. In this case, since the Split Request
 4277 **      addresses a location that has no read side effects, the completer must discard the Split
 4278 **      Completion and take no further action.
 4279 **      The data flow for an inbound read transaction on the internal bus is summarized in the following
 4280 **      statements:
 4281 **      ˇE The ATU internal bus master interface requests the internal bus when a PCI address appears in
 4282 **              an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
 4283 **              ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU
 4284 **              always uses conventional PCI ordering rules.
 4285 **      ˇE Once the internal bus is granted, the internal bus master interface drives the translated address
 4286 **              onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated.
 4287 **              When a master abort occurs, the transaction is considered complete and a target abort is loaded
 4288 **              into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI
 4289 **              master has been delivered the target abort).
 4290 **      ˇE Once the translated address is on the bus and the transaction has been accepted, the internal
 4291 **              bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously
 4292 **              received by the IRQ until one of the following is true:
 4293 **      ˇX The full byte count requested by the ATU read request is received. The ATU internal bus
 4294 **          initiator interface performs a initiator completion in this case.
 4295 **      ˇX When operating in the conventional PCI mode, a Target Abort is received on the internal
 4296 **              bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
 4297 **              informed.
 4298 **      ˇX When operating in the PCI-X mode, a Target Abort is received on the internal bus from
 4299 **              the internal bus target. In this case, the transaction is aborted. The ATU generates a Split
 4300 **              Completion Message (message class=2h - completer error, and message index=81h -
 4301 **              target abort) on the PCI bus to inform the requester about the abnormal condition. The
 4302 **              ITQ for this transaction is flushed.
 4303 **      ˇX When operating in the conventional PCI mode, a single data phase disconnection is
 4304 **              received from the internal bus target. When the data has not been received up to the next
 4305 **              QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus.
 4306 **              When not, the bus returns to idle.
 4307 **      ˇX When operating in the PCI-X mode, a single data phase disconnection is received from
 4308 **              the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to
 4309 **              obtain remaining data.
 4310 **      ˇX When operating in the conventional PCI mode, a disconnection at Next ADB is received
 4311 **          from the internal bus target. The bus returns to idle.
 4312 **      ˇX When operating in the PCI-X mode, a disconnection at Next ADB is received from the
 4313 **              internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain
 4314 **              remaining data.
 4315 **              To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
 4316 **              ignore the memory read command (Memory Read, Memory Read Line, and Memory Read
 4317 **              Multiple) when trying to match the current inbound read transaction with data in a DRC queue
 4318 **              which was read previously (DRC on target bus). When the Read Command Alias Bit in the
 4319 **              ATUCR register is set, the ATU does not distinguish the read commands on transactions. For
 4320 **              example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read
 4321 **              on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address
 4322 **              as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return
 4323 **              the read data from the DRC queue and consider the Delayed Read transaction complete. When the
 4324 **              Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
 4325 **              commands did not match, only the address.
 4326 **************************************************************************
 4327 */
 4328 /*
 4329 **************************************************************************
 4330 **                    Inbound Write Transaction
 4331 **========================================================================
 4332 **        An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
 4333 **        memory or a 80331 memory-mapped register.
 4334 **      Data flow for an inbound write transaction on the PCI bus is summarized as:
 4335 **      ˇE The ATU claims the PCI write transaction when the PCI address is within the inbound
 4336 **        translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
 4337 **        Base Address Register during DACs) and Inbound Limit Register.
 4338 **      ˇE When the IWADQ has at least one address entry available and the IWQ has at least one buffer
 4339 **        available, the address is captured and the first data phase is accepted.
 4340 **      ˇE The PCI interface continues to accept write data until one of the following is true:
 4341 **        ˇX The initiator performs a disconnect.
 4342 **        ˇX The transaction crosses a buffer boundary.
 4343 **      ˇE When an address parity error is detected during the address phase of the transaction, the
 4344 **        address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address
 4345 **        parity error response.
 4346 **      ˇE When operating in the PCI-X mode when an attribute parity error is detected, the attribute
 4347 **        parity error mechanism described in Section 3.7.1 is used.
 4348 **      ˇE When a data parity error is detected while accepting data, the slave interface sets the
 4349 **        appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6
 4350 **        for details of the inbound write data parity error response.
 4351 **        Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient
 4352 **        to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus
 4353 **        interface becomes aware of the inbound write. When there are additional write transactions ahead
 4354 **        in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been
 4355 **        satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU
 4356 **        internal master interface. The ATU does not insert target wait states nor do data merging on the PCI
 4357 **        interface, when operating in the PCI mode.
 4358 **        In the PCI-X mode memory writes are always executed as immediate transactions, while
 4359 **        configuration write transactions are processed as split transactions. The ATU generates a Split
 4360 **        Completion Message, (with Message class=0h - Write Completion Class and Message index =
 4361 **        00h - Write Completion Message) once a configuration write is successfully executed.
 4362 **        Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions.
 4363 **        The ATU handles such transactions as independent transactions.
 4364 **        Data flow for the inbound write transaction on the internal bus is summarized as:
 4365 **      ˇE The ATU internal bus master requests the internal bus when IWADQ has at least one entry
 4366 **        with associated data in the IWQ.
 4367 **      ˇE When the internal bus is granted, the internal bus master interface initiates the write
 4368 **        transaction by driving the translated address onto the internal bus. For details on inbound
 4369 **        address translation.
 4370 **      ˇE When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus.
 4371 **        The current transaction is flushed from the queue and SERR# may be asserted on the PCI
 4372 **        interface.
 4373 **      ˇE The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
 4374 **        IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
 4375 **        IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
 4376 **        from the IWQ to the internal bus when data is available and the internal bus interface retains
 4377 **        internal bus ownership.
 4378 **      ˇE The internal bus interface stops transferring data from the current transaction to the internal
 4379 **        bus when one of the following conditions becomes true:
 4380 **      ˇX The internal bus initiator interface loses bus ownership. The ATU internal initiator
 4381 **        terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB
 4382 **        is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
 4383 **        complete the delivery of remaining data using the same sequence ID but with the
 4384 **        modified starting address and byte count.
 4385 **      ˇX A Disconnect at Next ADB is signaled on the internal bus from the internal target. When
 4386 **        the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the
 4387 **        transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to
 4388 **        complete the delivery of remaining data using the same sequence ID but with the
 4389 **        modified starting address and byte count.
 4390 **      ˇX A Single Data Phase Disconnect is signaled on the internal bus from the internal target.
 4391 **        When the transaction in the IWQ needs only a single data phase, the master returns to idle.
 4392 **        When the transaction in the IWQ is not complete, the initiator attempts to reacquire the
 4393 **        bus to complete the delivery of remaining data using the same sequence ID but with the
 4394 **        modified starting address and byte count.
 4395 **      ˇX The data from the current transaction has completed (satisfaction of byte count). An
 4396 **        initiator termination is performed and the bus returns to idle.
 4397 **      ˇX A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
 4398 **        Data is flushed from the IWQ.
 4399 *****************************************************************
 4400 */
 4401 
 4402 
 4403 
 4404 /*
 4405 **************************************************************************
 4406 **               Inbound Read Completions Data Parity Errors
 4407 **========================================================================
 4408 **      As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
 4409 **      When as the completer of a Split Read Request the ATU observes PERR# assertion during the split
 4410 **      completion transaction, the ATU attempts to complete the transaction normally and no further
 4411 **      action is taken.
 4412 **************************************************************************
 4413 */
 4414 
 4415 /*
 4416 **************************************************************************
 4417 **               Inbound Configuration Write Completion Message Data Parity Errors
 4418 **========================================================================
 4419 **  As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
 4420 **  When as the completer of a Configuration (Split) Write Request the ATU observes PERR#
 4421 **  assertion during the split completion transaction, the ATU attempts to complete the transaction
 4422 **  normally and no further action is taken.
 4423 **************************************************************************
 4424 */
 4425 
 4426 /*
 4427 **************************************************************************
 4428 **              Inbound Read Request Data Parity Errors
 4429 **===================== Immediate Data Transfer ==========================
 4430 **  As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes.
 4431 **  Inbound read data parity errors occur when read data delivered from the IRQ is detected as having
 4432 **  bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally
 4433 **  report the error to the system by asserting PERR#. As a target device in this scenario, no action is
 4434 **  required and no error bits are set.
 4435 **=====================Split Response Termination=========================
 4436 **  As a target, the ATU may encounter this error when operating in the PCI-X mode.
 4437 **  Inbound read data parity errors occur during the Split Response Termination. The initiator may
 4438 **  optionally report the error to the system by asserting PERR#. As a target device in this scenario, no
 4439 **  action is required and no error bits are set.
 4440 **************************************************************************
 4441 */
 4442 
 4443 /*
 4444 **************************************************************************
 4445 **              Inbound Write Request Data Parity Errors
 4446 **========================================================================
 4447 **      As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
 4448 **      Data parity errors occurring during write operations received by the ATU may assert PERR# on
 4449 **      the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write
 4450 **      transaction completes or a queue fill condition is reached. Specifically, the following actions with
 4451 **      the given constraints are taken by the ATU:
 4452 **      ˇE PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
 4453 **      following the data phase in which the data parity error is detected on the bus. This is only
 4454 **      done when the Parity Error Response bit in the ATUCMD is set.
 4455 **      ˇE The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 4456 **      actions is taken:
 4457 **      ˇX When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 4458 **      Detected Parity Error bit in the ATUISR. When set, no action.
 4459 ***************************************************************************
 4460 */
 4461 
 4462 
 4463 /*
 4464 ***************************************************************************
 4465 **                 Inbound Configuration Write Request
 4466 **  =====================================================================
 4467 **  As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
 4468 **  ===============================================
 4469 **              Conventional PCI Mode
 4470 **  ===============================================
 4471 **  To allow for correct data parity calculations for delayed write transactions, the ATU delays the
 4472 **  assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a
 4473 **  delayed write transaction (inbound configuration write cycle) can occur in any of the following
 4474 **  parts of the transactions:
 4475 **  ˇE During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
 4476 **  address/command and data for delayed delivery to the internal configuration register.
 4477 **  ˇE During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
 4478 **  of the operation back to the original master.
 4479 **  The 80331 ATU PCI interface has the following responses to a delayed write parity error for
 4480 **  inbound transactions during Delayed Write Request cycles with the given constraints:
 4481 **  ˇE When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
 4482 **  (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the
 4483 **  parity error. The delayed write cycle is not enqueued and forwarded to the internal bus.
 4484 **  When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
 4485 **  transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be
 4486 **  forwarded to the internal bus. PERR# is not asserted.
 4487 **  ˇE The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 4488 **  actions is taken:
 4489 **  ˇX When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 4490 **  Detected Parity Error bit in the ATUISR. When set, no action.
 4491 **  For the original write transaction to be completed, the initiator retries the transaction on the PCI
 4492 **  bus and the ATU returns the status from the internal bus, completing the transaction.
 4493 **  For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and
 4494 **  therefore does not agree with the status being returned from the internal bus (i.e. status being
 4495 **  returned is normal completion) the ATU performs the following actions with the given constraints:
 4496 **  ˇE When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
 4497 **  (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in
 4498 **  the IDWQ remains since the data of retried command did not match the data within the queue.
 4499 **  ˇE The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 4500 **  actions is taken:
 4501 **  ˇX When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 4502 **  Detected Parity Error bit in the ATUISR. When set, no action.
 4503 **  =================================================== 
 4504 **                       PCI-X Mode
 4505 **  ===================================================
 4506 **  Data parity errors occurring during configuration write operations received by the ATU may cause
 4507 **  PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error
 4508 **  occurs, the ATU accepts the write data and complete with a Split Response Termination.
 4509 **  Specifically, the following actions with the given constraints are then taken by the ATU:
 4510 **  ˇE When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks
 4511 **  cycles following the Split Response Termination in which the data parity error is detected on
 4512 **  the bus. When the ATU asserts PERR#, additional actions is taken:
 4513 **  ˇX A Split Write Data Parity Error message (with message class=2h - completer error and
 4514 **  message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
 4515 **  that addresses the requester of the configuration write.
 4516 **  ˇX When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
 4517 **  clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no
 4518 **  action.
 4519 **  ˇX The Split Write Request is not enqueued and forwarded to the internal bus.
 4520 **  ˇE The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 4521 **  actions is taken:
 4522 **  ˇX When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 4523 **  Detected Parity Error bit in the ATUISR. When set, no action.
 4524 **
 4525 ***************************************************************************
 4526 */
 4527 
 4528 /*
 4529 ***************************************************************************
 4530 **                       Split Completion Messages
 4531 **  =======================================================================
 4532 **  As a target, the ATU may encounter this error when operating in the PCI-X mode.
 4533 **  Data parity errors occurring during Split Completion Messages claimed by the ATU may assert
 4534 **  PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
 4535 **  ATU accepts the data and complete normally. Specifically, the following actions with the given
 4536 **  constraints are taken by the ATU:
 4537 **  ˇE PERR# is asserted three clocks cycles following the data phase in which the data parity error
 4538 **  is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD
 4539 **  is set. When the ATU asserts PERR#, additional actions is taken:
 4540 **  ˇX The Master Parity Error bit in the ATUSR is set.
 4541 **  ˇX When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
 4542 **  PCI Master Parity Error bit in the ATUISR. When set, no action.
 4543 **  ˇX When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover
 4544 **  Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken.
 4545 **  When the ATU asserts SERR#, additional actions is taken:
 4546 **  Set the SERR# Asserted bit in the ATUSR.
 4547 **  When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
 4548 **  SERR# Asserted bit in the ATUISR. When set, no action.
 4549 **  When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
 4550 **  SERR# Detected bit in the ATUISR. When clear, no action.
 4551 **  ˇE When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
 4552 **  the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set.
 4553 **  When the ATU sets this bit, additional actions is taken:
 4554 **  ˇX When the ATU Received Split Completion Error Message Interrupt Mask bit in the
 4555 **  ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR.
 4556 **  When set, no action.
 4557 **  ˇE The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 4558 **  actions is taken:
 4559 **  ˇX When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 4560 **  Detected Parity Error bit in the ATUISR. When set, no action.
 4561 **  ˇE The transaction associated with the Split Completion Message is discarded.
 4562 **  ˇE When the discarded transaction was a read, a completion error message (with message
 4563 **  class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
 4564 **  the internal bus of the 80331.
 4565 *****************************************************************************
 4566 */
 4567 
 4568 
 4569 /*
 4570 ******************************************************************************************************
 4571 **                 Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
 4572 **  ==================================================================================================
 4573 **      The Messaging Unit (MU) transfers data between the PCI system and the 80331 
 4574 **  notifies the respective system when new data arrives.
 4575 **      The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation.
 4576 **      window defined by: 
 4577 **                    1.Inbound ATU Base Address Register 0 (IABAR0) 
 4578 **                    2.Inbound ATU Limit Register 0 (IALR0)
 4579 **      All of the Messaging Unit errors are reported in the same manner as ATU errors. 
 4580 **  Error conditions and status can be found in :
 4581 **                                               1.ATUSR 
 4582 **                                               2.ATUISR
 4583 **====================================================================================================
 4584 **     Mechanism        Quantity               Assert PCI Interrupt Signals      Generate I/O Processor Interrupt
 4585 **----------------------------------------------------------------------------------------------------
 4586 **  Message Registers      2 Inbound                   Optional                              Optional
 4587 **                         2 Outbound                
 4588 **----------------------------------------------------------------------------------------------------
 4589 **  Doorbell Registers     1 Inbound                   Optional                              Optional
 4590 **                         1 Outbound  
 4591 **----------------------------------------------------------------------------------------------------
 4592 **  Circular Queues        4 Circular Queues           Under certain conditions              Under certain conditions
 4593 **----------------------------------------------------------------------------------------------------
 4594 **  Index Registers     1004 32-bit Memory Locations   No                                    Optional
 4595 **====================================================================================================
 4596 **     PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
 4597 **====================================================================================================
 4598 **  0000H           Reserved
 4599 **  0004H           Reserved
 4600 **  0008H           Reserved
 4601 **  000CH           Reserved
 4602 **------------------------------------------------------------------------
 4603 **  0010H                       Inbound Message Register 0              ]
 4604 **  0014H                       Inbound Message Register 1              ]
 4605 **  0018H                       Outbound Message Register 0             ]
 4606 **  001CH                       Outbound Message Register 1             ]   4 Message Registers
 4607 **------------------------------------------------------------------------
 4608 **  0020H                       Inbound Doorbell Register               ]
 4609 **  0024H                       Inbound Interrupt Status Register       ]
 4610 **  0028H                       Inbound Interrupt Mask Register         ]
 4611 **  002CH                       Outbound Doorbell Register              ]
 4612 **  0030H                       Outbound Interrupt Status Register      ]
 4613 **  0034H                       Outbound Interrupt Mask Register        ]   2 Doorbell Registers and 4 Interrupt Registers
 4614 **------------------------------------------------------------------------
 4615 **  0038H                       Reserved
 4616 **  003CH                       Reserved
 4617 **------------------------------------------------------------------------
 4618 **  0040H                       Inbound Queue Port                      ]
 4619 **  0044H                       Outbound Queue Port                     ]   2 Queue Ports
 4620 **------------------------------------------------------------------------
 4621 **  0048H                       Reserved
 4622 **  004CH                       Reserved
 4623 **------------------------------------------------------------------------
 4624 **  0050H                                                   ]
 4625 **    :                                                     ]
 4626 **    :      Intel Xscale Microarchitecture Local Memory    ]
 4627 **    :                                                     ]
 4628 **  0FFCH                                                   ]   1004 Index Registers
 4629 *******************************************************************************
 4630 */
 4631 /*
 4632 *****************************************************************************
 4633 **                      Theory of MU Operation
 4634 *****************************************************************************
 4635 **--------------------
 4636 **   inbound_msgaddr0:
 4637 **   inbound_msgaddr1:
 4638 **  outbound_msgaddr0:
 4639 **  outbound_msgaddr1:
 4640 **  .  The MU has four independent messaging mechanisms.
 4641 **     There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 
 4642 **     Each holds a 32-bit value and generates an interrupt when written.
 4643 **--------------------
 4644 **   inbound_doorbell:
 4645 **  outbound_doorbell:
 4646 **  .  The two Doorbell Registers support software interrupts. 
 4647 **     When a bit is set in a Doorbell Register, an interrupt is generated.
 4648 **--------------------
 4649 **  inbound_queueport:
 4650 ** outbound_queueport:
 4651 **
 4652 **
 4653 **  .  The Circular Queues support a message passing scheme that uses 4 circular queues. 
 4654 **     The 4 circular queues are implemented in 80331 local memory. 
 4655 **     Two queues are used for inbound messages and two are used for outbound messages. 
 4656 **     Interrupts may be generated when the queue is written.
 4657 **--------------------
 4658 ** local_buffer 0x0050 ....0x0FFF
 4659 **  .  The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 
 4660 **     When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured.
 4661 **     Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 
 4662 **     Each interrupt generated by the Messaging Unit can be masked.
 4663 **--------------------
 4664 **  .  Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 
 4665 **     with the exception of Multi-DWORD reads to the index registers. 
 4666 **     In Conventional mode: the MU terminates   Multi-DWORD PCI transactions 
 4667 **     (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 
 4668 **     In PCI-X mode       : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 
 4669 **     and the data is returned through split completion transaction(s).
 4670 **     however, when the burst request crosses into or through the range of  offsets 40h to 4Ch 
 4671 **     (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 
 4672 **     In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 
 4673 **     which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written.
 4674 **--------------------
 4675 **  .  All registers needed to configure and control the Messaging Unit are memory-mapped registers.
 4676 **     The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
 4677 **     This PCI address window is used for PCI transactions that access the 80331 local memory.
 4678 **     The  PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register.
 4679 **--------------------
 4680 **  .  From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
 4681 **     The Messaging Unit uses the PCI configuration registers of the ATU for control and status information.
 4682 **     The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register.
 4683 **     The Messaging Unit reports all PCI errors in the ATU Status Register.
 4684 **--------------------
 4685 **  .  Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 
 4686 **     The register interface, message registers, doorbell registers, 
 4687 **     and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 
 4688 **     Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 
 4689 **     The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H.
 4690 **************************************************************************
 4691 */
 4692 /*
 4693 **************************************************************************
 4694 **  Message Registers
 4695 **  ==============================
 4696 **  . Messages can be sent and received by the 80331 through the use of the Message Registers. 
 4697 **  . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor.
 4698 **  . Inbound messages are sent by the host processor and received by the 80331.
 4699 **    Outbound messages are sent by the 80331 and received by the host processor.
 4700 **  . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register.
 4701 **    Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.
 4702 **
 4703 **  Inbound Messages:
 4704 **  -----------------
 4705 **  . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 
 4706 **  . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
 4707 **  . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 
 4708 **    The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 
 4709 **    This is a Read/Clear bit that is set by the MU hardware and cleared by software.
 4710 **    The interrupt is cleared when the Intel XScale core writes a value of 
 4711 **    1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
 4712 **  ------------------------------------------------------------------------
 4713 **  Inbound Message Register - IMRx
 4714 **
 4715 **  . There are two Inbound Message Registers: IMR0 and IMR1. 
 4716 **  . When the IMR register is written, an interrupt to the Intel XScale core may be generated.
 4717 **    The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 
 4718 **    by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
 4719 **  -----------------------------------------------------------------
 4720 **  Bit       Default                       Description
 4721 **  31:00    0000 0000H                     Inbound Message - This is a 32-bit message written by an external PCI agent. 
 4722 **                                                            When written, an interrupt to the Intel XScale core may be generated.
 4723 **************************************************************************
 4724 */
 4725 #define     ARCMSR_MU_INBOUND_MESSAGE_REG0                        0x10    /*dword 0x13,0x12,0x11,0x10*/
 4726 #define     ARCMSR_MU_INBOUND_MESSAGE_REG1                        0x14    /*dword 0x17,0x16,0x15,0x14*/
 4727 /*
 4728 **************************************************************************
 4729 **  Outbound Message Register - OMRx
 4730 **  --------------------------------
 4731 **  There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is
 4732 **  written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
 4733 **  Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound
 4734 **  Interrupt Mask Register.
 4735 **
 4736 **  Bit       Default                       Description
 4737 **  31:00    00000000H                      Outbound Message - This is 32-bit message written by the Intel  XScale  core. When written, an
 4738 **                                                             interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register.
 4739 **************************************************************************
 4740 */
 4741 #define     ARCMSR_MU_OUTBOUND_MESSAGE_REG0                       0x18    /*dword 0x1B,0x1A,0x19,0x18*/
 4742 #define     ARCMSR_MU_OUTBOUND_MESSAGE_REG1                       0x1C    /*dword 0x1F,0x1E,0x1D,0x1C*/
 4743 /*
 4744 **************************************************************************
 4745 **        Doorbell Registers
 4746 **  ==============================
 4747 **  There are two Doorbell Registers: 
 4748 **                                  Inbound Doorbell Register 
 4749 **                                  Outbound Doorbell Register
 4750 **  The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 
 4751 **  The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 
 4752 **  Both Doorbell Registers may generate interrupts whenever a bit in the register is set.
 4753 **
 4754 **  Inbound Doorbells:
 4755 **  ------------------
 4756 **  . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale  core.
 4757 **    An interrupt is generated when any of the bits in the doorbell register is written to a value of 1.
 4758 **    Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 
 4759 **  . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 
 4760 **    The interrupt is recorded in the Inbound Interrupt Status Register.
 4761 **  . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register.
 4762 **    When the mask bit is set for a particular bit, no interrupt is generated for that bit.
 4763 **    The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt
 4764 **    and not the values written to the Inbound Doorbell Register. 
 4765 **    One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
 4766 **  . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 
 4767 **    Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt.
 4768 **  ------------------------------------------------------------------------
 4769 **  Inbound Doorbell Register - IDR
 4770 **
 4771 **  . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 
 4772 **  . Bit 31 is reserved for generating an Error Doorbell interrupt. 
 4773 **    When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 
 4774 **    All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 
 4775 **    when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register.
 4776 **    The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale  core.
 4777 **  ------------------------------------------------------------------------
 4778 **  Bit       Default                       Description
 4779 **  31          0 2                         Error Interrupt - Generate an Error Interrupt to the Intel XScale core.
 4780 **  30:00    00000000H                      Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 
 4781 **                                                             When all bits are clear, do not generate a Normal Interrupt.
 4782 **************************************************************************
 4783 */
 4784 #define     ARCMSR_MU_INBOUND_DOORBELL_REG                        0x20    /*dword 0x23,0x22,0x21,0x20*/
 4785 /*
 4786 **************************************************************************
 4787 **  Inbound Interrupt Status Register - IISR
 4788 **
 4789 **  . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 
 4790 **    It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 
 4791 **    All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 
 4792 **    except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 
 4793 **    these two are routed to the Messaging Unit Error interrupt input. 
 4794 **    The generation of interrupts recorded in the Inbound Interrupt Status Register 
 4795 **    may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 
 4796 **    Some of the bits in this register are Read Only. 
 4797 **    For those bits, the interrupt must be cleared through another register.
 4798 **
 4799 **  Bit       Default                       Description
 4800 **  31:07    0000000H 0 2                   Reserved
 4801 **  06          0 2              Index Register Interrupt - This bit is set by the MU hardware 
 4802 **                               when an Index Register has been written after a PCI transaction.
 4803 **  05          0 2              Outbound Free Queue Full Interrupt - This bit is set 
 4804 **                               when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 
 4805 **                               An Error interrupt is generated for this condition.
 4806 **  04          0 2              Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 
 4807 **                               Once cleared, an interrupt does NOT be generated 
 4808 **                               when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
 4809 **                               Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 
 4810 **                               software must retain the information that the Inbound Post queue status is not empty.
 4811 **          NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller.
 4812 **  03          0 2              Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set.
 4813 **                               To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear.
 4814 **  02          0 2              Inbound Doorbell Interrupt - This bit is set when at least one 
 4815 **                               Normal Interrupt bit in the Inbound Doorbell Register is set.
 4816 **                               To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear.
 4817 **  01          0 2              Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written.
 4818 **  00          0 2              Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written.
 4819 **************************************************************************
 4820 */
 4821 #define     ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG            0x24    /*dword 0x27,0x26,0x25,0x24*/
 4822 #define     ARCMSR_MU_INBOUND_INDEX_INT                      0x40
 4823 #define     ARCMSR_MU_INBOUND_QUEUEFULL_INT                  0x20
 4824 #define     ARCMSR_MU_INBOUND_POSTQUEUE_INT                  0x10         
 4825 #define     ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT             0x08
 4826 #define     ARCMSR_MU_INBOUND_DOORBELL_INT                   0x04
 4827 #define     ARCMSR_MU_INBOUND_MESSAGE1_INT                   0x02
 4828 #define     ARCMSR_MU_INBOUND_MESSAGE0_INT                   0x01
 4829 /*
 4830 **************************************************************************
 4831 **  Inbound Interrupt Mask Register - IIMR
 4832 **
 4833 **  . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 
 4834 **    Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register.
 4835 **    Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 
 4836 **    They only affect the generation of the Intel XScale core interrupt.
 4837 **  ------------------------------------------------------------------------
 4838 **  Bit       Default                       Description
 4839 **  31:07     000000H 0 2                   Reserved
 4840 **  06        0 2               Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 
 4841 **                              when an Index Register has been written after a PCI transaction.
 4842 **  05        0 2               Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 
 4843 **                              when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
 4844 **  04        0 2               Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 
 4845 **                              by the MU hardware when the Inbound Post Queue has been written.
 4846 **  03        0 2               Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 
 4847 **                              when the Error Interrupt bit of the Inbound Doorbell Register is set.
 4848 **  02        0 2               Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 
 4849 **                              when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
 4850 **  01        0 2               Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 
 4851 **                              Interrupt generated by a write to the Inbound Message 1 Register.
 4852 **  00        0 2               Inbound Message 0 Interrupt Mask - When set, 
 4853 **                              this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register.
 4854 **************************************************************************
 4855 */
 4856 #define     ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG              0x28    /*dword 0x2B,0x2A,0x29,0x28*/
 4857 #define     ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE               0x40
 4858 #define     ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE           0x20
 4859 #define     ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE           0x10         
 4860 #define     ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE      0x08
 4861 #define     ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE            0x04
 4862 #define     ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE            0x02
 4863 #define     ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE            0x01
 4864 /*
 4865 **************************************************************************
 4866 **  Outbound Doorbell Register - ODR
 4867 **
 4868 **  The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 
 4869 **  XScale  core to generate PCI interrupts to the host processor by writing to this register. The
 4870 **  generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
 4871 **  Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
 4872 **  The Software Interrupt bits in this register can only be set by the Intel  XScale  core and can only
 4873 **  be cleared by an external PCI agent.
 4874 **  ----------------------------------------------------------------------
 4875 **  Bit       Default                       Description
 4876 **  31          0 2                          Reserved
 4877 **  30          0 2                          Reserved.
 4878 **  29          0 2                          Reserved
 4879 **  28       0000 0000H                      PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 
 4880 **                                                           (P_INTA# with BRG_EN and ARB_EN straps low)
 4881 **                                                           signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 
 4882 **                                                           When this bit is cleared, the P_INTC# interrupt output 
 4883 **                                                           (P_INTA# with BRG_EN and ARB_EN straps low) 
 4884 **                                                           signal is deasserted.
 4885 **  27:00     000 0000H                      Software Interrupts - When any bit is set the P_INTC# interrupt output 
 4886 **                                           (P_INTA# with BRG_EN and ARB_EN straps low) 
 4887 **                                           signal is asserted or a Message-signaled Interrupt is generated (when enabled).
 4888 **                                           When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
 4889 **                                           signal is deasserted.
 4890 **************************************************************************
 4891 */
 4892 #define     ARCMSR_MU_OUTBOUND_DOORBELL_REG                       0x2C    /*dword 0x2F,0x2E,0x2D,0x2C*/
 4893 /*
 4894 **************************************************************************
 4895 **  Outbound Interrupt Status Register - OISR
 4896 **
 4897 **  The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the
 4898 **  status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular
 4899 **  Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
 4900 **  be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the
 4901 **  bits in this register are Read Only. For those bits, the interrupt must be cleared through another
 4902 **  register.
 4903 **  ----------------------------------------------------------------------
 4904 **  Bit       Default                       Description
 4905 **  31:05     000000H 000 2                 Reserved
 4906 **  04        0 2                           PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register.
 4907 **                                                          To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared.
 4908 **  03        0 2                           Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is
 4909 **                                                          cleared when any prefetch data has been read from the Outbound Queue Port.
 4910 **  02        0 2                           Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound
 4911 **                                          Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
 4912 **                                          Doorbell Register must all be clear.
 4913 **  01        0 2                           Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is
 4914 **                                                          written. Clearing this bit clears the interrupt.
 4915 **  00        0 2                           Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is
 4916 **                                                          written. Clearing this bit clears the interrupt.
 4917 **************************************************************************
 4918 */
 4919 #define     ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG           0x30    /*dword 0x33,0x32,0x31,0x30*/
 4920 #define     ARCMSR_MU_OUTBOUND_PCI_INT                        0x10
 4921 #define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INT                      0x08 
 4922 #define     ARCMSR_MU_OUTBOUND_DOORBELL_INT                       0x04 
 4923 #define     ARCMSR_MU_OUTBOUND_MESSAGE1_INT                       0x02 
 4924 #define     ARCMSR_MU_OUTBOUND_MESSAGE0_INT                       0x01 
 4925 /*
 4926 **************************************************************************
 4927 **  Outbound Interrupt Mask Register - OIMR
 4928 **  The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
 4929 **  interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a
 4930 **  hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
 4931 **  interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated.
 4932 **  Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They
 4933 **  only affect the generation of the PCI interrupt.
 4934 **  ----------------------------------------------------------------------
 4935 **  Bit       Default                       Description
 4936 **  31:05     000000H                       Reserved
 4937 **  04          0 2                         PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28)
 4938 **                                                               in the Outbound Doorbell Register is set.
 4939 **  03          0 2                         Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in
 4940 **                                                               the prefetch buffer is valid.
 4941 **  02          0 2                         Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound
 4942 **                                                               Doorbell Register.
 4943 **  01          0 2                         Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt
 4944 **                                                               generated by a write to the Outbound Message 1 Register.
 4945 **  00          0 2                         Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt
 4946 **                                                               generated by a write to the Outbound Message 0 Register.
 4947 **************************************************************************
 4948 */
 4949 #define     ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG                 0x34    /*dword 0x37,0x36,0x35,0x34*/
 4950 #define     ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE                  0x10
 4951 #define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE        0x08 
 4952 #define     ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE             0x04 
 4953 #define     ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE             0x02 
 4954 #define     ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE             0x01 
 4955 #define     ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE                      0x1F 
 4956 /*
 4957 **************************************************************************
 4958 **
 4959 **************************************************************************
 4960 */
 4961 #define     ARCMSR_MU_INBOUND_QUEUE_PORT_REG              0x40    /*dword 0x43,0x42,0x41,0x40*/
 4962 #define     ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG             0x44    /*dword 0x47,0x46,0x45,0x44*/
 4963 /*
 4964 **************************************************************************
 4965 **                          Circular Queues
 4966 **  ======================================================================
 4967 **  The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
 4968 **  this case, inbound and outbound refer to the direction of the flow of posted messages.
 4969 **  Inbound messages are either:
 4970 **                                              ˇE posted messages by other processors for the Intel XScale core to process or
 4971 **                                              ˇE free (or empty) messages that can be reused by other processors.
 4972 **  Outbound messages are either:
 4973 **                                                      ˇE posted messages by the Intel XScale core for other processors to process or
 4974 **                                                      ˇE free (or empty) messages that can be reused by the Intel XScale core.
 4975 **  Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331.
 4976 **  The four Circular Queues are used to pass messages in the following manner. 
 4977 **      . The two inbound queues are used to handle inbound messages 
 4978 **        and the two outbound queues are used to handle  outbound messages. 
 4979 **      . One of the inbound queues is designated the Free queue and it contains inbound free messages. 
 4980 **        The other inbound queue is designated the Post queue and it contains inbound posted messages.
 4981 **        Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 
 4982 **
 4983 **  =============================================================================================================
 4984 **  Circular Queue Summary
 4985 **   _____________________________________________________________________________________________________________
 4986 **  |    Queue Name        |                     Purpose                                |  Action on PCI Interface|
 4987 **  |______________________|____________________________________________________________|_________________________|
 4988 **  |Inbound Post  Queue   |    Queue for inbound messages from other processors        |          Written        |
 4989 **  |                      |     waiting to be processed by the 80331                   |                         |
 4990 **  |Inbound Free  Queue   |    Queue for empty inbound messages from the 80331         |          Read           |
 4991 **  |                      |    available for use by other processors                   |                         |
 4992 **  |Outbound Post Queue   |    Queue for outbound messages from the 80331              |          Read           |
 4993 **  |                      |    that are being posted to the other processors           |                         |
 4994 **  |Outbound Free Queue   |    Queue for empty outbound messages from other processors |          Written        |
 4995 **  |                      |    available for use by the 80331                          |                         |
 4996 **  |______________________|____________________________________________________________|_________________________|
 4997 **
 4998 **  . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
 4999 **    queue and to receive free messages returning from the 80331. 
 5000 **    The host processor posts inbound messages, 
 5001 **    the Intel XScale core receives the posted message and when it is finished with the message,
 5002 **    places it back on the inbound free queue for reuse by the host processor.
 5003 **
 5004 **  The circular queues are accessed by external PCI agents through two port locations in the PCI
 5005 **  address space: 
 5006 **              Inbound Queue Port 
 5007 **          and Outbound Queue Port. 
 5008 **  The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 
 5009 **  The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue.
 5010 **  Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 
 5011 **  does not cause the MU hardware to increment the queue pointers. 
 5012 **  This is treated as when the PCI transaction did not occur. 
 5013 **  The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
 5014 **  ======================================================================================
 5015 **  Overview of Circular Queue Operation
 5016 **  ======================================================================================
 5017 **  . The data storage for the circular queues must be provided by the 80331 local memory.
 5018 **  . The base address of the circular queues is contained in the Queue Base Address Register.
 5019 **    Each entry in the queue is a 32-bit data value. 
 5020 **  . Each read from or write to the queue may access only one queue entry. 
 5021 **  . Multi-DWORD accesses to the circular queues are not allowed. 
 5022 **    Sub-DWORD accesses are promoted to DWORD accesses.
 5023 **  . Each circular queue has a head pointer and a tail pointer. 
 5024 **    The pointers are offsets from the Queue Base Address.
 5025 **  . Writes to a queue occur at the head of the queue and reads occur from the tail. 
 5026 **    The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware.
 5027 **    Which unit maintains the pointer is determined by the writer of the queue. 
 5028 **    More details about the pointers are given in the queue descriptions below. 
 5029 **    The pointers are incremented after the queue access.
 5030 **    Both pointers wrap around to the first address of the circular queue when they reach the circular queue size.
 5031 **
 5032 **  Messaging Unit...
 5033 **
 5034 **  The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions.
 5035 **  . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted.
 5036 **    The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).
 5037 **  . All four queues must be the same size and may be contiguous. 
 5038 **    Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 
 5039 **    The Queue size is determined by the Queue Size field in the MU Configuration Register.
 5040 **  . There is one base address for all four queues. 
 5041 **    It is stored in the Queue Base Address Register (QBAR).
 5042 **    The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 
 5043 **    here shows an example of how the circular queues should be set up based on the
 5044 **    Intelligent I/O (I 2 O) Architecture Specification. 
 5045 **    Other ordering of the circular queues is possible.
 5046 **
 5047 **                              Queue                           Starting Address
 5048 **                              Inbound Free Queue              QBAR
 5049 **                              Inbound Post Queue              QBAR + Queue Size
 5050 **                              Outbound Post Queue             QBAR + 2 * Queue Size
 5051 **                              Outbound Free Queue             QBAR + 3 * Queue Size
 5052 **  ===================================================================================
 5053 **  Inbound Post Queue
 5054 **  ------------------
 5055 **  The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process.
 5056 **  This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 
 5057 **  The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
 5058 **  For a PCI write transaction that accesses the Inbound Queue Port, 
 5059 **  the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register.
 5060 **  When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register.
 5061 **  An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 
 5062 **  The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status.
 5063 **  The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 
 5064 **  The interrupt can be masked by the Inbound Interrupt Mask Register. 
 5065 **  Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 
 5066 **  that the full condition is recognized by the core processor.
 5067 **  In addition, to guarantee that the queue does not get overwritten, 
 5068 **  software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt.
 5069 **  Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 
 5070 **  Only a new message posting the in the inbound queue generates a new interrupt. 
 5071 **  Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 
 5072 **  software must retain the information that the Inbound Post queue status.
 5073 **  From the time that the PCI write transaction is received until the data is written 
 5074 **  in local memory and the Inbound Post Head Pointer Register is incremented, 
 5075 **  any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
 5076 **  The Intel XScale core may read messages from the Inbound Post Queue 
 5077 **  by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 
 5078 **  The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 
 5079 **  When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 
 5080 **  the hardware retries any PCI writes until a slot in the queue becomes available. 
 5081 **  A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer.
 5082 **  ===================================================================================
 5083 **  Inbound Free Queue
 5084 **  ------------------
 5085 **  The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use.
 5086 **  This queue is read from the queue tail by external PCI agents. 
 5087 **  It is written to the queue head by the Intel XScale core. 
 5088 **  The tail pointer is maintained by the MU hardware.
 5089 **  The head pointer is maintained by the Intel XScale core.
 5090 **  For a PCI read transaction that accesses the Inbound Queue Port,
 5091 **  the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 
 5092 **  When the queue is not empty (head and tail pointers are not equal) 
 5093 **  or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned.
 5094 **  When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 
 5095 **  the value of -1 (FFFF.FFFFH) is  returned.
 5096 **  When the queue was not empty and the MU succeeded in returning the data at the tail, 
 5097 **  the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
 5098 **  To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 
 5099 **  The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 
 5100 **  When the PCI read access occurs, the data is read directly from the prefetch register.
 5101 **  The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 
 5102 **  when the head and tail pointers are equal and the queue is empty. 
 5103 **  In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 
 5104 **  the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 
 5105 **  and the Inbound Free Head Pointer Register is written.
 5106 **  The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue.
 5107 **  A prefetch must appear atomic from the perspective of the external PCI agent.
 5108 **  When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed.
 5109 **  The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
 5110 **  local memory location pointed to by the Inbound Free Head Pointer Register. 
 5111 **  The processor must then increment the Inbound Free Head Pointer Register.
 5112 **  ==================================================================================
 5113 **  Outbound Post Queue
 5114 **  -------------------
 5115 **  The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 
 5116 **  core for other processors to process. This queue is read from the queue tail by external PCI agents.
 5117 **  It is written to the queue head by the Intel XScale  core. The tail pointer is maintained by the
 5118 **  MU hardware. The head pointer is maintained by the Intel XScale  core.
 5119 **  For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
 5120 **  data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not
 5121 **  empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head
 5122 **  pointer was last written by software), the data is returned. When the queue is empty (head and tail
 5123 **  pointers are equal and the head pointer was last updated by hardware), the value of -1
 5124 **  (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the
 5125 **  data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
 5126 **  Register.
 5127 **  To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
 5128 **  accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
 5129 **  Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
 5130 **  occurs, the data is read directly from the prefetch register.
 5131 **  The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
 5132 **  and tail pointers are equal and the queue is empty. In order to update the prefetch register when
 5133 **  messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
 5134 **  starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head
 5135 **  Pointer Register is written. The Intel XScale  core needs to update the Outbound Post Head
 5136 **  Pointer Register when it adds messages to the queue.
 5137 **  A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is
 5138 **  started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry
 5139 **  until the prefetch is completed.
 5140 **  A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch
 5141 **  queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound
 5142 **  Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the
 5143 **  interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound
 5144 **  Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register.
 5145 **  The Intel XScale  core may place messages in the Outbound Post Queue by writing the data to
 5146 **  the local memory address in the Outbound Post Head Pointer Register. The processor must then
 5147 **  increment the Outbound Post Head Pointer Register.
 5148 **  ==================================================
 5149 **  Outbound Free Queue
 5150 **  -----------------------
 5151 **  The Outbound Free Queue holds free messages placed there by other processors for the Intel
 5152 **  XScale  core to use. This queue is read from the queue tail by the Intel XScale  core. It is
 5153 **  written to the queue head by external PCI agents. The tail pointer is maintained by the Intel
 5154 **  XScale  core. The head pointer is maintained by the MU hardware.
 5155 **  For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
 5156 **  local memory address in the Outbound Free Head Pointer Register. When the data written to the
 5157 **  Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
 5158 **  Head Pointer Register.
 5159 **  When the head pointer and the tail pointer become equal and the queue is full, the MU may signal
 5160 **  an interrupt to the Intel XScale  core to register the queue full condition. This interrupt is
 5161 **  recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free
 5162 **  Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can
 5163 **  be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the
 5164 **  Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the
 5165 **  core processor.
 5166 **  From the time that a PCI write transaction is received until the data is written in local memory and
 5167 **  the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
 5168 **  access the Outbound Free Queue Port is signalled a retry.
 5169 **  The Intel XScale  core may read messages from the Outbound Free Queue by reading the data
 5170 **  from the local memory address in the Outbound Free Tail Pointer Register. The processor must
 5171 **  then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full,
 5172 **  the hardware must retry any PCI writes until a slot in the queue becomes available.
 5173 **
 5174 **  ==================================================================================
 5175 **  Circular Queue Summary
 5176 **  ----------------------
 5177 **  ________________________________________________________________________________________________________________________________________________
 5178 ** | Queue Name  |  PCI Port     |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by|
 5179 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
 5180 ** |Inbound Post | Inbound Queue |                       |                                    |                          |                          |
 5181 ** |    Queue    |     Port      |          NO           |      Yes, when queue is written    |         MU hardware      |     Intel XScale         |
 5182 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
 5183 ** |Inbound Free | Inbound Queue |                       |                                    |                          |                          |
 5184 ** |    Queue    |     Port      |          NO           |      NO                            |        Intel XScale      |      MU hardware         |
 5185 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
 5186 ** ==================================================================================
 5187 **  Circular Queue Status Summary
 5188 **  ----------------------
 5189 **  ____________________________________________________________________________________________________
 5190 ** |     Queue Name      |  Queue Status  | Head & Tail Pointer |         Last Pointer Update           |
 5191 ** |_____________________|________________|_____________________|_______________________________________|
 5192 ** | Inbound Post Queue  |      Empty     |       Equal         | Tail pointer last updated by software |
 5193 ** |_____________________|________________|_____________________|_______________________________________|
 5194 ** | Inbound Free Queue  |      Empty     |       Equal         | Head pointer last updated by hardware |
 5195 ** |_____________________|________________|_____________________|_______________________________________|
 5196 **************************************************************************
 5197 */
 5198 
 5199 /*
 5200 **************************************************************************
 5201 **       Index Registers
 5202 **  ========================
 5203 **  . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 
 5204 **    These registers are for inbound messages only.
 5205 **    The interrupt is recorded in the Inbound Interrupt Status Register.
 5206 **    The storage for the Index Registers is allocated from the 80331 local memory. 
 5207 **    PCI write accesses to the Index Registers write the data to local memory. 
 5208 **    PCI read accesses to the Index Registers read the data from local memory. 
 5209 **  . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 
 5210 **                                                           to Inbound ATU Translate Value Register + FFFH.
 5211 **  . The address of the first write access is stored in the Index Address Register. 
 5212 **    This register is written during the earliest write access and provides a means to determine which Index Register was written. 
 5213 **    Once updated by the MU, the Index Address Register is not updated until the Index Register 
 5214 **    Interrupt bit in the Inbound Interrupt Status Register is cleared. 
 5215 **  . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access.
 5216 **    Writes by the Intel XScale core to the local memory used by the Index Registers 
 5217 **    does not cause an interrupt and does not update the Index Address Register.
 5218 **  . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
 5219 **************************************************************************
 5220 */
 5221 /*
 5222 **************************************************************************
 5223 **    Messaging Unit Internal Bus Memory Map
 5224 **  =======================================
 5225 **  Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_
 5226 **  FFFF E300H             reserved                                       |
 5227 **    ..                     ..                                           |
 5228 **  FFFF E30CH             reserved                                       |
 5229 **  FFFF E310H             Inbound Message Register 0                     | Available through
 5230 **  FFFF E314H             Inbound Message Register 1                     | ATU Inbound Translation Window
 5231 **  FFFF E318H             Outbound Message Register 0                    |
 5232 **  FFFF E31CH             Outbound Message Register 1                    | or
 5233 **  FFFF E320H             Inbound Doorbell Register                      |
 5234 **  FFFF E324H             Inbound Interrupt Status Register              | must translate PCI address to
 5235 **  FFFF E328H             Inbound Interrupt Mask Register                | the Intel Xscale Core
 5236 **  FFFF E32CH             Outbound Doorbell Register                     | Memory-Mapped Address
 5237 **  FFFF E330H             Outbound Interrupt Status Register             |
 5238 **  FFFF E334H             Outbound Interrupt Mask Register               |
 5239 **  ______________________________________________________________________|________________________________________
 5240 **  FFFF E338H             reserved                                       |
 5241 **  FFFF E33CH             reserved                                       |
 5242 **  FFFF E340H             reserved                                       |
 5243 **  FFFF E344H             reserved                                       |
 5244 **  FFFF E348H             reserved                                       |
 5245 **  FFFF E34CH             reserved                                       |
 5246 **  FFFF E350H             MU Configuration Register                      |
 5247 **  FFFF E354H             Queue Base Address Register                    |
 5248 **  FFFF E358H             reserved                                       |
 5249 **  FFFF E35CH             reserved                                       | must translate PCI address to
 5250 **  FFFF E360H             Inbound Free Head Pointer Register             | the Intel Xscale Core
 5251 **  FFFF E364H             Inbound Free Tail Pointer Register             | Memory-Mapped Address
 5252 **  FFFF E368H             Inbound Post Head pointer Register             |
 5253 **  FFFF E36CH             Inbound Post Tail Pointer Register             |
 5254 **  FFFF E370H             Outbound Free Head Pointer Register            |
 5255 **  FFFF E374H             Outbound Free Tail Pointer Register            |
 5256 **  FFFF E378H             Outbound Post Head pointer Register            |
 5257 **  FFFF E37CH             Outbound Post Tail Pointer Register            |
 5258 **  FFFF E380H             Index Address Register                         |
 5259 **  FFFF E384H             reserved                                       |
 5260 **   ..                       ..                                          |
 5261 **  FFFF E3FCH             reserved                                       |
 5262 **  ______________________________________________________________________|_______________________________________
 5263 **************************************************************************
 5264 */
 5265 /*
 5266 **************************************************************************
 5267 **  MU Configuration Register - MUCR  FFFF.E350H
 5268 **
 5269 **  . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue.
 5270 **  . The Circular Queue Enable bit enables or disables the Circular Queues. 
 5271 **    The Circular Queues are disabled at reset to allow the software to initialize the head 
 5272 **    and tail pointer registers before any PCI accesses to the Queue Ports. 
 5273 **  . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues.
 5274 **  ------------------------------------------------------------------------
 5275 **  Bit       Default                       Description
 5276 **  31:06     000000H 00 2                  Reserved
 5277 **  05:01     00001 2                       Circular Queue Size - This field determines the size of each Circular Queue. 
 5278 **                                      All four queues are the same size.
 5279 **                                      ˇE 00001 2 - 4K Entries (16 Kbytes)
 5280 **                                      ˇE 00010 2 - 8K Entries (32 Kbytes)
 5281 **                                      ˇE 00100 2 - 16K Entries (64 Kbytes)
 5282 **                                      ˇE 01000 2 - 32K Entries (128 Kbytes)
 5283 **                                      ˇE 10000 2 - 64K Entries (256 Kbytes)
 5284 **  00        0 2                       Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular
 5285 **                                      Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores
 5286 **                                      the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when
 5287 **                                      disabled. When set, the Circular Queues are fully enabled.
 5288 **************************************************************************
 5289 */
 5290 #define     ARCMSR_MU_CONFIGURATION_REG                   0xFFFFE350        
 5291 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K              0x0020    
 5292 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K              0x0010
 5293 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K              0x0008   
 5294 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K               0x0004   
 5295 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K               0x0002    
 5296 #define     ARCMSR_MU_CIRCULAR_QUEUE_ENABLE               0x0001        /*0:disable 1:enable*/
 5297 /*
 5298 **************************************************************************
 5299 **  Queue Base Address Register - QBAR
 5300 **
 5301 **  . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues.
 5302 **    The base address is required to be located on a 1 Mbyte address boundary.
 5303 **  . All Circular Queue head and tail pointers are based on the QBAR. 
 5304 **    When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 
 5305 **    Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register.
 5306 **  Warning: 
 5307 **         The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 
 5308 **  ------------------------------------------------------------------------
 5309 **  Bit       Default                       Description
 5310 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 5311 **  19:00     00000H                        Reserved
 5312 **************************************************************************
 5313 */
 5314 #define     ARCMSR_MU_QUEUE_BASE_ADDRESS_REG          0xFFFFE354   
 5315 /*
 5316 **************************************************************************
 5317 **  Inbound Free Head Pointer Register - IFHPR
 5318 **
 5319 **  . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 
 5320 **    the Queue Base Address of the head pointer for the Inbound Free Queue. 
 5321 **    The Head Pointer must be aligned on a DWORD address boundary.
 5322 **    When read, the Queue Base Address is provided in the upper 12 bits of the register. 
 5323 **    Writes to the upper 12 bits of the register are ignored. 
 5324 **    This register is maintained by software.
 5325 **  ------------------------------------------------------------------------
 5326 **  Bit       Default                       Description
 5327 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 5328 **  19:02     0000H 00 2                    Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue.
 5329 **  01:00     00 2                          Reserved
 5330 **************************************************************************
 5331 */
 5332 #define     ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG       0xFFFFE360   
 5333 /*
 5334 **************************************************************************
 5335 **  Inbound Free Tail Pointer Register - IFTPR
 5336 **
 5337 **  . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue
 5338 **    Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a
 5339 **    DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
 5340 **    of the register. Writes to the upper 12 bits of the register are ignored.
 5341 **  ------------------------------------------------------------------------
 5342 **  Bit       Default                       Description
 5343 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 5344 **  19:02     0000H 00 2                    Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue.
 5345 **  01:00     00 2                          Reserved
 5346 **************************************************************************
 5347 */
 5348 #define     ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG       0xFFFFE364  
 5349 /*
 5350 **************************************************************************
 5351 **  Inbound Post Head Pointer Register - IPHPR
 5352 **
 5353 **  . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue
 5354 **    Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on
 5355 **    a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
 5356 **    of the register. Writes to the upper 12 bits of the register are ignored.
 5357 **  ------------------------------------------------------------------------
 5358 **  Bit       Default                       Description
 5359 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 5360 **  19:02     0000H 00 2                    Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue.
 5361 **  01:00     00 2                          Reserved
 5362 **************************************************************************
 5363 */
 5364 #define     ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG       0xFFFFE368
 5365 /*
 5366 **************************************************************************
 5367 **  Inbound Post Tail Pointer Register - IPTPR
 5368 **
 5369 **  . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue
 5370 **    Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a
 5371 **    DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
 5372 **    of the register. Writes to the upper 12 bits of the register are ignored.
 5373 **  ------------------------------------------------------------------------
 5374 **  Bit       Default                       Description
 5375 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 5376 **  19:02     0000H 00 2                    Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue.
 5377 **  01:00     00 2                          Reserved
 5378 **************************************************************************
 5379 */
 5380 #define     ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG       0xFFFFE36C
 5381 /*
 5382 **************************************************************************
 5383 **  Index Address Register - IAR
 5384 **
 5385 **  . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register.
 5386 **    It is written by the MU when the Index Registers are written by a PCI agent.
 5387