The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/arcmsr/arcmsr.h

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    1 /*
    2 ***********************************************************************************************
    3 **        O.S   : FreeBSD
    4 **   FILE NAME  : arcmsr.h
    5 **        BY    : Erich Chen   
    6 **   Description: SCSI RAID Device Driver for 
    7 **                ARECA SATA RAID HOST Adapter[RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set]
    8 ***********************************************************************************************
    9 ************************************************************************
   10 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
   11 **
   12 **     Web site: www.areca.com.tw
   13 **       E-mail: erich@areca.com.tw
   14 **
   15 ** Redistribution and use in source and binary forms,with or without
   16 ** modification,are permitted provided that the following conditions
   17 ** are met:
   18 ** 1. Redistributions of source code must retain the above copyright
   19 **    notice,this list of conditions and the following disclaimer.
   20 ** 2. Redistributions in binary form must reproduce the above copyright
   21 **    notice,this list of conditions and the following disclaimer in the
   22 **    documentation and/or other materials provided with the distribution.
   23 ** 3. The name of the author may not be used to endorse or promote products
   24 **    derived from this software without specific prior written permission.
   25 **
   26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   27 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES
   28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT,
   30 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
   31 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   32 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
   33 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT
   34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
   35 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   36 **************************************************************************
   37 ** $FreeBSD$
   38 */
   39 #define ARCMSR_DRIVER_VERSION                        "Driver Version 1.20.00.12"
   40 #define ARCMSR_SCSI_INITIATOR_ID                                               16
   41 #define ARCMSR_DEV_SECTOR_SIZE                                                512
   42 #define ARCMSR_MAX_XFER_SECTORS                                               256
   43 #define ARCMSR_MAX_XFER_LEN      ARCMSR_MAX_XFER_SECTORS * ARCMSR_DEV_SECTOR_SIZE /*128k*/
   44 #define ARCMSR_MAX_TARGETID                                                    16 /*16 max target id + 1*/
   45 #define ARCMSR_MAX_TARGETLUN                                                    8 /*8*/
   46 #define ARCMSR_MAX_CHIPTYPE_NUM                                                 4
   47 #define ARCMSR_MAX_OUTSTANDING_CMD                                            256
   48 #define ARCMSR_MAX_START_JOB                                                  257
   49 #define ARCMSR_MAX_CMD_PERLUN                          ARCMSR_MAX_OUTSTANDING_CMD
   50 #define ARCMSR_MAX_FREESRB_NUM                                                320
   51 #define ARCMSR_MAX_QBUFFER                                                   4096 /* ioctl QBUFFER */
   52 #define ARCMSR_MAX_SG_ENTRIES                                                  38 /* max 38*/
   53 #define ARCMSR_MAX_ADAPTER                                                      4
   54 /*
   55 *********************************************************************
   56 */
   57 #ifndef TRUE
   58     #define TRUE  1
   59 #endif
   60 #ifndef FALSE
   61     #define FALSE 0
   62 #endif
   63 /*
   64 **********************************************************************************
   65 **
   66 **********************************************************************************
   67 */
   68 #define PCIVendorIDARECA                                             0x17D3     /* Vendor ID    */
   69 #define PCIDeviceIDARC1110                                           0x1110     /* Device ID    */
   70 #define PCIDeviceIDARC1120                                           0x1120 /* Device ID        */
   71 #define PCIDeviceIDARC1130                                           0x1130 /* Device ID        */
   72 #define PCIDeviceIDARC1160                                           0x1160 /* Device ID        */
   73 #define PCIDeviceIDARC1170                                           0x1170 /* Device ID        */
   74 #define PCIDeviceIDARC1210                                           0x1210     /* Device ID    */
   75 #define PCIDeviceIDARC1220                                           0x1220 /* Device ID        */
   76 #define PCIDeviceIDARC1230                                           0x1230 /* Device ID        */
   77 #define PCIDeviceIDARC1260                                           0x1260 /* Device ID        */
   78 #define PCIDeviceIDARC1270                                           0x1270 /* Device ID        */
   79 
   80 #define PCIDevVenIDARC1110                                           0x111017D3 /* Vendor Device ID     */
   81 #define PCIDevVenIDARC1120                                           0x112017D3 /* Vendor Device ID     */
   82 #define PCIDevVenIDARC1130                                           0x113017D3 /* Vendor Device ID     */
   83 #define PCIDevVenIDARC1160                                           0x116017D3 /* Vendor Device ID     */
   84 #define PCIDevVenIDARC1170                                           0x117017D3 /* Vendor Device ID     */
   85 #define PCIDevVenIDARC1210                                           0x121017D3 /* Vendor Device ID     */
   86 #define PCIDevVenIDARC1220                                           0x122017D3 /* Vendor Device ID     */
   87 #define PCIDevVenIDARC1230                                           0x123017D3 /* Vendor Device ID     */
   88 #define PCIDevVenIDARC1260                                           0x126017D3 /* Vendor Device ID     */
   89 #define PCIDevVenIDARC1270                                           0x127017D3 /* Vendor Device ID     */
   90 
   91 #define PCI_BASE_ADDR0                                               0x10
   92 #define PCI_BASE_ADDR1                                               0x14
   93 #define PCI_BASE_ADDR2                                               0x18
   94 #define PCI_BASE_ADDR3                                               0x1C
   95 #define PCI_BASE_ADDR4                                               0x20
   96 #define PCI_BASE_ADDR5                                               0x24
   97 /*
   98 **********************************************************************************
   99 **
  100 **********************************************************************************
  101 */
  102 #define ARCMSR_SCSICMD_IOCTL                                         0x77
  103 #define ARCMSR_CDEVSW_IOCTL                                          0x88
  104 #define ARC_IOCTL_SUCCESS                                            0x00
  105 /*
  106 **********************************************************************************
  107 **
  108 **********************************************************************************
  109 */
  110 /* CAM SIM entry points */
  111 #define arcmsr_ccbsrb_ptr                                                                       spriv_ptr0
  112 #define arcmsr_ccbacb_ptr                                                                       spriv_ptr1
  113 #define dma_addr_hi32(addr)                                                                     (u_int32_t) ((addr>>16)>>16)
  114 #define dma_addr_lo32(addr)                                                                     (u_int32_t) (addr & 0xffffffff)
  115 /*
  116 ************************************************************************
  117 **        IOCTL CONTROL CODE
  118 ************************************************************************
  119 */
  120 typedef struct _CMD_IO_CONTROL
  121 {
  122       u_int32_t HeaderLength;
  123       u_int8_t Signature[8];
  124       u_int32_t Timeout;
  125       u_int32_t ControlCode;
  126       u_int32_t ReturnCode;
  127       u_int32_t Length;
  128 }CMD_IO_CONTROL,*PCMD_IO_CONTROL;
  129 /*
  130 ************************************************************************************************************
  131 **
  132 ************************************************************************************************************
  133 */
  134 typedef struct _CMD_IOCTL_FIELD 
  135 {
  136     CMD_IO_CONTROL                                      cmdioctl; /*ioctl header*/
  137     u_int8_t                                            ioctldatabuffer[1032];/*areca gui program does not accept more than 1031 byte*/
  138 }CMD_IOCTL_FIELD,*PCMD_IOCTL_FIELD;
  139 /*error code for StorPortLogError,ScsiPortLogError*/
  140 #define ARCMSR_IOP_ERROR_ILLEGALPCI             0x0001
  141 #define ARCMSR_IOP_ERROR_VENDORID               0x0002
  142 #define ARCMSR_IOP_ERROR_DEVICEID               0x0002
  143 #define ARCMSR_IOP_ERROR_ILLEGALCDB             0x0003
  144 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR          0x0004
  145 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE        0x0005
  146 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G         0x0006
  147 #define ARCMSR_SYS_ERROR_MEMORY_LACK            0x0007
  148 #define ARCMSR_SYS_ERROR_MEMORY_RANGE           0x0008
  149 #define ARCMSR_SYS_ERROR_DEVICE_BASE            0x0009
  150 #define ARCMSR_SYS_ERROR_PORT_VALIDATE          0x000A
  151 /*DeviceType*/
  152 #define ARECA_SATA_RAID                         0x90000000
  153 /*FunctionCode*/
  154 #define FUNCTION_READ_RQBUFFER                  0x0801
  155 #define FUNCTION_WRITE_WQBUFFER                 0x0802
  156 #define FUNCTION_CLEAR_RQBUFFER                 0x0803
  157 #define FUNCTION_CLEAR_WQBUFFER                 0x0804
  158 #define FUNCTION_CLEAR_ALLQBUFFER               0x0805
  159 #define FUNCTION_REQUEST_RETURNCODE_3F          0x0806
  160 #define FUNCTION_SAY_HELLO                      0x0807
  161 #define FUNCTION_SAY_GOODBYE                    0x0808
  162 #define FUNCTION_FLUSH_ADAPTER_CACHE            0x0809
  163 /* ARECA IO CONTROL CODE*/
  164 #define ARCMSR_IOCTL_READ_RQBUFFER              _IOWR('F', FUNCTION_READ_RQBUFFER, CMD_IOCTL_FIELD)
  165 #define ARCMSR_IOCTL_WRITE_WQBUFFER             _IOWR('F', FUNCTION_WRITE_WQBUFFER, CMD_IOCTL_FIELD)
  166 #define ARCMSR_IOCTL_CLEAR_RQBUFFER             _IOWR('F', FUNCTION_CLEAR_RQBUFFER, CMD_IOCTL_FIELD)
  167 #define ARCMSR_IOCTL_CLEAR_WQBUFFER             _IOWR('F', FUNCTION_CLEAR_WQBUFFER, CMD_IOCTL_FIELD)
  168 #define ARCMSR_IOCTL_CLEAR_ALLQBUFFER           _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, CMD_IOCTL_FIELD)
  169 #define ARCMSR_IOCTL_REQUEST_RETURNCODE_3F      _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, CMD_IOCTL_FIELD)
  170 #define ARCMSR_IOCTL_SAY_HELLO                  _IOWR('F', FUNCTION_SAY_HELLO, CMD_IOCTL_FIELD) 
  171 #define ARCMSR_IOCTL_SAY_GOODBYE                _IOWR('F', FUNCTION_SAY_GOODBYE, CMD_IOCTL_FIELD)
  172 #define ARCMSR_IOCTL_FLUSH_ADAPTER_CACHE        _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, CMD_IOCTL_FIELD)
  173 /* ARECA IOCTL ReturnCode */
  174 #define ARCMSR_IOCTL_RETURNCODE_OK              0x00000001
  175 #define ARCMSR_IOCTL_RETURNCODE_ERROR           0x00000006
  176 #define ARCMSR_IOCTL_RETURNCODE_3F              0x0000003F
  177 /* 
  178 *************************************************************
  179 **   busmaster DMA related defines end
  180 *************************************************************
  181 */
  182 #define     get_min(x,y)            ((x) < (y) ? (x) : (y))
  183 #define     get_max(x,y)            ((x) < (y) ? (y) : (x))
  184 /* 
  185 *************************************************************
  186 **   structure for holding DMA address data 
  187 *************************************************************
  188 */
  189 #define IS_SG64_ADDR                0x01000000 /* bit24 */
  190 typedef struct _SG32ENTRY                             /* size 8 bytes */
  191 {                                              /* length bit 24 == 0                      */
  192     u_int32_t                                           length;    /* high 8 bit == flag,low 24 bit == length */
  193     u_int32_t                                           address;
  194 }SG32ENTRY,*PSG32ENTRY;
  195 typedef struct _SG64ENTRY                             /* size 12 bytes */
  196 {                                              /* length bit 24 == 1                      */
  197         u_int32_t                                       length;    /* high 8 bit == flag,low 24 bit == length */
  198         u_int32_t                                       address;
  199         u_int32_t                                       addresshigh;
  200 }SG64ENTRY,*PSG64ENTRY;
  201 typedef struct _SGENTRY_UNION
  202 {
  203         union
  204         {
  205                 struct _SG32ENTRY           sg32entry;   /* 30h   Scatter gather address  */
  206                 struct _SG64ENTRY           sg64entry;   /* 30h                           */
  207         }u;
  208 }SGENTRY_UNION,PSGENTRY_UNION;
  209 /*
  210 **********************************
  211 **
  212 **********************************
  213 */
  214 typedef struct _QBUFFER
  215 {
  216         u_int32_t     data_len;
  217     u_int8_t      data[124];
  218 }QBUFFER,*PQBUFFER;
  219 /*
  220 ************************************************************************************************
  221 **      FIRMWARE INFO
  222 ************************************************************************************************
  223 */
  224 typedef struct _FIRMWARE_INFO
  225 {
  226         u_int32_t      signature;                /*0,00-03*/
  227         u_int32_t      request_len;              /*1,04-07*/
  228         u_int32_t      numbers_queue;            /*2,08-11*/
  229         u_int32_t      sdram_size;               /*3,12-15*/
  230         u_int32_t      ide_channels;             /*4,16-19*/
  231         char           vendor[40];               /*5,20-59*/
  232         char           model[8];                 /*15,60-67*/
  233         char           firmware_ver[16];         /*17,68-83*/
  234         char           device_map[16];           /*21,84-99*/
  235 }FIRMWARE_INFO,*PFIRMWARE_INFO;
  236 /*
  237 ************************************************************************************************
  238 **                            ARECA FIRMWARE SPEC
  239 ************************************************************************************************
  240 **              Usage of IOP331 adapter
  241 **              (All In/Out is in IOP331's view)
  242 **              1. Message 0 --> InitThread message and retrun code
  243 **              2. Doorbell is used for RS-232 emulation
  244 **                              inDoorBell :    bit0 -- data in ready            (DRIVER DATA WRITE OK)
  245 **                                                              bit1 -- data out has been read   (DRIVER DATA READ OK)
  246 **                              outDooeBell:    bit0 -- data out ready           (IOP331 DATA WRITE OK)
  247 **                                                              bit1 -- data in has been read    (IOP331 DATA READ OK)
  248 **              3. Index Memory Usage
  249 **                      offset 0xf00 : for RS232 out (request buffer)
  250 **                      offset 0xe00 : for RS232 in  (scratch buffer)
  251 **                      offset 0xa00 : for inbound message code message_rwbuffer (driver send to IOP331)
  252 **                      offset 0xa00 : for outbound message code message_rwbuffer (IOP331 send to driver)
  253 **              4. RS-232 emulation
  254 **                      Currently 128 byte buffer is used
  255 **                                1st u_int32_t : Data length (1--124)
  256 **                              Byte 4--127 : Max 124 bytes of data
  257 **              5. PostQ
  258 **              All SCSI Command must be sent through postQ:
  259 **              (inbound queue port)    Request frame must be 32 bytes aligned 
  260 **            #   bit27--bit31 => flag for post ccb 
  261 **                        #   bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb  
  262 **                                                                                                      bit31 : 0 : 256 bytes frame
  263 **                                                                                                                      1 : 512 bytes frame
  264 **                                                                                                      bit30 : 0 : normal request
  265 **                                                                                                                      1 : BIOS request
  266 **                                                  bit29 : reserved
  267 **                                                  bit28 : reserved
  268 **                                                  bit27 : reserved
  269 **  -------------------------------------------------------------------------------
  270 **              (outbount queue port)   Request reply                          
  271 **            #   bit27--bit31 => flag for reply
  272 **                        #   bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 
  273 **                                                                                                      bit31 : must be 0 (for this type of reply)
  274 **                                                                                                      bit30 : reserved for BIOS handshake
  275 **                                                                                                      bit29 : reserved
  276 **                                                                                                      bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
  277 **                                                                                                                      1 : Error, error code in AdapStatus/DevStatus/SenseData
  278 **                                                                                                      bit27 : reserved
  279 **              6. BIOS request
  280 **                      All BIOS request is the same with request from PostQ
  281 **                      Except :
  282 **                              Request frame is sent from configuration space
  283 **                                                              offset: 0x78 : Request Frame (bit30 == 1)
  284 **                                                              offset: 0x18 : writeonly to generate IRQ to IOP331
  285 **                              Completion of request:
  286 **                                                    (bit30 == 0, bit28==err flag)
  287 **              7. Definition of SGL entry (structure)
  288 **              8. Message1 Out - Diag Status Code (????)
  289 **              9. Message0 message code :
  290 **                      0x00 : NOP
  291 **                      0x01 : Get Config ->offset 0xa00 :for outbound message code message_rwbuffer (IOP331 send to driver)
  292 **                                                                                              Signature             0x87974060(4)
  293 **                                                                                              Request len           0x00000200(4)
  294 **                                                                                              numbers of queue      0x00000100(4)
  295 **                                                                                              SDRAM Size            0x00000100(4)-->256 MB
  296 **                                                                                              IDE Channels          0x00000008(4)
  297 **                                                                                              vendor                40 bytes char
  298 **                                                                                              model                  8 bytes char
  299 **                                                                                              FirmVer               16 bytes char
  300 **                                                              Device Map            16 bytes char
  301 **
  302 **                                                              FirmwareVersion DWORD <== Added for checking of new firmware capability
  303 **                      0x02 : Set Config ->offset 0xa00 : for inbound message code message_rwbuffer (driver send to IOP331)
  304 **                                                                                              Signature             0x87974063(4)
  305 **                                                                                              UPPER32 of Request Frame  (4)-->Driver Only
  306 **                      0x03 : Reset (Abort all queued Command)
  307 **                      0x04 : Stop Background Activity
  308 **                      0x05 : Flush Cache
  309 **                      0x06 : Start Background Activity (re-start if background is halted)
  310 **                      0x07 : Check If Host Command Pending (Novell May Need This Function)
  311 **                      0x08 : Set controller time ->offset 0xa00 : for inbound message code message_rwbuffer (driver to IOP331)
  312 **                                                                                      byte 0 : 0xaa <-- signature
  313 **                                                              byte 1 : 0x55 <-- signature
  314 **                                                                                      byte 2 : year (04)
  315 **                                                                                      byte 3 : month (1..12)
  316 **                                                                                      byte 4 : date (1..31)
  317 **                                                                                      byte 5 : hour (0..23)
  318 **                                                                                      byte 6 : minute (0..59)
  319 **                                                                                      byte 7 : second (0..59)
  320 ************************************************************************************************
  321 */
  322 /* signature of set and get firmware config */
  323 #define ARCMSR_SIGNATURE_GET_CONFIG                   0x87974060
  324 #define ARCMSR_SIGNATURE_SET_CONFIG                   0x87974063
  325 /* message code of inbound message register */
  326 #define ARCMSR_INBOUND_MESG0_NOP                      0x00000000
  327 #define ARCMSR_INBOUND_MESG0_GET_CONFIG               0x00000001
  328 #define ARCMSR_INBOUND_MESG0_SET_CONFIG               0x00000002
  329 #define ARCMSR_INBOUND_MESG0_ABORT_CMD                0x00000003
  330 #define ARCMSR_INBOUND_MESG0_STOP_BGRB                0x00000004
  331 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE              0x00000005
  332 #define ARCMSR_INBOUND_MESG0_START_BGRB               0x00000006
  333 #define ARCMSR_INBOUND_MESG0_CHK331PENDING            0x00000007
  334 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER               0x00000008
  335 /* doorbell interrupt generator */
  336 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK           0x00000001
  337 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK            0x00000002
  338 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK          0x00000001
  339 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK           0x00000002
  340 /* srb areca cdb flag */
  341 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE                 0x80000000
  342 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS                  0x40000000
  343 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS                 0x40000000
  344 #define ARCMSR_SRBREPLY_FLAG_ERROR                    0x10000000
  345 /* outbound firmware ok */
  346 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK             0x80000000
  347 /*
  348 ************************************************************************************************
  349 **    size 0x1F8 (504)
  350 ************************************************************************************************
  351 */
  352 typedef struct _ARCMSR_CDB                          
  353 {
  354         u_int8_t                                                Bus;              /* 00h   should be 0            */
  355         u_int8_t                                                TargetID;         /* 01h   should be 0--15        */
  356         u_int8_t                                                LUN;              /* 02h   should be 0--7         */
  357         u_int8_t                                                Function;         /* 03h   should be 1            */
  358 
  359         u_int8_t                                                CdbLength;        /* 04h   not used now           */
  360         u_int8_t                                                sgcount;          /* 05h                          */
  361         u_int8_t                                                Flags;            /* 06h                          */
  362 #define ARCMSR_CDB_FLAG_SGL_BSIZE          0x01   /* bit 0: 0(256) / 1(512) bytes         */
  363 #define ARCMSR_CDB_FLAG_BIOS               0x02   /* bit 1: 0(from driver) / 1(from BIOS) */
  364 #define ARCMSR_CDB_FLAG_WRITE              0x04   /* bit 2: 0(Data in) / 1(Data out)      */
  365 #define ARCMSR_CDB_FLAG_SIMPLEQ            0x00   /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
  366 #define ARCMSR_CDB_FLAG_HEADQ              0x08
  367 #define ARCMSR_CDB_FLAG_ORDEREDQ           0x10
  368         u_int8_t                                                Reserved1;        /* 07h                             */
  369 
  370         u_int32_t                                               Context;          /* 08h   Address of this request */
  371         u_int32_t                                               DataLength;       /* 0ch   not used now            */
  372 
  373         u_int8_t                                                Cdb[16];          /* 10h   SCSI CDB                */
  374         /*
  375         ********************************************************
  376         **Device Status : the same from SCSI bus if error occur 
  377         ** SCSI bus status codes.
  378         ********************************************************
  379         */
  380         u_int8_t                                                DeviceStatus;     /* 20h   if error                */
  381 #define SCSISTAT_GOOD                           0x00
  382 #define SCSISTAT_CHECK_CONDITION                0x02
  383 #define SCSISTAT_CONDITION_MET                  0x04
  384 #define SCSISTAT_BUSY                           0x08
  385 #define SCSISTAT_INTERMEDIATE                   0x10
  386 #define SCSISTAT_INTERMEDIATE_COND_MET          0x14
  387 #define SCSISTAT_RESERVATION_CONFLICT           0x18
  388 #define SCSISTAT_COMMAND_TERMINATED             0x22
  389 #define SCSISTAT_QUEUE_FULL                     0x28
  390 #define ARCMSR_DEV_SELECT_TIMEOUT           0xF0
  391 #define ARCMSR_DEV_ABORTED                  0xF1
  392 #define ARCMSR_DEV_INIT_FAIL                0xF2
  393 
  394         u_int8_t                                                SenseData[15];    /* 21h   output                  */        
  395 
  396         union
  397         {
  398                 struct _SG32ENTRY                   sg32entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h   Scatter gather address  */
  399                 struct _SG64ENTRY                   sg64entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h                           */
  400         } u;
  401 }ARCMSR_CDB,*PARCMSR_CDB;
  402 /*
  403 *********************************************************************
  404 **                   Command Control Block (SrbExtension)
  405 ** SRB must be not cross page boundary,and the order from offset 0
  406 **         structure describing an ATA disk request
  407 **             this SRB length must be 32 bytes boundary
  408 *********************************************************************
  409 */
  410 typedef struct _SRB 
  411 {
  412         ARCMSR_CDB                                 arcmsr_cdb;              /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
  413         u_int32_t                               cdb_shifted_phyaddr;     /* 504-507 */
  414     u_int32_t                               reserved1;               /* 508-511*/
  415         /*  ======================512+32 bytes============================  */
  416 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__)
  417                 union ccb *                        pccb;                    /* 512-515 516-519 pointer of freebsd scsi command */
  418                 struct _ACB *                      pACB;                    /* 520-523 524-527 */
  419                 bus_dmamap_t                       dmamap;                  /* 528-531 532-535 */
  420                 u_int16_t                                          srb_flags;               /* 536-537 */
  421         #define         SRB_FLAG_READ                   0x0000
  422         #define         SRB_FLAG_WRITE                  0x0001
  423         #define         SRB_FLAG_ERROR                  0x0002
  424         #define         SRB_FLAG_FLUSHCACHE             0x0004
  425         #define         SRB_FLAG_MASTER_ABORTED     0x0008
  426                 u_int16_t                           startdone;               /* 538-539 */
  427         #define         ARCMSR_SRB_DONE                 0x0000
  428         #define         ARCMSR_SRB_START                0x55AA
  429         #define         ARCMSR_SRB_ABORTED              0xAA55
  430         #define         ARCMSR_SRB_ILLEGAL              0xFFFF
  431             u_int32_t                           reserved2;               /* 540-543 */
  432 #else
  433                 union ccb *                        pccb;                    /* 512-515 pointer of freebsd scsi command */
  434                 struct _ACB *                      pACB;                    /* 516-519 */
  435                 bus_dmamap_t                       dmamap;                  /* 520-523 */
  436                 u_int16_t                                          srb_flags;               /* 524-525 */
  437         #define         SRB_FLAG_READ                   0x0000
  438         #define         SRB_FLAG_WRITE                  0x0001
  439         #define         SRB_FLAG_ERROR                  0x0002
  440         #define         SRB_FLAG_FLUSHCACHE             0x0004
  441         #define         SRB_FLAG_MASTER_ABORTED     0x0008
  442                 u_int16_t                           startdone;               /* 526-527 */
  443         #define         ARCMSR_SRB_DONE                 0x0000
  444         #define         ARCMSR_SRB_START                0x55AA
  445         #define         ARCMSR_SRB_ABORTED              0xAA55
  446         #define         ARCMSR_SRB_ILLEGAL              0xFFFF
  447                 u_int32_t                           reserved2[4];            /* 528-531 532-535 536-539 540-543 */
  448 #endif
  449     /*  ==========================================================  */
  450 }SRB,*PSRB;
  451 /*
  452 *********************************************************************
  453 **                 Adapter Control Block
  454 ** 
  455 *********************************************************************
  456 */
  457 typedef struct _ACB
  458 {
  459         bus_space_tag_t                             btag;
  460         bus_space_handle_t                          bhandle;
  461         bus_dma_tag_t                       parent_dmat;
  462         bus_dma_tag_t                               buffer_dmat;                          /* dmat for buffer I/O */  
  463         bus_dma_tag_t                       srb_dmat;                             /* dmat for freesrb */
  464         bus_dmamap_t                        srb_dmamap;
  465         device_t                                    pci_dev;
  466 #if __FreeBSD_version < 503000
  467         dev_t                           ioctl_dev;
  468 #else
  469         struct cdev *                   ioctl_dev;
  470 #endif
  471         int                                                 pci_unit;
  472 
  473         struct resource *               sys_res_arcmsr;
  474     struct resource *               irqres;
  475         void *                          ih;                                    /* interrupt handle */
  476 
  477         /* Hooks into the CAM XPT */
  478         struct                          cam_sim *psim;
  479         struct                          cam_path *ppath;
  480     u_int8_t *                      uncacheptr;
  481     unsigned long                   vir2phy_offset;                        /* Offset is used in making arc cdb physical to virtual calculations */
  482     u_int32_t                       outbound_int_enable;
  483 
  484         struct _MU *                    pmu;                                   /* message unit ATU inbound base address0 */
  485 
  486         u_int8_t                                adapter_index;                         /*  */
  487         u_int8_t                                        irq;            
  488         u_int16_t                               acb_flags;                             /*  */
  489 #define ACB_F_SCSISTOPADAPTER         0x0001
  490 #define ACB_F_MSG_STOP_BGRB           0x0002                               /* stop RAID background rebuild */
  491 #define ACB_F_MSG_START_BGRB          0x0004                               /* stop RAID background rebuild */
  492 #define ACB_F_IOPDATA_OVERFLOW        0x0008                               /* iop ioctl data rqbuffer overflow */
  493 #define ACB_F_IOCTL_WQBUFFER_CLEARED  0x0010                               /* ioctl clear wqbuffer */
  494 #define ACB_F_IOCTL_RQBUFFER_CLEARED  0x0020                               /* ioctl clear rqbuffer */
  495 #define ACB_F_BUS_RESET               0x0040
  496 #define ACB_F_IOP_INITED              0x0080                               /* iop init */
  497 #define ACB_F_MAPFREESRB_FAILD            0x0200                               /* arcmsr_map_freesrb faild */
  498 
  499     struct _SRB *                   psrbwait2go[ARCMSR_MAX_OUTSTANDING_CMD];
  500         u_int32_t                       srbwait2gocount;
  501     u_int32_t                       srboutstandingcount;
  502 
  503         struct _SRB *                   psrb_pool[ARCMSR_MAX_FREESRB_NUM];     /* serial srb pointer array */
  504         struct _SRB *                   psrbringQ[ARCMSR_MAX_FREESRB_NUM];     /* working srb pointer array */
  505         u_int32_t                       srb_doneindex;                         /* done srb array index */
  506     u_int32_t                       srb_startindex;                        /* start srb array index  */
  507   
  508         u_int8_t                        rqbuffer[ARCMSR_MAX_QBUFFER];          /* data collection buffer for read from 80331 */
  509         u_int32_t                       rqbuf_firstindex;                      /* first of read buffer  */
  510     u_int32_t                       rqbuf_lastindex;                       /* last of read buffer   */
  511 
  512     u_int8_t                        wqbuffer[ARCMSR_MAX_QBUFFER];          /* data collection buffer for write to 80331  */
  513         u_int32_t                       wqbuf_firstindex;                      /* first of write buffer */
  514     u_int32_t                       wqbuf_lastindex;                       /* last of write buffer  */
  515 
  516         u_int8_t                        devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
  517 #define ARECA_RAID_GONE               0x55
  518 #define ARECA_RAID_GOOD               0xaa
  519         u_int32_t                               num_resets;
  520         u_int32_t                           num_aborts;
  521         u_int32_t                       firm_request_len;                      /*1,04-07*/
  522         u_int32_t                       firm_numbers_queue;                    /*2,08-11*/
  523         u_int32_t                       firm_sdram_size;                       /*3,12-15*/
  524         u_int32_t                       firm_ide_channels;                     /*4,16-19*/
  525         char                            firm_model[12];                        /*15,60-67*/
  526         char                            firm_version[20];                      /*17,68-83*/
  527 }ACB,*PACB;/* HW_DEVICE_EXTENSION */
  528 /*
  529 *************************************************************
  530 *************************************************************
  531 */
  532 typedef struct _SENSE_DATA 
  533 {
  534     u_int8_t                                            ErrorCode:7;
  535     u_int8_t                                            Valid:1;
  536     u_int8_t                                            SegmentNumber;
  537     u_int8_t                                            SenseKey:4;
  538     u_int8_t                                            Reserved:1;
  539     u_int8_t                                            IncorrectLength:1;
  540     u_int8_t                                            EndOfMedia:1;
  541     u_int8_t                                            FileMark:1;
  542     u_int8_t                                            Information[4];
  543     u_int8_t                                            AdditionalSenseLength;
  544     u_int8_t                                            CommandSpecificInformation[4];
  545     u_int8_t                                            AdditionalSenseCode;
  546     u_int8_t                                            AdditionalSenseCodeQualifier;
  547     u_int8_t                                            FieldReplaceableUnitCode;
  548     u_int8_t                                            SenseKeySpecific[3];
  549 }SENSE_DATA, *PSENSE_DATA;
  550 /* 
  551 **********************************
  552 **  Peripheral Device Type definitions 
  553 **********************************
  554 */
  555 #define SCSI_DASD                     0x00         /* Direct-access Device         */
  556 #define SCSI_SEQACESS             0x01     /* Sequential-access device */
  557 #define SCSI_PRINTER              0x02     /* Printer device               */
  558 #define SCSI_PROCESSOR            0x03     /* Processor device             */
  559 #define SCSI_WRITEONCE            0x04     /* Write-once device            */
  560 #define SCSI_CDROM                    0x05         /* CD-ROM device                    */
  561 #define SCSI_SCANNER              0x06     /* Scanner device               */
  562 #define SCSI_OPTICAL              0x07     /* Optical memory device        */
  563 #define SCSI_MEDCHGR              0x08     /* Medium changer device        */
  564 #define SCSI_COMM                     0x09         /* Communications device        */
  565 #define SCSI_NODEV                    0x1F         /* Unknown or no device type*/
  566 /*
  567 ************************************************************************************************************
  568 **                                       @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  569 **                                                        80331 PCI-to-PCI Bridge
  570 **                                                        PCI Configuration Space 
  571 **                              
  572 **                                       @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  573 **                                                          Programming Interface
  574 **                                                        ========================
  575 **                                          Configuration Register Address Space Groupings and Ranges
  576 **                                       =============================================================
  577 **                                               Register Group                      Configuration  Offset
  578 **                                       -------------------------------------------------------------
  579 **                                          Standard PCI Configuration                      00-3Fh
  580 **                                       -------------------------------------------------------------
  581 **                                           Device Specific Registers                      40-A7h
  582 **                                       -------------------------------------------------------------
  583 **                                                 Reserved                                 A8-CBh
  584 **                                       -------------------------------------------------------------
  585 **                                            Enhanced Capability List                      CC-FFh
  586 ** ==========================================================================================================
  587 **                         Standard PCI [Type 1] Configuration Space Address Map
  588 ** **********************************************************************************************************
  589 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              |   Configu-ration Byte Offset
  590 ** ----------------------------------------------------------------------------------------------------------
  591 ** |                    Device ID                    |                     Vendor ID                      | 00h
  592 ** ----------------------------------------------------------------------------------------------------------
  593 ** |                 Primary Status                  |                  Primary Command                   | 04h
  594 ** ----------------------------------------------------------------------------------------------------------
  595 ** |                   Class Code                                             |        RevID              | 08h
  596 ** ----------------------------------------------------------------------------------------------------------
  597 ** |        reserved        |      Header Type       |      Primary MLT       |      Primary CLS          | 0Ch
  598 ** ----------------------------------------------------------------------------------------------------------
  599 ** |                                             Reserved                                                 | 10h
  600 ** ----------------------------------------------------------------------------------------------------------
  601 ** |                                             Reserved                                                 | 14h
  602 ** ----------------------------------------------------------------------------------------------------------
  603 ** |     Secondary MLT      | Subordinate Bus Number |  Secondary Bus Number  |     Primary Bus Number    | 18h
  604 ** ----------------------------------------------------------------------------------------------------------
  605 ** |                 Secondary Status                |       I/O Limit        |        I/O Base           | 1Ch
  606 ** ----------------------------------------------------------------------------------------------------------
  607 ** |      Non-prefetchable Memory Limit Address      |       Non-prefetchable Memory Base Address         | 20h
  608 ** ----------------------------------------------------------------------------------------------------------
  609 ** |        Prefetchable Memory Limit Address        |           Prefetchable Memory Base Address         | 24h
  610 ** ----------------------------------------------------------------------------------------------------------
  611 ** |                          Prefetchable Memory Base Address Upper 32 Bits                              | 28h
  612 ** ----------------------------------------------------------------------------------------------------------
  613 ** |                          Prefetchable Memory Limit Address Upper 32 Bits                             | 2Ch
  614 ** ----------------------------------------------------------------------------------------------------------
  615 ** |             I/O Limit Upper 16 Bits             |                 I/O Base Upper 16                  | 30h
  616 ** ----------------------------------------------------------------------------------------------------------
  617 ** |                                Reserved                                  |   Capabilities Pointer    | 34h
  618 ** ----------------------------------------------------------------------------------------------------------
  619 ** |                                             Reserved                                                 | 38h
  620 ** ----------------------------------------------------------------------------------------------------------
  621 ** |                   Bridge Control                |  Primary Interrupt Pin | Primary Interrupt Line    | 3Ch
  622 **=============================================================================================================
  623 */
  624 /*
  625 **=============================================================================================================
  626 **  0x03-0x00 : 
  627 ** Bit       Default             Description
  628 **31:16       0335h            Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
  629 **                             ID is unique per product speed as indicated.
  630 **15:00       8086h            Vendor ID (VID): 16-bit field which indicates that Intel is the vendor.
  631 **=============================================================================================================
  632 */
  633 #define     ARCMSR_PCI2PCI_VENDORID_REG                  0x00    /*word*/
  634 #define     ARCMSR_PCI2PCI_DEVICEID_REG                  0x02    /*word*/
  635 /*
  636 **==============================================================================
  637 **  0x05-0x04 : command register 
  638 ** Bit       Default                           Description
  639 **15:11        00h                                           Reserved
  640 ** 10          0                                           Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 
  641 **                                                                            The bridge does not support interrupts.
  642 ** 09          0                                                 FB2B Enable: Enables/Disables the generation of fast back to back transactions on the primary bus. 
  643 **                                                                            The bridge does not generate fast back to back transactions on the primary bus.
  644 ** 08          0                                          SERR# Enable (SEE): Enables primary bus SERR# assertions.
  645 **                                                                            0=The bridge does not assert P_SERR#.
  646 **                                                                            1=The bridge may assert P_SERR#, subject to other programmable criteria.
  647 ** 07          0                                    Wait Cycle Control (WCC): Always returns 0bzero indicating that bridge does not perform address or data stepping,
  648 ** 06          0                                 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
  649 **                                                                            0=When a data parity error is detected bridge does not assert S_PERR#. 
  650 **                                                                                Also bridge does not assert P_SERR# in response to a detected address or attribute parity error.
  651 **                                                                            1=When a data parity error is detected bridge asserts S_PERR#. 
  652 **                                                                                The bridge also asserts P_SERR# (when enabled globally via bit(8) of this register) in response to a detected address or attribute parity error.
  653 ** 05          0                  VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 
  654 **                                                                    VGA palette write transactions are I/O transactions whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
  655 **                                                                    P_AD[15:10] are not decoded (i.e. aliases are claimed), or are fully decoding (i.e., must be all 0's depending upon the VGA aliasing bit in the Bridge Control Register, offset 3Eh.
  656 **                                                                    P_AD[31:16] equal to 0000h
  657 **                                                                    0=The bridge ignores VGA palette write transactions, unless decoded by the standard I/O address range window.
  658 **                                                                    1=The bridge responds to VGA palette write transactions with medium DEVSEL# timing and forwards them to the secondary bus.
  659 ** 04          0   Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 
  660 **                                                            MWI transactions targeting resources on the opposite side of the bridge, however, are forwarded as MWI transactions.
  661 ** 03          0                  Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 
  662 **                                                            This bit is read only and always returns 0 when read
  663 ** 02          0                     Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
  664 **                                                            Initiation of configuration transactions is not affected by the state of this bit.
  665 **                                                            0=The bridge does not initiate memory or I/O transactions on the primary interface.
  666 **                                                            1=The bridge is enabled to function as an initiator on the primary interface.
  667 ** 01          0                   Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface.
  668 **                                                            0=The bridge target response to memory transactions on the primary interface is disabled.
  669 **                                                            1=The bridge target response to memory transactions on the primary interface is enabled.
  670 ** 00          0                     I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface.
  671 **                                                            0=The bridge target response to I/O transactions on the primary interface is disabled.
  672 **                                                            1=The bridge target response to I/O transactions on the primary interface is enabled.
  673 **==============================================================================
  674 */
  675 #define     ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG           0x04    /*word*/
  676 #define     PCI_DISABLE_INTERRUPT          0x0400
  677 /*
  678 **==============================================================================
  679 **  0x07-0x06 : status register 
  680 ** Bit       Default                       Description
  681 ** 15          0                       Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, attribute or data parity error. 
  682 **                                                            This bit is set regardless of the state of the PER bit in the command register.
  683 ** 14          0                       Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
  684 ** 13          0                       Received Master Abort: The bridge sets this bit to a 1b when, acting as the initiator on the primary bus, its transaction (with the exception of special cycles) has been terminated with a Master Abort.
  685 ** 12          0                       Received Target Abort: The bridge sets this bit to a 1b when, acting as the initiator on the primary bus, its transaction has been terminated with a Target Abort.
  686 ** 11          0                       Signaled Target Abort: The bridge sets this bit to a 1b when it, as the target of a transaction, terminates it with a Target Abort. 
  687 **                                                            In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
  688 ** 10:09       01                             DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 
  689 **                                                            Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
  690 ** 08          0                    Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: The bridge is the current master on the primary bus
  691 **                                                            S_PERR# is detected asserted or is asserted by bridge
  692 **                                                            The Parity Error Response bit is set in the Command register
  693 ** 07          1                   Fast Back to Back Capable: Returns a 1b when read indicating that bridge is able to respond to fast back to back transactions on its primary interface.
  694 ** 06          0                             Reserved
  695 ** 05          1                   66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
  696 **                                                            1 =
  697 ** 04          1                    Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 
  698 **                                                            Offset 34h (Capability Pointer register) provides the offset for the first entry in the linked list of enhanced capabilities.
  699 ** 03          0                            Interrupt Status: Reflects the state of the interrupt in the device/function.
  700 **                                                            The bridge does not support interrupts.
  701 ** 02:00       000                           Reserved
  702 **==============================================================================
  703 */
  704 #define     ARCMSR_PCI2PCI_PRIMARY_STATUS_REG        0x06    /*word: 06,07 */
  705 #define          ARCMSR_ADAP_66MHZ         0x20
  706 /*
  707 **==============================================================================
  708 **  0x08 : revision ID 
  709 ** Bit       Default                       Description
  710 ** 07:00       00000000                  Revision ID (RID): '00h' indicating bridge A-0 stepping.
  711 **==============================================================================
  712 */
  713 #define     ARCMSR_PCI2PCI_REVISIONID_REG                    0x08    /*byte*/
  714 /*
  715 **==============================================================================
  716 **  0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 
  717 ** Bit       Default                       Description
  718 ** 23:16       06h                     Base Class Code (BCC): Indicates that this is a bridge device.
  719 ** 15:08       04h                      Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
  720 ** 07:00       00h               Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
  721 **==============================================================================
  722 */
  723 #define     ARCMSR_PCI2PCI_CLASSCODE_REG                 0x09    /*3bytes*/
  724 /*
  725 **==============================================================================
  726 **  0x0c : cache line size 
  727 ** Bit       Default                       Description
  728 ** 07:00       00h                     Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
  729 **                                                            The contents of this register are factored into internal policy decisions associated with memory read prefetching, and the promotion of Memory Write transactions to MWI transactions.
  730 **                                                            Valid cache line sizes are 8 and 16 dwords. 
  731 **                                                            When the cache line size is set to an invalid value, bridge behaves as though the cache line size was set to 00h.
  732 **==============================================================================
  733 */
  734 #define     ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C    /*byte*/
  735 /*
  736 **==============================================================================
  737 **  0x0d : latency timer (number of pci clock 00-ff ) 
  738 ** Bit       Default                       Description
  739 **                                   Primary Latency Timer (PTV):
  740 ** 07:00      00h (Conventional PCI)   Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
  741 **                                                            referenced from the assertion of FRAME# to the expiration of the timer, 
  742 **                                                            when bridge may continue as master of the current transaction. All bits are writable, 
  743 **                                                            resulting in a granularity of 1 PCI clock cycle. 
  744 **                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus after the first data transfer when its PCI bus grant has been deasserted.
  745 **         or 40h (PCI-X)                         PCI-X Mode: Primary bus Master latency timer. 
  746 **                                                            Indicates the number of PCI clock cycles,
  747 **                                                            referenced from the assertion of FRAME# to the expiration of the timer, 
  748 **                                                            when bridge may continue as master of the current transaction. 
  749 **                                                            All bits are writable, resulting in a granularity of 1 PCI clock cycle. 
  750 **                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 
  751 **                                                            (Except in the case where MLT expires within 3 data phases of an ADB.In this case bridge continues on until it reaches the next ADB before relinquishing the bus.)
  752 **==============================================================================
  753 */
  754 #define     ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG      0x0D    /*byte*/
  755 /*
  756 **==============================================================================
  757 **  0x0e : (header type,single function ) 
  758 ** Bit       Default                       Description
  759 ** 07           0                Multi-function device (MVD): 80331 is a single-function device.
  760 ** 06:00       01h                       Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 
  761 **                                                            Returns ¡§01h¡¨ when read indicating that the register layout conforms to the standard PCI-to-PCI bridge layout.
  762 **==============================================================================
  763 */
  764 #define     ARCMSR_PCI2PCI_HEADERTYPE_REG                0x0E    /*byte*/
  765 /*
  766 **==============================================================================
  767 **     0x0f   : 
  768 **==============================================================================
  769 */
  770 /*
  771 **==============================================================================
  772 **  0x13-0x10 : 
  773 **  PCI CFG Base Address #0 (0x10) 
  774 **==============================================================================
  775 */
  776 /*
  777 **==============================================================================
  778 **  0x17-0x14 : 
  779 **  PCI CFG Base Address #1 (0x14) 
  780 **==============================================================================
  781 */
  782 /*
  783 **==============================================================================
  784 **  0x1b-0x18 : 
  785 **  PCI CFG Base Address #2 (0x18) 
  786 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
  787 ** Bit       Default                       Description
  788 ** 23:16       00h             Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 
  789 **                                                            Any Type 1 configuration cycle on the primary bus whose bus number is greater than the secondary bus number,
  790 **                                                            and less than or equal to the subordinate bus number is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
  791 ** 15:08       00h               Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 
  792 **                                                            Any Type 1 configuration cycle matching this bus number is translated to a Type 0 configuration cycle (or a Special Cycle) before being executed on bridge's secondary PCI bus.
  793 ** 07:00       00h                  Primary Bus Number (PBN): Indicates bridge primary bus number. 
  794 **                                                            Any Type 1 configuration cycle on the primary interface with a bus number that is less than the contents of this register field does not be claimed by bridge.
  795 **-----------------0x1B--Secondary Latency Timer Register - SLTR
  796 ** Bit       Default                       Description
  797 **                             Secondary Latency Timer (STV):
  798 ** 07:00       00h (Conventional PCI)  Conventional PCI Mode: Secondary bus Master latency timer. 
  799 **                                                            Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# to the expiration of the timer, 
  800 **                                                            when bridge may continue as master of the current transaction. All bits are writable, 
  801 **                                                            resulting in a granularity of 1 PCI clock cycle.
  802 **                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus after the first data transfer when its PCI bus grant has been deasserted.
  803 **          or 40h (PCI-X)                        PCI-X Mode: Secondary bus Master latency timer. 
  804 **                                                            Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# to the expiration of the timer, 
  805 **                                                            when bridge may continue as master of the current transaction. All bits are writable, 
  806 **                                                            resulting in a granularity of 1 PCI clock cycle.
  807 **                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 
  808 **                                                            (Except in the case where MLT expires within 3 data phases of an ADB. In this case bridge continues on until it reaches the next ADB before relinquishing the bus)
  809 **==============================================================================
  810 */
  811 #define     ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG                 0x18    /*3byte 0x1A,0x19,0x18*/
  812 #define     ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG               0x19    /*byte*/
  813 #define     ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG         0x1A    /*byte*/
  814 #define     ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG        0x1B    /*byte*/
  815 /*
  816 **==============================================================================
  817 **  0x1f-0x1c : 
  818 **  PCI CFG Base Address #3 (0x1C) 
  819 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
  820 ** Bit       Default                       Description
  821 ** 15:12        0h            I/O Limit Address Bits [15:12]: Defines the top address of an address range to determine when to forward I/O transactions from one interface to the other. 
  822 **                                                            These bits correspond to address lines 15:12 for 4KB alignment. 
  823 **                                                            Bits 11:0 are assumed to be FFFh.
  824 ** 11:08        1h           I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
  825 ** 07:04        0h             I/O Base Address Bits [15:12]: Defines the bottom address of an address range to determine when to forward I/O transactions from one interface to the other. 
  826 **                                                            These bits correspond to address lines 15:12 for 4KB alignment. Bits 11:0 are assumed to be 000h.
  827 ** 03:00        1h            I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
  828 **-----------------0x1F,0x1E--Secondary Status Register - SSR
  829 ** Bit       Default                       Description
  830 ** 15           0b                     Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, attribute or data parity error on its secondary interface.
  831 ** 14           0b                     Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
  832 ** 13           0b                     Received Master Abort: The bridge sets this bit to a 1b when, acting as the initiator on the secondary bus, it's transaction (with the exception of special cycles) has been terminated with a Master Abort.
  833 ** 12           0b                     Received Target Abort: The bridge sets this bit to a 1b when, acting as the initiator on the secondary bus, it's transaction has been terminated with a Target Abort.
  834 ** 11           0b                     Signaled Target Abort: The bridge sets this bit to a 1b when it, as the target of a transaction, terminates it with a Target Abort. 
  835 **                                                            In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
  836 ** 10:09       01b                            DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 
  837 **                                                            Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
  838 ** 08           0b                  Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
  839 **                                                            The bridge is the current master on the secondary bus
  840 **                                                            S_PERR# is detected asserted or is asserted by bridge
  841 **                                                            The Parity Error Response bit is set in the Command register 
  842 ** 07           1b           Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
  843 ** 06           0b                           Reserved
  844 ** 05           1b                      66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
  845 **                                                            1 =
  846 ** 04:00       00h                           Reserved
  847 **==============================================================================
  848 */
  849 #define     ARCMSR_PCI2PCI_IO_BASE_REG                       0x1C    /*byte*/
  850 #define     ARCMSR_PCI2PCI_IO_LIMIT_REG                      0x1D    /*byte*/
  851 #define     ARCMSR_PCI2PCI_SECONDARY_STATUS_REG              0x1E    /*word: 0x1F,0x1E */
  852 /*
  853 **==============================================================================
  854 **  0x23-0x20 : 
  855 **  PCI CFG Base Address #4 (0x20)
  856 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
  857 ** Bit       Default                       Description
  858 ** 31:20      000h                              Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
  859 **                                                            the upper 1MB aligned value (exclusive) of the range. 
  860 **                                                            The incoming address must be less than or equal to this value. 
  861 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0] are assumed to be F FFFFh.
  862 ** 19:16        0h                            Reserved.
  863 ** 15:04      000h                               Memory Base: These 12 bits are compared with bits P_AD[31:20] of the incoming address to determine the lower 1MB aligned value (inclusive) of the range. 
  864 **                                                            The incoming address must be greater than or equal to this value.
  865 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) are assumed to be 0 0000h.
  866 ** 03:00        0h                            Reserved.
  867 **==============================================================================
  868 */
  869 #define     ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG   0x20    /*word: 0x21,0x20 */
  870 #define     ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG  0x22    /*word: 0x23,0x22 */
  871 /*
  872 **==============================================================================
  873 **  0x27-0x24 : 
  874 **  PCI CFG Base Address #5 (0x24) 
  875 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
  876 ** Bit       Default                       Description
  877 ** 31:20      000h                 Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
  878 **                                                            the upper 1MB aligned value (exclusive) of the range. 
  879 **                                                            The incoming address must be less than or equal to this value. 
  880 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0] are assumed to be F FFFFh.
  881 ** 19:16        1h                          64-bit Indicator: Indicates that 64-bit addressing is supported.
  882 ** 15:04      000h                  Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] of the incoming address to determine the lower 1MB aligned value (inclusive) of the range. 
  883 **                                                            The incoming address must be greater than or equal to this value. 
  884 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) are assumed to be 0 0000h.
  885 ** 03:00        1h                          64-bit Indicator: Indicates that 64-bit addressing is supported.
  886 **==============================================================================
  887 */
  888 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG      0x24    /*word: 0x25,0x24 */
  889 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG     0x26    /*word: 0x27,0x26 */
  890 /*
  891 **==============================================================================
  892 **  0x2b-0x28 : 
  893 ** Bit       Default                       Description
  894 ** 31:00    00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable  
  895 **                                                            bridge supports full 64-bit addressing.
  896 **==============================================================================
  897 */
  898 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG     0x28    /*dword: 0x2b,0x2a,0x29,0x28 */
  899 /*
  900 **==============================================================================
  901 **  0x2f-0x2c : 
  902 ** Bit       Default                       Description
  903 ** 31:00    00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 
  904 **                                                             bridge supports full 64-bit addressing.
  905 **==============================================================================
  906 */
  907 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG    0x2C    /*dword: 0x2f,0x2e,0x2d,0x2c */
  908 /*
  909 **==============================================================================
  910 **  0x33-0x30 : 
  911 ** Bit       Default                       Description
  912 ** 07:00       DCh                      Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
  913 **                                                            space. (Power Management Capability Registers)
  914 **==============================================================================
  915 */
  916 #define     ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG                      0x34    /*byte*/ 
  917 /*
  918 **==============================================================================
  919 **  0x3b-0x35 : reserved
  920 **==============================================================================
  921 */
  922 /*              
  923 **==============================================================================
  924 **  0x3d-0x3c : 
  925 **
  926 ** Bit       Default                       Description
  927 ** 15:08       00h                       Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
  928 ** 07:00       00h                     Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
  929 **==============================================================================
  930 */
  931 #define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG                0x3C    /*byte*/ 
  932 #define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG                 0x3D    /*byte*/ 
  933 /*
  934 **==============================================================================
  935 **  0x3f-0x3e : 
  936 ** Bit       Default                       Description
  937 ** 15:12        0h                          Reserved
  938 ** 11           0b                Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
  939 **                                                            to a timer discard on either the primary or secondary interface.
  940 **                                                            0b=SERR# is not asserted.
  941 **                                                            1b=SERR# is asserted.
  942 ** 10           0b                Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
  943 **                                                            The delayed completion is then discarded.
  944 ** 09           0b             Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles that bridge waits for an initiator on the secondary bus to repeat a delayed transaction request. 
  945 **                                                            The counter starts when the delayed transaction completion is ready to be returned to the initiator. 
  946 **                                                            When the initiator has not repeated the transaction at least once before the counter expires,bridge discards the delayed transaction from its queues.
  947 **                                                            0b=The secondary master time-out counter is 2 15 PCI clock cycles.
  948 **                                                            1b=The secondary master time-out counter is 2 10 PCI clock cycles.
  949 ** 08           0b               Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles that bridge waits for an initiator on the primary bus to repeat a delayed transaction request. 
  950 **                                                            The counter starts when the delayed transaction completion is ready to be returned to the initiator. 
  951 **                                                            When the initiator has not repeated the transaction at least once before the counter expires, bridge discards the delayed transaction from its queues.
  952 **                                                            0b=The primary master time-out counter is 2 15 PCI clock cycles.
  953 **                                                            1b=The primary master time-out counter is 2 10 PCI clock cycles.
  954 ** 07           0b            Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
  955 ** 06           0b                 Secondary Bus Reset (SBR): 
  956 **                                                            When cleared to 0b: The bridge deasserts S_RST#, when it had been asserted by writing this bit to a 1b.
  957 **                                                                When set to 1b: The bridge asserts S_RST#.
  958 ** 05           0b                   Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus when a master abort termination occurs in response to a delayed transaction initiated by bridge on the target bus.
  959 **                                                            0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,and returns FFFF FFFFh when a read.
  960 **                                                            1b=When the transaction had not yet been completed on the initiator bus (e.g.,delayed reads, or non-posted writes), 
  961 **                                                                 then bridge returns a Target Abort in response to the original requester 
  962 **                                                                 when it returns looking for its delayed completion on the initiator bus. 
  963 **                                                                 When the transaction had completed on the initiator bus (e.g., a PMW), then bridge asserts P_SERR# (when enabled).
  964 **                                   For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort while attempting to deliver a posted memory write on the destination bus.
  965 ** 04           0b                   VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit (also of this register), 
  966 **                                                            and the VGA Palette Snoop Enable bit (Command Register). 
  967 **                                                            When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) the VGA Aliasing bit for the corresponding enabled functionality,:
  968 **                                                            0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
  969 **                                                            1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
  970 **                                   When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), then this bit has no impact on bridge behavior.
  971 ** 03           0b                                VGA Enable: Setting this bit enables address decoding and transaction forwarding of the following VGA transactions from the primary bus to the secondary bus:
  972 **                                                            frame buffer memory addresses 000A0000h:000BFFFFh, VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h¡¨ and AD[15:10] are either not decoded (i.e., don't cares), or must be ¡§000000b¡¨
  973 **                                                            depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
  974 **                                                            I/O and Memory Enable bits must be set in the Command register to enable forwarding of VGA cycles.
  975 ** 02           0b                                ISA Enable: Setting this bit enables special handling for the forwarding of ISA I/O transactions that fall within the address range specified by the I/O Base and Limit registers, and are within the lowest 64Kbyte of the I/O address map (i.e., 0000 0000h - 0000 FFFFh).
  976 **                                                            0b=All I/O transactions that fall within the I/O Base and Limit registers' specified range are forwarded from primary to secondary unfiltered.
  977 **                                                            1b=Blocks the forwarding from primary to secondary of the top 768 bytes of each 1Kbyte alias. On the secondary the top 768 bytes of each 1K alias are inversely decoded and forwarded from secondary to primary.
  978 ** 01           0b                      SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
  979 **                                                            1b=The bridge asserts P_SERR# whenever S_SERR# is detected asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
  980 ** 00           0b                     Parity Error Response: This bit controls bridge response to a parity error that is detected on its secondary interface.
  981 **                                                            0b=When a data parity error is detected bridge does not assert S_PERR#. 
  982 **                                                            Also bridge does not assert P_SERR# in response to a detected address or attribute parity error.
  983 **                                                            1b=When a data parity error is detected bridge asserts S_PERR#. The bridge also asserts P_SERR# (when enabled globally via bit(8) of the Command register)
  984 **                                                            in response to a detected address or attribute parity error.
  985 **==============================================================================
  986 */
  987 #define     ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG                        0x3E    /*word*/ 
  988 /*
  989 **************************************************************************
  990 **                  Device Specific Registers 40-A7h
  991 **************************************************************************
  992 ** ----------------------------------------------------------------------------------------------------------
  993 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              | Configu-ration Byte Offset
  994 ** ----------------------------------------------------------------------------------------------------------
  995 ** |    Bridge Control 0    |             Arbiter Control/Status              |      Reserved             | 40h
  996 ** ----------------------------------------------------------------------------------------------------------
  997 ** |                 Bridge Control 2                |                 Bridge Control 1                   | 44h
  998 ** ----------------------------------------------------------------------------------------------------------
  999 ** |                    Reserved                     |                 Bridge Status                      | 48h
 1000 ** ----------------------------------------------------------------------------------------------------------
 1001 ** |                                             Reserved                                                 | 4Ch
 1002 ** ----------------------------------------------------------------------------------------------------------
 1003 ** |                 Prefetch Policy                 |               Multi-Transaction Timer              | 50h
 1004 ** ----------------------------------------------------------------------------------------------------------
 1005 ** |       Reserved         |      Pre-boot Status   |             P_SERR# Assertion Control              | 54h
 1006 ** ----------------------------------------------------------------------------------------------------------
 1007 ** |       Reserved         |        Reserved        |             Secondary Decode Enable                | 58h
 1008 ** ----------------------------------------------------------------------------------------------------------
 1009 ** |                    Reserved                     |                 Secondary IDSEL                    | 5Ch
 1010 ** ----------------------------------------------------------------------------------------------------------
 1011 ** |                                              Reserved                                                | 5Ch
 1012 ** ----------------------------------------------------------------------------------------------------------
 1013 ** |                                              Reserved                                                | 68h:CBh
 1014 ** ----------------------------------------------------------------------------------------------------------
 1015 **************************************************************************
 1016 **==============================================================================
 1017 **  0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
 1018 ** Bit       Default                       Description
 1019 ** 15:12      1111b                  Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule (PCI=16 clocks,PCI-X=6 clocks). 
 1020 **                                   Note that this field is only meaningful when:
 1021 **                                                              # Bit[11] of this register is set to 1b, indicating that a Grant Time-out violation had occurred. 
 1022 **                                                              # bridge internal arbiter is enabled.
 1023 **                                           Bits[15:12] Violating Agent (REQ#/GNT# pair number)
 1024 **                                                 0000b REQ#/GNT#[0]
 1025 **                                                 0001b REQ#/GNT#[1]
 1026 **                                                 0010b REQ#/GNT#[2]
 1027 **                                                 0011b REQ#/GNT#[3]
 1028 **                                                 1111b Default Value (no violation detected)
 1029 **                                   When bit[11] is cleared by software, this field reverts back to its default value.
 1030 **                                   All other values are Reserved
 1031 ** 11            0b                  Grant Time-out Occurred: When set to 1b, 
 1032 **                                   this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
 1033 **                                   Software clears this bit by writing a 1b to it.
 1034 ** 10            0b                      Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
 1035 **                                                            1=During bus idle, bridge parks the bus on itself. The bus grant is removed from the last master and internally asserted to bridge.
 1036 ** 09:08        00b                          Reserved
 1037 ** 07:00      0000 0000b  Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 
 1038 **                                                                      Each bit of this field assigns its corresponding secondary bus master to either the high priority arbiter ring (1b) or to the low priority arbiter ring (0b). 
 1039 **                                                                      Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 
 1040 **                                                                      Bit [6] corresponds to the bridge internal secondary bus request while Bit [7] corresponds to the SATU secondary bus request. 
 1041 **                                                                      Bits [5:4] are unused.
 1042 **                                                                      0b=Indicates that the master belongs to the low priority group.
 1043 **                                                                      1b=Indicates that the master belongs to the high priority group
 1044 **=================================================================================
 1045 **  0x43: Bridge Control Register 0 - BCR0
 1046 ** Bit       Default                       Description
 1047 ** 07           0b                  Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight and the Posted Write data is limited to 4KB.
 1048 **                                                            1=Operation in fully dynamic queue mode. The bridge enqueues up to 14 Posted Memory Write transactions and 8KB of posted write data.
 1049 ** 06:03        0H                          Reserved.
 1050 ** 02           0b                 Upstream Prefetch Disable: This bit disables bridge ability to perform upstream prefetch operations for Memory Read requests received on its secondary interface. 
 1051 **                                 This bit also controls the bridge's ability to generate advanced read commands when forwarding a Memory Read Block transaction request upstream from a PCI-X bus to a Conventional PCI bus.
 1052 **                                 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. The use of Memory Read Line and Memory Read
 1053 **                                      Multiple is enabled when forwarding a PCI-X Memory Read Block request to an upstream bus operating in Conventional PCI mode.
 1054 **                                 1b=bridge treats upstream PCI Memory Read requests as though they target non-prefetchable memory and forwards upstream PCI-X Memory Read Block commands as Memory Read when the primary bus is operating in Conventional PCI mode.
 1055 **                                 NOTE: This bit does not affect bridge ability to perform read prefetching when the received command is Memory Read Line or Memory Read Multiple.
 1056 **=================================================================================
 1057 **  0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
 1058 ** Bit       Default                       Description
 1059 ** 15:08    0000000b                         Reserved
 1060 ** 07:06         00b                   Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands, specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 
 1061 **                                                            The three options for handling these alias commands are to either pass it as is, re-map to the actual block memory read/write command encoding, or ignore
 1062 **                                                            the transaction forcing a Master Abort to occur on the Origination Bus.
 1063 **                                                   Bit (7:6) Handling of command
 1064 **                                                        0 0 Re-map to Memory Read/Write Block before forwarding
 1065 **                                                        0 1 Enqueue and forward the alias command code unaltered
 1066 **                                                        1 0 Ignore the transaction, forcing Master Abort
 1067 **                                                        1 1 Reserved
 1068 ** 05            1b                  Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 
 1069 **                                                            The watchdog timers are used to detect prohibitively long latencies in the system. 
 1070 **                                                            The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 
 1071 **                                                            or Split Requests (PCI-X mode) is not completed within 2 24 events 
 1072 **                                                            (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode, and as the number of times being retried when operating in Conventional PCI mode)
 1073 **                                                            0b=All 2 24 watchdog timers are enabled.
 1074 **                                                            1b=All 2 24 watchdog timers are disabled and there is no limits to the number of attempts bridge makes when initiating a PMW, 
 1075 **                                                                 transacting a Delayed Transaction, or how long it waits for a split completion corresponding to one of its requests.
 1076 ** 04            0b                  GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 
 1077 **                                                            Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
 1078 **                                                            0b=The Secondary bus arbiter times out an agent that does not assert FRAME# within 16/6 clocks of receiving its grant, once the bus has gone idle. 
 1079 **                                                                 The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 
 1080 **                                                                 An infringing agent does not receive a subsequent GNT# until it de-asserts its REQ# for at least one clock cycle.
 1081 **                                                            1b=GNT# time-out mechanism is disabled.
 1082 ** 03           00b                           Reserved.
 1083 ** 02            0b          Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
 1084 **                                                            The time out mechanism is used to ensure that initiators of delayed transactions return for their delayed completion data/status within a reasonable amount of time after it is available from bridge.
 1085 **                                                            0b=The secondary master time-out counter is enabled and uses the value specified by the Secondary Discard Timer bit (see Bridge Control Register).
 1086 **                                                            1b=The secondary master time-out counter is disabled. The bridge waits indefinitely for a secondary bus master to repeat a delayed transaction.
 1087 ** 01            0b            Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. The time out mechanism is used to ensure that initiators of delayed transactions return for their delayed completion data/status within a reasonable amount of time after it is available from bridge.
 1088 **                                                            0b=The primary master time-out counter is enabled and uses the value specified by the Primary Discard Timer bit (see Bridge Control Register).
 1089 **                                                            1b=The secondary master time-out counter is disabled. The bridge waits indefinitely for a secondary bus master to repeat a delayed transaction.
 1090 ** 00            0b                           Reserved
 1091 **=================================================================================
 1092 **  0x47-0x46: Bridge Control Register 2 - BCR2
 1093 ** Bit       Default                       Description
 1094 ** 15:07      0000b                          Reserved.
 1095 ** 06            0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): This bit disables all of the secondary PCI clock outputs including the feedback clock S_CLKOUT. 
 1096 **                                                            This means that the user is required to provide an S_CLKIN input source.
 1097 ** 05:04        11 (66 MHz)                  Preserved.
 1098 **              01 (100 MHz)
 1099 **              00 (133 MHz)
 1100 ** 03:00        Fh (100 MHz & 66 MHz)
 1101 **              7h (133 MHz)
 1102 **                                        This 4 bit field provides individual enable/disable mask bits for each of bridge
 1103 **                                        secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
 1104 **                                        default to being enabled following the rising edge of P_RST#, depending on the
 1105 **                                        frequency of the secondary bus clock:
 1106 **                                               ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with all four S_CLKOs enabled by default. (SCLKO[3:0])¡P
 1107 **                                               ¡E Designs with 133 MHz Secondary PCI clock power up with the lower order 3 S_CLKOs enabled by default. (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected to downstream device clock inputs.
 1108 **=================================================================================
 1109 **  0x49-0x48: Bridge Status Register - BSR
 1110 ** Bit       Default                       Description
 1111 ** 15           0b  Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# is conditionally asserted when the secondary discard timer expires.
 1112 ** 14           0b  Upstream Delayed/Split Read Watchdog Timer Expired: 
 1113 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream delayed read transaction request after 2 24 retries following the initial retry.
 1114 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream split read request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive.
 1115 ** 13           0b Upstream Delayed/Split Write Watchdog Timer Expired: 
 1116 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream delayed write transaction request after 2 24 retries following the initial retry.
 1117 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream split write request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive.
 1118 ** 12           0b           Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Master Abort occurs as a result of an attempt, by bridge, to retire a PMW upstream.
 1119 ** 11           0b           Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Target Abort occurs as a result of an attempt, by bridge, to retire a PMW upstream.
 1120 ** 10           0b                Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream PMW transaction after receiving 2 24 target retries from the primary bus target
 1121 ** 09           0b             Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when a data parity error is detected by bridge while attempting to retire a PMW upstream
 1122 ** 08           0b                  Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge detects an address parity error on the secondary bus.
 1123 ** 07           0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# is conditionally asserted when the primary bus discard timer expires.
 1124 ** 06           0b Downstream Delayed/Split Read Watchdog Timer Expired:
 1125 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream delayed read transaction request after receiving 2 24 target retries from the secondary bus target.
 1126 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream split read request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive.
 1127 ** 05           0b Downstream Delayed Write/Split Watchdog Timer Expired:
 1128 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream delayed write transaction request after receiving 2 24 target retries from the secondary bus target.
 1129 **                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream split write request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive.
 1130 ** 04           0b          Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Master Abort occurs as a result of an attempt, by bridge, to retire a PMW downstream.
 1131 ** 03           0b          Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Target Abort occurs as a result of an attempt, by bridge, to retire a PMW downstream.
 1132 ** 02           0b               Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream PMW transaction after receiving 2 24 target retries from the secondary bus target
 1133 ** 01           0b            Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when a data parity error is detected by bridge while attempting to retire a PMW downstream.
 1134 ** 00           0b                     Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge detects an address parity error on the primary bus.
 1135 **==================================================================================
 1136 **  0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
 1137 ** Bit       Default                       Description
 1138 ** 15:13       000b                          Reserved
 1139 ** 12:10       000b                          GRANT# Duration: This field specifies the count (PCI clocks) that a secondary bus master has its grant maintained in order to enable multiple transactions to execute within the same arbitration cycle.
 1140 **                                                    Bit[02:00] GNT# Extended Duration
 1141 **                                                               000 MTT Disabled (Default=no GNT# extension)
 1142 **                                                               001 16 clocks
 1143 **                                                               010 32 clocks
 1144 **                                                               011 64 clocks
 1145 **                                                               100 128 clocks
 1146 **                                                               101 256 clocks
 1147 **                                                               110 Invalid (treated as 000)
 1148 **                                                               111 Invalid (treated as 000)
 1149 ** 09:08        00b                          Reserved
 1150 ** 07:00        FFh                                 MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# pair supported by bridge secondary arbiter. 
 1151 **                                                            Bit(7) corresponds to SATU internal REQ#/GNT# pair,
 1152 **                                                            bit(6) corresponds to bridge internal REQ#/GNT# pair, 
 1153 **                                                            bit(5) corresponds to REQ#/GNT#(5) pair, etc.
 1154 **                                                  When a given bit is set to 1b, its corresponding REQ#/GNT# pair is enabled for MTT functionality as determined by bits(12:10) of this register.
 1155 **                                                  When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
 1156 **==================================================================================
 1157 **  0x53-0x52: Read Prefetch Policy Register - RPPR
 1158 ** Bit       Default                       Description
 1159 ** 15:13       000b                    ReRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the secondary bus interface on subsequent PreFetch operations given that the read demands were not satisfied using the FirstRead parameter.
 1160 **                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
 1161 ** 12:10       000b                 FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the secondary bus interface on the initial PreFetch operation.
 1162 **                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
 1163 ** 09:07       010b                  ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the primary bus interface on subsequent PreFetch operations given that the read demands were not satisfied using the FirstRead parameter.
 1164 **                                           The default value of 010b correlates to: Command Type Hardwired pre-fetch amount Memory Read 3 cache lines Memory Read Line 3 cache lines Memory Read Multiple 6 cache lines
 1165 ** 06:04       000b               FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the primary bus interface on the initial PreFetch operation.
 1166 **                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
 1167 ** 03:00      1111b                Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch algorithm for the secondary and the primary bus interfaces.
 1168 **                                                         Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
 1169 **                                                                            enable bits for REQ#/GNT#[2:0]. (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
 1170 **                                                                            1b: enables the staged pre-fetch feature
 1171 **                                                                            0b: disables staged pre-fetch,
 1172 **                                                         and hardwires read pre-fetch policy to the following for 
 1173 **                                                         Memory Read, 
 1174 **                                                         Memory Read Line, 
 1175 **                                                     and Memory Read Multiple commands: 
 1176 **                                                     Command Type Hardwired Pre-Fetch Amount...
 1177 **                                                                                      Memory Read 4 DWORDs
 1178 **                                                                                      Memory Read Line 1 cache line
 1179 **                                                                                      Memory Read Multiple 2 cache lines
 1180 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands only to the next higher cache line boundary.For non-cache line aligned Memory Read Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
 1181 **==================================================================================
 1182 **  0x55-0x54: P_SERR# Assertion Control - SERR_CTL
 1183 ** Bit       Default                       Description
 1184 **  15          0b   Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior in response to its discarding of a delayed transaction that was initiated from the primary bus.
 1185 **                                                                       0b=bridge asserts P_SERR#.
 1186 **                                                                       1b=bridge does not assert P_SERR#
 1187 **  14          0b   Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 1188 **                                                                       0b=bridge asserts P_SERR#.
 1189 **                                                                       1b=bridge does not assert P_SERR#
 1190 **  13          0b   Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 1191 **                                                                       0b=bridge asserts P_SERR#.
 1192 **                                                                       1b=bridge does not assert P_SERR#
 1193 **  12          0b             Master Abort during Upstream Posted Write: Dictates bridge behavior following its having detected a Master Abort while attempting to retire one of its PMWs upstream.
 1194 **                                                                       0b=bridge asserts P_SERR#.
 1195 **                                                                       1b=bridge does not assert P_SERR#
 1196 **  11          0b             Target Abort during Upstream Posted Write: Dictates bridge behavior following its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
 1197 **                                                                       0b=bridge asserts P_SERR#.
 1198 **                                                                       1b=bridge does not assert P_SERR#
 1199 **  10          0b                  Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that it discards an upstream posted write transaction.
 1200 **                                                                       0b=bridge asserts P_SERR#.
 1201 **                                                                       1b=bridge does not assert P_SERR#
 1202 **  09          0b               Upstream Posted Write Data Parity Error: Dictates bridge behavior when a data parity error is detected while attempting to retire on of its PMWs upstream.
 1203 **                                                                       0b=bridge asserts P_SERR#.
 1204 **                                                                       1b=bridge does not assert P_SERR#
 1205 **  08          0b                    Secondary Bus Address Parity Error: This bit dictates bridge behavior when it detects an address parity error on the secondary bus.
 1206 **                                                                       0b=bridge asserts P_SERR#.
 1207 **                                                                       1b=bridge does not assert P_SERR#
 1208 **  07          0b  Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to its discarding of a delayed transaction that was initiated on the secondary bus.
 1209 **                                                                       0b=bridge asserts P_SERR#.
 1210 **                                                                       1b=bridge does not assert P_SERR#
 1211 **  06          0b  Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 1212 **                                                                       0b=bridge asserts P_SERR#.
 1213 **                                                                       1b=bridge does not assert P_SERR#
 1214 **  05          0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 1215 **                                                                       0b=bridge asserts P_SERR#.
 1216 **                                                                       1b=bridge does not assert P_SERR#
 1217 **  04          0b           Master Abort during Downstream Posted Write: Dictates bridge behavior following its having detected a Master Abort while attempting to retire one of its PMWs downstream.
 1218 **                                                                       0b=bridge asserts P_SERR#.
 1219 **                                                                       1b=bridge does not assert P_SERR#
 1220 **  03          0b           Target Abort during Downstream Posted Write: Dictates bridge behavior following its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
 1221 **                                                                       0b=bridge asserts P_SERR#.
 1222 **                                                                       1b=bridge does not assert P_SERR#
 1223 **  02          0b                Downstream Posted Write Data Discarded: Dictates bridge behavior in the event that it discards a downstream posted write transaction.
 1224 **                                                                       0b=bridge asserts P_SERR#.
 1225 **                                                                       1b=bridge does not assert P_SERR#
 1226 **  01          0b             Downstream Posted Write Data Parity Error: Dictates bridge behavior when a data parity error is detected while attempting to retire on of its PMWs downstream.
 1227 **                                                                       0b=bridge asserts P_SERR#.
 1228 **                                                                       1b=bridge does not assert P_SERR#
 1229 **  00          0b                      Primary Bus Address Parity Error: This bit dictates bridge behavior when it detects an address parity error on the primary bus.
 1230 **                                                                       0b=bridge asserts P_SERR#.
 1231 **                                                                       1b=bridge does not assert P_SERR#
 1232 **===============================================================================
 1233 **  0x56: Pre-Boot Status Register - PBSR
 1234 ** Bit       Default                                                                            Description
 1235 ** 07           1                                                                                Reserved
 1236 ** 06           -                                                                                Reserved - value indeterminate
 1237 ** 05:02        0                                                                                Reserved
 1238 ** 01      Varies with External State of S_133EN at PCI Bus Reset    Secondary Bus Max Frequency Setting: This bit reflect captured S_133EN strap, indicating the maximum secondary bus clock frequency when in PCI-X mode.
 1239 **                                                                   Max Allowable Secondary Bus Frequency
 1240 **                                                                                                                                                                                                      S_133EN PCI-X Mode
 1241 **                                                                                                                                                                                                      0 100 MHz
 1242 **                                                                                                                                                                                                      1 133 MH
 1243 ** 00          0b                                                    Reserved
 1244 **===============================================================================
 1245 **  0x59-0x58: Secondary Decode Enable Register - SDER
 1246 ** Bit       Default                                                                            Description
 1247 ** 15:03      FFF1h                                                                              Preserved.
 1248 ** 02     Varies with External State of PRIVMEM at PCI Bus Reset   Private Memory Space Enable - when set, bridge overrides its secondary inverse decode logic and not
 1249 **                                                                 forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
 1250 **                                                                 This creates a private memory space on the Secondary PCI bus that allows peer-to-peer transactions.
 1251 ** 01:00      10 2                                                   Preserved.
 1252 **===============================================================================
 1253 **  0x5D-0x5C: Secondary IDSEL Select Register - SISR
 1254 ** Bit       Default                                                                            Description
 1255 ** 15:10     000000 2                                                                            Reserved.
 1256 ** 09    Varies with External State of PRIVDEV at PCI Bus Reset     AD25- IDSEL Disable - When this bit is set, AD25 is deasserted for any possible Type 1 to Type 0 conversion.
 1257 **                                                                                        When this bit is clear, AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
 1258 ** 08    Varies with External State of PRIVDEV at PCI Bus Reset     AD24- IDSEL Disable - When this bit is set, AD24 is deasserted for any possible Type 1 to Type 0 conversion.
 1259 **                                                                                        When this bit is clear, AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
 1260 ** 07    Varies with External State of PRIVDEV at PCI Bus Reset     AD23- IDSEL Disable - When this bit is set, AD23 is deasserted for any possible Type 1 to Type 0 conversion. 
 1261 **                                                                                        When this bit is clear, AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
 1262 ** 06    Varies with External State of PRIVDEV at PCI Bus Reset     AD22- IDSEL Disable - When this bit is set, AD22 is deasserted for any possible Type 1 to Type 0 conversion.
 1263 **                                                                                        When this bit is clear, AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
 1264 ** 05    Varies with External State of PRIVDEV at PCI Bus Reset     AD21- IDSEL Disable - When this bit is set, AD21 is deasserted for any possible Type 1 to Type 0 conversion.
 1265 **                                                                                        When this bit is clear, AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
 1266 ** 04    Varies with External State of PRIVDEV at PCI Bus Reset     AD20- IDSEL Disable - When this bit is set, AD20 is deasserted for any possible Type 1 to Type 0 conversion.
 1267 **                                                                                        When this bit is clear, AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
 1268 ** 03    Varies with External State of PRIVDEV at PCI Bus Reset     AD19- IDSEL Disable - When this bit is set, AD19 is deasserted for any possible Type 1 to Type 0 conversion.
 1269 **                                                                                        When this bit is clear, AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
 1270 ** 02    Varies with External State of PRIVDEV at PCI Bus Reset     AD18- IDSEL Disable - When this bit is set, AD18 is deasserted for any possible Type 1 to Type 0 conversion.
 1271 **                                                                                        When this bit is clear, AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
 1272 ** 01    Varies with External State of PRIVDEV at PCI Bus Reset     AD17- IDSEL Disable - When this bit is set, AD17 is deasserted for any possible Type 1 to Type 0 conversion.
 1273 **                                                                                        When this bit is clear, AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
 1274 ** 00    Varies with External State of PRIVDEV at PCI Bus Reset     AD16- IDSEL Disable - When this bit is set, AD16 is deasserted for any possible Type 1 to Type 0 conversion.
 1275 **                                                                                        When this bit is clear, AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
 1276 **************************************************************************
 1277 */
 1278 /*
 1279 **************************************************************************
 1280 **                 Reserved      A8-CBh           
 1281 **************************************************************************
 1282 */
 1283 /*
 1284 **************************************************************************
 1285 **                  PCI Extended Enhanced Capabilities List CC-FFh
 1286 **************************************************************************
 1287 ** ----------------------------------------------------------------------------------------------------------
 1288 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              | Configu-ration Byte Offset
 1289 ** ----------------------------------------------------------------------------------------------------------
 1290 ** |           Power Management Capabilities         |        Next Item Ptr   |     Capability ID         | DCh
 1291 ** ----------------------------------------------------------------------------------------------------------
 1292 ** |        PM Data         |       PPB Support      |            Extensions Power Management CSR         | E0h
 1293 ** ----------------------------------------------------------------------------------------------------------
 1294 ** |                    Reserved                     |        Reserved        |        Reserved           | E4h
 1295 ** ----------------------------------------------------------------------------------------------------------
 1296 ** |                                              Reserved                                                | E8h
 1297 ** ----------------------------------------------------------------------------------------------------------
 1298 ** |       Reserved         |        Reserved        |        Reserved        |         Reserved          | ECh
 1299 ** ----------------------------------------------------------------------------------------------------------
 1300 ** |              PCI-X Secondary Status             |       Next Item Ptr    |       Capability ID       | F0h
 1301 ** ----------------------------------------------------------------------------------------------------------
 1302 ** |                                         PCI-X Bridge Status                                          | F4h
 1303 ** ----------------------------------------------------------------------------------------------------------
 1304 ** |                                PCI-X Upstream Split Transaction Control                              | F8h
 1305 ** ----------------------------------------------------------------------------------------------------------
 1306 ** |                               PCI-X Downstream Split Transaction Control                             | FCh
 1307 ** ----------------------------------------------------------------------------------------------------------
 1308 **===============================================================================
 1309 **  0xDC: Power Management Capabilities Identifier - PM_CAPID
 1310 ** Bit       Default                       Description
 1311 ** 07:00       01h                        Identifier (ID): PCI SIG assigned ID for PCI-PM register block
 1312 **===============================================================================
 1313 **  0xDD: Next Item Pointer - PM_NXTP
 1314 ** Bit       Default                       Description
 1315 ** 07:00       F0H                Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header.
 1316 **===============================================================================
 1317 **  0xDF-0xDE: Power Management Capabilities Register - PMCR
 1318 ** Bit       Default                       Description
 1319 ** 15:11       00h                     PME Supported (PME): PME# cannot be asserted by bridge.
 1320 ** 10           0h                 State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
 1321 ** 09           1h                 State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
 1322 ** 08:06        0h                Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 
 1323 **                                                          This returns 000b as PME# wake-up for bridge is not implemented.
 1324 ** 05           0   Special Initialization Required (SINT): Special initialization is not required for bridge.
 1325 ** 04:03       00                            Reserved
 1326 ** 02:00       010                            Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1.
 1327 **===============================================================================
 1328 **  0xE1-0xE0: Power Management Control / Status - Register - PMCSR
 1329 ** Bit       Default                       Description
 1330 ** 15:09       00h                          Reserved
 1331 ** 08          0b                          PME_Enable: This bit, when set to 1b enables bridge to assert PME#. Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
 1332 ** 07:02       00h                          Reserved
 1333 ** 01:00       00                Power State (PSTATE): This 2-bit field is used both to determine the current power state of a function and to set the Function into a new power state.
 1334 **                                                                                                      00 - D0 state
 1335 **                                                                                                      01 - D1 state
 1336 **                                                                                                      10 - D2 state
 1337 **                                                                                                      11 - D3 hot state
 1338 **===============================================================================
 1339 **  0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
 1340 ** Bit       Default                       Description
 1341 ** 07          0         Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
 1342 ** 06          0                B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that is to occur as a direct result of programming the function to D3 hot.
 1343 **                                                                 This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨.
 1344 ** 05:00     00h                            Reserved
 1345 **===============================================================================
 1346 **  0xE3: Power Management Data Register - PMDR
 1347 ** Bit       Default                       Description
 1348 ** 07:00       00h                          Reserved
 1349 **===============================================================================
 1350 **  0xF0: PCI-X Capabilities Identifier - PX_CAPID
 1351 ** Bit       Default                       Description
 1352 ** 07:00       07h                       Identifier (ID): Indicates this is a PCI-X capabilities list.
 1353 **===============================================================================
 1354 **  0xF1: Next Item Pointer - PX_NXTP
 1355 ** Bit       Default                       Description
 1356 ** 07:00       00h                     Next Item Pointer: Points to the next capability in the linked list The power on default value of this
 1357 **                                                        register is 00h indicating that this is the last entry in the linked list of capabilities.
 1358 **===============================================================================
 1359 **  0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
 1360 ** Bit       Default                       Description
 1361 ** 15:09       00h                          Reserved
 1362 ** 08:06       Xxx                Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 
 1363 **                                                                 The values are:
 1364 **                                                                                                                                                                      BitsMax FrequencyClock Period
 1365 **                                                                                                                                                                      000PCI ModeN/A
 1366 **                                                                                                                                                                      00166 15
 1367 **                                                                                                                                                                      01010010
 1368 **                                                                                                                                                                      0111337.5
 1369 **                                                                                                                                                                      1xxreservedreserved
 1370 **                                                                                                                                                                      The default value for this register is the operating frequency of the secondary bus
 1371 ** 05           0b                   Split Request Delayed. (SRD):  This bit is supposed to be set by a bridge when it cannot forward a transaction on the
 1372 **                                                                                                                                      secondary bus to the primary bus because there is not enough room within the limit
 1373 **                                                                                                                                      specified in the Split Transaction Commitment Limit field in the Downstream Split
 1374 **                                                                                                                                      Transaction Control register. The bridge does not set this bit.
 1375 ** 04           0b                 Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the secondary bus with retry or Disconnect at next ADB because its buffers are full. The bridge does not set this bit.
 1376 ** 03           0b              Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID equal to bridge secondary bus number, device number 00h, and function number 0 is received on the secondary interface. This bit is cleared by software writing a '1'.
 1377 ** 02           0b               Split Completion Discarded (SCD): This bit is set when bridge discards a split completion moving toward the secondary bus because the requester would not accept it. This bit cleared by software writing a '1'.
 1378 ** 01           1b                                133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
 1379 ** 00           1b                            64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
 1380 **===============================================================================
 1381 **  0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
 1382 ** Bit       Default                                                                                     Description
 1383 ** 31:22        0                                                                                         Reserved
 1384 ** 21           0                                                                               Split Request Delayed (SRD): This bit does not be set by bridge.
 1385 ** 20           0                                                                            Split Completion Overrun (SCO): This bit does not be set by bridge because bridge throttles traffic on the completion side.
 1386 ** 19           0                                                                         Unexpected Split Completion (USC): The bridge sets this bit to 1b when it encounters a corrupted Split Completion, possibly with an inconsistent remaining byte count.Software clears this bit by writing a 1b to it.
 1387 ** 18           0                                                                          Split Completion Discarded (SCD): The bridge sets this bit to 1b when it has discarded a Split Completion.Software clears this bit by writing a 1b to it.
 1388 ** 17           1                                                                                           133 MHz Capable: This bit indicates that the bridge primary interface is capable of 133 MHz operation in PCI-X mode.
 1389 **                                                                                                                           0=The maximum operating frequency is 66 MHz.
 1390 **                                                                                                                           1=The maximum operating frequency is 133 MHz.
 1391 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset    64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
 1392 **                                                                                                                                                                                       0=Primary Interface is connected as a 32-bit PCI bus.
 1393 **                                                                                                                                                                                       1=Primary Interface is connected as a 64-bit PCI bus.
 1394 ** 15:08       00h                                                        Bus Number (BNUM): This field is simply an alias to the PBN field of the BNUM register at offset 18h.
 1395 **                                                                                           Apparently it was deemed necessary reflect it here for diagnostic purposes.
 1396 ** 07:03       1fh                                                     Device Number (DNUM): Indicates which IDSEL bridge consumes. May be updated whenever a PCI-X
 1397 **                                                                                                                                                                                       configuration write cycle that targets bridge scores a hit.
 1398 ** 02:00        0h                                                   Function Number (FNUM): The bridge Function #
 1399 **===============================================================================
 1400 **  0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
 1401 ** Bit       Default                       Description
 1402 ** 31:16      003Eh                 Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
 1403 **                                                                 Software is permitted to program this register to any value greater than or equal to
 1404 **                                                                 the contents of the Split Transaction Capacity register. A value less than the contents
 1405 **                                                                 of the Split Transaction Capacity register causes unspecified results.
 1406 **                                                                 A value of 003Eh or greater enables the bridge to forward all Split Requests of any
 1407 **                                                                 size regardless of the amount of buffer space available.
 1408 ** 15:00      003Eh              Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
 1409 **                                                                                                                                 split completions. This register controls behavior of the bridge buffers for forwarding
 1410 **                                                                                                                                 Split Transactions from a primary bus requester to a secondary bus completer.
 1411 **                                                                                                                                 The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
 1412 **===============================================================================
 1413 **  0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
 1414 ** Bit       Default                       Description
 1415 ** 31:16      003Eh                 Split Transaction Limit (STL):  This register indicates the size of the commitment limit in units of ADQs.
 1416 **                                                                                                                                      Software is permitted to program this register to any value greater than or equal to
 1417 **                                                                                                                                      the contents of the Split Transaction Capacity register. A value less than the contents
 1418 **                                                                                                                                      of the Split Transaction Capacity register causes unspecified results.
 1419 **                                                                                                                                      A value of 003Eh or greater enables the bridge to forward all Split Requests of any
 1420 **                                                                                                                                      size regardless of the amount of buffer space available.
 1421 ** 15:00      003Eh              Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
 1422 **                                                                 split completions. This register controls behavior of the bridge buffers for forwarding
 1423 **                                                                 Split Transactions from a primary bus requester to a secondary bus completer.
 1424 **                                                                 The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
 1425 **************************************************************************
 1426 */
 1427 
 1428 
 1429 
 1430 
 1431 /*
 1432 *************************************************************************************************************************************
 1433 **                       80331 Address Translation Unit Register Definitions
 1434 **                               ATU Interface Configuration Header Format
 1435 **               The ATU is programmed via a [Type 0] configuration command on the PCI interface.
 1436 *************************************************************************************************************************************
 1437 ** |    Byte 3              |         Byte 2         |        Byte 1          |       Byte 0              | Configuration Byte Offset
 1438 **===================================================================================================================================
 1439 ** |                ATU Device ID                    |                     Vendor ID                      | 00h
 1440 ** ----------------------------------------------------------------------------------------------------------
 1441 ** |                     Status                      |                     Command                        | 04H
 1442 ** ----------------------------------------------------------------------------------------------------------
 1443 ** |                              ATU Class Code                              |       Revision ID         | 08H
 1444 ** ----------------------------------------------------------------------------------------------------------
 1445 ** |         ATUBISTR       |     Header Type        |      Latency Timer     |      Cacheline Size       | 0CH
 1446 ** ----------------------------------------------------------------------------------------------------------
 1447 ** |                                     Inbound ATU Base Address 0                                       | 10H
 1448 ** ----------------------------------------------------------------------------------------------------------
 1449 ** |                               Inbound ATU Upper Base Address 0                                       | 14H
 1450 ** ----------------------------------------------------------------------------------------------------------
 1451 ** |                                     Inbound ATU Base Address 1                                       | 18H
 1452 ** ----------------------------------------------------------------------------------------------------------
 1453 ** |                               Inbound ATU Upper Base Address 1                                       | 1CH
 1454 ** ----------------------------------------------------------------------------------------------------------
 1455 ** |                                     Inbound ATU Base Address 2                                       | 20H
 1456 ** ----------------------------------------------------------------------------------------------------------
 1457 ** |                               Inbound ATU Upper Base Address 2                                       | 24H
 1458 ** ----------------------------------------------------------------------------------------------------------
 1459 ** |                                             Reserved                                                 | 28H   
 1460 ** ----------------------------------------------------------------------------------------------------------
 1461 ** |                ATU Subsystem ID                 |                ATU Subsystem Vendor ID             | 2CH
 1462 ** ----------------------------------------------------------------------------------------------------------
 1463 ** |                                       Expansion ROM Base Address                                     | 30H
 1464 ** ----------------------------------------------------------------------------------------------------------
 1465 ** |                                    Reserved Capabilities Pointer                                     | 34H
 1466 ** ----------------------------------------------------------------------------------------------------------
 1467 ** |                                             Reserved                                                 | 38H
 1468 ** ----------------------------------------------------------------------------------------------------------
 1469 ** |     Maximum Latency    |     Minimum Grant      |       Interrupt Pin    |      Interrupt Line       | 3CH
 1470 ** ----------------------------------------------------------------------------------------------------------
 1471 *********************************************************************************************************************
 1472 */
 1473 /*
 1474 ***********************************************************************************
 1475 **  ATU Vendor ID Register - ATUVID
 1476 **  -----------------------------------------------------------------
 1477 **  Bit       Default                       Description
 1478 **  15:00      8086H (0x17D3)               ATU Vendor ID - This is a 16-bit value assigned to Intel. This register, combined with the DID, uniquely identify the PCI device. 
 1479 **                                                          Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID to simulate the interface of a standard mechanism currently used by existing application software.
 1480 ***********************************************************************************
 1481 */
 1482 #define     ARCMSR_ATU_VENDOR_ID_REG                     0x00    /*word*/
 1483 /*
 1484 ***********************************************************************************
 1485 **  ATU Device ID Register - ATUDID
 1486 **  -----------------------------------------------------------------
 1487 **  Bit       Default                       Description
 1488 **  15:00      0336H (0x1110)               ATU Device ID - This is a 16-bit value assigned to the ATU. This ID, combined with the VID, uniquely identify any PCI device.
 1489 ***********************************************************************************
 1490 */
 1491 #define     ARCMSR_ATU_DEVICE_ID_REG                     0x02    /*word*/
 1492 /*
 1493 ***********************************************************************************
 1494 **  ATU Command Register - ATUCMD
 1495 **  -----------------------------------------------------------------
 1496 **  Bit       Default                       Description
 1497 **  15:11      000000 2                     Reserved
 1498 **  10           0                          Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
 1499 **                                                              0=enables the assertion of interrupt signal.
 1500 **                                                              1=disables the assertion of its interrupt signal.
 1501 **  09          0 2                         Fast Back to Back Enable - When cleared, the ATU interface is not allowed to generate fast back-to-back cycles on its bus. Ignored when operating in the PCI-X mode.
 1502 **  08          0 2                         SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
 1503 **  07          1 2                         Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
 1504 **                                          ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles of address stepping for PCI-X mode.
 1505 **  06          0 2                         Parity Error Response - When set, the ATU takes normal action when a parity error is detected. When cleared, parity checking is disabled.
 1506 **  05          0 2                         VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, does not perform VGA palette snooping.
 1507 **  04          0 2                         Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
 1508 **  03          0 2                         Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. Not implemented and a reserved bit field.
 1509 **  02          0 2                         Bus Master Enable - The ATU interface can act as a master on the PCI bus. When cleared, disables the device from generating PCI accesses. When set, allows the device to behave as a PCI bus master.
 1510 **                                          When operating in the PCI-X mode, ATU initiates a split completion transaction regardless of the state of this bit.
 1511 **  01          0 2                         Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses. When cleared, the ATU interface does not respond to any memory access on the PCI bus.
 1512 **  00          0 2                         I/O Space Enable - Controls the ATU interface response to I/O transactions. Not implemented and a reserved bit field.
 1513 ***********************************************************************************
 1514 */
 1515 #define     ARCMSR_ATU_COMMAND_REG                       0x04    /*word*/
 1516 /*
 1517 ***********************************************************************************
 1518 **  ATU Status Register - ATUSR (Sheet 1 of 2)
 1519 **  -----------------------------------------------------------------
 1520 **  Bit       Default                       Description
 1521 **  15          0 2                         Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
 1522 **                                                                              when the ATUCMD register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
 1523 **                                                                              ¡E Write Data Parity Error when the ATU is a target (inbound write).
 1524 **                                                                              ¡E Read Data Parity Error when the ATU is a requester (outbound read).
 1525 **                                                                              ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
 1526 **  14          0 2                         SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
 1527 **  13          0 2                         Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
 1528 **                                          or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
 1529 **  12          0 2                         Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
 1530 **                                          abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
 1531 **  11          0 2                         Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort.
 1532 **  10:09       01 2                        DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# timing for a target device in Conventional PCI Mode regardless of the operating mode (except configuration accesses).
 1533 **                                                                              00 2=Fast
 1534 **                                                                              01 2=Medium
 1535 **                                                                              10 2=Slow
 1536 **                                                                              11 2=Reserved
 1537 **                                          The ATU interface uses Medium timing.
 1538 **  08           0 2                        Master Parity Error - The ATU interface sets this bit under the following conditions:
 1539 **                                                                              ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
 1540 **                                                                              ¡E And the ATU acted as the requester for the operation in which the error occurred.
 1541 **                                                                              ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
 1542 **                                                                              ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
 1543 **                                                                              ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
 1544 **  07           1 2  (Conventional mode)
 1545 **               0 2  (PCI-X mode)
 1546 **                                                                              Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back
 1547 **                                                                              transactions in Conventional PCI mode when the transactions are not to the same target. Since fast
 1548 **                                                                              back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
 1549 **  06           0 2                        UDF Supported - User Definable Features are not supported
 1550 **  05           1 2                        66 MHz. Capable - 66 MHz operation is supported.
 1551 **  04           1 2                        Capabilities - When set, this function implements extended capabilities.
 1552 **  03             0                        Interrupt Status - reflects the state of the ATU interrupt when the Interrupt Disable bit in the command register is a 0.
 1553 **                                                                              0=ATU interrupt signal deasserted.
 1554 **                                                                              1=ATU interrupt signal asserted.
 1555 **                                                                              NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to
 1556 **                                                                              Section 3.10.23, ¡§ATU Interrupt Pin Register - ATUIPR¡¨ on page 236 for details on the ATU
 1557 **                                                                              interrupt signal.
 1558 **  02:00      00000 2                      Reserved.
 1559 ***********************************************************************************
 1560 */
 1561 #define     ARCMSR_ATU_STATUS_REG                        0x06    /*word*/
 1562 /*
 1563 ***********************************************************************************
 1564 **  ATU Revision ID Register - ATURID
 1565 **  -----------------------------------------------------------------
 1566 **  Bit       Default                       Description
 1567 **  07:00        00H                        ATU Revision - identifies the 80331 revision number.
 1568 ***********************************************************************************
 1569 */
 1570 #define     ARCMSR_ATU_REVISION_REG                      0x08    /*byte*/
 1571 /*
 1572 ***********************************************************************************
 1573 **  ATU Class Code Register - ATUCCR
 1574 **  -----------------------------------------------------------------
 1575 **  Bit       Default                       Description
 1576 **  23:16        05H                        Base Class - Memory Controller
 1577 **  15:08        80H                        Sub Class - Other Memory Controller
 1578 **  07:00        00H                        Programming Interface - None defined
 1579 ***********************************************************************************
 1580 */
 1581 #define     ARCMSR_ATU_CLASS_CODE_REG                    0x09    /*3bytes 0x0B,0x0A,0x09*/
 1582 /*
 1583 ***********************************************************************************
 1584 **  ATU Cacheline Size Register - ATUCLSR
 1585 **  -----------------------------------------------------------------
 1586 **  Bit       Default                       Description
 1587 **  07:00        00H                        ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs.
 1588 ***********************************************************************************
 1589 */
 1590 #define     ARCMSR_ATU_CACHELINE_SIZE_REG                        0x0C    /*byte*/
 1591 /*
 1592 ***********************************************************************************
 1593 **  ATU Latency Timer Register - ATULT
 1594 **  -----------------------------------------------------------------
 1595 **  Bit       Default                       Description
 1596 **  07:03     00000 2 (for Conventional mode)
 1597 **            01000 2 (for PCI-X mode)
 1598 **                                                                              Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks.
 1599 **                                                                              The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
 1600 **  02:00       000 2                       Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer.
 1601 ***********************************************************************************
 1602 */
 1603 #define     ARCMSR_ATU_LATENCY_TIMER_REG                         0x0D    /*byte*/
 1604 /*
 1605 ***********************************************************************************
 1606 **  ATU Header Type Register - ATUHTR
 1607 **  -----------------------------------------------------------------
 1608 **  Bit       Default                       Description
 1609 **  07           0 2                        Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device.
 1610 **  06:00   000000 2                        PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface
 1611 **                                          header conforms to PCI Local Bus Specification, Revision 2.3.
 1612 ***********************************************************************************
 1613 */
 1614 #define     ARCMSR_ATU_HEADER_TYPE_REG                   0x0E    /*byte*/
 1615 /*
 1616 ***********************************************************************************
 1617 **  ATU BIST Register - ATUBISTR
 1618 **
 1619 **  The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
 1620 **  initiated. This register is the interface between the host processor requesting BIST functions and
 1621 **  the 80331 replying with the results from the software implementation of the BIST functionality.
 1622 **  -----------------------------------------------------------------
 1623 **  Bit       Default                       Description
 1624 **  07           0 2                        BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 
 1625 **  06           0 2                        Start BIST - When the ATUCR BIST Interrupt Enable bit is set:
 1626 **                                                                                                       Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
 1627 **                                                                                                       The Intel XScale core clears this bit when the BIST software has completed with the BIST results
 1628 **                                                                                                       found in ATUBISTR register bits [3:0].
 1629 **                                                                                                       When the ATUCR BIST Interrupt Enable bit is clear:
 1630 **                                                                                                       Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 
 1631 **                                                       The Intel XScale core does not clear this bit.
 1632 **  05:04       00 2                        Reserved
 1633 **  03:00     0000 2                        BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6):
 1634 **                                          The Intel XScale  core places the results of the software BIST in these bits. A nonzero value indicates a device-specific error.
 1635 ***********************************************************************************
 1636 */
 1637 #define     ARCMSR_ATU_BIST_REG                  0x0F    /*byte*/
 1638 
 1639 /*
 1640 ***************************************************************************************  
 1641 **            ATU Base Registers and Associated Limit Registers
 1642 ***************************************************************************************
 1643 **           Base Address                         Register Limit                          Register Description
 1644 **  Inbound ATU Base Address Register 0           Inbound ATU Limit Register 0            Defines the inbound translation window 0 from the PCI bus.
 1645 **  Inbound ATU Upper Base Address Register 0     N/A                                     Together with ATU Base Address Register 0 defines the inbound translation window 0 from the PCI bus for DACs.
 1646 **  Inbound ATU Base Address Register 1           Inbound ATU Limit Register 1            Defines inbound window 1 from the PCI bus.
 1647 **  Inbound ATU Upper Base Address Register 1     N/A                                     Together with ATU Base Address Register 1 defines inbound window 1 from the PCI bus for DACs.
 1648 **  Inbound ATU Base Address Register 2           Inbound ATU Limit Register 2            Defines the inbound translation window 2 from the PCI bus.
 1649 **  Inbound ATU Upper Base Address Register 2     N/A                                     Together with ATU Base Address Register 2 defines the inbound translation window 2 from the PCI bus for DACs.
 1650 **  Inbound ATU Base Address Register 3           Inbound ATU Limit Register 3            Defines the inbound translation window 3 from the PCI bus.
 1651 **  Inbound ATU Upper Base Address Register 3     N/A                                     Together with ATU Base Address Register 3 defines the inbound translation window 3 from the PCI bus for DACs.
 1652 **                                                                                        NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
 1653 **  Expansion ROM Base Address Register           Expansion ROM Limit Register            Defines the window of addresses used by a bus master for reading from an Expansion ROM.
 1654 **--------------------------------------------------------------------------------------
 1655 **  ATU Inbound Window 1 is not a translate window. 
 1656 **  The ATU does not claim any PCI accesses that fall within this range. 
 1657 **  This window is used to allocate host memory for use by Private Devices. 
 1658 **  When enabled, the ATU interrupts the Intel  XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 
 1659 ***********************************************************************************
 1660 */
 1661 
 1662 /*
 1663 ***********************************************************************************
 1664 **  Inbound ATU Base Address Register 0 - IABAR0
 1665 **
 1666 **  . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) defines the block of memory addresses where the inbound translation window 0 begins. 
 1667 **  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 1668 **  . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size.
 1669 **  . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 
 1670 **    depending on the value located within the IALR0. 
 1671 **    This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
 1672 **    The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
 1673 **    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 1674 **  Warning: 
 1675 **    When IALR0 is cleared prior to host configuration:
 1676 **                          the user should also clear the Prefetchable Indicator and the Type Indicator. 
 1677 **    Assuming IALR0 is not cleared:
 1678 **                          a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
 1679 **                             when the Prefetchable Indicator is cleared prior to host configuration, 
 1680 **                             the user should also set the Type Indicator for 32 bit addressability.
 1681 **                          b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification,
 1682 **                             when the Prefetchable Indicator is set prior to host configuration, the user
 1683 **                             should also set the Type Indicator for 64 bit addressability. 
 1684 **                             This is the default for IABAR0.
 1685 **  -----------------------------------------------------------------
 1686 **  Bit       Default                       Description
 1687 **  31:12     00000H                        Translation Base Address 0 - These bits define the actual location the translation function is to respond to when addressed from the PCI bus.
 1688 **  11:04        00H                        Reserved.
 1689 **  03           1 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 1690 **  02:01       10 2                        Type Indicator - Defines the width of the addressability for this memory window:
 1691 **                                                                                              00 - Memory Window is locatable anywhere in 32 bit address space
 1692 **                                                                                              10 - Memory Window is locatable anywhere in 64 bit address space
 1693 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
 1694 **                                                                   The ATU does not occupy I/O space, 
 1695 **                                                                   thus this bit must be zero.
 1696 ***********************************************************************************
 1697 */
 1698 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG                         0x10    /*dword 0x13,0x12,0x11,0x10*/
 1699 #define     ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE                       0x08
 1700 #define     ARCMSR_INBOUND_ATU_MEMORY_WINDOW64                           0x04
 1701 /*
 1702 ***********************************************************************************
 1703 **  Inbound ATU Upper Base Address Register 0 - IAUBAR0
 1704 **
 1705 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 1706 **  Together with the Translation Base Address this register defines the actual location the translation
 1707 **  function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 1708 **  The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 1709 **  Note: 
 1710 **      When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 
 1711 **      the IAUBAR0 register attributes are read-only.
 1712 **  -----------------------------------------------------------------
 1713 **  Bit       Default                       Description
 1714 **  31:0      00000H                        Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the
 1715 **                                                                             actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
 1716 ***********************************************************************************
 1717 */
 1718 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG               0x14    /*dword 0x17,0x16,0x15,0x14*/
 1719 /*
 1720 ***********************************************************************************
 1721 **  Inbound ATU Base Address Register 1 - IABAR1
 1722 **
 1723 **  . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) defines the block of memory addresses where the inbound translation window 1 begins. 
 1724 **  . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
 1725 **  . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 1726 **  . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 
 1727 **  Warning: 
 1728 **    When a non-zero value is not written to IALR1 prior to host configuration, 
 1729 **                          the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 
 1730 **                          This is the default for IABAR1.
 1731 **    Assuming a non-zero value is written to IALR1, 
 1732 **                                      the user may set the Prefetchable Indicator 
 1733 **                                                    or the Type         Indicator:
 1734 **                                              a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address
 1735 **                                                 boundary, when the Prefetchable Indicator is not set prior to host configuration, 
 1736 **                             the user should also leave the Type Indicator set for 32 bit addressability. 
 1737 **                             This is the default for IABAR1.
 1738 **                                              b. when the Prefetchable Indicator is set prior to host configuration, 
 1739 **                             the user should also set the Type Indicator for 64 bit addressability.
 1740 **  -----------------------------------------------------------------
 1741 **  Bit       Default                       Description
 1742 **  31:12     00000H                        Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus.
 1743 **  11:04        00H                        Reserved.
 1744 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 1745 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 1746 **                                                                                              00 - Memory Window is locatable anywhere in 32 bit address space
 1747 **                                                                                              10 - Memory Window is locatable anywhere in 64 bit address space
 1748 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
 1749 **                                                                   The ATU does not occupy I/O space, 
 1750 **                                                                   thus this bit must be zero.
 1751 ***********************************************************************************
 1752 */
 1753 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG                         0x18    /*dword 0x1B,0x1A,0x19,0x18*/
 1754 /*
 1755 ***********************************************************************************
 1756 **  Inbound ATU Upper Base Address Register 1 - IAUBAR1
 1757 **
 1758 **  This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 
 1759 **  Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 
 1760 **  This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
 1761 **  The programmed value within the base address register must comply with the PCI programming
 1762 **  requirements for address alignment. 
 1763 **  When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
 1764 **  from the PCI bus. 
 1765 **  Note: 
 1766 **      When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 
 1767 **      the IAUBAR1 register attributes are read-only. 
 1768 **      This is the default for IABAR1.
 1769 **  -----------------------------------------------------------------
 1770 **  Bit       Default                       Description
 1771 **  31:0      00000H                        Translation Upper Base Address 1 - Together with the Translation Base Address 1 these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes.
 1772 ***********************************************************************************
 1773 */
 1774 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG                   0x1C    /*dword 0x1F,0x1E,0x1D,0x1C*/
 1775 /*
 1776 ***********************************************************************************
 1777 **  Inbound ATU Base Address Register 2 - IABAR2
 1778 **
 1779 **  . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) defines the block of memory addresses where the inbound translation window 2 begins. 
 1780 **  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 1781 **  . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size
 1782 **  . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2.
 1783 **    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 1784 **  Warning: 
 1785 **    When a non-zero value is not written to IALR2 prior to host configuration, 
 1786 **                          the user should not set either the Prefetchable Indicator 
 1787 **                                                      or the Type         Indicator for 64 bit addressability. 
 1788 **                          This is the default for IABAR2.
 1789 **  Assuming a non-zero value is written to IALR2, 
 1790 **                          the user may set the Prefetchable Indicator 
 1791 **                                        or the Type         Indicator:
 1792 **                                              a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 
 1793 **                             when the Prefetchable Indicator is not set prior to host configuration, 
 1794 **                             the user should also leave the Type Indicator set for 32 bit addressability. 
 1795 **                             This is the default for IABAR2.
 1796 **                                              b. when the Prefetchable Indicator is set prior to host configuration, 
 1797 **                             the user should also set the Type Indicator for 64 bit addressability.
 1798 **  -----------------------------------------------------------------
 1799 **  Bit       Default                       Description
 1800 **  31:12     00000H                        Translation Base Address 2 - These bits define the actual location the translation function is to respond to when addressed from the PCI bus.
 1801 **  11:04        00H                        Reserved.
 1802 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 1803 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 1804 **                                                                                              00 - Memory Window is locatable anywhere in 32 bit address space
 1805 **                                                                                              10 - Memory Window is locatable anywhere in 64 bit address space
 1806 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
 1807 **                                                                   The ATU does not occupy I/O space, 
 1808 **                                                                   thus this bit must be zero.
 1809 ***********************************************************************************
 1810 */
 1811 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG                         0x20    /*dword 0x23,0x22,0x21,0x20*/
 1812 /*
 1813 ***********************************************************************************
 1814 **  Inbound ATU Upper Base Address Register 2 - IAUBAR2
 1815 **  
 1816 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 1817 **  Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 1818 **  The programmed value within the base address register must comply with the PCI programming
 1819 **  requirements for address alignment.
 1820 **  Note: 
 1821 **      When the Type indicator of IABAR2 is set to indicate 32 bit addressability,
 1822 **      the IAUBAR2 register attributes are read-only. 
 1823 **      This is the default for IABAR2.
 1824 **  -----------------------------------------------------------------
 1825 **  Bit       Default                       Description
 1826 **  31:0      00000H                        Translation Upper Base Address 2 - Together with the Translation Base Address 2 these bits define the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
 1827 ***********************************************************************************
 1828 */
 1829 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG                   0x24    /*dword 0x27,0x26,0x25,0x24*/
 1830 /*
 1831 ***********************************************************************************
 1832 **  ATU Subsystem Vendor ID Register - ASVIR
 1833 **  -----------------------------------------------------------------
 1834 **  Bit       Default                       Description
 1835 **  15:0      0000H                         Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor.
 1836 ***********************************************************************************
 1837 */
 1838 #define     ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG                   0x2C    /*word 0x2D,0x2C*/
 1839 /*
 1840 ***********************************************************************************
 1841 **  ATU Subsystem ID Register - ASIR
 1842 **  -----------------------------------------------------------------
 1843 **  Bit       Default                       Description
 1844 **  15:0      0000H                         Subsystem ID - uniquely identifies the add-in board or subsystem.
 1845 ***********************************************************************************
 1846 */
 1847 #define     ARCMSR_ATU_SUBSYSTEM_ID_REG                  0x2E    /*word 0x2F,0x2E*/
 1848 /*
 1849 ***********************************************************************************
 1850 **  Expansion ROM Base Address Register -ERBAR
 1851 **  -----------------------------------------------------------------
 1852 **  Bit       Default                       Description
 1853 **  31:12     00000H                        Expansion ROM Base Address - These bits define the actual location where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary.
 1854 **  11:01     000H                          Reserved
 1855 **  00        0 2                           Address Decode Enable - This bit field shows the ROM address decoder is enabled or disabled. When cleared, indicates the address decoder is disabled.
 1856 ***********************************************************************************
 1857 */
 1858 #define     ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG                        0x30    /*dword 0x33,0x32,0v31,0x30*/
 1859 #define     ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE                       0x01    
 1860 /*
 1861 ***********************************************************************************
 1862 **  ATU Capabilities Pointer Register - ATU_CAP_PTR
 1863 **  -----------------------------------------------------------------
 1864 **  Bit Default Description
 1865 **  07:00     C0H                           Capability List Pointer - This provides an offset in this function¡¦s configuration space that points to the 80331 PCl Bus Power Management extended capability.
 1866 ***********************************************************************************
 1867 */
 1868 #define     ARCMSR_ATU_CAPABILITY_PTR_REG                    0x34    /*byte*/
 1869 /*
 1870 ***********************************************************************************  
 1871 **  Determining Block Sizes for Base Address Registers
 1872 **  The required address size and type can be determined by writing ones to a base address register and
 1873 **  reading from the registers. By scanning the returned value from the least-significant bit of the base
 1874 **  address registers upwards, the programmer can determine the required address space size. The
 1875 **  binary-weighted value of the first non-zero bit found indicates the required amount of space.
 1876 **  Table 105 describes the relationship between the values read back and the byte sizes the base
 1877 **  address register requires.
 1878 **  As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
 1879 **  (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires
 1880 **  memory address space. Bit three is one, so the memory does supports prefetching. Scanning
 1881 **  upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this
 1882 **  bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space.
 1883 **  The ATU Base Address Registers and the Expansion ROM Base Address Register use their
 1884 **  associated limit registers to enable which bits within the base address register are read/write and
 1885 **  which bits are read only (0). This allows the programming of these registers in a manner similar to
 1886 **  other PCI devices even though the limit is variable.
 1887 **  Table 105. Memory Block Size Read Response
 1888 **  Response After Writing all 1s
 1889 **  to the Base Address Register
 1890 **  Size
 1891 **  (Bytes)
 1892 **  Response After Writing all 1s
 1893 **  to the Base Address Register
 1894 **  Size
 1895 **  (Bytes)
 1896 **  FFFFFFF0H 16 FFF00000H 1 M
 1897 **  FFFFFFE0H 32 FFE00000H 2 M
 1898 **  FFFFFFC0H 64 FFC00000H 4 M
 1899 **  FFFFFF80H 128 FF800000H 8 M
 1900 **  FFFFFF00H 256 FF000000H 16 M
 1901 **  FFFFFE00H 512 FE000000H 32 M
 1902 **  FFFFFC00H 1K FC000000H 64 M
 1903 **  FFFFF800H 2K F8000000H 128 M
 1904 **  FFFFF000H 4K F0000000H 256 M
 1905 **  FFFFE000H 8K E0000000H 512 M
 1906 **  FFFFC000H 16K C0000000H 1 G
 1907 **  FFFF8000H 32K 80000000H 2 G
 1908 **  FFFF0000H 64K
 1909 **  00000000H
 1910 **  Register not
 1911 **  imple-mented,
 1912 **  no
 1913 **  address
 1914 **  space
 1915 **  required.
 1916 **  FFFE0000H 128K
 1917 **  FFFC0000H 256K
 1918 **  FFF80000H 512K
 1919 **  
 1920 ***************************************************************************************  
 1921 */
 1922 
 1923 
 1924 
 1925 /*
 1926 ***********************************************************************************
 1927 **  ATU Interrupt Line Register - ATUILR
 1928 **  -----------------------------------------------------------------
 1929 **  Bit       Default                       Description
 1930 **  07:00       FFH                         Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt
 1931 **                                                               request line connects to the device's PCI interrupt request lines (as specified in the interrupt pin register).
 1932 **                                                               A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨.
 1933 ***********************************************************************************
 1934 */
 1935 #define     ARCMSR_ATU_INTERRUPT_LINE_REG                    0x3C    /*byte*/
 1936 /*
 1937 ***********************************************************************************
 1938 **  ATU Interrupt Pin Register - ATUIPR
 1939 **  -----------------------------------------------------------------
 1940 **  Bit       Default                       Description
 1941 **  07:00       01H                         Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin.
 1942 ***********************************************************************************
 1943 */
 1944 #define     ARCMSR_ATU_INTERRUPT_PIN_REG                     0x3D    /*byte*/
 1945 /*
 1946 ***********************************************************************************
 1947 **  ATU Minimum Grant Register - ATUMGNT
 1948 **  -----------------------------------------------------------------
 1949 **  Bit       Default                       Description
 1950 **  07:00       80H                         This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
 1951 ***********************************************************************************
 1952 */
 1953 #define     ARCMSR_ATU_MINIMUM_GRANT_REG                     0x3E    /*byte*/
 1954 /*
 1955 ***********************************************************************************
 1956 **  ATU Maximum Latency Register - ATUMLAT
 1957 **  -----------------------------------------------------------------
 1958 **  Bit       Default                       Description
 1959 **  07:00       00H                         Specifies frequency (how often) the device needs to access the PCI bus in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement.
 1960 ***********************************************************************************
 1961 */
 1962 #define     ARCMSR_ATU_MAXIMUM_LATENCY_REG                   0x3F    /*byte*/
 1963 /*
 1964 ***********************************************************************************
 1965 **  Inbound Address Translation
 1966 **  
 1967 **  The ATU allows external PCI bus initiators to directly access the internal bus. 
 1968 **  These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 
 1969 **  The process of inbound address translation involves two steps:
 1970 **  1. Address Detection.
 1971 **             ¡E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
 1972 **                within the address windows defined for the inbound ATU.
 1973 **             ¡E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
 1974 **                mode and with Decode A DEVSEL# timing in the PCI-X mode.
 1975 **  2. Address Translation.
 1976 **             ¡E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address.
 1977 **                              The ATU uses the following registers in inbound address window 0 translation:
 1978 **                              ¡E Inbound ATU Base Address Register 0
 1979 **                              ¡E Inbound ATU Limit Register 0
 1980 **                              ¡E Inbound ATU Translate Value Register 0
 1981 **                              The ATU uses the following registers in inbound address window 2 translation:
 1982 **                              ¡E Inbound ATU Base Address Register 2
 1983 **                              ¡E Inbound ATU Limit Register 2
 1984 **                              ¡E Inbound ATU Translate Value Register 2
 1985 **                              The ATU uses the following registers in inbound address window 3 translation:
 1986 **                              ¡E Inbound ATU Base Address Register 3
 1987 **                              ¡E Inbound ATU Limit Register 3
 1988 **                              ¡E Inbound ATU Translate Value Register 3
 1989 **    Note: Inbound Address window 1 is not a translate window. 
 1990 **          Instead, window 1 may be used to allocate host memory for Private Devices.
 1991 **          Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 
 1992 **          thus the host BIOS does not configure window 3.
 1993 **          Window 3 is intended to be used as a special window into local memory for private PCI
 1994 **          agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge.
 1995 **          PCI-to-PCI Bridge in 80331 or
 1996 **          Inbound address detection is determined from the 32-bit PCI address, 
 1997 **          (64-bit PCI address during DACs) the base address register and the limit register. 
 1998 **          In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 
 1999 **  
 2000 **  The algorithm for detection is:
 2001 **  
 2002 **  Equation 1. Inbound Address Detection
 2003 **              When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 
 2004 **              the PCI Address is claimed by the Inbound ATU.
 2005 **  
 2006 **                      The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed
 2007 **                      with the associated inbound limit register. 
 2008 **              When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 
 2009 **              the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU.
 2010 **
 2011 **                      Note:   The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 
 2012 **                                      Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
 2013 **                                      internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the
 2014 **                                      lower 32-bits are used during address translation. 
 2015 **                              The algorithm is:
 2016 **  
 2017 **  
 2018 **  Equation 2. Inbound Translation
 2019 **              Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0].
 2020 **  
 2021 **                      The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the
 2022 **                      bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and
 2023 **                      the result is the internal bus address. This translation mechanism is used for all inbound memory
 2024 **                      read and write commands excluding inbound configuration read and writes. 
 2025 **                      In the PCI mode for inbound memory transactions, the only burst order supported is Linear
 2026 **                      Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase.
 2027 **                      The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode.
 2028 **  example:
 2029 **          Register Values
 2030 **                       Base_Register=3A00 0000H
 2031 **                      Limit_Register=FF80 0000H (8 Mbyte limit value)
 2032 **                      Value_Register=B100 0000H
 2033 **                      Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
 2034 **              
 2035 **              Address Detection (32-bit address)
 2036 **
 2037 **                                              PCI_Address & Limit_Register == Base_Register
 2038 **                                              3A45 012CH  &   FF80 0000H   ==  3A00 0000H
 2039 **
 2040 **                                      ANS: PCI_Address is in the Inbound Translation Window
 2041 **              Address Translation (to get internal bus address)
 2042 **
 2043 **                                              IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg
 2044 **                                              IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H
 2045 **
 2046 **                                      ANS:IB_Address=B145 012CH
 2047 ***********************************************************************************
 2048 */
 2049 
 2050 
 2051 
 2052 /*
 2053 ***********************************************************************************
 2054 **  Inbound ATU Limit Register 0 - IALR0
 2055 **  
 2056 **  Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
 2057 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 2058 **  PCI addresses to internal bus addresses.
 2059 **  The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
 2060 **  address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
 2061 **  bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
 2062 **  Specification, Revision 2.3 for additional information on programming base address registers.
 2063 **  Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a
 2064 **  one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit
 2065 **  within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0
 2066 **  makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of
 2067 **  this programming scheme is that unless a valid value exists within the IALR0, all writes to the
 2068 **  IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only  register.
 2069 **  -----------------------------------------------------------------
 2070 **  Bit       Default                       Description
 2071 **  31:12     FF000H                        Inbound Translation Limit 0 - This readback value determines the memory block size required for
 2072 **                                                                        inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB.
 2073 **  11:00       000H                        Reserved
 2074 ***********************************************************************************
 2075 */
 2076 #define     ARCMSR_INBOUND_ATU_LIMIT0_REG                    0x40    /*dword 0x43,0x42,0x41,0x40*/
 2077 /*
 2078 ***********************************************************************************
 2079 **  Inbound ATU Translate Value Register 0 - IATVR0
 2080 **  
 2081 **  The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
 2082 **  convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
 2083 **  inbound ATU address translation.
 2084 **  -----------------------------------------------------------------
 2085 **  Bit       Default                       Description
 2086 **  31:12     FF000H                        Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 
 2087 **                                          This value must be 64-bit aligned on the internal bus. The default address allows the ATU to access the internal 80331 memory-mapped registers.
 2088 **  11:00       000H                        Reserved
 2089 ***********************************************************************************
 2090 */
 2091 #define     ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG                  0x44    /*dword 0x47,0x46,0x45,0x44*/
 2092 /*
 2093 ***********************************************************************************
 2094 **  Expansion ROM Limit Register - ERLR
 2095 **  
 2096 **  The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines
 2097 **  as Expansion ROM address space. The block size is programmed by writing a value into the ERLR.
 2098 **  Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one
 2099 **  to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within
 2100 **  the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes
 2101 **  the corresponding bit within the ERBAR read/write from PCI.
 2102 **  -----------------------------------------------------------------
 2103 **  Bit       Default                       Description
 2104 **  31:12     000000H                       Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default
 2105 **                                                                value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0.
 2106 **  11:00        000H                       Reserved.
 2107 ***********************************************************************************
 2108 */
 2109 #define     ARCMSR_EXPANSION_ROM_LIMIT_REG                        0x48    /*dword 0x4B,0x4A,0x49,0x48*/
 2110 /*
 2111 ***********************************************************************************
 2112 **  Expansion ROM Translate Value Register - ERTVR
 2113 **  
 2114 **  The Expansion ROM Translate Value Register contains the 80331 internal bus address which the
 2115 **  ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
 2116 **  Expansion ROM address translation.
 2117 **  -----------------------------------------------------------------
 2118 **  Bit       Default                       Description
 2119 **  31:12     00000H                        Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses
 2120 **                                                                            for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus.
 2121 **  11:00       000H                        Reserved
 2122 ***********************************************************************************
 2123 */
 2124 #define     ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG                      0x4C    /*dword 0x4F,0x4E,0x4D,0x4C*/
 2125 /*
 2126 ***********************************************************************************
 2127 **  Inbound ATU Limit Register 1 - IALR1
 2128 **  
 2129 **  Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a
 2130 **  one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit
 2131 **  within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1
 2132 **  makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of
 2133 **  this programming scheme is that unless a valid value exists within the IALR1, all writes to the
 2134 **  IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only
 2135 **  register.
 2136 **  The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
 2137 **  not process any PCI bus transactions to this memory range.
 2138 **  Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
 2139 **  IAUBAR1, and IALR1.
 2140 **  -----------------------------------------------------------------
 2141 **  Bit       Default                       Description
 2142 **  31:12     00000H                        Inbound Translation Limit 1 - This readback value determines the memory block size required for the ATUs memory window 1.
 2143 **  11:00 000H Reserved
 2144 ***********************************************************************************
 2145 */
 2146 #define     ARCMSR_INBOUND_ATU_LIMIT1_REG                         0x50    /*dword 0x53,0x52,0x51,0x50*/
 2147 /*
 2148 ***********************************************************************************
 2149 **  Inbound ATU Limit Register 2 - IALR2
 2150 **  
 2151 **  Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
 2152 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 2153 **  PCI addresses to internal bus addresses.
 2154 **  The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When
 2155 **  determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
 2156 **  register provides the block size requirements for the base address register. The remaining registers
 2157 **  used for performing address translation are discussed in Section 3.2.1.1.
 2158 **  The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
 2159 **  address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
 2160 **  bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
 2161 **  Specification, Revision 2.3 for additional information on programming base address registers.
 2162 **  Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a
 2163 **  one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit
 2164 **  within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2
 2165 **  makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of
 2166 **  this programming scheme is that unless a valid value exists within the IALR2, all writes to the
 2167 **  IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only
 2168 **  register.
 2169 **  -----------------------------------------------------------------
 2170 **  Bit       Default                       Description
 2171 **  31:12     00000H                        Inbound Translation Limit 2 - This readback value determines the memory block size required for the ATUs memory window 2.
 2172 **  11:00       000H                        Reserved
 2173 ***********************************************************************************
 2174 */
 2175 #define     ARCMSR_INBOUND_ATU_LIMIT2_REG                         0x54    /*dword 0x57,0x56,0x55,0x54*/
 2176 /*
 2177 ***********************************************************************************
 2178 **  Inbound ATU Translate Value Register 2 - IATVR2
 2179 **  
 2180 **  The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
 2181 **  convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
 2182 **  inbound ATU address translation.
 2183 **  -----------------------------------------------------------------
 2184 **  Bit       Default                       Description
 2185 **  31:12     00000H                        Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 
 2186 **                                                                            This value must be 64-bit aligned on the internal bus. The default address allows the ATU to access the internal 80331 memory-mapped registers.
 2187 **  11:00       000H                        Reserved
 2188 ***********************************************************************************
 2189 */
 2190 #define     ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG                       0x58    /*dword 0x5B,0x5A,0x59,0x58*/
 2191 /*
 2192 ***********************************************************************************
 2193 **  Outbound I/O Window Translate Value Register - OIOWTVR
 2194 **  
 2195 **  The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
 2196 **  used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a
 2197 **  result of the outbound ATU address translation. 
 2198 **  The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed
 2199 **  length of 64 Kbytes.
 2200 **  -----------------------------------------------------------------
 2201 **  Bit       Default                       Description
 2202 **  31:16     0000H                         Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses.
 2203 **  15:00     0000H                         Reserved
 2204 ***********************************************************************************
 2205 */
 2206 #define     ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG                         0x5C    /*dword 0x5F,0x5E,0x5D,0x5C*/
 2207 /*
 2208 ***********************************************************************************
 2209 **  Outbound Memory Window Translate Value Register 0 -OMWTVR0
 2210 **  
 2211 **  The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
 2212 **  address used to convert 80331 internal bus addresses for outbound transactions. This address is
 2213 **  driven on the PCI bus as a result of the outbound ATU address translation. 
 2214 **  The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length
 2215 **  of 64 Mbytes.
 2216 **  -----------------------------------------------------------------
 2217 **  Bit       Default                       Description
 2218 **  31:26       00H                         Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
 2219 **  25:02     00 0000H                      Reserved
 2220 **  01:00      00 2                         Burst Order - This bit field shows the address sequence during a memory burst. Only linear incrementing mode is supported.
 2221 ***********************************************************************************
 2222 */
 2223 #define     ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG                    0x60    /*dword 0x63,0x62,0x61,0x60*/
 2224 /*
 2225 ***********************************************************************************
 2226 **  Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
 2227 **  
 2228 **  The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
 2229 **  the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
 2230 **  directly address anywhere within the 64-bit host address space. When this register is all-zero, then
 2231 **  a SAC is generated on the PCI bus.
 2232 **  The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed
 2233 **  length of 64 Mbytes.
 2234 **  -----------------------------------------------------------------
 2235 **  Bit       Default                       Description
 2236 **  31:00     0000 0000H                    These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
 2237 ***********************************************************************************
 2238 */
 2239 #define     ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG                    0x64    /*dword 0x67,0x66,0x65,0x64*/
 2240 /*
 2241 ***********************************************************************************
 2242 **  Outbound Memory Window Translate Value Register 1 -OMWTVR1
 2243 **  
 2244 **  The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
 2245 **  address used to convert 80331 internal bus addresses for outbound transactions. This address is
 2246 **  driven on the PCI bus as a result of the outbound ATU address translation. 
 2247 **  The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
 2248 **  of 64 Mbytes.
 2249 **  -----------------------------------------------------------------
 2250 **  Bit       Default                       Description
 2251 **  31:26       00H                         Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
 2252 **  25:02     00 0000H                      Reserved
 2253 **  01:00       00 2                        Burst Order - This bit field shows the address sequence during a memory burst. Only linear incrementing mode is supported.
 2254 ***********************************************************************************
 2255 */
 2256 #define     ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG                    0x68    /*dword 0x6B,0x6A,0x69,0x68*/
 2257 /*
 2258 ***********************************************************************************
 2259 **  Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
 2260 **  
 2261 **  The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
 2262 **  the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
 2263 **  directly address anywhere within the 64-bit host address space. When this register is all-zero, then
 2264 **  a SAC is generated on the PCI bus.
 2265 **  The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
 2266 **  of 64 Mbytes.
 2267 **  -----------------------------------------------------------------
 2268 **  Bit       Default                       Description
 2269 **  31:00    0000 0000H                     These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
 2270 ***********************************************************************************
 2271 */
 2272 #define     ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG                    0x6C    /*dword 0x6F,0x6E,0x6D,0x6C*/
 2273 /*
 2274 ***********************************************************************************
 2275 **  Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
 2276 **  
 2277 **  The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
 2278 **  upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing
 2279 **  Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
 2280 **  address space. When this register is all-zero, then a SAC is generated on the PCI bus.
 2281 **  -----------------------------------------------------------------
 2282 **  Bit       Default                       Description
 2283 **  31:00    0000 0000H                     These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
 2284 ***********************************************************************************
 2285 */
 2286 #define     ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG                     0x78    /*dword 0x7B,0x7A,0x79,0x78*/
 2287 /*
 2288 ***********************************************************************************
 2289 **  ATU Configuration Register - ATUCR
 2290 **  
 2291 **  The ATU Configuration Register controls the outbound address translation for address translation
 2292 **  unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard
 2293 **  timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
 2294 **  interrupt enabling.
 2295 **  -----------------------------------------------------------------
 2296 **  Bit       Default                       Description
 2297 **  31:20       00H                         Reserved
 2298 **  19          0 2                         ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a
 2299 **                                                                                                              current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read
 2300 **                                                                                                              transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not
 2301 **                                                                                                              applicable in the PCI-X mode.
 2302 **  18          0 2                         Direct Addressing Upper 2Gbytes Translation Enable - When set, with Direct Addressing enabled (bit 7 of the ATUCR set), the ATU forwards internal bus cycles with an address between 0000.0040H and
 2303 **                                                          7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). When clear, no translation occurs.
 2304 **  17          0 2                         Reserved
 2305 **  16          0 2                         SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until
 2306 **                                                          cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified.
 2307 **  15          0 2                         ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and
 2308 **                                                          discarded the delayed completion transaction within the queue. When clear, no timer has expired.
 2309 **  14:10    00000 2                        Reserved
 2310 **  09          0 2                         SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt
 2311 **                                                          when the ATU detects that SERR# was asserted. When clear, the Intel XScale core is not interrupted when SERR# is detected.
 2312 **  08          0 2                         Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
 2313 **                                                                                                              Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to
 2314 **                                                                                                              the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of the ATUCR.
 2315 **  07:04    0000 2                         Reserved
 2316 **  03          0 2                         ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start
 2317 **                                                          BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 in the ATUBISTR register.
 2318 **  02          0 2                         Reserved
 2319 **  01          0 2                         Outbound ATU Enable - When set, enables the outbound address translation unit. When cleared, disables the outbound ATU.
 2320 **  00          0 2                         Reserved
 2321 ***********************************************************************************
 2322 */
 2323 #define     ARCMSR_ATU_CONFIGURATION_REG                          0x80    /*dword 0x83,0x82,0x81,0x80*/
 2324 /*
 2325 ***********************************************************************************
 2326 **  PCI Configuration and Status Register - PCSR
 2327 **  
 2328 **  The PCI Configuration and Status Register has additional bits for controlling and monitoring
 2329 **  various features of the PCI bus interface.
 2330 **  -----------------------------------------------------------------
 2331 **  Bit       Default                       Description
 2332 **  31:19      0000H                        Reserved
 2333 **  18          0 2                         Detected Address or Attribute Parity Error - set when a parity error is detected during either the address
 2334 **                                                                                                              or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error
 2335 **                                                                                                              Response bit is cleared. Set under the following conditions:
 2336 **                                                                                                              ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
 2337 **  17:16  Varies with
 2338 **                                                                              external state
 2339 **                                                                              of DEVSEL#,
 2340 **                                                                              STOP#, and
 2341 **                                                                              TRDY#,
 2342 **                                                                              during
 2343 **                                                                              P_RST#
 2344 **                                                                              PCI-X capability - These two bits define the mode of the PCI bus (conventional or PCI-X) as well as the
 2345 **                                                                              operating frequency in the case of PCI-X mode.
 2346 **                                                                              00 - Conventional PCI mode
 2347 **                                                                              01 - PCI-X 66
 2348 **                                                                              10 - PCI-X 100
 2349 **                                                                              11 - PCI-X 133
 2350 **                                                                              As defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, the operating
 2351 **                                                                              mode is determined by an initialization pattern on the PCI bus during P_RST# assertion:
 2352 **                                                                              DEVSEL# STOP# TRDY# Mode
 2353 **                                                                              Deasserted Deasserted Deasserted Conventional
 2354 **                                                                              Deasserted Deasserted Asserted PCI-X 66
 2355 **                                                                              Deasserted Asserted Deasserted PCI-X 100
 2356 **                                                                              Deasserted Asserted Asserted PCI-X 133
 2357 **                                                                              All other patterns are reserved.
 2358 **  15          0 2
 2359 **                                                                              Outbound Transaction Queue Busy:
 2360 **                                                                                  0=Outbound Transaction Queue Empty
 2361 **                                                                                  1=Outbound Transaction Queue Busy
 2362 **  14          0 2
 2363 **                                                                              Inbound Transaction Queue Busy:
 2364 **                                                                                  0=Inbound Transaction Queue Empty
 2365 **                                                                                  1=Inbound Transaction Queue Busy
 2366 **  13          0 2                         Reserved.
 2367 **  12          0 2
 2368 **                                                                              Discard Timer Value - This bit controls the time-out value for the four discard timers attached to the queues holding read data. 
 2369 **                                                         A value of 0 indicates the time-out value is 2 15 clocks. 
 2370 **                                                         A value of 1 indicates the time-out value is 2 10 clocks.
 2371 **  11          0 2                         Reserved.
 2372 **  10      Varies with
 2373 **                                                                              external state
 2374 **                                                                              of M66EN
 2375 **                                                                              during
 2376 **                                                                              P_RST#
 2377 **                                                                              Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in
 2378 **                                                                              Conventional PCI mode by the assertion of M66EN during bus initialization. When clear, the interface
 2379 **                                                                              has been initialized as a 33 MHz bus.
 2380 **                                                                              NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is
 2381 **                                                                              operating in PCI-X mode.
 2382 **  09          0 2                         Reserved
 2383 **  08      Varies with
 2384 **                                                                              external state
 2385 **                                                                              of REQ64#
 2386 **                                                                              during
 2387 **                                                                              P_RST#
 2388 **                                                                              PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been configured as 64-bit capable by
 2389 **                                                                              the assertion of REQ64# on the rising edge of P_RST#. When set, the PCI interface is configured as
 2390 **                                                                              32-bit only.
 2391 **  07:06      00 2                         Reserved.
 2392 **  05         0 2                                              Reset Internal Bus - This bit controls the reset of the Intel XScale core and all units on the internal
 2393 **                                                                                                      bus. In addition to the internal bus initialization, this bit triggers the assertion of the M_RST# pin for
 2394 **                                                                                                      initialization of registered DIMMs. When set:
 2395 **                                                                                                      When operating in the conventional PCI mode:
 2396 **                                                                                                      ¡E All current PCI transactions being mastered by the ATU completes, and the ATU master interfaces
 2397 **                                                                                                      proceeds to an idle state. No additional transactions is mastered by these units until the internal bus
 2398 **                                                                                                      reset is complete.
 2399 **                                                                                                      ¡E All current transactions being slaved by the ATU on either the PCI bus or the internal bus
 2400 **                                                                                                      completes, and the ATU target interfaces proceeds to an idle state. All future slave transactions
 2401 **                                                                                                      master aborts, with the exception of the completion cycle for the transaction that set the Reset
 2402 **                                                                                                      Internal Bus bit in the PCSR.
 2403 **                                                                                                      ¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) is set, the
 2404 **                                                                                                      Intel XScale core is held in reset when the internal bus reset is complete.
 2405 **                                                                                                      ¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32 Internal Bus clocks.
 2406 **                                                                                                      ¡E The 80331 hardware clears this bit after the reset operation completes.
 2407 **                                                                                                      When operating in the PCI-X mode:
 2408 **                                                                                                      The ATU hardware responds the same as in Conventional PCI-X mode. However, this may create a
 2409 **                                                                                                      problem in PCI-X mode for split requests in that there may still be an outstanding split completion that the
 2410 **                                                                                                      ATU is either waiting to receive (Outbound Request) or initiate (Inbound Read Request). For a cleaner
 2411 **                                                                                                      internal bus reset, host software can take the following steps prior to asserting Reset Internal bus:
 2412 **                                                                                                      1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in
 2413 **                                                                                                      the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued.
 2414 **                                                                                                      2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction
 2415 **                                                                                                      queue busy bits to be clear.
 2416 **                                                                                                      3. Set the Reset Internal Bus bit
 2417 **                                                                                                      As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode,
 2418 **                                                                                                      however the user is now assured that the ATU no longer has any pending inbound or outbound split
 2419 **                                                                                                      completion transactions.
 2420 **                                                                                                      NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is
 2421 **                                                                                                      guaranteed that any prior configuration cycles have properly completed since there is only a one
 2422 **                                                                                                      deep transaction queue for configuration transaction requests. The ATU sends the appropriate
 2423 **                                                                                                  Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset.
 2424 **  04      0 2                                                 Bus Master Indicator Enable: Provides software control for the Bus Master Indicator signal P_BMI used
 2425 **                                                                                                      for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and
 2426 **                                                                                                      central resource/arbiter disabled (BRG_EN =low, ARB_EN=low).
 2427 **  03          Varies with
 2428 **                                                                                                      external state
 2429 **                                                                                                      of PRIVDEV
 2430 **                                                                                                      during
 2431 **                                                                                                      P_RST#
 2432 **                                                                                                      Private Device Enable - This bit indicates the state of the reset strap which enables the private device
 2433 **                                                                                                      control mechanism within the PCI-to-PCI Bridge SISR configuration register.
 2434 **                                                                                                      0=Private Device control Disabled - SISR register bits default to zero
 2435 **                                                                                                      1=Private Device control Enabled - SISR register bits default to one
 2436 **      02              Varies with
 2437 **                                                                                                      external state
 2438 **                                                                                                      of RETRY
 2439 **                                                                                                      during
 2440 **                                                                                                      P_RST#
 2441 **                                                                                                      Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all
 2442 **                                                                                                      configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate
 2443 **                                                                                                      configuration cycles.
 2444 **                                                                                                      The default condition for this bit is based on the external state of the RETRY pin at the rising edge of
 2445 **                                                                                                      P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is
 2446 **                                                                                                      low, the bit is cleared.
 2447 **  01          Varies with
 2448 **                                                                                                      external state
 2449 **                                                                                                      of
 2450 **                                                                                                      CORE_RST#
 2451 **                                                                                                      during
 2452 **                                                                                                      P_RST#
 2453 **                                                                                                      Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is
 2454 **                                                                                                      asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is
 2455 **                                                                                                      being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 
 2456 **                                                                                                      XScale  core reset.
 2457 **                                                                                                      The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge
 2458 **                                                                                                      of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is
 2459 **                                                                                                      high, the bit is clear.
 2460 **  00          Varies with
 2461 **                                                                                                      external state
 2462 **                                                                                                      of PRIVMEM
 2463 **                                                                                                      during
 2464 **                                                                                                      P_RST#
 2465 **                                                                                                      Private Memory Enable - This bit indicates the state of the reset strap which enables the private device
 2466 **                                                                                                      control mechanism within the PCI-to-PCI Bridge SDER configuration register.
 2467 **                                                                                                      0=Private Memory control Disabled - SDER register bit 2 default to zero
 2468 **                                                                                                      1=Private Memory control Enabled - SDER register bits 2 default to one
 2469 ***********************************************************************************
 2470 */
 2471 #define     ARCMSR_PCI_CONFIGURATION_STATUS_REG                   0x84    /*dword 0x87,0x86,0x85,0x84*/
 2472 /*
 2473 ***********************************************************************************
 2474 **  ATU Interrupt Status Register - ATUISR
 2475 **  
 2476 **  The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
 2477 **  interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit
 2478 **  of the 80331. All bits in this register are Read/Clear.
 2479 **  Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register
 2480 **  (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set
 2481 **  by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The
 2482 **  conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this
 2483 **  register.
 2484 **  Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core.
 2485 **  -----------------------------------------------------------------
 2486 **  Bit       Default                       Description
 2487 **  31:18      0000H                        Reserved
 2488 **  17          0 2                         VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR
 2489 **                                                                                                              register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set,
 2490 **                                                                                                              this bit results in the assertion of the ATU Configure Register Write Interrupt.
 2491 **  16          0 2                         Reserved
 2492 **  15          0 2                         ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register.
 2493 **                                                          When set, this bit results in the assertion of the ATU Configure Register Write Interrupt.
 2494 **  14          0 2                         ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write
 2495 **                                                                                                              occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these
 2496 **                                                                                                              registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU
 2497 **                                                                                                              Configure Register Write Interrupt.
 2498 **  13          0 2                         Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion
 2499 **                                                          Message on the PCI Bus with the Split Completion Error attribute bit set.
 2500 **  12          0 2                         Received Split Completion Error Message - This bit is set when the device receives a Split Completion
 2501 **                                                          Message from the PCI Bus with the Split Completion Error attribute bit set.
 2502 **  11          0 2                         Power State Transition - When the Power State Field of the ATU Power Management Control/Status
 2503 **                                                                                                              Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and
 2504 **                                                                                                              the ATU Power State Transition Interrupt mask bit is cleared, this bit is set.
 2505 **  10          0 2                         P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU.
 2506 **  09          0 2                         Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD
 2507 **                                                                                                              register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
 2508 **                                                                                                              ¡E Write Data Parity Error when the ATU is a target (inbound write).
 2509 **                                                                                                              ¡E Read Data Parity Error when the ATU is an initiator (outbound read).
 2510 **                                                                                                              ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
 2511 **  08          0 2                         ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor
 2512 **                                                                                                              has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR
 2513 **                                                                                                              register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR
 2514 **                                                                                                              register bits 3:0.
 2515 **                                                                                                              Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion
 2516 **                                                                                                              of the ATU Configure Register Write Interrupt.
 2517 **  07          0 2                         Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort.
 2518 **  06:05      00 2                         Reserved.
 2519 **  04          0 2                         P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU.
 2520 **  03          0 2                         PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort.
 2521 **  02          0 2                         PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort.
 2522 **  01          0 2                         PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort.
 2523 **  00          0 2                         PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following
 2524 **                                                                                                              conditions:
 2525 **                                                                                                              ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
 2526 **                                                                                                              ¡E And the ATU acted as the requester for the operation in which the error occurred.
 2527 **                                                                                                              ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
 2528 **                                                                                                              ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
 2529 **                                                                                                              ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
 2530 ***********************************************************************************
 2531 */
 2532 #define     ARCMSR_ATU_INTERRUPT_STATUS_REG                       0x88    /*dword 0x8B,0x8A,0x89,0x88*/
 2533 /*
 2534 ***********************************************************************************
 2535 **  ATU Interrupt Mask Register - ATUIMR
 2536 **  
 2537 **  The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts
 2538 **  generated by the ATU.
 2539 **  -----------------------------------------------------------------
 2540 **  Bit       Default                       Description
 2541 **  31:15     0 0000H                       Reserved
 2542 **  14        0 2                           VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the
 2543 **                                                                              ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register.
 2544 **                                                                              0=Not Masked
 2545 **                                                                              1=Masked
 2546 **  13        0 2                           Reserved
 2547 **  12        0 2                           Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the
 2548 **                                                                              ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register
 2549 **                                                                              except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR.
 2550 **                                                                              0=Not Masked
 2551 **                                                                              1=Masked
 2552 **  11        1 2                           ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and
 2553 **                                                                                                              generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the
 2554 **                                                                                                              IABAR1 register or the IAUBAR1 register.
 2555 **                                                                                                              0=Not Masked
 2556 **                                                                                                              1=Masked
 2557 **  10        0 2                           Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and
 2558 **                                                                                                              generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message.
 2559 **                                                                                                              0=Not Masked
 2560 **                                                                                                              1=Masked
 2561 **  09        0 2                           Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR
 2562 **                                                                                                              and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the
 2563 **                                                                                                              PCIXSR being set.
 2564 **                                                                                                              0=Not Masked
 2565 **                                                                                                              1=Masked
 2566 **  08        1 2                           Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the
 2567 **                                                                                                              ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the
 2568 **                                                                                                              ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
 2569 **                                                                                                              0=Not Masked
 2570 **                                                                                                              1=Masked
 2571 **  07        0 2                           ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of
 2572 **                                                                                                              the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR.
 2573 **                                                                                                              0=Not Masked
 2574 **                                                                                                              1=Masked
 2575 **  06        0 2                           ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the
 2576 **                                                                                                              ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set.
 2577 **                                                                                                              0=Not Masked
 2578 **                                                                                                              1=Masked
 2579 **                                                                                                              NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master.
 2580 **  05        0 2                           ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the
 2581 **                                                                                                              ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set.
 2582 **                                                                                                              0=Not Masked
 2583 **                                                                                                              1=Masked
 2584 **  04        0 2                           ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error
 2585 **                                                                                                              generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set
 2586 **                                                                                                              0=Not Masked
 2587 **                                                                                                              1=Masked
 2588 **  03        0 2                           ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation
 2589 **                                                                                                              of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set.
 2590 **                                                                                                              0=Not Masked
 2591 **                                                                                                              1=Masked
 2592 **  02        0 2                           ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation
 2593 **                                                                                                              of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set.
 2594 **                                                                                                              0=Not Masked
 2595 **                                                                                                              1=Masked
 2596 **  01        0 2                           ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the
 2597 **                                                                                                              ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an
 2598 **                                                                                                              inbound write transaction.
 2599 **                                                                                                              0=SERR# Not Asserted due to error
 2600 **                                                                                                              1=SERR# Asserted due to error
 2601 **  00        0 2                           ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC
 2602 **                                                                                                              error) from the memory controller on the internal bus. In conventional mode, this action only occurs
 2603 **                                                                                                              during an inbound read transaction where the data phase that was target aborted on the internal bus is
 2604 **                                                                                                              actually requested from the inbound read queue.
 2605 **                                                                                                              0=Disconnect with data (the data being up to 64 bits of 1¡¦s)
 2606 **                                                                                                              1=Target Abort
 2607 **                                                                                                              NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h -
 2608 **                                                                                                              completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
 2609 **                                                                                                              independent of the setting of this bit.
 2610 *********************************************************************************** 
 2611 */
 2612 #define     ARCMSR_ATU_INTERRUPT_MASK_REG                         0x8C    /*dword 0x8F,0x8E,0x8D,0x8C*/
 2613 /*
 2614 ***********************************************************************************
 2615 **  Inbound ATU Base Address Register 3 - IABAR3
 2616 **  
 2617 **  . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block of memory addresses where the inbound translation window 3 begins. 
 2618 **  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 2619 **  . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size.
 2620 **  . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 
 2621 **    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
 2622 **  Note: 
 2623 **      Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 
 2624 **      IABAR3 is not configured by the host during normal system initialization.
 2625 **  Warning: 
 2626 **    When a non-zero value is not written to IALR3, 
 2627 **                          the user should not set either the Prefetchable Indicator 
 2628 **                                                      or the Type         Indicator for 64 bit addressability.
 2629 **                          This is the default for IABAR3. 
 2630 **  Assuming a non-zero value is written to IALR3,
 2631 **                          the user may set the Prefetchable Indicator 
 2632 **                                        or the Type         Indicator:
 2633 **                                              a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
 2634 **                             when the Prefetchable Indicator is not set, 
 2635 **                             the user should also leave the Type Indicator set for 32 bit addressability.
 2636 **                             This is the default for IABAR3.
 2637 **                                              b. when the Prefetchable Indicator is set, 
 2638 **                             the user should also set the Type Indicator for 64 bit addressability.
 2639 **  -----------------------------------------------------------------
 2640 **  Bit       Default                       Description
 2641 **  31:12     00000H                        Translation Base Address 3 - These bits define the actual location the translation function is to respond to when addressed from the PCI bus.
 2642 **  11:04        00H                        Reserved.
 2643 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 2644 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 2645 **                                                                                              00 - Memory Window is locatable anywhere in 32 bit address space
 2646 **                                                                                              10 - Memory Window is locatable anywhere in 64 bit address space
 2647 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address.
 2648 **                                                                   The ATU does not occupy I/O space, 
 2649 **                                                                   thus this bit must be zero.
 2650 ***********************************************************************************
 2651 */
 2652 #define     ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG                          0x90    /*dword 0x93,0x92,0x91,0x90*/
 2653 /*
 2654 ***********************************************************************************
 2655 **  Inbound ATU Upper Base Address Register 3 - IAUBAR3
 2656 **  
 2657 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 2658 **  Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 2659 **  The programmed value within the base address register must comply with the PCI programming
 2660 **  requirements for address alignment.
 2661 **  Note: 
 2662 **      When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 
 2663 **      the IAUBAR3 register attributes are read-only. 
 2664 **      This is the default for IABAR3.
 2665 **  -----------------------------------------------------------------
 2666 **  Bit       Default                       Description
 2667 **  31:0      00000H                        Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
 2668 ***********************************************************************************
 2669 */
 2670 #define     ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG                    0x94    /*dword 0x97,0x96,0x95,0x94*/
 2671 /*
 2672 ***********************************************************************************
 2673 **  Inbound ATU Limit Register 3 - IALR3
 2674 **  
 2675 **  Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
 2676 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 2677 **  PCI addresses to internal bus addresses.
 2678 **  The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When
 2679 **  determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
 2680 **  register provides the block size requirements for the base address register. The remaining registers
 2681 **  used for performing address translation are discussed in Section 3.2.1.1.
 2682 **  The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
 2683 **  address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
 2684 **  bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
 2685 **  Specification, Revision 2.3 for additional information on programming base address registers.
 2686 **  Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a
 2687 **  one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit
 2688 **  within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3
 2689 **  makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of
 2690 **  this programming scheme is that unless a valid value exists within the IALR3, all writes to the
 2691 **  IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only
 2692 **  register.
 2693 **  -----------------------------------------------------------------
 2694 **  Bit       Default                       Description
 2695 **  31:12     00000H                        Inbound Translation Limit 3 - This readback value determines the memory block size required for the ATUs memory window 3.
 2696 **  11:00       000H                        Reserved
 2697 ***********************************************************************************
 2698 */
 2699 #define     ARCMSR_INBOUND_ATU_LIMIT3_REG                         0x98    /*dword 0x9B,0x9A,0x99,0x98*/
 2700 /*
 2701 ***********************************************************************************
 2702 **  Inbound ATU Translate Value Register 3 - IATVR3
 2703 **  
 2704 **  The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
 2705 **  convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
 2706 **  inbound ATU address translation.
 2707 **  -----------------------------------------------------------------
 2708 **  Bit       Default                       Description
 2709 **  31:12     00000H                        Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 
 2710 **                                                          This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
 2711 **                                                          access the internal 80331 memory-mapped registers.
 2712 **  11:00       000H                        Reserved
 2713 ***********************************************************************************
 2714 */
 2715 #define     ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG                       0x9C    /*dword 0x9F,0x9E,0x9D,0x9C*/
 2716 /*
 2717 ***********************************************************************************
 2718 **  Outbound Configuration Cycle Address Register - OCCAR
 2719 **  
 2720 **  The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
 2721 **  cycle address. The Intel XScale core writes the PCI configuration cycles address which then
 2722 **  enables the outbound configuration read or write. The Intel XScale core then performs a read or
 2723 **  write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the
 2724 **  PCI bus.
 2725 **  Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently
 2726 **  for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
 2727 **  Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
 2728 **  the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears
 2729 **  bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
 2730 **  Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
 2731 **  -----------------------------------------------------------------
 2732 **  Bit       Default                       Description
 2733 **  31:00    0000 0000H                     Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound configuration read or write cycle.
 2734 ***********************************************************************************
 2735 */
 2736 #define     ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG                       0xA4    /*dword 0xA7,0xA6,0xA5,0xA4*/
 2737 /*
 2738 ***********************************************************************************
 2739 **  Outbound Configuration Cycle Data Register - OCCDR
 2740 **  
 2741 **  The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write
 2742 **  on the PCI bus. The register is logical rather than physical meaning that it is an address not a
 2743 **  register. The Intel XScale core reads or writes the data registers memory-mapped address to
 2744 **  initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a
 2745 **  configuration write, the data is latched from the internal bus and forwarded directly to the OWQ.
 2746 **  For a read, the data is returned directly from the ORQ to the Intel XScale core and is never
 2747 **  actually entered into the data register (which does not physically exist).
 2748 **  The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value
 2749 **  within the ATU configuration space.
 2750 **  -----------------------------------------------------------------
 2751 **  Bit       Default                       Description
 2752 **  31:00    0000 0000H                     Configuration Cycle Data - These bits define the data used during an outbound configuration read or write cycle.
 2753 ***********************************************************************************
 2754 */
 2755 #define     ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG                          0xAC    /*dword 0xAF,0xAE,0xAD,0xAC*/
 2756 /*
 2757 ***********************************************************************************
 2758 **  VPD Capability Identifier Register - VPD_CAPID
 2759 **  
 2760 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 2761 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 2762 **  Capability contained in that header. In the case of the 80331, this is the VPD extended capability
 2763 **  with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3.
 2764 **  -----------------------------------------------------------------
 2765 **  Bit       Default                       Description
 2766 **  07:00       03H                         Cap_Id - This field with its¡¦ 03H value identifies this item in the linked list of Extended Capability Headers as being the VPD capability registers.
 2767 ***********************************************************************************
 2768 */
 2769 #define     ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG                      0xB8    /*byte*/
 2770 /*
 2771 ***********************************************************************************
 2772 **  VPD Next Item Pointer Register - VPD_NXTP
 2773 **  
 2774 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 2775 **  Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
 2776 **  For the 80331, this the final capability list, and hence, this register is set to 00H.
 2777 **  -----------------------------------------------------------------
 2778 **  Bit       Default                       Description
 2779 **  07:00       00H                         Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
 2780 **                                                          next item in the function¡¦s capability list. Since the VPD capabilities are the last in the linked list of
 2781 **                                                          extended capabilities in the 80331, the register is set to 00H.
 2782 ***********************************************************************************
 2783 */
 2784 #define     ARCMSR_VPD_NEXT_ITEM_PTR_REG                          0xB9    /*byte*/
 2785 /*
 2786 ***********************************************************************************
 2787 **  VPD Address Register - VPD_AR
 2788 **  
 2789 **  The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
 2790 **  accessed. The register is read/write and the initial value at power-up is indeterminate.
 2791 **  A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use
 2792 **  the Flag setting to determine whether the configuration write was intended to initiate a read or
 2793 **  write of the VPD through the VPD Data Register.
 2794 **  -----------------------------------------------------------------
 2795 **  Bit       Default                       Description
 2796 **  15          0 2                         Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage
 2797 **                                                          component has completed. Please see Section 3.9, ¡§Vital Product Data¡¨ on page 201 for more details on
 2798 **                                                          how the 80331 handles the data transfer.
 2799 **  14:0       0000H                        VPD Address - This register is written to set the DWORD-aligned byte address used to read or write
 2800 **                                                          Vital Product Data from the VPD storage component.
 2801 ***********************************************************************************
 2802 */
 2803 #define     ARCMSR_VPD_ADDRESS_REG                        0xBA    /*word 0xBB,0xBA*/
 2804 /*
 2805 ***********************************************************************************
 2806 **  VPD Data Register - VPD_DR
 2807 **  
 2808 **  This register is used to transfer data between the 80331 and the VPD storage component.
 2809 **  -----------------------------------------------------------------
 2810 **  Bit       Default                       Description
 2811 **  31:00      0000H                        VPD Data - Four bytes are always read or written through this register to/from the VPD storage component.
 2812 ***********************************************************************************
 2813 */
 2814 #define     ARCMSR_VPD_DATA_REG                   0xBC    /*dword 0xBF,0xBE,0xBD,0xBC*/
 2815 /*
 2816 ***********************************************************************************
 2817 **  Power Management Capability Identifier Register -PM_CAPID
 2818 **  
 2819 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 2820 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 2821 **  Capability contained in that header. In the case of the 80331, this is the PCI Bus Power
 2822 **  Management extended capability with an ID of 01H as defined by the PCI Bus Power Management
 2823 **  Interface Specification, Revision 1.1.
 2824 **  -----------------------------------------------------------------
 2825 **  Bit       Default                       Description
 2826 **  07:00       01H                         Cap_Id - This field with its¡¦ 01H value identifies this item in the linked list of Extended Capability Headers as being the PCI Power Management Registers.
 2827 ***********************************************************************************
 2828 */
 2829 #define     ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG                     0xC0    /*byte*/
 2830 /*
 2831 ***********************************************************************************
 2832 **  Power Management Next Item Pointer Register - PM_NXTP
 2833 **  
 2834 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 2835 **  Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
 2836 **  For the 80331, the next capability (MSI capability list) is located at off-set D0H.
 2837 **  -----------------------------------------------------------------
 2838 **  Bit       Default                       Description
 2839 **  07:00       D0H                         Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
 2840 **                                                          next item in the function¡¦s capability list which in the 80331 is the MSI extended capabilities header.
 2841 ***********************************************************************************
 2842 */
 2843 #define     ARCMSR_POWER_NEXT_ITEM_PTR_REG                        0xC1    /*byte*/
 2844 /*
 2845 ***********************************************************************************
 2846 **  Power Management Capabilities Register - PM_CAP
 2847 **  
 2848 **  Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
 2849 **  Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
 2850 **  information on the capabilities of the ATU function related to power management.
 2851 **  -----------------------------------------------------------------
 2852 **  Bit       Default                       Description
 2853 **  15:11   00000 2                         PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# is not supported by the 80331.
 2854 **  10          0 2                         D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State
 2855 **  9           1 2                         D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State
 2856 **  8:6       000 2                         Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the
 2857 **                                                          3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1
 2858 **  5           0 2                         DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence
 2859 **                                                          following the transition to the D0 uninitialized state.
 2860 **  4           0 2                         Reserved.
 2861 **  3           0 2                         PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 .
 2862 **  2:0       010 2                         Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management Interface Specification, Revision 1.1
 2863 ***********************************************************************************
 2864 */
 2865 #define     ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG                        0xC2    /*word 0xC3,0xC2*/
 2866 /*
 2867 ***********************************************************************************
 2868 **  Power Management Control/Status Register - PM_CSR
 2869 **  
 2870 **  Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
 2871 **  Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
 2872 **  interface for the power management extended capability.
 2873 **  -----------------------------------------------------------------
 2874 **  Bit       Default                       Description
 2875 **  15          0 2                         PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not supported by the 80331.
 2876 **  14:9        00H                         Reserved
 2877 **  8           0 2                         PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# generation from any power state.
 2878 **  7:2    000000 2                         Reserved
 2879 **  1:0        00 2                         Power State - This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the values is:
 2880 **                                                                                                              00 2 - D0
 2881 **                                                                                                              01 2 - D1
 2882 **                                                                                                              10 2 - D2 (Unsupported)
 2883 **                                                                                                              11 2 - D3 hot
 2884 **                                                                                                              The 80331 supports only the D0 and D3 hot states.
 2885 **  
 2886 ***********************************************************************************
 2887 */
 2888 #define     ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG                    0xC4    /*word 0xC5,0xC4*/
 2889 /*
 2890 ***********************************************************************************
 2891 **  PCI-X Capability Identifier Register - PX_CAPID
 2892 **  
 2893 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 2894 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 2895 **  Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with
 2896 **  an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
 2897 **  -----------------------------------------------------------------
 2898 **  Bit       Default                       Description
 2899 **  07:00       07H                         Cap_Id - This field with its¡¦ 07H value identifies this item in the linked list of Extended Capability Headers as being the PCI-X capability registers.
 2900 ***********************************************************************************
 2901 */
 2902 #define     ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG                         0xE0    /*byte*/
 2903 /*
 2904 ***********************************************************************************
 2905 **  PCI-X Next Item Pointer Register - PX_NXTP
 2906 **  
 2907 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 2908 **  Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
 2909 **  By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults
 2910 **  to 00H.
 2911 **  However, this register may be written to B8H prior to host configuration to include the VPD
 2912 **  capability located at off-set B8H.
 2913 **  Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may
 2914 **  produce unpredictable system behavior.
 2915 **  In order to guarantee that this register is written prior to host configuration, the 80331 must be
 2916 **  initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically,
 2917 **  the Intel XScale core would be enabled to boot immediately following P_RST# assertion in
 2918 **  this case (bit 1 of PCSR), as well. Please see Table 125, ¡§PCI Configuration and Status Register -
 2919 **  PCSR¡¨ on page 253 for more details on the 80331 initialization modes.
 2920 **  -----------------------------------------------------------------
 2921 **  Bit       Default                       Description
 2922 **  07:00       00H                         Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
 2923 **                                                                                                              next item in the function¡¦s capability list. Since the PCI-X capabilities are the last in the linked list of
 2924 **                                                                                                              extended capabilities in the 80331, the register is set to 00H.
 2925 **                                                                                                              However, this field may be written prior to host configuration with B8H to extend the list to include the
 2926 **                                                                                                              VPD extended capabilities header.
 2927 ***********************************************************************************
 2928 */
 2929 #define     ARCMSR_PCIX_NEXT_ITEM_PTR_REG                         0xE1    /*byte*/
 2930 /*
 2931 ***********************************************************************************
 2932 **  PCI-X Command Register - PX_CMD
 2933 **  
 2934 **  This register controls various modes and features of ATU and Message Unit when operating in the
 2935 **  PCI-X mode.
 2936 **  -----------------------------------------------------------------
 2937 **  Bit       Default                       Description
 2938 **  15:7     000000000 2                    Reserved.
 2939 **  6:4        011 2                        Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
 2940 **                                                                                                              the device is permitted to have outstanding at one time.
 2941 **                                                                                                              Register Maximum Outstanding
 2942 **                                                                                                              0 1
 2943 **                                                                                                              1 2
 2944 **                                                                                                              2 3
 2945 **                                                                                                              3 4
 2946 **                                                                                                              4 8
 2947 **                                                                                                              5 12
 2948 **                                                                                                              6 16
 2949 **                                                                                                              7 32
 2950 **  3:2        00 2                         Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
 2951 **                                                          initiating a Sequence with one of the burst memory read commands.
 2952 **                                                                                                              Register Maximum Byte Count
 2953 **                                                                                                              0 512
 2954 **                                                                                                              1 1024
 2955 **                                                                                                              2 2048
 2956 **                                                                                                              3 4096
 2957 **                                                                                                              1 0 2
 2958 **                                                                                                              Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes
 2959 **                                                                                                              of Transactions.
 2960 **  0          0 2                          Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to
 2961 **                                                          recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts
 2962 **                                                          SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set.
 2963 ***********************************************************************************
 2964 */
 2965 #define     ARCMSR_PCIX_COMMAND_REG                       0xE2    /*word 0xE3,0xE2*/
 2966 /*
 2967 ***********************************************************************************
 2968 **  PCI-X Status Register - PX_SR
 2969 **  
 2970 **  This register identifies the capabilities and current operating mode of ATU, DMAs and Message
 2971 **  Unit when operating in the PCI-X mode.
 2972 **  -----------------------------------------------------------------
 2973 **  Bit       Default                       Description
 2974 **  31:30       00 2                        Reserved
 2975 **  29           0 2                        Received Split Completion Error Message - This bit is set when the device receives a Split Completion
 2976 **                                                                                                              Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
 2977 **                                                                                                              writes a 1 to this location.
 2978 **                                                                                                              0=no Split Completion error message received.
 2979 **                                                                                                              1=a Split Completion error message has been received.
 2980 **  28:26      001 2                        Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
 2981 **                                                                                                              of the Maximum Memory Read Byte Count field of the PCIXCMD register:
 2982 **                                                                                                              DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
 2983 **                                                                                                              1 16 512 (Default)
 2984 **                                                                                                              2 32 1024
 2985 **                                                                                                              2 32 2048
 2986 **                                                                                                              2 32 4096
 2987 **  25:23      011 2                        Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions.
 2988 **  22:21       01 2                        Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up to 1024 bytes.
 2989 **  20           1 2                        80331 is a complex device.
 2990 **  19           0 2                        Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s
 2991 **                                                                                                              Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
 2992 **                                                                                                              0=no unexpected Split Completion has been received.
 2993 **                                                                                                              1=an unexpected Split Completion has been received.
 2994 **  18           0 2                        Split Completion Discarded - This bit is set when the device discards a Split Completion because the
 2995 **                                                                                                              requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
 2996 **                                                                                                              Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this
 2997 **                                                                                                              location.
 2998 **                                                                                                              0=no Split Completion has been discarded.
 2999 **                                                                                                              1=a Split Completion has been discarded.
 3000 **                                                                                                              NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read
 3001 **                                                                                                              Requests with Split Responses (Memory or Register) that has ¡§read side effects.¡¨
 3002 **  17           1 2                        80331 is a 133 MHz capable device.
 3003 **  16           1 2 or P_32BITPCI#                     80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, therefore this bit is always set.
 3004 **                                                      80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 
 3005 **                                                      This strap, by default, identifies the add in card based on 80331 with bridge disabled as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
 3006 **                                                                                                              0=The bus is 32 bits wide.
 3007 **                                                                                                              1=The bus is 64 bits wide.
 3008 **  15:8         FFH                        Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus
 3009 **                                                                                                              segment for the device containing this function. The function uses this number as part of its Requester
 3010 **                                                                                                              ID and Completer ID. For all devices other than the source bridge, each time the function is addressed
 3011 **                                                                                                              by a Configuration Write transaction, the function must update this register with the contents of AD[7::0]
 3012 **                                                                                                              of the attribute phase of the Configuration Write, regardless of which register in the function is
 3013 **                                                                                                              addressed by the transaction. The function is addressed by a Configuration Write transaction when all of
 3014 **                                                                                                              the following are true:
 3015 **                                                                                                              1. The transaction uses a Configuration Write command.
 3016 **                                                                                                              2. IDSEL is asserted during the address phase.
 3017 **                                                                                                              3. AD[1::0] are 00b (Type 0 configuration transaction).
 3018 **                                                                                                              4. AD[10::08] of the configuration address contain the appropriate function number.
 3019 **  7:3          1FH                        Device Number - This register is read for diagnostic purposes only. It indicates the number of the device
 3020 **                                                                                                              containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a
 3021 **                                                                                                              Type 0 configuration transaction that is assigned to the device containing this function by the connection
 3022 **                                                                                                              of the system hardware. The system must assign a device number other than 00h (00h is reserved for
 3023 **                                                                                                              the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each
 3024 **                                                                                                              time the function is addressed by a Configuration Write transaction, the device must update this register
 3025 **                                                                                                              with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which
 3026 **                                                                                                              register in the function is addressed by the transaction. The function is addressed by a Configuration
 3027 **                                                                                                              Write transaction when all of the following are true:
 3028 **                                                                                                              1. The transaction uses a Configuration Write command.
 3029 **                                                                                                              2. IDSEL is asserted during the address phase.
 3030 **                                                                                                              3. AD[1::0] are 00b (Type 0 configuration transaction).
 3031 **                                                                                                              4. AD[10::08] of the configuration address contain the appropriate function number.
 3032 **  2:0        000 2                        Function Number - This register is read for diagnostic purposes only. It indicates the number of this
 3033 **                                                                                                              function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0
 3034 **                                                                                                              configuration transaction to which this function responds. The function uses this number as part of its
 3035 **                                                                                                              Requester ID and Completer ID.
 3036 **  
 3037 **************************************************************************
 3038 */
 3039 #define     ARCMSR_PCIX_STATUS_REG                        0xE4    /*dword 0xE7,0xE6,0xE5,0xE4*/
 3040 
 3041 /*
 3042 **************************************************************************
 3043 **                 Inbound Read Transaction
 3044 **  ========================================================================
 3045 **      An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
 3046 **      memory or a 80331 memory-mapped register space. The read transaction is propagated through
 3047 **      the inbound transaction queue (ITQ) and read data is returned through the inbound read queue
 3048 **      (IRQ).
 3049 **      When operating in the conventional PCI mode, all inbound read transactions are processed as
 3050 **      delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
 3051 **      processed as split transactions. The ATUs PCI interface claims the read transaction and forwards
 3052 **      the read request through to the internal bus and returns the read data to the PCI bus. Data flow for
 3053 **      an inbound read transaction on the PCI bus is summarized in the following statements:
 3054 **      ¡E The ATU claims the PCI read transaction when the PCI address is within the inbound
 3055 **      translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
 3056 **      Address Register during DACs) and Inbound Limit Register.
 3057 **      ¡E When operating in the conventional PCI mode, when the ITQ is currently holding transaction
 3058 **      information from a previous delayed read, the current transaction information is compared to
 3059 **      the previous transaction information (based on the setting of the DRC Alias bit in
 3060 **      Section 3.10.39, ¡§ATU Configuration Register - ATUCR¡¨ on page 252). When there is a
 3061 **      match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a
 3062 **      match and the data is not available, a Retry is signaled with no other action taken. When there
 3063 **      is not a match and when the ITQ has less than eight entries, capture the transaction
 3064 **      information, signal a Retry and initiate a delayed transaction. When there is not a match and
 3065 **      when the ITQ is full, then signal a Retry with no other action taken.
 3066 **      ¡X When an address parity error is detected, the address parity response defined in
 3067 **      Section 3.7 is used.
 3068 **      ¡E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from
 3069 **      the IRQ, it continues until one of the following is true:
 3070 **      ¡X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the
 3071 **      data is flushed.
 3072 **      ¡X An internal bus Target Abort was detected. In this case, the QWORD associated with the
 3073 **      Target Abort is never entered into the IRQ, and therefore is never returned.
 3074 **      ¡X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error.
 3075 **      ¡X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to
 3076 **      the initiator on the last data word available.
 3077 **      ¡E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
 3078 **      command are latched into the available ITQ and a Split Response Termination is signalled to
 3079 **      the initiator.
 3080 **      ¡E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
 3081 **      boundary, then the ATU waits until it receives the full byte count from the internal bus target
 3082 **      before returning read data by generating the split completion transaction on the PCI-X bus.
 3083 **      When the read requested crosses at least one 1024 byte boundary, then ATU completes the
 3084 **      transfer by returning data in 1024 byte aligned chunks.
 3085 **      ¡E When operating in the PCI-X mode, once a split completion transaction has started, it
 3086 **      continues until one of the following is true:
 3087 **      ¡X The requester (now the target) generates a Retry Termination, or a Disconnection at Next
 3088 **      ADB (when the requester is a bridge)
 3089 **      ¡X The byte count is satisfied.
 3090 **      ¡X An internal bus Target Abort was detected. The ATU generates a Split Completion
 3091 **      Message (message class=2h - completer error, and message index=81h - target abort) to
 3092 **      inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
 3093 **      Refer to Section 3.7.1.
 3094 **      ¡X An internal bus Master Abort was detected. The ATU generates a Split Completion
 3095 **      Message (message class=2h - completer error, and message index=80h - Master abort) to
 3096 **      inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
 3097 **      Refer to Section 3.7.1
 3098 **      ¡E When operating in the conventional PCI mode, when the master inserts wait states on the PCI
 3099 **      bus, the ATU PCI slave interface waits with no premature disconnects.
 3100 **      ¡E When a data parity error occurs signified by PERR# asserted from the initiator, no action is
 3101 **      taken by the target interface. Refer to Section 3.7.2.5.
 3102 **      ¡E When operating in the conventional PCI mode, when the read on the internal bus is
 3103 **      target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is
 3104 **      based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
 3105 **      target abort is used, when clear, a disconnect is used.
 3106 **      ¡E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
 3107 **      and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates
 3108 **      a Split Completion Message (message class=2h - completer error, and message index=81h -
 3109 **      internal bus target abort) to inform the requester about the abnormal condition. For the MU
 3110 **      queue ports, the ATU returns either a target abort or a single data phase disconnect depending
 3111 **      on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
 3112 **      transaction is flushed. Refer to Section 3.7.1.
 3113 **      ¡E When operating in the conventional PCI mode, when the transaction on the internal bus
 3114 **      resulted in a master abort, the ATU returns a target abort to inform the requester about the
 3115 **      abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1
 3116 **      ¡E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
 3117 **      master abort, the ATU generates a Split Completion Message (message class=2h - completer
 3118 **      error, and message index=80h - internal bus master abort) to inform the requester about the
 3119 **      abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1.
 3120 **      ¡E When operating in the PCI-X mode, when the Split Completion transaction completes with
 3121 **      either Master-Abort or Target-Abort, the requester is indicating a failure condition that
 3122 **      prevents it from accepting the completion it requested. In this case, since the Split Request
 3123 **      addresses a location that has no read side effects, the completer must discard the Split
 3124 **      Completion and take no further action.
 3125 **      The data flow for an inbound read transaction on the internal bus is summarized in the following
 3126 **      statements:
 3127 **      ¡E The ATU internal bus master interface requests the internal bus when a PCI address appears in
 3128 **              an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
 3129 **              ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU
 3130 **              always uses conventional PCI ordering rules.
 3131 **      ¡E Once the internal bus is granted, the internal bus master interface drives the translated address
 3132 **              onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated.
 3133 **              When a master abort occurs, the transaction is considered complete and a target abort is loaded
 3134 **              into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI
 3135 **              master has been delivered the target abort).
 3136 **      ¡E Once the translated address is on the bus and the transaction has been accepted, the internal
 3137 **              bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously
 3138 **              received by the IRQ until one of the following is true:
 3139 **      ¡X The full byte count requested by the ATU read request is received. The ATU internal bus
 3140 **          initiator interface performs a initiator completion in this case.
 3141 **      ¡X When operating in the conventional PCI mode, a Target Abort is received on the internal
 3142 **              bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
 3143 **              informed.
 3144 **      ¡X When operating in the PCI-X mode, a Target Abort is received on the internal bus from
 3145 **              the internal bus target. In this case, the transaction is aborted. The ATU generates a Split
 3146 **              Completion Message (message class=2h - completer error, and message index=81h -
 3147 **              target abort) on the PCI bus to inform the requester about the abnormal condition. The
 3148 **              ITQ for this transaction is flushed.
 3149 **      ¡X When operating in the conventional PCI mode, a single data phase disconnection is
 3150 **              received from the internal bus target. When the data has not been received up to the next
 3151 **              QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus.
 3152 **              When not, the bus returns to idle.
 3153 **      ¡X When operating in the PCI-X mode, a single data phase disconnection is received from
 3154 **              the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to
 3155 **              obtain remaining data.
 3156 **      ¡X When operating in the conventional PCI mode, a disconnection at Next ADB is received
 3157 **          from the internal bus target. The bus returns to idle.
 3158 **      ¡X When operating in the PCI-X mode, a disconnection at Next ADB is received from the
 3159 **              internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain
 3160 **              remaining data.
 3161 **              To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
 3162 **              ignore the memory read command (Memory Read, Memory Read Line, and Memory Read
 3163 **              Multiple) when trying to match the current inbound read transaction with data in a DRC queue
 3164 **              which was read previously (DRC on target bus). When the Read Command Alias Bit in the
 3165 **              ATUCR register is set, the ATU does not distinguish the read commands on transactions. For
 3166 **              example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read
 3167 **              on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address
 3168 **              as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return
 3169 **              the read data from the DRC queue and consider the Delayed Read transaction complete. When the
 3170 **              Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
 3171 **              commands did not match, only the address.
 3172 **************************************************************************
 3173 */
 3174 /*
 3175 **************************************************************************
 3176 **                    Inbound Write Transaction
 3177 **========================================================================
 3178 **        An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
 3179 **        memory or a 80331 memory-mapped register.
 3180 **      Data flow for an inbound write transaction on the PCI bus is summarized as:
 3181 **      ¡E The ATU claims the PCI write transaction when the PCI address is within the inbound
 3182 **        translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
 3183 **        Base Address Register during DACs) and Inbound Limit Register.
 3184 **      ¡E When the IWADQ has at least one address entry available and the IWQ has at least one buffer
 3185 **        available, the address is captured and the first data phase is accepted.
 3186 **      ¡E The PCI interface continues to accept write data until one of the following is true:
 3187 **        ¡X The initiator performs a disconnect.
 3188 **        ¡X The transaction crosses a buffer boundary.
 3189 **      ¡E When an address parity error is detected during the address phase of the transaction, the
 3190 **        address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address
 3191 **        parity error response.
 3192 **      ¡E When operating in the PCI-X mode when an attribute parity error is detected, the attribute
 3193 **        parity error mechanism described in Section 3.7.1 is used.
 3194 **      ¡E When a data parity error is detected while accepting data, the slave interface sets the
 3195 **        appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6
 3196 **        for details of the inbound write data parity error response.
 3197 **        Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient
 3198 **        to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus
 3199 **        interface becomes aware of the inbound write. When there are additional write transactions ahead
 3200 **        in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been
 3201 **        satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU
 3202 **        internal master interface. The ATU does not insert target wait states nor do data merging on the PCI
 3203 **        interface, when operating in the PCI mode.
 3204 **        In the PCI-X mode memory writes are always executed as immediate transactions, while
 3205 **        configuration write transactions are processed as split transactions. The ATU generates a Split
 3206 **        Completion Message, (with Message class=0h - Write Completion Class and Message index =
 3207 **        00h - Write Completion Message) once a configuration write is successfully executed.
 3208 **        Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions.
 3209 **        The ATU handles such transactions as independent transactions.
 3210 **        Data flow for the inbound write transaction on the internal bus is summarized as:
 3211 **      ¡E The ATU internal bus master requests the internal bus when IWADQ has at least one entry
 3212 **        with associated data in the IWQ.
 3213 **      ¡E When the internal bus is granted, the internal bus master interface initiates the write
 3214 **        transaction by driving the translated address onto the internal bus. For details on inbound
 3215 **        address translation.
 3216 **      ¡E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus.
 3217 **        The current transaction is flushed from the queue and SERR# may be asserted on the PCI
 3218 **        interface.
 3219 **      ¡E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
 3220 **        IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
 3221 **        IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
 3222 **        from the IWQ to the internal bus when data is available and the internal bus interface retains
 3223 **        internal bus ownership.
 3224 **      ¡E The internal bus interface stops transferring data from the current transaction to the internal
 3225 **        bus when one of the following conditions becomes true:
 3226 **      ¡X The internal bus initiator interface loses bus ownership. The ATU internal initiator
 3227 **        terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB
 3228 **        is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
 3229 **        complete the delivery of remaining data using the same sequence ID but with the
 3230 **        modified starting address and byte count.
 3231 **      ¡X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When
 3232 **        the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the
 3233 **        transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to
 3234 **        complete the delivery of remaining data using the same sequence ID but with the
 3235 **        modified starting address and byte count.
 3236 **      ¡X A Single Data Phase Disconnect is signaled on the internal bus from the internal target.
 3237 **        When the transaction in the IWQ needs only a single data phase, the master returns to idle.
 3238 **        When the transaction in the IWQ is not complete, the initiator attempts to reacquire the
 3239 **        bus to complete the delivery of remaining data using the same sequence ID but with the
 3240 **        modified starting address and byte count.
 3241 **      ¡X The data from the current transaction has completed (satisfaction of byte count). An
 3242 **        initiator termination is performed and the bus returns to idle.
 3243 **      ¡X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
 3244 **        Data is flushed from the IWQ.
 3245 *****************************************************************
 3246 */
 3247 
 3248 
 3249 
 3250 /*
 3251 **************************************************************************
 3252 **               Inbound Read Completions Data Parity Errors
 3253 **========================================================================
 3254 **      As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
 3255 **      When as the completer of a Split Read Request the ATU observes PERR# assertion during the split
 3256 **      completion transaction, the ATU attempts to complete the transaction normally and no further
 3257 **      action is taken.
 3258 **************************************************************************
 3259 */
 3260 
 3261 /*
 3262 **************************************************************************
 3263 **               Inbound Configuration Write Completion Message Data Parity Errors
 3264 **========================================================================
 3265 **  As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
 3266 **  When as the completer of a Configuration (Split) Write Request the ATU observes PERR#
 3267 **  assertion during the split completion transaction, the ATU attempts to complete the transaction
 3268 **  normally and no further action is taken.
 3269 **************************************************************************
 3270 */
 3271 
 3272 /*
 3273 **************************************************************************
 3274 **              Inbound Read Request Data Parity Errors
 3275 **===================== Immediate Data Transfer ==========================
 3276 **  As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes.
 3277 **  Inbound read data parity errors occur when read data delivered from the IRQ is detected as having
 3278 **  bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally
 3279 **  report the error to the system by asserting PERR#. As a target device in this scenario, no action is
 3280 **  required and no error bits are set.
 3281 **=====================Split Response Termination=========================
 3282 **  As a target, the ATU may encounter this error when operating in the PCI-X mode.
 3283 **  Inbound read data parity errors occur during the Split Response Termination. The initiator may
 3284 **  optionally report the error to the system by asserting PERR#. As a target device in this scenario, no
 3285 **  action is required and no error bits are set.
 3286 **************************************************************************
 3287 */
 3288 
 3289 /*
 3290 **************************************************************************
 3291 **              Inbound Write Request Data Parity Errors
 3292 **========================================================================
 3293 **      As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
 3294 **      Data parity errors occurring during write operations received by the ATU may assert PERR# on
 3295 **      the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write
 3296 **      transaction completes or a queue fill condition is reached. Specifically, the following actions with
 3297 **      the given constraints are taken by the ATU:
 3298 **      ¡E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
 3299 **      following the data phase in which the data parity error is detected on the bus. This is only
 3300 **      done when the Parity Error Response bit in the ATUCMD is set.
 3301 **      ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 3302 **      actions is taken:
 3303 **      ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 3304 **      Detected Parity Error bit in the ATUISR. When set, no action.
 3305 ***************************************************************************
 3306 */
 3307 
 3308 
 3309 /*
 3310 ***************************************************************************
 3311 **                 Inbound Configuration Write Request
 3312 **  =====================================================================
 3313 **  As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
 3314 **  ===============================================
 3315 **              Conventional PCI Mode
 3316 **  ===============================================
 3317 **  To allow for correct data parity calculations for delayed write transactions, the ATU delays the
 3318 **  assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a
 3319 **  delayed write transaction (inbound configuration write cycle) can occur in any of the following
 3320 **  parts of the transactions:
 3321 **  ¡E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
 3322 **  address/command and data for delayed delivery to the internal configuration register.
 3323 **  ¡E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
 3324 **  of the operation back to the original master.
 3325 **  The 80331 ATU PCI interface has the following responses to a delayed write parity error for
 3326 **  inbound transactions during Delayed Write Request cycles with the given constraints:
 3327 **  ¡E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
 3328 **  (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the
 3329 **  parity error. The delayed write cycle is not enqueued and forwarded to the internal bus.
 3330 **  When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
 3331 **  transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be
 3332 **  forwarded to the internal bus. PERR# is not asserted.
 3333 **  ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 3334 **  actions is taken:
 3335 **  ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 3336 **  Detected Parity Error bit in the ATUISR. When set, no action.
 3337 **  For the original write transaction to be completed, the initiator retries the transaction on the PCI
 3338 **  bus and the ATU returns the status from the internal bus, completing the transaction.
 3339 **  For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and
 3340 **  therefore does not agree with the status being returned from the internal bus (i.e. status being
 3341 **  returned is normal completion) the ATU performs the following actions with the given constraints:
 3342 **  ¡E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
 3343 **  (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in
 3344 **  the IDWQ remains since the data of retried command did not match the data within the queue.
 3345 **  ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 3346 **  actions is taken:
 3347 **  ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 3348 **  Detected Parity Error bit in the ATUISR. When set, no action.
 3349 **  =================================================== 
 3350 **                       PCI-X Mode
 3351 **  ===================================================
 3352 **  Data parity errors occurring during configuration write operations received by the ATU may cause
 3353 **  PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error
 3354 **  occurs, the ATU accepts the write data and complete with a Split Response Termination.
 3355 **  Specifically, the following actions with the given constraints are then taken by the ATU:
 3356 **  ¡E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks
 3357 **  cycles following the Split Response Termination in which the data parity error is detected on
 3358 **  the bus. When the ATU asserts PERR#, additional actions is taken:
 3359 **  ¡X A Split Write Data Parity Error message (with message class=2h - completer error and
 3360 **  message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
 3361 **  that addresses the requester of the configuration write.
 3362 **  ¡X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
 3363 **  clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no
 3364 **  action.
 3365 **  ¡X The Split Write Request is not enqueued and forwarded to the internal bus.
 3366 **  ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 3367 **  actions is taken:
 3368 **  ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 3369 **  Detected Parity Error bit in the ATUISR. When set, no action.
 3370 **
 3371 ***************************************************************************
 3372 */
 3373 
 3374 /*
 3375 ***************************************************************************
 3376 **                       Split Completion Messages
 3377 **  =======================================================================
 3378 **  As a target, the ATU may encounter this error when operating in the PCI-X mode.
 3379 **  Data parity errors occurring during Split Completion Messages claimed by the ATU may assert
 3380 **  PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
 3381 **  ATU accepts the data and complete normally. Specifically, the following actions with the given
 3382 **  constraints are taken by the ATU:
 3383 **  ¡E PERR# is asserted three clocks cycles following the data phase in which the data parity error
 3384 **  is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD
 3385 **  is set. When the ATU asserts PERR#, additional actions is taken:
 3386 **  ¡X The Master Parity Error bit in the ATUSR is set.
 3387 **  ¡X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
 3388 **  PCI Master Parity Error bit in the ATUISR. When set, no action.
 3389 **  ¡X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover
 3390 **  Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken.
 3391 **  When the ATU asserts SERR#, additional actions is taken:
 3392 **  Set the SERR# Asserted bit in the ATUSR.
 3393 **  When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
 3394 **  SERR# Asserted bit in the ATUISR. When set, no action.
 3395 **  When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
 3396 **  SERR# Detected bit in the ATUISR. When clear, no action.
 3397 **  ¡E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
 3398 **  the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set.
 3399 **  When the ATU sets this bit, additional actions is taken:
 3400 **  ¡X When the ATU Received Split Completion Error Message Interrupt Mask bit in the
 3401 **  ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR.
 3402 **  When set, no action.
 3403 **  ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
 3404 **  actions is taken:
 3405 **  ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 3406 **  Detected Parity Error bit in the ATUISR. When set, no action.
 3407 **  ¡E The transaction associated with the Split Completion Message is discarded.
 3408 **  ¡E When the discarded transaction was a read, a completion error message (with message
 3409 **  class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
 3410 **  the internal bus of the 80331.
 3411 *****************************************************************************
 3412 */
 3413 
 3414 
 3415 /*
 3416 ******************************************************************************************************
 3417 **                 Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
 3418 **  ==================================================================================================
 3419 **      The Messaging Unit (MU) transfers data between the PCI system and the 80331 
 3420 **  notifies the respective system when new data arrives.
 3421 **      The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation.
 3422 **      window defined by: 
 3423 **                    1.Inbound ATU Base Address Register 0 (IABAR0) 
 3424 **                    2.Inbound ATU Limit Register 0 (IALR0)
 3425 **      All of the Messaging Unit errors are reported in the same manner as ATU errors. 
 3426 **  Error conditions and status can be found in :
 3427 **                                               1.ATUSR 
 3428 **                                               2.ATUISR
 3429 **====================================================================================================
 3430 **     Mechanism        Quantity               Assert PCI Interrupt Signals      Generate I/O Processor Interrupt
 3431 **----------------------------------------------------------------------------------------------------
 3432 **  Message Registers      2 Inbound                   Optional                              Optional
 3433 **                         2 Outbound                
 3434 **----------------------------------------------------------------------------------------------------
 3435 **  Doorbell Registers     1 Inbound                   Optional                              Optional
 3436 **                         1 Outbound  
 3437 **----------------------------------------------------------------------------------------------------
 3438 **  Circular Queues        4 Circular Queues           Under certain conditions              Under certain conditions
 3439 **----------------------------------------------------------------------------------------------------
 3440 **  Index Registers     1004 32-bit Memory Locations   No                                    Optional
 3441 **====================================================================================================
 3442 **     PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
 3443 **====================================================================================================
 3444 **  0000H           Reserved
 3445 **  0004H           Reserved
 3446 **  0008H           Reserved
 3447 **  000CH           Reserved
 3448 **------------------------------------------------------------------------
 3449 **  0010H                       Inbound Message Register 0              ]
 3450 **  0014H                       Inbound Message Register 1              ]
 3451 **  0018H                       Outbound Message Register 0             ]
 3452 **  001CH                       Outbound Message Register 1             ]   4 Message Registers
 3453 **------------------------------------------------------------------------
 3454 **  0020H                       Inbound Doorbell Register               ]
 3455 **  0024H                       Inbound Interrupt Status Register       ]
 3456 **  0028H                       Inbound Interrupt Mask Register         ]
 3457 **  002CH                       Outbound Doorbell Register              ]
 3458 **  0030H                       Outbound Interrupt Status Register      ]
 3459 **  0034H                       Outbound Interrupt Mask Register        ]   2 Doorbell Registers and 4 Interrupt Registers
 3460 **------------------------------------------------------------------------
 3461 **  0038H                       Reserved
 3462 **  003CH                       Reserved
 3463 **------------------------------------------------------------------------
 3464 **  0040H                       Inbound Queue Port                      ]
 3465 **  0044H                       Outbound Queue Port                     ]   2 Queue Ports
 3466 **------------------------------------------------------------------------
 3467 **  0048H                       Reserved
 3468 **  004CH                       Reserved
 3469 **------------------------------------------------------------------------
 3470 **  0050H                                                   ]
 3471 **    :                                                     ]
 3472 **    :      Intel Xscale Microarchitecture Local Memory    ]
 3473 **    :                                                     ]
 3474 **  0FFCH                                                   ]   1004 Index Registers
 3475 *******************************************************************************
 3476 */
 3477 struct _MU
 3478 {
 3479         u_int32_t                                                               resrved0[4];                /*0000 000F*/
 3480         u_int32_t                                                               inbound_msgaddr0;               /*0010 0013*/
 3481         u_int32_t                                                               inbound_msgaddr1;               /*0014 0017*/
 3482         u_int32_t                                                               outbound_msgaddr0;              /*0018 001B*/
 3483         u_int32_t                                                               outbound_msgaddr1;              /*001C 001F*/
 3484         u_int32_t                                                               inbound_doorbell;               /*0020 0023*/
 3485         u_int32_t                                                               inbound_intstatus;              /*0024 0027*/
 3486         u_int32_t                                                               inbound_intmask;                /*0028 002B*/
 3487         u_int32_t                                                               outbound_doorbell;              /*002C 002F*/
 3488         u_int32_t                                                               outbound_intstatus;             /*0030 0033*/
 3489         u_int32_t                                                               outbound_intmask;               /*0034 0037*/
 3490         u_int32_t                                                               reserved1[2];               /*0038 003F*/
 3491         u_int32_t                                                               inbound_queueport;              /*0040 0043*/
 3492         u_int32_t                                                               outbound_queueport;             /*0044 0047*/
 3493         u_int32_t                                                               reserved2[2];               /*0048 004F*/
 3494         u_int32_t                               reserved3[492];             /*0050 07FF ......local_buffer 492*/
 3495         u_int32_t                               reserved4[128];             /*0800 09FF                    128*/
 3496         u_int32_t                               message_rwbuffer[256];      /*0a00 0DFF                    256*/
 3497         u_int32_t                               ioctl_wbuffer[32];          /*0E00 0E7F                     32*/
 3498     u_int32_t                               reserved5[32];              /*0E80 0EFF                     32*/
 3499         u_int32_t                               ioctl_rbuffer[32];          /*0F00 0F7F                     32*/
 3500         u_int32_t                               reserved6[32];              /*0F80 0FFF                     32*/
 3501 };
 3502 /*
 3503 *****************************************************************************
 3504 **                      Theory of MU Operation
 3505 *****************************************************************************
 3506 **--------------------
 3507 **   inbound_msgaddr0:
 3508 **   inbound_msgaddr1:
 3509 **  outbound_msgaddr0:
 3510 **  outbound_msgaddr1:
 3511 **  .  The MU has four independent messaging mechanisms.
 3512 **     There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 
 3513 **     Each holds a 32-bit value and generates an interrupt when written.
 3514 **--------------------
 3515 **   inbound_doorbell:
 3516 **  outbound_doorbell:
 3517 **  .  The two Doorbell Registers support software interrupts. 
 3518 **     When a bit is set in a Doorbell Register, an interrupt is generated.
 3519 **--------------------
 3520 **  inbound_queueport:
 3521 ** outbound_queueport:
 3522 **
 3523 **
 3524 **  .  The Circular Queues support a message passing scheme that uses 4 circular queues. 
 3525 **     The 4 circular queues are implemented in 80331 local memory. 
 3526 **     Two queues are used for inbound messages and two are used for outbound messages. 
 3527 **     Interrupts may be generated when the queue is written.
 3528 **--------------------
 3529 ** local_buffer 0x0050 ....0x0FFF
 3530 **  .  The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 
 3531 **     When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured.
 3532 **     Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 
 3533 **     Each interrupt generated by the Messaging Unit can be masked.
 3534 **--------------------
 3535 **  .  Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 
 3536 **     with the exception of Multi-DWORD reads to the index registers. 
 3537 **     In Conventional mode: the MU terminates   Multi-DWORD PCI transactions (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 
 3538 **     In PCI-X mode       : the MU terminates a Multi-DWORD PCI read transaction with a Split Response and the data is returned through split completion transaction(s).
 3539 **     however, when the burst request crosses into or through the range of  offsets 40h to 4Ch (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 
 3540 **         In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written.
 3541 **--------------------
 3542 **  .  All registers needed to configure and control the Messaging Unit are memory-mapped registers.
 3543 **     The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
 3544 **     This PCI address window is used for PCI transactions that access the 80331 local memory.
 3545 **     The  PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register.
 3546 **--------------------
 3547 **  .  From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
 3548 **     The Messaging Unit uses the PCI configuration registers of the ATU for control and status information.
 3549 **     The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register.
 3550 **     The Messaging Unit reports all PCI errors in the ATU Status Register.
 3551 **--------------------
 3552 **  .  Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 
 3553 **     The register interface, message registers, doorbell registers, and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 
 3554 **     Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 
 3555 **     The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H.
 3556 **************************************************************************
 3557 */
 3558 /*
 3559 **************************************************************************
 3560 **  Message Registers
 3561 **  ==============================
 3562 **  . Messages can be sent and received by the 80331 through the use of the Message Registers. 
 3563 **  . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor.
 3564 **  . Inbound messages are sent by the host processor and received by the 80331.
 3565 **    Outbound messages are sent by the 80331 and received by the host processor.
 3566 **  . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register.
 3567 **    Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.
 3568 **  
 3569 **  Inbound Messages:
 3570 **  -----------------
 3571 **  . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 
 3572 **  . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
 3573 **  . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 
 3574 **    The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 
 3575 **    This is a Read/Clear bit that is set by the MU hardware and cleared by software.
 3576 **    The interrupt is cleared when the Intel XScale core writes a value of 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
 3577 **  ------------------------------------------------------------------------
 3578 **  Inbound Message Register - IMRx
 3579 **
 3580 **  . There are two Inbound Message Registers: IMR0 and IMR1. 
 3581 **  . When the IMR register is written, an interrupt to the Intel XScale core may be generated.
 3582 **    The interrupt is recorded in the Inbound Interrupt Status Register and may be masked by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
 3583 **  -----------------------------------------------------------------
 3584 **  Bit       Default                       Description
 3585 **  31:00    0000 0000H                     Inbound Message - This is a 32-bit message written by an external PCI agent. 
 3586 **                                                            When written, an interrupt to the Intel XScale core may be generated.
 3587 **************************************************************************
 3588 */
 3589 #define     ARCMSR_MU_INBOUND_MESSAGE_REG0                        0x10    /*dword 0x13,0x12,0x11,0x10*/
 3590 #define     ARCMSR_MU_INBOUND_MESSAGE_REG1                        0x14    /*dword 0x17,0x16,0x15,0x14*/
 3591 /*
 3592 **************************************************************************
 3593 **  Outbound Message Register - OMRx
 3594 **  --------------------------------
 3595 **  There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is
 3596 **  written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
 3597 **  Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound
 3598 **  Interrupt Mask Register.
 3599 **  
 3600 **  Bit       Default                       Description
 3601 **  31:00    00000000H                      Outbound Message - This is 32-bit message written by the Intel  XScale  core. When written, an
 3602 **                                                             interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register.
 3603 **************************************************************************
 3604 */
 3605 #define     ARCMSR_MU_OUTBOUND_MESSAGE_REG0                       0x18    /*dword 0x1B,0x1A,0x19,0x18*/
 3606 #define     ARCMSR_MU_OUTBOUND_MESSAGE_REG1                       0x1C    /*dword 0x1F,0x1E,0x1D,0x1C*/
 3607 /*
 3608 **************************************************************************
 3609 **        Doorbell Registers
 3610 **  ==============================
 3611 **  There are two Doorbell Registers: 
 3612 **                                  Inbound Doorbell Register 
 3613 **                                  Outbound Doorbell Register
 3614 **  The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 
 3615 **  The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 
 3616 **  Both Doorbell Registers may generate interrupts whenever a bit in the register is set.
 3617 **  
 3618 **  Inbound Doorbells:
 3619 **  ------------------
 3620 **  . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale  core.
 3621 **    An interrupt is generated when any of the bits in the doorbell register is written to a value of 1.
 3622 **    Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 
 3623 **  . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 
 3624 **    The interrupt is recorded in the Inbound Interrupt Status Register.
 3625 **  . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register.
 3626 **    When the mask bit is set for a particular bit, no interrupt is generated for that bit.
 3627 **    The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt and not the values written to the Inbound Doorbell Register. 
 3628 **    One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
 3629 **  . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 
 3630 **    Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt.
 3631 **  ------------------------------------------------------------------------
 3632 **  Inbound Doorbell Register - IDR
 3633 **
 3634 **  . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 
 3635 **  . Bit 31 is reserved for generating an Error Doorbell interrupt. 
 3636 **    When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 
 3637 **    All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 
 3638 **    when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register.
 3639 **    The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale  core.
 3640 **  ------------------------------------------------------------------------
 3641 **  Bit       Default                       Description
 3642 **  31          0 2                         Error Interrupt - Generate an Error Interrupt to the Intel XScale core.
 3643 **  30:00    00000000H                      Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 
 3644 **                                                             When all bits are clear, do not generate a Normal Interrupt.
 3645 **************************************************************************
 3646 */
 3647 #define     ARCMSR_MU_INBOUND_DOORBELL_REG                        0x20    /*dword 0x23,0x22,0x21,0x20*/
 3648 /*
 3649 **************************************************************************
 3650 **  Inbound Interrupt Status Register - IISR
 3651 **
 3652 **  . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 
 3653 **    It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 
 3654 **    All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 
 3655 **    except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 
 3656 **    these two are routed to the Messaging Unit Error interrupt input. 
 3657 **    The generation of interrupts recorded in the Inbound Interrupt Status Register may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 
 3658 **    Some of the bits in this register are Read Only. 
 3659 **    For those bits, the interrupt must be cleared through another register.
 3660 **
 3661 **  Bit       Default                       Description
 3662 **  31:07    0000000H 0 2                   Reserved
 3663 **  06          0 2                         Index Register Interrupt - This bit is set by the MU hardware when an Index Register has been written after a PCI transaction.
 3664 **  05          0 2                         Outbound Free Queue Full Interrupt - This bit is set when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 
 3665 **                                                                               An Error interrupt is generated for this condition.
 3666 **  04          0 2                         Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 
 3667 **                                                                         Once cleared, an interrupt does NOT be generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
 3668 **                                                                         Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 
 3669 **                                                                         software must retain the information that the Inbound Post queue status is not empty.
 3670 **                                                                         NOTE: 
 3671 **                                                                         This interrupt is provided with dedicated support in the 80331 Interrupt Controller.
 3672 **  03          0 2                         Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set.
 3673 **                                                                     To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear.
 3674 **  02          0 2                         Inbound Doorbell Interrupt - This bit is set when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
 3675 **                                                                       To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear.
 3676 **  01          0 2                         Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written.
 3677 **  00          0 2                         Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written.
 3678 **************************************************************************
 3679 */
 3680 #define     ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG            0x24    /*dword 0x27,0x26,0x25,0x24*/
 3681 #define     ARCMSR_MU_INBOUND_INDEX_INT                      0x40
 3682 #define     ARCMSR_MU_INBOUND_QUEUEFULL_INT                  0x20
 3683 #define     ARCMSR_MU_INBOUND_POSTQUEUE_INT                  0x10         
 3684 #define     ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT             0x08
 3685 #define     ARCMSR_MU_INBOUND_DOORBELL_INT                   0x04
 3686 #define     ARCMSR_MU_INBOUND_MESSAGE1_INT                   0x02
 3687 #define     ARCMSR_MU_INBOUND_MESSAGE0_INT                   0x01
 3688 /*
 3689 **************************************************************************
 3690 **  Inbound Interrupt Mask Register - IIMR
 3691 **
 3692 **  . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 
 3693 **    Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register.
 3694 **    Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 
 3695 **    They only affect the generation of the Intel XScale core interrupt.
 3696 **  ------------------------------------------------------------------------
 3697 **  Bit       Default                       Description
 3698 **  31:07     000000H 0 2                   Reserved
 3699 **  06        0 2                           Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware when an Index Register has been written after a PCI transaction.
 3700 **  05        0 2                           Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
 3701 **  04        0 2                           Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware when the Inbound Post Queue has been written.
 3702 **  03        0 2                           Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt when the Error Interrupt bit of the Inbound Doorbell Register is set.
 3703 **  02        0 2                           Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
 3704 **  01        0 2                           Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 Interrupt generated by a write to the Inbound Message 1 Register.
 3705 **  00        0 2                           Inbound Message 0 Interrupt Mask - When set, this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register.
 3706 **************************************************************************
 3707 */
 3708 #define     ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG              0x28    /*dword 0x2B,0x2A,0x29,0x28*/
 3709 #define     ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE               0x40
 3710 #define     ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE           0x20
 3711 #define     ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE           0x10         
 3712 #define     ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE      0x08
 3713 #define     ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE            0x04
 3714 #define     ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE            0x02
 3715 #define     ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE            0x01
 3716 /*
 3717 **************************************************************************
 3718 **  Outbound Doorbell Register - ODR
 3719 **
 3720 **  The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 
 3721 **  XScale  core to generate PCI interrupts to the host processor by writing to this register. The
 3722 **  generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
 3723 **  Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
 3724 **  The Software Interrupt bits in this register can only be set by the Intel  XScale  core and can only
 3725 **  be cleared by an external PCI agent.
 3726 **  ----------------------------------------------------------------------
 3727 **  Bit       Default                       Description
 3728 **  31          0 2                          Reserved
 3729 **  30          0 2                          Reserved.
 3730 **  29          0 2                          Reserved
 3731 **  28       0000 0000H                      PCI Interrupt - When set, this bit causes the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
 3732 **                                                           signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 
 3733 **                                                           When this bit is cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 
 3734 **                                                           signal is deasserted.
 3735 **  27:00     000 0000H                      Software Interrupts - When any bit is set the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 
 3736 **                                                           signal is asserted or a Message-signaled Interrupt is generated (when enabled).
 3737 **                                                           When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
 3738 **                                                           signal is deasserted.
 3739 **************************************************************************
 3740 */
 3741 #define     ARCMSR_MU_OUTBOUND_DOORBELL_REG                       0x2C    /*dword 0x2F,0x2E,0x2D,0x2C*/
 3742 /*
 3743 **************************************************************************
 3744 **  Outbound Interrupt Status Register - OISR
 3745 **
 3746 **  The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the
 3747 **  status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular
 3748 **  Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
 3749 **  be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the
 3750 **  bits in this register are Read Only. For those bits, the interrupt must be cleared through another
 3751 **  register.
 3752 **  ----------------------------------------------------------------------
 3753 **  Bit       Default                       Description
 3754 **  31:05     000000H 000 2                 Reserved
 3755 **  04        0 2                           PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register.
 3756 **                                                          To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared.
 3757 **  03        0 2                           Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is
 3758 **                                                          cleared when any prefetch data has been read from the Outbound Queue Port.
 3759 **  02        0 2                           Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound
 3760 **                                                          Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
 3761 **                                                          Doorbell Register must all be clear.
 3762 **  01        0 2                           Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is
 3763 **                                                          written. Clearing this bit clears the interrupt.
 3764 **  00        0 2                           Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is
 3765 **                                                          written. Clearing this bit clears the interrupt.
 3766 **************************************************************************
 3767 */
 3768 #define     ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG           0x30    /*dword 0x33,0x32,0x31,0x30*/
 3769 #define     ARCMSR_MU_OUTBOUND_PCI_INT                        0x10
 3770 #define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INT                      0x08 
 3771 #define     ARCMSR_MU_OUTBOUND_DOORBELL_INT                       0x04 
 3772 #define     ARCMSR_MU_OUTBOUND_MESSAGE1_INT                       0x02 
 3773 #define     ARCMSR_MU_OUTBOUND_MESSAGE0_INT                       0x01 
 3774 /*
 3775 **************************************************************************
 3776 **  Outbound Interrupt Mask Register - OIMR
 3777 **  The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
 3778 **  interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a
 3779 **  hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
 3780 **  interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated.
 3781 **  Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They
 3782 **  only affect the generation of the PCI interrupt.
 3783 **  ----------------------------------------------------------------------
 3784 **  Bit       Default                       Description
 3785 **  31:05     000000H                       Reserved
 3786 **  04          0 2                         PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28)
 3787 **                                                               in the Outbound Doorbell Register is set.
 3788 **  03          0 2                         Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in
 3789 **                                                               the prefetch buffer is valid.
 3790 **  02          0 2                         Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound
 3791 **                                                               Doorbell Register.
 3792 **  01          0 2                         Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt
 3793 **                                                               generated by a write to the Outbound Message 1 Register.
 3794 **  00          0 2                         Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt
 3795 **                                                               generated by a write to the Outbound Message 0 Register.
 3796 **************************************************************************
 3797 */
 3798 #define     ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG                 0x34    /*dword 0x37,0x36,0x35,0x34*/
 3799 #define     ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE                  0x10
 3800 #define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE        0x08 
 3801 #define     ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE             0x04 
 3802 #define     ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE             0x02 
 3803 #define     ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE             0x01 
 3804 #define     ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE                      0x1F 
 3805 /*
 3806 **************************************************************************
 3807 **
 3808 **************************************************************************
 3809 */
 3810 #define     ARCMSR_MU_INBOUND_QUEUE_PORT_REG              0x40    /*dword 0x43,0x42,0x41,0x40*/
 3811 #define     ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG             0x44    /*dword 0x47,0x46,0x45,0x44*/
 3812 /*
 3813 **************************************************************************
 3814 **                          Circular Queues
 3815 **  ======================================================================
 3816 **  The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
 3817 **  this case, inbound and outbound refer to the direction of the flow of posted messages.
 3818 **  Inbound messages are either:
 3819 **                                              ¡E posted messages by other processors for the Intel XScale core to process or
 3820 **                                              ¡E free (or empty) messages that can be reused by other processors.
 3821 **  Outbound messages are either:
 3822 **                                                      ¡E posted messages by the Intel XScale core for other processors to process or
 3823 **                                                      ¡E free (or empty) messages that can be reused by the Intel XScale core.
 3824 **  Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331.
 3825 **  The four Circular Queues are used to pass messages in the following manner. 
 3826 **      . The two inbound queues are used to handle inbound messages 
 3827 **        and the two outbound queues are used to handle  outbound messages. 
 3828 **      . One of the inbound queues is designated the Free queue and it contains inbound free messages. 
 3829 **        The other inbound queue is designated the Post queue and it contains inbound posted messages.
 3830 **        Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 
 3831 **  
 3832 **  =============================================================================================================
 3833 **  Circular Queue Summary
 3834 **   _____________________________________________________________________________________________________________
 3835 **  |    Queue Name        |                     Purpose                                |  Action on PCI Interface|
 3836 **  |______________________|____________________________________________________________|_________________________|
 3837 **  |Inbound Post  Queue   |    Queue for inbound messages from other processors        |          Written        |
 3838 **  |                      |     waiting to be processed by the 80331                   |                         |
 3839 **  |Inbound Free  Queue   |    Queue for empty inbound messages from the 80331         |          Read           |
 3840 **  |                      |    available for use by other processors                   |                         |
 3841 **  |Outbound Post Queue   |    Queue for outbound messages from the 80331              |          Read           |
 3842 **  |                      |    that are being posted to the other processors           |                         |
 3843 **  |Outbound Free Queue   |    Queue for empty outbound messages from other processors |          Written        |
 3844 **  |                      |    available for use by the 80331                          |                         |
 3845 **  |______________________|____________________________________________________________|_________________________|
 3846 **
 3847 **  . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
 3848 **    queue and to receive free messages returning from the 80331. 
 3849 **    The host processor posts inbound messages, 
 3850 **    the Intel XScale core receives the posted message and when it is finished with the message,
 3851 **    places it back on the inbound free queue for reuse by the host processor.
 3852 **  
 3853 **  The circular queues are accessed by external PCI agents through two port locations in the PCI
 3854 **  address space: 
 3855 **              Inbound Queue Port 
 3856 **          and Outbound Queue Port. 
 3857 **  The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 
 3858 **  The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue.
 3859 **  Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 
 3860 **  does not cause the MU hardware to increment the queue pointers. 
 3861 **  This is treated as when the PCI transaction did not occur. 
 3862 **  The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
 3863 **  ======================================================================================
 3864 **  Overview of Circular Queue Operation
 3865 **  ======================================================================================
 3866 **  . The data storage for the circular queues must be provided by the 80331 local memory.
 3867 **  . The base address of the circular queues is contained in the Queue Base Address Register.
 3868 **    Each entry in the queue is a 32-bit data value. 
 3869 **  . Each read from or write to the queue may access only one queue entry. 
 3870 **  . Multi-DWORD accesses to the circular queues are not allowed. 
 3871 **    Sub-DWORD accesses are promoted to DWORD accesses.
 3872 **  . Each circular queue has a head pointer and a tail pointer. 
 3873 **    The pointers are offsets from the Queue Base Address.
 3874 **  . Writes to a queue occur at the head of the queue and reads occur from the tail. 
 3875 **    The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware.
 3876 **    Which unit maintains the pointer is determined by the writer of the queue. 
 3877 **    More details about the pointers are given in the queue descriptions below. 
 3878 **    The pointers are incremented after the queue access.
 3879 **    Both pointers wrap around to the first address of the circular queue when they reach the circular queue size.
 3880 **  
 3881 **  Messaging Unit...
 3882 **
 3883 **  The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions.
 3884 **  . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted.
 3885 **    The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).
 3886 **  . All four queues must be the same size and may be contiguous. 
 3887 **    Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 
 3888 **    The Queue size is determined by the Queue Size field in the MU Configuration Register.
 3889 **  . There is one base address for all four queues. 
 3890 **    It is stored in the Queue Base Address Register (QBAR).
 3891 **    The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 
 3892 **    here shows an example of how the circular queues should be set up based on the
 3893 **    Intelligent I/O (I 2 O) Architecture Specification. 
 3894 **    Other ordering of the circular queues is possible.
 3895 **  
 3896 **                              Queue                           Starting Address
 3897 **                              Inbound Free Queue              QBAR
 3898 **                              Inbound Post Queue              QBAR + Queue Size
 3899 **                              Outbound Post Queue             QBAR + 2 * Queue Size
 3900 **                              Outbound Free Queue             QBAR + 3 * Queue Size
 3901 **  ===================================================================================
 3902 **  Inbound Post Queue
 3903 **  ------------------
 3904 **  The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process.
 3905 **  This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 
 3906 **  The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
 3907 **  For a PCI write transaction that accesses the Inbound Queue Port, the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register.
 3908 **  When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register.
 3909 **  An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 
 3910 **  The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status.
 3911 **  The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 
 3912 **  The interrupt can be masked by the Inbound Interrupt Mask Register. 
 3913 **  Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee that the full condition is recognized by the core processor.
 3914 **  In addition, to guarantee that the queue does not get overwritten, software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt.
 3915 **  Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 
 3916 **  Only a new message posting the in the inbound queue generates a new interrupt. 
 3917 **  Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, software must retain the information that the Inbound Post queue status.
 3918 **  From the time that the PCI write transaction is received until the data is written in local memory and the Inbound Post Head Pointer Register is incremented, any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
 3919 **  The Intel XScale core may read messages from the Inbound Post Queue by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 
 3920 **  The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 
 3921 **  When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), the hardware retries any PCI writes until a slot in the queue becomes available. 
 3922 **  A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer.
 3923 **  ===================================================================================
 3924 **  Inbound Free Queue
 3925 **  ------------------
 3926 **  The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use.
 3927 **  This queue is read from the queue tail by external PCI agents. 
 3928 **  It is written to the queue head by the Intel XScale core. 
 3929 **  The tail pointer is maintained by the MU hardware.
 3930 **  The head pointer is maintained by the Intel XScale core.
 3931 **  For a PCI read transaction that accesses the Inbound Queue Port,
 3932 **  the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 
 3933 **  When the queue is not empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned.
 3934 **  When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), the value of -1 (FFFF.FFFFH) is  returned.
 3935 **  When the queue was not empty and the MU succeeded in returning the data at the tail, 
 3936 **  the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
 3937 **  To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 
 3938 **  The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 
 3939 **  When the PCI read access occurs, the data is read directly from the prefetch register.
 3940 **  The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 
 3941 **  when the head and tail pointers are equal and the queue is empty. 
 3942 **  In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 
 3943 **  the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH and the Inbound Free Head Pointer Register is written.
 3944 **  The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue.
 3945 **  A prefetch must appear atomic from the perspective of the external PCI agent.
 3946 **  When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed.
 3947 **  The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
 3948 **  local memory location pointed to by the Inbound Free Head Pointer Register. 
 3949 **  The processor must then increment the Inbound Free Head Pointer Register.
 3950 **  ==================================================================================
 3951 **  Outbound Post Queue
 3952 **  -------------------
 3953 **  The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 
 3954 **  core for other processors to process. This queue is read from the queue tail by external PCI agents.
 3955 **  It is written to the queue head by the Intel XScale  core. The tail pointer is maintained by the
 3956 **  MU hardware. The head pointer is maintained by the Intel XScale  core.
 3957 **  For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
 3958 **  data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not
 3959 **  empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head
 3960 **  pointer was last written by software), the data is returned. When the queue is empty (head and tail
 3961 **  pointers are equal and the head pointer was last updated by hardware), the value of -1
 3962 **  (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the
 3963 **  data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
 3964 **  Register.
 3965 **  To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
 3966 **  accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
 3967 **  Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
 3968 **  occurs, the data is read directly from the prefetch register.
 3969 **  The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
 3970 **  and tail pointers are equal and the queue is empty. In order to update the prefetch register when
 3971 **  messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
 3972 **  starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head
 3973 **  Pointer Register is written. The Intel XScale  core needs to update the Outbound Post Head
 3974 **  Pointer Register when it adds messages to the queue.
 3975 **  A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is
 3976 **  started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry
 3977 **  until the prefetch is completed.
 3978 **  A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch
 3979 **  queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound
 3980 **  Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the
 3981 **  interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound
 3982 **  Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register.
 3983 **  The Intel XScale  core may place messages in the Outbound Post Queue by writing the data to
 3984 **  the local memory address in the Outbound Post Head Pointer Register. The processor must then
 3985 **  increment the Outbound Post Head Pointer Register.
 3986 **  ==================================================
 3987 **  Outbound Free Queue
 3988 **  -----------------------
 3989 **  The Outbound Free Queue holds free messages placed there by other processors for the Intel
 3990 **  XScale  core to use. This queue is read from the queue tail by the Intel XScale  core. It is
 3991 **  written to the queue head by external PCI agents. The tail pointer is maintained by the Intel
 3992 **  XScale  core. The head pointer is maintained by the MU hardware.
 3993 **  For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
 3994 **  local memory address in the Outbound Free Head Pointer Register. When the data written to the
 3995 **  Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
 3996 **  Head Pointer Register.
 3997 **  When the head pointer and the tail pointer become equal and the queue is full, the MU may signal
 3998 **  an interrupt to the Intel XScale  core to register the queue full condition. This interrupt is
 3999 **  recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free
 4000 **  Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can
 4001 **  be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the
 4002 **  Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the
 4003 **  core processor.
 4004 **  From the time that a PCI write transaction is received until the data is written in local memory and
 4005 **  the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
 4006 **  access the Outbound Free Queue Port is signalled a retry.
 4007 **  The Intel XScale  core may read messages from the Outbound Free Queue by reading the data
 4008 **  from the local memory address in the Outbound Free Tail Pointer Register. The processor must
 4009 **  then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full,
 4010 **  the hardware must retry any PCI writes until a slot in the queue becomes available.
 4011 **  
 4012 **  ==================================================================================
 4013 **  Circular Queue Summary
 4014 **  ----------------------
 4015 **  ________________________________________________________________________________________________________________________________________________
 4016 ** | Queue Name  |  PCI Port     |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by|
 4017 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
 4018 ** |Inbound Post | Inbound Queue |                       |                                    |                          |                          |
 4019 ** |    Queue    |     Port      |          NO           |      Yes, when queue is written    |         MU hardware      |     Intel XScale         |
 4020 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
 4021 ** |Inbound Free | Inbound Queue |                       |                                    |                          |                          |
 4022 ** |    Queue    |     Port      |          NO           |      NO                            |        Intel XScale      |      MU hardware         |
 4023 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
 4024 ** ==================================================================================
 4025 **  Circular Queue Status Summary
 4026 **  ----------------------
 4027 **  ____________________________________________________________________________________________________
 4028 ** |     Queue Name      |  Queue Status  | Head & Tail Pointer |         Last Pointer Update           |
 4029 ** |_____________________|________________|_____________________|_______________________________________|
 4030 ** | Inbound Post Queue  |      Empty     |       Equal         | Tail pointer last updated by software |
 4031 ** |_____________________|________________|_____________________|_______________________________________|
 4032 ** | Inbound Free Queue  |      Empty     |       Equal         | Head pointer last updated by hardware |
 4033 ** |_____________________|________________|_____________________|_______________________________________|
 4034 **************************************************************************
 4035 */
 4036 
 4037 /*
 4038 **************************************************************************
 4039 **       Index Registers
 4040 **  ========================
 4041 **  . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 
 4042 **    These registers are for inbound messages only.
 4043 **    The interrupt is recorded in the Inbound Interrupt Status Register.
 4044 **    The storage for the Index Registers is allocated from the 80331 local memory. 
 4045 **    PCI write accesses to the Index Registers write the data to local memory. 
 4046 **    PCI read accesses to the Index Registers read the data from local memory. 
 4047 **  . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 
 4048 **                                                           to Inbound ATU Translate Value Register + FFFH.
 4049 **  . The address of the first write access is stored in the Index Address Register. 
 4050 **    This register is written during the earliest write access and provides a means to determine which Index Register was written. 
 4051 **    Once updated by the MU, the Index Address Register is not updated until the Index Register Interrupt bit in the Inbound Interrupt Status Register is cleared. 
 4052 **  . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access.
 4053 **    Writes by the Intel XScale core to the local memory used by the Index Registers does not cause an interrupt and does not update the Index Address Register.
 4054 **  . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
 4055 **************************************************************************
 4056 */
 4057 /*
 4058 **************************************************************************
 4059 **    Messaging Unit Internal Bus Memory Map
 4060 **  =======================================
 4061 **  Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_
 4062 **  FFFF E300H             reserved                                       |
 4063 **    ..                     ..                                           |
 4064 **  FFFF E30CH             reserved                                       | 
 4065 **  FFFF E310H             Inbound Message Register 0                     | Available through
 4066 **  FFFF E314H             Inbound Message Register 1                     | ATU Inbound Translation Window
 4067 **  FFFF E318H             Outbound Message Register 0                    | 
 4068 **  FFFF E31CH             Outbound Message Register 1                    | or  
 4069 **  FFFF E320H             Inbound Doorbell Register                      |  
 4070 **  FFFF E324H             Inbound Interrupt Status Register              | must translate PCI address to 
 4071 **  FFFF E328H             Inbound Interrupt Mask Register                | the Intel Xscale Core
 4072 **  FFFF E32CH             Outbound Doorbell Register                     | Memory-Mapped Address
 4073 **  FFFF E330H             Outbound Interrupt Status Register             |
 4074 **  FFFF E334H             Outbound Interrupt Mask Register               |
 4075 **  ______________________________________________________________________|________________________________________
 4076 **  FFFF E338H             reserved                                       |
 4077 **  FFFF E33CH             reserved                                       |
 4078 **  FFFF E340H             reserved                                       |
 4079 **  FFFF E344H             reserved                                       |
 4080 **  FFFF E348H             reserved                                       |
 4081 **  FFFF E34CH             reserved                                       |
 4082 **  FFFF E350H             MU Configuration Register                      |
 4083 **  FFFF E354H             Queue Base Address Register                    |
 4084 **  FFFF E358H             reserved                                       |
 4085 **  FFFF E35CH             reserved                                       | must translate PCI address to 
 4086 **  FFFF E360H             Inbound Free Head Pointer Register             | the Intel Xscale Core 
 4087 **  FFFF E364H             Inbound Free Tail Pointer Register             | Memory-Mapped Address
 4088 **  FFFF E368H             Inbound Post Head pointer Register             |
 4089 **  FFFF E36CH             Inbound Post Tail Pointer Register             |
 4090 **  FFFF E370H             Outbound Free Head Pointer Register            | 
 4091 **  FFFF E374H             Outbound Free Tail Pointer Register            |
 4092 **  FFFF E378H             Outbound Post Head pointer Register            |
 4093 **  FFFF E37CH             Outbound Post Tail Pointer Register            |
 4094 **  FFFF E380H             Index Address Register                         |
 4095 **  FFFF E384H             reserved                                       |
 4096 **   ..                       ..                                          |
 4097 **  FFFF E3FCH             reserved                                       |
 4098 **  ______________________________________________________________________|_______________________________________
 4099 **************************************************************************
 4100 */
 4101 /*
 4102 **************************************************************************
 4103 **  MU Configuration Register - MUCR  FFFF.E350H
 4104 **
 4105 **  . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue.
 4106 **  . The Circular Queue Enable bit enables or disables the Circular Queues. 
 4107 **    The Circular Queues are disabled at reset to allow the software to initialize the head and tail pointer registers before any PCI accesses to the Queue Ports. 
 4108 **  . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues.
 4109 **  ------------------------------------------------------------------------
 4110 **  Bit       Default                       Description
 4111 **  31:06     000000H 00 2                  Reserved
 4112 **  05:01     00001 2                       Circular Queue Size - This field determines the size of each Circular Queue. 
 4113 **                                                                All four queues are the same size.
 4114 **                                                                                                                              ¡E 00001 2 - 4K Entries (16 Kbytes)
 4115 **                                                                                                                              ¡E 00010 2 - 8K Entries (32 Kbytes)
 4116 **                                                                                                                              ¡E 00100 2 - 16K Entries (64 Kbytes)
 4117 **                                                                                                                              ¡E 01000 2 - 32K Entries (128 Kbytes)
 4118 **                                                                                                                              ¡E 10000 2 - 64K Entries (256 Kbytes)
 4119 **  00        0 2                           Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular
 4120 **                                                                                                                              Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores
 4121 **                                                                                                                              the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when
 4122 **                                                                                                                              disabled. When set, the Circular Queues are fully enabled.
 4123 **************************************************************************
 4124 */
 4125 #define     ARCMSR_MU_CONFIGURATION_REG                   0xFFFFE350        
 4126 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K              0x0020    
 4127 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K              0x0010
 4128 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K              0x0008   
 4129 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K               0x0004   
 4130 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K               0x0002    
 4131 #define     ARCMSR_MU_CIRCULAR_QUEUE_ENABLE               0x0001        /*0:disable 1:enable*/
 4132 /*
 4133 **************************************************************************
 4134 **  Queue Base Address Register - QBAR
 4135 **
 4136 **  . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues.
 4137 **    The base address is required to be located on a 1 Mbyte address boundary.
 4138 **  . All Circular Queue head and tail pointers are based on the QBAR. 
 4139 **    When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 
 4140 **    Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register.
 4141 **  Warning: 
 4142 **         The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 
 4143 **  ------------------------------------------------------------------------
 4144 **  Bit       Default                       Description
 4145 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 4146 **  19:00     00000H                        Reserved
 4147 **************************************************************************
 4148 */
 4149 #define     ARCMSR_MU_QUEUE_BASE_ADDRESS_REG          0xFFFFE354   
 4150 /*
 4151 **************************************************************************
 4152 **  Inbound Free Head Pointer Register - IFHPR
 4153 **
 4154 **  . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from the Queue Base Address of the head pointer for the Inbound Free Queue. 
 4155 **    The Head Pointer must be aligned on a DWORD address boundary.
 4156 **    When read, the Queue Base Address is provided in the upper 12 bits of the register. 
 4157 **    Writes to the upper 12 bits of the register are ignored. 
 4158 **    This register is maintained by software.
 4159 **  ------------------------------------------------------------------------
 4160 **  Bit       Default                       Description
 4161 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 4162 **  19:02     0000H 00 2                    Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue.
 4163 **  01:00     00 2                          Reserved
 4164 **************************************************************************
 4165 */
 4166 #define     ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG       0xFFFFE360   
 4167 /*
 4168 **************************************************************************
 4169 **  Inbound Free Tail Pointer Register - IFTPR
 4170 **
 4171 **  . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue
 4172 **    Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a
 4173 **    DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
 4174 **    of the register. Writes to the upper 12 bits of the register are ignored.
 4175 **  ------------------------------------------------------------------------
 4176 **  Bit       Default                       Description
 4177 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 4178 **  19:02     0000H 00 2                    Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue.
 4179 **  01:00     00 2                          Reserved
 4180 **************************************************************************
 4181 */
 4182 #define     ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG       0xFFFFE364  
 4183 /*
 4184 **************************************************************************
 4185 **  Inbound Post Head Pointer Register - IPHPR
 4186 **
 4187 **  . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue
 4188 **    Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on
 4189 **    a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
 4190 **    of the register. Writes to the upper 12 bits of the register are ignored.
 4191 **  ------------------------------------------------------------------------
 4192 **  Bit       Default                       Description
 4193 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 4194 **  19:02     0000H 00 2                    Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue.
 4195 **  01:00     00 2                          Reserved
 4196 **************************************************************************
 4197 */
 4198 #define     ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG       0xFFFFE368
 4199 /*
 4200 **************************************************************************
 4201 **  Inbound Post Tail Pointer Register - IPTPR
 4202 **
 4203 **  . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue
 4204 **    Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a
 4205 **    DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
 4206 **    of the register. Writes to the upper 12 bits of the register are ignored.
 4207 **  ------------------------------------------------------------------------
 4208 **  Bit       Default                       Description
 4209 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 4210 **  19:02     0000H 00 2                    Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue.
 4211 **  01:00     00 2                          Reserved
 4212 **************************************************************************
 4213 */
 4214 #define     ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG       0xFFFFE36C
 4215 /*
 4216 **************************************************************************
 4217 **  Index Address Register - IAR
 4218 **
 4219 **  . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register.
 4220 **    It is written by the MU when the Index Registers are written by a PCI agent.
 4221 **    The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared.
 4222 **  . The local memory address of the Index Register least recently accessed is computed by adding the Index Address Register to the Inbound ATU Translate Value Register.
 4223 **  ------------------------------------------------------------------------
 4224 **  Bit       Default                       Description
 4225 **  31:12     000000H                       Reserved
 4226 **  11:02     00H 00 2                      Index Address - is the local memory offset of the Index Register written (050H to FFCH)
 4227 **  01:00     00 2                          Reserved
 4228 **************************************************************************
 4229 */
 4230 #define     ARCMSR_MU_LOCAL_MEMORY_INDEX_REG          0xFFFFE380    /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/
 4231 /*
 4232 **********************************************************************************************************
 4233 **                                RS-232 Interface for Areca Raid Controller
 4234 **                    The low level command interface is exclusive with VT100 terminal
 4235 **  --------------------------------------------------------------------
 4236 **    1. Sequence of command execution
 4237 **  --------------------------------------------------------------------
 4238 **      (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
 4239 **      (B) Command block : variable length of data including length, command code, data and checksum byte
 4240 **      (C) Return data : variable length of data
 4241 **  --------------------------------------------------------------------  
 4242 **    2. Command block
 4243 **  --------------------------------------------------------------------
 4244 **      (A) 1st byte : command block length (low byte)
 4245 **      (B) 2nd byte : command block length (high byte)
 4246 **                note ..command block length shouldn't > 2040 bytes, length excludes these two bytes
 4247 **      (C) 3rd byte : command code
 4248 **      (D) 4th and following bytes : variable length data bytes depends on command code
 4249 **      (E) last byte : checksum byte (sum of 1st byte until last data byte)
 4250 **  --------------------------------------------------------------------  
 4251 **    3. Command code and associated data
 4252 **  --------------------------------------------------------------------
 4253 **      The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, no password checking is needed and should be implemented in separate well controlled utility and not for end user access.
 4254 **      Command code 0x20--0x?? always check the password, password must be entered to enable these command.
 4255 **      enum
 4256 **      {
 4257 **              GUI_SET_SERIAL=0x10,
 4258 **              GUI_SET_VENDOR,
 4259 **              GUI_SET_MODEL,
 4260 **              GUI_IDENTIFY,
 4261 **              GUI_CHECK_PASSWORD,
 4262 **              GUI_LOGOUT,
 4263 **              GUI_HTTP,
 4264 **              GUI_SET_ETHERNET_ADDR,
 4265 **              GUI_SET_LOGO,
 4266 **              GUI_POLL_EVENT,
 4267 **              GUI_GET_EVENT,
 4268 **              GUI_GET_HW_MONITOR,
 4269 **    
 4270 **              //    GUI_QUICK_CREATE=0x20, (function removed)
 4271 **              GUI_GET_INFO_R=0x20,
 4272 **              GUI_GET_INFO_V,
 4273 **              GUI_GET_INFO_P,
 4274 **              GUI_GET_INFO_S,
 4275 **              GUI_CLEAR_EVENT,
 4276 **    
 4277 **              GUI_MUTE_BEEPER=0x30,
 4278 **              GUI_BEEPER_SETTING,
 4279 **              GUI_SET_PASSWORD,
 4280 **              GUI_HOST_INTERFACE_MODE,
 4281 **              GUI_REBUILD_PRIORITY,
 4282 **              GUI_MAX_ATA_MODE,
 4283 **              GUI_RESET_CONTROLLER,
 4284 **              GUI_COM_PORT_SETTING,
 4285 **              GUI_NO_OPERATION,
 4286 **              GUI_DHCP_IP,
 4287 **    
 4288 **              GUI_CREATE_PASS_THROUGH=0x40,
 4289 **              GUI_MODIFY_PASS_THROUGH,
 4290 **              GUI_DELETE_PASS_THROUGH,
 4291 **              GUI_IDENTIFY_DEVICE,
 4292 **    
 4293 **              GUI_CREATE_RAIDSET=0x50,
 4294 **              GUI_DELETE_RAIDSET,
 4295 **              GUI_EXPAND_RAIDSET,
 4296 **              GUI_ACTIVATE_RAIDSET,
 4297 **              GUI_CREATE_HOT_SPARE,
 4298 **              GUI_DELETE_HOT_SPARE,
 4299 **    
 4300 **              GUI_CREATE_VOLUME=0x60,
 4301 **              GUI_MODIFY_VOLUME,
 4302 **              GUI_DELETE_VOLUME,
 4303 **              GUI_START_CHECK_VOLUME,
 4304 **              GUI_STOP_CHECK_VOLUME
 4305 **      };
 4306 **    
 4307 **    Command description :
 4308 **    
 4309 **      GUI_SET_SERIAL : Set the controller serial#
 4310 **              byte 0,1        : length
 4311 **              byte 2          : command code 0x10
 4312 **              byte 3          : password length (should be 0x0f)
 4313 **              byte 4-0x13     : should be "ArEcATecHnoLogY"
 4314 **              byte 0x14--0x23 : Serial number string (must be 16 bytes)
 4315 **      GUI_SET_VENDOR : Set vendor string for the controller
 4316 **              byte 0,1        : length
 4317 **              byte 2          : command code 0x11
 4318 **              byte 3          : password length (should be 0x08)
 4319 **              byte 4-0x13     : should be "ArEcAvAr"
 4320 **              byte 0x14--0x3B : vendor string (must be 40 bytes)
 4321 **      GUI_SET_MODEL : Set the model name of the controller
 4322 **              byte 0,1        : length
 4323 **              byte 2          : command code 0x12
 4324 **              byte 3          : password length (should be 0x08)
 4325 **              byte 4-0x13     : should be "ArEcAvAr"
 4326 **              byte 0x14--0x1B : model string (must be 8 bytes)
 4327 **      GUI_IDENTIFY : Identify device
 4328 **              byte 0,1        : length
 4329 **              byte 2          : command code 0x13
 4330 **                                return "Areca RAID Subsystem "
 4331 **      GUI_CHECK_PASSWORD : Verify password
 4332 **              byte 0,1        : length
 4333 **              byte 2          : command code 0x14
 4334 **              byte 3          : password length
 4335 **              byte 4-0x??     : user password to be checked
 4336 **      GUI_LOGOUT : Logout GUI (force password checking on next command)
 4337 **              byte 0,1        : length
 4338 **              byte 2          : command code 0x15
 4339 **      GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16)
 4340 **
 4341 **      GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address
 4342 **              byte 0,1        : length
 4343 **              byte 2          : command code 0x17
 4344 **              byte 3          : password length (should be 0x08)
 4345 **              byte 4-0x13     : should be "ArEcAvAr"
 4346 **              byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
 4347 **      GUI_SET_LOGO : Set logo in HTTP
 4348 **              byte 0,1        : length
 4349 **              byte 2          : command code 0x18
 4350 **              byte 3          : Page# (0/1/2/3) (0xff --> clear OEM logo)
 4351 **              byte 4/5/6/7    : 0x55/0xaa/0xa5/0x5a
 4352 **              byte 8          : TITLE.JPG data (each page must be 2000 bytes)
 4353 **                                note .... page0 1st 2 byte must be actual length of the JPG file
 4354 **      GUI_POLL_EVENT : Poll If Event Log Changed
 4355 **              byte 0,1        : length
 4356 **              byte 2          : command code 0x19
 4357 **      GUI_GET_EVENT : Read Event
 4358 **              byte 0,1        : length
 4359 **              byte 2          : command code 0x1a
 4360 **              byte 3          : Event Page (0:1st page/1/2/3:last page)
 4361 **      GUI_GET_HW_MONITOR : Get HW monitor data
 4362 **              byte 0,1        : length
 4363 **              byte 2                  : command code 0x1b
 4364 **              byte 3                  : # of FANs(example 2)
 4365 **              byte 4                  : # of Voltage sensor(example 3)
 4366 **              byte 5                  : # of temperature sensor(example 2)
 4367 **              byte 6                  : # of power
 4368 **              byte 7/8        : Fan#0 (RPM)
 4369 **              byte 9/10       : Fan#1
 4370 **              byte 11/12              : Voltage#0 original value in *1000
 4371 **              byte 13/14              : Voltage#0 value
 4372 **              byte 15/16              : Voltage#1 org
 4373 **              byte 17/18              : Voltage#1
 4374 **              byte 19/20              : Voltage#2 org
 4375 **              byte 21/22              : Voltage#2
 4376 **              byte 23                 : Temp#0
 4377 **              byte 24                 : Temp#1
 4378 **              byte 25                 : Power indicator (bit0 : power#0, bit1 : power#1)
 4379 **              byte 26                 : UPS indicator
 4380 **      GUI_QUICK_CREATE : Quick create raid/volume set
 4381 **          byte 0,1        : length
 4382 **          byte 2          : command code 0x20
 4383 **          byte 3/4/5/6    : raw capacity
 4384 **          byte 7                      : raid level
 4385 **          byte 8                      : stripe size
 4386 **          byte 9                      : spare
 4387 **          byte 10/11/12/13: device mask (the devices to create raid/volume) 
 4388 **                                This function is removed, application like to implement quick create function 
 4389 **                                need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function.
 4390 **      GUI_GET_INFO_R : Get Raid Set Information
 4391 **              byte 0,1        : length
 4392 **              byte 2          : command code 0x20
 4393 **              byte 3          : raidset#
 4394 **    
 4395 **      typedef struct sGUI_RAIDSET
 4396 **      {
 4397 **              BYTE grsRaidSetName[16];
 4398 **              DWORD grsCapacity;
 4399 **              DWORD grsCapacityX;
 4400 **              DWORD grsFailMask;
 4401 **              BYTE grsDevArray[32];
 4402 **              BYTE grsMemberDevices;
 4403 **              BYTE grsNewMemberDevices;
 4404 **              BYTE grsRaidState;
 4405 **              BYTE grsVolumes;
 4406 **              BYTE grsVolumeList[16];
 4407 **              BYTE grsRes1;
 4408 **              BYTE grsRes2;
 4409 **              BYTE grsRes3;
 4410 **              BYTE grsFreeSegments;
 4411 **              DWORD grsRawStripes[8];
 4412 **              DWORD grsRes4;
 4413 **              DWORD grsRes5; //     Total to 128 bytes
 4414 **              DWORD grsRes6; //     Total to 128 bytes
 4415 **      } sGUI_RAIDSET, *pGUI_RAIDSET;
 4416 **      GUI_GET_INFO_V : Get Volume Set Information
 4417 **              byte 0,1        : length
 4418 **              byte 2          : command code 0x21
 4419 **              byte 3          : volumeset#
 4420 **    
 4421 **      typedef struct sGUI_VOLUMESET
 4422 **      {
 4423 **              BYTE gvsVolumeName[16]; //     16
 4424 **              DWORD gvsCapacity;
 4425 **              DWORD gvsCapacityX;
 4426 **              DWORD gvsFailMask;
 4427 **              DWORD gvsStripeSize;
 4428 **              DWORD gvsNewFailMask;
 4429 **              DWORD gvsNewStripeSize;
 4430 **              DWORD gvsVolumeStatus;
 4431 **              DWORD gvsProgress; //     32
 4432 **              sSCSI_ATTR gvsScsi; 
 4433 **              BYTE gvsMemberDisks;
 4434 **              BYTE gvsRaidLevel; //     8
 4435 **    
 4436 **              BYTE gvsNewMemberDisks;
 4437 **              BYTE gvsNewRaidLevel;
 4438 **              BYTE gvsRaidSetNumber;
 4439 **              BYTE gvsRes0; //     4
 4440 **              BYTE gvsRes1[4]; //     64 bytes
 4441 **      } sGUI_VOLUMESET, *pGUI_VOLUMESET;
 4442 **    
 4443 **      GUI_GET_INFO_P : Get Physical Drive Information
 4444 **              byte 0,1        : length
 4445 **              byte 2          : command code 0x22
 4446 **              byte 3          : drive # (from 0 to max-channels - 1)
 4447 **    
 4448 **      typedef struct sGUI_PHY_DRV
 4449 **      {
 4450 **              BYTE gpdModelName[40];
 4451 **              BYTE gpdSerialNumber[20];
 4452 **              BYTE gpdFirmRev[8];
 4453 **              DWORD gpdCapacity;
 4454 **              DWORD gpdCapacityX; //     Reserved for expansion
 4455 **              BYTE gpdDeviceState;
 4456 **              BYTE gpdPioMode;
 4457 **              BYTE gpdCurrentUdmaMode;
 4458 **              BYTE gpdUdmaMode;
 4459 **              BYTE gpdDriveSelect;
 4460 **              BYTE gpdRaidNumber; //     0xff if not belongs to a raid set
 4461 **              sSCSI_ATTR gpdScsi;
 4462 **              BYTE gpdReserved[40]; //     Total to 128 bytes
 4463 **      } sGUI_PHY_DRV, *pGUI_PHY_DRV;
 4464 **    
 4465 **      GUI_GET_INFO_S : Get System Information
 4466 **              byte 0,1        : length
 4467 **              byte 2          : command code 0x23
 4468 **    
 4469 **      typedef struct sCOM_ATTR
 4470 **      {
 4471 **              BYTE comBaudRate;
 4472 **              BYTE comDataBits;
 4473 **              BYTE comStopBits;
 4474 **              BYTE comParity;
 4475 **              BYTE comFlowControl;
 4476 **      } sCOM_ATTR, *pCOM_ATTR;
 4477 **    
 4478 **      typedef struct sSYSTEM_INFO
 4479 **      {
 4480 **              BYTE gsiVendorName[40];
 4481 **              BYTE gsiSerialNumber[16];
 4482 **              BYTE gsiFirmVersion[16];
 4483 **              BYTE gsiBootVersion[16];
 4484 **              BYTE gsiMbVersion[16];
 4485 **              BYTE gsiModelName[8];
 4486 **              BYTE gsiLocalIp[4];
 4487 **              BYTE gsiCurrentIp[4];
 4488 **              DWORD gsiTimeTick;
 4489 **              DWORD gsiCpuSpeed;
 4490 **              DWORD gsiICache;
 4491 **              DWORD gsiDCache;
 4492 **              DWORD gsiScache;
 4493 **              DWORD gsiMemorySize;
 4494 **              DWORD gsiMemorySpeed;
 4495 **              DWORD gsiEvents;
 4496 **              BYTE gsiMacAddress[6];
 4497 **              BYTE gsiDhcp;
 4498 **              BYTE gsiBeeper;
 4499 **              BYTE gsiChannelUsage;
 4500 **              BYTE gsiMaxAtaMode;
 4501 **              BYTE gsiSdramEcc; //     1:if ECC enabled
 4502 **              BYTE gsiRebuildPriority;
 4503 **              sCOM_ATTR gsiComA; //     5 bytes
 4504 **              sCOM_ATTR gsiComB; //     5 bytes
 4505 **              BYTE gsiIdeChannels;
 4506 **              BYTE gsiScsiHostChannels;
 4507 **              BYTE gsiIdeHostChannels;
 4508 **              BYTE gsiMaxVolumeSet;
 4509 **              BYTE gsiMaxRaidSet;
 4510 **              BYTE gsiEtherPort; //     1:if ether net port supported
 4511 **              BYTE gsiRaid6Engine; //     1:Raid6 engine supported
 4512 **              BYTE gsiRes[75];
 4513 **      } sSYSTEM_INFO, *pSYSTEM_INFO;
 4514 **    
 4515 **      GUI_CLEAR_EVENT : Clear System Event
 4516 **              byte 0,1        : length
 4517 **              byte 2          : command code 0x24
 4518 **    
 4519 **      GUI_MUTE_BEEPER : Mute current beeper
 4520 **              byte 0,1        : length
 4521 **              byte 2          : command code 0x30
 4522 **    
 4523 **      GUI_BEEPER_SETTING : Disable beeper
 4524 **              byte 0,1        : length
 4525 **              byte 2          : command code 0x31
 4526 **              byte 3          : 0->disable, 1->enable
 4527 **    
 4528 **      GUI_SET_PASSWORD : Change password
 4529 **              byte 0,1        : length
 4530 **              byte 2                  : command code 0x32
 4531 **              byte 3                  : pass word length ( must <= 15 )
 4532 **              byte 4                  : password (must be alpha-numerical)
 4533 **    
 4534 **      GUI_HOST_INTERFACE_MODE : Set host interface mode
 4535 **              byte 0,1        : length
 4536 **              byte 2                  : command code 0x33
 4537 **              byte 3                  : 0->Independent, 1->cluster
 4538 **    
 4539 **      GUI_REBUILD_PRIORITY : Set rebuild priority
 4540 **              byte 0,1        : length
 4541 **              byte 2                  : command code 0x34
 4542 **              byte 3                  : 0/1/2/3 (low->high)
 4543 **    
 4544 **      GUI_MAX_ATA_MODE : Set maximum ATA mode to be used
 4545 **              byte 0,1        : length
 4546 **              byte 2                  : command code 0x35
 4547 **              byte 3                  : 0/1/2/3 (133/100/66/33)
 4548 **    
 4549 **      GUI_RESET_CONTROLLER : Reset Controller
 4550 **              byte 0,1        : length
 4551 **              byte 2          : command code 0x36
 4552 **                            *Response with VT100 screen (discard it)
 4553 **    
 4554 **      GUI_COM_PORT_SETTING : COM port setting
 4555 **              byte 0,1        : length
 4556 **              byte 2                  : command code 0x37
 4557 **              byte 3                  : 0->COMA (term port), 1->COMB (debug port)
 4558 **              byte 4                  : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200)
 4559 **              byte 5                  : data bit (0:7 bit, 1:8 bit : must be 8 bit)
 4560 **              byte 6                  : stop bit (0:1, 1:2 stop bits)
 4561 **              byte 7                  : parity (0:none, 1:off, 2:even)
 4562 **              byte 8                  : flow control (0:none, 1:xon/xoff, 2:hardware => must use none)
 4563 **    
 4564 **      GUI_NO_OPERATION : No operation
 4565 **              byte 0,1        : length
 4566 **              byte 2          : command code 0x38
 4567 **    
 4568 **      GUI_DHCP_IP : Set DHCP option and local IP address
 4569 **              byte 0,1        : length
 4570 **              byte 2          : command code 0x39
 4571 **              byte 3          : 0:dhcp disabled, 1:dhcp enabled
 4572 **              byte 4/5/6/7    : IP address
 4573 **    
 4574 **      GUI_CREATE_PASS_THROUGH : Create pass through disk
 4575 **              byte 0,1        : length
 4576 **              byte 2                  : command code 0x40
 4577 **              byte 3                  : device #
 4578 **              byte 4                  : scsi channel (0/1)
 4579 **              byte 5                  : scsi id (0-->15)
 4580 **              byte 6                  : scsi lun (0-->7)
 4581 **              byte 7                  : tagged queue (1 : enabled)
 4582 **              byte 8                  : cache mode (1 : enabled)
 4583 **              byte 9                  : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
 4584 **                                                                  (0/1/2/3/4, 33/66/100/133/150 for ide  )
 4585 **    
 4586 **      GUI_MODIFY_PASS_THROUGH : Modify pass through disk
 4587 **              byte 0,1        : length
 4588 **              byte 2                  : command code 0x41
 4589 **              byte 3                  : device #
 4590 **              byte 4                  : scsi channel (0/1)
 4591 **              byte 5                  : scsi id (0-->15)
 4592 **              byte 6                  : scsi lun (0-->7)
 4593 **              byte 7                  : tagged queue (1 : enabled)
 4594 **              byte 8                  : cache mode (1 : enabled)
 4595 **              byte 9                  : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
 4596 **                                                              (0/1/2/3/4, 33/66/100/133/150 for ide  )
 4597 **    
 4598 **      GUI_DELETE_PASS_THROUGH : Delete pass through disk
 4599 **              byte 0,1        : length
 4600 **              byte 2          : command code 0x42
 4601 **              byte 3          : device# to be deleted
 4602 **    
 4603 **      GUI_IDENTIFY_DEVICE : Identify Device
 4604 **              byte 0,1        : length
 4605 **              byte 2          : command code 0x43
 4606 **              byte 3          : Flash Method(0:flash selected, 1:flash not selected)
 4607 **              byte 4/5/6/7    : IDE device mask to be flashed
 4608 **                           note .... no response data available
 4609 **    
 4610 **      GUI_CREATE_RAIDSET : Create Raid Set
 4611 **              byte 0,1        : length
 4612 **              byte 2          : command code 0x50
 4613 **              byte 3/4/5/6    : device mask
 4614 **              byte 7-22       : raidset name (if byte 7 == 0:use default)
 4615 **    
 4616 **      GUI_DELETE_RAIDSET : Delete Raid Set
 4617 **              byte 0,1        : length
 4618 **              byte 2          : command code 0x51
 4619 **              byte 3          : raidset#
 4620 **    
 4621 **      GUI_EXPAND_RAIDSET : Expand Raid Set 
 4622 **              byte 0,1        : length
 4623 **              byte 2          : command code 0x52
 4624 **              byte 3          : raidset#
 4625 **              byte 4/5/6/7    : device mask for expansion
 4626 **              byte 8/9/10     : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
 4627 **              byte 11/12/13   : repeat for each volume in the raidset ....
 4628 **    
 4629 **      GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 
 4630 **              byte 0,1        : length
 4631 **              byte 2          : command code 0x53
 4632 **              byte 3          : raidset#
 4633 **    
 4634 **      GUI_CREATE_HOT_SPARE : Create hot spare disk 
 4635 **              byte 0,1        : length
 4636 **              byte 2          : command code 0x54
 4637 **              byte 3/4/5/6    : device mask for hot spare creation
 4638 **    
 4639 **      GUI_DELETE_HOT_SPARE : Delete hot spare disk 
 4640 **              byte 0,1        : length
 4641 **              byte 2          : command code 0x55
 4642 **              byte 3/4/5/6    : device mask for hot spare deletion
 4643 **    
 4644 **      GUI_CREATE_VOLUME : Create volume set 
 4645 **              byte 0,1        : length
 4646 **              byte 2          : command code 0x60
 4647 **              byte 3          : raidset#
 4648 **              byte 4-19       : volume set name (if byte4 == 0, use default)
 4649 **              byte 20-27      : volume capacity (blocks)
 4650 **              byte 28                 : raid level
 4651 **              byte 29                 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
 4652 **              byte 30                 : channel
 4653 **              byte 31                 : ID
 4654 **              byte 32                 : LUN
 4655 **              byte 33                 : 1 enable tag
 4656 **              byte 34                 : 1 enable cache
 4657 **              byte 35                 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
 4658 **                                                              (0/1/2/3/4->33/66/100/133/150 for IDE  )
 4659 **              byte 36                 : 1 to select quick init
 4660 **    
 4661 **      GUI_MODIFY_VOLUME : Modify volume Set
 4662 **              byte 0,1        : length
 4663 **              byte 2          : command code 0x61
 4664 **              byte 3          : volumeset#
 4665 **              byte 4-19       : new volume set name (if byte4 == 0, not change)
 4666 **              byte 20-27      : new volume capacity (reserved)
 4667 **              byte 28                 : new raid level
 4668 **              byte 29                 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
 4669 **              byte 30                 : new channel
 4670 **              byte 31                 : new ID
 4671 **              byte 32                 : new LUN
 4672 **              byte 33                 : 1 enable tag
 4673 **              byte 34                 : 1 enable cache
 4674 **              byte 35                 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
 4675 **                                                              (0/1/2/3/4->33/66/100/133/150 for IDE  )
 4676 **    
 4677 **      GUI_DELETE_VOLUME : Delete volume set
 4678 **              byte 0,1        : length
 4679 **              byte 2          : command code 0x62
 4680 **              byte 3          : volumeset#
 4681 **    
 4682 **      GUI_START_CHECK_VOLUME : Start volume consistency check
 4683 **              byte 0,1        : length
 4684 **              byte 2          : command code 0x63
 4685 **              byte 3          : volumeset#
 4686 **    
 4687 **      GUI_STOP_CHECK_VOLUME : Stop volume consistency check
 4688 **              byte 0,1        : length
 4689 **              byte 2          : command code 0x64
 4690 ** ---------------------------------------------------------------------   
 4691 **    4. Returned data
 4692 ** ---------------------------------------------------------------------   
 4693 **      (A) Header          : 3 bytes sequence (0x5E, 0x01, 0x61)
 4694 **      (B) Length          : 2 bytes (low byte 1st, excludes length and checksum byte)
 4695 **      (C) status or data  :
 4696 **           <1> If length == 1 ==> 1 byte status code
 4697 **                                                              #define GUI_OK                    0x41
 4698 **                                                              #define GUI_RAIDSET_NOT_NORMAL    0x42
 4699 **                                                              #define GUI_VOLUMESET_NOT_NORMAL  0x43
 4700 **                                                              #define GUI_NO_RAIDSET            0x44
 4701 **                                                              #define GUI_NO_VOLUMESET          0x45
 4702 **                                                              #define GUI_NO_PHYSICAL_DRIVE     0x46
 4703 **                                                              #define GUI_PARAMETER_ERROR       0x47
 4704 **                                                              #define GUI_UNSUPPORTED_COMMAND   0x48
 4705 **                                                              #define GUI_DISK_CONFIG_CHANGED   0x49
 4706 **                                                              #define GUI_INVALID_PASSWORD      0x4a
 4707 **                                                              #define GUI_NO_DISK_SPACE         0x4b
 4708 **                                                              #define GUI_CHECKSUM_ERROR        0x4c
 4709 **                                                              #define GUI_PASSWORD_REQUIRED     0x4d
 4710 **           <2> If length > 1 ==> data block returned from controller and the contents depends on the command code
 4711 **        (E) Checksum : checksum of length and status or data byte
 4712 **************************************************************************
 4713 */

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