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sys/dev/arcmsr/arcmsr.h
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1 /* 2 *********************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA SATA RAID HOST Adapter 8 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 9 *********************************************************************************************** 10 ************************************************************************ 11 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 12 ** 13 ** Web site: www.areca.com.tw 14 ** E-mail: erich@areca.com.tw 15 ** 16 ** Redistribution and use in source and binary forms,with or without 17 ** modification,are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice,this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice,this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 31 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 32 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ************************************************************************** 38 * $FreeBSD: releng/6.2/sys/dev/arcmsr/arcmsr.h 165452 2006-12-21 21:59:19Z scottl $ 39 */ 40 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.13 2006-8-18" 41 #define ARCMSR_SCSI_INITIATOR_ID 255 42 #define ARCMSR_DEV_SECTOR_SIZE 512 43 #define ARCMSR_MAX_XFER_SECTORS 4096 44 #define ARCMSR_MAX_TARGETID 16 /*16 max target id + 1*/ 45 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 46 #define ARCMSR_MAX_CHIPTYPE_NUM 4 47 #define ARCMSR_MAX_OUTSTANDING_CMD 256 48 #define ARCMSR_MAX_START_JOB 257 49 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 50 #define ARCMSR_MAX_FREESRB_NUM 320 51 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 52 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 53 #define ARCMSR_MAX_ADAPTER 4 54 /* 55 ********************************************************************* 56 */ 57 #ifndef TRUE 58 #define TRUE 1 59 #endif 60 #ifndef FALSE 61 #define FALSE 0 62 #endif 63 #ifndef INTR_ENTROPY 64 # define INTR_ENTROPY 0 65 #endif 66 67 #ifndef offsetof 68 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 69 #endif 70 /* 71 ********************************************************************************** 72 ** 73 ********************************************************************************** 74 */ 75 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 76 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 77 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 78 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 79 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 80 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 81 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 82 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 83 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 84 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 85 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 86 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 87 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 88 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 91 92 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 93 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 94 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 95 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 96 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 97 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 98 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 99 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 100 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 101 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 102 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 103 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 104 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 105 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 106 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 107 108 #ifndef PCIR_BARS 109 #define PCIR_BARS 0x10 110 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 111 #endif 112 113 #define PCI_BASE_ADDR0 0x10 114 #define PCI_BASE_ADDR1 0x14 115 #define PCI_BASE_ADDR2 0x18 116 #define PCI_BASE_ADDR3 0x1C 117 #define PCI_BASE_ADDR4 0x20 118 #define PCI_BASE_ADDR5 0x24 119 /* 120 ********************************************************************************** 121 ** 122 ********************************************************************************** 123 */ 124 #define ARCMSR_SCSICMD_IOCTL 0x77 125 #define ARCMSR_CDEVSW_IOCTL 0x88 126 #define ARCMSR_MESSAGE_FAIL 0x0001 127 #define ARCMSR_MESSAGE_SUCCESS 0x0000 128 /* 129 ********************************************************************************** 130 ** 131 ********************************************************************************** 132 */ 133 #define arcmsr_ccbsrb_ptr spriv_ptr0 134 #define arcmsr_ccbacb_ptr spriv_ptr1 135 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 136 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 137 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 138 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 139 /* 140 ********************************************************************************** 141 ** 142 ********************************************************************************** 143 */ 144 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 145 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 146 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 147 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 148 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 149 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 150 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 151 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 152 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 153 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 154 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 155 /*DeviceType*/ 156 #define ARECA_SATA_RAID 0x90000000 157 /*FunctionCode*/ 158 #define FUNCTION_READ_RQBUFFER 0x0801 159 #define FUNCTION_WRITE_WQBUFFER 0x0802 160 #define FUNCTION_CLEAR_RQBUFFER 0x0803 161 #define FUNCTION_CLEAR_WQBUFFER 0x0804 162 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 163 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 164 #define FUNCTION_SAY_HELLO 0x0807 165 #define FUNCTION_SAY_GOODBYE 0x0808 166 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 167 /* 168 ************************************************************************ 169 ** IOCTL CONTROL CODE 170 ************************************************************************ 171 */ 172 struct CMD_MESSAGE { 173 u_int32_t HeaderLength; 174 u_int8_t Signature[8]; 175 u_int32_t Timeout; 176 u_int32_t ControlCode; 177 u_int32_t ReturnCode; 178 u_int32_t Length; 179 }; 180 181 struct CMD_MESSAGE_FIELD { 182 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 183 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 184 }; 185 /* ARECA IO CONTROL CODE*/ 186 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 187 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 188 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 189 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 190 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 191 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 192 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 193 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 194 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 195 /* ARECA IOCTL ReturnCode */ 196 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 197 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 198 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 199 /* 200 ************************************************************* 201 ** structure for holding DMA address data 202 ************************************************************* 203 */ 204 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 205 /* 206 ************************************************************************************************ 207 ** ARECA FIRMWARE SPEC 208 ************************************************************************************************ 209 ** Usage of IOP331 adapter 210 ** (All In/Out is in IOP331's view) 211 ** 1. Message 0 --> InitThread message and retrun code 212 ** 2. Doorbell is used for RS-232 emulation 213 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 214 ** bit1 -- data out has been read (DRIVER DATA READ OK) 215 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 216 ** bit1 -- data in has been read (IOP331 DATA READ OK) 217 ** 3. Index Memory Usage 218 ** offset 0xf00 : for RS232 out (request buffer) 219 ** offset 0xe00 : for RS232 in (scratch buffer) 220 ** offset 0xa00 : for inbound message code message_rwbuffer (driver send to IOP331) 221 ** offset 0xa00 : for outbound message code message_rwbuffer (IOP331 send to driver) 222 ** 4. RS-232 emulation 223 ** Currently 128 byte buffer is used 224 ** 1st u_int32_t : Data length (1--124) 225 ** Byte 4--127 : Max 124 bytes of data 226 ** 5. PostQ 227 ** All SCSI Command must be sent through postQ: 228 ** (inbound queue port) Request frame must be 32 bytes aligned 229 ** # bit27--bit31 => flag for post ccb 230 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 231 ** bit31 : 0 : 256 bytes frame 232 ** 1 : 512 bytes frame 233 ** bit30 : 0 : normal request 234 ** 1 : BIOS request 235 ** bit29 : reserved 236 ** bit28 : reserved 237 ** bit27 : reserved 238 ** ------------------------------------------------------------------------------- 239 ** (outbount queue port) Request reply 240 ** # bit27--bit31 => flag for reply 241 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 242 ** bit31 : must be 0 (for this type of reply) 243 ** bit30 : reserved for BIOS handshake 244 ** bit29 : reserved 245 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 246 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 247 ** bit27 : reserved 248 ** 6. BIOS request 249 ** All BIOS request is the same with request from PostQ 250 ** Except : 251 ** Request frame is sent from configuration space 252 ** offset: 0x78 : Request Frame (bit30 == 1) 253 ** offset: 0x18 : writeonly to generate IRQ to IOP331 254 ** Completion of request: 255 ** (bit30 == 0, bit28==err flag) 256 ** 7. Definition of SGL entry (structure) 257 ** 8. Message1 Out - Diag Status Code (????) 258 ** 9. Message0 message code : 259 ** 0x00 : NOP 260 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code message_rwbuffer (IOP331 send to driver) 261 ** Signature 0x87974060(4) 262 ** Request len 0x00000200(4) 263 ** numbers of queue 0x00000100(4) 264 ** SDRAM Size 0x00000100(4)-->256 MB 265 ** IDE Channels 0x00000008(4) 266 ** vendor 40 bytes char 267 ** model 8 bytes char 268 ** FirmVer 16 bytes char 269 ** Device Map 16 bytes char 270 ** 271 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 272 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code message_rwbuffer (driver send to IOP331) 273 ** Signature 0x87974063(4) 274 ** UPPER32 of Request Frame (4)-->Driver Only 275 ** 0x03 : Reset (Abort all queued Command) 276 ** 0x04 : Stop Background Activity 277 ** 0x05 : Flush Cache 278 ** 0x06 : Start Background Activity (re-start if background is halted) 279 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 280 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code message_rwbuffer (driver to IOP331) 281 ** byte 0 : 0xaa <-- signature 282 ** byte 1 : 0x55 <-- signature 283 ** byte 2 : year (04) 284 ** byte 3 : month (1..12) 285 ** byte 4 : date (1..31) 286 ** byte 5 : hour (0..23) 287 ** byte 6 : minute (0..59) 288 ** byte 7 : second (0..59) 289 ************************************************************************************************ 290 */ 291 /* signature of set and get firmware config */ 292 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 293 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 294 /* message code of inbound message register */ 295 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 296 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 297 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 298 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 299 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 300 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 301 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 302 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 303 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 304 /* doorbell interrupt generator */ 305 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 306 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 307 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 308 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 309 /* srb areca cdb flag */ 310 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 311 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 312 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 313 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 314 /* outbound firmware ok */ 315 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 316 /* 317 ********************************** 318 ** 319 ********************************** 320 */ 321 /* size 8 bytes */ 322 struct SG32ENTRY { /* length bit 24 == 0 */ 323 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 324 u_int32_t address; 325 }; 326 /* size 12 bytes */ 327 struct SG64ENTRY { /* length bit 24 == 1 */ 328 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 329 u_int32_t address; 330 u_int32_t addresshigh; 331 }; 332 struct SGENTRY_UNION { 333 union { 334 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 335 struct SG64ENTRY sg64entry; /* 30h */ 336 }u; 337 }; 338 /* 339 ********************************** 340 ** 341 ********************************** 342 */ 343 struct QBUFFER { 344 u_int32_t data_len; 345 u_int8_t data[124]; 346 }; 347 /* 348 ************************************************************************************************ 349 ** FIRMWARE INFO 350 ************************************************************************************************ 351 */ 352 struct FIRMWARE_INFO { 353 u_int32_t signature; /*0,00-03*/ 354 u_int32_t request_len; /*1,04-07*/ 355 u_int32_t numbers_queue; /*2,08-11*/ 356 u_int32_t sdram_size; /*3,12-15*/ 357 u_int32_t ide_channels; /*4,16-19*/ 358 char vendor[40]; /*5,20-59*/ 359 char model[8]; /*15,60-67*/ 360 char firmware_ver[16]; /*17,68-83*/ 361 char device_map[16]; /*21,84-99*/ 362 }; 363 /* 364 ************************************************************************************************ 365 ** size 0x1F8 (504) 366 ************************************************************************************************ 367 */ 368 struct ARCMSR_CDB { 369 u_int8_t Bus; /* 00h should be 0 */ 370 u_int8_t TargetID; /* 01h should be 0--15 */ 371 u_int8_t LUN; /* 02h should be 0--7 */ 372 u_int8_t Function; /* 03h should be 1 */ 373 374 u_int8_t CdbLength; /* 04h not used now */ 375 u_int8_t sgcount; /* 05h */ 376 u_int8_t Flags; /* 06h */ 377 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 378 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 379 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 380 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 381 #define ARCMSR_CDB_FLAG_HEADQ 0x08 382 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 383 u_int8_t Reserved1; /* 07h */ 384 385 u_int32_t Context; /* 08h Address of this request */ 386 u_int32_t DataLength; /* 0ch not used now */ 387 388 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 389 /* 390 ******************************************************** 391 **Device Status : the same from SCSI bus if error occur 392 ** SCSI bus status codes. 393 ******************************************************** 394 */ 395 u_int8_t DeviceStatus; /* 20h if error */ 396 #define SCSISTAT_GOOD 0x00 397 #define SCSISTAT_CHECK_CONDITION 0x02 398 #define SCSISTAT_CONDITION_MET 0x04 399 #define SCSISTAT_BUSY 0x08 400 #define SCSISTAT_INTERMEDIATE 0x10 401 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 402 #define SCSISTAT_RESERVATION_CONFLICT 0x18 403 #define SCSISTAT_COMMAND_TERMINATED 0x22 404 #define SCSISTAT_QUEUE_FULL 0x28 405 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 406 #define ARCMSR_DEV_ABORTED 0xF1 407 #define ARCMSR_DEV_INIT_FAIL 0xF2 408 409 u_int8_t SenseData[15]; /* 21h output */ 410 411 union { 412 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 413 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 414 } u; 415 }; 416 /* 417 ********************************************************************* 418 ** Command Control Block (SrbExtension) 419 ** SRB must be not cross page boundary,and the order from offset 0 420 ** structure describing an ATA disk request 421 ** this SRB length must be 32 bytes boundary 422 ********************************************************************* 423 */ 424 struct CommandControlBlock { 425 struct ARCMSR_CDB arcmsr_cdb; 426 /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 427 u_int32_t cdb_shifted_phyaddr; /* 504-507 */ 428 u_int32_t reserved1; /* 508-511*/ 429 /* ======================512+32 bytes============================ */ 430 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) || defined(__sparc64__) || defined(__powerpc__) 431 union ccb * pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 432 struct AdapterControlBlock * acb; /* 520-523 524-527 */ 433 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 434 u_int16_t srb_flags; /* 536-537 */ 435 #define SRB_FLAG_READ 0x0000 436 #define SRB_FLAG_WRITE 0x0001 437 #define SRB_FLAG_ERROR 0x0002 438 #define SRB_FLAG_FLUSHCACHE 0x0004 439 #define SRB_FLAG_MASTER_ABORTED 0x0008 440 u_int16_t startdone; /* 538-539 */ 441 #define ARCMSR_SRB_DONE 0x0000 442 #define ARCMSR_SRB_START 0x55AA 443 #define ARCMSR_SRB_ABORTED 0xAA55 444 #define ARCMSR_SRB_ILLEGAL 0xFFFF 445 u_int32_t reserved2; /* 540-543 */ 446 #else 447 union ccb * pccb; /* 512-515 pointer of freebsd scsi command */ 448 struct AdapterControlBlock * acb; /* 516-519 */ 449 bus_dmamap_t dm_segs_dmamap; /* 520-523 */ 450 u_int16_t srb_flags; /* 524-525 */ 451 #define SRB_FLAG_READ 0x0000 452 #define SRB_FLAG_WRITE 0x0001 453 #define SRB_FLAG_ERROR 0x0002 454 #define SRB_FLAG_FLUSHCACHE 0x0004 455 #define SRB_FLAG_MASTER_ABORTED 0x0008 456 u_int16_t startdone; /* 526-527 */ 457 #define ARCMSR_SRB_DONE 0x0000 458 #define ARCMSR_SRB_START 0x55AA 459 #define ARCMSR_SRB_ABORTED 0xAA55 460 #define ARCMSR_SRB_ILLEGAL 0xFFFF 461 u_int32_t reserved2[4]; /* 528-531 532-535 536-539 540-543 */ 462 #endif 463 /* ========================================================== */ 464 }; 465 /* 466 ********************************************************************* 467 ** Adapter Control Block 468 ********************************************************************* 469 */ 470 struct AdapterControlBlock { 471 bus_space_tag_t btag; 472 bus_space_handle_t bhandle; 473 bus_dma_tag_t parent_dmat; 474 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 475 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 476 bus_dmamap_t srb_dmamap; 477 device_t pci_dev; 478 #if __FreeBSD_version < 503000 479 dev_t ioctl_dev; 480 #else 481 struct cdev * ioctl_dev; 482 #endif 483 int pci_unit; 484 485 struct resource * sys_res_arcmsr; 486 struct resource * irqres; 487 void * ih; /* interrupt handle */ 488 489 /* Hooks into the CAM XPT */ 490 struct cam_sim *psim; 491 struct cam_path *ppath; 492 u_int8_t * uncacheptr; 493 unsigned long vir2phy_offset; 494 /* Offset is used in making arc cdb physical to virtual calculations */ 495 u_int32_t outbound_int_enable; 496 497 struct MessageUnit * pmu; /* message unit ATU inbound base address0 */ 498 499 u_int8_t adapter_index; /* */ 500 u_int8_t irq; 501 u_int16_t acb_flags; /* */ 502 #define ACB_F_SCSISTOPADAPTER 0x0001 503 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 504 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 505 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 506 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 507 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 508 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 509 #define ACB_F_BUS_RESET 0x0080 510 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 511 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 512 513 struct CommandControlBlock * psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 514 struct CommandControlBlock * srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 515 int32_t workingsrb_doneindex; /* done srb array index */ 516 int32_t workingsrb_startindex; /* start srb array index */ 517 int32_t srboutstandingcount; 518 519 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 520 u_int32_t rqbuf_firstindex; /* first of read buffer */ 521 u_int32_t rqbuf_lastindex; /* last of read buffer */ 522 523 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 524 u_int32_t wqbuf_firstindex; /* first of write buffer */ 525 u_int32_t wqbuf_lastindex; /* last of write buffer */ 526 527 arcmsr_lock_t workingQ_done_lock; 528 arcmsr_lock_t workingQ_start_lock; 529 arcmsr_lock_t qbuffer_lock; 530 531 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 532 #define ARECA_RAID_GONE 0x55 533 #define ARECA_RAID_GOOD 0xaa 534 u_int32_t num_resets; 535 u_int32_t num_aborts; 536 u_int32_t firm_request_len; /*1,04-07*/ 537 u_int32_t firm_numbers_queue; /*2,08-11*/ 538 u_int32_t firm_sdram_size; /*3,12-15*/ 539 u_int32_t firm_ide_channels; /*4,16-19*/ 540 char firm_model[12]; /*15,60-67*/ 541 char firm_version[20]; /*17,68-83*/ 542 };/* HW_DEVICE_EXTENSION */ 543 /* 544 ************************************************************* 545 ************************************************************* 546 */ 547 struct SENSE_DATA { 548 u_int8_t ErrorCode:7; 549 u_int8_t Valid:1; 550 u_int8_t SegmentNumber; 551 u_int8_t SenseKey:4; 552 u_int8_t Reserved:1; 553 u_int8_t IncorrectLength:1; 554 u_int8_t EndOfMedia:1; 555 u_int8_t FileMark:1; 556 u_int8_t Information[4]; 557 u_int8_t AdditionalSenseLength; 558 u_int8_t CommandSpecificInformation[4]; 559 u_int8_t AdditionalSenseCode; 560 u_int8_t AdditionalSenseCodeQualifier; 561 u_int8_t FieldReplaceableUnitCode; 562 u_int8_t SenseKeySpecific[3]; 563 }; 564 /* 565 ********************************** 566 ** Peripheral Device Type definitions 567 ********************************** 568 */ 569 #define SCSI_DASD 0x00 /* Direct-access Device */ 570 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 571 #define SCSI_PRINTER 0x02 /* Printer device */ 572 #define SCSI_PROCESSOR 0x03 /* Processor device */ 573 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 574 #define SCSI_CDROM 0x05 /* CD-ROM device */ 575 #define SCSI_SCANNER 0x06 /* Scanner device */ 576 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 577 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 578 #define SCSI_COMM 0x09 /* Communications device */ 579 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 580 /* 581 ************************************************************************************************************ 582 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 583 ** 80331 PCI-to-PCI Bridge 584 ** PCI Configuration Space 585 ** 586 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 587 ** Programming Interface 588 ** ======================== 589 ** Configuration Register Address Space Groupings and Ranges 590 ** ============================================================= 591 ** Register Group Configuration Offset 592 ** ------------------------------------------------------------- 593 ** Standard PCI Configuration 00-3Fh 594 ** ------------------------------------------------------------- 595 ** Device Specific Registers 40-A7h 596 ** ------------------------------------------------------------- 597 ** Reserved A8-CBh 598 ** ------------------------------------------------------------- 599 ** Enhanced Capability List CC-FFh 600 ** ========================================================================================================== 601 ** Standard PCI [Type 1] Configuration Space Address Map 602 ** ********************************************************************************************************** 603 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 604 ** ---------------------------------------------------------------------------------------------------------- 605 ** | Device ID | Vendor ID | 00h 606 ** ---------------------------------------------------------------------------------------------------------- 607 ** | Primary Status | Primary Command | 04h 608 ** ---------------------------------------------------------------------------------------------------------- 609 ** | Class Code | RevID | 08h 610 ** ---------------------------------------------------------------------------------------------------------- 611 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 612 ** ---------------------------------------------------------------------------------------------------------- 613 ** | Reserved | 10h 614 ** ---------------------------------------------------------------------------------------------------------- 615 ** | Reserved | 14h 616 ** ---------------------------------------------------------------------------------------------------------- 617 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 618 ** ---------------------------------------------------------------------------------------------------------- 619 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 620 ** ---------------------------------------------------------------------------------------------------------- 621 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 622 ** ---------------------------------------------------------------------------------------------------------- 623 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 624 ** ---------------------------------------------------------------------------------------------------------- 625 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 626 ** ---------------------------------------------------------------------------------------------------------- 627 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 628 ** ---------------------------------------------------------------------------------------------------------- 629 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 630 ** ---------------------------------------------------------------------------------------------------------- 631 ** | Reserved | Capabilities Pointer | 34h 632 ** ---------------------------------------------------------------------------------------------------------- 633 ** | Reserved | 38h 634 ** ---------------------------------------------------------------------------------------------------------- 635 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 636 **============================================================================================================= 637 */ 638 /* 639 **============================================================================================================= 640 ** 0x03-0x00 : 641 ** Bit Default Description 642 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 643 ** ID is unique per product speed as indicated. 644 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 645 **============================================================================================================= 646 */ 647 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 648 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 649 /* 650 **============================================================================== 651 ** 0x05-0x04 : command register 652 ** Bit Default Description 653 **15:11 00h Reserved 654 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 655 ** The bridge does not support interrupts. 656 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 657 ** transactions on the primary bus. 658 ** The bridge does not generate fast back to back 659 ** transactions on the primary bus. 660 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 661 ** 0=The bridge does not assert P_SERR#. 662 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 663 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 664 ** that bridge does not perform address or data stepping, 665 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 666 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 667 ** Also bridge does not assert P_SERR# in response to 668 ** a detected address or attribute parity error. 669 ** 1=When a data parity error is detected bridge asserts S_PERR#. 670 ** The bridge also asserts P_SERR# 671 ** (when enabled globally via bit(8) of this register) 672 ** in response to a detected address or attribute parity error. 673 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 674 ** VGA palette write transactions are I/O transactions 675 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 676 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 677 ** or are fully decoding 678 ** (i.e., must be all 0's depending upon the VGA 679 ** aliasing bit in the Bridge Control Register, offset 3Eh. 680 ** P_AD[31:16] equal to 0000h 681 ** 0=The bridge ignores VGA palette write transactions, 682 ** unless decoded by the standard I/O address range window. 683 ** 1=The bridge responds to VGA palette write transactions 684 ** with medium DEVSEL# timing and forwards them to the secondary bus. 685 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 686 ** MWI transactions targeting resources on the opposite side of the bridge, 687 ** however, are forwarded as MWI transactions. 688 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 689 ** This bit is read only and always returns 0 when read 690 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 691 ** Initiation of configuration transactions is not affected by the state of this bit. 692 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 693 ** 1=The bridge is enabled to function as an initiator on the primary interface. 694 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 695 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 696 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 697 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 698 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 699 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 700 **============================================================================== 701 */ 702 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 703 #define PCI_DISABLE_INTERRUPT 0x0400 704 /* 705 **============================================================================== 706 ** 0x07-0x06 : status register 707 ** Bit Default Description 708 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 709 ** attribute or data parity error. 710 ** This bit is set regardless of the state of the PER bit in the command register. 711 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 712 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 713 ** acting as the initiator on the primary bus, 714 ** its transaction (with the exception of special cycles) 715 ** has been terminated with a Master Abort. 716 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 717 ** acting as the initiator on the primary bus, 718 ** its transaction has been terminated with a Target Abort. 719 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 720 ** as the target of a transaction, terminates it with a Target Abort. 721 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 722 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 723 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing. 724 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 725 ** The bridge is the current master on the primary bus 726 ** S_PERR# is detected asserted or is asserted by bridge 727 ** The Parity Error Response bit is set in the Command register 728 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 729 ** is able to respond to fast back to back transactions on its primary interface. 730 ** 06 0 Reserved 731 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 732 ** 1 = 733 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 734 ** Offset 34h (Capability Pointer register) 735 ** provides the offset for the first entry 736 ** in the linked list of enhanced capabilities. 737 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 738 ** The bridge does not support interrupts. 739 ** 02:00 000 Reserved 740 **============================================================================== 741 */ 742 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 743 #define ARCMSR_ADAP_66MHZ 0x20 744 /* 745 **============================================================================== 746 ** 0x08 : revision ID 747 ** Bit Default Description 748 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 749 **============================================================================== 750 */ 751 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 752 /* 753 **============================================================================== 754 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 755 ** Bit Default Description 756 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 757 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 758 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 759 **============================================================================== 760 */ 761 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 762 /* 763 **============================================================================== 764 ** 0x0c : cache line size 765 ** Bit Default Description 766 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 767 ** The contents of this register are factored into 768 ** internal policy decisions associated with memory read prefetching, 769 ** and the promotion of Memory Write transactions to MWI transactions. 770 ** Valid cache line sizes are 8 and 16 dwords. 771 ** When the cache line size is set to an invalid value, 772 ** bridge behaves as though the cache line size was set to 00h. 773 **============================================================================== 774 */ 775 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 776 /* 777 **============================================================================== 778 ** 0x0d : latency timer (number of pci clock 00-ff ) 779 ** Bit Default Description 780 ** Primary Latency Timer (PTV): 781 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 782 ** referenced from the assertion of FRAME# to the expiration of the timer, 783 ** when bridge may continue as master of the current transaction. All bits are writable, 784 ** resulting in a granularity of 1 PCI clock cycle. 785 ** When the timer expires (i.e., equals 00h) 786 ** bridge relinquishes the bus after the first data transfer 787 ** when its PCI bus grant has been deasserted. 788 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 789 ** Indicates the number of PCI clock cycles, 790 ** referenced from the assertion of FRAME# to the expiration of the timer, 791 ** when bridge may continue as master of the current transaction. 792 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 793 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 794 ** (Except in the case where MLT expires within 3 data phases 795 ** of an ADB.In this case bridge continues on 796 ** until it reaches the next ADB before relinquishing the bus.) 797 **============================================================================== 798 */ 799 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 800 /* 801 **============================================================================== 802 ** 0x0e : (header type,single function ) 803 ** Bit Default Description 804 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 805 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 806 ** Returns ¡§01h¡¨ when read indicating 807 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 808 **============================================================================== 809 */ 810 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 811 /* 812 **============================================================================== 813 ** 0x0f : 814 **============================================================================== 815 */ 816 /* 817 **============================================================================== 818 ** 0x13-0x10 : 819 ** PCI CFG Base Address #0 (0x10) 820 **============================================================================== 821 */ 822 /* 823 **============================================================================== 824 ** 0x17-0x14 : 825 ** PCI CFG Base Address #1 (0x14) 826 **============================================================================== 827 */ 828 /* 829 **============================================================================== 830 ** 0x1b-0x18 : 831 ** PCI CFG Base Address #2 (0x18) 832 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 833 ** Bit Default Description 834 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 835 ** Any Type 1 configuration cycle 836 ** on the primary bus whose bus number is greater than the secondary bus number, 837 ** and less than or equal to the subordinate bus number 838 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 839 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 840 ** Any Type 1 configuration cycle matching this bus number 841 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 842 ** before being executed on bridge's secondary PCI bus. 843 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 844 ** Any Type 1 configuration cycle on the primary interface 845 ** with a bus number that is less than the contents 846 ** of this register field does not be claimed by bridge. 847 **-----------------0x1B--Secondary Latency Timer Register - SLTR 848 ** Bit Default Description 849 ** Secondary Latency Timer (STV): 850 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 851 ** Indicates the number of PCI clock cycles, 852 ** referenced from the assertion of FRAME# to the expiration of the timer, 853 ** when bridge may continue as master of the current transaction. All bits are writable, 854 ** resulting in a granularity of 1 PCI clock cycle. 855 ** When the timer expires (i.e., equals 00h) 856 ** bridge relinquishes the bus after the first data transfer 857 ** when its PCI bus grant has been deasserted. 858 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 859 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 860 ** to the expiration of the timer, 861 ** when bridge may continue as master of the current transaction. All bits are writable, 862 ** resulting in a granularity of 1 PCI clock cycle. 863 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 864 ** (Except in the case where MLT expires within 3 data phases of an ADB. 865 ** In this case bridge continues on until it reaches the next ADB 866 ** before relinquishing the bus) 867 **============================================================================== 868 */ 869 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 870 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 871 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 872 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 873 /* 874 **============================================================================== 875 ** 0x1f-0x1c : 876 ** PCI CFG Base Address #3 (0x1C) 877 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 878 ** Bit Default Description 879 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 880 ** determine when to forward I/O transactions from one interface to the other. 881 ** These bits correspond to address lines 15:12 for 4KB alignment. 882 ** Bits 11:0 are assumed to be FFFh. 883 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 884 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 885 ** an address range to determine when to forward I/O transactions 886 ** from one interface to the other. 887 ** These bits correspond to address lines 15:12 for 4KB alignment. 888 ** Bits 11:0 are assumed to be 000h. 889 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 890 **-----------------0x1F,0x1E--Secondary Status Register - SSR 891 ** Bit Default Description 892 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 893 ** attribute or data parity error on its secondary interface. 894 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 895 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 896 ** acting as the initiator on the secondary bus, 897 ** it's transaction (with the exception of special cycles) 898 ** has been terminated with a Master Abort. 899 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 900 ** acting as the initiator on the secondary bus, 901 ** it's transaction has been terminated with a Target Abort. 902 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 903 ** as the target of a transaction, terminates it with a Target Abort. 904 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 905 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 906 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing. 907 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 908 ** The bridge is the current master on the secondary bus 909 ** S_PERR# is detected asserted or is asserted by bridge 910 ** The Parity Error Response bit is set in the Command register 911 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 912 ** 06 0b Reserved 913 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 914 ** 1 = 915 ** 04:00 00h Reserved 916 **============================================================================== 917 */ 918 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 919 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 920 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 921 /* 922 **============================================================================== 923 ** 0x23-0x20 : 924 ** PCI CFG Base Address #4 (0x20) 925 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 926 ** Bit Default Description 927 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 928 ** the upper 1MB aligned value (exclusive) of the range. 929 ** The incoming address must be less than or equal to this value. 930 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 931 ** are assumed to be F FFFFh. 932 ** 19:16 0h Reserved. 933 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 934 ** of the incoming address to determine the lower 1MB 935 ** aligned value (inclusive) of the range. 936 ** The incoming address must be greater than or equal to this value. 937 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 938 ** are assumed to be 0 0000h. 939 ** 03:00 0h Reserved. 940 **============================================================================== 941 */ 942 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 943 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 944 /* 945 **============================================================================== 946 ** 0x27-0x24 : 947 ** PCI CFG Base Address #5 (0x24) 948 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 949 ** Bit Default Description 950 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 951 ** the upper 1MB aligned value (exclusive) of the range. 952 ** The incoming address must be less than or equal to this value. 953 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 954 ** are assumed to be F FFFFh. 955 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 956 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 957 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 958 ** of the range. 959 ** The incoming address must be greater than or equal to this value. 960 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 961 ** are assumed to be 0 0000h. 962 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 963 **============================================================================== 964 */ 965 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 966 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 967 /* 968 **============================================================================== 969 ** 0x2b-0x28 : 970 ** Bit Default Description 971 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 972 ** bridge supports full 64-bit addressing. 973 **============================================================================== 974 */ 975 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 976 /* 977 **============================================================================== 978 ** 0x2f-0x2c : 979 ** Bit Default Description 980 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 981 ** bridge supports full 64-bit addressing. 982 **============================================================================== 983 */ 984 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 985 /* 986 **============================================================================== 987 ** 0x33-0x30 : 988 ** Bit Default Description 989 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 990 ** space. (Power Management Capability Registers) 991 **============================================================================== 992 */ 993 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 994 /* 995 **============================================================================== 996 ** 0x3b-0x35 : reserved 997 **============================================================================== 998 */ 999 /* 1000 **============================================================================== 1001 ** 0x3d-0x3c : 1002 ** 1003 ** Bit Default Description 1004 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1005 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1006 **============================================================================== 1007 */ 1008 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1009 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1010 /* 1011 **============================================================================== 1012 ** 0x3f-0x3e : 1013 ** Bit Default Description 1014 ** 15:12 0h Reserved 1015 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1016 ** to a timer discard on either the primary or secondary interface. 1017 ** 0b=SERR# is not asserted. 1018 ** 1b=SERR# is asserted. 1019 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1020 ** The delayed completion is then discarded. 1021 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1022 ** that bridge waits for an initiator on the secondary bus 1023 ** to repeat a delayed transaction request. 1024 ** The counter starts when the delayed transaction completion is ready 1025 ** to be returned to the initiator. 1026 ** When the initiator has not repeated the transaction 1027 ** at least once before the counter expires,bridge 1028 ** discards the delayed transaction from its queues. 1029 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1030 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1031 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1032 ** that bridge waits for an initiator on the primary bus 1033 ** to repeat a delayed transaction request. 1034 ** The counter starts when the delayed transaction completion 1035 ** is ready to be returned to the initiator. 1036 ** When the initiator has not repeated the transaction 1037 ** at least once before the counter expires, 1038 ** bridge discards the delayed transaction from its queues. 1039 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1040 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1041 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1042 ** 06 0b Secondary Bus Reset (SBR): 1043 ** When cleared to 0b: The bridge deasserts S_RST#, 1044 ** when it had been asserted by writing this bit to a 1b. 1045 ** When set to 1b: The bridge asserts S_RST#. 1046 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1047 ** when a master abort termination occurs in response to 1048 ** a delayed transaction initiated by bridge on the target bus. 1049 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1050 ** and returns FFFF FFFFh when a read. 1051 ** 1b=When the transaction had not yet been completed on the initiator bus 1052 ** (e.g.,delayed reads, or non-posted writes), 1053 ** then bridge returns a Target Abort in response to the original requester 1054 ** when it returns looking for its delayed completion on the initiator bus. 1055 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1056 ** then bridge asserts P_SERR# (when enabled). 1057 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1058 ** while attempting to deliver a posted memory write on the destination bus. 1059 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1060 ** (also of this register), 1061 ** and the VGA Palette Snoop Enable bit (Command Register). 1062 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1063 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1064 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1065 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1066 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1067 ** then this bit has no impact on bridge behavior. 1068 ** 03 0b VGA Enable: Setting this bit enables address decoding 1069 ** and transaction forwarding of the following VGA transactions from the primary bus 1070 ** to the secondary bus: 1071 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1072 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h¡ 1073 ** ¨ and AD[15:10] are either not decoded (i.e., don't cares), 1074 ** or must be ¡§000000b¡¨ 1075 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1076 ** I/O and Memory Enable bits must be set in the Command register 1077 ** to enable forwarding of VGA cycles. 1078 ** 02 0b ISA Enable: Setting this bit enables special handling 1079 ** for the forwarding of ISA I/O transactions that fall within the address range 1080 ** specified by the I/O Base and Limit registers, 1081 ** and are within the lowest 64Kbyte of the I/O address map 1082 ** (i.e., 0000 0000h - 0000 FFFFh). 1083 ** 0b=All I/O transactions that fall within the I/O Base 1084 ** and Limit registers' specified range are forwarded 1085 ** from primary to secondary unfiltered. 1086 ** 1b=Blocks the forwarding from primary to secondary 1087 ** of the top 768 bytes of each 1Kbyte alias. 1088 ** On the secondary the top 768 bytes of each 1K alias 1089 ** are inversely decoded and forwarded 1090 ** from secondary to primary. 1091 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1092 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1093 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1094 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1095 ** that is detected on its secondary interface. 1096 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1097 ** Also bridge does not assert P_SERR# in response to a detected address 1098 ** or attribute parity error. 1099 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1100 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1101 ** of the Command register) 1102 ** in response to a detected address or attribute parity error. 1103 **============================================================================== 1104 */ 1105 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1106 /* 1107 ************************************************************************** 1108 ** Device Specific Registers 40-A7h 1109 ************************************************************************** 1110 ** ---------------------------------------------------------------------------------------------------------- 1111 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1112 ** ---------------------------------------------------------------------------------------------------------- 1113 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1114 ** ---------------------------------------------------------------------------------------------------------- 1115 ** | Bridge Control 2 | Bridge Control 1 | 44h 1116 ** ---------------------------------------------------------------------------------------------------------- 1117 ** | Reserved | Bridge Status | 48h 1118 ** ---------------------------------------------------------------------------------------------------------- 1119 ** | Reserved | 4Ch 1120 ** ---------------------------------------------------------------------------------------------------------- 1121 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1122 ** ---------------------------------------------------------------------------------------------------------- 1123 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1124 ** ---------------------------------------------------------------------------------------------------------- 1125 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1126 ** ---------------------------------------------------------------------------------------------------------- 1127 ** | Reserved | Secondary IDSEL | 5Ch 1128 ** ---------------------------------------------------------------------------------------------------------- 1129 ** | Reserved | 5Ch 1130 ** ---------------------------------------------------------------------------------------------------------- 1131 ** | Reserved | 68h:CBh 1132 ** ---------------------------------------------------------------------------------------------------------- 1133 ************************************************************************** 1134 **============================================================================== 1135 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1136 ** Bit Default Description 1137 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1138 ** (PCI=16 clocks,PCI-X=6 clocks). 1139 ** Note that this field is only meaningful when: 1140 ** # Bit[11] of this register is set to 1b, 1141 ** indicating that a Grant Time-out violation had occurred. 1142 ** # bridge internal arbiter is enabled. 1143 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1144 ** 0000b REQ#/GNT#[0] 1145 ** 0001b REQ#/GNT#[1] 1146 ** 0010b REQ#/GNT#[2] 1147 ** 0011b REQ#/GNT#[3] 1148 ** 1111b Default Value (no violation detected) 1149 ** When bit[11] is cleared by software, this field reverts back to its default value. 1150 ** All other values are Reserved 1151 ** 11 0b Grant Time-out Occurred: When set to 1b, 1152 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1153 ** Software clears this bit by writing a 1b to it. 1154 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1155 ** 1=During bus idle, bridge parks the bus on itself. 1156 ** The bus grant is removed from the last master and internally asserted to bridge. 1157 ** 09:08 00b Reserved 1158 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1159 ** Each bit of this field assigns its corresponding secondary 1160 ** bus master to either the high priority arbiter ring (1b) 1161 ** or to the low priority arbiter ring (0b). 1162 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1163 ** Bit [6] corresponds to the bridge internal secondary bus request 1164 ** while Bit [7] corresponds to the SATU secondary bus request. 1165 ** Bits [5:4] are unused. 1166 ** 0b=Indicates that the master belongs to the low priority group. 1167 ** 1b=Indicates that the master belongs to the high priority group 1168 **================================================================================= 1169 ** 0x43: Bridge Control Register 0 - BCR0 1170 ** Bit Default Description 1171 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1172 ** and the Posted Write data is limited to 4KB. 1173 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1174 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1175 ** 06:03 0H Reserved. 1176 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1177 ** to perform upstream prefetch operations for Memory 1178 ** Read requests received on its secondary interface. 1179 ** This bit also controls the bridge's ability to generate advanced read commands 1180 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1181 ** to a Conventional PCI bus. 1182 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1183 ** The use of Memory Read Line and Memory Read 1184 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1185 ** to an upstream bus operating in Conventional PCI mode. 1186 ** 1b=bridge treats upstream PCI Memory Read requests as though 1187 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 1188 ** Read Block commands as Memory Read 1189 ** when the primary bus is operating 1190 ** in Conventional PCI mode. 1191 ** NOTE: This bit does not affect bridge ability to perform read prefetching 1192 ** when the received command is Memory Read Line or Memory Read Multiple. 1193 **================================================================================= 1194 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1195 ** Bit Default Description 1196 ** 15:08 0000000b Reserved 1197 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands, 1198 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1199 ** The three options for handling these alias commands are to either pass it as is, 1200 ** re-map to the actual block memory read/write command encoding, or ignore 1201 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1202 ** Bit (7:6) Handling of command 1203 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1204 ** 0 1 Enqueue and forward the alias command code unaltered 1205 ** 1 0 Ignore the transaction, forcing Master Abort 1206 ** 1 1 Reserved 1207 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1208 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1209 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1210 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1211 ** (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode, 1212 ** and as the number of times being retried when operating in Conventional PCI mode) 1213 ** 0b=All 2 24 watchdog timers are enabled. 1214 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1215 ** the number of attempts bridge makes when initiating a PMW, 1216 ** transacting a Delayed Transaction, or how long it waits for 1217 ** a split completion corresponding to one of its requests. 1218 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1219 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1220 ** 0b=The Secondary bus arbiter times out an agent 1221 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1222 ** once the bus has gone idle. 1223 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1224 ** An infringing agent does not receive a subsequent GNT# 1225 ** until it de-asserts its REQ# for at least one clock cycle. 1226 ** 1b=GNT# time-out mechanism is disabled. 1227 ** 03 00b Reserved. 1228 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1229 ** The time out mechanism is used to ensure that initiators 1230 ** of delayed transactions return for their delayed completion data/status 1231 ** within a reasonable amount of time after it is available from bridge. 1232 ** 0b=The secondary master time-out counter is enabled 1233 ** and uses the value specified by the Secondary Discard Timer bit 1234 ** (see Bridge Control Register). 1235 ** 1b=The secondary master time-out counter is disabled. 1236 ** The bridge waits indefinitely for a secondary bus master 1237 ** to repeat a delayed transaction. 1238 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1239 ** The time out mechanism is used to ensure that initiators 1240 ** of delayed transactions return for their delayed completion data/status 1241 ** within a reasonable amount of time after it is available from bridge. 1242 ** 0b=The primary master time-out counter is enabled and uses the value specified 1243 ** by the Primary Discard Timer bit (see Bridge Control Register). 1244 ** 1b=The secondary master time-out counter is disabled. 1245 ** The bridge waits indefinitely for a secondary bus master 1246 ** to repeat a delayed transaction. 1247 ** 00 0b Reserved 1248 **================================================================================= 1249 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1250 ** Bit Default Description 1251 ** 15:07 0000b Reserved. 1252 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1253 ** This bit disables all of the secondary PCI clock outputs including 1254 ** the feedback clock S_CLKOUT. 1255 ** This means that the user is required to provide an S_CLKIN input source. 1256 ** 05:04 11 (66 MHz) Preserved. 1257 ** 01 (100 MHz) 1258 ** 00 (133 MHz) 1259 ** 03:00 Fh (100 MHz & 66 MHz) 1260 ** 7h (133 MHz) 1261 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1262 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1263 ** default to being enabled following the rising edge of P_RST#, depending on the 1264 ** frequency of the secondary bus clock: 1265 ** ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1266 ** all four S_CLKOs enabled by default. (SCLKO[3:0])¡P 1267 ** ¡E Designs with 133 MHz Secondary PCI clock power up 1268 ** with the lower order 3 S_CLKOs enabled by default. 1269 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1270 ** to downstream device clock inputs. 1271 **================================================================================= 1272 ** 0x49-0x48: Bridge Status Register - BSR 1273 ** Bit Default Description 1274 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1275 ** is conditionally asserted when the secondary discard timer expires. 1276 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1277 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1278 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1279 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1280 ** when bridge discards an upstream split read request 1281 ** after waiting in excess of 2 24 clocks for the corresponding 1282 ** Split Completion to arrive. 1283 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1284 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1285 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1286 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1287 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1288 ** Split Completion to arrive. 1289 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1290 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1291 ** by bridge, to retire a PMW upstream. 1292 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1293 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1294 ** by bridge, to retire a PMW upstream. 1295 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1296 ** is conditionally asserted when bridge discards an upstream PMW transaction 1297 ** after receiving 2 24 target retries from the primary bus target 1298 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1299 ** is conditionally asserted when a data parity error is detected by bridge 1300 ** while attempting to retire a PMW upstream 1301 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1302 ** is conditionally asserted when bridge detects an address parity error on 1303 ** the secondary bus. 1304 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1305 ** is conditionally asserted when the primary bus discard timer expires. 1306 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1307 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1308 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1309 ** from the secondary bus target. 1310 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1311 ** when bridge discards a downstream split read request 1312 ** after waiting in excess of 2 24 clocks for the corresponding 1313 ** Split Completion to arrive. 1314 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1315 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1316 ** when bridge discards a downstream delayed write transaction request 1317 ** after receiving 2 24 target retries from the secondary bus target. 1318 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1319 ** is conditionally asserted when bridge discards a downstream 1320 ** split write request after waiting in excess of 2 24 clocks 1321 ** for the corresponding Split Completion to arrive. 1322 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1323 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1324 ** by bridge, to retire a PMW downstream. 1325 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1326 ** when a Target Abort occurs as a result of an attempt, by bridge, 1327 ** to retire a PMW downstream. 1328 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1329 ** is conditionally asserted when bridge discards a downstream PMW transaction 1330 ** after receiving 2 24 target retries from the secondary bus target 1331 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1332 ** is conditionally asserted when a data parity error is detected by bridge 1333 ** while attempting to retire a PMW downstream. 1334 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1335 ** when bridge detects an address parity error on the primary bus. 1336 **================================================================================== 1337 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 1338 ** Bit Default Description 1339 ** 15:13 000b Reserved 1340 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 1341 ** that a secondary bus master has its grant maintained in order to enable 1342 ** multiple transactions to execute within the same arbitration cycle. 1343 ** Bit[02:00] GNT# Extended Duration 1344 ** 000 MTT Disabled (Default=no GNT# extension) 1345 ** 001 16 clocks 1346 ** 010 32 clocks 1347 ** 011 64 clocks 1348 ** 100 128 clocks 1349 ** 101 256 clocks 1350 ** 110 Invalid (treated as 000) 1351 ** 111 Invalid (treated as 000) 1352 ** 09:08 00b Reserved 1353 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 1354 ** pair supported by bridge secondary arbiter. 1355 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 1356 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 1357 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 1358 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 1359 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 1360 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 1361 **================================================================================== 1362 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 1363 ** Bit Default Description 1364 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 1365 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 1366 ** using the FirstRead parameter. 1367 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1368 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 1369 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 1370 ** the number of bytes to prefetch from the secondary bus interface 1371 ** on the initial PreFetch operation. 1372 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1373 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1374 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1375 ** in calculating the number of bytes to prefetch from the primary 1376 ** bus interface on subsequent PreFetch operations given 1377 ** that the read demands were not satisfied using 1378 ** the FirstRead parameter. 1379 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 1380 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 1381 ** Memory Read Multiple 6 cache lines 1382 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1383 ** in calculating the number of bytes to prefetch from 1384 ** the primary bus interface on the initial PreFetch operation. 1385 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 1386 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1387 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 1388 ** algorithm for the secondary and the primary bus interfaces. 1389 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 1390 ** enable bits for REQ#/GNT#[2:0]. 1391 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 1392 ** 1b: enables the staged pre-fetch feature 1393 ** 0b: disables staged pre-fetch, 1394 ** and hardwires read pre-fetch policy to the following for 1395 ** Memory Read, 1396 ** Memory Read Line, 1397 ** and Memory Read Multiple commands: 1398 ** Command Type Hardwired Pre-Fetch Amount... 1399 ** Memory Read 4 DWORDs 1400 ** Memory Read Line 1 cache line 1401 ** Memory Read Multiple 2 cache lines 1402 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 1403 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 1404 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 1405 **================================================================================== 1406 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 1407 ** Bit Default Description 1408 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 1409 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 1410 ** 0b=bridge asserts P_SERR#. 1411 ** 1b=bridge does not assert P_SERR# 1412 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1413 ** 0b=bridge asserts P_SERR#. 1414 ** 1b=bridge does not assert P_SERR# 1415 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1416 ** 0b=bridge asserts P_SERR#. 1417 ** 1b=bridge does not assert P_SERR# 1418 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 1419 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 1420 ** 0b=bridge asserts P_SERR#. 1421 ** 1b=bridge does not assert P_SERR# 1422 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 1423 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 1424 ** 0b=bridge asserts P_SERR#. 1425 ** 1b=bridge does not assert P_SERR# 1426 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 1427 ** it discards an upstream posted write transaction. 1428 ** 0b=bridge asserts P_SERR#. 1429 ** 1b=bridge does not assert P_SERR# 1430 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 1431 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 1432 ** 0b=bridge asserts P_SERR#. 1433 ** 1b=bridge does not assert P_SERR# 1434 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 1435 ** when it detects an address parity error on the secondary bus. 1436 ** 0b=bridge asserts P_SERR#. 1437 ** 1b=bridge does not assert P_SERR# 1438 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 1439 ** its discarding of a delayed transaction that was initiated on the secondary bus. 1440 ** 0b=bridge asserts P_SERR#. 1441 ** 1b=bridge does not assert P_SERR# 1442 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1443 ** 0b=bridge asserts P_SERR#. 1444 ** 1b=bridge does not assert P_SERR# 1445 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1446 ** 0b=bridge asserts P_SERR#. 1447 ** 1b=bridge does not assert P_SERR# 1448 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 1449 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 1450 ** 0b=bridge asserts P_SERR#. 1451 ** 1b=bridge does not assert P_SERR# 1452 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 1453 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 1454 ** 0b=bridge asserts P_SERR#. 1455 ** 1b=bridge does not assert P_SERR# 1456 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 1457 ** that it discards a downstream posted write transaction. 1458 ** 0b=bridge asserts P_SERR#. 1459 ** 1b=bridge does not assert P_SERR# 1460 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 1461 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 1462 ** 0b=bridge asserts P_SERR#. 1463 ** 1b=bridge does not assert P_SERR# 1464 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 1465 ** when it detects an address parity error on the primary bus. 1466 ** 0b=bridge asserts P_SERR#. 1467 ** 1b=bridge does not assert P_SERR# 1468 **=============================================================================== 1469 ** 0x56: Pre-Boot Status Register - PBSR 1470 ** Bit Default Description 1471 ** 07 1 Reserved 1472 ** 06 - Reserved - value indeterminate 1473 ** 05:02 0 Reserved 1474 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 1475 ** This bit reflect captured S_133EN strap, 1476 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 1477 ** Max Allowable Secondary Bus Frequency 1478 ** ** S_133EN PCI-X Mode 1479 ** ** 0 100 MHz 1480 ** ** 1 133 MH 1481 ** 00 0b Reserved 1482 **=============================================================================== 1483 ** 0x59-0x58: Secondary Decode Enable Register - SDER 1484 ** Bit Default Description 1485 ** 15:03 FFF1h Preserved. 1486 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 1487 ** bridge overrides its secondary inverse decode logic and not 1488 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 1489 ** This creates a private memory space on the Secondary PCI bus 1490 ** that allows peer-to-peer transactions. 1491 ** 01:00 10 2 Preserved. 1492 **=============================================================================== 1493 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 1494 ** Bit Default Description 1495 ** 15:10 000000 2 Reserved. 1496 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 1497 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 1498 ** When this bit is clear, 1499 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 1500 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 1501 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 1502 ** When this bit is clear, 1503 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 1504 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 1505 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 1506 ** When this bit is clear, 1507 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 1508 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 1509 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 1510 ** When this bit is clear, 1511 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 1512 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 1513 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 1514 ** When this bit is clear, 1515 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 1516 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 1517 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 1518 ** When this bit is clear, 1519 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 1520 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 1521 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 1522 ** When this bit is clear, 1523 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 1524 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 1525 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 1526 ** When this bit is clear, 1527 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 1528 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 1529 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 1530 ** When this bit is clear, 1531 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 1532 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 1533 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 1534 ** When this bit is clear, 1535 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 1536 ************************************************************************** 1537 */ 1538 /* 1539 ************************************************************************** 1540 ** Reserved A8-CBh 1541 ************************************************************************** 1542 */ 1543 /* 1544 ************************************************************************** 1545 ** PCI Extended Enhanced Capabilities List CC-FFh 1546 ************************************************************************** 1547 ** ---------------------------------------------------------------------------------------------------------- 1548 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1549 ** ---------------------------------------------------------------------------------------------------------- 1550 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 1551 ** ---------------------------------------------------------------------------------------------------------- 1552 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 1553 ** ---------------------------------------------------------------------------------------------------------- 1554 ** | Reserved | Reserved | Reserved | E4h 1555 ** ---------------------------------------------------------------------------------------------------------- 1556 ** | Reserved | E8h 1557 ** ---------------------------------------------------------------------------------------------------------- 1558 ** | Reserved | Reserved | Reserved | Reserved | ECh 1559 ** ---------------------------------------------------------------------------------------------------------- 1560 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 1561 ** ---------------------------------------------------------------------------------------------------------- 1562 ** | PCI-X Bridge Status | F4h 1563 ** ---------------------------------------------------------------------------------------------------------- 1564 ** | PCI-X Upstream Split Transaction Control | F8h 1565 ** ---------------------------------------------------------------------------------------------------------- 1566 ** | PCI-X Downstream Split Transaction Control | FCh 1567 ** ---------------------------------------------------------------------------------------------------------- 1568 **=============================================================================== 1569 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 1570 ** Bit Default Description 1571 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 1572 **=============================================================================== 1573 ** 0xDD: Next Item Pointer - PM_NXTP 1574 ** Bit Default Description 1575 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 1576 **=============================================================================== 1577 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 1578 ** Bit Default Description 1579 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 1580 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 1581 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 1582 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 1583 ** This returns 000b as PME# wake-up for bridge is not implemented. 1584 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 1585 ** 04:03 00 Reserved 1586 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 1587 **=============================================================================== 1588 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 1589 ** Bit Default Description 1590 ** 15:09 00h Reserved 1591 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 1592 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 1593 ** 07:02 00h Reserved 1594 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 1595 ** a function and to set the Function into a new power state. 1596 ** 00 - D0 state 1597 ** 01 - D1 state 1598 ** 10 - D2 state 1599 ** 11 - D3 hot state 1600 **=============================================================================== 1601 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 1602 ** Bit Default Description 1603 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 1604 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 1605 ** is to occur as a direct result of programming the function to D3 hot. 1606 ** This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨. 1607 ** 05:00 00h Reserved 1608 **=============================================================================== 1609 ** 0xE3: Power Management Data Register - PMDR 1610 ** Bit Default Description 1611 ** 07:00 00h Reserved 1612 **=============================================================================== 1613 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 1614 ** Bit Default Description 1615 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 1616 **=============================================================================== 1617 ** 0xF1: Next Item Pointer - PX_NXTP 1618 ** Bit Default Description 1619 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 1620 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 1621 **=============================================================================== 1622 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 1623 ** Bit Default Description 1624 ** 15:09 00h Reserved 1625 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 1626 ** The values are: 1627 ** ** BitsMax FrequencyClock Period 1628 ** ** 000PCI ModeN/A 1629 ** ** 00166 15 1630 ** ** 01010010 1631 ** ** 0111337.5 1632 ** ** 1xxreservedreserved 1633 ** ** The default value for this register is the operating frequency of the secondary bus 1634 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 1635 ** secondary bus to the primary bus because there is not enough room within the limit 1636 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 1637 ** Transaction Control register. The bridge does not set this bit. 1638 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 1639 ** The bridge does not set this bit. 1640 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 1641 ** equal to bridge secondary bus number, device number 00h, 1642 ** and function number 0 is received on the secondary interface. 1643 ** This bit is cleared by software writing a '1'. 1644 ** 02 0b Split Completion Discarded (SCD): This bit is set 1645 ** when bridge discards a split completion moving toward the secondary bus 1646 ** because the requester would not accept it. This bit cleared by software writing a '1'. 1647 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 1648 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 1649 **=============================================================================== 1650 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 1651 ** Bit Default Description 1652 ** 31:22 0 Reserved 1653 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 1654 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 1655 ** because bridge throttles traffic on the completion side. 1656 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 1657 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 1658 ** this bit by writing a 1b to it. 1659 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 1660 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 1661 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 1662 ** 0=The maximum operating frequency is 66 MHz. 1663 ** 1=The maximum operating frequency is 133 MHz. 1664 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 1665 ** 0=Primary Interface is connected as a 32-bit PCI bus. 1666 ** 1=Primary Interface is connected as a 64-bit PCI bus. 1667 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 1668 ** of the BNUM register at offset 18h. 1669 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 1670 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 1671 ** May be updated whenever a PCI-X 1672 ** configuration write cycle that targets bridge scores a hit. 1673 ** 02:00 0h Function Number (FNUM): The bridge Function # 1674 **=============================================================================== 1675 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 1676 ** Bit Default Description 1677 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 1678 ** Software is permitted to program this register to any value greater than or equal to 1679 ** the contents of the Split Transaction Capacity register. A value less than the contents 1680 ** of the Split Transaction Capacity register causes unspecified results. 1681 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 1682 ** size regardless of the amount of buffer space available. 1683 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 1684 ** split completions. This register controls behavior of the bridge buffers for forwarding 1685 ** Split Transactions from a primary bus requester to a secondary bus completer. 1686 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 1687 **=============================================================================== 1688 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 1689 ** Bit Default Description 1690 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 1691 ** Software is permitted to program this register to any value greater than or equal to 1692 ** the contents of the Split Transaction Capacity register. A value less than the contents 1693 ** of the Split Transaction Capacity register causes unspecified results. 1694 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 1695 ** size regardless of the amount of buffer space available. 1696 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 1697 ** split completions. This register controls behavior of the bridge buffers for forwarding 1698 ** Split Transactions from a primary bus requester to a secondary bus completer. 1699 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 1700 ** (7936 bytes). 1701 ************************************************************************** 1702 */ 1703 1704 1705 1706 1707 /* 1708 ************************************************************************************************************************************* 1709 ** 80331 Address Translation Unit Register Definitions 1710 ** ATU Interface Configuration Header Format 1711 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 1712 ************************************************************************************************************************************* 1713 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 1714 **=================================================================================================================================== 1715 ** | ATU Device ID | Vendor ID | 00h 1716 ** ---------------------------------------------------------------------------------------------------------- 1717 ** | Status | Command | 04H 1718 ** ---------------------------------------------------------------------------------------------------------- 1719 ** | ATU Class Code | Revision ID | 08H 1720 ** ---------------------------------------------------------------------------------------------------------- 1721 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 1722 ** ---------------------------------------------------------------------------------------------------------- 1723 ** | Inbound ATU Base Address 0 | 10H 1724 ** ---------------------------------------------------------------------------------------------------------- 1725 ** | Inbound ATU Upper Base Address 0 | 14H 1726 ** ---------------------------------------------------------------------------------------------------------- 1727 ** | Inbound ATU Base Address 1 | 18H 1728 ** ---------------------------------------------------------------------------------------------------------- 1729 ** | Inbound ATU Upper Base Address 1 | 1CH 1730 ** ---------------------------------------------------------------------------------------------------------- 1731 ** | Inbound ATU Base Address 2 | 20H 1732 ** ---------------------------------------------------------------------------------------------------------- 1733 ** | Inbound ATU Upper Base Address 2 | 24H 1734 ** ---------------------------------------------------------------------------------------------------------- 1735 ** | Reserved | 28H 1736 ** ---------------------------------------------------------------------------------------------------------- 1737 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 1738 ** ---------------------------------------------------------------------------------------------------------- 1739 ** | Expansion ROM Base Address | 30H 1740 ** ---------------------------------------------------------------------------------------------------------- 1741 ** | Reserved Capabilities Pointer | 34H 1742 ** ---------------------------------------------------------------------------------------------------------- 1743 ** | Reserved | 38H 1744 ** ---------------------------------------------------------------------------------------------------------- 1745 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 1746 ** ---------------------------------------------------------------------------------------------------------- 1747 ********************************************************************************************************************* 1748 */ 1749 /* 1750 *********************************************************************************** 1751 ** ATU Vendor ID Register - ATUVID 1752 ** ----------------------------------------------------------------- 1753 ** Bit Default Description 1754 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 1755 ** This register, combined with the DID, uniquely identify the PCI device. 1756 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 1757 ** to simulate the interface of a standard mechanism currently used by existing application software. 1758 *********************************************************************************** 1759 */ 1760 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 1761 /* 1762 *********************************************************************************** 1763 ** ATU Device ID Register - ATUDID 1764 ** ----------------------------------------------------------------- 1765 ** Bit Default Description 1766 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 1767 ** This ID, combined with the VID, uniquely identify any PCI device. 1768 *********************************************************************************** 1769 */ 1770 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 1771 /* 1772 *********************************************************************************** 1773 ** ATU Command Register - ATUCMD 1774 ** ----------------------------------------------------------------- 1775 ** Bit Default Description 1776 ** 15:11 000000 2 Reserved 1777 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 1778 ** 0=enables the assertion of interrupt signal. 1779 ** 1=disables the assertion of its interrupt signal. 1780 ** 09 0 2 Fast Back to Back Enable - When cleared, 1781 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 1782 ** Ignored when operating in the PCI-X mode. 1783 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 1784 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 1785 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 1786 ** of address stepping for PCI-X mode. 1787 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 1788 ** is detected. When cleared, parity checking is disabled. 1789 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 1790 ** does not perform VGA palette snooping. 1791 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 1792 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 1793 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 1794 ** Not implemented and a reserved bit field. 1795 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 1796 ** When cleared, disables the device from generating PCI accesses. 1797 ** When set, allows the device to behave as a PCI bus master. 1798 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 1799 ** of the state of this bit. 1800 ** 01 0 2 Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses. 1801 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 1802 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 1803 ** Not implemented and a reserved bit field. 1804 *********************************************************************************** 1805 */ 1806 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 1807 /* 1808 *********************************************************************************** 1809 ** ATU Status Register - ATUSR (Sheet 1 of 2) 1810 ** ----------------------------------------------------------------- 1811 ** Bit Default Description 1812 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 1813 ** when the ATUCMD register¡¦s Parity Error Response bit is cleared. Set under the following conditions: 1814 ** ¡E Write Data Parity Error when the ATU is a target (inbound write). 1815 ** ¡E Read Data Parity Error when the ATU is a requester (outbound read). 1816 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 1817 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 1818 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 1819 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 1820 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 1821 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 1822 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 1823 ** terminates the transaction on the PCI bus with a target abort. 1824 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 1825 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 1826 ** (except configuration accesses). 1827 ** 00 2=Fast 1828 ** 01 2=Medium 1829 ** 10 2=Slow 1830 ** 11 2=Reserved 1831 ** The ATU interface uses Medium timing. 1832 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 1833 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 1834 ** ¡E And the ATU acted as the requester 1835 ** for the operation in which the error occurred. 1836 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set 1837 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 1838 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set 1839 ** 07 1 2 (Conventional mode) 1840 ** 0 2 (PCI-X mode) 1841 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 1842 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 1843 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 1844 ** 06 0 2 UDF Supported - User Definable Features are not supported 1845 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 1846 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 1847 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 1848 ** when the Interrupt Disable bit in the command register is a 0. 1849 ** 0=ATU interrupt signal deasserted. 1850 ** 1=ATU interrupt signal asserted. 1851 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 1852 ** Section 3.10.23, ¡§ATU Interrupt Pin Register - ATUIPR¡¨ on page 236 for details on the ATU 1853 ** interrupt signal. 1854 ** 02:00 00000 2 Reserved. 1855 *********************************************************************************** 1856 */ 1857 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 1858 /* 1859 *********************************************************************************** 1860 ** ATU Revision ID Register - ATURID 1861 ** ----------------------------------------------------------------- 1862 ** Bit Default Description 1863 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 1864 *********************************************************************************** 1865 */ 1866 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 1867 /* 1868 *********************************************************************************** 1869 ** ATU Class Code Register - ATUCCR 1870 ** ----------------------------------------------------------------- 1871 ** Bit Default Description 1872 ** 23:16 05H Base Class - Memory Controller 1873 ** 15:08 80H Sub Class - Other Memory Controller 1874 ** 07:00 00H Programming Interface - None defined 1875 *********************************************************************************** 1876 */ 1877 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 1878 /* 1879 *********************************************************************************** 1880 ** ATU Cacheline Size Register - ATUCLSR 1881 ** ----------------------------------------------------------------- 1882 ** Bit Default Description 1883 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 1884 *********************************************************************************** 1885 */ 1886 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 1887 /* 1888 *********************************************************************************** 1889 ** ATU Latency Timer Register - ATULT 1890 ** ----------------------------------------------------------------- 1891 ** Bit Default Description 1892 ** 07:03 00000 2 (for Conventional mode) 1893 ** 01000 2 (for PCI-X mode) 1894 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 1895 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 1896 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 1897 *********************************************************************************** 1898 */ 1899 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 1900 /* 1901 *********************************************************************************** 1902 ** ATU Header Type Register - ATUHTR 1903 ** ----------------------------------------------------------------- 1904 ** Bit Default Description 1905 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 1906 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 1907 ** header conforms to PCI Local Bus Specification, Revision 2.3. 1908 *********************************************************************************** 1909 */ 1910 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 1911 /* 1912 *********************************************************************************** 1913 ** ATU BIST Register - ATUBISTR 1914 ** 1915 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 1916 ** initiated. This register is the interface between the host processor requesting BIST functions and 1917 ** the 80331 replying with the results from the software implementation of the BIST functionality. 1918 ** ----------------------------------------------------------------- 1919 ** Bit Default Description 1920 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 1921 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 1922 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 1923 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 1924 ** found in ATUBISTR register bits [3:0]. 1925 ** When the ATUCR BIST Interrupt Enable bit is clear: 1926 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 1927 ** The Intel XScale core does not clear this bit. 1928 ** 05:04 00 2 Reserved 1929 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 1930 ** The Intel XScale core places the results of the software BIST in these bits. 1931 ** A nonzero value indicates a device-specific error. 1932 *********************************************************************************** 1933 */ 1934 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 1935 1936 /* 1937 *************************************************************************************** 1938 ** ATU Base Registers and Associated Limit Registers 1939 *************************************************************************************** 1940 ** Base Address Register Limit Register Description 1941 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 1942 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 1943 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 1944 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 1945 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 1946 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 1947 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 1948 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 1949 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 1950 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 1951 **-------------------------------------------------------------------------------------- 1952 ** ATU Inbound Window 1 is not a translate window. 1953 ** The ATU does not claim any PCI accesses that fall within this range. 1954 ** This window is used to allocate host memory for use by Private Devices. 1955 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 1956 *********************************************************************************** 1957 */ 1958 1959 /* 1960 *********************************************************************************** 1961 ** Inbound ATU Base Address Register 0 - IABAR0 1962 ** 1963 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 1964 ** defines the block of memory addresses where the inbound translation window 0 begins. 1965 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 1966 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 1967 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 1968 ** depending on the value located within the IALR0. 1969 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 1970 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 1971 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 1972 ** Warning: 1973 ** When IALR0 is cleared prior to host configuration: 1974 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 1975 ** Assuming IALR0 is not cleared: 1976 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 1977 ** when the Prefetchable Indicator is cleared prior to host configuration, 1978 ** the user should also set the Type Indicator for 32 bit addressability. 1979 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 1980 ** when the Prefetchable Indicator is set prior to host configuration, the user 1981 ** should also set the Type Indicator for 64 bit addressability. 1982 ** This is the default for IABAR0. 1983 ** ----------------------------------------------------------------- 1984 ** Bit Default Description 1985 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 1986 ** the translation function is to respond to when addressed from the PCI bus. 1987 ** 11:04 00H Reserved. 1988 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 1989 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 1990 ** 00 - Memory Window is locatable anywhere in 32 bit address space 1991 ** 10 - Memory Window is locatable anywhere in 64 bit address space 1992 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 1993 ** The ATU does not occupy I/O space, 1994 ** thus this bit must be zero. 1995 *********************************************************************************** 1996 */ 1997 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 1998 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 1999 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2000 /* 2001 *********************************************************************************** 2002 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2003 ** 2004 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2005 ** Together with the Translation Base Address this register defines the actual location the translation 2006 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2007 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2008 ** Note: 2009 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2010 ** the IAUBAR0 register attributes are read-only. 2011 ** ----------------------------------------------------------------- 2012 ** Bit Default Description 2013 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2014 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2015 *********************************************************************************** 2016 */ 2017 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2018 /* 2019 *********************************************************************************** 2020 ** Inbound ATU Base Address Register 1 - IABAR1 2021 ** 2022 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2023 ** defines the block of memory addresses where the inbound translation window 1 begins. 2024 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2025 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2026 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2027 ** Warning: 2028 ** When a non-zero value is not written to IALR1 prior to host configuration, 2029 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2030 ** This is the default for IABAR1. 2031 ** Assuming a non-zero value is written to IALR1, 2032 ** the user may set the Prefetchable Indicator 2033 ** or the Type Indicator: 2034 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2035 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2036 ** the user should also leave the Type Indicator set for 32 bit addressability. 2037 ** This is the default for IABAR1. 2038 ** b. when the Prefetchable Indicator is set prior to host configuration, 2039 ** the user should also set the Type Indicator for 64 bit addressability. 2040 ** ----------------------------------------------------------------- 2041 ** Bit Default Description 2042 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2043 ** 11:04 00H Reserved. 2044 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2045 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2046 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2047 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2048 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2049 ** The ATU does not occupy I/O space, 2050 ** thus this bit must be zero. 2051 *********************************************************************************** 2052 */ 2053 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2054 /* 2055 *********************************************************************************** 2056 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2057 ** 2058 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2059 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2060 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2061 ** The programmed value within the base address register must comply with the PCI programming 2062 ** requirements for address alignment. 2063 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2064 ** from the PCI bus. 2065 ** Note: 2066 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2067 ** the IAUBAR1 register attributes are read-only. 2068 ** This is the default for IABAR1. 2069 ** ----------------------------------------------------------------- 2070 ** Bit Default Description 2071 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2072 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2073 *********************************************************************************** 2074 */ 2075 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2076 /* 2077 *********************************************************************************** 2078 ** Inbound ATU Base Address Register 2 - IABAR2 2079 ** 2080 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2081 ** defines the block of memory addresses where the inbound translation window 2 begins. 2082 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2083 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2084 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2085 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2086 ** Warning: 2087 ** When a non-zero value is not written to IALR2 prior to host configuration, 2088 ** the user should not set either the Prefetchable Indicator 2089 ** or the Type Indicator for 64 bit addressability. 2090 ** This is the default for IABAR2. 2091 ** Assuming a non-zero value is written to IALR2, 2092 ** the user may set the Prefetchable Indicator 2093 ** or the Type Indicator: 2094 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2095 ** when the Prefetchable Indicator is not set prior to host configuration, 2096 ** the user should also leave the Type Indicator set for 32 bit addressability. 2097 ** This is the default for IABAR2. 2098 ** b. when the Prefetchable Indicator is set prior to host configuration, 2099 ** the user should also set the Type Indicator for 64 bit addressability. 2100 ** ----------------------------------------------------------------- 2101 ** Bit Default Description 2102 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2103 ** the translation function is to respond to when addressed from the PCI bus. 2104 ** 11:04 00H Reserved. 2105 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2106 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2107 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2108 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2109 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2110 ** The ATU does not occupy I/O space, 2111 ** thus this bit must be zero. 2112 *********************************************************************************** 2113 */ 2114 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2115 /* 2116 *********************************************************************************** 2117 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2118 ** 2119 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2120 ** Together with the Translation Base Address this register defines the actual location 2121 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2122 ** The programmed value within the base address register must comply with the PCI programming 2123 ** requirements for address alignment. 2124 ** Note: 2125 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2126 ** the IAUBAR2 register attributes are read-only. 2127 ** This is the default for IABAR2. 2128 ** ----------------------------------------------------------------- 2129 ** Bit Default Description 2130 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2131 ** these bits define the actual location the translation function is to respond to 2132 ** when addressed from the PCI bus for addresses > 4GBytes. 2133 *********************************************************************************** 2134 */ 2135 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2136 /* 2137 *********************************************************************************** 2138 ** ATU Subsystem Vendor ID Register - ASVIR 2139 ** ----------------------------------------------------------------- 2140 ** Bit Default Description 2141 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2142 *********************************************************************************** 2143 */ 2144 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2145 /* 2146 *********************************************************************************** 2147 ** ATU Subsystem ID Register - ASIR 2148 ** ----------------------------------------------------------------- 2149 ** Bit Default Description 2150 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2151 *********************************************************************************** 2152 */ 2153 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2154 /* 2155 *********************************************************************************** 2156 ** Expansion ROM Base Address Register -ERBAR 2157 ** ----------------------------------------------------------------- 2158 ** Bit Default Description 2159 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2160 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2161 ** 11:01 000H Reserved 2162 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2163 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2164 *********************************************************************************** 2165 */ 2166 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2167 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2168 /* 2169 *********************************************************************************** 2170 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2171 ** ----------------------------------------------------------------- 2172 ** Bit Default Description 2173 ** 07:00 C0H Capability List Pointer - This provides an offset in this function¡¦s configuration space 2174 ** that points to the 80331 PCl Bus Power Management extended capability. 2175 *********************************************************************************** 2176 */ 2177 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2178 /* 2179 *********************************************************************************** 2180 ** Determining Block Sizes for Base Address Registers 2181 ** The required address size and type can be determined by writing ones to a base address register and 2182 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2183 ** address registers upwards, the programmer can determine the required address space size. The 2184 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2185 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2186 ** address register requires. 2187 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2188 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2189 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2190 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2191 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2192 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2193 ** associated limit registers to enable which bits within the base address register are read/write and 2194 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2195 ** other PCI devices even though the limit is variable. 2196 ** Table 105. Memory Block Size Read Response 2197 ** Response After Writing all 1s 2198 ** to the Base Address Register 2199 ** Size 2200 ** (Bytes) 2201 ** Response After Writing all 1s 2202 ** to the Base Address Register 2203 ** Size 2204 ** (Bytes) 2205 ** FFFFFFF0H 16 FFF00000H 1 M 2206 ** FFFFFFE0H 32 FFE00000H 2 M 2207 ** FFFFFFC0H 64 FFC00000H 4 M 2208 ** FFFFFF80H 128 FF800000H 8 M 2209 ** FFFFFF00H 256 FF000000H 16 M 2210 ** FFFFFE00H 512 FE000000H 32 M 2211 ** FFFFFC00H 1K FC000000H 64 M 2212 ** FFFFF800H 2K F8000000H 128 M 2213 ** FFFFF000H 4K F0000000H 256 M 2214 ** FFFFE000H 8K E0000000H 512 M 2215 ** FFFFC000H 16K C0000000H 1 G 2216 ** FFFF8000H 32K 80000000H 2 G 2217 ** FFFF0000H 64K 2218 ** 00000000H 2219 ** Register not 2220 ** imple-mented, 2221 ** no 2222 ** address 2223 ** space 2224 ** required. 2225 ** FFFE0000H 128K 2226 ** FFFC0000H 256K 2227 ** FFF80000H 512K 2228 ** 2229 *************************************************************************************** 2230 */ 2231 2232 2233 2234 /* 2235 *********************************************************************************** 2236 ** ATU Interrupt Line Register - ATUILR 2237 ** ----------------------------------------------------------------- 2238 ** Bit Default Description 2239 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt 2240 ** request line connects to the device's PCI interrupt request lines 2241 ** (as specified in the interrupt pin register). 2242 ** A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨. 2243 *********************************************************************************** 2244 */ 2245 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2246 /* 2247 *********************************************************************************** 2248 ** ATU Interrupt Pin Register - ATUIPR 2249 ** ----------------------------------------------------------------- 2250 ** Bit Default Description 2251 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2252 *********************************************************************************** 2253 */ 2254 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2255 /* 2256 *********************************************************************************** 2257 ** ATU Minimum Grant Register - ATUMGNT 2258 ** ----------------------------------------------------------------- 2259 ** Bit Default Description 2260 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2261 *********************************************************************************** 2262 */ 2263 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2264 /* 2265 *********************************************************************************** 2266 ** ATU Maximum Latency Register - ATUMLAT 2267 ** ----------------------------------------------------------------- 2268 ** Bit Default Description 2269 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2270 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2271 *********************************************************************************** 2272 */ 2273 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2274 /* 2275 *********************************************************************************** 2276 ** Inbound Address Translation 2277 ** 2278 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2279 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2280 ** The process of inbound address translation involves two steps: 2281 ** 1. Address Detection. 2282 ** ¡E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2283 ** within the address windows defined for the inbound ATU. 2284 ** ¡E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2285 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2286 ** 2. Address Translation. 2287 ** ¡E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2288 ** The ATU uses the following registers in inbound address window 0 translation: 2289 ** ¡E Inbound ATU Base Address Register 0 2290 ** ¡E Inbound ATU Limit Register 0 2291 ** ¡E Inbound ATU Translate Value Register 0 2292 ** The ATU uses the following registers in inbound address window 2 translation: 2293 ** ¡E Inbound ATU Base Address Register 2 2294 ** ¡E Inbound ATU Limit Register 2 2295 ** ¡E Inbound ATU Translate Value Register 2 2296 ** The ATU uses the following registers in inbound address window 3 translation: 2297 ** ¡E Inbound ATU Base Address Register 3 2298 ** ¡E Inbound ATU Limit Register 3 2299 ** ¡E Inbound ATU Translate Value Register 3 2300 ** Note: Inbound Address window 1 is not a translate window. 2301 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2302 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2303 ** thus the host BIOS does not configure window 3. 2304 ** Window 3 is intended to be used as a special window into local memory for private PCI 2305 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2306 ** PCI-to-PCI Bridge in 80331 or 2307 ** Inbound address detection is determined from the 32-bit PCI address, 2308 ** (64-bit PCI address during DACs) the base address register and the limit register. 2309 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2310 ** 2311 ** The algorithm for detection is: 2312 ** 2313 ** Equation 1. Inbound Address Detection 2314 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2315 ** the PCI Address is claimed by the Inbound ATU. 2316 ** 2317 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2318 ** with the associated inbound limit register. 2319 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2320 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2321 ** 2322 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2323 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2324 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2325 ** lower 32-bits are used during address translation. 2326 ** The algorithm is: 2327 ** 2328 ** 2329 ** Equation 2. Inbound Translation 2330 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2331 ** 2332 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2333 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2334 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 2335 ** read and write commands excluding inbound configuration read and writes. 2336 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 2337 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 2338 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 2339 ** example: 2340 ** Register Values 2341 ** Base_Register=3A00 0000H 2342 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 2343 ** Value_Register=B100 0000H 2344 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 2345 ** 2346 ** Address Detection (32-bit address) 2347 ** 2348 ** PCI_Address & Limit_Register == Base_Register 2349 ** 3A45 012CH & FF80 0000H == 3A00 0000H 2350 ** 2351 ** ANS: PCI_Address is in the Inbound Translation Window 2352 ** Address Translation (to get internal bus address) 2353 ** 2354 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 2355 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 2356 ** 2357 ** ANS:IB_Address=B145 012CH 2358 *********************************************************************************** 2359 */ 2360 2361 2362 2363 /* 2364 *********************************************************************************** 2365 ** Inbound ATU Limit Register 0 - IALR0 2366 ** 2367 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 2368 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2369 ** PCI addresses to internal bus addresses. 2370 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base 2371 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address 2372 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2373 ** Specification, Revision 2.3 for additional information on programming base address registers. 2374 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 2375 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 2376 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 2377 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 2378 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 2379 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 2380 ** ----------------------------------------------------------------- 2381 ** Bit Default Description 2382 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 2383 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 2384 ** 11:00 000H Reserved 2385 *********************************************************************************** 2386 */ 2387 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 2388 /* 2389 *********************************************************************************** 2390 ** Inbound ATU Translate Value Register 0 - IATVR0 2391 ** 2392 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 2393 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2394 ** inbound ATU address translation. 2395 ** ----------------------------------------------------------------- 2396 ** Bit Default Description 2397 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 2398 ** This value must be 64-bit aligned on the internal bus. 2399 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 2400 ** 11:00 000H Reserved 2401 *********************************************************************************** 2402 */ 2403 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 2404 /* 2405 *********************************************************************************** 2406 ** Expansion ROM Limit Register - ERLR 2407 ** 2408 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 2409 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 2410 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 2411 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 2412 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 2413 ** the corresponding bit within the ERBAR read/write from PCI. 2414 ** ----------------------------------------------------------------- 2415 ** Bit Default Description 2416 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 2417 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 2418 ** 11:00 000H Reserved. 2419 *********************************************************************************** 2420 */ 2421 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 2422 /* 2423 *********************************************************************************** 2424 ** Expansion ROM Translate Value Register - ERTVR 2425 ** 2426 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 2427 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 2428 ** Expansion ROM address translation. 2429 ** ----------------------------------------------------------------- 2430 ** Bit Default Description 2431 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 2432 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 2433 ** 11:00 000H Reserved 2434 *********************************************************************************** 2435 */ 2436 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 2437 /* 2438 *********************************************************************************** 2439 ** Inbound ATU Limit Register 1 - IALR1 2440 ** 2441 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 2442 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 2443 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 2444 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 2445 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 2446 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 2447 ** register. 2448 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 2449 ** not process any PCI bus transactions to this memory range. 2450 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 2451 ** IAUBAR1, and IALR1. 2452 ** ----------------------------------------------------------------- 2453 ** Bit Default Description 2454 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 2455 ** required for the ATUs memory window 1. 2456 ** 11:00 000H Reserved 2457 *********************************************************************************** 2458 */ 2459 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 2460 /* 2461 *********************************************************************************** 2462 ** Inbound ATU Limit Register 2 - IALR2 2463 ** 2464 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 2465 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2466 ** PCI addresses to internal bus addresses. 2467 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 2468 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit 2469 ** register provides the block size requirements for the base address register. The remaining registers 2470 ** used for performing address translation are discussed in Section 3.2.1.1. 2471 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base 2472 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address 2473 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2474 ** Specification, Revision 2.3 for additional information on programming base address registers. 2475 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 2476 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 2477 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 2478 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 2479 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 2480 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 2481 ** register. 2482 ** ----------------------------------------------------------------- 2483 ** Bit Default Description 2484 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 2485 ** required for the ATUs memory window 2. 2486 ** 11:00 000H Reserved 2487 *********************************************************************************** 2488 */ 2489 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 2490 /* 2491 *********************************************************************************** 2492 ** Inbound ATU Translate Value Register 2 - IATVR2 2493 ** 2494 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 2495 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2496 ** inbound ATU address translation. 2497 ** ----------------------------------------------------------------- 2498 ** Bit Default Description 2499 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 2500 ** This value must be 64-bit aligned on the internal bus. 2501 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 2502 ** 11:00 000H Reserved 2503 *********************************************************************************** 2504 */ 2505 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 2506 /* 2507 *********************************************************************************** 2508 ** Outbound I/O Window Translate Value Register - OIOWTVR 2509 ** 2510 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 2511 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 2512 ** result of the outbound ATU address translation. 2513 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 2514 ** length of 64 Kbytes. 2515 ** ----------------------------------------------------------------- 2516 ** Bit Default Description 2517 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 2518 ** 15:00 0000H Reserved 2519 *********************************************************************************** 2520 */ 2521 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 2522 /* 2523 *********************************************************************************** 2524 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 2525 ** 2526 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 2527 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2528 ** driven on the PCI bus as a result of the outbound ATU address translation. 2529 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 2530 ** of 64 Mbytes. 2531 ** ----------------------------------------------------------------- 2532 ** Bit Default Description 2533 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2534 ** 25:02 00 0000H Reserved 2535 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 2536 ** Only linear incrementing mode is supported. 2537 *********************************************************************************** 2538 */ 2539 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 2540 /* 2541 *********************************************************************************** 2542 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 2543 ** 2544 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 2545 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 2546 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 2547 ** a SAC is generated on the PCI bus. 2548 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 2549 ** length of 64 Mbytes. 2550 ** ----------------------------------------------------------------- 2551 ** Bit Default Description 2552 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2553 *********************************************************************************** 2554 */ 2555 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 2556 /* 2557 *********************************************************************************** 2558 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 2559 ** 2560 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 2561 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2562 ** driven on the PCI bus as a result of the outbound ATU address translation. 2563 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 2564 ** of 64 Mbytes. 2565 ** ----------------------------------------------------------------- 2566 ** Bit Default Description 2567 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2568 ** 25:02 00 0000H Reserved 2569 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 2570 ** Only linear incrementing mode is supported. 2571 *********************************************************************************** 2572 */ 2573 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 2574 /* 2575 *********************************************************************************** 2576 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 2577 ** 2578 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 2579 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 2580 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 2581 ** a SAC is generated on the PCI bus. 2582 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 2583 ** of 64 Mbytes. 2584 ** ----------------------------------------------------------------- 2585 ** Bit Default Description 2586 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2587 *********************************************************************************** 2588 */ 2589 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 2590 /* 2591 *********************************************************************************** 2592 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 2593 ** 2594 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 2595 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 2596 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 2597 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 2598 ** ----------------------------------------------------------------- 2599 ** Bit Default Description 2600 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2601 *********************************************************************************** 2602 */ 2603 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 2604 /* 2605 *********************************************************************************** 2606 ** ATU Configuration Register - ATUCR 2607 ** 2608 ** The ATU Configuration Register controls the outbound address translation for address translation 2609 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 2610 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 2611 ** interrupt enabling. 2612 ** ----------------------------------------------------------------- 2613 ** Bit Default Description 2614 ** 31:20 00H Reserved 2615 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 2616 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 2617 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 2618 ** applicable in the PCI-X mode. 2619 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 2620 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 2621 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 2622 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 2623 ** When clear, no translation occurs. 2624 ** 17 0 2 Reserved 2625 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 2626 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 2627 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 2628 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 2629 ** 14:10 00000 2 Reserved 2630 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 2631 ** when the ATU detects that SERR# was asserted. When clear, 2632 ** the Intel XScale core is not interrupted when SERR# is detected. 2633 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 2634 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 2635 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 2636 ** the ATUCR. 2637 ** 07:04 0000 2 Reserved 2638 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 2639 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 2640 ** in the ATUBISTR register. 2641 ** 02 0 2 Reserved 2642 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 2643 ** When cleared, disables the outbound ATU. 2644 ** 00 0 2 Reserved 2645 *********************************************************************************** 2646 */ 2647 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 2648 /* 2649 *********************************************************************************** 2650 ** PCI Configuration and Status Register - PCSR 2651 ** 2652 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 2653 ** various features of the PCI bus interface. 2654 ** ----------------------------------------------------------------- 2655 ** Bit Default Description 2656 ** 31:19 0000H Reserved 2657 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 2658 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 2659 ** Response bit is cleared. Set under the following conditions: 2660 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 2661 ** 17:16 Varies with 2662 ** external state 2663 ** of DEVSEL#, 2664 ** STOP#, and 2665 ** TRDY#, 2666 ** during 2667 ** P_RST# 2668 ** PCI-X capability - These two bits define the mode of 2669 ** the PCI bus (conventional or PCI-X) as well as the 2670 ** operating frequency in the case of PCI-X mode. 2671 ** 00 - Conventional PCI mode 2672 ** 01 - PCI-X 66 2673 ** 10 - PCI-X 100 2674 ** 11 - PCI-X 133 2675 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 2676 ** Revision 1.0a, the operating 2677 ** mode is determined by an initialization pattern on the PCI bus during 2678 ** P_RST# assertion: 2679 ** DEVSEL# STOP# TRDY# Mode 2680 ** Deasserted Deasserted Deasserted Conventional 2681 ** Deasserted Deasserted Asserted PCI-X 66 2682 ** Deasserted Asserted Deasserted PCI-X 100 2683 ** Deasserted Asserted Asserted PCI-X 133 2684 ** All other patterns are reserved. 2685 ** 15 0 2 2686 ** Outbound Transaction Queue Busy: 2687 ** 0=Outbound Transaction Queue Empty 2688 ** 1=Outbound Transaction Queue Busy 2689 ** 14 0 2 2690 ** Inbound Transaction Queue Busy: 2691 ** 0=Inbound Transaction Queue Empty 2692 ** 1=Inbound Transaction Queue Busy 2693 ** 13 0 2 Reserved. 2694 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 2695 ** for the four discard timers attached to the queues holding read data. 2696 ** A value of 0 indicates the time-out value is 2 15 clocks. 2697 ** A value of 1 indicates the time-out value is 2 10 clocks. 2698 ** 11 0 2 Reserved. 2699 ** 10 Varies with 2700 ** external state 2701 ** of M66EN 2702 ** during 2703 ** P_RST# 2704 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 2705 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 2706 ** When clear, the interface 2707 ** has been initialized as a 33 MHz bus. 2708 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 2709 ** 09 0 2 Reserved 2710 ** 08 Varies with 2711 ** external state 2712 ** of REQ64# 2713 ** during 2714 ** P_RST# 2715 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 2716 ** configured as 64-bit capable by 2717 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 2718 ** the PCI interface is configured as 2719 ** 32-bit only. 2720 ** 07:06 00 2 Reserved. 2721 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 2722 ** and all units on the internal 2723 ** bus. In addition to the internal bus initialization, 2724 ** this bit triggers the assertion of the M_RST# pin for 2725 ** initialization of registered DIMMs. When set: 2726 ** When operating in the conventional PCI mode: 2727 ** ¡E All current PCI transactions being mastered by the ATU completes, 2728 ** and the ATU master interfaces 2729 ** proceeds to an idle state. No additional transactions is mastered by these units 2730 ** until the internal bus reset is complete. 2731 ** ¡E All current transactions being slaved by the ATU on either the PCI bus 2732 ** or the internal bus 2733 ** completes, and the ATU target interfaces proceeds to an idle state. 2734 ** All future slave transactions master aborts, 2735 ** with the exception of the completion cycle for the transaction that set the Reset 2736 ** Internal Bus bit in the PCSR. 2737 ** ¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 2738 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 2739 ** ¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32 2740 ** Internal Bus clocks. 2741 ** ¡E The 80331 hardware clears this bit after the reset operation completes. 2742 ** When operating in the PCI-X mode: 2743 ** The ATU hardware responds the same as in Conventional PCI-X mode. 2744 ** However, this may create a problem in PCI-X mode for split requests in 2745 ** that there may still be an outstanding split completion that the 2746 ** ATU is either waiting to receive (Outbound Request) or initiate 2747 ** (Inbound Read Request). For a cleaner 2748 ** internal bus reset, host software can take the following steps prior 2749 ** to asserting Reset Internal bus: 2750 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 2751 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 2752 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 2753 ** queue busy bits to be clear. 2754 ** 3. Set the Reset Internal Bus bit 2755 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 2756 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 2757 ** completion transactions. 2758 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 2759 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 2760 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 2761 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 2762 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 2763 ** Bus Master Indicator signal P_BMI used 2764 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 2765 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 2766 ** 03 Varies with external state of PRIVDEV during 2767 ** P_RST# 2768 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 2769 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 2770 ** 0=Private Device control Disabled - SISR register bits default to zero 2771 ** 1=Private Device control Enabled - SISR register bits default to one 2772 ** 02 Varies with external state of RETRY during P_RST# 2773 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 2774 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 2775 ** configuration cycles. 2776 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 2777 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 2778 ** low, the bit is cleared. 2779 ** 01 Varies with external state of CORE_RST# during P_RST# 2780 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 2781 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 2782 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 2783 ** XScale core reset. 2784 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 2785 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 2786 ** high, the bit is clear. 2787 ** 00 Varies with external state of PRIVMEM during P_RST# 2788 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 2789 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 2790 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 2791 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 2792 *********************************************************************************** 2793 */ 2794 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 2795 /* 2796 *********************************************************************************** 2797 ** ATU Interrupt Status Register - ATUISR 2798 ** 2799 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 2800 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 2801 ** of the 80331. All bits in this register are Read/Clear. 2802 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 2803 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 2804 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 2805 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 2806 ** register. 2807 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 2808 ** ----------------------------------------------------------------- 2809 ** Bit Default Description 2810 ** 31:18 0000H Reserved 2811 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 2812 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 2813 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 2814 ** 16 0 2 Reserved 2815 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 2816 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 2817 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 2818 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 2819 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 2820 ** Configure Register Write Interrupt. 2821 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 2822 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 2823 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 2824 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 2825 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 2826 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 2827 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 2828 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 2829 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 2830 ** register¡¦s Parity Error Response bit is cleared. Set under the following conditions: 2831 ** ¡E Write Data Parity Error when the ATU is a target (inbound write). 2832 ** ¡E Read Data Parity Error when the ATU is an initiator (outbound read). 2833 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 2834 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 2835 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 2836 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 2837 ** register bits 3:0. 2838 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 2839 ** of the ATU Configure Register Write Interrupt. 2840 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 2841 ** 06:05 00 2 Reserved. 2842 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 2843 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 2844 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 2845 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 2846 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 2847 ** conditions: 2848 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2849 ** ¡E And the ATU acted as the requester for the operation in which the error occurred. 2850 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set 2851 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2852 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set 2853 *********************************************************************************** 2854 */ 2855 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 2856 /* 2857 *********************************************************************************** 2858 ** ATU Interrupt Mask Register - ATUIMR 2859 ** 2860 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 2861 ** generated by the ATU. 2862 ** ----------------------------------------------------------------- 2863 ** Bit Default Description 2864 ** 31:15 0 0000H Reserved 2865 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 2866 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 2867 ** 0=Not Masked 2868 ** 1=Masked 2869 ** 13 0 2 Reserved 2870 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 2871 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 2872 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 2873 ** 0=Not Masked 2874 ** 1=Masked 2875 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 2876 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 2877 ** IABAR1 register or the IAUBAR1 register. 2878 ** 0=Not Masked 2879 ** 1=Masked 2880 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 2881 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 2882 ** 0=Not Masked 2883 ** 1=Masked 2884 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 2885 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 2886 ** PCIXSR being set. 2887 ** 0=Not Masked 2888 ** 1=Masked 2889 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 2890 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 2891 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 2892 ** 0=Not Masked 2893 ** 1=Masked 2894 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 2895 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 2896 ** 0=Not Masked 2897 ** 1=Masked 2898 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 2899 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 2900 ** 0=Not Masked 2901 ** 1=Masked 2902 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 2903 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 2904 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 2905 ** 0=Not Masked 2906 ** 1=Masked 2907 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 2908 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 2909 ** 0=Not Masked 2910 ** 1=Masked 2911 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 2912 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 2913 ** 0=Not Masked 2914 ** 1=Masked 2915 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 2916 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 2917 ** 0=Not Masked 2918 ** 1=Masked 2919 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 2920 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 2921 ** inbound write transaction. 2922 ** 0=SERR# Not Asserted due to error 2923 ** 1=SERR# Asserted due to error 2924 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 2925 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 2926 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 2927 ** actually requested from the inbound read queue. 2928 ** 0=Disconnect with data 2929 ** (the data being up to 64 bits of 1¡¦s) 2930 ** 1=Target Abort 2931 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 2932 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 2933 ** independent of the setting of this bit. 2934 *********************************************************************************** 2935 */ 2936 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 2937 /* 2938 *********************************************************************************** 2939 ** Inbound ATU Base Address Register 3 - IABAR3 2940 ** 2941 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 2942 ** of memory addresses where the inbound translation window 3 begins. 2943 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2944 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 2945 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 2946 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2947 ** Note: 2948 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 2949 ** IABAR3 is not configured by the host during normal system initialization. 2950 ** Warning: 2951 ** When a non-zero value is not written to IALR3, 2952 ** the user should not set either the Prefetchable Indicator 2953 ** or the Type Indicator for 64 bit addressability. 2954 ** This is the default for IABAR3. 2955 ** Assuming a non-zero value is written to IALR3, 2956 ** the user may set the Prefetchable Indicator 2957 ** or the Type Indicator: 2958 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2959 ** when the Prefetchable Indicator is not set, 2960 ** the user should also leave the Type Indicator set for 32 bit addressability. 2961 ** This is the default for IABAR3. 2962 ** b. when the Prefetchable Indicator is set, 2963 ** the user should also set the Type Indicator for 64 bit addressability. 2964 ** ----------------------------------------------------------------- 2965 ** Bit Default Description 2966 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 2967 ** the translation function is to respond to when addressed from the PCI bus. 2968 ** 11:04 00H Reserved. 2969 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2970 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2971 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2972 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2973 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2974 ** The ATU does not occupy I/O space, 2975 ** thus this bit must be zero. 2976 *********************************************************************************** 2977 */ 2978 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 2979 /* 2980 *********************************************************************************** 2981 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 2982 ** 2983 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2984 ** Together with the Translation Base Address this register defines the actual location 2985 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2986 ** The programmed value within the base address register must comply with the PCI programming 2987 ** requirements for address alignment. 2988 ** Note: 2989 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 2990 ** the IAUBAR3 register attributes are read-only. 2991 ** This is the default for IABAR3. 2992 ** ----------------------------------------------------------------- 2993 ** Bit Default Description 2994 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 2995 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2996 *********************************************************************************** 2997 */ 2998 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 2999 /* 3000 *********************************************************************************** 3001 ** Inbound ATU Limit Register 3 - IALR3 3002 ** 3003 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3004 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3005 ** PCI addresses to internal bus addresses. 3006 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3007 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit 3008 ** register provides the block size requirements for the base address register. The remaining registers 3009 ** used for performing address translation are discussed in Section 3.2.1.1. 3010 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base 3011 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address 3012 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3013 ** Specification, Revision 2.3 for additional information on programming base address registers. 3014 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3015 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3016 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3017 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3018 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3019 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3020 ** register. 3021 ** ----------------------------------------------------------------- 3022 ** Bit Default Description 3023 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3024 ** for the ATUs memory window 3. 3025 ** 11:00 000H Reserved 3026 *********************************************************************************** 3027 */ 3028 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3029 /* 3030 *********************************************************************************** 3031 ** Inbound ATU Translate Value Register 3 - IATVR3 3032 ** 3033 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3034 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3035 ** inbound ATU address translation. 3036 ** ----------------------------------------------------------------- 3037 ** Bit Default Description 3038 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3039 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3040 ** access the internal 80331 memory-mapped registers. 3041 ** 11:00 000H Reserved 3042 *********************************************************************************** 3043 */ 3044 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3045 /* 3046 *********************************************************************************** 3047 ** Outbound Configuration Cycle Address Register - OCCAR 3048 ** 3049 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3050 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3051 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3052 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3053 ** PCI bus. 3054 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3055 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3056 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3057 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3058 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3059 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3060 ** ----------------------------------------------------------------- 3061 ** Bit Default Description 3062 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3063 ** configuration read or write cycle. 3064 *********************************************************************************** 3065 */ 3066 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3067 /* 3068 *********************************************************************************** 3069 ** Outbound Configuration Cycle Data Register - OCCDR 3070 ** 3071 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3072 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3073 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3074 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3075 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3076 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3077 ** actually entered into the data register (which does not physically exist). 3078 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3079 ** within the ATU configuration space. 3080 ** ----------------------------------------------------------------- 3081 ** Bit Default Description 3082 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3083 ** or write cycle. 3084 *********************************************************************************** 3085 */ 3086 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3087 /* 3088 *********************************************************************************** 3089 ** VPD Capability Identifier Register - VPD_CAPID 3090 ** 3091 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3092 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3093 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3094 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3095 ** ----------------------------------------------------------------- 3096 ** Bit Default Description 3097 ** 07:00 03H Cap_Id - This field with its¡¦ 03H value identifies this item in the linked list of Extended Capability 3098 ** Headers as being the VPD capability registers. 3099 *********************************************************************************** 3100 */ 3101 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3102 /* 3103 *********************************************************************************** 3104 ** VPD Next Item Pointer Register - VPD_NXTP 3105 ** 3106 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3107 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list. 3108 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3109 ** ----------------------------------------------------------------- 3110 ** Bit Default Description 3111 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the 3112 ** next item in the function¡¦s capability list. Since the VPD capabilities are the last in the linked list of 3113 ** extended capabilities in the 80331, the register is set to 00H. 3114 *********************************************************************************** 3115 */ 3116 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3117 /* 3118 *********************************************************************************** 3119 ** VPD Address Register - VPD_AR 3120 ** 3121 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3122 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3123 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3124 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3125 ** write of the VPD through the VPD Data Register. 3126 ** ----------------------------------------------------------------- 3127 ** Bit Default Description 3128 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3129 ** component has completed. Please see Section 3.9, ¡§Vital Product Data¡¨ on page 201 for more details on 3130 ** how the 80331 handles the data transfer. 3131 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3132 ** Vital Product Data from the VPD storage component. 3133 *********************************************************************************** 3134 */ 3135 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3136 /* 3137 *********************************************************************************** 3138 ** VPD Data Register - VPD_DR 3139 ** 3140 ** This register is used to transfer data between the 80331 and the VPD storage component. 3141 ** ----------------------------------------------------------------- 3142 ** Bit Default Description 3143 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3144 *********************************************************************************** 3145 */ 3146 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3147 /* 3148 *********************************************************************************** 3149 ** Power Management Capability Identifier Register -PM_CAPID 3150 ** 3151 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3152 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3153 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3154 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3155 ** Interface Specification, Revision 1.1. 3156 ** ----------------------------------------------------------------- 3157 ** Bit Default Description 3158 ** 07:00 01H Cap_Id - This field with its¡¦ 01H value identifies this item in the linked list of Extended Capability 3159 ** Headers as being the PCI Power Management Registers. 3160 *********************************************************************************** 3161 */ 3162 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3163 /* 3164 *********************************************************************************** 3165 ** Power Management Next Item Pointer Register - PM_NXTP 3166 ** 3167 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3168 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list. 3169 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3170 ** ----------------------------------------------------------------- 3171 ** Bit Default Description 3172 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the 3173 ** next item in the function¡¦s capability list which in the 80331 is the MSI extended capabilities header. 3174 *********************************************************************************** 3175 */ 3176 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3177 /* 3178 *********************************************************************************** 3179 ** Power Management Capabilities Register - PM_CAP 3180 ** 3181 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3182 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3183 ** information on the capabilities of the ATU function related to power management. 3184 ** ----------------------------------------------------------------- 3185 ** Bit Default Description 3186 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3187 ** is not supported by the 80331. 3188 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3189 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3190 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3191 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3192 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3193 ** following the transition to the D0 uninitialized state. 3194 ** 4 0 2 Reserved. 3195 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3196 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3197 ** Interface Specification, Revision 1.1 3198 *********************************************************************************** 3199 */ 3200 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3201 /* 3202 *********************************************************************************** 3203 ** Power Management Control/Status Register - PM_CSR 3204 ** 3205 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3206 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3207 ** interface for the power management extended capability. 3208 ** ----------------------------------------------------------------- 3209 ** Bit Default Description 3210 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3211 ** supported by the 80331. 3212 ** 14:9 00H Reserved 3213 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3214 ** generation from any power state. 3215 ** 7:2 000000 2 Reserved 3216 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3217 ** of a function and to set the function into a new power state. The definition of the values is: 3218 ** 00 2 - D0 3219 ** 01 2 - D1 3220 ** 10 2 - D2 (Unsupported) 3221 ** 11 2 - D3 hot 3222 ** The 80331 supports only the D0 and D3 hot states. 3223 ** 3224 *********************************************************************************** 3225 */ 3226 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3227 /* 3228 *********************************************************************************** 3229 ** PCI-X Capability Identifier Register - PX_CAPID 3230 ** 3231 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3232 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3233 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3234 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3235 ** ----------------------------------------------------------------- 3236 ** Bit Default Description 3237 ** 07:00 07H Cap_Id - This field with its¡¦ 07H value identifies this item in the linked list of Extended Capability 3238 ** Headers as being the PCI-X capability registers. 3239 *********************************************************************************** 3240 */ 3241 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3242 /* 3243 *********************************************************************************** 3244 ** PCI-X Next Item Pointer Register - PX_NXTP 3245 ** 3246 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3247 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list. 3248 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3249 ** to 00H. 3250 ** However, this register may be written to B8H prior to host configuration to include the VPD 3251 ** capability located at off-set B8H. 3252 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3253 ** produce unpredictable system behavior. 3254 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3255 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3256 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3257 ** this case (bit 1 of PCSR), as well. Please see Table 125, ¡§PCI Configuration and Status Register - 3258 ** PCSR¡¨ on page 253 for more details on the 80331 initialization modes. 3259 ** ----------------------------------------------------------------- 3260 ** Bit Default Description 3261 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the 3262 ** next item in the function¡¦s capability list. Since the PCI-X capabilities are the last in the linked list of 3263 ** extended capabilities in the 80331, the register is set to 00H. 3264 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3265 ** VPD extended capabilities header. 3266 *********************************************************************************** 3267 */ 3268 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3269 /* 3270 *********************************************************************************** 3271 ** PCI-X Command Register - PX_CMD 3272 ** 3273 ** This register controls various modes and features of ATU and Message Unit when operating in the 3274 ** PCI-X mode. 3275 ** ----------------------------------------------------------------- 3276 ** Bit Default Description 3277 ** 15:7 000000000 2 Reserved. 3278 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3279 ** the device is permitted to have outstanding at one time. 3280 ** Register Maximum Outstanding 3281 ** 0 1 3282 ** 1 2 3283 ** 2 3 3284 ** 3 4 3285 ** 4 8 3286 ** 5 12 3287 ** 6 16 3288 ** 7 32 3289 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3290 ** initiating a Sequence with one of the burst memory read commands. 3291 ** Register Maximum Byte Count 3292 ** 0 512 3293 ** 1 1024 3294 ** 2 2048 3295 ** 3 4096 3296 ** 1 0 2 3297 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3298 ** of Transactions. 3299 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3300 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3301 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3302 *********************************************************************************** 3303 */ 3304 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3305 /* 3306 *********************************************************************************** 3307 ** PCI-X Status Register - PX_SR 3308 ** 3309 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3310 ** Unit when operating in the PCI-X mode. 3311 ** ----------------------------------------------------------------- 3312 ** Bit Default Description 3313 ** 31:30 00 2 Reserved 3314 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3315 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3316 ** writes a 1 to this location. 3317 ** 0=no Split Completion error message received. 3318 ** 1=a Split Completion error message has been received. 3319 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3320 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3321 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3322 ** 1 16 512 (Default) 3323 ** 2 32 1024 3324 ** 2 32 2048 3325 ** 2 32 4096 3326 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3327 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3328 ** to 1024 bytes. 3329 ** 20 1 2 80331 is a complex device. 3330 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s 3331 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3332 ** 0=no unexpected Split Completion has been received. 3333 ** 1=an unexpected Split Completion has been received. 3334 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3335 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3336 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 3337 ** location. 3338 ** 0=no Split Completion has been discarded. 3339 ** 1=a Split Completion has been discarded. 3340 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 3341 ** Requests with Split Responses (Memory or Register) that has ¡§read side effects.¡¨ 3342 ** 17 1 2 80331 is a 133 MHz capable device. 3343 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 3344 ** therefore this bit is always set. 3345 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 3346 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 3347 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 3348 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 3349 ** 0=The bus is 32 bits wide. 3350 ** 1=The bus is 64 bits wide. 3351 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 3352 ** segment for the device containing this function. The function uses this number as part of its Requester 3353 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 3354 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 3355 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 3356 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 3357 ** the following are true: 3358 ** 1. The transaction uses a Configuration Write command. 3359 ** 2. IDSEL is asserted during the address phase. 3360 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3361 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3362 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 3363 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 3364 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 3365 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 3366 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 3367 ** time the function is addressed by a Configuration Write transaction, the device must update this register 3368 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 3369 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 3370 ** Write transaction when all of the following are true: 3371 ** 1. The transaction uses a Configuration Write command. 3372 ** 2. IDSEL is asserted during the address phase. 3373 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3374 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3375 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 3376 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 3377 ** configuration transaction to which this function responds. The function uses this number as part of its 3378 ** Requester ID and Completer ID. 3379 ** 3380 ************************************************************************** 3381 */ 3382 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 3383 3384 /* 3385 ************************************************************************** 3386 ** Inbound Read Transaction 3387 ** ======================================================================== 3388 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 3389 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 3390 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 3391 ** (IRQ). 3392 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 3393 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 3394 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 3395 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 3396 ** an inbound read transaction on the PCI bus is summarized in the following statements: 3397 ** ¡E The ATU claims the PCI read transaction when the PCI address is within the inbound 3398 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 3399 ** Address Register during DACs) and Inbound Limit Register. 3400 ** ¡E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 3401 ** information from a previous delayed read, the current transaction information is compared to 3402 ** the previous transaction information (based on the setting of the DRC Alias bit in 3403 ** Section 3.10.39, ¡§ATU Configuration Register - ATUCR¡¨ on page 252). When there is a 3404 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 3405 ** match and the data is not available, a Retry is signaled with no other action taken. When there 3406 ** is not a match and when the ITQ has less than eight entries, capture the transaction 3407 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 3408 ** when the ITQ is full, then signal a Retry with no other action taken. 3409 ** ¡X When an address parity error is detected, the address parity response defined in 3410 ** Section 3.7 is used. 3411 ** ¡E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 3412 ** the IRQ, it continues until one of the following is true: 3413 ** ¡X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 3414 ** data is flushed. 3415 ** ¡X An internal bus Target Abort was detected. In this case, the QWORD associated with the 3416 ** Target Abort is never entered into the IRQ, and therefore is never returned. 3417 ** ¡X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 3418 ** ¡X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 3419 ** the initiator on the last data word available. 3420 ** ¡E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 3421 ** command are latched into the available ITQ and a Split Response Termination is signalled to 3422 ** the initiator. 3423 ** ¡E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 3424 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 3425 ** before returning read data by generating the split completion transaction on the PCI-X bus. 3426 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 3427 ** transfer by returning data in 1024 byte aligned chunks. 3428 ** ¡E When operating in the PCI-X mode, once a split completion transaction has started, it 3429 ** continues until one of the following is true: 3430 ** ¡X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 3431 ** ADB (when the requester is a bridge) 3432 ** ¡X The byte count is satisfied. 3433 ** ¡X An internal bus Target Abort was detected. The ATU generates a Split Completion 3434 ** Message (message class=2h - completer error, and message index=81h - target abort) to 3435 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3436 ** Refer to Section 3.7.1. 3437 ** ¡X An internal bus Master Abort was detected. The ATU generates a Split Completion 3438 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 3439 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3440 ** Refer to Section 3.7.1 3441 ** ¡E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 3442 ** bus, the ATU PCI slave interface waits with no premature disconnects. 3443 ** ¡E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 3444 ** taken by the target interface. Refer to Section 3.7.2.5. 3445 ** ¡E When operating in the conventional PCI mode, when the read on the internal bus is 3446 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 3447 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 3448 ** target abort is used, when clear, a disconnect is used. 3449 ** ¡E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 3450 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 3451 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 3452 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 3453 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 3454 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 3455 ** transaction is flushed. Refer to Section 3.7.1. 3456 ** ¡E When operating in the conventional PCI mode, when the transaction on the internal bus 3457 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 3458 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 3459 ** ¡E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 3460 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 3461 ** error, and message index=80h - internal bus master abort) to inform the requester about the 3462 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 3463 ** ¡E When operating in the PCI-X mode, when the Split Completion transaction completes with 3464 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 3465 ** prevents it from accepting the completion it requested. In this case, since the Split Request 3466 ** addresses a location that has no read side effects, the completer must discard the Split 3467 ** Completion and take no further action. 3468 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 3469 ** statements: 3470 ** ¡E The ATU internal bus master interface requests the internal bus when a PCI address appears in 3471 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 3472 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 3473 ** always uses conventional PCI ordering rules. 3474 ** ¡E Once the internal bus is granted, the internal bus master interface drives the translated address 3475 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 3476 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 3477 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 3478 ** master has been delivered the target abort). 3479 ** ¡E Once the translated address is on the bus and the transaction has been accepted, the internal 3480 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 3481 ** received by the IRQ until one of the following is true: 3482 ** ¡X The full byte count requested by the ATU read request is received. The ATU internal bus 3483 ** initiator interface performs a initiator completion in this case. 3484 ** ¡X When operating in the conventional PCI mode, a Target Abort is received on the internal 3485 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 3486 ** informed. 3487 ** ¡X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 3488 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 3489 ** Completion Message (message class=2h - completer error, and message index=81h - 3490 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 3491 ** ITQ for this transaction is flushed. 3492 ** ¡X When operating in the conventional PCI mode, a single data phase disconnection is 3493 ** received from the internal bus target. When the data has not been received up to the next 3494 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 3495 ** When not, the bus returns to idle. 3496 ** ¡X When operating in the PCI-X mode, a single data phase disconnection is received from 3497 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 3498 ** obtain remaining data. 3499 ** ¡X When operating in the conventional PCI mode, a disconnection at Next ADB is received 3500 ** from the internal bus target. The bus returns to idle. 3501 ** ¡X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 3502 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 3503 ** remaining data. 3504 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 3505 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 3506 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 3507 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 3508 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 3509 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 3510 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 3511 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 3512 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 3513 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 3514 ** commands did not match, only the address. 3515 ************************************************************************** 3516 */ 3517 /* 3518 ************************************************************************** 3519 ** Inbound Write Transaction 3520 **======================================================================== 3521 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 3522 ** memory or a 80331 memory-mapped register. 3523 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 3524 ** ¡E The ATU claims the PCI write transaction when the PCI address is within the inbound 3525 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 3526 ** Base Address Register during DACs) and Inbound Limit Register. 3527 ** ¡E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 3528 ** available, the address is captured and the first data phase is accepted. 3529 ** ¡E The PCI interface continues to accept write data until one of the following is true: 3530 ** ¡X The initiator performs a disconnect. 3531 ** ¡X The transaction crosses a buffer boundary. 3532 ** ¡E When an address parity error is detected during the address phase of the transaction, the 3533 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 3534 ** parity error response. 3535 ** ¡E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 3536 ** parity error mechanism described in Section 3.7.1 is used. 3537 ** ¡E When a data parity error is detected while accepting data, the slave interface sets the 3538 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 3539 ** for details of the inbound write data parity error response. 3540 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 3541 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 3542 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 3543 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 3544 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 3545 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 3546 ** interface, when operating in the PCI mode. 3547 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 3548 ** configuration write transactions are processed as split transactions. The ATU generates a Split 3549 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 3550 ** 00h - Write Completion Message) once a configuration write is successfully executed. 3551 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 3552 ** The ATU handles such transactions as independent transactions. 3553 ** Data flow for the inbound write transaction on the internal bus is summarized as: 3554 ** ¡E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 3555 ** with associated data in the IWQ. 3556 ** ¡E When the internal bus is granted, the internal bus master interface initiates the write 3557 ** transaction by driving the translated address onto the internal bus. For details on inbound 3558 ** address translation. 3559 ** ¡E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 3560 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 3561 ** interface. 3562 ** ¡E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 3563 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 3564 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 3565 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 3566 ** internal bus ownership. 3567 ** ¡E The internal bus interface stops transferring data from the current transaction to the internal 3568 ** bus when one of the following conditions becomes true: 3569 ** ¡X The internal bus initiator interface loses bus ownership. The ATU internal initiator 3570 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 3571 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 3572 ** complete the delivery of remaining data using the same sequence ID but with the 3573 ** modified starting address and byte count. 3574 ** ¡X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 3575 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 3576 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 3577 ** complete the delivery of remaining data using the same sequence ID but with the 3578 ** modified starting address and byte count. 3579 ** ¡X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 3580 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 3581 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 3582 ** bus to complete the delivery of remaining data using the same sequence ID but with the 3583 ** modified starting address and byte count. 3584 ** ¡X The data from the current transaction has completed (satisfaction of byte count). An 3585 ** initiator termination is performed and the bus returns to idle. 3586 ** ¡X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 3587 ** Data is flushed from the IWQ. 3588 ***************************************************************** 3589 */ 3590 3591 3592 3593 /* 3594 ************************************************************************** 3595 ** Inbound Read Completions Data Parity Errors 3596 **======================================================================== 3597 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 3598 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 3599 ** completion transaction, the ATU attempts to complete the transaction normally and no further 3600 ** action is taken. 3601 ************************************************************************** 3602 */ 3603 3604 /* 3605 ************************************************************************** 3606 ** Inbound Configuration Write Completion Message Data Parity Errors 3607 **======================================================================== 3608 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 3609 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 3610 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 3611 ** normally and no further action is taken. 3612 ************************************************************************** 3613 */ 3614 3615 /* 3616 ************************************************************************** 3617 ** Inbound Read Request Data Parity Errors 3618 **===================== Immediate Data Transfer ========================== 3619 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 3620 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 3621 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 3622 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 3623 ** required and no error bits are set. 3624 **=====================Split Response Termination========================= 3625 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 3626 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 3627 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 3628 ** action is required and no error bits are set. 3629 ************************************************************************** 3630 */ 3631 3632 /* 3633 ************************************************************************** 3634 ** Inbound Write Request Data Parity Errors 3635 **======================================================================== 3636 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 3637 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 3638 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 3639 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 3640 ** the given constraints are taken by the ATU: 3641 ** ¡E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 3642 ** following the data phase in which the data parity error is detected on the bus. This is only 3643 ** done when the Parity Error Response bit in the ATUCMD is set. 3644 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3645 ** actions is taken: 3646 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3647 ** Detected Parity Error bit in the ATUISR. When set, no action. 3648 *************************************************************************** 3649 */ 3650 3651 3652 /* 3653 *************************************************************************** 3654 ** Inbound Configuration Write Request 3655 ** ===================================================================== 3656 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 3657 ** =============================================== 3658 ** Conventional PCI Mode 3659 ** =============================================== 3660 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 3661 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 3662 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 3663 ** parts of the transactions: 3664 ** ¡E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 3665 ** address/command and data for delayed delivery to the internal configuration register. 3666 ** ¡E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 3667 ** of the operation back to the original master. 3668 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 3669 ** inbound transactions during Delayed Write Request cycles with the given constraints: 3670 ** ¡E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 3671 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 3672 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 3673 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 3674 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 3675 ** forwarded to the internal bus. PERR# is not asserted. 3676 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3677 ** actions is taken: 3678 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3679 ** Detected Parity Error bit in the ATUISR. When set, no action. 3680 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 3681 ** bus and the ATU returns the status from the internal bus, completing the transaction. 3682 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 3683 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 3684 ** returned is normal completion) the ATU performs the following actions with the given constraints: 3685 ** ¡E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 3686 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 3687 ** the IDWQ remains since the data of retried command did not match the data within the queue. 3688 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3689 ** actions is taken: 3690 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3691 ** Detected Parity Error bit in the ATUISR. When set, no action. 3692 ** =================================================== 3693 ** PCI-X Mode 3694 ** =================================================== 3695 ** Data parity errors occurring during configuration write operations received by the ATU may cause 3696 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 3697 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 3698 ** Specifically, the following actions with the given constraints are then taken by the ATU: 3699 ** ¡E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 3700 ** cycles following the Split Response Termination in which the data parity error is detected on 3701 ** the bus. When the ATU asserts PERR#, additional actions is taken: 3702 ** ¡X A Split Write Data Parity Error message (with message class=2h - completer error and 3703 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 3704 ** that addresses the requester of the configuration write. 3705 ** ¡X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 3706 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 3707 ** action. 3708 ** ¡X The Split Write Request is not enqueued and forwarded to the internal bus. 3709 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3710 ** actions is taken: 3711 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3712 ** Detected Parity Error bit in the ATUISR. When set, no action. 3713 ** 3714 *************************************************************************** 3715 */ 3716 3717 /* 3718 *************************************************************************** 3719 ** Split Completion Messages 3720 ** ======================================================================= 3721 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 3722 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 3723 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 3724 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 3725 ** constraints are taken by the ATU: 3726 ** ¡E PERR# is asserted three clocks cycles following the data phase in which the data parity error 3727 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 3728 ** is set. When the ATU asserts PERR#, additional actions is taken: 3729 ** ¡X The Master Parity Error bit in the ATUSR is set. 3730 ** ¡X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 3731 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 3732 ** ¡X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 3733 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 3734 ** When the ATU asserts SERR#, additional actions is taken: 3735 ** Set the SERR# Asserted bit in the ATUSR. 3736 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 3737 ** SERR# Asserted bit in the ATUISR. When set, no action. 3738 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 3739 ** SERR# Detected bit in the ATUISR. When clear, no action. 3740 ** ¡E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 3741 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 3742 ** When the ATU sets this bit, additional actions is taken: 3743 ** ¡X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 3744 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 3745 ** When set, no action. 3746 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3747 ** actions is taken: 3748 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3749 ** Detected Parity Error bit in the ATUISR. When set, no action. 3750 ** ¡E The transaction associated with the Split Completion Message is discarded. 3751 ** ¡E When the discarded transaction was a read, a completion error message (with message 3752 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 3753 ** the internal bus of the 80331. 3754 ***************************************************************************** 3755 */ 3756 3757 3758 /* 3759 ****************************************************************************************************** 3760 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 3761 ** ================================================================================================== 3762 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 3763 ** notifies the respective system when new data arrives. 3764 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 3765 ** window defined by: 3766 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 3767 ** 2.Inbound ATU Limit Register 0 (IALR0) 3768 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 3769 ** Error conditions and status can be found in : 3770 ** 1.ATUSR 3771 ** 2.ATUISR 3772 **==================================================================================================== 3773 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 3774 **---------------------------------------------------------------------------------------------------- 3775 ** Message Registers 2 Inbound Optional Optional 3776 ** 2 Outbound 3777 **---------------------------------------------------------------------------------------------------- 3778 ** Doorbell Registers 1 Inbound Optional Optional 3779 ** 1 Outbound 3780 **---------------------------------------------------------------------------------------------------- 3781 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 3782 **---------------------------------------------------------------------------------------------------- 3783 ** Index Registers 1004 32-bit Memory Locations No Optional 3784 **==================================================================================================== 3785 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 3786 **==================================================================================================== 3787 ** 0000H Reserved 3788 ** 0004H Reserved 3789 ** 0008H Reserved 3790 ** 000CH Reserved 3791 **------------------------------------------------------------------------ 3792 ** 0010H Inbound Message Register 0 ] 3793 ** 0014H Inbound Message Register 1 ] 3794 ** 0018H Outbound Message Register 0 ] 3795 ** 001CH Outbound Message Register 1 ] 4 Message Registers 3796 **------------------------------------------------------------------------ 3797 ** 0020H Inbound Doorbell Register ] 3798 ** 0024H Inbound Interrupt Status Register ] 3799 ** 0028H Inbound Interrupt Mask Register ] 3800 ** 002CH Outbound Doorbell Register ] 3801 ** 0030H Outbound Interrupt Status Register ] 3802 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 3803 **------------------------------------------------------------------------ 3804 ** 0038H Reserved 3805 ** 003CH Reserved 3806 **------------------------------------------------------------------------ 3807 ** 0040H Inbound Queue Port ] 3808 ** 0044H Outbound Queue Port ] 2 Queue Ports 3809 **------------------------------------------------------------------------ 3810 ** 0048H Reserved 3811 ** 004CH Reserved 3812 **------------------------------------------------------------------------ 3813 ** 0050H ] 3814 ** : ] 3815 ** : Intel Xscale Microarchitecture Local Memory ] 3816 ** : ] 3817 ** 0FFCH ] 1004 Index Registers 3818 ******************************************************************************* 3819 */ 3820 struct MessageUnit 3821 { 3822 u_int32_t resrved0[4]; /*0000 000F*/ 3823 u_int32_t inbound_msgaddr0; /*0010 0013*/ 3824 u_int32_t inbound_msgaddr1; /*0014 0017*/ 3825 u_int32_t outbound_msgaddr0; /*0018 001B*/ 3826 u_int32_t outbound_msgaddr1; /*001C 001F*/ 3827 u_int32_t inbound_doorbell; /*0020 0023*/ 3828 u_int32_t inbound_intstatus; /*0024 0027*/ 3829 u_int32_t inbound_intmask; /*0028 002B*/ 3830 u_int32_t outbound_doorbell; /*002C 002F*/ 3831 u_int32_t outbound_intstatus; /*0030 0033*/ 3832 u_int32_t outbound_intmask; /*0034 0037*/ 3833 u_int32_t reserved1[2]; /*0038 003F*/ 3834 u_int32_t inbound_queueport; /*0040 0043*/ 3835 u_int32_t outbound_queueport; /*0044 0047*/ 3836 u_int32_t reserved2[2]; /*0048 004F*/ 3837 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 3838 u_int32_t reserved4[128]; /*0800 09FF 128*/ 3839 u_int32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 3840 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 3841 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 3842 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 3843 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 3844 }; 3845 /* 3846 ***************************************************************************** 3847 ** Theory of MU Operation 3848 ***************************************************************************** 3849 **-------------------- 3850 ** inbound_msgaddr0: 3851 ** inbound_msgaddr1: 3852 ** outbound_msgaddr0: 3853 ** outbound_msgaddr1: 3854 ** . The MU has four independent messaging mechanisms. 3855 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 3856 ** Each holds a 32-bit value and generates an interrupt when written. 3857 **-------------------- 3858 ** inbound_doorbell: 3859 ** outbound_doorbell: 3860 ** . The two Doorbell Registers support software interrupts. 3861 ** When a bit is set in a Doorbell Register, an interrupt is generated. 3862 **-------------------- 3863 ** inbound_queueport: 3864 ** outbound_queueport: 3865 ** 3866 ** 3867 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 3868 ** The 4 circular queues are implemented in 80331 local memory. 3869 ** Two queues are used for inbound messages and two are used for outbound messages. 3870 ** Interrupts may be generated when the queue is written. 3871 **-------------------- 3872 ** local_buffer 0x0050 ....0x0FFF 3873 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 3874 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 3875 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 3876 ** Each interrupt generated by the Messaging Unit can be masked. 3877 **-------------------- 3878 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 3879 ** with the exception of Multi-DWORD reads to the index registers. 3880 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 3881 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 3882 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 3883 ** and the data is returned through split completion transaction(s). 3884 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 3885 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 3886 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 3887 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 3888 **-------------------- 3889 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 3890 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 3891 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 3892 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 3893 **-------------------- 3894 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 3895 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 3896 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 3897 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 3898 **-------------------- 3899 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 3900 ** The register interface, message registers, doorbell registers, 3901 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 3902 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 3903 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 3904 ************************************************************************** 3905 */ 3906 /* 3907 ************************************************************************** 3908 ** Message Registers 3909 ** ============================== 3910 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 3911 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 3912 ** . Inbound messages are sent by the host processor and received by the 80331. 3913 ** Outbound messages are sent by the 80331 and received by the host processor. 3914 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 3915 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 3916 ** 3917 ** Inbound Messages: 3918 ** ----------------- 3919 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 3920 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 3921 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 3922 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 3923 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 3924 ** The interrupt is cleared when the Intel XScale core writes a value of 3925 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 3926 ** ------------------------------------------------------------------------ 3927 ** Inbound Message Register - IMRx 3928 ** 3929 ** . There are two Inbound Message Registers: IMR0 and IMR1. 3930 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 3931 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 3932 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 3933 ** ----------------------------------------------------------------- 3934 ** Bit Default Description 3935 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 3936 ** When written, an interrupt to the Intel XScale core may be generated. 3937 ************************************************************************** 3938 */ 3939 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 3940 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 3941 /* 3942 ************************************************************************** 3943 ** Outbound Message Register - OMRx 3944 ** -------------------------------- 3945 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 3946 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 3947 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 3948 ** Interrupt Mask Register. 3949 ** 3950 ** Bit Default Description 3951 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 3952 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 3953 ************************************************************************** 3954 */ 3955 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 3956 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 3957 /* 3958 ************************************************************************** 3959 ** Doorbell Registers 3960 ** ============================== 3961 ** There are two Doorbell Registers: 3962 ** Inbound Doorbell Register 3963 ** Outbound Doorbell Register 3964 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 3965 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 3966 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 3967 ** 3968 ** Inbound Doorbells: 3969 ** ------------------ 3970 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 3971 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 3972 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 3973 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 3974 ** The interrupt is recorded in the Inbound Interrupt Status Register. 3975 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 3976 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 3977 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 3978 ** and not the values written to the Inbound Doorbell Register. 3979 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 3980 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 3981 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 3982 ** ------------------------------------------------------------------------ 3983 ** Inbound Doorbell Register - IDR 3984 ** 3985 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 3986 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 3987 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 3988 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 3989 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 3990 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 3991 ** ------------------------------------------------------------------------ 3992 ** Bit Default Description 3993 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 3994 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 3995 ** When all bits are clear, do not generate a Normal Interrupt. 3996 ************************************************************************** 3997 */ 3998 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 3999 /* 4000 ************************************************************************** 4001 ** Inbound Interrupt Status Register - IISR 4002 ** 4003 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4004 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4005 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4006 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4007 ** these two are routed to the Messaging Unit Error interrupt input. 4008 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4009 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4010 ** Some of the bits in this register are Read Only. 4011 ** For those bits, the interrupt must be cleared through another register. 4012 ** 4013 ** Bit Default Description 4014 ** 31:07 0000000H 0 2 Reserved 4015 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4016 ** when an Index Register has been written after a PCI transaction. 4017 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4018 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4019 ** An Error interrupt is generated for this condition. 4020 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4021 ** Once cleared, an interrupt does NOT be generated 4022 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4023 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4024 ** software must retain the information that the Inbound Post queue status is not empty. 4025 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4026 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4027 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4028 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4029 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4030 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4031 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4032 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4033 ************************************************************************** 4034 */ 4035 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4036 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4037 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4038 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4039 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4040 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4041 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4042 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4043 /* 4044 ************************************************************************** 4045 ** Inbound Interrupt Mask Register - IIMR 4046 ** 4047 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4048 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4049 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4050 ** They only affect the generation of the Intel XScale core interrupt. 4051 ** ------------------------------------------------------------------------ 4052 ** Bit Default Description 4053 ** 31:07 000000H 0 2 Reserved 4054 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4055 ** when an Index Register has been written after a PCI transaction. 4056 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4057 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4058 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4059 ** by the MU hardware when the Inbound Post Queue has been written. 4060 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4061 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4062 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4063 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4064 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4065 ** Interrupt generated by a write to the Inbound Message 1 Register. 4066 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4067 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4068 ************************************************************************** 4069 */ 4070 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4071 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4072 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4073 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4074 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4075 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4076 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4077 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4078 /* 4079 ************************************************************************** 4080 ** Outbound Doorbell Register - ODR 4081 ** 4082 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4083 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4084 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4085 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4086 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4087 ** be cleared by an external PCI agent. 4088 ** ---------------------------------------------------------------------- 4089 ** Bit Default Description 4090 ** 31 0 2 Reserved 4091 ** 30 0 2 Reserved. 4092 ** 29 0 2 Reserved 4093 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4094 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4095 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4096 ** When this bit is cleared, the P_INTC# interrupt output 4097 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4098 ** signal is deasserted. 4099 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4100 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4101 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4102 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4103 ** signal is deasserted. 4104 ************************************************************************** 4105 */ 4106 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4107 /* 4108 ************************************************************************** 4109 ** Outbound Interrupt Status Register - OISR 4110 ** 4111 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4112 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4113 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4114 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4115 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4116 ** register. 4117 ** ---------------------------------------------------------------------- 4118 ** Bit Default Description 4119 ** 31:05 000000H 000 2 Reserved 4120 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4121 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4122 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4123 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4124 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4125 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4126 ** Doorbell Register must all be clear. 4127 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4128 ** written. Clearing this bit clears the interrupt. 4129 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4130 ** written. Clearing this bit clears the interrupt. 4131 ************************************************************************** 4132 */ 4133 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4134 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4135 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4136 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4137 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4138 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4139 /* 4140 ************************************************************************** 4141 ** Outbound Interrupt Mask Register - OIMR 4142 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4143 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4144 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4145 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4146 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4147 ** only affect the generation of the PCI interrupt. 4148 ** ---------------------------------------------------------------------- 4149 ** Bit Default Description 4150 ** 31:05 000000H Reserved 4151 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4152 ** in the Outbound Doorbell Register is set. 4153 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4154 ** the prefetch buffer is valid. 4155 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4156 ** Doorbell Register. 4157 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4158 ** generated by a write to the Outbound Message 1 Register. 4159 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4160 ** generated by a write to the Outbound Message 0 Register. 4161 ************************************************************************** 4162 */ 4163 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4164 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4165 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4166 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4167 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4168 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4169 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4170 /* 4171 ************************************************************************** 4172 ** 4173 ************************************************************************** 4174 */ 4175 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4176 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4177 /* 4178 ************************************************************************** 4179 ** Circular Queues 4180 ** ====================================================================== 4181 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4182 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4183 ** Inbound messages are either: 4184 ** ¡E posted messages by other processors for the Intel XScale core to process or 4185 ** ¡E free (or empty) messages that can be reused by other processors. 4186 ** Outbound messages are either: 4187 ** ¡E posted messages by the Intel XScale core for other processors to process or 4188 ** ¡E free (or empty) messages that can be reused by the Intel XScale core. 4189 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4190 ** The four Circular Queues are used to pass messages in the following manner. 4191 ** . The two inbound queues are used to handle inbound messages 4192 ** and the two outbound queues are used to handle outbound messages. 4193 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4194 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4195 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4196 ** 4197 ** ============================================================================================================= 4198 ** Circular Queue Summary 4199 ** _____________________________________________________________________________________________________________ 4200 ** | Queue Name | Purpose | Action on PCI Interface| 4201 ** |______________________|____________________________________________________________|_________________________| 4202 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4203 ** | | waiting to be processed by the 80331 | | 4204 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4205 ** | | available for use by other processors | | 4206 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4207 ** | | that are being posted to the other processors | | 4208 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4209 ** | | available for use by the 80331 | | 4210 ** |______________________|____________________________________________________________|_________________________| 4211 ** 4212 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4213 ** queue and to receive free messages returning from the 80331. 4214 ** The host processor posts inbound messages, 4215 ** the Intel XScale core receives the posted message and when it is finished with the message, 4216 ** places it back on the inbound free queue for reuse by the host processor. 4217 ** 4218 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4219 ** address space: 4220 ** Inbound Queue Port 4221 ** and Outbound Queue Port. 4222 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4223 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4224 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4225 ** does not cause the MU hardware to increment the queue pointers. 4226 ** This is treated as when the PCI transaction did not occur. 4227 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4228 ** ====================================================================================== 4229 ** Overview of Circular Queue Operation 4230 ** ====================================================================================== 4231 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4232 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4233 ** Each entry in the queue is a 32-bit data value. 4234 ** . Each read from or write to the queue may access only one queue entry. 4235 ** . Multi-DWORD accesses to the circular queues are not allowed. 4236 ** Sub-DWORD accesses are promoted to DWORD accesses. 4237 ** . Each circular queue has a head pointer and a tail pointer. 4238 ** The pointers are offsets from the Queue Base Address. 4239 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4240 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4241 ** Which unit maintains the pointer is determined by the writer of the queue. 4242 ** More details about the pointers are given in the queue descriptions below. 4243 ** The pointers are incremented after the queue access. 4244 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4245 ** 4246 ** Messaging Unit... 4247 ** 4248 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4249 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4250 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4251 ** . All four queues must be the same size and may be contiguous. 4252 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4253 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4254 ** . There is one base address for all four queues. 4255 ** It is stored in the Queue Base Address Register (QBAR). 4256 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4257 ** here shows an example of how the circular queues should be set up based on the 4258 ** Intelligent I/O (I 2 O) Architecture Specification. 4259 ** Other ordering of the circular queues is possible. 4260 ** 4261 ** Queue Starting Address 4262 ** Inbound Free Queue QBAR 4263 ** Inbound Post Queue QBAR + Queue Size 4264 ** Outbound Post Queue QBAR + 2 * Queue Size 4265 ** Outbound Free Queue QBAR + 3 * Queue Size 4266 ** =================================================================================== 4267 ** Inbound Post Queue 4268 ** ------------------ 4269 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4270 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4271 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4272 ** For a PCI write transaction that accesses the Inbound Queue Port, 4273 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4274 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4275 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4276 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4277 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4278 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4279 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4280 ** that the full condition is recognized by the core processor. 4281 ** In addition, to guarantee that the queue does not get overwritten, 4282 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4283 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4284 ** Only a new message posting the in the inbound queue generates a new interrupt. 4285 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4286 ** software must retain the information that the Inbound Post queue status. 4287 ** From the time that the PCI write transaction is received until the data is written 4288 ** in local memory and the Inbound Post Head Pointer Register is incremented, 4289 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4290 ** The Intel XScale core may read messages from the Inbound Post Queue 4291 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4292 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4293 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4294 ** the hardware retries any PCI writes until a slot in the queue becomes available. 4295 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4296 ** =================================================================================== 4297 ** Inbound Free Queue 4298 ** ------------------ 4299 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4300 ** This queue is read from the queue tail by external PCI agents. 4301 ** It is written to the queue head by the Intel XScale core. 4302 ** The tail pointer is maintained by the MU hardware. 4303 ** The head pointer is maintained by the Intel XScale core. 4304 ** For a PCI read transaction that accesses the Inbound Queue Port, 4305 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4306 ** When the queue is not empty (head and tail pointers are not equal) 4307 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4308 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4309 ** the value of -1 (FFFF.FFFFH) is returned. 4310 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4311 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4312 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4313 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4314 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4315 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4316 ** when the head and tail pointers are equal and the queue is empty. 4317 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4318 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4319 ** and the Inbound Free Head Pointer Register is written. 4320 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4321 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4322 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4323 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4324 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4325 ** The processor must then increment the Inbound Free Head Pointer Register. 4326 ** ================================================================================== 4327 ** Outbound Post Queue 4328 ** ------------------- 4329 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4330 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4331 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4332 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4333 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4334 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4335 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4336 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4337 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 4338 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4339 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4340 ** Register. 4341 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4342 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4343 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4344 ** occurs, the data is read directly from the prefetch register. 4345 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4346 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4347 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4348 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4349 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4350 ** Pointer Register when it adds messages to the queue. 4351 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4352 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4353 ** until the prefetch is completed. 4354 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4355 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4356 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4357 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4358 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4359 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4360 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4361 ** increment the Outbound Post Head Pointer Register. 4362 ** ================================================== 4363 ** Outbound Free Queue 4364 ** ----------------------- 4365 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 4366 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 4367 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 4368 ** XScale core. The head pointer is maintained by the MU hardware. 4369 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 4370 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 4371 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 4372 ** Head Pointer Register. 4373 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 4374 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 4375 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 4376 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 4377 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 4378 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 4379 ** core processor. 4380 ** From the time that a PCI write transaction is received until the data is written in local memory and 4381 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 4382 ** access the Outbound Free Queue Port is signalled a retry. 4383 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 4384 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 4385 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 4386 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 4387 ** 4388 ** ================================================================================== 4389 ** Circular Queue Summary 4390 ** ---------------------- 4391 ** ________________________________________________________________________________________________________________________________________________ 4392 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 4393 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4394 ** |Inbound Post | Inbound Queue | | | | | 4395 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 4396 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4397 ** |Inbound Free | Inbound Queue | | | | | 4398 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 4399 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4400 ** ================================================================================== 4401 ** Circular Queue Status Summary 4402 ** ---------------------- 4403 ** ____________________________________________________________________________________________________ 4404 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 4405 ** |_____________________|________________|_____________________|_______________________________________| 4406 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 4407 ** |_____________________|________________|_____________________|_______________________________________| 4408 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 4409 ** |_____________________|________________|_____________________|_______________________________________| 4410 ************************************************************************** 4411 */ 4412 4413 /* 4414 ************************************************************************** 4415 ** Index Registers 4416 ** ======================== 4417 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 4418 ** These registers are for inbound messages only. 4419 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4420 ** The storage for the Index Registers is allocated from the 80331 local memory. 4421 ** PCI write accesses to the Index Registers write the data to local memory. 4422 ** PCI read accesses to the Index Registers read the data from local memory. 4423 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 4424 ** to Inbound ATU Translate Value Register + FFFH. 4425 ** . The address of the first write access is stored in the Index Address Register. 4426 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 4427 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 4428 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 4429 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 4430 ** Writes by the Intel XScale core to the local memory used by the Index Registers 4431 ** does not cause an interrupt and does not update the Index Address Register. 4432 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 4433 ************************************************************************** 4434 */ 4435 /* 4436 ************************************************************************** 4437 ** Messaging Unit Internal Bus Memory Map 4438 ** ======================================= 4439 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 4440 ** FFFF E300H reserved | 4441 ** .. .. | 4442 ** FFFF E30CH reserved | 4443 ** FFFF E310H Inbound Message Register 0 | Available through 4444 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 4445 ** FFFF E318H Outbound Message Register 0 | 4446 ** FFFF E31CH Outbound Message Register 1 | or 4447 ** FFFF E320H Inbound Doorbell Register | 4448 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 4449 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 4450 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 4451 ** FFFF E330H Outbound Interrupt Status Register | 4452 ** FFFF E334H Outbound Interrupt Mask Register | 4453 ** ______________________________________________________________________|________________________________________ 4454 ** FFFF E338H reserved | 4455 ** FFFF E33CH reserved | 4456 ** FFFF E340H reserved | 4457 ** FFFF E344H reserved | 4458 ** FFFF E348H reserved | 4459 ** FFFF E34CH reserved | 4460 ** FFFF E350H MU Configuration Register | 4461 ** FFFF E354H Queue Base Address Register | 4462 ** FFFF E358H reserved | 4463 ** FFFF E35CH reserved | must translate PCI address to 4464 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 4465 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 4466 ** FFFF E368H Inbound Post Head pointer Register | 4467 ** FFFF E36CH Inbound Post Tail Pointer Register | 4468 ** FFFF E370H Outbound Free Head Pointer Register | 4469 ** FFFF E374H Outbound Free Tail Pointer Register | 4470 ** FFFF E378H Outbound Post Head pointer Register | 4471 ** FFFF E37CH Outbound Post Tail Pointer Register | 4472 ** FFFF E380H Index Address Register | 4473 ** FFFF E384H reserved | 4474 ** .. .. | 4475 ** FFFF E3FCH reserved | 4476 ** ______________________________________________________________________|_______________________________________ 4477 ************************************************************************** 4478 */ 4479 /* 4480 ************************************************************************** 4481 ** MU Configuration Register - MUCR FFFF.E350H 4482 ** 4483 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 4484 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 4485 ** The Circular Queues are disabled at reset to allow the software to initialize the head 4486 ** and tail pointer registers before any PCI accesses to the Queue Ports. 4487 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 4488 ** ------------------------------------------------------------------------ 4489 ** Bit Default Description 4490 ** 31:06 000000H 00 2 Reserved 4491 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 4492 ** All four queues are the same size. 4493 ** ¡E 00001 2 - 4K Entries (16 Kbytes) 4494 ** ¡E 00010 2 - 8K Entries (32 Kbytes) 4495 ** ¡E 00100 2 - 16K Entries (64 Kbytes) 4496 ** ¡E 01000 2 - 32K Entries (128 Kbytes) 4497 ** ¡E 10000 2 - 64K Entries (256 Kbytes) 4498 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 4499 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 4500 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 4501 ** disabled. When set, the Circular Queues are fully enabled. 4502 ************************************************************************** 4503 */ 4504 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 4505 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 4506 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 4507 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 4508 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 4509 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 4510 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 4511 /* 4512 ************************************************************************** 4513 ** Queue Base Address Register - QBAR 4514 ** 4515 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 4516 ** The base address is required to be located on a 1 Mbyte address boundary. 4517 ** . All Circular Queue head and tail pointers are based on the QBAR. 4518 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 4519 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 4520 ** Warning: 4521 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 4522 ** ------------------------------------------------------------------------ 4523 ** Bit Default Description 4524 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4525 ** 19:00 00000H Reserved 4526 ************************************************************************** 4527 */ 4528 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 4529 /* 4530 ************************************************************************** 4531 ** Inbound Free Head Pointer Register - IFHPR 4532 ** 4533 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 4534 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 4535 ** The Head Pointer must be aligned on a DWORD address boundary. 4536 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 4537 ** Writes to the upper 12 bits of the register are ignored. 4538 ** This register is maintained by software. 4539 ** ------------------------------------------------------------------------ 4540 ** Bit Default Description 4541 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4542 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 4543 ** 01:00 00 2 Reserved 4544 ************************************************************************** 4545 */ 4546 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 4547 /* 4548 ************************************************************************** 4549 ** Inbound Free Tail Pointer Register - IFTPR 4550 ** 4551 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 4552 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 4553 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4554 ** of the register. Writes to the upper 12 bits of the register are ignored. 4555 ** ------------------------------------------------------------------------ 4556 ** Bit Default Description 4557 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4558 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 4559 ** 01:00 00 2 Reserved 4560 ************************************************************************** 4561 */ 4562 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 4563 /* 4564 ************************************************************************** 4565 ** Inbound Post Head Pointer Register - IPHPR 4566 ** 4567 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 4568 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 4569 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4570 ** of the register. Writes to the upper 12 bits of the register are ignored. 4571 ** ------------------------------------------------------------------------ 4572 ** Bit Default Description 4573 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4574 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 4575 ** 01:00 00 2 Reserved 4576 ************************************************************************** 4577 */ 4578 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 4579 /* 4580 ************************************************************************** 4581 ** Inbound Post Tail Pointer Register - IPTPR 4582 ** 4583 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 4584 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 4585 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4586 ** of the register. Writes to the upper 12 bits of the register are ignored. 4587 ** ------------------------------------------------------------------------ 4588 ** Bit Default Description 4589 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4590 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 4591 ** 01:00 00 2 Reserved 4592 ************************************************************************** 4593 */ 4594 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 4595 /* 4596 ************************************************************************** 4597 ** Index Address Register - IAR 4598 ** 4599 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 4600 ** It is written by the MU when the Index Registers are written by a PCI agent. 4601 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 4602 ** . The local memory address of the Index Register least recently accessed is computed 4603 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 4604 ** ------------------------------------------------------------------------ 4605 ** Bit Default Description 4606 ** 31:12 000000H Reserved 4607 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 4608 ** 01:00 00 2 Reserved 4609 ************************************************************************** 4610 */ 4611 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 4612 /* 4613 ********************************************************************************************************** 4614 ** RS-232 Interface for Areca Raid Controller 4615 ** The low level command interface is exclusive with VT100 terminal 4616 ** -------------------------------------------------------------------- 4617 ** 1. Sequence of command execution 4618 ** -------------------------------------------------------------------- 4619 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 4620 ** (B) Command block : variable length of data including length, command code, data and checksum byte 4621 ** (C) Return data : variable length of data 4622 ** -------------------------------------------------------------------- 4623 ** 2. Command block 4624 ** -------------------------------------------------------------------- 4625 ** (A) 1st byte : command block length (low byte) 4626 ** (B) 2nd byte : command block length (high byte) 4627 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 4628 ** (C) 3rd byte : command code 4629 ** (D) 4th and following bytes : variable length data bytes depends on command code 4630 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 4631 ** -------------------------------------------------------------------- 4632 ** 3. Command code and associated data 4633 ** -------------------------------------------------------------------- 4634 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 4635 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 4636 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 4637 ** enum 4638 ** { 4639 ** GUI_SET_SERIAL=0x10, 4640 ** GUI_SET_VENDOR, 4641 ** GUI_SET_MODEL, 4642 ** GUI_IDENTIFY, 4643 ** GUI_CHECK_PASSWORD, 4644 ** GUI_LOGOUT, 4645 ** GUI_HTTP, 4646 ** GUI_SET_ETHERNET_ADDR, 4647 ** GUI_SET_LOGO, 4648 ** GUI_POLL_EVENT, 4649 ** GUI_GET_EVENT, 4650 ** GUI_GET_HW_MONITOR, 4651 ** 4652 ** // GUI_QUICK_CREATE=0x20, (function removed) 4653 ** GUI_GET_INFO_R=0x20, 4654 ** GUI_GET_INFO_V, 4655 ** GUI_GET_INFO_P, 4656 ** GUI_GET_INFO_S, 4657 ** GUI_CLEAR_EVENT, 4658 ** 4659 ** GUI_MUTE_BEEPER=0x30, 4660 ** GUI_BEEPER_SETTING, 4661 ** GUI_SET_PASSWORD, 4662 ** GUI_HOST_INTERFACE_MODE, 4663 ** GUI_REBUILD_PRIORITY, 4664 ** GUI_MAX_ATA_MODE, 4665 ** GUI_RESET_CONTROLLER, 4666 ** GUI_COM_PORT_SETTING, 4667 ** GUI_NO_OPERATION, 4668 ** GUI_DHCP_IP, 4669 ** 4670 ** GUI_CREATE_PASS_THROUGH=0x40, 4671 ** GUI_MODIFY_PASS_THROUGH, 4672 ** GUI_DELETE_PASS_THROUGH, 4673 ** GUI_IDENTIFY_DEVICE, 4674 ** 4675 ** GUI_CREATE_RAIDSET=0x50, 4676 ** GUI_DELETE_RAIDSET, 4677 ** GUI_EXPAND_RAIDSET, 4678 ** GUI_ACTIVATE_RAIDSET, 4679 ** GUI_CREATE_HOT_SPARE, 4680 ** GUI_DELETE_HOT_SPARE, 4681 ** 4682 ** GUI_CREATE_VOLUME=0x60, 4683 ** GUI_MODIFY_VOLUME, 4684 ** GUI_DELETE_VOLUME, 4685 ** GUI_START_CHECK_VOLUME, 4686 ** GUI_STOP_CHECK_VOLUME 4687 ** }; 4688 ** 4689 ** Command description : 4690 ** 4691 ** GUI_SET_SERIAL : Set the controller serial# 4692 ** byte 0,1 : length 4693 ** byte 2 : command code 0x10 4694 ** byte 3 : password length (should be 0x0f) 4695 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 4696 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 4697 ** GUI_SET_VENDOR : Set vendor string for the controller 4698 ** byte 0,1 : length 4699 ** byte 2 : command code 0x11 4700 ** byte 3 : password length (should be 0x08) 4701 ** byte 4-0x13 : should be "ArEcAvAr" 4702 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 4703 ** GUI_SET_MODEL : Set the model name of the controller 4704 ** byte 0,1 : length 4705 ** byte 2 : command code 0x12 4706 ** byte 3 : password length (should be 0x08) 4707 ** byte 4-0x13 : should be "ArEcAvAr" 4708 ** byte 0x14--0x1B : model string (must be 8 bytes) 4709 ** GUI_IDENTIFY : Identify device 4710 ** byte 0,1 : length 4711 ** byte 2 : command code 0x13 4712 ** return "Areca RAID Subsystem " 4713 ** GUI_CHECK_PASSWORD : Verify password 4714 ** byte 0,1 : length 4715 ** byte 2 : command code 0x14 4716 ** byte 3 : password length 4717 ** byte 4-0x?? : user password to be checked 4718 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 4719 ** byte 0,1 : length 4720 ** byte 2 : command code 0x15 4721 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 4722 ** 4723 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 4724 ** byte 0,1 : length 4725 ** byte 2 : command code 0x17 4726 ** byte 3 : password length (should be 0x08) 4727 ** byte 4-0x13 : should be "ArEcAvAr" 4728 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 4729 ** GUI_SET_LOGO : Set logo in HTTP 4730 ** byte 0,1 : length 4731 ** byte 2 : command code 0x18 4732 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 4733 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 4734 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 4735 ** note .... page0 1st 2 byte must be actual length of the JPG file 4736 ** GUI_POLL_EVENT : Poll If Event Log Changed 4737 ** byte 0,1 : length 4738 ** byte 2 : command code 0x19 4739 ** GUI_GET_EVENT : Read Event 4740 ** byte 0,1 : length 4741 ** byte 2 : command code 0x1a 4742 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 4743 ** GUI_GET_HW_MONITOR : Get HW monitor data 4744 ** byte 0,1 : length 4745 ** byte 2 : command code 0x1b 4746 ** byte 3 : # of FANs(example 2) 4747 ** byte 4 : # of Voltage sensor(example 3) 4748 ** byte 5 : # of temperature sensor(example 2) 4749 ** byte 6 : # of power 4750 ** byte 7/8 : Fan#0 (RPM) 4751 ** byte 9/10 : Fan#1 4752 ** byte 11/12 : Voltage#0 original value in *1000 4753 ** byte 13/14 : Voltage#0 value 4754 ** byte 15/16 : Voltage#1 org 4755 ** byte 17/18 : Voltage#1 4756 ** byte 19/20 : Voltage#2 org 4757 ** byte 21/22 : Voltage#2 4758 ** byte 23 : Temp#0 4759 ** byte 24 : Temp#1 4760 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 4761 ** byte 26 : UPS indicator 4762 ** GUI_QUICK_CREATE : Quick create raid/volume set 4763 ** byte 0,1 : length 4764 ** byte 2 : command code 0x20 4765 ** byte 3/4/5/6 : raw capacity 4766 ** byte 7 : raid level 4767 ** byte 8 : stripe size 4768 ** byte 9 : spare 4769 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 4770 ** This function is removed, application like to implement quick create function 4771 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 4772 ** GUI_GET_INFO_R : Get Raid Set Information 4773 ** byte 0,1 : length 4774 ** byte 2 : command code 0x20 4775 ** byte 3 : raidset# 4776 ** 4777 ** typedef struct sGUI_RAIDSET 4778 ** { 4779 ** BYTE grsRaidSetName[16]; 4780 ** DWORD grsCapacity; 4781 ** DWORD grsCapacityX; 4782 ** DWORD grsFailMask; 4783 ** BYTE grsDevArray[32]; 4784 ** BYTE grsMemberDevices; 4785 ** BYTE grsNewMemberDevices; 4786 ** BYTE grsRaidState; 4787 ** BYTE grsVolumes; 4788 ** BYTE grsVolumeList[16]; 4789 ** BYTE grsRes1; 4790 ** BYTE grsRes2; 4791 ** BYTE grsRes3; 4792 ** BYTE grsFreeSegments; 4793 ** DWORD grsRawStripes[8]; 4794 ** DWORD grsRes4; 4795 ** DWORD grsRes5; // Total to 128 bytes 4796 ** DWORD grsRes6; // Total to 128 bytes 4797 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 4798 ** GUI_GET_INFO_V : Get Volume Set Information 4799 ** byte 0,1 : length 4800 ** byte 2 : command code 0x21 4801 ** byte 3 : volumeset# 4802 ** 4803 ** typedef struct sGUI_VOLUMESET 4804 ** { 4805 ** BYTE gvsVolumeName[16]; // 16 4806 ** DWORD gvsCapacity; 4807 ** DWORD gvsCapacityX; 4808 ** DWORD gvsFailMask; 4809 ** DWORD gvsStripeSize; 4810 ** DWORD gvsNewFailMask; 4811 ** DWORD gvsNewStripeSize; 4812 ** DWORD gvsVolumeStatus; 4813 ** DWORD gvsProgress; // 32 4814 ** sSCSI_ATTR gvsScsi; 4815 ** BYTE gvsMemberDisks; 4816 ** BYTE gvsRaidLevel; // 8 4817 ** 4818 ** BYTE gvsNewMemberDisks; 4819 ** BYTE gvsNewRaidLevel; 4820 ** BYTE gvsRaidSetNumber; 4821 ** BYTE gvsRes0; // 4 4822 ** BYTE gvsRes1[4]; // 64 bytes 4823 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 4824 ** 4825 ** GUI_GET_INFO_P : Get Physical Drive Information 4826 ** byte 0,1 : length 4827 ** byte 2 : command code 0x22 4828 ** byte 3 : drive # (from 0 to max-channels - 1) 4829 ** 4830 ** typedef struct sGUI_PHY_DRV 4831 ** { 4832 ** BYTE gpdModelName[40]; 4833 ** BYTE gpdSerialNumber[20]; 4834 ** BYTE gpdFirmRev[8]; 4835 ** DWORD gpdCapacity; 4836 ** DWORD gpdCapacityX; // Reserved for expansion 4837 ** BYTE gpdDeviceState; 4838 ** BYTE gpdPioMode; 4839 ** BYTE gpdCurrentUdmaMode; 4840 ** BYTE gpdUdmaMode; 4841 ** BYTE gpdDriveSelect; 4842 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 4843 ** sSCSI_ATTR gpdScsi; 4844 ** BYTE gpdReserved[40]; // Total to 128 bytes 4845 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 4846 ** 4847 ** GUI_GET_INFO_S : Get System Information 4848 ** byte 0,1 : length 4849 ** byte 2 : command code 0x23 4850 ** 4851 ** typedef struct sCOM_ATTR 4852 ** { 4853 ** BYTE comBaudRate; 4854 ** BYTE comDataBits; 4855 ** BYTE comStopBits; 4856 ** BYTE comParity; 4857 ** BYTE comFlowControl; 4858 ** } sCOM_ATTR, *pCOM_ATTR; 4859 ** 4860 ** typedef struct sSYSTEM_INFO 4861 ** { 4862 ** BYTE gsiVendorName[40]; 4863 ** BYTE gsiSerialNumber[16]; 4864 ** BYTE gsiFirmVersion[16]; 4865 ** BYTE gsiBootVersion[16]; 4866 ** BYTE gsiMbVersion[16]; 4867 ** BYTE gsiModelName[8]; 4868 ** BYTE gsiLocalIp[4]; 4869 ** BYTE gsiCurrentIp[4]; 4870 ** DWORD gsiTimeTick; 4871 ** DWORD gsiCpuSpeed; 4872 ** DWORD gsiICache; 4873 ** DWORD gsiDCache; 4874 ** DWORD gsiScache; 4875 ** DWORD gsiMemorySize; 4876 ** DWORD gsiMemorySpeed; 4877 ** DWORD gsiEvents; 4878 ** BYTE gsiMacAddress[6]; 4879 ** BYTE gsiDhcp; 4880 ** BYTE gsiBeeper; 4881 ** BYTE gsiChannelUsage; 4882 ** BYTE gsiMaxAtaMode; 4883 ** BYTE gsiSdramEcc; // 1:if ECC enabled 4884 ** BYTE gsiRebuildPriority; 4885 ** sCOM_ATTR gsiComA; // 5 bytes 4886 ** sCOM_ATTR gsiComB; // 5 bytes 4887 ** BYTE gsiIdeChannels; 4888 ** BYTE gsiScsiHostChannels; 4889 ** BYTE gsiIdeHostChannels; 4890 ** BYTE gsiMaxVolumeSet; 4891 ** BYTE gsiMaxRaidSet; 4892 ** BYTE gsiEtherPort; // 1:if ether net port supported 4893 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 4894 ** BYTE gsiRes[75]; 4895 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 4896 ** 4897 ** GUI_CLEAR_EVENT : Clear System Event 4898 ** byte 0,1 : length 4899 ** byte 2 : command code 0x24 4900 ** 4901 ** GUI_MUTE_BEEPER : Mute current beeper 4902 ** byte 0,1 : length 4903 ** byte 2 : command code 0x30 4904 ** 4905 ** GUI_BEEPER_SETTING : Disable beeper 4906 ** byte 0,1 : length 4907 ** byte 2 : command code 0x31 4908 ** byte 3 : 0->disable, 1->enable 4909 ** 4910 ** GUI_SET_PASSWORD : Change password 4911 ** byte 0,1 : length 4912 ** byte 2 : command code 0x32 4913 ** byte 3 : pass word length ( must <= 15 ) 4914 ** byte 4 : password (must be alpha-numerical) 4915 ** 4916 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 4917 ** byte 0,1 : length 4918 ** byte 2 : command code 0x33 4919 ** byte 3 : 0->Independent, 1->cluster 4920 ** 4921 ** GUI_REBUILD_PRIORITY : Set rebuild priority 4922 ** byte 0,1 : length 4923 ** byte 2 : command code 0x34 4924 ** byte 3 : 0/1/2/3 (low->high) 4925 ** 4926 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 4927 ** byte 0,1 : length 4928 ** byte 2 : command code 0x35 4929 ** byte 3 : 0/1/2/3 (133/100/66/33) 4930 ** 4931 ** GUI_RESET_CONTROLLER : Reset Controller 4932 ** byte 0,1 : length 4933 ** byte 2 : command code 0x36 4934 ** *Response with VT100 screen (discard it) 4935 ** 4936 ** GUI_COM_PORT_SETTING : COM port setting 4937 ** byte 0,1 : length 4938 ** byte 2 : command code 0x37 4939 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 4940 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 4941 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 4942 ** byte 6 : stop bit (0:1, 1:2 stop bits) 4943 ** byte 7 : parity (0:none, 1:off, 2:even) 4944 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 4945 ** 4946 ** GUI_NO_OPERATION : No operation 4947 ** byte 0,1 : length 4948 ** byte 2 : command code 0x38 4949 ** 4950 ** GUI_DHCP_IP : Set DHCP option and local IP address 4951 ** byte 0,1 : length 4952 ** byte 2 : command code 0x39 4953 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 4954 ** byte 4/5/6/7 : IP address 4955 ** 4956 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 4957 ** byte 0,1 : length 4958 ** byte 2 : command code 0x40 4959 ** byte 3 : device # 4960 ** byte 4 : scsi channel (0/1) 4961 ** byte 5 : scsi id (0-->15) 4962 ** byte 6 : scsi lun (0-->7) 4963 ** byte 7 : tagged queue (1 : enabled) 4964 ** byte 8 : cache mode (1 : enabled) 4965 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 4966 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 4967 ** 4968 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 4969 ** byte 0,1 : length 4970 ** byte 2 : command code 0x41 4971 ** byte 3 : device # 4972 ** byte 4 : scsi channel (0/1) 4973 ** byte 5 : scsi id (0-->15) 4974 ** byte 6 : scsi lun (0-->7) 4975 ** byte 7 : tagged queue (1 : enabled) 4976 ** byte 8 : cache mode (1 : enabled) 4977 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 4978 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 4979 ** 4980 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 4981 ** byte 0,1 : length 4982 ** byte 2 : command code 0x42 4983 ** byte 3 : device# to be deleted 4984 ** 4985 ** GUI_IDENTIFY_DEVICE : Identify Device 4986 ** byte 0,1 : length 4987 ** byte 2 : command code 0x43 4988 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 4989 ** byte 4/5/6/7 : IDE device mask to be flashed 4990 ** note .... no response data available 4991 ** 4992 ** GUI_CREATE_RAIDSET : Create Raid Set 4993 ** byte 0,1 : length 4994 ** byte 2 : command code 0x50 4995 ** byte 3/4/5/6 : device mask 4996 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 4997 ** 4998 ** GUI_DELETE_RAIDSET : Delete Raid Set 4999 ** byte 0,1 : length 5000 ** byte 2 : command code 0x51 5001 ** byte 3 : raidset# 5002 ** 5003 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5004 ** byte 0,1 : length 5005 ** byte 2 : command code 0x52 5006 ** byte 3 : raidset# 5007 ** byte 4/5/6/7 : device mask for expansion 5008 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5009 ** byte 11/12/13 : repeat for each volume in the raidset .... 5010 ** 5011 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5012 ** byte 0,1 : length 5013 ** byte 2 : command code 0x53 5014 ** byte 3 : raidset# 5015 ** 5016 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5017 ** byte 0,1 : length 5018 ** byte 2 : command code 0x54 5019 ** byte 3/4/5/6 : device mask for hot spare creation 5020 ** 5021 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5022 ** byte 0,1 : length 5023 ** byte 2 : command code 0x55 5024 ** byte 3/4/5/6 : device mask for hot spare deletion 5025 ** 5026 ** GUI_CREATE_VOLUME : Create volume set 5027 ** byte 0,1 : length 5028 ** byte 2 : command code 0x60 5029 ** byte 3 : raidset# 5030 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5031 ** byte 20-27 : volume capacity (blocks) 5032 ** byte 28 : raid level 5033 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5034 ** byte 30 : channel 5035 ** byte 31 : ID 5036 ** byte 32 : LUN 5037 ** byte 33 : 1 enable tag 5038 ** byte 34 : 1 enable cache 5039 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5040 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5041 ** byte 36 : 1 to select quick init 5042 ** 5043 ** GUI_MODIFY_VOLUME : Modify volume Set 5044 ** byte 0,1 : length 5045 ** byte 2 : command code 0x61 5046 ** byte 3 : volumeset# 5047 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5048 ** byte 20-27 : new volume capacity (reserved) 5049 ** byte 28 : new raid level 5050 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5051 ** byte 30 : new channel 5052 ** byte 31 : new ID 5053 ** byte 32 : new LUN 5054 ** byte 33 : 1 enable tag 5055 ** byte 34 : 1 enable cache 5056 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5057 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5058 ** 5059 ** GUI_DELETE_VOLUME : Delete volume set 5060 ** byte 0,1 : length 5061 ** byte 2 : command code 0x62 5062 ** byte 3 : volumeset# 5063 ** 5064 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5065 ** byte 0,1 : length 5066 ** byte 2 : command code 0x63 5067 ** byte 3 : volumeset# 5068 ** 5069 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5070 ** byte 0,1 : length 5071 ** byte 2 : command code 0x64 5072 ** --------------------------------------------------------------------- 5073 ** 4. Returned data 5074 ** --------------------------------------------------------------------- 5075 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5076 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5077 ** (C) status or data : 5078 ** <1> If length == 1 ==> 1 byte status code 5079 ** #define GUI_OK 0x41 5080 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5081 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5082 ** #define GUI_NO_RAIDSET 0x44 5083 ** #define GUI_NO_VOLUMESET 0x45 5084 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5085 ** #define GUI_PARAMETER_ERROR 0x47 5086 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5087 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5088 ** #define GUI_INVALID_PASSWORD 0x4a 5089 ** #define GUI_NO_DISK_SPACE 0x4b 5090 ** #define GUI_CHECKSUM_ERROR 0x4c 5091 ** #define GUI_PASSWORD_REQUIRED 0x4d 5092 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5093 ** (E) Checksum : checksum of length and status or data byte 5094 ************************************************************************** 5095 */
Cache object: c16620ceb95ed64a9ad83bb1c37a8d4f
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