FreeBSD/Linux Kernel Cross Reference
sys/dev/asmc/asmcvar.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32 #define ASMC_MAXFANS 6
33
34 struct asmc_softc {
35 device_t sc_dev;
36 struct mtx sc_mtx;
37 int sc_nfan;
38 int16_t sms_rest_x;
39 int16_t sms_rest_y;
40 int16_t sms_rest_z;
41 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
42 struct sysctl_oid *sc_temp_tree;
43 struct sysctl_oid *sc_sms_tree;
44 struct sysctl_oid *sc_light_tree;
45 const struct asmc_model *sc_model;
46 int sc_rid_port;
47 int sc_rid_irq;
48 struct resource *sc_ioport;
49 struct resource *sc_irq;
50 void *sc_cookie;
51 int sc_sms_intrtype;
52 struct taskqueue *sc_sms_tq;
53 struct task sc_sms_task;
54 uint8_t sc_sms_intr_works;
55 };
56
57 /*
58 * Data port.
59 */
60 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
61 #define ASMC_DATAPORT_WRITE(sc, val) \
62 bus_write_1(sc->sc_ioport, 0x00, val)
63 #define ASMC_STATUS_MASK 0x0f
64
65 /*
66 * Command port.
67 */
68 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
69 #define ASMC_CMDPORT_WRITE(sc, val) \
70 bus_write_1(sc->sc_ioport, 0x04, val)
71 #define ASMC_CMDREAD 0x10
72 #define ASMC_CMDWRITE 0x11
73
74 /*
75 * Interrupt port.
76 */
77 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
78
79 /* Number of keys */
80 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
81
82 /*
83 * Fan control via SMC.
84 */
85 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
86 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
87 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
88 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
89 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
90 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
91 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
92 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
93
94 /*
95 * Sudden Motion Sensor (SMS).
96 */
97 #define ASMC_SMS_INIT1 0xe0
98 #define ASMC_SMS_INIT2 0xf8
99 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
100 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
101 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
102 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
103 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
104 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
105 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
106 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
107 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
108 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
109 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
110 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
111
112 /*
113 * Light Sensor.
114 */
115 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */
116
117 /*
118 * Keyboard backlight.
119 */
120 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
121 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
122 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
123
124 /*
125 * Clamshell.
126 */
127 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
128
129 /*
130 * Interrupt keys.
131 */
132 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
133
134 /*
135 * Temperatures.
136 *
137 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
138 * fourth the Mac Pro 8-core and finally the MacBook Air.
139 *
140 */
141 /* maximum array size for temperatures including the last NULL */
142 #define ASMC_TEMP_MAX 80
143 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
144 "TM0P", NULL }
145 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
146 "northbridge2", "heatsink1", \
147 "heatsink2", "memory", }
148 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
149 "Northbridge Point 1", \
150 "Northbridge Point 2", "Heatsink 1", \
151 "Heatsink 2", "Memory Bank A", }
152
153 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \
154 "TM0P", NULL }
155
156 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \
157 "heatsink1", "heatsink2", \
158 "memory", }
159
160 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \
161 "Northbridge Point 1", \
162 "Heatsink 1","Heatsink 2" \
163 "Memory Bank A", }
164
165 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \
166 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \
167 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \
168 "Ts0P", "Ts0S", NULL }
169
170 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \
171 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \
172 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \
173 "palm_rest", "memory_proximity", }
174
175 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \
176 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \
177 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \
178 "Palm Rest", "Memory Proximity", }
179
180 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
181 "TG0H", "TG0P", "TG0T", NULL }
182
183 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
184 "heatsink2", "memory", "graphics", \
185 "graphicssink", "unknown", }
186
187 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
188 "Heatsink 1", "Heatsink 2", \
189 "Memory Controller", \
190 "Graphics Chip", "Graphics Heatsink", \
191 "Unknown", }
192
193 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
194 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
195 "TTF0", "TW0P", NULL }
196
197 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \
198 "heatsink3", "memory", "graphicssink", \
199 "graphics", "cpu", "cpu2", "unknown1", \
200 "unknown2", "wireless", }
201
202 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \
203 "Main Heatsink 1", "Main Heatsink 2", \
204 "Main Heatsink 3", \
205 "Memory Controller", \
206 "Graphics Chip Heatsink", \
207 "Graphics Chip Diode", \
208 "CPU Temperature Diode", "CPU Point 2", \
209 "Unknown", "Unknown", \
210 "Wireless Module", }
211
212 #define ASMC_MBP51_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \
213 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \
214 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \
215 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \
216 NULL }
217
218 #define ASMC_MBP51_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \
219 "enclosure_bottom_2", "enclosure_bottom_3", \
220 "cpu_diode", "cpu", \
221 "cpu_pin", "gpu_diode", \
222 "gpu", "gpu_heatsink", \
223 "gpu_pin", "gpu_transistor", \
224 "gpu_2_heatsink", "northbridge_diode", \
225 "northbridge_pin", "unknown", \
226 "heatsink_2", "memory_controller", \
227 "pci_express_slot_pin", "pci_express_slot_unk" }
228
229 #define ASMC_MBP51_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \
230 "Enclosure Bottom 2", "Enclosure Bottom 3", \
231 "CPU Diode", "CPU ???", \
232 "CPU Pin", "GPU Diode", \
233 "GPU ???", "GPU Heatsink", \
234 "GPU Pin", "GPU Transistor", \
235 "GPU 2 Heatsink", "Northbridge Diode", \
236 "Northbridge Pin", "Unknown", \
237 "Heatsink 2", "Memory Controller", \
238 "PCI Express Slot Pin", "PCI Express Slot (unk)" }
239
240 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \
241 "TC0C", "TC0D", "TC0P", \
242 "TC1C", "TG0D", "TG0P", \
243 "TG0T", "TMCD", "TP0P", \
244 "TPCD", "Th1H", "Th2H", \
245 "Tm0P", "Ts0P", "Ts0S" }
246
247 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \
248 "enclosure_bottom_2", "cpu0", \
249 "cpu_diode", "cpu_proximity", \
250 "cpu1", "gpu_diode", \
251 "gpu_pin", "gpu_transistor", \
252 "TMCD", "pch_controller_proximity", \
253 "pch_die", "heatsink1", \
254 "heatsink2", "memory-controller", \
255 "palmrest", "memoryproximity" }
256
257 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \
258 "Enclosure Bottom 2", "CPU 0", \
259 "CPU Diode", "CPU Proximity", \
260 "CPU 1", "GPU Diode", \
261 "GPU Pin", "GPU Transistor", \
262 "TMCD", "PCH Controller Proximity", \
263 "PCH Die", "Heat Sink 1", \
264 "Heat Sink 2", "Memory Controller", \
265 "Palm Rest", "Memory Proximity" }
266
267 #define ASMC_MBP55_TEMPS { "TB0T", "TB1T", \
268 "TB2T", "TB3T", \
269 "TC0D", "TC0P", \
270 "TN0D", "TN0P", \
271 "TTF0", \
272 "Th0H", "Th1H", "ThFH", \
273 "Ts0P", "Ts0S", \
274 NULL }
275
276 #define ASMC_MBP55_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \
277 "enclosure_bottom_2", "enclosure_bottom_3", \
278 "cpu_diode", "cpu_pin", \
279 "northbridge_diode", "northbridge_pin", \
280 "unknown", \
281 "heatsink_0", "heatsink_1", "heatsink_2", \
282 "pci_express_slot_pin", "pci_express_slot_unk" }
283
284 #define ASMC_MBP55_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \
285 "Enclosure Bottom 2", "Enclosure Bottom 3", \
286 "CPU Diode", "CPU Pin", \
287 "Northbridge Diode", "Northbridge Pin", \
288 "Unknown", \
289 "Heatsink 0", "Heatsink 1", "Heatsink 2", \
290 "PCI Express Slot Pin", "PCI Express Slot (unk)" }
291
292 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
293 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
294 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
295 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \
296 "Ts0S", NULL }
297
298 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
299 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
300 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
301 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \
302 "Ts0S" }
303
304 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
305 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
306 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
307 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \
308 "Ts0S" }
309
310 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
311 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
312 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
313 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
314 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
315 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
316
317 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
318 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
319 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
320 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
321 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
322 "Th2H", "memory", "Ts0P", "Ts0S" }
323
324 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
325 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
326 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
327 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
328 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
329 "Th2H", "Tm0P", "Ts0P", "Ts0S" }
330
331 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \
332 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
333 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \
334 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \
335 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \
336 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL }
337
338 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \
339 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \
340 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \
341 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \
342 "cpu_core_peci", "gpu_analog", \
343 "gpu_proximity", "geforce_gpu_digital", "tg1f", \
344 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \
345 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \
346 "main_heatsink_r", "main_heatsink_l", "palm_rest", \
347 "bottom_skin", "tsqf" }
348
349 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \
350 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \
351 "CPU Proximity", "CPU Core 1", "CPU Core 2", \
352 "CPU Core 3", "CPU Core 4", "Intel GPU", \
353 "CPU System Agent Core", "CPU Core - PECI", \
354 "GPU Die - Analog", "GPU Proximity", \
355 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \
356 "TGTC", "TGTD", "Memory Proximity", \
357 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \
358 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \
359 "Bottom Skin", "Tsqf" }
360
361 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \
362 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \
363 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \
364 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \
365 "TPCD", NULL }
366
367 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \
368 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \
369 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \
370 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \
371 "TPCD" }
372
373 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \
374 "Battery 1", "Battery 2", "Battery TS_MAX", \
375 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \
376 "TC0J", "CPU 1 Proximity", "TCFC", \
377 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \
378 "GPU Die", "Memory Bank A1", "Memory Module A1", \
379 "PCH Die" }
380
381 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
382 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
383 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
384 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
385 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
386 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
387 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
388 "Ts1S", NULL }
389
390 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
391 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
392 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
393 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
394 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
395 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
396 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
397 "Ts1S" }
398
399 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
400 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
401 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
402 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
403 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
404 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
405 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
406 "Ts1S" }
407
408 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
409 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
410 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
411 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
412 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
413 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
414 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
415 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
416 "Ts1S", NULL }
417
418 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
419 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
420 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
421 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
422 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
423 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
424 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
425 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
426 "Ts1S" }
427
428 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
429 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
430 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
431 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
432 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
433 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
434 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
435 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
436 "Ts1S" }
437 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
438 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
439 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
440 "Northbridge Point 2" }
441
442 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \
443 "TC0H", "TC0P", \
444 "TC1P", "TN0P", \
445 "TN1P", NULL }
446
447 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \
448 "cpu_heatsink", "cpu_proximity1", \
449 "cpu_proximity2", "northbridge_proximity1", \
450 "northbridge_proximity2", }
451
452 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \
453 "CPU Die Core Temperature", \
454 "CPU Heatsink Temperature", \
455 "CPU Proximity 1 Temperature", \
456 "CPU Proximity 2 Temperature", \
457 "Northbridge Proximity 1 Temperature", \
458 "Northbridge Proximity 2 Temperature", }
459
460 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
461 "TC0P", "TH0P", \
462 "TN0D", "TN0P", \
463 "TW0P", NULL }
464
465 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
466 "cpu0_proximity", "hdd_bay", \
467 "northbridge_die", \
468 "northbridge_proximity", \
469 "wireless_proximity", }
470
471 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
472 "CPU0 Heatsink Temperature", \
473 "CPU0 Proximity Temperature", \
474 "HDD Bay Temperature", \
475 "Northbridge Die Core Temperature", \
476 "Northbridge Proximity Temperature", \
477 "Wireless Module Proximity Temperature", }
478
479 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
480 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
481 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
482 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
483 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
484 "TW0P", "Tm0P", "Tp0C", NULL }
485
486 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
487 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
488 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
489 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
490 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
491 "TW0P", "Tm0P", "Tp0C", NULL }
492
493 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
494 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
495 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
496 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
497 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
498 "TW0P", "Tm0P", "Tp0C", NULL }
499
500 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \
501 "TC0D", "TC0P", \
502 "TG0D", "TG1D", \
503 "TG0P", "TG0M", \
504 "TI0P", \
505 "TM0S", "TMBS", \
506 "TM0P", "TP0P", \
507 "TPCD", "Tp0C", \
508 "TW0P", NULL }
509
510 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \
511 "cpu_die", "cpu_proximity", \
512 "gpu_diode1", "gpu_diode2", \
513 "gpu_proximity", "gpu_integrated_switcher", \
514 "thunderbolt_proximity", \
515 "memory_slot1", "memory_slot2", \
516 "memory_proximity", "pch_controller_proximity", \
517 "pch_controller_die", "pwr_supply", \
518 "wireless_proximity", }
519
520 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \
521 "Combo Ambient CPU PCH Wireless DIMM Temperature", \
522 "CPU Die Temperature", "CPU Proximity Temperature", \
523 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \
524 "GPU Proximity Temperature", \
525 "Integrated Graphics/GPU Switcher Temperature", \
526 "Thunderbolt Proximity Temperature", \
527 "Memory Slot 1 Temperature", \
528 "Memory Slot 2 Temperature", \
529 "Memory Slots Proximity Temperature", \
530 "Platform Controller Hub Proximity Temperature", \
531 "Platform Controller Hub Die Temperature", \
532 "Power Supply Temperature", \
533 "Wireless Module Proximity Temperature", }
534
535 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \
536 "TA2p", "TC0c", \
537 "TC0p", "TC1c", \
538 "TCGc", "TCSc", \
539 "TCXC", "TCXR", \
540 "TM0p", "TPCd", \
541 "TW0p", "Te0T", \
542 "Tm0P", NULL }
543
544 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \
545 "ambient_air3", "cpu_core1_peci", \
546 "cpu_proximity", "cpu_core2_peci", \
547 "intel_gpu", "cpu_sa_core_peci", \
548 "cpu_core", "cpu_peci_dts", \
549 "memory_proximity", "pch_controller_die", \
550 "wireless_proximity", "thunderbolt_diode", \
551 "logic_board", }
552
553 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \
554 "Ambient Air Temperature 2", \
555 "Ambient Air Temperature 3", \
556 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \
557 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \
558 "CPU System Agent Core PECI Temperature", \
559 "CPU Core Temperature", "CPU PECI DTS Temperature", \
560 "Memory Proximity Temperature", \
561 "Platform Controller Hub Die Temperature", \
562 "Wireless Module Proximity Temperature", \
563 "Thunderbolt Diode Temperature", \
564 "Logic Board temperature", }
565
566 #define ASMC_MP1_TEMPS { "TA0P", \
567 "TCAH", "TCBH", \
568 "TC0P", "TC0C", "TC1C", \
569 "TC2C", "TC3C", "THTG", \
570 "TH0P", "TH1P", \
571 "TH2P", "TH3P", \
572 "TM0P", "TM1P", "TM2P", \
573 "TM8P", "TM9P", "TMAP", \
574 "TM0S", "TM1S", "TM2P", "TM3S", \
575 "TM8S", "TM9S", "TMAS", "TMBS", \
576 "TN0H", "TS0C", \
577 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL }
578
579 #define ASMC_MP1_TEMPNAMES { "ambient", \
580 "cpu_a_heatsink", "cpu_b_heatsink", \
581 "cpu_a_proximity", "cpu_core0", "cpu_core1", \
582 "cpu_core2", "cpu_core3", "THTG", \
583 "hdd_bay0", "hdd_bay1", \
584 "hdd_bay2", "hdd_bay3", \
585 "memory_card_a_proximity0", \
586 "memory_card_a_proximity1", \
587 "memory_card_a_proximity2", \
588 "memory_card_b_proximity0", \
589 "memory_card_b_proximity1", \
590 "memory_card_b_proximity2", \
591 "memory_card_a_slot0", \
592 "memory_card_a_slot1", \
593 "memory_card_a_slot2", \
594 "memory_card_a_slot3", \
595 "memory_card_b_slot0", \
596 "memory_card_b_slot1", \
597 "memory_card_b_slot2", \
598 "memory_card_b_slot3", \
599 "mch_heatsink", "expansion_slots", \
600 "power_supply_loc0", "power_supply_loc1", \
601 "Tv0S", "Tv1S", }
602
603 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \
604 "CPU A Heatsink", "CPU B Heatsink", \
605 "CPU A Proximity", \
606 "CPU Core 1", "CPU Core 2", \
607 "CPU Core 3", "CPU Core 4", "THTG", \
608 "Hard Drive Bay 1", "Hard Drive Bay 2", \
609 "Hard Drive Bay 3", "Hard Drive Bay 4", \
610 "Memory Riser A, Proximity 1", \
611 "Memory Riser A, Proximity 2", \
612 "Memory Riser A, Proximity 3", \
613 "Memory Riser B, Proximity 1", \
614 "Memory Riser B, Proximity 2", \
615 "Memory Riser B, Proximity 3", \
616 "Memory Riser A, Slot 1", \
617 "Memory Riser A, Slot 2", \
618 "Memory Riser A, Slot 3", \
619 "Memory Riser A, Slot 4", \
620 "Memory Riser B, Slot 1", \
621 "Memory Riser B, Slot 2", \
622 "Memory Riser B, Slot 3", \
623 "Memory Riser B, Slot 4", \
624 "MCH Heatsink", "Expansion Slots", \
625 "Power Supply, Location 1", \
626 "Power Supply, Location 2", \
627 "Tv0S", "Tv1S", }
628
629 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
630 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
631 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
632 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
633 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
634 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
635 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
636 NULL }
637
638 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
639 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
640 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
641 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
642 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
643 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
644 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
645
646 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
647 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
648 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
649 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
650 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
651 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
652 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
653
654 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
655 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
656 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
657 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
658 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
659 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
660 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
661 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
662 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
663 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
664 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
665 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
666 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
667 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
668 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
669 NULL }
670
671 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
672 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
673 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
674 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
675 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
676 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
677 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
678 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
679 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
680 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
681 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
682 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
683 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
684 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
685 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
686
687 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
688 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
689 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
690 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
691 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
692 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
693 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
694 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
695 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
696 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
697 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
698 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
699 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
700 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
701 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
702
703 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \
704 "TG1D", "TG1P", "TM0P", "TM1P", NULL }
705
706 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \
707 "cpu_proximity", "gpu_diode_1", \
708 "gpu_proximity_1", "gpu_diode_2", \
709 "gpu_proximity_2", "mem_proximity_1", \
710 "mem_proximity_2" }
711
712 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \
713 "CPU Proximity", "GPU Diode 1", \
714 "GPU Proximity 1", "GPU Diode 2", \
715 "GPU Proximity 2", "Memory Bank A", \
716 "Memory Bank B" }
717
718 #define ASMC_MBA_TEMPS { "TB0T", NULL }
719 #define ASMC_MBA_TEMPNAMES { "enclosure" }
720 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
721
722 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
723 "TC0D", "TC0E", "TC0P", NULL }
724
725 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
726 "TC0D", "TC0E", "TC0P" }
727
728 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
729 "TC0D", "TC0E", "TC0P" }
730
731 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \
732 "TC0D", "TC0E", "TC0F", "TC0P", \
733 "TC1C", "TC2C", "TCGC", "TCSA", \
734 "TH0F", "TH0J", "TH0O", "TH0o", \
735 "TM0P", "TPCD", "Ta0P", "Th1H", \
736 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \
737 NULL }
738
739 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \
740 "TC0D", "TC0E", "TC0F", "TC0P", \
741 "TC1C", "TC2C", "TCGC", "TCSA", \
742 "TH0F", "TH0J", "TH0O", "TH0o", \
743 "TM0P", "TPCD", "Ta0P", "Th1H", \
744 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \
745 NULL }
746
747 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \
748 "TC0D", "TC0E", "TC0F", "TC0P", \
749 "TC1C", "TC2C", "TCGC", "TCSA", \
750 "TH0F", "TH0J", "TH0O", "TH0o", \
751 "TM0P", "TPCD", "Ta0P", "Th1H", \
752 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \
753 NULL }
754
755 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \
756 "TC0D", "TC0E", "TC0F", "TC0P", \
757 "TC1C", "TC2C", "TCGC", "TCSA", \
758 "TCXC", "THSP", "TM0P", "TPCD", \
759 "Ta0P", "Th1H", "Tm0P", "Tm1P", \
760 "Ts0P", "Ts0S", NULL }
761
762 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \
763 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \
764 "cpucore1", "cpucore2", "cpupeci", "pecisa", \
765 "TCXC", "THSP", "memorybank", "pchdie", \
766 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \
767 "palmrest", "memoryproximity" }
768
769 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\
770 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
771 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
772 "TCXC", "THSP", "Memory Bank A", "PCH Die", \
773 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \
774 "Palm Rest", "Memory Proximity" }
775
776 /*
777 * TODO: validate the temp zones for MBA 6.x !
778 */
779 #define ASMC_MBA6_TEMPS { "TB0T", "TB1T", "TB2T", \
780 "TC0E", "TC0F", "TC0P", \
781 "TC1C", "TC2C", "TCGC", "TCSA", \
782 "TCXC", "THSP", "TM0P", "TPCD", \
783 "Ta0P", "Th1H", "Tm0P", \
784 "Ts0P", "Ts0S", NULL }
785
786 #define ASMC_MBA6_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \
787 "cputemp1", "cputemp2", "cpuproximity", \
788 "cpucore1", "cpucore2", "cpupeci", "pecisa", \
789 "TCXC", "THSP", "memorybank", "pchdie", \
790 "Ta0P", "heatpipe", "mainboardproximity1", \
791 "palmrest", "memoryproximity" }
792
793 #define ASMC_MBA6_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \
794 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
795 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
796 "TCXC", "THSP", "Memory Bank A", "PCH Die", \
797 "Ta0P", "Heatpipe", "Mainboard Proximity 1", \
798 "Palm Rest", "Memory Proximity" }
799
800
801 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \
802 "TC0E", "TC0F", "TC0P", \
803 "TC1C", "TC2C", \
804 "TCGC", "TCSA", "TCXC", \
805 "THSP", "TM0P", "TPCD", \
806 "TW0P" "Ta0P", "Th1H", \
807 "Tm0P", "Ts0P", "Ts0S", NULL }
808
809 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \
810 "cputemp1", "cputemp2", "cpuproximity", \
811 "cpucore1", "cpucore2", \
812 "pecigpu", "pecisa", "pecicpu", \
813 "thunderboltproximity", "memorybank", "pchdie", \
814 "wirelessproximity", "airflowproximity", "heatpipe", \
815 "mainboardproximity", "palmrest", "memoryproximity" }
816
817 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \
818 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
819 "CPU Core 1", "CPU Core 2", \
820 "PECI GPU", "PECI SA", "PECI CPU", \
821 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \
822 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \
823 "Mainboard Proximity", "Palm Rest", "Memory Proximity" }
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