Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/asmc/asmcvar.h
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1 /*- 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/11.2/sys/dev/asmc/asmcvar.h 331722 2018-03-29 02:50:57Z eadler $ 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int16_t sms_rest_x; 37 int16_t sms_rest_y; 38 int16_t sms_rest_z; 39 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 40 struct sysctl_oid *sc_temp_tree; 41 struct sysctl_oid *sc_sms_tree; 42 struct sysctl_oid *sc_light_tree; 43 struct asmc_model *sc_model; 44 int sc_rid_port; 45 int sc_rid_irq; 46 struct resource *sc_ioport; 47 struct resource *sc_irq; 48 void *sc_cookie; 49 int sc_sms_intrtype; 50 struct taskqueue *sc_sms_tq; 51 struct task sc_sms_task; 52 uint8_t sc_sms_intr_works; 53 }; 54 55 /* 56 * Data port. 57 */ 58 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 59 #define ASMC_DATAPORT_WRITE(sc, val) \ 60 bus_write_1(sc->sc_ioport, 0x00, val) 61 #define ASMC_STATUS_MASK 0x0f 62 63 /* 64 * Command port. 65 */ 66 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 67 #define ASMC_CMDPORT_WRITE(sc, val) \ 68 bus_write_1(sc->sc_ioport, 0x04, val) 69 #define ASMC_CMDREAD 0x10 70 #define ASMC_CMDWRITE 0x11 71 72 /* 73 * Interrupt port. 74 */ 75 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 76 77 78 /* Number of keys */ 79 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 80 81 /* 82 * Fan control via SMC. 83 */ 84 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 85 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 86 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 87 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 88 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 89 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 90 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 91 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 92 93 /* 94 * Sudden Motion Sensor (SMS). 95 */ 96 #define ASMC_SMS_INIT1 0xe0 97 #define ASMC_SMS_INIT2 0xf8 98 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 99 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 100 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 101 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 102 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 103 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 104 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 105 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 106 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 107 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 108 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 109 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 110 111 /* 112 * Keyboard backlight. 113 */ 114 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 115 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 116 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 117 118 /* 119 * Clamshell. 120 */ 121 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 122 123 /* 124 * Interrupt keys. 125 */ 126 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 127 128 /* 129 * Temperatures. 130 * 131 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 132 * fourth the Mac Pro 8-core and finally the MacBook Air. 133 * 134 */ 135 /* maximum array size for temperatures including the last NULL */ 136 #define ASMC_TEMP_MAX 80 137 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 138 "TM0P", NULL } 139 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 140 "northbridge2", "heatsink1", \ 141 "heatsink2", "memory", } 142 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 143 "Northbridge Point 1", \ 144 "Northbridge Point 2", "Heatsink 1", \ 145 "Heatsink 2", "Memory Bank A", } 146 147 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 148 "TM0P", NULL } 149 150 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 151 "heatsink1", "heatsink2", \ 152 "memory", } 153 154 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 155 "Northbridge Point 1", \ 156 "Heatsink 1","Heatsink 2" \ 157 "Memory Bank A", } 158 159 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 160 "TG0H", "TG0P", "TG0T", NULL } 161 162 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 163 "heatsink2", "memory", "graphics", \ 164 "graphicssink", "unknown", } 165 166 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 167 "Heatsink 1", "Heatsink 2", \ 168 "Memory Controller", \ 169 "Graphics Chip", "Graphics Heatsink", \ 170 "Unknown", } 171 172 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 173 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 174 "TTF0", "TW0P", NULL } 175 176 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 177 "heatsink3", "memory", "graphicssink", \ 178 "graphics", "cpu", "cpu2", "unknown1", \ 179 "unknown2", "wireless", } 180 181 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 182 "Main Heatsink 1", "Main Heatsink 2", \ 183 "Main Heatsink 3", \ 184 "Memory Controller", \ 185 "Graphics Chip Heatsink", \ 186 "Graphics Chip Diode", \ 187 "CPU Temperature Diode", "CPU Point 2", \ 188 "Unknown", "Unknown", \ 189 "Wireless Module", } 190 191 #define ASMC_MBP5_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 192 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 193 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 194 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 195 NULL } 196 197 #define ASMC_MBP5_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 198 "enclosure_bottom_2", "enclosure_bottom_3", \ 199 "cpu_diode", "cpu", \ 200 "cpu_pin", "gpu_diode", \ 201 "gpu", "gpu_heatsink", \ 202 "gpu_pin", "gpu_transistor", \ 203 "gpu_2_heatsink", "northbridge_diode", \ 204 "northbridge_pin", "unknown", \ 205 "heatsink_2", "memory_controller", \ 206 "pci_express_slot_pin", "pci_express_slot_unk" } 207 208 #define ASMC_MBP5_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 209 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 210 "CPU Diode", "CPU ???", \ 211 "CPU Pin", "GPU Diode", \ 212 "GPU ???", "GPU Heatsink", \ 213 "GPU Pin", "GPU Transistor", \ 214 "GPU 2 Heatsink", "Northbridge Diode", \ 215 "Northbridge Pin", "Unknown", \ 216 "Heatsink 2", "Memory Controller", \ 217 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 218 219 #define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 220 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 221 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 222 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 223 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 224 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 225 226 #define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 227 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 228 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 229 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 230 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 231 "Th2H", "memory", "Ts0P", "Ts0S" } 232 233 #define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 234 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 235 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 236 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 237 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 238 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 239 240 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 241 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 242 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 243 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 244 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 245 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 246 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 247 "Ts1S", NULL } 248 249 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 250 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 251 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 252 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 253 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 254 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 255 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 256 "Ts1S" } 257 258 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 259 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 260 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 261 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 262 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 263 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 264 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 265 "Ts1S" } 266 267 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 268 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 269 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 270 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 271 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 272 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 273 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 274 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 275 "Ts1S", NULL } 276 277 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 278 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 279 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 280 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 281 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 282 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 283 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 284 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 285 "Ts1S" } 286 287 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 288 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 289 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 290 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 291 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 292 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 293 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 294 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 295 "Ts1S" } 296 297 298 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 299 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 300 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 301 "Northbridge Point 2" } 302 303 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 304 "TC0P", "TH0P", \ 305 "TN0D", "TN0P", \ 306 "TW0P", NULL } 307 308 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 309 "cpu0_proximity", "hdd_bay", \ 310 "northbridge_die", \ 311 "northbridge_proximity", \ 312 "wireless_proximity", } 313 314 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 315 "CPU0 Heatsink Temperature", \ 316 "CPU0 Proximity Temperature", \ 317 "HDD Bay Temperature", \ 318 "Northbridge Die Core Temperature", \ 319 "Northbridge Proximity Temperature", \ 320 "Wireless Module Proximity Temperature", } 321 322 #define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 323 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 324 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 325 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 326 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 327 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 328 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 329 NULL } 330 331 #define ASMC_MP_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 332 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 333 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 334 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 335 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 336 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 337 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 338 339 #define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 340 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 341 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 342 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 343 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 344 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 345 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 346 347 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 348 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 349 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 350 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 351 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 352 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 353 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 354 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 355 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 356 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 357 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 358 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 359 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 360 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 361 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 362 NULL } 363 364 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 365 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 366 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 367 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 368 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 369 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 370 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 371 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 372 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 373 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 374 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 375 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 376 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 377 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 378 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 379 380 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 381 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 382 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 383 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 384 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 385 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 386 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 387 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 388 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 389 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 390 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 391 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 392 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 393 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 394 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 395 396 #define ASMC_MBA_TEMPS { "TB0T", NULL } 397 #define ASMC_MBA_TEMPNAMES { "enclosure" } 398 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 399 400 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 401 "TC0D", "TC0E", "TC0P", NULL } 402 403 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 404 "TC0D", "TC0E", "TC0P" } 405 406 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 407 "TC0D", "TC0E", "TC0P" } 408 409 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 410 "TC0D", "TC0E", "TC0F", "TC0P", \ 411 "TC1C", "TC2C", "TCGC", "TCSA", \ 412 "TCXC", "THSP", "TM0P", "TPCD", \ 413 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 414 "Ts0P", "Ts0S", NULL } 415 416 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 417 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 418 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 419 "TCXC", "THSP", "memorybank", "pchdie", \ 420 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 421 "palmrest", "memoryproximity" } 422 423 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 424 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 425 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 426 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 427 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 428 "Palm Rest", "Memory Proximity" }
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