Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ata/ata-all.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/ata.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/endian.h> 38 #include <sys/ctype.h> 39 #include <sys/conf.h> 40 #include <sys/bus.h> 41 #include <sys/bio.h> 42 #include <sys/malloc.h> 43 #include <sys/sysctl.h> 44 #include <sys/sema.h> 45 #include <sys/taskqueue.h> 46 #include <vm/uma.h> 47 #include <machine/stdarg.h> 48 #include <machine/resource.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/pci/pcivar.h> 53 #include <ata_if.h> 54 55 #include <cam/cam.h> 56 #include <cam/cam_ccb.h> 57 #include <cam/cam_sim.h> 58 #include <cam/cam_xpt_sim.h> 59 #include <cam/cam_debug.h> 60 61 /* prototypes */ 62 static void ataaction(struct cam_sim *sim, union ccb *ccb); 63 static void atapoll(struct cam_sim *sim); 64 static void ata_cam_begin_transaction(device_t dev, union ccb *ccb); 65 static void ata_cam_end_transaction(device_t dev, struct ata_request *request); 66 static void ata_cam_request_sense(device_t dev, struct ata_request *request); 67 static int ata_check_ids(device_t dev, union ccb *ccb); 68 static void ata_conn_event(void *context, int dummy); 69 static void ata_interrupt_locked(void *data); 70 static int ata_module_event_handler(module_t mod, int what, void *arg); 71 static void ata_periodic_poll(void *data); 72 static int ata_str2mode(const char *str); 73 74 /* global vars */ 75 MALLOC_DEFINE(M_ATA, "ata_generic", "ATA driver generic layer"); 76 int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data) = NULL; 77 devclass_t ata_devclass; 78 int ata_dma_check_80pin = 1; 79 80 /* sysctl vars */ 81 static SYSCTL_NODE(_hw, OID_AUTO, ata, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 82 "ATA driver parameters"); 83 SYSCTL_INT(_hw_ata, OID_AUTO, ata_dma_check_80pin, 84 CTLFLAG_RWTUN, &ata_dma_check_80pin, 0, 85 "Check for 80pin cable before setting ATA DMA mode"); 86 FEATURE(ata_cam, "ATA devices are accessed through the cam(4) driver"); 87 88 /* 89 * newbus device interface related functions 90 */ 91 int 92 ata_probe(device_t dev) 93 { 94 return (BUS_PROBE_LOW_PRIORITY); 95 } 96 97 int 98 ata_attach(device_t dev) 99 { 100 struct ata_channel *ch = device_get_softc(dev); 101 int error, rid; 102 struct cam_devq *devq; 103 const char *res; 104 char buf[64]; 105 int i, mode; 106 107 /* check that we have a virgin channel to attach */ 108 if (ch->r_irq) 109 return EEXIST; 110 111 /* initialize the softc basics */ 112 ch->dev = dev; 113 ch->state = ATA_IDLE; 114 bzero(&ch->state_mtx, sizeof(struct mtx)); 115 mtx_init(&ch->state_mtx, "ATA state lock", NULL, MTX_DEF); 116 TASK_INIT(&ch->conntask, 0, ata_conn_event, dev); 117 for (i = 0; i < 16; i++) { 118 ch->user[i].revision = 0; 119 snprintf(buf, sizeof(buf), "dev%d.sata_rev", i); 120 if (resource_int_value(device_get_name(dev), 121 device_get_unit(dev), buf, &mode) != 0 && 122 resource_int_value(device_get_name(dev), 123 device_get_unit(dev), "sata_rev", &mode) != 0) 124 mode = -1; 125 if (mode >= 0) 126 ch->user[i].revision = mode; 127 ch->user[i].mode = 0; 128 snprintf(buf, sizeof(buf), "dev%d.mode", i); 129 if (resource_string_value(device_get_name(dev), 130 device_get_unit(dev), buf, &res) == 0) 131 mode = ata_str2mode(res); 132 else if (resource_string_value(device_get_name(dev), 133 device_get_unit(dev), "mode", &res) == 0) 134 mode = ata_str2mode(res); 135 else 136 mode = -1; 137 if (mode >= 0) 138 ch->user[i].mode = mode; 139 if (ch->flags & ATA_SATA) 140 ch->user[i].bytecount = 8192; 141 else 142 ch->user[i].bytecount = 65536; 143 ch->user[i].caps = 0; 144 ch->curr[i] = ch->user[i]; 145 if (ch->flags & ATA_SATA) { 146 if (ch->pm_level > 0) 147 ch->user[i].caps |= CTS_SATA_CAPS_H_PMREQ; 148 if (ch->pm_level > 1) 149 ch->user[i].caps |= CTS_SATA_CAPS_D_PMREQ; 150 } else { 151 if (!(ch->flags & ATA_NO_48BIT_DMA)) 152 ch->user[i].caps |= CTS_ATA_CAPS_H_DMA48; 153 } 154 } 155 callout_init(&ch->poll_callout, 1); 156 157 /* allocate DMA resources if DMA HW present*/ 158 if (ch->dma.alloc) 159 ch->dma.alloc(dev); 160 161 /* setup interrupt delivery */ 162 rid = ATA_IRQ_RID; 163 ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 164 RF_SHAREABLE | RF_ACTIVE); 165 if (!ch->r_irq) { 166 device_printf(dev, "unable to allocate interrupt\n"); 167 return ENXIO; 168 } 169 if ((error = bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 170 ata_interrupt, ch, &ch->ih))) { 171 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 172 device_printf(dev, "unable to setup interrupt\n"); 173 return error; 174 } 175 176 if (ch->flags & ATA_PERIODIC_POLL) 177 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 178 mtx_lock(&ch->state_mtx); 179 /* Create the device queue for our SIM. */ 180 devq = cam_simq_alloc(1); 181 if (devq == NULL) { 182 device_printf(dev, "Unable to allocate simq\n"); 183 error = ENOMEM; 184 goto err1; 185 } 186 /* Construct SIM entry */ 187 ch->sim = cam_sim_alloc(ataaction, atapoll, "ata", ch, 188 device_get_unit(dev), &ch->state_mtx, 1, 0, devq); 189 if (ch->sim == NULL) { 190 device_printf(dev, "unable to allocate sim\n"); 191 cam_simq_free(devq); 192 error = ENOMEM; 193 goto err1; 194 } 195 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 196 device_printf(dev, "unable to register xpt bus\n"); 197 error = ENXIO; 198 goto err2; 199 } 200 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 201 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 202 device_printf(dev, "unable to create path\n"); 203 error = ENXIO; 204 goto err3; 205 } 206 mtx_unlock(&ch->state_mtx); 207 return (0); 208 209 err3: 210 xpt_bus_deregister(cam_sim_path(ch->sim)); 211 err2: 212 cam_sim_free(ch->sim, /*free_devq*/TRUE); 213 ch->sim = NULL; 214 err1: 215 bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq); 216 mtx_unlock(&ch->state_mtx); 217 if (ch->flags & ATA_PERIODIC_POLL) 218 callout_drain(&ch->poll_callout); 219 return (error); 220 } 221 222 int 223 ata_detach(device_t dev) 224 { 225 struct ata_channel *ch = device_get_softc(dev); 226 227 /* check that we have a valid channel to detach */ 228 if (!ch->r_irq) 229 return ENXIO; 230 231 /* grap the channel lock so no new requests gets launched */ 232 mtx_lock(&ch->state_mtx); 233 ch->state |= ATA_STALL_QUEUE; 234 mtx_unlock(&ch->state_mtx); 235 if (ch->flags & ATA_PERIODIC_POLL) 236 callout_drain(&ch->poll_callout); 237 238 taskqueue_drain(taskqueue_thread, &ch->conntask); 239 240 mtx_lock(&ch->state_mtx); 241 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 242 xpt_free_path(ch->path); 243 xpt_bus_deregister(cam_sim_path(ch->sim)); 244 cam_sim_free(ch->sim, /*free_devq*/TRUE); 245 ch->sim = NULL; 246 mtx_unlock(&ch->state_mtx); 247 248 /* release resources */ 249 bus_teardown_intr(dev, ch->r_irq, ch->ih); 250 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 251 ch->r_irq = NULL; 252 253 /* free DMA resources if DMA HW present*/ 254 if (ch->dma.free) 255 ch->dma.free(dev); 256 257 mtx_destroy(&ch->state_mtx); 258 return 0; 259 } 260 261 static void 262 ata_conn_event(void *context, int dummy) 263 { 264 device_t dev = (device_t)context; 265 struct ata_channel *ch = device_get_softc(dev); 266 union ccb *ccb; 267 268 mtx_lock(&ch->state_mtx); 269 if (ch->sim == NULL) { 270 mtx_unlock(&ch->state_mtx); 271 return; 272 } 273 ata_reinit(dev); 274 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 275 return; 276 if (xpt_create_path(&ccb->ccb_h.path, NULL, 277 cam_sim_path(ch->sim), 278 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 279 xpt_free_ccb(ccb); 280 return; 281 } 282 xpt_rescan(ccb); 283 mtx_unlock(&ch->state_mtx); 284 } 285 286 int 287 ata_reinit(device_t dev) 288 { 289 struct ata_channel *ch = device_get_softc(dev); 290 struct ata_request *request; 291 292 xpt_freeze_simq(ch->sim, 1); 293 if ((request = ch->running)) { 294 ch->running = NULL; 295 if (ch->state == ATA_ACTIVE) 296 ch->state = ATA_IDLE; 297 callout_stop(&request->callout); 298 if (ch->dma.unload) 299 ch->dma.unload(request); 300 request->result = ERESTART; 301 ata_cam_end_transaction(dev, request); 302 } 303 /* reset the controller HW, the channel and device(s) */ 304 ATA_RESET(dev); 305 /* Tell the XPT about the event */ 306 xpt_async(AC_BUS_RESET, ch->path, NULL); 307 xpt_release_simq(ch->sim, TRUE); 308 return(0); 309 } 310 311 int 312 ata_suspend(device_t dev) 313 { 314 struct ata_channel *ch; 315 316 /* check for valid device */ 317 if (!dev || !(ch = device_get_softc(dev))) 318 return ENXIO; 319 320 if (ch->flags & ATA_PERIODIC_POLL) 321 callout_drain(&ch->poll_callout); 322 mtx_lock(&ch->state_mtx); 323 xpt_freeze_simq(ch->sim, 1); 324 while (ch->state != ATA_IDLE) 325 msleep(ch, &ch->state_mtx, PRIBIO, "atasusp", hz/100); 326 mtx_unlock(&ch->state_mtx); 327 return(0); 328 } 329 330 int 331 ata_resume(device_t dev) 332 { 333 struct ata_channel *ch; 334 int error; 335 336 /* check for valid device */ 337 if (!dev || !(ch = device_get_softc(dev))) 338 return ENXIO; 339 340 mtx_lock(&ch->state_mtx); 341 error = ata_reinit(dev); 342 xpt_release_simq(ch->sim, TRUE); 343 mtx_unlock(&ch->state_mtx); 344 if (ch->flags & ATA_PERIODIC_POLL) 345 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 346 return error; 347 } 348 349 void 350 ata_interrupt(void *data) 351 { 352 struct ata_channel *ch = (struct ata_channel *)data; 353 354 mtx_lock(&ch->state_mtx); 355 ata_interrupt_locked(data); 356 mtx_unlock(&ch->state_mtx); 357 } 358 359 static void 360 ata_interrupt_locked(void *data) 361 { 362 struct ata_channel *ch = (struct ata_channel *)data; 363 struct ata_request *request; 364 365 /* ignore interrupt if its not for us */ 366 if (ch->hw.status && !ch->hw.status(ch->dev)) 367 return; 368 369 /* do we have a running request */ 370 if (!(request = ch->running)) 371 return; 372 373 ATA_DEBUG_RQ(request, "interrupt"); 374 375 /* safetycheck for the right state */ 376 if (ch->state == ATA_IDLE) { 377 device_printf(request->dev, "interrupt on idle channel ignored\n"); 378 return; 379 } 380 381 /* 382 * we have the HW locks, so end the transaction for this request 383 * if it finishes immediately otherwise wait for next interrupt 384 */ 385 if (ch->hw.end_transaction(request) == ATA_OP_FINISHED) { 386 ch->running = NULL; 387 if (ch->state == ATA_ACTIVE) 388 ch->state = ATA_IDLE; 389 ata_cam_end_transaction(ch->dev, request); 390 return; 391 } 392 } 393 394 static void 395 ata_periodic_poll(void *data) 396 { 397 struct ata_channel *ch = (struct ata_channel *)data; 398 399 callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch); 400 ata_interrupt(ch); 401 } 402 403 void 404 ata_print_cable(device_t dev, u_int8_t *who) 405 { 406 device_printf(dev, 407 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 408 } 409 410 /* 411 * misc support functions 412 */ 413 void 414 ata_default_registers(device_t dev) 415 { 416 struct ata_channel *ch = device_get_softc(dev); 417 418 /* fill in the defaults from whats setup already */ 419 ch->r_io[ATA_ERROR].res = ch->r_io[ATA_FEATURE].res; 420 ch->r_io[ATA_ERROR].offset = ch->r_io[ATA_FEATURE].offset; 421 ch->r_io[ATA_IREASON].res = ch->r_io[ATA_COUNT].res; 422 ch->r_io[ATA_IREASON].offset = ch->r_io[ATA_COUNT].offset; 423 ch->r_io[ATA_STATUS].res = ch->r_io[ATA_COMMAND].res; 424 ch->r_io[ATA_STATUS].offset = ch->r_io[ATA_COMMAND].offset; 425 ch->r_io[ATA_ALTSTAT].res = ch->r_io[ATA_CONTROL].res; 426 ch->r_io[ATA_ALTSTAT].offset = ch->r_io[ATA_CONTROL].offset; 427 } 428 429 void 430 ata_udelay(int interval) 431 { 432 /* for now just use DELAY, the timer/sleep subsystems are not there yet */ 433 if (1 || interval < (1000000/hz) || ata_delayed_attach) 434 DELAY(interval); 435 else 436 pause("ataslp", interval/(1000000/hz)); 437 } 438 439 const char * 440 ata_cmd2str(struct ata_request *request) 441 { 442 static char buffer[20]; 443 444 if (request->flags & ATA_R_ATAPI) { 445 switch (request->u.atapi.sense.key ? 446 request->u.atapi.saved_cmd : request->u.atapi.ccb[0]) { 447 case 0x00: return ("TEST_UNIT_READY"); 448 case 0x01: return ("REZERO"); 449 case 0x03: return ("REQUEST_SENSE"); 450 case 0x04: return ("FORMAT"); 451 case 0x08: return ("READ"); 452 case 0x0a: return ("WRITE"); 453 case 0x10: return ("WEOF"); 454 case 0x11: return ("SPACE"); 455 case 0x12: return ("INQUIRY"); 456 case 0x15: return ("MODE_SELECT"); 457 case 0x19: return ("ERASE"); 458 case 0x1a: return ("MODE_SENSE"); 459 case 0x1b: return ("START_STOP"); 460 case 0x1e: return ("PREVENT_ALLOW"); 461 case 0x23: return ("ATAPI_READ_FORMAT_CAPACITIES"); 462 case 0x25: return ("READ_CAPACITY"); 463 case 0x28: return ("READ_BIG"); 464 case 0x2a: return ("WRITE_BIG"); 465 case 0x2b: return ("LOCATE"); 466 case 0x34: return ("READ_POSITION"); 467 case 0x35: return ("SYNCHRONIZE_CACHE"); 468 case 0x3b: return ("WRITE_BUFFER"); 469 case 0x3c: return ("READ_BUFFER"); 470 case 0x42: return ("READ_SUBCHANNEL"); 471 case 0x43: return ("READ_TOC"); 472 case 0x45: return ("PLAY_10"); 473 case 0x47: return ("PLAY_MSF"); 474 case 0x48: return ("PLAY_TRACK"); 475 case 0x4b: return ("PAUSE"); 476 case 0x51: return ("READ_DISK_INFO"); 477 case 0x52: return ("READ_TRACK_INFO"); 478 case 0x53: return ("RESERVE_TRACK"); 479 case 0x54: return ("SEND_OPC_INFO"); 480 case 0x55: return ("MODE_SELECT_BIG"); 481 case 0x58: return ("REPAIR_TRACK"); 482 case 0x59: return ("READ_MASTER_CUE"); 483 case 0x5a: return ("MODE_SENSE_BIG"); 484 case 0x5b: return ("CLOSE_TRACK/SESSION"); 485 case 0x5c: return ("READ_BUFFER_CAPACITY"); 486 case 0x5d: return ("SEND_CUE_SHEET"); 487 case 0x96: return ("SERVICE_ACTION_IN"); 488 case 0xa1: return ("BLANK_CMD"); 489 case 0xa3: return ("SEND_KEY"); 490 case 0xa4: return ("REPORT_KEY"); 491 case 0xa5: return ("PLAY_12"); 492 case 0xa6: return ("LOAD_UNLOAD"); 493 case 0xad: return ("READ_DVD_STRUCTURE"); 494 case 0xb4: return ("PLAY_CD"); 495 case 0xbb: return ("SET_SPEED"); 496 case 0xbd: return ("MECH_STATUS"); 497 case 0xbe: return ("READ_CD"); 498 case 0xff: return ("POLL_DSC"); 499 } 500 } else { 501 switch (request->u.ata.command) { 502 case 0x00: 503 switch (request->u.ata.feature) { 504 case 0x00: return ("NOP FLUSHQUEUE"); 505 case 0x01: return ("NOP AUTOPOLL"); 506 } 507 return ("NOP"); 508 case 0x03: return ("CFA_REQUEST_EXTENDED_ERROR"); 509 case 0x06: 510 switch (request->u.ata.feature) { 511 case 0x01: return ("DSM TRIM"); 512 } 513 return "DSM"; 514 case 0x08: return ("DEVICE_RESET"); 515 case 0x20: return ("READ"); 516 case 0x24: return ("READ48"); 517 case 0x25: return ("READ_DMA48"); 518 case 0x26: return ("READ_DMA_QUEUED48"); 519 case 0x27: return ("READ_NATIVE_MAX_ADDRESS48"); 520 case 0x29: return ("READ_MUL48"); 521 case 0x2a: return ("READ_STREAM_DMA48"); 522 case 0x2b: return ("READ_STREAM48"); 523 case 0x2f: return ("READ_LOG_EXT"); 524 case 0x30: return ("WRITE"); 525 case 0x34: return ("WRITE48"); 526 case 0x35: return ("WRITE_DMA48"); 527 case 0x36: return ("WRITE_DMA_QUEUED48"); 528 case 0x37: return ("SET_MAX_ADDRESS48"); 529 case 0x39: return ("WRITE_MUL48"); 530 case 0x3a: return ("WRITE_STREAM_DMA48"); 531 case 0x3b: return ("WRITE_STREAM48"); 532 case 0x3d: return ("WRITE_DMA_FUA48"); 533 case 0x3e: return ("WRITE_DMA_QUEUED_FUA48"); 534 case 0x3f: return ("WRITE_LOG_EXT"); 535 case 0x40: return ("READ_VERIFY"); 536 case 0x42: return ("READ_VERIFY48"); 537 case 0x45: 538 switch (request->u.ata.feature) { 539 case 0x55: return ("WRITE_UNCORRECTABLE48 PSEUDO"); 540 case 0xaa: return ("WRITE_UNCORRECTABLE48 FLAGGED"); 541 } 542 return "WRITE_UNCORRECTABLE48"; 543 case 0x51: return ("CONFIGURE_STREAM"); 544 case 0x60: return ("READ_FPDMA_QUEUED"); 545 case 0x61: return ("WRITE_FPDMA_QUEUED"); 546 case 0x63: return ("NCQ_NON_DATA"); 547 case 0x64: return ("SEND_FPDMA_QUEUED"); 548 case 0x65: return ("RECEIVE_FPDMA_QUEUED"); 549 case 0x67: 550 if (request->u.ata.feature == 0xec) 551 return ("SEP_ATTN IDENTIFY"); 552 switch (request->u.ata.lba) { 553 case 0x00: return ("SEP_ATTN READ BUFFER"); 554 case 0x02: return ("SEP_ATTN RECEIVE DIAGNOSTIC RESULTS"); 555 case 0x80: return ("SEP_ATTN WRITE BUFFER"); 556 case 0x82: return ("SEP_ATTN SEND DIAGNOSTIC"); 557 } 558 return ("SEP_ATTN"); 559 case 0x70: return ("SEEK"); 560 case 0x87: return ("CFA_TRANSLATE_SECTOR"); 561 case 0x90: return ("EXECUTE_DEVICE_DIAGNOSTIC"); 562 case 0x92: return ("DOWNLOAD_MICROCODE"); 563 case 0xa0: return ("PACKET"); 564 case 0xa1: return ("ATAPI_IDENTIFY"); 565 case 0xa2: return ("SERVICE"); 566 case 0xb0: 567 switch(request->u.ata.feature) { 568 case 0xd0: return ("SMART READ ATTR VALUES"); 569 case 0xd1: return ("SMART READ ATTR THRESHOLDS"); 570 case 0xd3: return ("SMART SAVE ATTR VALUES"); 571 case 0xd4: return ("SMART EXECUTE OFFLINE IMMEDIATE"); 572 case 0xd5: return ("SMART READ LOG DATA"); 573 case 0xd8: return ("SMART ENABLE OPERATION"); 574 case 0xd9: return ("SMART DISABLE OPERATION"); 575 case 0xda: return ("SMART RETURN STATUS"); 576 } 577 return ("SMART"); 578 case 0xb1: return ("DEVICE CONFIGURATION"); 579 case 0xc0: return ("CFA_ERASE"); 580 case 0xc4: return ("READ_MUL"); 581 case 0xc5: return ("WRITE_MUL"); 582 case 0xc6: return ("SET_MULTI"); 583 case 0xc7: return ("READ_DMA_QUEUED"); 584 case 0xc8: return ("READ_DMA"); 585 case 0xca: return ("WRITE_DMA"); 586 case 0xcc: return ("WRITE_DMA_QUEUED"); 587 case 0xcd: return ("CFA_WRITE_MULTIPLE_WITHOUT_ERASE"); 588 case 0xce: return ("WRITE_MUL_FUA48"); 589 case 0xd1: return ("CHECK_MEDIA_CARD_TYPE"); 590 case 0xda: return ("GET_MEDIA_STATUS"); 591 case 0xde: return ("MEDIA_LOCK"); 592 case 0xdf: return ("MEDIA_UNLOCK"); 593 case 0xe0: return ("STANDBY_IMMEDIATE"); 594 case 0xe1: return ("IDLE_IMMEDIATE"); 595 case 0xe2: return ("STANDBY"); 596 case 0xe3: return ("IDLE"); 597 case 0xe4: return ("READ_BUFFER/PM"); 598 case 0xe5: return ("CHECK_POWER_MODE"); 599 case 0xe6: return ("SLEEP"); 600 case 0xe7: return ("FLUSHCACHE"); 601 case 0xe8: return ("WRITE_PM"); 602 case 0xea: return ("FLUSHCACHE48"); 603 case 0xec: return ("ATA_IDENTIFY"); 604 case 0xed: return ("MEDIA_EJECT"); 605 case 0xef: 606 switch (request->u.ata.feature) { 607 case 0x03: return ("SETFEATURES SET TRANSFER MODE"); 608 case 0x02: return ("SETFEATURES ENABLE WCACHE"); 609 case 0x82: return ("SETFEATURES DISABLE WCACHE"); 610 case 0x06: return ("SETFEATURES ENABLE PUIS"); 611 case 0x86: return ("SETFEATURES DISABLE PUIS"); 612 case 0x07: return ("SETFEATURES SPIN-UP"); 613 case 0x10: return ("SETFEATURES ENABLE SATA FEATURE"); 614 case 0x90: return ("SETFEATURES DISABLE SATA FEATURE"); 615 case 0xaa: return ("SETFEATURES ENABLE RCACHE"); 616 case 0x55: return ("SETFEATURES DISABLE RCACHE"); 617 case 0x5d: return ("SETFEATURES ENABLE RELIRQ"); 618 case 0xdd: return ("SETFEATURES DISABLE RELIRQ"); 619 case 0x5e: return ("SETFEATURES ENABLE SRVIRQ"); 620 case 0xde: return ("SETFEATURES DISABLE SRVIRQ"); 621 } 622 return "SETFEATURES"; 623 case 0xf1: return ("SECURITY_SET_PASSWORD"); 624 case 0xf2: return ("SECURITY_UNLOCK"); 625 case 0xf3: return ("SECURITY_ERASE_PREPARE"); 626 case 0xf4: return ("SECURITY_ERASE_UNIT"); 627 case 0xf5: return ("SECURITY_FREEZE_LOCK"); 628 case 0xf6: return ("SECURITY_DISABLE_PASSWORD"); 629 case 0xf8: return ("READ_NATIVE_MAX_ADDRESS"); 630 case 0xf9: return ("SET_MAX_ADDRESS"); 631 } 632 } 633 sprintf(buffer, "unknown CMD (0x%02x)", request->u.ata.command); 634 return (buffer); 635 } 636 637 const char * 638 ata_mode2str(int mode) 639 { 640 switch (mode) { 641 case -1: return "UNSUPPORTED"; 642 case ATA_PIO0: return "PIO0"; 643 case ATA_PIO1: return "PIO1"; 644 case ATA_PIO2: return "PIO2"; 645 case ATA_PIO3: return "PIO3"; 646 case ATA_PIO4: return "PIO4"; 647 case ATA_WDMA0: return "WDMA0"; 648 case ATA_WDMA1: return "WDMA1"; 649 case ATA_WDMA2: return "WDMA2"; 650 case ATA_UDMA0: return "UDMA16"; 651 case ATA_UDMA1: return "UDMA25"; 652 case ATA_UDMA2: return "UDMA33"; 653 case ATA_UDMA3: return "UDMA40"; 654 case ATA_UDMA4: return "UDMA66"; 655 case ATA_UDMA5: return "UDMA100"; 656 case ATA_UDMA6: return "UDMA133"; 657 case ATA_SA150: return "SATA150"; 658 case ATA_SA300: return "SATA300"; 659 case ATA_SA600: return "SATA600"; 660 default: 661 if (mode & ATA_DMA_MASK) 662 return "BIOSDMA"; 663 else 664 return "BIOSPIO"; 665 } 666 } 667 668 static int 669 ata_str2mode(const char *str) 670 { 671 672 if (!strcasecmp(str, "PIO0")) return (ATA_PIO0); 673 if (!strcasecmp(str, "PIO1")) return (ATA_PIO1); 674 if (!strcasecmp(str, "PIO2")) return (ATA_PIO2); 675 if (!strcasecmp(str, "PIO3")) return (ATA_PIO3); 676 if (!strcasecmp(str, "PIO4")) return (ATA_PIO4); 677 if (!strcasecmp(str, "WDMA0")) return (ATA_WDMA0); 678 if (!strcasecmp(str, "WDMA1")) return (ATA_WDMA1); 679 if (!strcasecmp(str, "WDMA2")) return (ATA_WDMA2); 680 if (!strcasecmp(str, "UDMA0")) return (ATA_UDMA0); 681 if (!strcasecmp(str, "UDMA16")) return (ATA_UDMA0); 682 if (!strcasecmp(str, "UDMA1")) return (ATA_UDMA1); 683 if (!strcasecmp(str, "UDMA25")) return (ATA_UDMA1); 684 if (!strcasecmp(str, "UDMA2")) return (ATA_UDMA2); 685 if (!strcasecmp(str, "UDMA33")) return (ATA_UDMA2); 686 if (!strcasecmp(str, "UDMA3")) return (ATA_UDMA3); 687 if (!strcasecmp(str, "UDMA44")) return (ATA_UDMA3); 688 if (!strcasecmp(str, "UDMA4")) return (ATA_UDMA4); 689 if (!strcasecmp(str, "UDMA66")) return (ATA_UDMA4); 690 if (!strcasecmp(str, "UDMA5")) return (ATA_UDMA5); 691 if (!strcasecmp(str, "UDMA100")) return (ATA_UDMA5); 692 if (!strcasecmp(str, "UDMA6")) return (ATA_UDMA6); 693 if (!strcasecmp(str, "UDMA133")) return (ATA_UDMA6); 694 return (-1); 695 } 696 697 int 698 ata_atapi(device_t dev, int target) 699 { 700 struct ata_channel *ch = device_get_softc(dev); 701 702 return (ch->devices & (ATA_ATAPI_MASTER << target)); 703 } 704 705 void 706 ata_timeout(void *arg) 707 { 708 struct ata_request *request; 709 struct ata_channel *ch; 710 711 request = arg; 712 ch = device_get_softc(request->parent); 713 //request->flags |= ATA_R_DEBUG; 714 ATA_DEBUG_RQ(request, "timeout"); 715 716 /* 717 * If we have an ATA_ACTIVE request running, we flag the request 718 * ATA_R_TIMEOUT so ata_cam_end_transaction() will handle it correctly. 719 * Also, NULL out the running request so we wont loose the race with 720 * an eventual interrupt arriving late. 721 */ 722 if (ch->state == ATA_ACTIVE) { 723 request->flags |= ATA_R_TIMEOUT; 724 if (ch->dma.unload) 725 ch->dma.unload(request); 726 ch->running = NULL; 727 ch->state = ATA_IDLE; 728 ata_cam_end_transaction(ch->dev, request); 729 } 730 mtx_unlock(&ch->state_mtx); 731 } 732 733 static void 734 ata_cam_begin_transaction(device_t dev, union ccb *ccb) 735 { 736 struct ata_channel *ch = device_get_softc(dev); 737 struct ata_request *request; 738 739 request = &ch->request; 740 bzero(request, sizeof(*request)); 741 742 /* setup request */ 743 request->dev = NULL; 744 request->parent = dev; 745 request->unit = ccb->ccb_h.target_id; 746 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 747 request->data = ccb->ataio.data_ptr; 748 request->bytecount = ccb->ataio.dxfer_len; 749 request->u.ata.command = ccb->ataio.cmd.command; 750 request->u.ata.feature = ((uint16_t)ccb->ataio.cmd.features_exp << 8) | 751 (uint16_t)ccb->ataio.cmd.features; 752 request->u.ata.count = ((uint16_t)ccb->ataio.cmd.sector_count_exp << 8) | 753 (uint16_t)ccb->ataio.cmd.sector_count; 754 if (ccb->ataio.cmd.flags & CAM_ATAIO_48BIT) { 755 request->flags |= ATA_R_48BIT; 756 request->u.ata.lba = 757 ((uint64_t)ccb->ataio.cmd.lba_high_exp << 40) | 758 ((uint64_t)ccb->ataio.cmd.lba_mid_exp << 32) | 759 ((uint64_t)ccb->ataio.cmd.lba_low_exp << 24); 760 } else { 761 request->u.ata.lba = 762 ((uint64_t)(ccb->ataio.cmd.device & 0x0f) << 24); 763 } 764 request->u.ata.lba |= ((uint64_t)ccb->ataio.cmd.lba_high << 16) | 765 ((uint64_t)ccb->ataio.cmd.lba_mid << 8) | 766 (uint64_t)ccb->ataio.cmd.lba_low; 767 if (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT) 768 request->flags |= ATA_R_NEEDRESULT; 769 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 770 ccb->ataio.cmd.flags & CAM_ATAIO_DMA) 771 request->flags |= ATA_R_DMA; 772 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 773 request->flags |= ATA_R_READ; 774 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 775 request->flags |= ATA_R_WRITE; 776 if (ccb->ataio.cmd.command == ATA_READ_MUL || 777 ccb->ataio.cmd.command == ATA_READ_MUL48 || 778 ccb->ataio.cmd.command == ATA_WRITE_MUL || 779 ccb->ataio.cmd.command == ATA_WRITE_MUL48) { 780 request->transfersize = min(request->bytecount, 781 ch->curr[ccb->ccb_h.target_id].bytecount); 782 } else 783 request->transfersize = min(request->bytecount, 512); 784 } else { 785 request->data = ccb->csio.data_ptr; 786 request->bytecount = ccb->csio.dxfer_len; 787 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 788 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 789 request->u.atapi.ccb, ccb->csio.cdb_len); 790 request->flags |= ATA_R_ATAPI; 791 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 792 request->flags |= ATA_R_ATAPI16; 793 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 794 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 795 request->flags |= ATA_R_DMA; 796 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 797 request->flags |= ATA_R_READ; 798 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) 799 request->flags |= ATA_R_WRITE; 800 request->transfersize = min(request->bytecount, 801 ch->curr[ccb->ccb_h.target_id].bytecount); 802 } 803 request->retries = 0; 804 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 805 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 806 request->ccb = ccb; 807 request->flags |= ATA_R_DATA_IN_CCB; 808 809 ch->running = request; 810 ch->state = ATA_ACTIVE; 811 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 812 ch->running = NULL; 813 ch->state = ATA_IDLE; 814 ata_cam_end_transaction(dev, request); 815 return; 816 } 817 } 818 819 static void 820 ata_cam_request_sense(device_t dev, struct ata_request *request) 821 { 822 struct ata_channel *ch = device_get_softc(dev); 823 union ccb *ccb = request->ccb; 824 825 ch->requestsense = 1; 826 827 bzero(request, sizeof(*request)); 828 request->dev = NULL; 829 request->parent = dev; 830 request->unit = ccb->ccb_h.target_id; 831 request->data = (void *)&ccb->csio.sense_data; 832 request->bytecount = ccb->csio.sense_len; 833 request->u.atapi.ccb[0] = ATAPI_REQUEST_SENSE; 834 request->u.atapi.ccb[4] = ccb->csio.sense_len; 835 request->flags |= ATA_R_ATAPI; 836 if (ch->curr[ccb->ccb_h.target_id].atapi == 16) 837 request->flags |= ATA_R_ATAPI16; 838 if (ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 839 request->flags |= ATA_R_DMA; 840 request->flags |= ATA_R_READ; 841 request->transfersize = min(request->bytecount, 842 ch->curr[ccb->ccb_h.target_id].bytecount); 843 request->retries = 0; 844 request->timeout = (ccb->ccb_h.timeout + 999) / 1000; 845 callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); 846 request->ccb = ccb; 847 848 ch->running = request; 849 ch->state = ATA_ACTIVE; 850 if (ch->hw.begin_transaction(request) == ATA_OP_FINISHED) { 851 ch->running = NULL; 852 ch->state = ATA_IDLE; 853 ata_cam_end_transaction(dev, request); 854 return; 855 } 856 } 857 858 static void 859 ata_cam_process_sense(device_t dev, struct ata_request *request) 860 { 861 struct ata_channel *ch = device_get_softc(dev); 862 union ccb *ccb = request->ccb; 863 int fatalerr = 0; 864 865 ch->requestsense = 0; 866 867 if (request->flags & ATA_R_TIMEOUT) 868 fatalerr = 1; 869 if ((request->flags & ATA_R_TIMEOUT) == 0 && 870 (request->status & ATA_S_ERROR) == 0 && 871 request->result == 0) { 872 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 873 } else { 874 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 875 ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; 876 } 877 878 xpt_done(ccb); 879 /* Do error recovery if needed. */ 880 if (fatalerr) 881 ata_reinit(dev); 882 } 883 884 static void 885 ata_cam_end_transaction(device_t dev, struct ata_request *request) 886 { 887 struct ata_channel *ch = device_get_softc(dev); 888 union ccb *ccb = request->ccb; 889 int fatalerr = 0; 890 891 if (ch->requestsense) { 892 ata_cam_process_sense(dev, request); 893 return; 894 } 895 896 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 897 if (request->flags & ATA_R_TIMEOUT) { 898 xpt_freeze_simq(ch->sim, 1); 899 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 900 ccb->ccb_h.status |= CAM_CMD_TIMEOUT | CAM_RELEASE_SIMQ; 901 fatalerr = 1; 902 } else if (request->status & ATA_S_ERROR) { 903 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 904 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 905 } else { 906 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 907 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 908 } 909 } else if (request->result == ERESTART) 910 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 911 else if (request->result != 0) 912 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 913 else 914 ccb->ccb_h.status |= CAM_REQ_CMP; 915 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP && 916 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 917 xpt_freeze_devq(ccb->ccb_h.path, 1); 918 ccb->ccb_h.status |= CAM_DEV_QFRZN; 919 } 920 if (ccb->ccb_h.func_code == XPT_ATA_IO && 921 ((request->status & ATA_S_ERROR) || 922 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT))) { 923 struct ata_res *res = &ccb->ataio.res; 924 res->status = request->status; 925 res->error = request->error; 926 res->lba_low = request->u.ata.lba; 927 res->lba_mid = request->u.ata.lba >> 8; 928 res->lba_high = request->u.ata.lba >> 16; 929 res->device = request->u.ata.lba >> 24; 930 res->lba_low_exp = request->u.ata.lba >> 24; 931 res->lba_mid_exp = request->u.ata.lba >> 32; 932 res->lba_high_exp = request->u.ata.lba >> 40; 933 res->sector_count = request->u.ata.count; 934 res->sector_count_exp = request->u.ata.count >> 8; 935 } 936 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 937 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 938 ccb->ataio.resid = 939 ccb->ataio.dxfer_len - request->donecount; 940 } else { 941 ccb->csio.resid = 942 ccb->csio.dxfer_len - request->donecount; 943 } 944 } 945 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 946 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) 947 ata_cam_request_sense(dev, request); 948 else 949 xpt_done(ccb); 950 /* Do error recovery if needed. */ 951 if (fatalerr) 952 ata_reinit(dev); 953 } 954 955 static int 956 ata_check_ids(device_t dev, union ccb *ccb) 957 { 958 struct ata_channel *ch = device_get_softc(dev); 959 960 if (ccb->ccb_h.target_id > ((ch->flags & ATA_NO_SLAVE) ? 0 : 1)) { 961 ccb->ccb_h.status = CAM_TID_INVALID; 962 xpt_done(ccb); 963 return (-1); 964 } 965 if (ccb->ccb_h.target_lun != 0) { 966 ccb->ccb_h.status = CAM_LUN_INVALID; 967 xpt_done(ccb); 968 return (-1); 969 } 970 /* 971 * It's a programming error to see AUXILIARY register requests. 972 */ 973 KASSERT(ccb->ccb_h.func_code != XPT_ATA_IO || 974 ((ccb->ataio.ata_flags & ATA_FLAG_AUX) == 0), 975 ("AUX register unsupported")); 976 return (0); 977 } 978 979 static void 980 ataaction(struct cam_sim *sim, union ccb *ccb) 981 { 982 device_t dev, parent; 983 struct ata_channel *ch; 984 985 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ataaction func_code=%x\n", 986 ccb->ccb_h.func_code)); 987 988 ch = (struct ata_channel *)cam_sim_softc(sim); 989 dev = ch->dev; 990 switch (ccb->ccb_h.func_code) { 991 /* Common cases first */ 992 case XPT_ATA_IO: /* Execute the requested I/O operation */ 993 case XPT_SCSI_IO: 994 if (ata_check_ids(dev, ccb)) 995 return; 996 if ((ch->devices & ((ATA_ATA_MASTER | ATA_ATAPI_MASTER) 997 << ccb->ccb_h.target_id)) == 0) { 998 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 999 break; 1000 } 1001 if (ch->running) 1002 device_printf(dev, "already running!\n"); 1003 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1004 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1005 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1006 struct ata_res *res = &ccb->ataio.res; 1007 1008 bzero(res, sizeof(*res)); 1009 if (ch->devices & (ATA_ATA_MASTER << ccb->ccb_h.target_id)) { 1010 res->lba_high = 0; 1011 res->lba_mid = 0; 1012 } else { 1013 res->lba_high = 0xeb; 1014 res->lba_mid = 0x14; 1015 } 1016 ccb->ccb_h.status = CAM_REQ_CMP; 1017 break; 1018 } 1019 ata_cam_begin_transaction(dev, ccb); 1020 return; 1021 case XPT_ABORT: /* Abort the specified CCB */ 1022 /* XXX Implement */ 1023 ccb->ccb_h.status = CAM_REQ_INVALID; 1024 break; 1025 case XPT_SET_TRAN_SETTINGS: 1026 { 1027 struct ccb_trans_settings *cts = &ccb->cts; 1028 struct ata_cam_device *d; 1029 1030 if (ata_check_ids(dev, ccb)) 1031 return; 1032 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1033 d = &ch->curr[ccb->ccb_h.target_id]; 1034 else 1035 d = &ch->user[ccb->ccb_h.target_id]; 1036 if (ch->flags & ATA_SATA) { 1037 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 1038 d->revision = cts->xport_specific.sata.revision; 1039 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) { 1040 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1041 d->mode = ATA_SETMODE(ch->dev, 1042 ccb->ccb_h.target_id, 1043 cts->xport_specific.sata.mode); 1044 } else 1045 d->mode = cts->xport_specific.sata.mode; 1046 } 1047 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 1048 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 1049 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 1050 d->atapi = cts->xport_specific.sata.atapi; 1051 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 1052 d->caps = cts->xport_specific.sata.caps; 1053 } else { 1054 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_MODE) { 1055 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1056 d->mode = ATA_SETMODE(ch->dev, 1057 ccb->ccb_h.target_id, 1058 cts->xport_specific.ata.mode); 1059 } else 1060 d->mode = cts->xport_specific.ata.mode; 1061 } 1062 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_BYTECOUNT) 1063 d->bytecount = cts->xport_specific.ata.bytecount; 1064 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_ATAPI) 1065 d->atapi = cts->xport_specific.ata.atapi; 1066 if (cts->xport_specific.ata.valid & CTS_ATA_VALID_CAPS) 1067 d->caps = cts->xport_specific.ata.caps; 1068 } 1069 ccb->ccb_h.status = CAM_REQ_CMP; 1070 break; 1071 } 1072 case XPT_GET_TRAN_SETTINGS: 1073 { 1074 struct ccb_trans_settings *cts = &ccb->cts; 1075 struct ata_cam_device *d; 1076 1077 if (ata_check_ids(dev, ccb)) 1078 return; 1079 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1080 d = &ch->curr[ccb->ccb_h.target_id]; 1081 else 1082 d = &ch->user[ccb->ccb_h.target_id]; 1083 cts->protocol = PROTO_UNSPECIFIED; 1084 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1085 if (ch->flags & ATA_SATA) { 1086 cts->transport = XPORT_SATA; 1087 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1088 cts->xport_specific.sata.valid = 0; 1089 cts->xport_specific.sata.mode = d->mode; 1090 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 1091 cts->xport_specific.sata.bytecount = d->bytecount; 1092 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 1093 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1094 cts->xport_specific.sata.revision = 1095 ATA_GETREV(dev, ccb->ccb_h.target_id); 1096 if (cts->xport_specific.sata.revision != 0xff) { 1097 cts->xport_specific.sata.valid |= 1098 CTS_SATA_VALID_REVISION; 1099 } 1100 cts->xport_specific.sata.caps = 1101 d->caps & CTS_SATA_CAPS_D; 1102 if (ch->pm_level) { 1103 cts->xport_specific.sata.caps |= 1104 CTS_SATA_CAPS_H_PMREQ; 1105 } 1106 cts->xport_specific.sata.caps &= 1107 ch->user[ccb->ccb_h.target_id].caps; 1108 } else { 1109 cts->xport_specific.sata.revision = d->revision; 1110 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 1111 cts->xport_specific.sata.caps = d->caps; 1112 } 1113 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1114 cts->xport_specific.sata.atapi = d->atapi; 1115 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 1116 } else { 1117 cts->transport = XPORT_ATA; 1118 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1119 cts->xport_specific.ata.valid = 0; 1120 cts->xport_specific.ata.mode = d->mode; 1121 cts->xport_specific.ata.valid |= CTS_ATA_VALID_MODE; 1122 cts->xport_specific.ata.bytecount = d->bytecount; 1123 cts->xport_specific.ata.valid |= CTS_ATA_VALID_BYTECOUNT; 1124 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1125 cts->xport_specific.ata.caps = 1126 d->caps & CTS_ATA_CAPS_D; 1127 if (!(ch->flags & ATA_NO_48BIT_DMA)) 1128 cts->xport_specific.ata.caps |= 1129 CTS_ATA_CAPS_H_DMA48; 1130 cts->xport_specific.ata.caps &= 1131 ch->user[ccb->ccb_h.target_id].caps; 1132 } else 1133 cts->xport_specific.ata.caps = d->caps; 1134 cts->xport_specific.ata.valid |= CTS_ATA_VALID_CAPS; 1135 cts->xport_specific.ata.atapi = d->atapi; 1136 cts->xport_specific.ata.valid |= CTS_ATA_VALID_ATAPI; 1137 } 1138 ccb->ccb_h.status = CAM_REQ_CMP; 1139 break; 1140 } 1141 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1142 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1143 ata_reinit(dev); 1144 ccb->ccb_h.status = CAM_REQ_CMP; 1145 break; 1146 case XPT_TERM_IO: /* Terminate the I/O process */ 1147 /* XXX Implement */ 1148 ccb->ccb_h.status = CAM_REQ_INVALID; 1149 break; 1150 case XPT_PATH_INQ: /* Path routing inquiry */ 1151 { 1152 struct ccb_pathinq *cpi = &ccb->cpi; 1153 1154 parent = device_get_parent(dev); 1155 cpi->version_num = 1; /* XXX??? */ 1156 cpi->hba_inquiry = PI_SDTR_ABLE; 1157 cpi->target_sprt = 0; 1158 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 1159 cpi->hba_eng_cnt = 0; 1160 if (ch->flags & ATA_NO_SLAVE) 1161 cpi->max_target = 0; 1162 else 1163 cpi->max_target = 1; 1164 cpi->max_lun = 0; 1165 cpi->initiator_id = 0; 1166 cpi->bus_id = cam_sim_bus(sim); 1167 if (ch->flags & ATA_SATA) 1168 cpi->base_transfer_speed = 150000; 1169 else 1170 cpi->base_transfer_speed = 3300; 1171 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1172 strlcpy(cpi->hba_vid, "ATA", HBA_IDLEN); 1173 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1174 cpi->unit_number = cam_sim_unit(sim); 1175 if (ch->flags & ATA_SATA) 1176 cpi->transport = XPORT_SATA; 1177 else 1178 cpi->transport = XPORT_ATA; 1179 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1180 cpi->protocol = PROTO_ATA; 1181 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1182 cpi->maxio = ch->dma.max_iosize ? ch->dma.max_iosize : DFLTPHYS; 1183 if (device_get_devclass(device_get_parent(parent)) == 1184 devclass_find("pci")) { 1185 cpi->hba_vendor = pci_get_vendor(parent); 1186 cpi->hba_device = pci_get_device(parent); 1187 cpi->hba_subvendor = pci_get_subvendor(parent); 1188 cpi->hba_subdevice = pci_get_subdevice(parent); 1189 } 1190 cpi->ccb_h.status = CAM_REQ_CMP; 1191 break; 1192 } 1193 default: 1194 ccb->ccb_h.status = CAM_REQ_INVALID; 1195 break; 1196 } 1197 xpt_done(ccb); 1198 } 1199 1200 static void 1201 atapoll(struct cam_sim *sim) 1202 { 1203 struct ata_channel *ch = (struct ata_channel *)cam_sim_softc(sim); 1204 1205 ata_interrupt_locked(ch); 1206 } 1207 1208 /* 1209 * module handeling 1210 */ 1211 static int 1212 ata_module_event_handler(module_t mod, int what, void *arg) 1213 { 1214 1215 switch (what) { 1216 case MOD_LOAD: 1217 ata_devclass = devclass_find("ata"); 1218 return 0; 1219 1220 case MOD_UNLOAD: 1221 return 0; 1222 1223 default: 1224 return EOPNOTSUPP; 1225 } 1226 } 1227 1228 static moduledata_t ata_moduledata = { "ata", ata_module_event_handler, NULL }; 1229 DECLARE_MODULE(ata, ata_moduledata, SI_SUB_DRIVERS, SI_ORDER_ANY); 1230 MODULE_VERSION(ata, 1); 1231 MODULE_DEPEND(ata, cam, 1, 1, 1);
Cache object: 9808565c36e59cd329c52a76c6fac73a
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