Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ata/ata-all.h
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1 /*- 2 * Copyright (c) 1998 - 2004 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* ATA register defines */ 32 #define ATA_DATA 0x00 /* data register */ 33 34 #define ATA_ERROR 0x01 /* (R) error register */ 35 #define ATA_E_ILI 0x01 /* illegal length */ 36 #define ATA_E_NM 0x02 /* no media */ 37 #define ATA_E_ABORT 0x04 /* command aborted */ 38 #define ATA_E_MCR 0x08 /* media change request */ 39 #define ATA_E_IDNF 0x10 /* ID not found */ 40 #define ATA_E_MC 0x20 /* media changed */ 41 #define ATA_E_UNC 0x40 /* uncorrectable data */ 42 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 43 #define ATA_E_MASK 0x0f /* error mask */ 44 #define ATA_SK_MASK 0xf0 /* sense key mask */ 45 #define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ 46 #define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ 47 #define ATA_SK_NOT_READY 0x20 /* no access to drive */ 48 #define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ 49 #define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ 50 #define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ 51 #define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ 52 #define ATA_SK_DATA_PROTECT 0x70 /* write protect */ 53 #define ATA_SK_BLANK_CHECK 0x80 /* blank check */ 54 #define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ 55 #define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ 56 #define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ 57 #define ATA_SK_EQUAL 0xc0 /* equal */ 58 #define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ 59 #define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ 60 #define ATA_SK_RESERVED 0xf0 61 62 #define ATA_FEATURE 0x01 /* (W) feature register */ 63 #define ATA_F_DMA 0x01 /* enable DMA */ 64 #define ATA_F_OVL 0x02 /* enable overlap */ 65 66 #define ATA_COUNT 0x02 /* (W) sector count */ 67 #define ATA_IREASON 0x02 /* (R) interrupt reason */ 68 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 69 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 70 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 71 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 72 73 #define ATA_SECTOR 0x03 /* sector # */ 74 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 75 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 76 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 77 #define ATA_D_LBA 0x40 /* use LBA addressing */ 78 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 79 80 #define ATA_CMD 0x07 /* command register */ 81 82 #define ATA_STATUS 0x07 /* status register */ 83 #define ATA_S_ERROR 0x01 /* error */ 84 #define ATA_S_INDEX 0x02 /* index */ 85 #define ATA_S_CORR 0x04 /* data corrected */ 86 #define ATA_S_DRQ 0x08 /* data request */ 87 #define ATA_S_DSC 0x10 /* drive seek completed */ 88 #define ATA_S_SERVICE 0x10 /* drive needs service */ 89 #define ATA_S_DWF 0x20 /* drive write fault */ 90 #define ATA_S_DMA 0x20 /* DMA ready */ 91 #define ATA_S_READY 0x40 /* drive ready */ 92 #define ATA_S_BUSY 0x80 /* busy */ 93 94 #define ATA_ALTSTAT 0x08 /* alternate status register */ 95 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */ 96 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ 97 #define ATA_PC98_ALTOFFSET 0x10c /* do for PC98 devices */ 98 #define ATA_A_IDS 0x02 /* disable interrupts */ 99 #define ATA_A_RESET 0x04 /* RESET controller */ 100 #define ATA_A_4BIT 0x08 /* 4 head bits */ 101 102 /* ATAPI misc defines */ 103 #define ATAPI_MAGIC_LSB 0x14 104 #define ATAPI_MAGIC_MSB 0xeb 105 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 106 #define ATAPI_P_WRITE (ATA_S_DRQ) 107 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 108 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 109 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 110 #define ATAPI_P_ABORT 0 111 112 /* misc defines */ 113 #define ATA_PRIMARY 0x1f0 114 #define ATA_SECONDARY 0x170 115 #define ATA_PC98_BANK 0x432 116 #define ATA_IOSIZE 0x08 117 #define ATA_PC98_IOSIZE 0x10 118 #define ATA_ALTIOSIZE 0x01 119 #define ATA_BMIOSIZE 0x08 120 #define ATA_PC98_BANKIOSIZE 0x01 121 #define ATA_IOADDR_RID 0 122 #define ATA_ALTADDR_RID 1 123 #define ATA_BMADDR_RID 0x20 124 #define ATA_PC98_ALTADDR_RID 8 125 #define ATA_PC98_BANKADDR_RID 9 126 127 #define ATA_IRQ_RID 0 128 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 129 130 /* busmaster DMA related defines */ 131 #define ATA_DMA_ENTRIES 256 132 #define ATA_DMA_EOT 0x80000000 133 134 #define ATA_BMCMD_PORT 0x09 135 #define ATA_BMCMD_START_STOP 0x01 136 #define ATA_BMCMD_WRITE_READ 0x08 137 138 #define ATA_BMDEVSPEC_0 0x0a 139 #define ATA_BMSTAT_PORT 0x0b 140 #define ATA_BMSTAT_ACTIVE 0x01 141 #define ATA_BMSTAT_ERROR 0x02 142 #define ATA_BMSTAT_INTERRUPT 0x04 143 #define ATA_BMSTAT_MASK 0x07 144 #define ATA_BMSTAT_DMA_MASTER 0x20 145 #define ATA_BMSTAT_DMA_SLAVE 0x40 146 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 147 148 #define ATA_BMDEVSPEC_1 0x0c 149 #define ATA_BMDTP_PORT 0x0d 150 151 #define ATA_IDX_ADDR 0x0e 152 #define ATA_IDX_DATA 0x0f 153 #define ATA_MAX_RES 0x10 154 155 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 156 #define ATA_OP_CONTINUES 0 157 #define ATA_OP_FINISHED 1 158 159 #define ATA_MAX_28BIT_LBA 268435455 160 161 /* ATAPI request sense structure */ 162 struct atapi_sense { 163 u_int8_t error_code :7; /* current or deferred errors */ 164 u_int8_t valid :1; /* follows ATAPI spec */ 165 u_int8_t segment; /* Segment number */ 166 u_int8_t sense_key :4; /* sense key */ 167 u_int8_t reserved2_4 :1; /* reserved */ 168 u_int8_t ili :1; /* incorrect length indicator */ 169 u_int8_t eom :1; /* end of medium */ 170 u_int8_t filemark :1; /* filemark */ 171 u_int32_t cmd_info __packed; /* cmd information */ 172 u_int8_t sense_length; /* additional sense len (n-7) */ 173 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ 174 u_int8_t asc; /* additional sense code */ 175 u_int8_t ascq; /* additional sense code qual */ 176 u_int8_t replaceable_unit_code; /* replaceable unit code */ 177 u_int8_t sk_specific :7; /* sense key specific */ 178 u_int8_t sksv :1; /* sense key specific info OK */ 179 u_int8_t sk_specific1; /* sense key specific */ 180 u_int8_t sk_specific2; /* sense key specific */ 181 }; 182 183 struct ata_request { 184 struct ata_device *device; /* ptr to device softc */ 185 void *driver; /* driver specific */ 186 187 union { 188 struct { 189 u_int8_t command; /* command reg */ 190 u_int8_t feature; /* feature reg */ 191 u_int16_t count; /* count reg */ 192 u_int64_t lba; /* lba reg */ 193 } ata; 194 struct { 195 u_int8_t ccb[16]; /* ATAPI command block */ 196 struct atapi_sense sense_data; /* ATAPI request sense data */ 197 u_int8_t sense_key; /* ATAPI request sense key */ 198 u_int8_t sense_cmd; /* ATAPI saved command */ 199 } atapi; 200 } u; 201 202 u_int8_t status; /* ATA status */ 203 u_int8_t error; /* ATA error */ 204 u_int8_t dmastat; /* DMA status */ 205 206 u_int32_t bytecount; /* bytes to transfer */ 207 u_int32_t transfersize; /* bytes pr transfer */ 208 u_int32_t donecount; /* bytes transferred */ 209 caddr_t data; /* pointer to data buf */ 210 int flags; 211 #define ATA_R_CONTROL 0x0001 212 #define ATA_R_READ 0x0002 213 #define ATA_R_WRITE 0x0004 214 #define ATA_R_DMA 0x0008 215 216 #define ATA_R_ATAPI 0x0010 217 #define ATA_R_QUIET 0x0020 218 #define ATA_R_INTR_SEEN 0x0040 219 #define ATA_R_TIMEOUT 0x0080 220 221 #define ATA_R_ORDERED 0x0100 222 #define ATA_R_IMMEDIATE 0x0200 223 #define ATA_R_REQUEUE 0x0400 224 225 #define ATA_R_DEBUG 0x1000 226 227 void (*callback)(struct ata_request *request); 228 struct sema done; /* request done sema */ 229 int retries; /* retry count */ 230 int timeout; /* timeout for this cmd */ 231 struct callout callout; /* callout management */ 232 int result; /* result error code */ 233 struct task task; /* task management */ 234 struct bio *bio; /* bio for this request */ 235 TAILQ_ENTRY(ata_request) sequence; /* sequence management */ 236 TAILQ_ENTRY(ata_request) chain; /* list management */ 237 }; 238 239 /* define this for debugging request processing */ 240 #if 0 241 #define ATA_DEBUG_RQ(request, string) \ 242 { \ 243 if (request->flags & ATA_R_DEBUG) \ 244 ata_prtdev(request->device, "req=%p %s " string "\n", \ 245 request, ata_cmd2str(request)); \ 246 } 247 #else 248 #define ATA_DEBUG_RQ(request, string) 249 #endif 250 251 252 /* structure describing an ATA/ATAPI device */ 253 struct ata_device { 254 struct ata_channel *channel; 255 int unit; /* unit number */ 256 #define ATA_MASTER 0x00 257 #define ATA_SLAVE 0x10 258 259 char *name; /* device name */ 260 struct ata_params *param; /* ata param structure */ 261 void *softc; /* ptr to softc for device */ 262 void (*attach)(struct ata_device *atadev); 263 void (*detach)(struct ata_device *atadev); 264 void (*config)(struct ata_device *atadev); 265 void (*start)(struct ata_device *atadev); 266 int flags; 267 #define ATA_D_USE_CHS 0x0001 268 #define ATA_D_DETACHING 0x0002 269 #define ATA_D_MEDIA_CHANGED 0x0004 270 #define ATA_D_ENC_PRESENT 0x0008 271 272 int cmd; /* last cmd executed */ 273 int mode; /* transfermode */ 274 void (*setmode)(struct ata_device *atadev, int mode); 275 }; 276 277 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 278 struct ata_dma_prdentry { 279 u_int32_t addr; 280 u_int32_t count; 281 }; 282 283 /* structure used by the setprd function */ 284 struct ata_dmasetprd_args { 285 void *dmatab; 286 int error; 287 }; 288 289 /* structure holding DMA related information */ 290 struct ata_dma { 291 bus_dma_tag_t dmatag; /* parent DMA tag */ 292 bus_dma_tag_t cdmatag; /* control DMA tag */ 293 bus_dmamap_t cdmamap; /* control DMA map */ 294 bus_dma_tag_t ddmatag; /* data DMA tag */ 295 bus_dmamap_t ddmamap; /* data DMA map */ 296 void *dmatab; /* DMA transfer table */ 297 bus_addr_t mdmatab; /* bus address of dmatab */ 298 bus_dma_tag_t wdmatag; /* workspace DMA tag */ 299 bus_dmamap_t wdmamap; /* workspace DMA map */ 300 u_int8_t *workspace; /* workspace */ 301 bus_addr_t wdmatab; /* bus address of dmatab */ 302 303 u_int32_t alignment; /* DMA engine alignment */ 304 u_int32_t boundary; /* DMA engine boundary */ 305 u_int32_t max_iosize; /* DMA engine max IO size */ 306 u_int32_t cur_iosize; /* DMA engine current IO size */ 307 int flags; 308 #define ATA_DMA_READ 0x01 /* transaction is a read */ 309 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */ 310 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */ 311 312 void (*alloc)(struct ata_channel *ch); 313 void (*free)(struct ata_channel *ch); 314 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 315 int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir); 316 int (*unload)(struct ata_channel *ch); 317 int (*start)(struct ata_channel *ch); 318 int (*stop)(struct ata_channel *ch); 319 }; 320 321 /* structure holding lowlevel functions */ 322 struct ata_lowlevel { 323 int (*begin_transaction)(struct ata_request *request); 324 int (*end_transaction)(struct ata_request *request); 325 void (*interrupt)(void *channel); 326 void (*reset)(struct ata_channel *ch); 327 int (*command)(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature); 328 }; 329 330 /* structure holding resources for an ATA channel */ 331 struct ata_resource { 332 struct resource *res; 333 int offset; 334 }; 335 336 /* structure describing an ATA channel */ 337 struct ata_channel { 338 struct device *dev; /* device handle */ 339 int unit; /* channel number */ 340 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 341 struct resource *r_irq; /* interrupt of this channel */ 342 void *ih; /* interrupt handle */ 343 struct ata_lowlevel hw; /* lowlevel HW functions */ 344 struct ata_dma *dma; /* DMA data / functions */ 345 int flags; /* channel flags */ 346 #define ATA_NO_SLAVE 0x01 347 #define ATA_USE_16BIT 0x02 348 #define ATA_USE_PC98GEOM 0x04 349 #define ATA_ATAPI_DMA_RO 0x08 350 #define ATA_48BIT_ACTIVE 0x10 351 #define ATA_IMMEDIATE_MODE 0x20 352 #define ATA_HWGONE 0x40 353 354 struct ata_device device[2]; /* devices on this channel */ 355 #define MASTER 0x00 356 #define SLAVE 0x01 357 358 int devices; /* what is present */ 359 #define ATA_ATA_MASTER 0x01 360 #define ATA_ATA_SLAVE 0x02 361 #define ATA_ATAPI_MASTER 0x04 362 #define ATA_ATAPI_SLAVE 0x08 363 364 struct mtx state_mtx; /* state lock */ 365 int state; /* ATA channel state */ 366 #define ATA_IDLE 0x0000 367 #define ATA_ACTIVE 0x0001 368 #define ATA_INTERRUPT 0x0002 369 #define ATA_TIMEOUT 0x0004 370 371 void (*reset)(struct ata_channel *); 372 int (*locking)(struct ata_channel *, int); 373 #define ATA_LF_LOCK 0x0001 374 #define ATA_LF_UNLOCK 0x0002 375 #define ATA_LF_WHICH 0x0004 376 377 struct mtx queue_mtx; /* queue lock */ 378 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 379 struct ata_request *running; /* currently running request */ 380 }; 381 382 /* disk bay/enclosure related */ 383 #define ATA_LED_OFF 0x00 384 #define ATA_LED_RED 0x01 385 #define ATA_LED_GREEN 0x02 386 #define ATA_LED_ORANGE 0x03 387 #define ATA_LED_MASK 0x03 388 389 /* externs */ 390 extern devclass_t ata_devclass; 391 extern int ata_wc; 392 393 /* public prototypes */ 394 /* ata-all.c: */ 395 int ata_probe(device_t dev); 396 int ata_attach(device_t dev); 397 int ata_detach(device_t dev); 398 int ata_suspend(device_t dev); 399 int ata_resume(device_t dev); 400 void ata_udelay(int interval); 401 int ata_printf(struct ata_channel *ch, int device, const char *fmt, ...) __printflike(3, 4); 402 int ata_prtdev(struct ata_device *atadev, const char *fmt, ...) __printflike(2, 3); 403 void ata_set_name(struct ata_device *atadev, char *name, int lun); 404 void ata_free_name(struct ata_device *atadev); 405 int ata_get_lun(u_int32_t *map); 406 int ata_test_lun(u_int32_t *map, int lun); 407 void ata_free_lun(u_int32_t *map, int lun); 408 char *ata_mode2str(int mode); 409 int ata_pmode(struct ata_params *ap); 410 int ata_wmode(struct ata_params *ap); 411 int ata_umode(struct ata_params *ap); 412 int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode); 413 414 /* ata-queue.c: */ 415 int ata_reinit(struct ata_channel *ch); 416 void ata_start(struct ata_channel *ch); 417 int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 418 int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 419 void ata_queue_request(struct ata_request *request); 420 void ata_finish(struct ata_request *request); 421 void ata_catch_inflight(struct ata_channel *ch); 422 void ata_fail_requests(struct ata_channel *ch, struct ata_device *device); 423 char *ata_cmd2str(struct ata_request *request); 424 425 /* ata-lowlevel.c: */ 426 void ata_generic_hw(struct ata_channel *ch); 427 int ata_generic_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature); 428 429 /* subdrivers */ 430 void ad_attach(struct ata_device *atadev); 431 void acd_attach(struct ata_device *atadev); 432 void afd_attach(struct ata_device *atadev); 433 void ast_attach(struct ata_device *atadev); 434 void atapi_cam_attach_bus(struct ata_channel *ch); 435 void atapi_cam_detach_bus(struct ata_channel *ch); 436 void atapi_cam_reinit_bus(struct ata_channel *ch); 437 438 /* macros for alloc/free of ata_requests */ 439 extern uma_zone_t ata_zone; 440 #define ata_alloc_request() uma_zalloc(ata_zone, M_NOWAIT | M_ZERO) 441 #define ata_free_request(request) uma_zfree(ata_zone, request) 442 443 /* macros to hide busspace uglyness */ 444 #define ATA_INB(res, offset) \ 445 bus_space_read_1(rman_get_bustag((res)), \ 446 rman_get_bushandle((res)), (offset)) 447 448 #define ATA_INW(res, offset) \ 449 bus_space_read_2(rman_get_bustag((res)), \ 450 rman_get_bushandle((res)), (offset)) 451 #define ATA_INL(res, offset) \ 452 bus_space_read_4(rman_get_bustag((res)), \ 453 rman_get_bushandle((res)), (offset)) 454 #define ATA_INSW(res, offset, addr, count) \ 455 bus_space_read_multi_2(rman_get_bustag((res)), \ 456 rman_get_bushandle((res)), \ 457 (offset), (addr), (count)) 458 #define ATA_INSW_STRM(res, offset, addr, count) \ 459 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 460 rman_get_bushandle((res)), \ 461 (offset), (addr), (count)) 462 #define ATA_INSL(res, offset, addr, count) \ 463 bus_space_read_multi_4(rman_get_bustag((res)), \ 464 rman_get_bushandle((res)), \ 465 (offset), (addr), (count)) 466 #define ATA_INSL_STRM(res, offset, addr, count) \ 467 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 468 rman_get_bushandle((res)), \ 469 (offset), (addr), (count)) 470 #define ATA_OUTB(res, offset, value) \ 471 bus_space_write_1(rman_get_bustag((res)), \ 472 rman_get_bushandle((res)), (offset), (value)) 473 #define ATA_OUTW(res, offset, value) \ 474 bus_space_write_2(rman_get_bustag((res)), \ 475 rman_get_bushandle((res)), (offset), (value)) 476 #define ATA_OUTL(res, offset, value) \ 477 bus_space_write_4(rman_get_bustag((res)), \ 478 rman_get_bushandle((res)), (offset), (value)) 479 #define ATA_OUTSW(res, offset, addr, count) \ 480 bus_space_write_multi_2(rman_get_bustag((res)), \ 481 rman_get_bushandle((res)), \ 482 (offset), (addr), (count)) 483 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 484 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 485 rman_get_bushandle((res)), \ 486 (offset), (addr), (count)) 487 #define ATA_OUTSL(res, offset, addr, count) \ 488 bus_space_write_multi_4(rman_get_bustag((res)), \ 489 rman_get_bushandle((res)), \ 490 (offset), (addr), (count)) 491 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 492 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 493 rman_get_bushandle((res)), \ 494 (offset), (addr), (count)) 495 496 #define ATA_IDX_INB(ch, idx) \ 497 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 498 499 #define ATA_IDX_INW(ch, idx) \ 500 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 501 502 #define ATA_IDX_INL(ch, idx) \ 503 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 504 505 #define ATA_IDX_INSW(ch, idx, addr, count) \ 506 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 507 508 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 509 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 510 511 #define ATA_IDX_INSL(ch, idx, addr, count) \ 512 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 513 514 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 515 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 516 517 #define ATA_IDX_OUTB(ch, idx, value) \ 518 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 519 520 #define ATA_IDX_OUTW(ch, idx, value) \ 521 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 522 523 #define ATA_IDX_OUTL(ch, idx, value) \ 524 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 525 526 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 527 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 528 529 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 530 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 531 532 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 533 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 534 535 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 536 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
Cache object: 35c550235ce10787be456b9435b717f7
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