Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ata/ata-all.h
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1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/8.4/sys/dev/ata/ata-all.h 247653 2013-03-02 17:32:20Z marius $ 27 */ 28 29 #include "opt_ata.h" 30 31 #if 0 32 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 33 * some modern devices */ 34 #endif 35 36 /* ATA register defines */ 37 #define ATA_DATA 0 /* (RW) data */ 38 39 #define ATA_FEATURE 1 /* (W) feature */ 40 #define ATA_F_DMA 0x01 /* enable DMA */ 41 #define ATA_F_OVL 0x02 /* enable overlap */ 42 43 #define ATA_COUNT 2 /* (W) sector count */ 44 45 #define ATA_SECTOR 3 /* (RW) sector # */ 46 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 47 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 48 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 49 #define ATA_D_LBA 0x40 /* use LBA addressing */ 50 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 51 52 #define ATA_COMMAND 7 /* (W) command */ 53 54 #define ATA_ERROR 8 /* (R) error */ 55 #define ATA_E_ILI 0x01 /* illegal length */ 56 #define ATA_E_NM 0x02 /* no media */ 57 #define ATA_E_ABORT 0x04 /* command aborted */ 58 #define ATA_E_MCR 0x08 /* media change request */ 59 #define ATA_E_IDNF 0x10 /* ID not found */ 60 #define ATA_E_MC 0x20 /* media changed */ 61 #define ATA_E_UNC 0x40 /* uncorrectable data */ 62 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 63 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 64 65 #define ATA_IREASON 9 /* (R) interrupt reason */ 66 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 67 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 68 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 69 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 70 71 #define ATA_STATUS 10 /* (R) status */ 72 #define ATA_ALTSTAT 11 /* (R) alternate status */ 73 #define ATA_S_ERROR 0x01 /* error */ 74 #define ATA_S_INDEX 0x02 /* index */ 75 #define ATA_S_CORR 0x04 /* data corrected */ 76 #define ATA_S_DRQ 0x08 /* data request */ 77 #define ATA_S_DSC 0x10 /* drive seek completed */ 78 #define ATA_S_SERVICE 0x10 /* drive needs service */ 79 #define ATA_S_DWF 0x20 /* drive write fault */ 80 #define ATA_S_DMA 0x20 /* DMA ready */ 81 #define ATA_S_READY 0x40 /* drive ready */ 82 #define ATA_S_BUSY 0x80 /* busy */ 83 84 #define ATA_CONTROL 12 /* (W) control */ 85 86 #define ATA_CTLOFFSET 0x206 /* control register offset */ 87 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 88 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 89 #define ATA_A_IDS 0x02 /* disable interrupts */ 90 #define ATA_A_RESET 0x04 /* RESET controller */ 91 #ifdef ATA_LEGACY_SUPPORT 92 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 93 #else 94 #define ATA_A_4BIT 0x00 95 #endif 96 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 97 98 /* SATA register defines */ 99 #define ATA_SSTATUS 13 100 #define ATA_SS_DET_MASK 0x0000000f 101 #define ATA_SS_DET_NO_DEVICE 0x00000000 102 #define ATA_SS_DET_DEV_PRESENT 0x00000001 103 #define ATA_SS_DET_PHY_ONLINE 0x00000003 104 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 105 106 #define ATA_SS_SPD_MASK 0x000000f0 107 #define ATA_SS_SPD_NO_SPEED 0x00000000 108 #define ATA_SS_SPD_GEN1 0x00000010 109 #define ATA_SS_SPD_GEN2 0x00000020 110 111 #define ATA_SS_IPM_MASK 0x00000f00 112 #define ATA_SS_IPM_NO_DEVICE 0x00000000 113 #define ATA_SS_IPM_ACTIVE 0x00000100 114 #define ATA_SS_IPM_PARTIAL 0x00000200 115 #define ATA_SS_IPM_SLUMBER 0x00000600 116 117 #define ATA_SERROR 14 118 #define ATA_SE_DATA_CORRECTED 0x00000001 119 #define ATA_SE_COMM_CORRECTED 0x00000002 120 #define ATA_SE_DATA_ERR 0x00000100 121 #define ATA_SE_COMM_ERR 0x00000200 122 #define ATA_SE_PROT_ERR 0x00000400 123 #define ATA_SE_HOST_ERR 0x00000800 124 #define ATA_SE_PHY_CHANGED 0x00010000 125 #define ATA_SE_PHY_IERROR 0x00020000 126 #define ATA_SE_COMM_WAKE 0x00040000 127 #define ATA_SE_DECODE_ERR 0x00080000 128 #define ATA_SE_PARITY_ERR 0x00100000 129 #define ATA_SE_CRC_ERR 0x00200000 130 #define ATA_SE_HANDSHAKE_ERR 0x00400000 131 #define ATA_SE_LINKSEQ_ERR 0x00800000 132 #define ATA_SE_TRANSPORT_ERR 0x01000000 133 #define ATA_SE_UNKNOWN_FIS 0x02000000 134 135 #define ATA_SCONTROL 15 136 #define ATA_SC_DET_MASK 0x0000000f 137 #define ATA_SC_DET_IDLE 0x00000000 138 #define ATA_SC_DET_RESET 0x00000001 139 #define ATA_SC_DET_DISABLE 0x00000004 140 141 #define ATA_SC_SPD_MASK 0x000000f0 142 #define ATA_SC_SPD_NO_SPEED 0x00000000 143 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 144 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 145 #define ATA_SC_SPD_SPEED_GEN3 0x00000040 146 147 #define ATA_SC_IPM_MASK 0x00000f00 148 #define ATA_SC_IPM_NONE 0x00000000 149 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 150 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 151 152 #define ATA_SACTIVE 16 153 154 /* SATA AHCI v1.0 register defines */ 155 #define ATA_AHCI_CAP 0x00 156 #define ATA_AHCI_CAP_NPMASK 0x0000001f 157 #define ATA_AHCI_CAP_SXS 0x00000020 158 #define ATA_AHCI_CAP_EMS 0x00000040 159 #define ATA_AHCI_CAP_CCCS 0x00000080 160 #define ATA_AHCI_CAP_NCS 0x00001F00 161 #define ATA_AHCI_CAP_NCS_SHIFT 8 162 #define ATA_AHCI_CAP_PSC 0x00002000 163 #define ATA_AHCI_CAP_SSC 0x00004000 164 #define ATA_AHCI_CAP_PMD 0x00008000 165 #define ATA_AHCI_CAP_FBSS 0x00010000 166 #define ATA_AHCI_CAP_SPM 0x00020000 167 #define ATA_AHCI_CAP_SAM 0x00080000 168 #define ATA_AHCI_CAP_ISS 0x00F00000 169 #define ATA_AHCI_CAP_ISS_SHIFT 20 170 #define ATA_AHCI_CAP_SCLO 0x01000000 171 #define ATA_AHCI_CAP_SAL 0x02000000 172 #define ATA_AHCI_CAP_SALP 0x04000000 173 #define ATA_AHCI_CAP_SSS 0x08000000 174 #define ATA_AHCI_CAP_SMPS 0x10000000 175 #define ATA_AHCI_CAP_SSNTF 0x20000000 176 #define ATA_AHCI_CAP_SNCQ 0x40000000 177 #define ATA_AHCI_CAP_64BIT 0x80000000 178 179 #define ATA_AHCI_GHC 0x04 180 #define ATA_AHCI_GHC_AE 0x80000000 181 #define ATA_AHCI_GHC_IE 0x00000002 182 #define ATA_AHCI_GHC_HR 0x00000001 183 184 #define ATA_AHCI_IS 0x08 185 #define ATA_AHCI_PI 0x0c 186 #define ATA_AHCI_VS 0x10 187 188 #define ATA_AHCI_OFFSET 0x80 189 190 #define ATA_AHCI_P_CLB 0x100 191 #define ATA_AHCI_P_CLBU 0x104 192 #define ATA_AHCI_P_FB 0x108 193 #define ATA_AHCI_P_FBU 0x10c 194 #define ATA_AHCI_P_IS 0x110 195 #define ATA_AHCI_P_IE 0x114 196 #define ATA_AHCI_P_IX_DHR 0x00000001 197 #define ATA_AHCI_P_IX_PS 0x00000002 198 #define ATA_AHCI_P_IX_DS 0x00000004 199 #define ATA_AHCI_P_IX_SDB 0x00000008 200 #define ATA_AHCI_P_IX_UF 0x00000010 201 #define ATA_AHCI_P_IX_DP 0x00000020 202 #define ATA_AHCI_P_IX_PC 0x00000040 203 #define ATA_AHCI_P_IX_DI 0x00000080 204 205 #define ATA_AHCI_P_IX_PRC 0x00400000 206 #define ATA_AHCI_P_IX_IPM 0x00800000 207 #define ATA_AHCI_P_IX_OF 0x01000000 208 #define ATA_AHCI_P_IX_INF 0x04000000 209 #define ATA_AHCI_P_IX_IF 0x08000000 210 #define ATA_AHCI_P_IX_HBD 0x10000000 211 #define ATA_AHCI_P_IX_HBF 0x20000000 212 #define ATA_AHCI_P_IX_TFE 0x40000000 213 #define ATA_AHCI_P_IX_CPD 0x80000000 214 215 #define ATA_AHCI_P_CMD 0x118 216 #define ATA_AHCI_P_CMD_ST 0x00000001 217 #define ATA_AHCI_P_CMD_SUD 0x00000002 218 #define ATA_AHCI_P_CMD_POD 0x00000004 219 #define ATA_AHCI_P_CMD_CLO 0x00000008 220 #define ATA_AHCI_P_CMD_FRE 0x00000010 221 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 222 #define ATA_AHCI_P_CMD_ISS 0x00002000 223 #define ATA_AHCI_P_CMD_FR 0x00004000 224 #define ATA_AHCI_P_CMD_CR 0x00008000 225 #define ATA_AHCI_P_CMD_CPS 0x00010000 226 #define ATA_AHCI_P_CMD_PMA 0x00020000 227 #define ATA_AHCI_P_CMD_HPCP 0x00040000 228 #define ATA_AHCI_P_CMD_ISP 0x00080000 229 #define ATA_AHCI_P_CMD_CPD 0x00100000 230 #define ATA_AHCI_P_CMD_ATAPI 0x01000000 231 #define ATA_AHCI_P_CMD_DLAE 0x02000000 232 #define ATA_AHCI_P_CMD_ALPE 0x04000000 233 #define ATA_AHCI_P_CMD_ASP 0x08000000 234 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 235 #define ATA_AHCI_P_CMD_NOOP 0x00000000 236 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000 237 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000 238 #define ATA_AHCI_P_CMD_SLUMBER 0x60000000 239 240 #define ATA_AHCI_P_TFD 0x120 241 #define ATA_AHCI_P_SIG 0x124 242 #define ATA_AHCI_P_SSTS 0x128 243 #define ATA_AHCI_P_SCTL 0x12c 244 #define ATA_AHCI_P_SERR 0x130 245 #define ATA_AHCI_P_SACT 0x134 246 #define ATA_AHCI_P_CI 0x138 247 #define ATA_AHCI_P_SNTF 0x13C 248 #define ATA_AHCI_P_FBS 0x140 249 250 #define ATA_AHCI_CL_SIZE 32 251 #define ATA_AHCI_CL_OFFSET 0 252 #define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 253 #define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 254 #define ATA_AHCI_CT_SIZE (2176 + 128) 255 256 struct ata_ahci_dma_prd { 257 u_int64_t dba; 258 u_int32_t reserved; 259 u_int32_t dbc; /* 0 based */ 260 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 261 #define ATA_AHCI_PRD_IPC (1<<31) 262 } __packed; 263 264 struct ata_ahci_cmd_tab { 265 u_int8_t cfis[64]; 266 u_int8_t acmd[32]; 267 u_int8_t reserved[32]; 268 #define ATA_AHCI_DMA_ENTRIES 129 269 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 270 } __packed; 271 272 struct ata_ahci_cmd_list { 273 u_int16_t cmd_flags; 274 #define ATA_AHCI_CMD_ATAPI 0x0020 275 #define ATA_AHCI_CMD_WRITE 0x0040 276 #define ATA_AHCI_CMD_PREFETCH 0x0080 277 #define ATA_AHCI_CMD_RESET 0x0100 278 #define ATA_AHCI_CMD_BIST 0x0200 279 #define ATA_AHCI_CMD_CLR_BUSY 0x0400 280 281 u_int16_t prd_length; /* PRD entries */ 282 u_int32_t bytecount; 283 u_int64_t cmd_table_phys; /* 128byte aligned */ 284 } __packed; 285 286 287 /* DMA register defines */ 288 #define ATA_DMA_ENTRIES 256 289 #define ATA_DMA_EOT 0x80000000 290 291 #define ATA_BMCMD_PORT 17 292 #define ATA_BMCMD_START_STOP 0x01 293 #define ATA_BMCMD_WRITE_READ 0x08 294 295 #define ATA_BMDEVSPEC_0 18 296 #define ATA_BMSTAT_PORT 19 297 #define ATA_BMSTAT_ACTIVE 0x01 298 #define ATA_BMSTAT_ERROR 0x02 299 #define ATA_BMSTAT_INTERRUPT 0x04 300 #define ATA_BMSTAT_MASK 0x07 301 #define ATA_BMSTAT_DMA_MASTER 0x20 302 #define ATA_BMSTAT_DMA_SLAVE 0x40 303 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 304 305 #define ATA_BMDEVSPEC_1 20 306 #define ATA_BMDTP_PORT 21 307 308 #define ATA_IDX_ADDR 22 309 #define ATA_IDX_DATA 23 310 #define ATA_MAX_RES 24 311 312 /* misc defines */ 313 #define ATA_PRIMARY 0x1f0 314 #define ATA_SECONDARY 0x170 315 #define ATA_PC98_BANK 0x432 316 #define ATA_IOSIZE 0x08 317 #define ATA_PC98_IOSIZE 0x10 318 #define ATA_CTLIOSIZE 0x01 319 #define ATA_BMIOSIZE 0x08 320 #define ATA_PC98_BANKIOSIZE 0x01 321 #define ATA_IOADDR_RID 0 322 #define ATA_CTLADDR_RID 1 323 #define ATA_BMADDR_RID 0x20 324 #define ATA_PC98_CTLADDR_RID 8 325 #define ATA_PC98_BANKADDR_RID 9 326 #define ATA_IRQ_RID 0 327 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 328 #define ATA_CFA_MAGIC1 0x844A 329 #define ATA_CFA_MAGIC2 0x848A 330 #define ATA_CFA_MAGIC3 0x8400 331 #define ATAPI_MAGIC_LSB 0x14 332 #define ATAPI_MAGIC_MSB 0xeb 333 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 334 #define ATAPI_P_WRITE (ATA_S_DRQ) 335 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 336 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 337 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 338 #define ATAPI_P_ABORT 0 339 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 340 #define ATA_OP_CONTINUES 0 341 #define ATA_OP_FINISHED 1 342 #define ATA_MAX_28BIT_LBA 268435455UL 343 344 #ifndef ATA_REQUEST_TIMEOUT 345 #define ATA_REQUEST_TIMEOUT 10 346 #endif 347 348 /* structure used for composite atomic operations */ 349 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 350 struct ata_composite { 351 struct mtx lock; /* control lock */ 352 u_int32_t rd_needed; /* needed read subdisks */ 353 u_int32_t rd_done; /* done read subdisks */ 354 u_int32_t wr_needed; /* needed write subdisks */ 355 u_int32_t wr_depend; /* write depends on subdisks */ 356 u_int32_t wr_done; /* done write subdisks */ 357 struct ata_request *request[MAX_COMPOSITES]; 358 u_int32_t residual; /* bytes still to transfer */ 359 caddr_t data_1; 360 caddr_t data_2; 361 }; 362 363 /* structure used to queue an ATA/ATAPI request */ 364 struct ata_request { 365 device_t dev; /* device handle */ 366 device_t parent; /* channel handle */ 367 int unit; /* physical unit */ 368 union { 369 struct { 370 u_int8_t command; /* command reg */ 371 u_int16_t feature; /* feature reg */ 372 u_int16_t count; /* count reg */ 373 u_int64_t lba; /* lba reg */ 374 } ata; 375 struct { 376 u_int8_t ccb[16]; /* ATAPI command block */ 377 struct atapi_sense sense; /* ATAPI request sense data */ 378 u_int8_t saved_cmd; /* ATAPI saved command */ 379 } atapi; 380 } u; 381 u_int32_t bytecount; /* bytes to transfer */ 382 u_int32_t transfersize; /* bytes pr transfer */ 383 caddr_t data; /* pointer to data buf */ 384 u_int32_t tag; /* HW tag of this request */ 385 int flags; 386 #define ATA_R_CONTROL 0x00000001 387 #define ATA_R_READ 0x00000002 388 #define ATA_R_WRITE 0x00000004 389 #define ATA_R_ATAPI 0x00000008 390 #define ATA_R_DMA 0x00000010 391 #define ATA_R_QUIET 0x00000020 392 #define ATA_R_TIMEOUT 0x00000040 393 #define ATA_R_48BIT 0x00000080 394 395 #define ATA_R_ORDERED 0x00000100 396 #define ATA_R_AT_HEAD 0x00000200 397 #define ATA_R_REQUEUE 0x00000400 398 #define ATA_R_THREAD 0x00000800 399 #define ATA_R_DIRECT 0x00001000 400 #define ATA_R_NEEDRESULT 0x00002000 401 402 #define ATA_R_ATAPI16 0x00010000 403 #define ATA_R_ATAPI_INTR 0x00020000 404 405 #define ATA_R_DEBUG 0x10000000 406 #define ATA_R_DANGER1 0x20000000 407 #define ATA_R_DANGER2 0x40000000 408 409 struct ata_dmaslot *dma; /* DMA slot of this request */ 410 u_int8_t status; /* ATA status */ 411 u_int8_t error; /* ATA error */ 412 u_int32_t donecount; /* bytes transferred */ 413 int result; /* result error code */ 414 void (*callback)(struct ata_request *request); 415 struct sema done; /* request done sema */ 416 int retries; /* retry count */ 417 int timeout; /* timeout for this cmd */ 418 struct callout callout; /* callout management */ 419 struct task task; /* task management */ 420 struct bio *bio; /* bio for this request */ 421 int this; /* this request ID */ 422 struct ata_composite *composite; /* for composite atomic ops */ 423 void *driver; /* driver specific */ 424 TAILQ_ENTRY(ata_request) chain; /* list management */ 425 #ifdef ATA_CAM 426 union ccb *ccb; 427 #endif 428 }; 429 430 /* define this for debugging request processing */ 431 #if 0 432 #define ATA_DEBUG_RQ(request, string) \ 433 { \ 434 if (request->flags & ATA_R_DEBUG) \ 435 device_printf(request->parent, "req=%p %s " string "\n", \ 436 request, ata_cmd2str(request)); \ 437 } 438 #else 439 #define ATA_DEBUG_RQ(request, string) 440 #endif 441 442 443 /* structure describing an ATA/ATAPI device */ 444 struct ata_device { 445 device_t dev; /* device handle */ 446 int unit; /* physical unit */ 447 #define ATA_MASTER 0x00 448 #define ATA_SLAVE 0x01 449 #define ATA_PM 0x0f 450 451 struct ata_params param; /* ata param structure */ 452 int mode; /* current transfermode */ 453 u_int32_t max_iosize; /* max IO size */ 454 int spindown; /* idle spindown timeout */ 455 struct callout spindown_timer; 456 int spindown_state; 457 int flags; 458 #define ATA_D_USE_CHS 0x0001 459 #define ATA_D_MEDIA_CHANGED 0x0002 460 #define ATA_D_ENC_PRESENT 0x0004 461 }; 462 463 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 464 struct ata_dma_prdentry { 465 u_int32_t addr; 466 u_int32_t count; 467 }; 468 469 /* structure used by the setprd function */ 470 struct ata_dmasetprd_args { 471 void *dmatab; 472 int nsegs; 473 int error; 474 }; 475 476 struct ata_dmaslot { 477 u_int8_t status; /* DMA status */ 478 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 479 bus_dmamap_t sg_map; /* SG list DMA map */ 480 void *sg; /* DMA transfer table */ 481 bus_addr_t sg_bus; /* bus address of dmatab */ 482 bus_dma_tag_t data_tag; /* data DMA tag */ 483 bus_dmamap_t data_map; /* data DMA map */ 484 }; 485 486 /* structure holding DMA related information */ 487 struct ata_dma { 488 bus_dma_tag_t dmatag; /* parent DMA tag */ 489 bus_dma_tag_t work_tag; /* workspace DMA tag */ 490 bus_dmamap_t work_map; /* workspace DMA map */ 491 u_int8_t *work; /* workspace */ 492 bus_addr_t work_bus; /* bus address of dmatab */ 493 494 #define ATA_DMA_SLOTS 1 495 int dma_slots; /* DMA slots allocated */ 496 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 497 u_int32_t alignment; /* DMA SG list alignment */ 498 u_int32_t boundary; /* DMA SG list boundary */ 499 u_int32_t segsize; /* DMA SG list segment size */ 500 u_int32_t max_iosize; /* DMA data max IO size */ 501 u_int64_t max_address; /* highest DMA'able address */ 502 int flags; 503 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 504 505 void (*alloc)(device_t dev); 506 void (*free)(device_t dev); 507 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 508 int (*load)(struct ata_request *request, void *addr, int *nsegs); 509 int (*unload)(struct ata_request *request); 510 int (*start)(struct ata_request *request); 511 int (*stop)(struct ata_request *request); 512 void (*reset)(device_t dev); 513 }; 514 515 /* structure holding lowlevel functions */ 516 struct ata_lowlevel { 517 u_int32_t (*softreset)(device_t dev, int pmport); 518 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 519 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 520 int (*status)(device_t dev); 521 int (*begin_transaction)(struct ata_request *request); 522 int (*end_transaction)(struct ata_request *request); 523 int (*command)(struct ata_request *request); 524 void (*tf_read)(struct ata_request *request); 525 void (*tf_write)(struct ata_request *request); 526 }; 527 528 /* structure holding resources for an ATA channel */ 529 struct ata_resource { 530 struct resource *res; 531 int offset; 532 }; 533 534 #ifdef ATA_CAM 535 struct ata_cam_device { 536 u_int revision; 537 int mode; 538 u_int bytecount; 539 u_int atapi; 540 u_int caps; 541 }; 542 #endif 543 544 /* structure describing an ATA channel */ 545 struct ata_channel { 546 device_t dev; /* device handle */ 547 int unit; /* physical channel */ 548 int attached; /* channel is attached */ 549 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 550 struct resource *r_irq; /* interrupt of this channel */ 551 void *ih; /* interrupt handle */ 552 struct ata_lowlevel hw; /* lowlevel HW functions */ 553 struct ata_dma dma; /* DMA data / functions */ 554 int flags; /* channel flags */ 555 #define ATA_NO_SLAVE 0x01 556 #define ATA_USE_16BIT 0x02 557 #define ATA_ATAPI_DMA_RO 0x04 558 #define ATA_NO_48BIT_DMA 0x08 559 #define ATA_ALWAYS_DMASTAT 0x10 560 #define ATA_CHECKS_CABLE 0x20 561 #define ATA_NO_ATAPI_DMA 0x40 562 #define ATA_SATA 0x80 563 #define ATA_DMA_BEFORE_CMD 0x100 564 #define ATA_KNOWN_PRESENCE 0x200 565 #define ATA_STATUS_IS_LONG 0x400 566 #define ATA_PERIODIC_POLL 0x800 567 568 int pm_level; /* power management level */ 569 int devices; /* what is present */ 570 #define ATA_ATA_MASTER 0x00000001 571 #define ATA_ATA_SLAVE 0x00000002 572 #define ATA_PORTMULTIPLIER 0x00008000 573 #define ATA_ATAPI_MASTER 0x00010000 574 #define ATA_ATAPI_SLAVE 0x00020000 575 576 struct mtx state_mtx; /* state lock */ 577 int state; /* ATA channel state */ 578 #define ATA_IDLE 0x0000 579 #define ATA_ACTIVE 0x0001 580 #define ATA_STALL_QUEUE 0x0002 581 582 struct mtx queue_mtx; /* queue lock */ 583 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 584 struct ata_request *freezepoint; /* composite freezepoint */ 585 struct ata_request *running; /* currently running request */ 586 struct task conntask; /* PHY events handling task */ 587 #ifdef ATA_CAM 588 struct cam_sim *sim; 589 struct cam_path *path; 590 struct ata_cam_device user[16]; /* User-specified settings */ 591 struct ata_cam_device curr[16]; /* Current settings */ 592 int requestsense; /* CCB waiting for SENSE. */ 593 #endif 594 struct callout poll_callout; /* Periodic status poll. */ 595 }; 596 597 /* disk bay/enclosure related */ 598 #define ATA_LED_OFF 0x00 599 #define ATA_LED_RED 0x01 600 #define ATA_LED_GREEN 0x02 601 #define ATA_LED_ORANGE 0x03 602 #define ATA_LED_MASK 0x03 603 604 /* externs */ 605 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 606 extern struct intr_config_hook *ata_delayed_attach; 607 extern devclass_t ata_devclass; 608 extern int ata_wc; 609 extern int ata_setmax; 610 extern int ata_dma_check_80pin; 611 612 /* public prototypes */ 613 /* ata-all.c: */ 614 int ata_probe(device_t dev); 615 int ata_attach(device_t dev); 616 int ata_detach(device_t dev); 617 int ata_reinit(device_t dev); 618 int ata_suspend(device_t dev); 619 int ata_resume(device_t dev); 620 void ata_interrupt(void *data); 621 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 622 int ata_getparam(struct ata_device *atadev, int init); 623 int ata_identify(device_t dev); 624 void ata_default_registers(device_t dev); 625 void ata_modify_if_48bit(struct ata_request *request); 626 void ata_udelay(int interval); 627 const char *ata_unit2str(struct ata_device *atadev); 628 const char *ata_mode2str(int mode); 629 int ata_str2mode(const char *str); 630 const char *ata_satarev2str(int rev); 631 int ata_atapi(device_t dev, int target); 632 int ata_pmode(struct ata_params *ap); 633 int ata_wmode(struct ata_params *ap); 634 int ata_umode(struct ata_params *ap); 635 int ata_limit_mode(device_t dev, int mode, int maxmode); 636 void ata_setmode(device_t dev); 637 void ata_print_cable(device_t dev, u_int8_t *who); 638 int ata_check_80pin(device_t dev, int mode); 639 #ifdef ATA_CAM 640 void ata_cam_begin_transaction(device_t dev, union ccb *ccb); 641 void ata_cam_end_transaction(device_t dev, struct ata_request *request); 642 #endif 643 644 /* ata-queue.c: */ 645 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 646 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 647 void ata_queue_request(struct ata_request *request); 648 void ata_start(device_t dev); 649 void ata_finish(struct ata_request *request); 650 void ata_timeout(struct ata_request *); 651 void ata_catch_inflight(device_t dev); 652 void ata_fail_requests(device_t dev); 653 void ata_drop_requests(device_t dev); 654 const char *ata_cmd2str(struct ata_request *request); 655 656 /* ata-lowlevel.c: */ 657 void ata_generic_hw(device_t dev); 658 int ata_begin_transaction(struct ata_request *); 659 int ata_end_transaction(struct ata_request *); 660 void ata_generic_reset(device_t dev); 661 int ata_generic_command(struct ata_request *request); 662 663 /* ata-dma.c: */ 664 void ata_dmainit(device_t); 665 void ata_dmafini(device_t dev); 666 667 /* ata-sata.c: */ 668 void ata_sata_phy_check_events(device_t dev, int port); 669 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 670 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 671 int ata_sata_phy_reset(device_t dev, int port, int quick); 672 int ata_sata_setmode(device_t dev, int target, int mode); 673 int ata_sata_getrev(device_t dev, int target); 674 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 675 void ata_pm_identify(device_t dev); 676 677 /* macros for alloc/free of struct ata_request */ 678 extern uma_zone_t ata_request_zone; 679 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 680 #define ata_free_request(request) { \ 681 if (!(request->flags & ATA_R_DANGER2)) \ 682 uma_zfree(ata_request_zone, request); \ 683 } 684 685 /* macros for alloc/free of struct ata_composite */ 686 extern uma_zone_t ata_composite_zone; 687 #define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 688 #define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 689 690 MALLOC_DECLARE(M_ATA); 691 692 /* misc newbus defines */ 693 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 694 695 /* macros to hide busspace uglyness */ 696 #define ATA_INB(res, offset) \ 697 bus_read_1((res), (offset)) 698 699 #define ATA_INW(res, offset) \ 700 bus_read_2((res), (offset)) 701 #define ATA_INW_STRM(res, offset) \ 702 bus_read_stream_2((res), (offset)) 703 #define ATA_INL(res, offset) \ 704 bus_read_4((res), (offset)) 705 #define ATA_INSW(res, offset, addr, count) \ 706 bus_read_multi_2((res), (offset), (addr), (count)) 707 #define ATA_INSW_STRM(res, offset, addr, count) \ 708 bus_read_multi_stream_2((res), (offset), (addr), (count)) 709 #define ATA_INSL(res, offset, addr, count) \ 710 bus_read_multi_4((res), (offset), (addr), (count)) 711 #define ATA_INSL_STRM(res, offset, addr, count) \ 712 bus_read_multi_stream_4((res), (offset), (addr), (count)) 713 #define ATA_OUTB(res, offset, value) \ 714 bus_write_1((res), (offset), (value)) 715 #define ATA_OUTW(res, offset, value) \ 716 bus_write_2((res), (offset), (value)) 717 #define ATA_OUTW_STRM(res, offset, value) \ 718 bus_write_stream_2((res), (offset), (value)) 719 #define ATA_OUTL(res, offset, value) \ 720 bus_write_4((res), (offset), (value)) 721 #define ATA_OUTSW(res, offset, addr, count) \ 722 bus_write_multi_2((res), (offset), (addr), (count)) 723 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 724 bus_write_multi_stream_2((res), (offset), (addr), (count)) 725 #define ATA_OUTSL(res, offset, addr, count) \ 726 bus_write_multi_4((res), (offset), (addr), (count)) 727 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 728 bus_write_multi_stream_4((res), (offset), (addr), (count)) 729 730 #define ATA_IDX_INB(ch, idx) \ 731 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 732 733 #define ATA_IDX_INW(ch, idx) \ 734 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 735 736 #define ATA_IDX_INW_STRM(ch, idx) \ 737 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset) 738 739 #define ATA_IDX_INL(ch, idx) \ 740 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 741 742 #define ATA_IDX_INSW(ch, idx, addr, count) \ 743 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 744 745 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 746 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 747 748 #define ATA_IDX_INSL(ch, idx, addr, count) \ 749 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 750 751 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 752 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 753 754 #define ATA_IDX_OUTB(ch, idx, value) \ 755 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 756 757 #define ATA_IDX_OUTW(ch, idx, value) \ 758 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 759 760 #define ATA_IDX_OUTW_STRM(ch, idx, value) \ 761 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value) 762 763 #define ATA_IDX_OUTL(ch, idx, value) \ 764 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 765 766 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 767 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 768 769 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 770 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 771 772 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 773 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 774 775 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 776 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
Cache object: 641fe855ed3f30e34dfa4ae3c53689c0
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