1 /*-
2 * Copyright (c) 1998 - 2004 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_ata.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/ata.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/sema.h>
43 #include <sys/taskqueue.h>
44 #include <vm/uma.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
53
54 /* misc defines */
55 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
56 #define ATAPI_DEVICE(atadev) \
57 ((atadev->unit == ATA_MASTER && \
58 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
59 (atadev->unit == ATA_SLAVE && \
60 atadev->channel->devices & ATA_ATAPI_SLAVE))
61
62 /* local prototypes */
63 static int ata_generic_chipinit(device_t);
64 static void ata_generic_intr(void *);
65 static void ata_generic_setmode(struct ata_device *, int);
66 static int ata_acard_chipinit(device_t);
67 static void ata_acard_intr(void *);
68 static void ata_acard_850_setmode(struct ata_device *, int);
69 static void ata_acard_86X_setmode(struct ata_device *, int);
70 static int ata_ali_chipinit(device_t);
71 static void ata_ali_setmode(struct ata_device *, int);
72 static int ata_amd_chipinit(device_t);
73 static int ata_cyrix_chipinit(device_t);
74 static void ata_cyrix_setmode(struct ata_device *, int);
75 static int ata_cypress_chipinit(device_t);
76 static void ata_cypress_setmode(struct ata_device *, int);
77 static int ata_highpoint_chipinit(device_t);
78 static void ata_highpoint_intr(void *);
79 static void ata_highpoint_setmode(struct ata_device *, int);
80 static int ata_highpoint_check_80pin(struct ata_device *, int);
81 static int ata_intel_chipinit(device_t);
82 static void ata_intel_intr(void *);
83 static void ata_intel_reset(struct ata_channel *);
84 static void ata_intel_old_setmode(struct ata_device *, int);
85 static void ata_intel_new_setmode(struct ata_device *, int);
86 static int ata_ite_chipinit(device_t);
87 static void ata_ite_setmode(struct ata_device *, int);
88 static int ata_national_chipinit(device_t);
89 static void ata_national_setmode(struct ata_device *, int);
90 static int ata_nvidia_chipinit(device_t);
91 static int ata_via_chipinit(device_t);
92 static void ata_via_family_setmode(struct ata_device *, int);
93 static void ata_via_southbridge_fixup(device_t);
94 static int ata_promise_chipinit(device_t);
95 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
96 static void ata_promise_mio_intr(void *);
97 static void ata_promise_sx4_intr(void *);
98 static void ata_promise_mio_dmainit(struct ata_channel *);
99 static void ata_promise_mio_reset(struct ata_channel *ch);
100 static int ata_promise_mio_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
101 static int ata_promise_sx4_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
102 static int ata_promise_apkt(u_int8_t *bytep, struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
103 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
104 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
105 static void ata_promise_tx2_intr(void *);
106 static void ata_promise_old_intr(void *);
107 static void ata_promise_new_dmainit(struct ata_channel *);
108 static void ata_promise_setmode(struct ata_device *, int);
109 static int ata_serverworks_chipinit(device_t);
110 static void ata_serverworks_setmode(struct ata_device *, int);
111 static int ata_sii_chipinit(device_t);
112 static int ata_sii_allocate(device_t, struct ata_channel *);
113 static void ata_sii_reset(struct ata_channel *);
114 static void ata_sii_intr(void *);
115 static void ata_cmd_intr(void *);
116 static void ata_cmd_old_intr(void *);
117 static void ata_sii_setmode(struct ata_device *, int);
118 static void ata_cmd_setmode(struct ata_device *, int);
119 static int ata_sis_chipinit(device_t);
120 static void ata_sis_setmode(struct ata_device *, int);
121 static int ata_check_80pin(struct ata_device *, int);
122 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
123 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
124 static int ata_setup_interrupt(device_t);
125 static int ata_serialize(struct ata_channel *, int);
126 static int ata_mode2idx(int);
127
128 /* generic or unknown ATA chipset init code */
129 int
130 ata_generic_ident(device_t dev)
131 {
132 struct ata_pci_controller *ctlr = device_get_softc(dev);
133
134 device_set_desc(dev, "GENERIC ATA controller");
135 ctlr->chipinit = ata_generic_chipinit;
136 return 0;
137 }
138
139 static int
140 ata_generic_chipinit(device_t dev)
141 {
142 struct ata_pci_controller *ctlr = device_get_softc(dev);
143
144 if (ata_setup_interrupt(dev))
145 return ENXIO;
146 ctlr->setmode = ata_generic_setmode;
147 return 0;
148 }
149
150 static void
151 ata_generic_intr(void *data)
152 {
153 struct ata_pci_controller *ctlr = data;
154 struct ata_channel *ch;
155 int unit;
156
157 /* implement this as a toggle instead to balance load XXX */
158 for (unit = 0; unit < 2; unit++) {
159 if (!(ch = ctlr->interrupt[unit].argument))
160 continue;
161 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
162 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
163
164 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
165 ATA_BMSTAT_INTERRUPT)
166 continue;
167 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
168 DELAY(1);
169 }
170 ctlr->interrupt[unit].function(ch);
171 }
172 }
173
174 static void
175 ata_generic_setmode(struct ata_device *atadev, int mode)
176 {
177 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
178 mode = ata_check_80pin(atadev, mode);
179 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
180 atadev->mode = mode;
181 }
182
183 static void
184 ata_sata_setmode(struct ata_device *atadev, int mode)
185 {
186 /*
187 * if we detect that the device isn't a real SATA device we limit
188 * the transfer mode to UDMA5/ATA100.
189 * this works around the problems some devices has with the
190 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
191 */
192 if (atadev->param->satacapabilities != 0x0000 &&
193 atadev->param->satacapabilities != 0xffff) {
194 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
195 ata_limit_mode(atadev, mode, ATA_UDMA6)))
196 atadev->mode = ATA_SA150;
197 }
198 else {
199 mode = ata_limit_mode(atadev, mode, ATA_UDMA5);
200 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
201 atadev->mode = mode;
202 }
203 }
204
205 /*
206 * Acard chipset support functions
207 */
208 int
209 ata_acard_ident(device_t dev)
210 {
211 struct ata_pci_controller *ctlr = device_get_softc(dev);
212 struct ata_chip_id *idx;
213 static struct ata_chip_id ids[] =
214 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
215 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
216 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
217 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
218 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
219 { 0, 0, 0, 0, 0, 0}};
220 char buffer[64];
221
222 if (!(idx = ata_match_chip(dev, ids)))
223 return ENXIO;
224
225 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
226 device_set_desc_copy(dev, buffer);
227 ctlr->chip = idx;
228 ctlr->chipinit = ata_acard_chipinit;
229 return 0;
230 }
231
232 static int
233 ata_acard_chipinit(device_t dev)
234 {
235 struct ata_pci_controller *ctlr = device_get_softc(dev);
236 int rid = ATA_IRQ_RID;
237
238 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
239 RF_SHAREABLE | RF_ACTIVE))) {
240 device_printf(dev, "unable to map interrupt\n");
241 return ENXIO;
242 }
243 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
244 ata_acard_intr, ctlr, &ctlr->handle))) {
245 device_printf(dev, "unable to setup interrupt\n");
246 return ENXIO;
247 }
248 if (ctlr->chip->cfg1 == ATPOLD) {
249 ctlr->setmode = ata_acard_850_setmode;
250 ctlr->locking = ata_serialize;
251 }
252 else
253 ctlr->setmode = ata_acard_86X_setmode;
254 return 0;
255 }
256
257 static void
258 ata_acard_intr(void *data)
259 {
260 struct ata_pci_controller *ctlr = data;
261 struct ata_channel *ch;
262 int unit;
263
264 /* implement this as a toggle instead to balance load XXX */
265 for (unit = 0; unit < 2; unit++) {
266 if (!(ch = ctlr->interrupt[unit].argument))
267 continue;
268 if (ctlr->chip->cfg1 == ATPOLD && ch->locking(ch, ATA_LF_WHICH) != unit)
269 continue;
270 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
271 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
272
273 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
274 ATA_BMSTAT_INTERRUPT)
275 continue;
276 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
277 DELAY(1);
278 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
279 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
280 DELAY(1);
281 }
282 ctlr->interrupt[unit].function(ch);
283 }
284 }
285
286 static void
287 ata_acard_850_setmode(struct ata_device *atadev, int mode)
288 {
289 device_t parent = device_get_parent(atadev->channel->dev);
290 struct ata_pci_controller *ctlr = device_get_softc(parent);
291 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
292 int error;
293
294 mode = ata_limit_mode(atadev, mode,
295 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
296
297 /* XXX missing WDMA0+1 + PIO modes */
298 if (mode >= ATA_WDMA2) {
299 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
300 if (bootverbose)
301 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
302 (error) ? "FAILURE " : "",
303 ata_mode2str(mode), ctlr->chip->text);
304 if (!error) {
305 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
306
307 reg54 &= ~(0x03 << (devno << 1));
308 if (mode >= ATA_UDMA0)
309 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
310 pci_write_config(parent, 0x54, reg54, 1);
311 pci_write_config(parent, 0x4a, 0xa6, 1);
312 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
313 atadev->mode = mode;
314 return;
315 }
316 }
317 /* we could set PIO mode timings, but we assume the BIOS did that */
318 }
319
320 static void
321 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
322 {
323 device_t parent = device_get_parent(atadev->channel->dev);
324 struct ata_pci_controller *ctlr = device_get_softc(parent);
325 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
326 int error;
327
328
329 mode = ata_limit_mode(atadev, mode,
330 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
331
332 mode = ata_check_80pin(atadev, mode);
333
334 /* XXX missing WDMA0+1 + PIO modes */
335 if (mode >= ATA_WDMA2) {
336 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
337 if (bootverbose)
338 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
339 (error) ? "FAILURE " : "",
340 ata_mode2str(mode), ctlr->chip->text);
341 if (!error) {
342 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
343
344 reg44 &= ~(0x000f << (devno << 2));
345 if (mode >= ATA_UDMA0)
346 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
347 pci_write_config(parent, 0x44, reg44, 2);
348 pci_write_config(parent, 0x4a, 0xa6, 1);
349 pci_write_config(parent, 0x40 + devno, 0x31, 1);
350 atadev->mode = mode;
351 return;
352 }
353 }
354 /* we could set PIO mode timings, but we assume the BIOS did that */
355 }
356
357 /*
358 * Acer Labs Inc (ALI) chipset support functions
359 */
360 int
361 ata_ali_ident(device_t dev)
362 {
363 struct ata_pci_controller *ctlr = device_get_softc(dev);
364 struct ata_chip_id *idx;
365 static struct ata_chip_id ids[] =
366 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
367 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
368 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
369 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
370 { 0, 0, 0, 0, 0, 0}};
371 char buffer[64];
372
373 if (!(idx = ata_match_chip(dev, ids)))
374 return ENXIO;
375
376 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
377 device_set_desc_copy(dev, buffer);
378 ctlr->chip = idx;
379 ctlr->chipinit = ata_ali_chipinit;
380 return 0;
381 }
382
383 static int
384 ata_ali_chipinit(device_t dev)
385 {
386 struct ata_pci_controller *ctlr = device_get_softc(dev);
387
388 if (ata_setup_interrupt(dev))
389 return ENXIO;
390
391 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
392 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
393
394 /* enable cable detection and UDMA support on newer chips */
395 if (ctlr->chip->cfg2 & ALINEW)
396 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
397 ctlr->setmode = ata_ali_setmode;
398 return 0;
399 }
400
401 static void
402 ata_ali_setmode(struct ata_device *atadev, int mode)
403 {
404 device_t parent = device_get_parent(atadev->channel->dev);
405 struct ata_pci_controller *ctlr = device_get_softc(parent);
406 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
407 int error;
408
409 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
410
411 if (ctlr->chip->cfg2 & ALINEW) {
412 if (mode > ATA_UDMA2 &&
413 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
414 ata_prtdev(atadev,
415 "DMA limited to UDMA33, non-ATA66 cable or device\n");
416 mode = ATA_UDMA2;
417 }
418 }
419 else
420 mode = ata_check_80pin(atadev, mode);
421
422 if (ctlr->chip->cfg2 & ALIOLD) {
423 /* doesn't support ATAPI DMA on write */
424 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
425 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
426 atadev->channel->devices & ATA_ATAPI_SLAVE) {
427 /* doesn't support ATAPI DMA on two ATAPI devices */
428 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
429 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
430 }
431 }
432
433 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
434
435 if (bootverbose)
436 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
437 (error) ? "FAILURE " : "",
438 ata_mode2str(mode), ctlr->chip->text);
439 if (!error) {
440 if (mode >= ATA_UDMA0) {
441 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
442 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
443
444 word54 &= ~(0x000f000f << (devno << 2));
445 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
446 pci_write_config(parent, 0x54, word54, 4);
447 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
448 0x00310001, 4);
449 }
450 else {
451 u_int32_t piotimings[] =
452 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
453 0x00310001, 0x00440001, 0x00330001, 0x00310001};
454
455 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
456 ~(0x0008000f << (devno << 2)), 4);
457 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
458 piotimings[ata_mode2idx(mode)], 4);
459 }
460 atadev->mode = mode;
461 }
462 }
463
464 /*
465 * American Micro Devices (AMD) support functions
466 */
467 int
468 ata_amd_ident(device_t dev)
469 {
470 struct ata_pci_controller *ctlr = device_get_softc(dev);
471 struct ata_chip_id *idx;
472 static struct ata_chip_id ids[] =
473 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
474 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
475 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
476 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
477 { 0, 0, 0, 0, 0, 0}};
478 char buffer[64];
479
480 if (!(idx = ata_match_chip(dev, ids)))
481 return ENXIO;
482
483 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
484 device_set_desc_copy(dev, buffer);
485 ctlr->chip = idx;
486 ctlr->chipinit = ata_amd_chipinit;
487 return 0;
488 }
489
490 static int
491 ata_amd_chipinit(device_t dev)
492 {
493 struct ata_pci_controller *ctlr = device_get_softc(dev);
494
495 if (ata_setup_interrupt(dev))
496 return ENXIO;
497
498 /* disable/set prefetch, postwrite */
499 if (ctlr->chip->cfg2 & AMDBUG)
500 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
501 else
502 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
503
504 ctlr->setmode = ata_via_family_setmode;
505 return 0;
506 }
507
508 /*
509 * Cyrix chipset support functions
510 */
511 int
512 ata_cyrix_ident(device_t dev)
513 {
514 struct ata_pci_controller *ctlr = device_get_softc(dev);
515
516 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
517 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
518 ctlr->chipinit = ata_cyrix_chipinit;
519 return 0;
520 }
521 return ENXIO;
522 }
523
524 static int
525 ata_cyrix_chipinit(device_t dev)
526 {
527 struct ata_pci_controller *ctlr = device_get_softc(dev);
528
529 if (ata_setup_interrupt(dev))
530 return ENXIO;
531
532 if (ctlr->r_res1)
533 ctlr->setmode = ata_cyrix_setmode;
534 else
535 ctlr->setmode = ata_generic_setmode;
536 return 0;
537 }
538
539 static void
540 ata_cyrix_setmode(struct ata_device *atadev, int mode)
541 {
542 struct ata_channel *ch = atadev->channel;
543 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
544 u_int32_t piotiming[] =
545 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
546 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
547 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
548 int error;
549
550 atadev->channel->dma->alignment = 16;
551 atadev->channel->dma->max_iosize = 126 * DEV_BSIZE;
552
553 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
554
555 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
556
557 if (bootverbose)
558 ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n",
559 (error) ? "FAILURE " : "", ata_mode2str(mode));
560 if (!error) {
561 if (mode >= ATA_UDMA0) {
562 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
563 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
564 }
565 else if (mode >= ATA_WDMA0) {
566 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
567 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
568 }
569 else {
570 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
571 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
572 }
573 atadev->mode = mode;
574 }
575 }
576
577 /*
578 * Cypress chipset support functions
579 */
580 int
581 ata_cypress_ident(device_t dev)
582 {
583 struct ata_pci_controller *ctlr = device_get_softc(dev);
584
585 /*
586 * the Cypress chip is a mess, it contains two ATA functions, but
587 * both channels are visible on the first one.
588 * simply ignore the second function for now, as the right
589 * solution (ignoring the second channel on the first function)
590 * doesn't work with the crappy ATA interrupt setup on the alpha.
591 */
592 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
593 pci_get_function(dev) == 1 &&
594 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
595 device_set_desc(dev, "Cypress 82C693 ATA controller");
596 ctlr->chipinit = ata_cypress_chipinit;
597 return 0;
598 }
599 return ENXIO;
600 }
601
602 static int
603 ata_cypress_chipinit(device_t dev)
604 {
605 struct ata_pci_controller *ctlr = device_get_softc(dev);
606
607 if (ata_setup_interrupt(dev))
608 return ENXIO;
609
610 ctlr->setmode = ata_cypress_setmode;
611 return 0;
612 }
613
614 static void
615 ata_cypress_setmode(struct ata_device *atadev, int mode)
616 {
617 device_t parent = device_get_parent(atadev->channel->dev);
618 int error;
619
620 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
621
622 /* XXX missing WDMA0+1 + PIO modes */
623 if (mode == ATA_WDMA2) {
624 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
625 if (bootverbose)
626 ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n",
627 error ? "FAILURE " : "");
628 if (!error) {
629 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
630 atadev->mode = mode;
631 return;
632 }
633 }
634 /* we could set PIO mode timings, but we assume the BIOS did that */
635 }
636
637 /*
638 * HighPoint chipset support functions
639 */
640 int
641 ata_highpoint_ident(device_t dev)
642 {
643 struct ata_pci_controller *ctlr = device_get_softc(dev);
644 struct ata_chip_id *idx;
645 static struct ata_chip_id ids[] =
646 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
647 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
648 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
649 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
650 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
651 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
652 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
653 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
654 { 0, 0, 0, 0, 0, 0}};
655 char buffer[64];
656
657 if (!(idx = ata_match_chip(dev, ids)))
658 return ENXIO;
659
660 strcpy(buffer, idx->text);
661 if (idx->cfg1 == HPT374) {
662 if (pci_get_function(dev) == 0)
663 strcat(buffer, " (channel 0+1)");
664 else if (pci_get_function(dev) == 1)
665 strcat(buffer, " (channel 2+3)");
666 }
667 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
668 device_set_desc_copy(dev, buffer);
669 ctlr->chip = idx;
670 ctlr->chipinit = ata_highpoint_chipinit;
671 return 0;
672 }
673
674 static int
675 ata_highpoint_chipinit(device_t dev)
676 {
677 struct ata_pci_controller *ctlr = device_get_softc(dev);
678 int rid = ATA_IRQ_RID;
679
680 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
681 RF_SHAREABLE | RF_ACTIVE))) {
682 device_printf(dev, "unable to map interrupt\n");
683 return ENXIO;
684 }
685 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
686 ata_highpoint_intr, ctlr, &ctlr->handle))) {
687 device_printf(dev, "unable to setup interrupt\n");
688 return ENXIO;
689 }
690
691 if (ctlr->chip->cfg2 == HPTOLD) {
692 /* disable interrupt prediction */
693 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
694 }
695 else {
696 /* disable interrupt prediction */
697 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
698 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
699
700 /* enable interrupts */
701 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
702
703 /* set clocks etc */
704 if (ctlr->chip->cfg1 < HPT372)
705 pci_write_config(dev, 0x5b, 0x22, 1);
706 else
707 pci_write_config(dev, 0x5b,
708 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
709 }
710 ctlr->setmode = ata_highpoint_setmode;
711 return 0;
712 }
713
714 static void
715 ata_highpoint_intr(void *data)
716 {
717 struct ata_pci_controller *ctlr = data;
718 struct ata_channel *ch;
719 int unit;
720
721 /* implement this as a toggle instead to balance load XXX */
722 for (unit = 0; unit < 2; unit++) {
723 if (!(ch = ctlr->interrupt[unit].argument))
724 continue;
725 if (ch->dma) {
726 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
727
728 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
729 ATA_BMSTAT_INTERRUPT)
730 continue;
731 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
732 DELAY(1);
733 }
734 ctlr->interrupt[unit].function(ch);
735 }
736 }
737
738 static void
739 ata_highpoint_setmode(struct ata_device *atadev, int mode)
740 {
741 device_t parent = device_get_parent(atadev->channel->dev);
742 struct ata_pci_controller *ctlr = device_get_softc(parent);
743 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
744 int error;
745 u_int32_t timings33[][4] = {
746 /* HPT366 HPT370 HPT372 HPT374 mode */
747 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
748 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
749 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
750 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
751 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
752 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
753 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
754 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
755 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
756 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
757 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
758 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
759 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
760 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
761 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
762 };
763
764 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
765
766 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
767 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
768
769 mode = ata_highpoint_check_80pin(atadev, mode);
770
771 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
772
773 if (bootverbose)
774 ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n",
775 (error) ? "FAILURE " : "", ata_mode2str(mode));
776 if (!error)
777 pci_write_config(parent, 0x40 + (devno << 2),
778 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
779 atadev->mode = mode;
780 }
781
782 static int
783 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
784 {
785 device_t parent = device_get_parent(atadev->channel->dev);
786 struct ata_pci_controller *ctlr = device_get_softc(parent);
787 u_int8_t reg, val, res;
788
789 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
790 reg = atadev->channel->unit ? 0x57 : 0x53;
791 val = pci_read_config(parent, reg, 1);
792 pci_write_config(parent, reg, val | 0x80, 1);
793 }
794 else {
795 reg = 0x5b;
796 val = pci_read_config(parent, reg, 1);
797 pci_write_config(parent, reg, val & 0xfe, 1);
798 }
799 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
800 pci_write_config(parent, reg, val, 1);
801
802 if (mode > ATA_UDMA2 && res) {
803 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
804 mode = ATA_UDMA2;
805 }
806 return mode;
807 }
808
809 /*
810 * Intel chipset support functions
811 */
812 int
813 ata_intel_ident(device_t dev)
814 {
815 struct ata_pci_controller *ctlr = device_get_softc(dev);
816 struct ata_chip_id *idx;
817 static struct ata_chip_id ids[] =
818 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
819 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
820 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
821 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
822 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
823 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
824 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
825 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
826 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
827 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
828 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
829 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
830 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
831 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
832 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
833 { ATA_I82801EB_S1,0, 0, 0x00, ATA_SA150, "Intel ICH5" },
834 { ATA_I82801EB_R1,0, 0, 0x00, ATA_SA150, "Intel ICH5" },
835 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "Intel 6300ESB" },
836 { ATA_I6300ESB_S1,0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
837 { ATA_I6300ESB_R1,0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
838 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH6" },
839 { ATA_I82801FB_S1,0, 0, 0x00, ATA_SA150, "Intel ICH6" },
840 { ATA_I82801FB_R1,0, 0, 0x00, ATA_SA150, "Intel ICH6" },
841 { ATA_I82801FBM, 0, 0, 0x00, ATA_SA150, "Intel ICH6" },
842 { 0, 0, 0, 0, 0, 0}};
843 char buffer[64];
844
845 if (!(idx = ata_match_chip(dev, ids)))
846 return ENXIO;
847
848 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
849 device_set_desc_copy(dev, buffer);
850 ctlr->chip = idx;
851 ctlr->chipinit = ata_intel_chipinit;
852 return 0;
853 }
854
855 static int
856 ata_intel_chipinit(device_t dev)
857 {
858 struct ata_pci_controller *ctlr = device_get_softc(dev);
859 int rid = ATA_IRQ_RID;
860
861 if (!ata_legacy(dev)) {
862 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
863 RF_SHAREABLE | RF_ACTIVE))) {
864 device_printf(dev, "unable to map interrupt\n");
865 return ENXIO;
866 }
867 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
868 ata_intel_intr, ctlr, &ctlr->handle))) {
869 device_printf(dev, "unable to setup interrupt\n");
870 return ENXIO;
871 }
872 }
873
874 if (ctlr->chip->chipid == ATA_I82371FB) {
875 ctlr->setmode = ata_intel_old_setmode;
876 }
877 else if (ctlr->chip->max_dma < ATA_SA150) {
878 ctlr->setmode = ata_intel_new_setmode;
879 }
880 else {
881 pci_write_config(dev, PCIR_COMMAND,
882 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
883 ctlr->reset = ata_intel_reset;
884 ctlr->setmode = ata_sata_setmode;
885 }
886 return 0;
887 }
888
889 static void
890 ata_intel_intr(void *data)
891 {
892 struct ata_pci_controller *ctlr = data;
893 struct ata_channel *ch;
894 int unit;
895
896 /* implement this as a toggle instead to balance load XXX */
897 for (unit = 0; unit < 2; unit++) {
898 if (!(ch = ctlr->interrupt[unit].argument))
899 continue;
900 if (ch->dma) {
901 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
902
903 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
904 ATA_BMSTAT_INTERRUPT)
905 continue;
906 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
907 DELAY(1);
908 }
909 ctlr->interrupt[unit].function(ch);
910 }
911 }
912
913 static void
914 ata_intel_old_setmode(struct ata_device *atadev, int mode)
915 {
916 /* NOT YET */
917 }
918
919 static void
920 ata_intel_reset(struct ata_channel *ch)
921 {
922 device_t parent = device_get_parent(ch->dev);
923 struct ata_pci_controller *ctlr = device_get_softc(parent);
924 int mask, timeout = 100;
925
926 /* ICH6 has 4 SATA ports as master/slave on 2 channels so deal with pairs */
927 if (ctlr->chip->chipid == ATA_I82801FB_S1 ||
928 ctlr->chip->chipid == ATA_I82801FB_R1 ||
929 ctlr->chip->chipid == ATA_I82801FBM) {
930 mask = (0x0005 << ch->unit);
931 }
932 else {
933 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
934 if (pci_read_config(parent, 0x90, 1) & 0x04)
935 mask = 0x0003;
936 else
937 mask = (0x0001 << ch->unit);
938 }
939 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
940 DELAY(10);
941 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
942
943 while (timeout--) {
944 ata_udelay(10000);
945 if ((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) {
946 ata_udelay(10000);
947 return;
948 }
949 }
950 }
951
952 static void
953 ata_intel_new_setmode(struct ata_device *atadev, int mode)
954 {
955 device_t parent = device_get_parent(atadev->channel->dev);
956 struct ata_pci_controller *ctlr = device_get_softc(parent);
957 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
958 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
959 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
960 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
961 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
962 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
963 u_int32_t mask40 = 0, new40 = 0;
964 u_int8_t mask44 = 0, new44 = 0;
965 int error;
966 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
967 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
968
969 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
970
971 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
972 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
973 mode = ATA_UDMA2;
974 }
975
976 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
977
978 if (bootverbose)
979 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
980 (error) ? "FAILURE " : "",
981 ata_mode2str(mode), ctlr->chip->text);
982 if (error)
983 return;
984
985 if (mode >= ATA_UDMA0) {
986 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
987 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
988 (0x01 + !(mode & 0x01)), 2);
989 }
990 else {
991 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
992 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
993 }
994 reg54 |= 0x0400;
995 if (mode >= ATA_UDMA2)
996 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
997 else
998 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
999
1000 if (mode >= ATA_UDMA5)
1001 pci_write_config(parent, 0x54, reg54 | (0x1000 << devno), 2);
1002 else
1003 pci_write_config(parent, 0x54, reg54 & ~(0x1000 << devno), 2);
1004
1005 reg40 &= ~0x00ff00ff;
1006 reg40 |= 0x40774077;
1007
1008 if (atadev->unit == ATA_MASTER) {
1009 mask40 = 0x3300;
1010 new40 = timings[ata_mode2idx(mode)] << 8;
1011 }
1012 else {
1013 mask44 = 0x0f;
1014 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
1015 (timings[ata_mode2idx(mode)] & 0x03);
1016 }
1017 if (atadev->channel->unit) {
1018 mask40 <<= 16;
1019 new40 <<= 16;
1020 mask44 <<= 4;
1021 new44 <<= 4;
1022 }
1023 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
1024 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
1025
1026 atadev->mode = mode;
1027 }
1028
1029 /*
1030 * Integrated Technology Express Inc. (ITE) chipset support functions
1031 */
1032 int
1033 ata_ite_ident(device_t dev)
1034 {
1035 struct ata_pci_controller *ctlr = device_get_softc(dev);
1036
1037 if (pci_get_devid(dev) == ATA_IT8212F) {
1038 device_set_desc(dev, "ITE IT8212F ATA133 controller");
1039 ctlr->chipinit = ata_ite_chipinit;
1040 return 0;
1041 }
1042 return ENXIO;
1043 }
1044
1045 static int
1046 ata_ite_chipinit(device_t dev)
1047 {
1048 struct ata_pci_controller *ctlr = device_get_softc(dev);
1049
1050 if (ata_setup_interrupt(dev))
1051 return ENXIO;
1052
1053 ctlr->setmode = ata_ite_setmode;
1054
1055 /* set PCI mode and 66Mhz reference clock */
1056 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
1057
1058 /* set default active & recover timings */
1059 pci_write_config(dev, 0x54, 0x31, 1);
1060 pci_write_config(dev, 0x56, 0x31, 1);
1061 return 0;
1062 }
1063
1064 static void
1065 ata_ite_setmode(struct ata_device *atadev, int mode)
1066 {
1067 device_t parent = device_get_parent(atadev->channel->dev);
1068 struct ata_channel *ch = atadev->channel;
1069 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1070 int error;
1071
1072 /* correct the mode for what the HW supports */
1073 mode = ata_limit_mode(atadev, mode, ATA_UDMA6);
1074
1075 /* check the CBLID bits for 80 conductor cable detection */
1076 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x40, 2) &
1077 (ch->unit ? (1<<3) : (1<<2)))) {
1078 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
1079 mode = ATA_UDMA2;
1080 }
1081
1082 /* set the wanted mode on the device */
1083 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1084
1085 if (bootverbose)
1086 ata_prtdev(atadev, "%s setting %s on ITE8212F chip\n",
1087 (error) ? "failed" : "success", ata_mode2str(mode));
1088
1089 /* if the device accepted the mode change, setup the HW accordingly */
1090 if (!error) {
1091 if (mode >= ATA_UDMA0) {
1092 u_int8_t udmatiming[] =
1093 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
1094
1095 /* enable UDMA mode */
1096 pci_write_config(parent, 0x50,
1097 pci_read_config(parent, 0x50, 1) &
1098 ~(1 << (devno + 3)), 1);
1099
1100 /* set UDMA timing */
1101 pci_write_config(parent,
1102 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
1103 udmatiming[mode & ATA_MODE_MASK], 1);
1104 }
1105 else {
1106 u_int8_t chtiming[] =
1107 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
1108
1109 /* disable UDMA mode */
1110 pci_write_config(parent, 0x50,
1111 pci_read_config(parent, 0x50, 1) |
1112 (1 << (devno + 3)), 1);
1113
1114 /* set active and recover timing (shared between master & slave) */
1115 if (pci_read_config(parent, 0x54 + (ch->unit << 2), 1) <
1116 chtiming[ata_mode2idx(mode)])
1117 pci_write_config(parent, 0x54 + (ch->unit << 2),
1118 chtiming[ata_mode2idx(mode)], 1);
1119 }
1120 atadev->mode = mode;
1121 }
1122 }
1123 /*
1124 * National chipset support functions
1125 */
1126 int
1127 ata_national_ident(device_t dev)
1128 {
1129 struct ata_pci_controller *ctlr = device_get_softc(dev);
1130
1131 /* this chip is a clone of the Cyrix chip, bugs and all */
1132 if (pci_get_devid(dev) == ATA_SC1100) {
1133 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
1134 ctlr->chipinit = ata_national_chipinit;
1135 return 0;
1136 }
1137 return ENXIO;
1138 }
1139
1140 static device_t nat_host = NULL;
1141
1142 static int
1143 ata_national_chipinit(device_t dev)
1144 {
1145 struct ata_pci_controller *ctlr = device_get_softc(dev);
1146 device_t *children;
1147 int nchildren, i;
1148
1149 if (ata_setup_interrupt(dev))
1150 return ENXIO;
1151
1152 /* locate the ISA part in the southbridge and enable UDMA33 */
1153 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1154 for (i = 0; i < nchildren; i++) {
1155 if (pci_get_devid(children[i]) == 0x0510100b) {
1156 nat_host = children[i];
1157 break;
1158 }
1159 }
1160 free(children, M_TEMP);
1161 }
1162 ctlr->setmode = ata_national_setmode;
1163 return 0;
1164 }
1165
1166 static void
1167 ata_national_setmode(struct ata_device *atadev, int mode)
1168 {
1169 device_t parent = device_get_parent(atadev->channel->dev);
1170 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1171 u_int32_t piotiming[] =
1172 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1173 0x00803020, 0x20102010, 0x00100010,
1174 0x00100010, 0x00100010, 0x00100010 };
1175 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1176 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1177 int error;
1178
1179 atadev->channel->dma->alignment = 16;
1180 atadev->channel->dma->max_iosize = 126 * DEV_BSIZE;
1181
1182 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
1183
1184 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1185
1186 if (bootverbose)
1187 ata_prtdev(atadev, "%s setting %s on National chip\n",
1188 (error) ? "failed" : "success", ata_mode2str(mode));
1189 if (!error) {
1190 if (mode >= ATA_UDMA0) {
1191 pci_write_config(parent, 0x44 + (devno << 3),
1192 udmatiming[mode & ATA_MODE_MASK], 4);
1193 }
1194 else if (mode >= ATA_WDMA0) {
1195 pci_write_config(parent, 0x44 + (devno << 3),
1196 dmatiming[mode & ATA_MODE_MASK], 4);
1197 }
1198 else {
1199 pci_write_config(parent, 0x44 + (devno << 3),
1200 pci_read_config(parent, 0x44 + (devno << 3), 4) |
1201 0x80000000, 4);
1202 }
1203 pci_write_config(parent, 0x40 + (devno << 3),
1204 piotiming[ata_mode2idx(mode)], 4);
1205 atadev->mode = mode;
1206 }
1207 }
1208
1209 /*
1210 * nVidia chipset support functions
1211 */
1212 int
1213 ata_nvidia_ident(device_t dev)
1214 {
1215 struct ata_pci_controller *ctlr = device_get_softc(dev);
1216 struct ata_chip_id *idx;
1217 static struct ata_chip_id ids[] =
1218 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nVidia nForce" },
1219 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2" },
1220 { ATA_NFORCE2_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2 MCP" },
1221 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
1222 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 Pro" },
1223 { ATA_NFORCE3_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 MCP" },
1224 { ATA_NFORCE4, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce4" },
1225 { 0, 0, 0, 0, 0, 0}};
1226 char buffer[64];
1227
1228 if (!(idx = ata_match_chip(dev, ids)))
1229 return ENXIO;
1230
1231 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1232 device_set_desc_copy(dev, buffer);
1233 ctlr->chip = idx;
1234 ctlr->chipinit = ata_nvidia_chipinit;
1235 return 0;
1236 }
1237
1238 static int
1239 ata_nvidia_chipinit(device_t dev)
1240 {
1241 struct ata_pci_controller *ctlr = device_get_softc(dev);
1242
1243 if (ata_setup_interrupt(dev))
1244 return ENXIO;
1245
1246 /* disable prefetch, postwrite */
1247 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
1248
1249 ctlr->setmode = ata_via_family_setmode;
1250 return 0;
1251 }
1252
1253 /*
1254 * Promise chipset support functions
1255 */
1256 #define ATA_PDC_APKT_OFFSET 0x00000010
1257 #define ATA_PDC_HPKT_OFFSET 0x00000040
1258 #define ATA_PDC_ASG_OFFSET 0x00000080
1259 #define ATA_PDC_LSG_OFFSET 0x000000c0
1260 #define ATA_PDC_HSG_OFFSET 0x00000100
1261 #define ATA_PDC_CHN_OFFSET 0x00000400
1262 #define ATA_PDC_BUF_BASE 0x00400000
1263 #define ATA_PDC_BUF_OFFSET 0x00100000
1264 #define ATA_PDC_MAX_HPKT 8
1265 #define ATA_PDC_WRITE_REG 0x00
1266 #define ATA_PDC_WRITE_CTL 0x0e
1267 #define ATA_PDC_WRITE_END 0x08
1268 #define ATA_PDC_WAIT_NBUSY 0x10
1269 #define ATA_PDC_WAIT_READY 0x18
1270 #define ATA_PDC_1B 0x20
1271 #define ATA_PDC_2B 0x40
1272
1273 struct ata_promise_sx4 {
1274 struct mtx mtx;
1275 u_int32_t array[ATA_PDC_MAX_HPKT];
1276 int head, tail;
1277 int busy;
1278 };
1279
1280 int
1281 ata_promise_ident(device_t dev)
1282 {
1283 struct ata_pci_controller *ctlr = device_get_softc(dev);
1284 struct ata_chip_id *idx;
1285 static struct ata_chip_id ids[] =
1286 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
1287 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
1288 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
1289 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
1290 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
1291 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
1292 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
1293 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
1294 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
1295 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
1296 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
1297 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
1298 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
1299 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
1300 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20371" },
1301 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20375" },
1302 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20376" },
1303 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20377" },
1304 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20378" },
1305 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20379" },
1306 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20571" },
1307 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20575" },
1308 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20579" },
1309 { ATA_PDC20580, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20580" },
1310 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20617" },
1311 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20618" },
1312 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20619" },
1313 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20620" },
1314 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "Promise PDC20621" },
1315 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "Promise PDC20622" },
1316 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "Promise PDC40518" },
1317 { 0, 0, 0, 0, 0, 0}};
1318 char buffer[64];
1319 uintptr_t devid = 0;
1320
1321 if (!(idx = ata_match_chip(dev, ids)))
1322 return ENXIO;
1323
1324 /* if we are on a SuperTrak SX6000 dont attach */
1325 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1326 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1327 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1328 devid == ATA_I960RM)
1329 return ENXIO;
1330
1331 strcpy(buffer, idx->text);
1332
1333 /* if we are on a FastTrak TX4, adjust the interrupt resource */
1334 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1335 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1336 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1337 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
1338 static long start = 0, end = 0;
1339
1340 if (pci_get_slot(dev) == 1) {
1341 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
1342 strcat(buffer, " (channel 0+1)");
1343 }
1344 else if (pci_get_slot(dev) == 2 && start && end) {
1345 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1346 start = end = 0;
1347 strcat(buffer, " (channel 2+3)");
1348 }
1349 else {
1350 start = end = 0;
1351 }
1352 }
1353 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1354 device_set_desc_copy(dev, buffer);
1355 ctlr->chip = idx;
1356 ctlr->chipinit = ata_promise_chipinit;
1357 return 0;
1358 }
1359
1360 static int
1361 ata_promise_chipinit(device_t dev)
1362 {
1363 struct ata_pci_controller *ctlr = device_get_softc(dev);
1364 int rid = ATA_IRQ_RID;
1365
1366 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1367 RF_SHAREABLE | RF_ACTIVE))) {
1368 device_printf(dev, "unable to map interrupt\n");
1369 return ENXIO;
1370 }
1371
1372 if (ctlr->chip->max_dma >= ATA_SA150)
1373 ctlr->setmode = ata_sata_setmode;
1374 else
1375 ctlr->setmode = ata_promise_setmode;
1376
1377 switch (ctlr->chip->cfg1) {
1378 case PRNEW:
1379 /* setup clocks */
1380 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
1381
1382 ctlr->dmainit = ata_promise_new_dmainit;
1383 /* FALLTHROUGH */
1384
1385 case PROLD:
1386 /* enable burst mode */
1387 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
1388
1389 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1390 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1391 device_printf(dev, "unable to setup interrupt\n");
1392 return ENXIO;
1393 }
1394 break;
1395
1396 case PRTX:
1397 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1398 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1399 device_printf(dev, "unable to setup interrupt\n");
1400 return ENXIO;
1401 }
1402 break;
1403
1404 case PRMIO:
1405 // if (ctlr->r_res1)
1406 // bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
1407 ctlr->r_type1 = SYS_RES_MEMORY;
1408 ctlr->r_rid1 = PCIR_BAR(4);
1409 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
1410 &ctlr->r_rid1, RF_ACTIVE)))
1411 return ENXIO;
1412
1413 ctlr->r_type2 = SYS_RES_MEMORY;
1414 ctlr->r_rid2 = PCIR_BAR(3);
1415 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1416 &ctlr->r_rid2, RF_ACTIVE)))
1417 return ENXIO;
1418
1419 ctlr->reset = ata_promise_mio_reset;
1420 ctlr->dmainit = ata_promise_mio_dmainit;
1421 ctlr->allocate = ata_promise_mio_allocate;
1422
1423 switch (ctlr->chip->cfg2) {
1424 case PRPATA:
1425 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
1426 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
1427 break;
1428
1429 case PRCMBO:
1430 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
1431 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 3;
1432 break;
1433
1434 case PRSATA:
1435 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
1436 ctlr->channels = 4;
1437 break;
1438
1439 case PRCMBO2:
1440 ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
1441 ctlr->channels = 3;
1442 break;
1443
1444 case PRSATA2:
1445 ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
1446 ctlr->channels = 4;
1447 break;
1448
1449 case PRSX4X: {
1450 struct ata_promise_sx4 *hpkt;
1451 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
1452
1453 /* print info about cache memory */
1454 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
1455 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
1456 ((dimm >> 24) & 0xff),
1457 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
1458 " ECC enabled" : "" );
1459
1460 ATA_OUTL(ctlr->r_res2, 0x000c000c,
1461 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
1462
1463 ctlr->driver = malloc(sizeof(struct ata_promise_sx4),
1464 M_TEMP, M_NOWAIT | M_ZERO);
1465 hpkt = ctlr->driver;
1466 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
1467 hpkt->busy = hpkt->head = hpkt->tail = 0;
1468
1469 ctlr->channels = 4;
1470
1471 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1472 ata_promise_sx4_intr, ctlr, &ctlr->handle))) {
1473 device_printf(dev, "unable to setup interrupt\n");
1474 return ENXIO;
1475 }
1476 return 0;
1477 }
1478 }
1479
1480 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1481 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1482 device_printf(dev, "unable to setup interrupt\n");
1483 return ENXIO;
1484 }
1485 return 0;
1486 }
1487 return ENXIO;
1488 }
1489
1490 static int
1491 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1492 {
1493 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1494 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
1495 int i;
1496
1497 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1498 ch->r_io[i].res = ctlr->r_res2;
1499 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
1500 }
1501 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
1502 ch->r_io[ATA_ALTSTAT].offset = offset + 0x0238 + (ch->unit << 7);
1503 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1504 ch->flags |= ATA_USE_16BIT;
1505 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
1506 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2))
1507 ch->flags |= ATA_NO_SLAVE;
1508 ata_generic_hw(ch);
1509 if (ctlr->chip->cfg2 & PRSX4X)
1510 ch->hw.command = ata_promise_sx4_command;
1511 else
1512 ch->hw.command = ata_promise_mio_command;
1513 return 0;
1514 }
1515
1516 static void
1517 ata_promise_mio_intr(void *data)
1518 {
1519 struct ata_pci_controller *ctlr = data;
1520 struct ata_channel *ch;
1521 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x00040);
1522 u_int32_t status = 0;
1523 int unit;
1524
1525 if (ctlr->chip->cfg2 & (PRSATA | PRCMBO)) {
1526 status = ATA_INL(ctlr->r_res2, 0x06c);
1527 ATA_OUTL(ctlr->r_res2, 0x06c, status & 0x000000ff);
1528 }
1529 if (ctlr->chip->cfg2 & (PRSATA2 | PRCMBO2)) {
1530 ATA_OUTL(ctlr->r_res2, 0x040, vector & 0x0000ffff);
1531 status = ATA_INL(ctlr->r_res2, 0x060);
1532 ATA_OUTL(ctlr->r_res2, 0x060, status & 0x000000ff);
1533 }
1534 for (unit = 0; unit < ctlr->channels; unit++) {
1535 if (status & (0x00000011 << unit))
1536 if ((ch = ctlr->interrupt[unit].argument))
1537 ata_promise_mio_reset(ch);
1538 if (vector & (1 << (unit + 1)))
1539 if ((ch = ctlr->interrupt[unit].argument))
1540 ctlr->interrupt[unit].function(ch);
1541 }
1542 }
1543
1544 static void
1545 ata_promise_sx4_intr(void *data)
1546 {
1547 struct ata_pci_controller *ctlr = data;
1548 struct ata_channel *ch;
1549 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
1550 int unit;
1551
1552 for (unit = 0; unit < ctlr->channels; unit++) {
1553 if (vector & (1 << (unit + 1)))
1554 if ((ch = ctlr->interrupt[unit].argument))
1555 ctlr->interrupt[unit].function(ch);
1556 if (vector & (1 << (unit + 5)))
1557 if ((ch = ctlr->interrupt[unit].argument))
1558 ata_promise_queue_hpkt(ctlr,
1559 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1560 ATA_PDC_HPKT_OFFSET));
1561 if (vector & (1 << (unit + 9))) {
1562 ata_promise_next_hpkt(ctlr);
1563 if ((ch = ctlr->interrupt[unit].argument))
1564 ctlr->interrupt[unit].function(ch);
1565 }
1566 if (vector & (1 << (unit + 13))) {
1567 ata_promise_next_hpkt(ctlr);
1568 if ((ch = ctlr->interrupt[unit].argument))
1569 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1570 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1571 ATA_PDC_APKT_OFFSET));
1572 }
1573 }
1574 }
1575
1576 static int
1577 ata_promise_mio_dmastart(struct ata_channel *ch)
1578 {
1579 ch->flags |= ATA_DMA_ACTIVE;
1580 return 0;
1581 }
1582
1583 static int
1584 ata_promise_mio_dmastop(struct ata_channel *ch)
1585 {
1586 ch->flags &= ~ATA_DMA_ACTIVE;
1587 /* get status XXX SOS */
1588 return 0;
1589 }
1590
1591 static void
1592 ata_promise_mio_dmainit(struct ata_channel *ch)
1593 {
1594 ata_dmainit(ch);
1595 if (ch->dma) {
1596 ch->dma->start = ata_promise_mio_dmastart;
1597 ch->dma->stop = ata_promise_mio_dmastop;
1598 }
1599 }
1600
1601 static void
1602 ata_promise_mio_reset(struct ata_channel *ch)
1603 {
1604 struct ata_pci_controller *ctlr =
1605 device_get_softc(device_get_parent(ch->dev));
1606
1607 switch (ctlr->chip->cfg2) {
1608 case PRSX4X: {
1609 struct ata_promise_sx4 *hpktp = ctlr->driver;
1610
1611 /* softreset channel ATA module */
1612 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
1613 DELAY(1000);
1614 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
1615 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
1616 ~0x00003f9f) | (ch->unit + 1));
1617
1618 /* softreset HOST module */
1619 mtx_lock(&hpktp->mtx);
1620 ATA_OUTL(ctlr->r_res2, 0xc012c,
1621 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
1622 DELAY(10);
1623 ATA_OUTL(ctlr->r_res2, 0xc012c,
1624 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
1625 mtx_unlock(&hpktp->mtx);
1626 }
1627 break;
1628
1629 case PRCMBO:
1630 case PRCMBO2:
1631 /* softreset channel ATA module */
1632 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
1633 ata_udelay(10000);
1634 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1635 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1636 ~0x00003f9f) | (ch->unit + 1));
1637 break;
1638
1639 case PRSATA: {
1640 u_int32_t status = 0;
1641 int timeout;
1642
1643 /* mask plug/unplug intr */
1644 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
1645
1646 /* softreset channels ATA module */
1647 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
1648 ata_udelay(10000);
1649 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1650 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1651 ~0x00003f9f) | (ch->unit + 1));
1652
1653 /* enable PHY XXX SOS */
1654 /* wait up to 1 sec for "connect well" */
1655 for (timeout = 0; timeout > 1000000 ; timeout += 100) {
1656 status = ATA_INL(ctlr->r_res2, 0x400 + (ch->unit << 8));
1657
1658 if ((status & 0x313) == 0x112)
1659 break;
1660 ata_udelay(10000);
1661 }
1662 if (timeout >= 1000000)
1663 device_printf(ch->dev, "connect status=%08x\n", status);
1664
1665 /* reset and enable plug/unplug intr */
1666 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
1667 }
1668 break;
1669
1670 case PRSATA2: {
1671 u_int32_t status = 0;
1672 int timeout;
1673
1674 /* set portmultiplier port */
1675 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
1676
1677 /* mask plug/unplug intr */
1678 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
1679
1680 /* softreset channels ATA module */
1681 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
1682 ata_udelay(10000);
1683 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1684 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1685 ~0x00003f9f) | (ch->unit + 1));
1686
1687 /* enable PHY XXX SOS */
1688 /* set PHY mode to "improved" */
1689 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
1690 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
1691 ~0x00000003) | 0x00000001);
1692
1693 /* wait up to 1 sec for "connect well" */
1694 for (timeout = 0; timeout > 1000000 ; timeout += 100) {
1695 status = ATA_INL(ctlr->r_res2, 0x400 + (ch->unit << 8));
1696
1697 if ((status & 0x737) == 0x113 || (status & 0x727) == 0x123)
1698 break;
1699 ata_udelay(10000);
1700 }
1701 if (timeout >= 1000000)
1702 device_printf(ch->dev, "connect status=%08x\n", status);
1703
1704 /* reset and enable plug/unplug intr */
1705 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
1706
1707 /* set portmultiplier port */
1708 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
1709 }
1710 break;
1711 }
1712 }
1713
1714 static int
1715 ata_promise_mio_command(struct ata_device *atadev, u_int8_t command,
1716 u_int64_t lba, u_int16_t count, u_int16_t feature)
1717 {
1718 struct ata_pci_controller *ctlr =
1719 device_get_softc(device_get_parent(atadev->channel->dev));
1720 u_int32_t *wordp = (u_int32_t *)atadev->channel->dma->workspace;
1721
1722 ATA_OUTL(ctlr->r_res2, (atadev->channel->unit + 1) << 2, 0x00000001);
1723
1724 switch (command) {
1725 default:
1726 return ata_generic_command(atadev, command, lba, count, feature);
1727
1728 case ATA_READ_DMA:
1729 wordp[0] = htole32(0x04 | ((atadev->channel->unit+1)<<16) | (0x00<<24));
1730 break;
1731
1732 case ATA_WRITE_DMA:
1733 wordp[0] = htole32(0x00 | ((atadev->channel->unit+1)<<16) | (0x00<<24));
1734 break;
1735 }
1736 wordp[1] = htole32(atadev->channel->dma->mdmatab);
1737 wordp[2] = 0;
1738 ata_promise_apkt((u_int8_t*)wordp, atadev, command, lba, count, feature);
1739
1740 ATA_OUTL(ctlr->r_res2, 0x0240 + (atadev->channel->unit << 7),
1741 atadev->channel->dma->wdmatab);
1742 return 0;
1743 }
1744
1745 static int
1746 ata_promise_sx4_command(struct ata_device *atadev, u_int8_t command,
1747 u_int64_t lba, u_int16_t count, u_int16_t feature)
1748 {
1749 struct ata_channel *ch = atadev->channel;
1750 struct ata_dma_prdentry *prd = ch->dma->dmatab;
1751 struct ata_pci_controller *ctlr =
1752 device_get_softc(device_get_parent(ch->dev));
1753 caddr_t window = rman_get_virtual(ctlr->r_res1);
1754 u_int32_t *wordp;
1755 int i, idx, length = 0;
1756
1757 switch (command) {
1758
1759 default:
1760 return -1;
1761
1762 case ATA_ATA_IDENTIFY:
1763 case ATA_READ:
1764 case ATA_READ_MUL:
1765 case ATA_WRITE:
1766 case ATA_WRITE_MUL:
1767 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1768 return ata_generic_command(atadev, command, lba, count, feature);
1769
1770 case ATA_SETFEATURES:
1771 case ATA_FLUSHCACHE:
1772 case ATA_SLEEP:
1773 case ATA_SET_MULTI:
1774 wordp = (u_int32_t *)
1775 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1776 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
1777 wordp[1] = 0;
1778 wordp[2] = 0;
1779 ata_promise_apkt((u_int8_t *)wordp, atadev, command, lba,count,feature);
1780 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1781 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1782 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1783 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
1784 return 0;
1785
1786 case ATA_READ_DMA:
1787 case ATA_WRITE_DMA:
1788 wordp = (u_int32_t *)
1789 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
1790 i = idx = 0;
1791 do {
1792 wordp[idx++] = htole32(prd[i].addr);
1793 wordp[idx++] = htole32(prd[i].count & ~ATA_DMA_EOT);
1794 length += (prd[i].count & ~ATA_DMA_EOT);
1795 } while (!(prd[i++].count & ATA_DMA_EOT));
1796 wordp[idx - 1] |= htole32(ATA_DMA_EOT);
1797
1798 wordp = (u_int32_t *)
1799 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
1800 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1801 wordp[1] = htole32((count * DEV_BSIZE) | ATA_DMA_EOT);
1802
1803 wordp = (u_int32_t *)
1804 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
1805 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1806 wordp[1] = htole32((count * DEV_BSIZE) | ATA_DMA_EOT);
1807
1808 wordp = (u_int32_t *)
1809 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
1810 if (command == ATA_READ_DMA)
1811 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
1812 if (command == ATA_WRITE_DMA)
1813 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
1814 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
1815 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
1816 wordp[3] = 0;
1817
1818 wordp = (u_int32_t *)
1819 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1820 if (command == ATA_READ_DMA)
1821 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
1822 if (command == ATA_WRITE_DMA)
1823 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
1824 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
1825 wordp[2] = 0;
1826 ata_promise_apkt((u_int8_t *)wordp, atadev, command, lba,count,feature);
1827 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1828
1829 if (command == ATA_READ_DMA) {
1830 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
1831 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
1832 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1833 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
1834 }
1835 if (command == ATA_WRITE_DMA) {
1836 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
1837 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
1838 ata_promise_queue_hpkt(ctlr,
1839 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
1840 }
1841 return 0;
1842 }
1843 }
1844
1845 static int
1846 ata_promise_apkt(u_int8_t *bytep, struct ata_device *atadev, u_int8_t command,
1847 u_int64_t lba, u_int16_t count, u_int16_t feature)
1848 {
1849 int i = 12;
1850
1851 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
1852 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
1853 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
1854 bytep[i++] = ATA_A_4BIT;
1855
1856 if ((lba >= ATA_MAX_28BIT_LBA || count > 256) && atadev->param &&
1857 (atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48)) {
1858 atadev->channel->flags |= ATA_48BIT_ACTIVE;
1859 if (command == ATA_READ_DMA)
1860 command = ATA_READ_DMA48;
1861 if (command == ATA_WRITE_DMA)
1862 command = ATA_WRITE_DMA48;
1863 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1864 bytep[i++] = (feature >> 8) & 0xff;
1865 bytep[i++] = feature & 0xff;
1866 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
1867 bytep[i++] = (count >> 8) & 0xff;
1868 bytep[i++] = count & 0xff;
1869 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1870 bytep[i++] = (lba >> 24) & 0xff;
1871 bytep[i++] = lba & 0xff;
1872 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1873 bytep[i++] = (lba >> 32) & 0xff;
1874 bytep[i++] = (lba >> 8) & 0xff;
1875 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1876 bytep[i++] = (lba >> 40) & 0xff;
1877 bytep[i++] = (lba >> 16) & 0xff;
1878 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1879 bytep[i++] = ATA_D_LBA | atadev->unit;
1880 }
1881 else {
1882 atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
1883 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1884 bytep[i++] = feature;
1885 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
1886 bytep[i++] = count;
1887 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1888 bytep[i++] = lba & 0xff;
1889 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1890 bytep[i++] = (lba >> 8) & 0xff;
1891 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1892 bytep[i++] = (lba >> 16) & 0xff;
1893 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1894 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
1895 ATA_D_IBM | atadev->unit | ((lba >> 24) & 0xf);
1896 }
1897 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_CMD;
1898 bytep[i++] = command;
1899 return i;
1900 }
1901
1902 static void
1903 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
1904 {
1905 struct ata_promise_sx4 *hpktp = ctlr->driver;
1906
1907 mtx_lock(&hpktp->mtx);
1908 if (hpktp->tail == hpktp->head && !hpktp->busy) {
1909 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
1910 hpktp->busy = 1;
1911 }
1912 else
1913 hpktp->array[(hpktp->head++) & (ATA_PDC_MAX_HPKT - 1)] = hpkt;
1914 mtx_unlock(&hpktp->mtx);
1915 }
1916
1917 static void
1918 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
1919 {
1920 struct ata_promise_sx4 *hpktp = ctlr->driver;
1921
1922 mtx_lock(&hpktp->mtx);
1923 if (hpktp->tail != hpktp->head) {
1924 ATA_OUTL(ctlr->r_res2, 0x000c0100,
1925 hpktp->array[(hpktp->tail++) & (ATA_PDC_MAX_HPKT - 1)]);
1926 }
1927 else
1928 hpktp->busy = 0;
1929 mtx_unlock(&hpktp->mtx);
1930 }
1931
1932 static void
1933 ata_promise_tx2_intr(void *data)
1934 {
1935 struct ata_pci_controller *ctlr = data;
1936 struct ata_channel *ch;
1937 int unit;
1938
1939 /* implement this as a toggle instead to balance load XXX */
1940 for (unit = 0; unit < 2; unit++) {
1941 if (!(ch = ctlr->interrupt[unit].argument))
1942 continue;
1943 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1944 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1945 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1946 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1947
1948 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1949 ATA_BMSTAT_INTERRUPT)
1950 continue;
1951 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1952 DELAY(1);
1953 }
1954 ctlr->interrupt[unit].function(ch);
1955 }
1956 }
1957 }
1958
1959 static void
1960 ata_promise_old_intr(void *data)
1961 {
1962 struct ata_pci_controller *ctlr = data;
1963 struct ata_channel *ch;
1964 int unit;
1965
1966 /* implement this as a toggle instead to balance load XXX */
1967 for (unit = 0; unit < 2; unit++) {
1968 if (!(ch = ctlr->interrupt[unit].argument))
1969 continue;
1970 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)){
1971 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1972 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1973
1974 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1975 ATA_BMSTAT_INTERRUPT)
1976 continue;
1977 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1978 DELAY(1);
1979 }
1980 ctlr->interrupt[unit].function(ch);
1981 }
1982 }
1983 }
1984
1985 static int
1986 ata_promise_new_dmastart(struct ata_channel *ch)
1987 {
1988 struct ata_pci_controller *ctlr =
1989 device_get_softc(device_get_parent(ch->dev));
1990
1991 if (ch->flags & ATA_48BIT_ACTIVE) {
1992 ATA_OUTB(ctlr->r_res1, 0x11,
1993 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
1994 ATA_OUTL(ctlr->r_res1, 0x20,
1995 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
1996 (ch->dma->cur_iosize >> 1));
1997 }
1998 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1999 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
2000 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
2001 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
2002 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
2003 ATA_BMCMD_START_STOP);
2004 ch->flags |= ATA_DMA_ACTIVE;
2005 return 0;
2006 }
2007
2008 static int
2009 ata_promise_new_dmastop(struct ata_channel *ch)
2010 {
2011 struct ata_pci_controller *ctlr =
2012 device_get_softc(device_get_parent(ch->dev));
2013 int error;
2014
2015 if (ch->flags & ATA_48BIT_ACTIVE) {
2016 ATA_OUTB(ctlr->r_res1, 0x11,
2017 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
2018 ATA_OUTL(ctlr->r_res1, 0x20, 0);
2019 }
2020 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
2021 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
2022 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
2023 ch->flags &= ~ATA_DMA_ACTIVE;
2024 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
2025 return error;
2026 }
2027
2028 static void
2029 ata_promise_new_dmainit(struct ata_channel *ch)
2030 {
2031 ata_dmainit(ch);
2032 if (ch->dma) {
2033 ch->dma->start = ata_promise_new_dmastart;
2034 ch->dma->stop = ata_promise_new_dmastop;
2035 }
2036 }
2037
2038 static void
2039 ata_promise_setmode(struct ata_device *atadev, int mode)
2040 {
2041 device_t parent = device_get_parent(atadev->channel->dev);
2042 struct ata_pci_controller *ctlr = device_get_softc(parent);
2043 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2044 int error;
2045 u_int32_t timings33[][2] = {
2046 /* PROLD PRNEW mode */
2047 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
2048 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
2049 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
2050 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
2051 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
2052 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
2053 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
2054 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
2055 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
2056 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
2057 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
2058 { 0, 0x00424ef6 }, /* UDMA 3 */
2059 { 0, 0x004127f3 }, /* UDMA 4 */
2060 { 0, 0x004127f3 } /* UDMA 5 */
2061 };
2062
2063 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2064
2065 switch (ctlr->chip->cfg1) {
2066 case PROLD:
2067 case PRNEW:
2068 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
2069 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
2070 ata_prtdev(atadev,
2071 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2072 mode = ATA_UDMA2;
2073 }
2074 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
2075 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
2076 break;
2077
2078 case PRTX:
2079 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
2080 if (mode > ATA_UDMA2 &&
2081 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
2082 ata_prtdev(atadev,
2083 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2084 mode = ATA_UDMA2;
2085 }
2086 break;
2087
2088 case PRMIO:
2089 if (mode > ATA_UDMA2 &&
2090 (ATA_INL(ctlr->r_res2,
2091 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
2092 (atadev->channel->unit << 7)) & 0x01000000)) {
2093 ata_prtdev(atadev,
2094 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2095 mode = ATA_UDMA2;
2096 }
2097 break;
2098 }
2099
2100 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2101
2102 if (bootverbose)
2103 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2104 (error) ? "FAILURE " : "",
2105 ata_mode2str(mode), ctlr->chip->text);
2106 if (!error) {
2107 if (ctlr->chip->cfg1 < PRTX)
2108 pci_write_config(parent, 0x60 + (devno << 2),
2109 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
2110 atadev->mode = mode;
2111 }
2112 return;
2113 }
2114
2115 /*
2116 * ServerWorks chipset support functions
2117 */
2118 int
2119 ata_serverworks_ident(device_t dev)
2120 {
2121 struct ata_pci_controller *ctlr = device_get_softc(dev);
2122 struct ata_chip_id *idx;
2123 static struct ata_chip_id ids[] =
2124 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
2125 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
2126 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
2127 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
2128 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
2129 { 0, 0, 0, 0, 0, 0}};
2130 char buffer[64];
2131
2132 if (!(idx = ata_match_chip(dev, ids)))
2133 return ENXIO;
2134
2135 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2136 device_set_desc_copy(dev, buffer);
2137 ctlr->chip = idx;
2138 ctlr->chipinit = ata_serverworks_chipinit;
2139 return 0;
2140 }
2141
2142 static int
2143 ata_serverworks_chipinit(device_t dev)
2144 {
2145 struct ata_pci_controller *ctlr = device_get_softc(dev);
2146
2147 if (ata_setup_interrupt(dev))
2148 return ENXIO;
2149
2150 if (ctlr->chip->cfg1 == SWKS33) {
2151 device_t *children;
2152 int nchildren, i;
2153
2154 /* locate the ISA part in the southbridge and enable UDMA33 */
2155 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
2156 for (i = 0; i < nchildren; i++) {
2157 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
2158 pci_write_config(children[i], 0x64,
2159 (pci_read_config(children[i], 0x64, 4) &
2160 ~0x00002000) | 0x00004000, 4);
2161 break;
2162 }
2163 }
2164 free(children, M_TEMP);
2165 }
2166 }
2167 else {
2168 pci_write_config(dev, 0x5a,
2169 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
2170 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
2171 }
2172 ctlr->setmode = ata_serverworks_setmode;
2173 return 0;
2174 }
2175
2176 static void
2177 ata_serverworks_setmode(struct ata_device *atadev, int mode)
2178 {
2179 device_t parent = device_get_parent(atadev->channel->dev);
2180 struct ata_pci_controller *ctlr = device_get_softc(parent);
2181 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2182 int offset = (devno ^ 0x01) << 3;
2183 int error;
2184 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
2185 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
2186 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
2187
2188 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2189
2190 mode = ata_check_80pin(atadev, mode);
2191
2192 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2193
2194 if (bootverbose)
2195 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2196 (error) ? "FAILURE " : "",
2197 ata_mode2str(mode), ctlr->chip->text);
2198 if (!error) {
2199 if (mode >= ATA_UDMA0) {
2200 pci_write_config(parent, 0x56,
2201 (pci_read_config(parent, 0x56, 2) &
2202 ~(0xf << (devno << 2))) |
2203 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
2204 pci_write_config(parent, 0x54,
2205 pci_read_config(parent, 0x54, 1) |
2206 (0x01 << devno), 1);
2207 pci_write_config(parent, 0x44,
2208 (pci_read_config(parent, 0x44, 4) &
2209 ~(0xff << offset)) |
2210 (dmatimings[2] << offset), 4);
2211 }
2212 else if (mode >= ATA_WDMA0) {
2213 pci_write_config(parent, 0x54,
2214 pci_read_config(parent, 0x54, 1) &
2215 ~(0x01 << devno), 1);
2216 pci_write_config(parent, 0x44,
2217 (pci_read_config(parent, 0x44, 4) &
2218 ~(0xff << offset)) |
2219 (dmatimings[mode & ATA_MODE_MASK] << offset),4);
2220 }
2221 else
2222 pci_write_config(parent, 0x54,
2223 pci_read_config(parent, 0x54, 1) &
2224 ~(0x01 << devno), 1);
2225
2226 pci_write_config(parent, 0x40,
2227 (pci_read_config(parent, 0x40, 4) &
2228 ~(0xff << offset)) |
2229 (piotimings[ata_mode2idx(mode)] << offset), 4);
2230 atadev->mode = mode;
2231 }
2232 }
2233
2234 /*
2235 * Silicon Image (former CMD) chipset support functions
2236 */
2237 int
2238 ata_sii_ident(device_t dev)
2239 {
2240 struct ata_pci_controller *ctlr = device_get_softc(dev);
2241 struct ata_chip_id *idx;
2242 static struct ata_chip_id ids[] =
2243 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
2244 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
2245 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
2246 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
2247 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
2248 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
2249 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
2250 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
2251 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
2252 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
2253 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
2254 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
2255 { 0, 0, 0, 0, 0, 0}};
2256 char buffer[64];
2257
2258 if (!(idx = ata_match_chip(dev, ids)))
2259 return ENXIO;
2260
2261 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2262 device_set_desc_copy(dev, buffer);
2263 ctlr->chip = idx;
2264 ctlr->chipinit = ata_sii_chipinit;
2265 return 0;
2266 }
2267
2268 static int
2269 ata_sii_chipinit(device_t dev)
2270 {
2271 struct ata_pci_controller *ctlr = device_get_softc(dev);
2272 int rid = ATA_IRQ_RID;
2273
2274 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2275 RF_SHAREABLE | RF_ACTIVE))) {
2276 device_printf(dev, "unable to map interrupt\n");
2277 return ENXIO;
2278 }
2279
2280 if (ctlr->chip->cfg1 == SIIMEMIO) {
2281 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2282 ata_sii_intr, ctlr, &ctlr->handle))) {
2283 device_printf(dev, "unable to setup interrupt\n");
2284 return ENXIO;
2285 }
2286
2287 ctlr->r_type2 = SYS_RES_MEMORY;
2288 ctlr->r_rid2 = PCIR_BAR(5);
2289 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2290 &ctlr->r_rid2, RF_ACTIVE)))
2291 return ENXIO;
2292
2293 if (ctlr->chip->cfg2 & SIISETCLK) {
2294 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
2295 pci_write_config(dev, 0x8a,
2296 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
2297 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
2298 device_printf(dev, "%s could not set ATA133 clock\n",
2299 ctlr->chip->text);
2300 }
2301
2302 /* enable interrupt as BIOS might not */
2303 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
2304
2305 if (ctlr->chip->cfg2 & SII4CH) {
2306 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
2307 ctlr->channels = 4;
2308 }
2309
2310 ctlr->allocate = ata_sii_allocate;
2311 if (ctlr->chip->max_dma >= ATA_SA150) {
2312 ctlr->reset = ata_sii_reset;
2313 ctlr->setmode = ata_sata_setmode;
2314 }
2315 else
2316 ctlr->setmode = ata_sii_setmode;
2317 }
2318 else {
2319 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2320 ctlr->chip->cfg2 & SIIINTR ?
2321 ata_cmd_intr : ata_cmd_old_intr,
2322 ctlr, &ctlr->handle))) {
2323 device_printf(dev, "unable to setup interrupt\n");
2324 return ENXIO;
2325 }
2326
2327 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
2328 device_printf(dev, "HW has secondary channel disabled\n");
2329 ctlr->channels = 1;
2330 }
2331
2332 /* enable interrupt as BIOS might not */
2333 pci_write_config(dev, 0x71, 0x01, 1);
2334
2335 ctlr->setmode = ata_cmd_setmode;
2336 }
2337 return 0;
2338 }
2339
2340 static int
2341 ata_sii_allocate(device_t dev, struct ata_channel *ch)
2342 {
2343 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2344 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
2345 int i;
2346
2347 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
2348 ch->r_io[i].res = ctlr->r_res2;
2349 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
2350 }
2351 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
2352 ch->r_io[ATA_ALTSTAT].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
2353 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
2354 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
2355 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
2356 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
2357 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
2358 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
2359 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2;
2360 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8);
2361 ch->r_io[ATA_BMDEVSPEC_1].res = ctlr->r_res2;
2362 ch->r_io[ATA_BMDEVSPEC_1].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
2363 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
2364
2365 if (ctlr->chip->max_dma >= ATA_SA150)
2366 ch->flags |= ATA_NO_SLAVE;
2367
2368 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
2369 ch->dma->boundary = 16 * DEV_BSIZE;
2370 ch->dma->max_iosize = 15 * DEV_BSIZE;
2371 }
2372
2373 ata_generic_hw(ch);
2374
2375 return 0;
2376 }
2377
2378 static void
2379 ata_sii_reset(struct ata_channel *ch)
2380 {
2381 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000001);
2382 DELAY(25000);
2383 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000000);
2384 ata_udelay(1000000);
2385 }
2386
2387 static void
2388 ata_sii_intr(void *data)
2389 {
2390 struct ata_pci_controller *ctlr = data;
2391 struct ata_channel *ch;
2392 int unit;
2393
2394 /* implement this as a toggle instead to balance load XXX */
2395 for (unit = 0; unit < ctlr->channels; unit++) {
2396 if (!(ch = ctlr->interrupt[unit].argument))
2397 continue;
2398 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
2399 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2400 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2401
2402 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
2403 continue;
2404 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2405 DELAY(1);
2406 }
2407 ctlr->interrupt[unit].function(ch);
2408 }
2409 }
2410 }
2411
2412 static void
2413 ata_cmd_intr(void *data)
2414 {
2415 struct ata_pci_controller *ctlr = data;
2416 struct ata_channel *ch;
2417 u_int8_t reg71;
2418 int unit;
2419
2420 /* implement this as a toggle instead to balance load XXX */
2421 for (unit = 0; unit < 2; unit++) {
2422 if (!(ch = ctlr->interrupt[unit].argument))
2423 continue;
2424 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
2425 (ch->unit ? 0x08 : 0x04))) {
2426 pci_write_config(device_get_parent(ch->dev), 0x71,
2427 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
2428 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2429 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2430
2431 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
2432 ATA_BMSTAT_INTERRUPT)
2433 continue;
2434 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2435 DELAY(1);
2436 }
2437 ctlr->interrupt[unit].function(ch);
2438 }
2439 }
2440 }
2441
2442 static void
2443 ata_cmd_old_intr(void *data)
2444 {
2445 struct ata_pci_controller *ctlr = data;
2446 struct ata_channel *ch;
2447 int unit;
2448
2449 /* implement this as a toggle instead to balance load XXX */
2450 for (unit = 0; unit < 2; unit++) {
2451 if (!(ch = ctlr->interrupt[unit].argument))
2452 continue;
2453 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2454 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2455
2456 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
2457 ATA_BMSTAT_INTERRUPT)
2458 continue;
2459 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2460 DELAY(1);
2461 }
2462 ctlr->interrupt[unit].function(ch);
2463 }
2464 }
2465
2466 static void
2467 ata_sii_setmode(struct ata_device *atadev, int mode)
2468 {
2469 device_t parent = device_get_parent(atadev->channel->dev);
2470 struct ata_pci_controller *ctlr = device_get_softc(parent);
2471 int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
2472 int mreg = atadev->channel->unit ? 0x84 : 0x80;
2473 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
2474 int mval = pci_read_config(parent, mreg, 1) & ~mask;
2475 int error;
2476
2477 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2478
2479 if (ctlr->chip->cfg2 & SIISETCLK) {
2480 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
2481 (atadev->channel->unit ? 0x02 : 0x01))) {
2482 ata_prtdev(atadev,
2483 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2484 mode = ATA_UDMA2;
2485 }
2486 }
2487 else
2488 mode = ata_check_80pin(atadev, mode);
2489
2490 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2491
2492 if (bootverbose)
2493 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2494 (error) ? "FAILURE " : "",
2495 ata_mode2str(mode), ctlr->chip->text);
2496 if (error)
2497 return;
2498
2499 if (mode >= ATA_UDMA0) {
2500 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
2501 u_int8_t ureg = 0xac + rego;
2502
2503 pci_write_config(parent, mreg,
2504 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
2505 pci_write_config(parent, ureg,
2506 (pci_read_config(parent, ureg, 1) & ~0x3f) |
2507 udmatimings[mode & ATA_MODE_MASK], 1);
2508
2509 }
2510 else if (mode >= ATA_WDMA0) {
2511 u_int8_t dreg = 0xa8 + rego;
2512 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
2513
2514 pci_write_config(parent, mreg,
2515 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
2516 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
2517
2518 }
2519 else {
2520 u_int8_t preg = 0xa4 + rego;
2521 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
2522
2523 pci_write_config(parent, mreg,
2524 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
2525 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
2526 }
2527 atadev->mode = mode;
2528 }
2529
2530 static void
2531 ata_cmd_setmode(struct ata_device *atadev, int mode)
2532 {
2533 device_t parent = device_get_parent(atadev->channel->dev);
2534 struct ata_pci_controller *ctlr = device_get_softc(parent);
2535 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2536 int error;
2537
2538 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2539
2540 mode = ata_check_80pin(atadev, mode);
2541
2542 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2543
2544 if (bootverbose)
2545 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2546 (error) ? "FAILURE " : "",
2547 ata_mode2str(mode), ctlr->chip->text);
2548 if (!error) {
2549 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
2550 int ureg = atadev->channel->unit ? 0x7b : 0x73;
2551
2552 if (mode >= ATA_UDMA0) {
2553 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
2554 { 0x11, 0x42 }, { 0x25, 0x8a },
2555 { 0x15, 0x4a }, { 0x05, 0x0a } };
2556
2557 u_int8_t umode = pci_read_config(parent, ureg, 1);
2558
2559 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
2560 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
2561 pci_write_config(parent, ureg, umode, 1);
2562 }
2563 else if (mode >= ATA_WDMA0) {
2564 int dmatimings[] = { 0x87, 0x32, 0x3f };
2565
2566 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
2567 pci_write_config(parent, ureg,
2568 pci_read_config(parent, ureg, 1) &
2569 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
2570 }
2571 else {
2572 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
2573 pci_write_config(parent, treg,
2574 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
2575 pci_write_config(parent, ureg,
2576 pci_read_config(parent, ureg, 1) &
2577 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
2578 }
2579 atadev->mode = mode;
2580 }
2581 }
2582
2583 /*
2584 * SiS chipset support functions
2585 */
2586 int
2587 ata_sis_ident(device_t dev)
2588 {
2589 struct ata_pci_controller *ctlr = device_get_softc(dev);
2590 struct ata_chip_id *idx;
2591 static struct ata_chip_id ids[] =
2592 {{ ATA_SIS964_S,0x00, SISSATA, 0, ATA_SA150, "SiS 964" }, /* south */
2593 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 964" }, /* south */
2594 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
2595 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
2596
2597 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
2598 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
2599 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
2600 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
2601
2602 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
2603 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
2604 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
2605 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
2606 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
2607
2608 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
2609 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
2610 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
2611
2612 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "SiS 5513" },
2613 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "SiS 5513" },
2614 { 0, 0, 0, 0, 0, 0 }};
2615 char buffer[64];
2616 int found = 0;
2617
2618 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
2619 return ENXIO;
2620
2621 if (idx->cfg2 && !found) {
2622 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
2623
2624 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
2625 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
2626 found = 1;
2627 idx->cfg1 = SIS133NEW;
2628 idx->max_dma = ATA_UDMA6;
2629 sprintf(buffer, "SiS 962/963 %s controller",
2630 ata_mode2str(idx->max_dma));
2631 }
2632 pci_write_config(dev, 0x57, reg57, 1);
2633 }
2634 if (idx->cfg2 && !found) {
2635 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
2636
2637 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
2638 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
2639 struct ata_chip_id id[] =
2640 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
2641
2642 found = 1;
2643 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
2644 idx->cfg1 = SIS133OLD;
2645 idx->max_dma = ATA_UDMA6;
2646 }
2647 else {
2648 idx->cfg1 = SIS100NEW;
2649 idx->max_dma = ATA_UDMA5;
2650 }
2651 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
2652 }
2653 pci_write_config(dev, 0x4a, reg4a, 1);
2654 }
2655 if (!found)
2656 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
2657
2658 device_set_desc_copy(dev, buffer);
2659 ctlr->chip = idx;
2660 ctlr->chipinit = ata_sis_chipinit;
2661 return 0;
2662 }
2663
2664 static int
2665 ata_sis_chipinit(device_t dev)
2666 {
2667 struct ata_pci_controller *ctlr = device_get_softc(dev);
2668
2669 if (ata_setup_interrupt(dev))
2670 return ENXIO;
2671
2672 switch (ctlr->chip->cfg1) {
2673 case SIS33:
2674 break;
2675 case SIS66:
2676 case SIS100OLD:
2677 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
2678 break;
2679 case SIS100NEW:
2680 case SIS133OLD:
2681 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
2682 break;
2683 case SIS133NEW:
2684 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
2685 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
2686 break;
2687 case SISSATA:
2688 pci_write_config(dev, PCIR_COMMAND,
2689 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2690 ctlr->setmode = ata_sata_setmode;
2691 return 0;
2692 default:
2693 return ENXIO;
2694 }
2695 ctlr->setmode = ata_sis_setmode;
2696 return 0;
2697 }
2698
2699 static void
2700 ata_sis_setmode(struct ata_device *atadev, int mode)
2701 {
2702 device_t parent = device_get_parent(atadev->channel->dev);
2703 struct ata_pci_controller *ctlr = device_get_softc(parent);
2704 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2705 int error;
2706
2707 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2708
2709 if (ctlr->chip->cfg1 == SIS133NEW) {
2710 if (mode > ATA_UDMA2 &&
2711 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
2712 ata_prtdev(atadev,
2713 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2714 mode = ATA_UDMA2;
2715 }
2716 }
2717 else {
2718 if (mode > ATA_UDMA2 &&
2719 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
2720 ata_prtdev(atadev,
2721 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2722 mode = ATA_UDMA2;
2723 }
2724 }
2725
2726 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2727
2728 if (bootverbose)
2729 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2730 (error) ? "FAILURE " : "",
2731 ata_mode2str(mode), ctlr->chip->text);
2732 if (!error) {
2733 switch (ctlr->chip->cfg1) {
2734 case SIS133NEW: {
2735 u_int32_t timings[] =
2736 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
2737 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
2738 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
2739 u_int32_t reg;
2740
2741 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
2742 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
2743 break;
2744 }
2745 case SIS133OLD: {
2746 u_int16_t timings[] =
2747 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
2748 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
2749
2750 u_int16_t reg = 0x40 + (devno << 1);
2751
2752 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2753 break;
2754 }
2755 case SIS100NEW: {
2756 u_int16_t timings[] =
2757 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
2758 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2759 u_int16_t reg = 0x40 + (devno << 1);
2760
2761 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2762 break;
2763 }
2764 case SIS100OLD:
2765 case SIS66:
2766 case SIS33: {
2767 u_int16_t timings[] =
2768 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
2769 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
2770 u_int16_t reg = 0x40 + (devno << 1);
2771
2772 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2773 break;
2774 }
2775 }
2776 atadev->mode = mode;
2777 }
2778 }
2779
2780 /* VIA chipsets */
2781 int
2782 ata_via_ident(device_t dev)
2783 {
2784 struct ata_pci_controller *ctlr = device_get_softc(dev);
2785 struct ata_chip_id *idx;
2786 static struct ata_chip_id ids[] =
2787 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
2788 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
2789 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
2790 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
2791 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
2792 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
2793 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
2794 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
2795 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
2796 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
2797 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
2798 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
2799 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
2800 { 0, 0, 0, 0, 0, 0 }};
2801 static struct ata_chip_id new_ids[] =
2802 {{ ATA_VIA6410, 0x00, 0x00, 0x00, ATA_UDMA6, "VIA 6410" },
2803 { ATA_VIA6420, 0x00, 0x00, 0x00, ATA_SA150, "VIA 6420" },
2804 { 0, 0, 0, 0, 0, 0 }};
2805 char buffer[64];
2806
2807 if (pci_get_devid(dev) == ATA_VIA82C571) {
2808 if (!(idx = ata_find_chip(dev, ids, -99)))
2809 return ENXIO;
2810 }
2811 else {
2812 if (!(idx = ata_match_chip(dev, new_ids)))
2813 return ENXIO;
2814 }
2815
2816 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2817 device_set_desc_copy(dev, buffer);
2818 ctlr->chip = idx;
2819 ctlr->chipinit = ata_via_chipinit;
2820 return 0;
2821 }
2822
2823 static int
2824 ata_via_chipinit(device_t dev)
2825 {
2826 struct ata_pci_controller *ctlr = device_get_softc(dev);
2827
2828 if (ata_setup_interrupt(dev))
2829 return ENXIO;
2830
2831 if (ctlr->chip->max_dma >= ATA_SA150) {
2832 pci_write_config(dev, PCIR_COMMAND,
2833 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2834 ctlr->setmode = ata_sata_setmode;
2835 return 0;
2836 }
2837
2838 /* prepare for ATA-66 on the 82C686a and 82C596b */
2839 if (ctlr->chip->cfg2 & VIACLK)
2840 pci_write_config(dev, 0x50, 0x030b030b, 4);
2841
2842 /* the southbridge might need the data corruption fix */
2843 if (ctlr->chip->cfg2 & VIABUG)
2844 ata_via_southbridge_fixup(dev);
2845
2846 /* set fifo configuration half'n'half */
2847 pci_write_config(dev, 0x43,
2848 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
2849
2850 /* set status register read retry */
2851 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
2852
2853 /* set DMA read & end-of-sector fifo flush */
2854 pci_write_config(dev, 0x46,
2855 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
2856
2857 /* set sector size */
2858 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
2859 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
2860
2861 ctlr->setmode = ata_via_family_setmode;
2862 return 0;
2863 }
2864
2865 static void
2866 ata_via_southbridge_fixup(device_t dev)
2867 {
2868 device_t *children;
2869 int nchildren, i;
2870
2871 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2872 return;
2873
2874 for (i = 0; i < nchildren; i++) {
2875 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
2876 pci_get_devid(children[i]) == ATA_VIA8371 ||
2877 pci_get_devid(children[i]) == ATA_VIA8662 ||
2878 pci_get_devid(children[i]) == ATA_VIA8361) {
2879 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
2880
2881 if ((reg76 & 0xf0) != 0xd0) {
2882 device_printf(dev,
2883 "Correcting VIA config for southbridge data corruption bug\n");
2884 pci_write_config(children[i], 0x75, 0x80, 1);
2885 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
2886 }
2887 break;
2888 }
2889 }
2890 free(children, M_TEMP);
2891 }
2892
2893 /* common code for VIA, AMD & nVidia */
2894 static void
2895 ata_via_family_setmode(struct ata_device *atadev, int mode)
2896 {
2897 device_t parent = device_get_parent(atadev->channel->dev);
2898 struct ata_pci_controller *ctlr = device_get_softc(parent);
2899 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
2900 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
2901 int modes[][7] = {
2902 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2903 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2904 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2905 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
2906 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
2907 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2908 int reg = 0x53 - devno;
2909 int error;
2910
2911 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2912
2913 if (ctlr->chip->cfg2 & AMDCABLE) {
2914 if (mode > ATA_UDMA2 &&
2915 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
2916 ata_prtdev(atadev,
2917 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2918 mode = ATA_UDMA2;
2919 }
2920 }
2921 else
2922 mode = ata_check_80pin(atadev, mode);
2923
2924 if (ctlr->chip->cfg2 & NVIDIA)
2925 reg += 0x10;
2926
2927 if (ctlr->chip->cfg1 != VIA133)
2928 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
2929
2930 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2931
2932 if (bootverbose)
2933 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2934 (error) ? "FAILURE " : "", ata_mode2str(mode),
2935 ctlr->chip->text);
2936 if (!error) {
2937 if (mode >= ATA_UDMA0)
2938 pci_write_config(parent, reg,
2939 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2940 else
2941 pci_write_config(parent, reg, 0x8b, 1);
2942 atadev->mode = mode;
2943 }
2944 }
2945
2946 /* misc functions */
2947 static struct ata_chip_id *
2948 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2949 {
2950 device_t *children;
2951 int nchildren, i;
2952
2953 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2954 return 0;
2955
2956 while (index->chipid != 0) {
2957 for (i = 0; i < nchildren; i++) {
2958 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
2959 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
2960 pci_get_devid(children[i]) == index->chipid &&
2961 pci_get_revid(children[i]) >= index->chiprev) {
2962 free(children, M_TEMP);
2963 return index;
2964 }
2965 }
2966 index++;
2967 }
2968 free(children, M_TEMP);
2969 return NULL;
2970 }
2971
2972 static struct ata_chip_id *
2973 ata_match_chip(device_t dev, struct ata_chip_id *index)
2974 {
2975 while (index->chipid != 0) {
2976 if (pci_get_devid(dev) == index->chipid &&
2977 pci_get_revid(dev) >= index->chiprev)
2978 return index;
2979 index++;
2980 }
2981 return NULL;
2982 }
2983
2984 static int
2985 ata_setup_interrupt(device_t dev)
2986 {
2987 struct ata_pci_controller *ctlr = device_get_softc(dev);
2988 int rid = ATA_IRQ_RID;
2989
2990 if (!ata_legacy(dev)) {
2991 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2992 RF_SHAREABLE | RF_ACTIVE))) {
2993 device_printf(dev, "unable to map interrupt\n");
2994 return ENXIO;
2995 }
2996 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2997 ata_generic_intr, ctlr, &ctlr->handle))) {
2998 device_printf(dev, "unable to setup interrupt\n");
2999 return ENXIO;
3000 }
3001 }
3002 return 0;
3003 }
3004
3005 struct ata_serialize {
3006 struct mtx locked_mtx;
3007 int locked_ch;
3008 int restart_ch;
3009 };
3010
3011 static int
3012 ata_serialize(struct ata_channel *ch, int flags)
3013 {
3014 struct ata_pci_controller *ctlr =
3015 device_get_softc(device_get_parent(ch->dev));
3016 struct ata_serialize *serial;
3017 static int inited = 0;
3018 int res;
3019
3020 if (!inited) {
3021 ctlr->driver = malloc(sizeof(struct ata_serialize),
3022 M_TEMP, M_NOWAIT | M_ZERO);
3023 serial = ctlr->driver;
3024 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
3025 serial->locked_ch = -1;
3026 serial->restart_ch = -1;
3027 inited = 1;
3028 }
3029 else
3030 serial = ctlr->driver;
3031
3032 mtx_lock(&serial->locked_mtx);
3033 switch (flags) {
3034 case ATA_LF_LOCK:
3035 if (serial->locked_ch == -1)
3036 serial->locked_ch = ch->unit;
3037 if (serial->locked_ch != ch->unit)
3038 serial->restart_ch = ch->unit;
3039 break;
3040
3041 case ATA_LF_UNLOCK:
3042 if (serial->locked_ch == ch->unit) {
3043 serial->locked_ch = -1;
3044 if (serial->restart_ch != -1) {
3045 if (ctlr->interrupt[serial->restart_ch].argument) {
3046 mtx_unlock(&serial->locked_mtx);
3047 ata_start(ctlr->interrupt[serial->restart_ch].argument);
3048 mtx_lock(&serial->locked_mtx);
3049 }
3050 serial->restart_ch = -1;
3051 }
3052 }
3053 break;
3054
3055 case ATA_LF_WHICH:
3056 break;
3057 }
3058 res = serial->locked_ch;
3059 mtx_unlock(&serial->locked_mtx);
3060 return res;
3061 }
3062
3063 static int
3064 ata_check_80pin(struct ata_device *atadev, int mode)
3065 {
3066 if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) {
3067 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
3068 mode = ATA_UDMA2;
3069 }
3070 return mode;
3071 }
3072
3073 static int
3074 ata_mode2idx(int mode)
3075 {
3076 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
3077 return (mode & ATA_MODE_MASK) + 8;
3078 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
3079 return (mode & ATA_MODE_MASK) + 5;
3080 return (mode & ATA_MODE_MASK) - ATA_PIO0;
3081 }
Cache object: 8db50eb16ff93d5ea345b3e832610910
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