The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ata/ata-chipset.c

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    1 /*-
    2  * Copyright (c) 1998 - 2007 Søren Schmidt <sos@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer,
   10  *    without modification, immediately at the beginning of the file.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD$");
   29 
   30 #include "opt_ata.h"
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/kernel.h>
   34 #include <sys/ata.h>
   35 #include <sys/bus.h>
   36 #include <sys/endian.h>
   37 #include <sys/malloc.h>
   38 #include <sys/lock.h>
   39 #include <sys/mutex.h>
   40 #include <sys/sema.h>
   41 #include <sys/taskqueue.h>
   42 #include <vm/uma.h>
   43 #include <machine/stdarg.h>
   44 #include <machine/resource.h>
   45 #include <machine/bus.h>
   46 #include <sys/rman.h>
   47 #include <dev/pci/pcivar.h>
   48 #include <dev/pci/pcireg.h>
   49 #include <dev/ata/ata-all.h>
   50 #include <dev/ata/ata-pci.h>
   51 #include <ata_if.h>
   52 
   53 /* local prototypes */
   54 /* ata-chipset.c */
   55 static int ata_generic_chipinit(device_t dev);
   56 static void ata_generic_intr(void *data);
   57 static void ata_generic_setmode(device_t dev, int mode);
   58 static void ata_sata_phy_check_events(device_t dev);
   59 static void ata_sata_phy_event(void *context, int dummy);
   60 static int ata_sata_phy_reset(device_t dev);
   61 static int ata_sata_connect(struct ata_channel *ch);
   62 static void ata_sata_setmode(device_t dev, int mode);
   63 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
   64 static int ata_ahci_chipinit(device_t dev);
   65 static int ata_ahci_allocate(device_t dev);
   66 static int ata_ahci_status(device_t dev);
   67 static int ata_ahci_begin_transaction(struct ata_request *request);
   68 static int ata_ahci_end_transaction(struct ata_request *request);
   69 static void ata_ahci_reset(device_t dev);
   70 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
   71 static void ata_ahci_dmainit(device_t dev);
   72 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
   73 static int ata_acard_chipinit(device_t dev);
   74 static int ata_acard_allocate(device_t dev);
   75 static int ata_acard_status(device_t dev);
   76 static void ata_acard_850_setmode(device_t dev, int mode);
   77 static void ata_acard_86X_setmode(device_t dev, int mode);
   78 static int ata_ali_chipinit(device_t dev);
   79 static int ata_ali_allocate(device_t dev);
   80 static int ata_ali_sata_allocate(device_t dev);
   81 static void ata_ali_reset(device_t dev);
   82 static void ata_ali_setmode(device_t dev, int mode);
   83 static int ata_amd_chipinit(device_t dev);
   84 static int ata_ati_chipinit(device_t dev);
   85 static void ata_ati_setmode(device_t dev, int mode);
   86 static int ata_cyrix_chipinit(device_t dev);
   87 static void ata_cyrix_setmode(device_t dev, int mode);
   88 static int ata_cypress_chipinit(device_t dev);
   89 static void ata_cypress_setmode(device_t dev, int mode);
   90 static int ata_highpoint_chipinit(device_t dev);
   91 static int ata_highpoint_allocate(device_t dev);
   92 static void ata_highpoint_setmode(device_t dev, int mode);
   93 static int ata_highpoint_check_80pin(device_t dev, int mode);
   94 static int ata_intel_chipinit(device_t dev);
   95 static int ata_intel_allocate(device_t dev);
   96 static void ata_intel_reset(device_t dev);
   97 static void ata_intel_old_setmode(device_t dev, int mode);
   98 static void ata_intel_new_setmode(device_t dev, int mode);
   99 static void ata_intel_sata_setmode(device_t dev, int mode);
  100 static int ata_intel_31244_allocate(device_t dev);
  101 static int ata_intel_31244_status(device_t dev);
  102 static void ata_intel_31244_tf_write(struct ata_request *request);
  103 static void ata_intel_31244_reset(device_t dev);
  104 static int ata_ite_chipinit(device_t dev);
  105 static void ata_ite_8213_setmode(device_t dev, int mode);
  106 static void ata_ite_821x_setmode(device_t dev, int mode);
  107 static int ata_jmicron_chipinit(device_t dev);
  108 static int ata_jmicron_allocate(device_t dev);
  109 static void ata_jmicron_reset(device_t dev);
  110 static void ata_jmicron_dmainit(device_t dev);
  111 static void ata_jmicron_setmode(device_t dev, int mode);
  112 static int ata_marvell_pata_chipinit(device_t dev);
  113 static int ata_marvell_pata_allocate(device_t dev);
  114 static void ata_marvell_pata_setmode(device_t dev, int mode);
  115 static int ata_marvell_edma_chipinit(device_t dev);
  116 static int ata_marvell_edma_allocate(device_t dev);
  117 static int ata_marvell_edma_status(device_t dev);
  118 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
  119 static int ata_marvell_edma_end_transaction(struct ata_request *request);
  120 static void ata_marvell_edma_reset(device_t dev);
  121 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
  122 static void ata_marvell_edma_dmainit(device_t dev);
  123 static int ata_national_chipinit(device_t dev);
  124 static void ata_national_setmode(device_t dev, int mode);
  125 static int ata_netcell_chipinit(device_t dev);
  126 static int ata_netcell_allocate(device_t dev);
  127 static int ata_nvidia_chipinit(device_t dev);
  128 static int ata_nvidia_allocate(device_t dev);
  129 static int ata_nvidia_status(device_t dev);
  130 static void ata_nvidia_reset(device_t dev);
  131 static int ata_promise_chipinit(device_t dev);
  132 static int ata_promise_allocate(device_t dev);
  133 static int ata_promise_status(device_t dev);
  134 static int ata_promise_dmastart(device_t dev);
  135 static int ata_promise_dmastop(device_t dev);
  136 static void ata_promise_dmareset(device_t dev);
  137 static void ata_promise_dmainit(device_t dev);
  138 static void ata_promise_setmode(device_t dev, int mode);
  139 static int ata_promise_tx2_allocate(device_t dev);
  140 static int ata_promise_tx2_status(device_t dev);
  141 static int ata_promise_mio_allocate(device_t dev);
  142 static void ata_promise_mio_intr(void *data);
  143 static int ata_promise_mio_status(device_t dev);
  144 static int ata_promise_mio_command(struct ata_request *request);
  145 static void ata_promise_mio_reset(device_t dev);
  146 static void ata_promise_mio_dmainit(device_t dev);
  147 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
  148 static void ata_promise_mio_setmode(device_t dev, int mode);
  149 static void ata_promise_sx4_intr(void *data);
  150 static int ata_promise_sx4_command(struct ata_request *request);
  151 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
  152 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
  153 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
  154 static int ata_serverworks_chipinit(device_t dev);
  155 static int ata_serverworks_allocate(device_t dev);
  156 static void ata_serverworks_tf_read(struct ata_request *request);
  157 static void ata_serverworks_tf_write(struct ata_request *request);
  158 static void ata_serverworks_setmode(device_t dev, int mode);
  159 static int ata_sii_chipinit(device_t dev);
  160 static int ata_cmd_allocate(device_t dev);
  161 static int ata_cmd_status(device_t dev);
  162 static void ata_cmd_setmode(device_t dev, int mode);
  163 static int ata_sii_allocate(device_t dev);
  164 static int ata_sii_status(device_t dev);
  165 static void ata_sii_reset(device_t dev);
  166 static void ata_sii_setmode(device_t dev, int mode);
  167 static int ata_siiprb_allocate(device_t dev);
  168 static int ata_siiprb_status(device_t dev);
  169 static int ata_siiprb_begin_transaction(struct ata_request *request);
  170 static int ata_siiprb_end_transaction(struct ata_request *request);
  171 static void ata_siiprb_reset(device_t dev);
  172 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
  173 static void ata_siiprb_dmainit(device_t dev);
  174 static int ata_sis_chipinit(device_t dev);
  175 static int ata_sis_allocate(device_t dev);
  176 static void ata_sis_reset(device_t dev);
  177 static void ata_sis_setmode(device_t dev, int mode);
  178 static int ata_via_chipinit(device_t dev);
  179 static int ata_via_allocate(device_t dev);
  180 static void ata_via_reset(device_t dev);
  181 static void ata_via_setmode(device_t dev, int mode);
  182 static void ata_via_southbridge_fixup(device_t dev);
  183 static void ata_via_family_setmode(device_t dev, int mode);
  184 static void ata_set_desc(device_t dev);
  185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
  186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
  187 static int ata_setup_interrupt(device_t dev);
  188 static int ata_serialize(device_t dev, int flags);
  189 static void ata_print_cable(device_t dev, u_int8_t *who);
  190 static int ata_atapi(device_t dev);
  191 static int ata_check_80pin(device_t dev, int mode);
  192 static int ata_mode2idx(int mode);
  193 
  194 
  195 /*
  196  * generic ATA support functions
  197  */
  198 int
  199 ata_generic_ident(device_t dev)
  200 {
  201     struct ata_pci_controller *ctlr = device_get_softc(dev);
  202     char buffer[64];
  203 
  204     sprintf(buffer, "%s ATA controller", ata_pcivendor2str(dev));
  205     device_set_desc_copy(dev, buffer);
  206     ctlr->chipinit = ata_generic_chipinit;
  207     return 0;
  208 }
  209 
  210 static int
  211 ata_generic_chipinit(device_t dev)
  212 {
  213     struct ata_pci_controller *ctlr = device_get_softc(dev);
  214 
  215     if (ata_setup_interrupt(dev))
  216         return ENXIO;
  217     ctlr->setmode = ata_generic_setmode;
  218     return 0;
  219 }
  220 
  221 static void
  222 ata_generic_intr(void *data)
  223 {
  224     struct ata_pci_controller *ctlr = data;
  225     struct ata_channel *ch;
  226     int unit;
  227 
  228     for (unit = 0; unit < ctlr->channels; unit++) {
  229         if ((ch = ctlr->interrupt[unit].argument))
  230             ctlr->interrupt[unit].function(ch);
  231     }
  232 }
  233 
  234 static void
  235 ata_generic_setmode(device_t dev, int mode)
  236 {
  237     struct ata_device *atadev = device_get_softc(dev);
  238 
  239     mode = ata_limit_mode(dev, mode, ATA_UDMA2);
  240     mode = ata_check_80pin(dev, mode);
  241     if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
  242         atadev->mode = mode;
  243 }
  244 
  245 
  246 /*
  247  * SATA support functions
  248  */
  249 static void
  250 ata_sata_phy_check_events(device_t dev)
  251 {
  252     struct ata_channel *ch = device_get_softc(dev);
  253     u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
  254 
  255     /* clear error bits/interrupt */
  256     ATA_IDX_OUTL(ch, ATA_SERROR, error);
  257 
  258     /* do we have any events flagged ? */
  259     if (error) {
  260         struct ata_connect_task *tp;
  261         u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
  262 
  263         /* if we have a connection event deal with it */
  264         if ((error & ATA_SE_PHY_CHANGED) &&
  265             (tp = (struct ata_connect_task *)
  266                   malloc(sizeof(struct ata_connect_task),
  267                          M_ATA, M_NOWAIT | M_ZERO))) {
  268 
  269             if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
  270                 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
  271                 if (bootverbose)
  272                     device_printf(ch->dev, "CONNECT requested\n");
  273                 tp->action = ATA_C_ATTACH;
  274             }
  275             else {
  276                 if (bootverbose)
  277                     device_printf(ch->dev, "DISCONNECT requested\n");
  278                 tp->action = ATA_C_DETACH;
  279             }
  280             tp->dev = ch->dev;
  281             TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
  282             taskqueue_enqueue(taskqueue_thread, &tp->task);
  283         }
  284     }
  285 }
  286 
  287 static void
  288 ata_sata_phy_event(void *context, int dummy)
  289 {
  290     struct ata_connect_task *tp = (struct ata_connect_task *)context;
  291     struct ata_channel *ch = device_get_softc(tp->dev);
  292     device_t *children;
  293     int nchildren, i;
  294 
  295     mtx_lock(&Giant);   /* newbus suckage it needs Giant */
  296     if (tp->action == ATA_C_ATTACH) {
  297         if (bootverbose)
  298             device_printf(tp->dev, "CONNECTED\n");
  299         ATA_RESET(tp->dev);
  300         ata_identify(tp->dev);
  301     }
  302     if (tp->action == ATA_C_DETACH) {
  303         if (!device_get_children(tp->dev, &children, &nchildren)) {
  304             for (i = 0; i < nchildren; i++)
  305                 if (children[i])
  306                     device_delete_child(tp->dev, children[i]);
  307             free(children, M_TEMP);
  308         }    
  309         mtx_lock(&ch->state_mtx);
  310         ch->state = ATA_IDLE;
  311         mtx_unlock(&ch->state_mtx);
  312         if (bootverbose)
  313             device_printf(tp->dev, "DISCONNECTED\n");
  314     }
  315     mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
  316     free(tp, M_ATA);
  317 }
  318 
  319 static int
  320 ata_sata_phy_reset(device_t dev)
  321 {
  322     struct ata_channel *ch = device_get_softc(dev);
  323     int loop, retry;
  324 
  325     if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
  326         return ata_sata_connect(ch);
  327 
  328     for (retry = 0; retry < 10; retry++) {
  329         for (loop = 0; loop < 10; loop++) {
  330             ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
  331             ata_udelay(100);
  332             if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 
  333                 ATA_SC_DET_RESET)
  334                 break;
  335         }
  336         ata_udelay(5000);
  337         for (loop = 0; loop < 10; loop++) {
  338             ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
  339                                            ATA_SC_IPM_DIS_PARTIAL |
  340                                            ATA_SC_IPM_DIS_SLUMBER);
  341             ata_udelay(100);
  342             if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
  343                 return ata_sata_connect(ch);
  344         }
  345     }
  346     return 0;
  347 }
  348 
  349 static int
  350 ata_sata_connect(struct ata_channel *ch)
  351 {
  352     u_int32_t status;
  353     int timeout;
  354 
  355     /* wait up to 1 second for "connect well" */
  356     for (timeout = 0; timeout < 100 ; timeout++) {
  357         status = ATA_IDX_INL(ch, ATA_SSTATUS);
  358         if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
  359             (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
  360             break;
  361         ata_udelay(10000);
  362     }
  363     if (timeout >= 100) {
  364         if (bootverbose)
  365             device_printf(ch->dev, "SATA connect status=%08x\n", status);
  366         return 0;
  367     }
  368     if (bootverbose)
  369         device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
  370 
  371     /* clear SATA error register */
  372     ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
  373 
  374     return 1;
  375 }
  376 
  377 static void
  378 ata_sata_setmode(device_t dev, int mode)
  379 {
  380     struct ata_device *atadev = device_get_softc(dev);
  381 
  382     /*
  383      * if we detect that the device isn't a real SATA device we limit 
  384      * the transfer mode to UDMA5/ATA100.
  385      * this works around the problems some devices has with the 
  386      * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
  387      */
  388     if (atadev->param.satacapabilities != 0x0000 &&
  389         atadev->param.satacapabilities != 0xffff) {
  390         struct ata_channel *ch = device_get_softc(device_get_parent(dev));
  391 
  392         /* on some drives we need to set the transfer mode */
  393         ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
  394                        ata_limit_mode(dev, mode, ATA_UDMA6));
  395 
  396         /* query SATA STATUS for the speed */
  397         if (ch->r_io[ATA_SSTATUS].res && 
  398            ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
  399             ATA_SS_CONWELL_GEN2))
  400             atadev->mode = ATA_SA300;
  401         else 
  402             atadev->mode = ATA_SA150;
  403     }
  404     else {
  405         mode = ata_limit_mode(dev, mode, ATA_UDMA5);
  406         if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
  407             atadev->mode = mode;
  408     }
  409 }
  410 
  411 static int
  412 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
  413 {
  414     struct ata_device *atadev = device_get_softc(request->dev);
  415 
  416     if (request->flags & ATA_R_ATAPI) {
  417         fis[0] = 0x27;  /* host to device */
  418         fis[1] = 0x80;  /* command FIS (note PM goes here) */
  419         fis[2] = ATA_PACKET_CMD;
  420         if (request->flags & (ATA_R_READ | ATA_R_WRITE))
  421             fis[3] = ATA_F_DMA;
  422         else {
  423             fis[5] = request->transfersize;
  424             fis[6] = request->transfersize >> 8;
  425         }
  426         fis[7] = ATA_D_LBA | atadev->unit;
  427         fis[15] = ATA_A_4BIT;
  428         return 20;
  429     }
  430     else {
  431         ata_modify_if_48bit(request);
  432         fis[0] = 0x27;  /* host to device */
  433         fis[1] = 0x80;  /* command FIS (note PM goes here) */
  434         fis[2] = request->u.ata.command;
  435         fis[3] = request->u.ata.feature;
  436         fis[4] = request->u.ata.lba;
  437         fis[5] = request->u.ata.lba >> 8;
  438         fis[6] = request->u.ata.lba >> 16;
  439         fis[7] = ATA_D_LBA | atadev->unit;
  440         if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
  441             fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
  442         fis[8] = request->u.ata.lba >> 24;
  443         fis[9] = request->u.ata.lba >> 32; 
  444         fis[10] = request->u.ata.lba >> 40; 
  445         fis[11] = request->u.ata.feature >> 8;
  446         fis[12] = request->u.ata.count;
  447         fis[13] = request->u.ata.count >> 8;
  448         fis[15] = ATA_A_4BIT;
  449         return 20;
  450     }
  451     return 0;
  452 }
  453 
  454 
  455 /*
  456  * AHCI v1.x compliant SATA chipset support functions
  457  */
  458 int
  459 ata_ahci_ident(device_t dev)
  460 {
  461     struct ata_pci_controller *ctlr = device_get_softc(dev);
  462     char buffer[64];
  463 
  464     /* is this PCI device flagged as an AHCI compliant chip ? */
  465     if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
  466         return ENXIO;
  467 
  468     if (bootverbose)
  469         sprintf(buffer, "%s (ID=%08x) AHCI controller", 
  470                 ata_pcivendor2str(dev), pci_get_devid(dev));
  471     else
  472         sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
  473     device_set_desc_copy(dev, buffer);
  474     ctlr->chipinit = ata_ahci_chipinit;
  475     return 0;
  476 }
  477 
  478 static int
  479 ata_ahci_chipinit(device_t dev)
  480 {
  481     struct ata_pci_controller *ctlr = device_get_softc(dev);
  482     u_int32_t version;
  483 
  484     /* if we have a memory BAR(5) we are likely on an AHCI part */
  485     ctlr->r_type2 = SYS_RES_MEMORY;
  486     ctlr->r_rid2 = PCIR_BAR(5);
  487     if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
  488                                                &ctlr->r_rid2, RF_ACTIVE)))
  489         return ENXIO;
  490 
  491     /* setup interrupt delivery if not done allready by a vendor driver */
  492     if (!ctlr->r_irq) {
  493         if (ata_setup_interrupt(dev))
  494             return ENXIO;
  495     }
  496     else
  497         device_printf(dev, "AHCI called from vendor specific driver\n");
  498 
  499     /* enable AHCI mode */
  500     ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
  501 
  502     /* reset AHCI controller */
  503     ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
  504     DELAY(1000000);
  505     if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
  506         bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
  507         device_printf(dev, "AHCI controller reset failure\n");
  508         return ENXIO;
  509     }
  510 
  511     /* reenable AHCI mode */
  512     ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
  513 
  514     /* get the number of HW channels */
  515     ctlr->channels =
  516         MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 
  517             (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
  518 
  519     /* clear interrupts */
  520     ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
  521 
  522     /* enable AHCI interrupts */
  523     ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
  524              ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
  525 
  526     ctlr->reset = ata_ahci_reset;
  527     ctlr->dmainit = ata_ahci_dmainit;
  528     ctlr->allocate = ata_ahci_allocate;
  529     ctlr->setmode = ata_sata_setmode;
  530 
  531     /* announce we support the HW */
  532     version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
  533     device_printf(dev,
  534                   "AHCI Version %x%x.%x%x controller with %d ports detected\n",
  535                   (version >> 24) & 0xff, (version >> 16) & 0xff,
  536                   (version >> 8) & 0xff, version & 0xff,
  537                   (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
  538     return 0;
  539 }
  540 
  541 static int
  542 ata_ahci_allocate(device_t dev)
  543 {
  544     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
  545     struct ata_channel *ch = device_get_softc(dev);
  546     u_int64_t work;
  547     int offset = ch->unit << 7;
  548 
  549     /* set the SATA resources */
  550     ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
  551     ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
  552     ch->r_io[ATA_SERROR].res = ctlr->r_res2;
  553     ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
  554     ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
  555     ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
  556     ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
  557     ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
  558 
  559     ch->hw.status = ata_ahci_status;
  560     ch->hw.begin_transaction = ata_ahci_begin_transaction;
  561     ch->hw.end_transaction = ata_ahci_end_transaction;
  562     ch->hw.command = NULL;      /* not used here */
  563 
  564     /* setup work areas */
  565     work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
  566     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
  567     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
  568 
  569     work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
  570     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 
  571     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
  572 
  573     /* enable wanted port interrupts */
  574     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
  575              (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
  576               ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
  577               ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
  578               ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
  579               ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
  580 
  581     /* start operations on this channel */
  582     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  583              (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
  584               ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
  585     return 0;
  586 }
  587 
  588 static int
  589 ata_ahci_status(device_t dev)
  590 {
  591     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
  592     struct ata_channel *ch = device_get_softc(dev);
  593     u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
  594     int offset = ch->unit << 7;
  595     int tag = 0;
  596 
  597     if (action & (1 << ch->unit)) {
  598         u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
  599         u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
  600 
  601         /* clear interrupt(s) */
  602         ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
  603         ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
  604 
  605         /* do we have any PHY events ? */
  606         /* XXX SOS check istatus phy bits */
  607         ata_sata_phy_check_events(dev);
  608 
  609         /* do we have a potentially hanging engine to take care of? */
  610         if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
  611 
  612             u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
  613             int timeout = 0;
  614 
  615             /* kill off all activity on this channel */
  616             ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  617                      cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
  618 
  619             /* XXX SOS this is not entirely wrong */
  620             do {
  621                 DELAY(1000);
  622                 if (timeout++ > 500) {
  623                     device_printf(dev, "stopping AHCI engine failed\n");
  624                     break;
  625                 }
  626             } while (ATA_INL(ctlr->r_res2,
  627                              ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
  628 
  629             /* start operations on this channel */
  630             ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  631                      cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
  632 
  633             return 1;
  634         }
  635         else
  636             return (!(cstatus & (1 << tag)));
  637     }
  638     return 0;
  639 }
  640 
  641 /* must be called with ATA channel locked and state_mtx held */
  642 static int
  643 ata_ahci_begin_transaction(struct ata_request *request)
  644 {
  645     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
  646     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
  647     struct ata_ahci_cmd_tab *ctp;
  648     struct ata_ahci_cmd_list *clp;
  649     int offset = ch->unit << 7;
  650     int tag = 0, entries = 0;
  651     int fis_size;
  652         
  653     /* get a piece of the workspace for this request */
  654     ctp = (struct ata_ahci_cmd_tab *)
  655           (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
  656 
  657     /* setup the FIS for this request */
  658     if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
  659         device_printf(request->dev, "setting up SATA FIS failed\n");
  660         request->result = EIO;
  661         return ATA_OP_FINISHED;
  662     }
  663 
  664     /* if request moves data setup and load SG list */
  665     if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
  666         if (ch->dma->load(ch->dev, request->data, request->bytecount,
  667                           request->flags & ATA_R_READ,
  668                           ctp->prd_tab, &entries)) {
  669             device_printf(request->dev, "setting up DMA failed\n");
  670             request->result = EIO;
  671             return ATA_OP_FINISHED;
  672         }
  673     }
  674 
  675     /* setup the command list entry */
  676     clp = (struct ata_ahci_cmd_list *)
  677           (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
  678 
  679     clp->prd_length = entries;
  680     clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
  681                      (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
  682                      (fis_size / sizeof(u_int32_t));
  683     clp->bytecount = 0;
  684     clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
  685                                   (ATA_AHCI_CT_SIZE * tag));
  686 
  687     /* clear eventual ACTIVE bit */
  688     ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
  689 
  690     /* set command type bit */
  691     if (request->flags & ATA_R_ATAPI)
  692         ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  693                  ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
  694                  ATA_AHCI_P_CMD_ATAPI);
  695     else
  696         ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  697                  ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
  698                  ~ATA_AHCI_P_CMD_ATAPI);
  699 
  700     /* issue command to controller */
  701     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
  702     
  703     if (!(request->flags & ATA_R_ATAPI)) {
  704         /* device reset doesn't interrupt */
  705         if (request->u.ata.command == ATA_DEVICE_RESET) {
  706             u_int32_t tf_data;
  707             int timeout = 1000000;
  708 
  709             do {
  710                 DELAY(10);
  711                 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
  712             } while ((tf_data & ATA_S_BUSY) && timeout--);
  713             if (bootverbose)
  714                 device_printf(ch->dev, "device_reset timeout=%dus\n",
  715                               (1000000-timeout)*10);
  716             request->status = tf_data;
  717             if (request->status & ATA_S_ERROR)
  718                 request->error = tf_data >> 8;
  719             return ATA_OP_FINISHED;
  720         }
  721     }
  722 
  723     /* start the timeout */
  724     callout_reset(&request->callout, request->timeout * hz,
  725                   (timeout_t*)ata_timeout, request);
  726     return ATA_OP_CONTINUES;
  727 }
  728 
  729 /* must be called with ATA channel locked and state_mtx held */
  730 static int
  731 ata_ahci_end_transaction(struct ata_request *request)
  732 {
  733     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
  734     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
  735     struct ata_ahci_cmd_list *clp;
  736     u_int32_t tf_data;
  737     int offset = ch->unit << 7;
  738     int tag = 0;
  739 
  740     /* kill the timeout */
  741     callout_stop(&request->callout);
  742 
  743     /* get status */
  744     tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
  745     request->status = tf_data;
  746 
  747     /* if error status get details */
  748     if (request->status & ATA_S_ERROR)  
  749         request->error = tf_data >> 8;
  750 
  751     /* record how much data we actually moved */
  752     clp = (struct ata_ahci_cmd_list *)
  753           (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
  754     request->donecount = clp->bytecount;
  755 
  756     /* release SG list etc */
  757     ch->dma->unload(ch->dev);
  758 
  759     return ATA_OP_FINISHED;
  760 }
  761 
  762 static void
  763 ata_ahci_reset(device_t dev)
  764 {
  765     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
  766     struct ata_channel *ch = device_get_softc(dev);
  767     u_int32_t cmd, signature;
  768     int offset = ch->unit << 7;
  769     int timeout;
  770 
  771     if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
  772         device_printf(dev, "port not implemented\n");
  773         return;
  774     }
  775     ch->devices = 0;
  776 
  777     /* kill off all activity on this channel */
  778     cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
  779     ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  780              cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
  781 
  782     /* XXX SOS this is not entirely wrong */
  783     timeout = 0;
  784     do {
  785         DELAY(1000);
  786         if (timeout++ > 500) {
  787             device_printf(dev, "stopping AHCI engine failed\n");
  788             break;
  789         }
  790     }
  791     while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
  792 
  793     /* issue Command List Override if supported */ 
  794     if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
  795         cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
  796         cmd |= ATA_AHCI_P_CMD_CLO;
  797         ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
  798         timeout = 0;
  799         do {
  800             DELAY(1000);
  801             if (timeout++ > 500) {
  802                 device_printf(dev, "executing CLO failed\n");
  803                 break;
  804             }
  805         }
  806         while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
  807     }
  808 
  809     /* reset PHY and decide what is present */
  810     if (ata_sata_phy_reset(dev)) {
  811 
  812         /* clear any interrupts pending on this channel */
  813         ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
  814                  ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
  815 
  816         /* clear SATA error register */
  817         ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
  818 
  819         /* start operations on this channel */
  820         ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
  821                  (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
  822                   ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
  823 
  824         signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
  825         if (bootverbose)
  826             device_printf(dev, "SIGNATURE: %08x\n", signature);
  827         switch (signature) {
  828         case 0x00000101:
  829             ch->devices = ATA_ATA_MASTER;
  830             break;
  831         case 0x96690101:
  832             ch->devices = ATA_PORTMULTIPLIER;
  833             device_printf(ch->dev, "Portmultipliers not supported yet\n");
  834             ch->devices = 0;
  835             break;
  836         case 0xeb140101:
  837             ch->devices = ATA_ATAPI_MASTER;
  838             break;
  839         default: /* SOS XXX */
  840             if (bootverbose)
  841                 device_printf(ch->dev, "No signature, asuming disk device\n");
  842             ch->devices = ATA_ATA_MASTER;
  843         }
  844     }
  845     if (bootverbose)
  846         device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
  847                       "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
  848 }
  849 
  850 static void
  851 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
  852 {    
  853     struct ata_dmasetprd_args *args = xsc;
  854     struct ata_ahci_dma_prd *prd = args->dmatab;
  855     int i;
  856 
  857     if (!(args->error = error)) {
  858         for (i = 0; i < nsegs; i++) {
  859             prd[i].dba = htole64(segs[i].ds_addr);
  860             prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
  861         }
  862     }
  863     KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
  864     args->nsegs = nsegs;
  865 }
  866 
  867 static void
  868 ata_ahci_dmainit(device_t dev)
  869 {
  870     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
  871     struct ata_channel *ch = device_get_softc(dev);
  872 
  873     ata_dmainit(dev);
  874     if (ch->dma) {
  875         /* note start and stop are not used here */
  876         ch->dma->setprd = ata_ahci_dmasetprd;
  877         ch->dma->max_iosize = 8192 * DEV_BSIZE;
  878         if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
  879             ch->dma->max_address = BUS_SPACE_MAXADDR;
  880     }
  881 }
  882 
  883 static int
  884 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
  885 {
  886     bzero(ctp->cfis, 64);
  887     if (request->flags & ATA_R_ATAPI) {
  888         bzero(ctp->acmd, 32);
  889         bcopy(request->u.atapi.ccb, ctp->acmd, 16);
  890     }
  891     return ata_request2fis_h2d(request, &ctp->cfis[0]);
  892 }
  893 
  894 
  895 /*
  896  * Acard chipset support functions
  897  */
  898 int
  899 ata_acard_ident(device_t dev)
  900 {
  901     struct ata_pci_controller *ctlr = device_get_softc(dev);
  902     static struct ata_chip_id ids[] =
  903     {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
  904      { ATA_ATP860A, 0, 0,      0x00, ATA_UDMA4, "ATP860A" },
  905      { ATA_ATP860R, 0, 0,      0x00, ATA_UDMA4, "ATP860R" },
  906      { ATA_ATP865A, 0, 0,      0x00, ATA_UDMA6, "ATP865A" },
  907      { ATA_ATP865R, 0, 0,      0x00, ATA_UDMA6, "ATP865R" },
  908      { 0, 0, 0, 0, 0, 0}};
  909 
  910     if (!(ctlr->chip = ata_match_chip(dev, ids)))
  911         return ENXIO;
  912 
  913     ata_set_desc(dev);
  914     ctlr->chipinit = ata_acard_chipinit;
  915     return 0;
  916 }
  917 
  918 static int
  919 ata_acard_chipinit(device_t dev)
  920 {
  921     struct ata_pci_controller *ctlr = device_get_softc(dev);
  922 
  923     if (ata_setup_interrupt(dev))
  924         return ENXIO;
  925 
  926     ctlr->allocate = ata_acard_allocate;
  927     if (ctlr->chip->cfg1 == ATPOLD) {
  928         ctlr->setmode = ata_acard_850_setmode;
  929         ctlr->locking = ata_serialize;
  930     }
  931     else
  932         ctlr->setmode = ata_acard_86X_setmode;
  933     return 0;
  934 }
  935 
  936 static int
  937 ata_acard_allocate(device_t dev)
  938 {
  939     struct ata_channel *ch = device_get_softc(dev);
  940 
  941     /* setup the usual register normal pci style */
  942     if (ata_pci_allocate(dev))
  943         return ENXIO;
  944 
  945     ch->hw.status = ata_acard_status;
  946     return 0;
  947 }
  948 
  949 static int
  950 ata_acard_status(device_t dev)
  951 {
  952     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
  953     struct ata_channel *ch = device_get_softc(dev);
  954 
  955     if (ctlr->chip->cfg1 == ATPOLD &&
  956         ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
  957             return 0;
  958     if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
  959         int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
  960 
  961         if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
  962             ATA_BMSTAT_INTERRUPT)
  963             return 0;
  964         ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
  965         DELAY(1);
  966         ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
  967                      ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
  968         DELAY(1);
  969     }
  970     if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
  971         DELAY(100);
  972         if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
  973             return 0;
  974     }
  975     return 1;
  976 }
  977 
  978 static void
  979 ata_acard_850_setmode(device_t dev, int mode)
  980 {
  981     device_t gparent = GRANDPARENT(dev);
  982     struct ata_pci_controller *ctlr = device_get_softc(gparent);
  983     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
  984     struct ata_device *atadev = device_get_softc(dev);
  985     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
  986     int error;
  987 
  988     mode = ata_limit_mode(dev, mode,
  989                           ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
  990 
  991     /* XXX SOS missing WDMA0+1 + PIO modes */
  992     if (mode >= ATA_WDMA2) {
  993         error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
  994         if (bootverbose)
  995             device_printf(dev, "%ssetting %s on %s chip\n",
  996                           (error) ? "FAILURE " : "",
  997                           ata_mode2str(mode), ctlr->chip->text);
  998         if (!error) {
  999             u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
 1000             
 1001             reg54 &= ~(0x03 << (devno << 1));
 1002             if (mode >= ATA_UDMA0)
 1003                 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
 1004             pci_write_config(gparent, 0x54, reg54, 1);
 1005             pci_write_config(gparent, 0x4a, 0xa6, 1);
 1006             pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
 1007             atadev->mode = mode;
 1008             return;
 1009         }
 1010     }
 1011     /* we could set PIO mode timings, but we assume the BIOS did that */
 1012 }
 1013 
 1014 static void
 1015 ata_acard_86X_setmode(device_t dev, int mode)
 1016 {
 1017     device_t gparent = GRANDPARENT(dev);
 1018     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 1019     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1020     struct ata_device *atadev = device_get_softc(dev);
 1021     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 1022     int error;
 1023 
 1024 
 1025     mode = ata_limit_mode(dev, mode,
 1026                           ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
 1027 
 1028     mode = ata_check_80pin(dev, mode);
 1029 
 1030     /* XXX SOS missing WDMA0+1 + PIO modes */
 1031     if (mode >= ATA_WDMA2) {
 1032         error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 1033         if (bootverbose)
 1034             device_printf(dev, "%ssetting %s on %s chip\n",
 1035                           (error) ? "FAILURE " : "",
 1036                           ata_mode2str(mode), ctlr->chip->text);
 1037         if (!error) {
 1038             u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
 1039             
 1040             reg44 &= ~(0x000f << (devno << 2));
 1041             if (mode >= ATA_UDMA0)
 1042                 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
 1043             pci_write_config(gparent, 0x44, reg44, 2);
 1044             pci_write_config(gparent, 0x4a, 0xa6, 1);
 1045             pci_write_config(gparent, 0x40 + devno, 0x31, 1);
 1046             atadev->mode = mode;
 1047             return;
 1048         }
 1049     }
 1050     /* we could set PIO mode timings, but we assume the BIOS did that */
 1051 }
 1052 
 1053 
 1054 /*
 1055  * Acer Labs Inc (ALI) chipset support functions
 1056  */
 1057 int
 1058 ata_ali_ident(device_t dev)
 1059 {
 1060     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1061     static struct ata_chip_id ids[] =
 1062     {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
 1063      { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
 1064      { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
 1065      { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
 1066      { ATA_ALI_5229, 0xc5, 0, ALINEW,  ATA_UDMA6, "M5229" },
 1067      { ATA_ALI_5229, 0xc4, 0, ALINEW,  ATA_UDMA5, "M5229" },
 1068      { ATA_ALI_5229, 0xc2, 0, ALINEW,  ATA_UDMA4, "M5229" },
 1069      { ATA_ALI_5229, 0x20, 0, ALIOLD,  ATA_UDMA2, "M5229" },
 1070      { ATA_ALI_5229, 0x00, 0, ALIOLD,  ATA_WDMA2, "M5229" },
 1071      { 0, 0, 0, 0, 0, 0}};
 1072 
 1073     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 1074         return ENXIO;
 1075 
 1076     ata_set_desc(dev);
 1077     ctlr->chipinit = ata_ali_chipinit;
 1078     return 0;
 1079 }
 1080 
 1081 static int
 1082 ata_ali_chipinit(device_t dev)
 1083 {
 1084     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1085 
 1086     if (ata_setup_interrupt(dev))
 1087         return ENXIO;
 1088 
 1089     switch (ctlr->chip->cfg2) {
 1090     case ALISATA:
 1091         ctlr->channels = ctlr->chip->cfg1;
 1092         ctlr->allocate = ata_ali_sata_allocate;
 1093         ctlr->setmode = ata_sata_setmode;
 1094 
 1095         /* AHCI mode is correctly supported only on the ALi 5288. */
 1096         if ((ctlr->chip->chipid == ATA_ALI_5288) &&
 1097             (ata_ahci_chipinit(dev) != ENXIO))
 1098             return 0;
 1099         break;
 1100 
 1101     case ALINEW:
 1102         /* use device interrupt as byte count end */
 1103         pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
 1104 
 1105         /* enable cable detection and UDMA support on newer chips */
 1106         pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
 1107 
 1108         /* enable ATAPI UDMA mode */
 1109         pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
 1110 
 1111         /* only chips with revision > 0xc4 can do 48bit DMA */
 1112         if (ctlr->chip->chiprev <= 0xc4)
 1113             device_printf(dev,
 1114                           "using PIO transfers above 137GB as workaround for "
 1115                           "48bit DMA access bug, expect reduced performance\n");
 1116         ctlr->allocate = ata_ali_allocate;
 1117         ctlr->reset = ata_ali_reset;
 1118         ctlr->setmode = ata_ali_setmode;
 1119         break;
 1120 
 1121     case ALIOLD:
 1122         /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
 1123         pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
 1124         ctlr->setmode = ata_ali_setmode;
 1125         break;
 1126     }
 1127     return 0;
 1128 }
 1129 
 1130 static int
 1131 ata_ali_allocate(device_t dev)
 1132 {
 1133     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 1134     struct ata_channel *ch = device_get_softc(dev);
 1135 
 1136     /* setup the usual register normal pci style */
 1137     if (ata_pci_allocate(dev))
 1138         return ENXIO;
 1139 
 1140     /* older chips can't do 48bit DMA transfers */
 1141     if (ctlr->chip->chiprev <= 0xc4)
 1142         ch->flags |= ATA_NO_48BIT_DMA;
 1143 
 1144     return 0;
 1145 }
 1146 
 1147 static int
 1148 ata_ali_sata_allocate(device_t dev)
 1149 {
 1150     device_t parent = device_get_parent(dev);
 1151     struct ata_pci_controller *ctlr = device_get_softc(parent);
 1152     struct ata_channel *ch = device_get_softc(dev);
 1153     struct resource *io = NULL, *ctlio = NULL;
 1154     int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
 1155     int i, rid;
 1156                 
 1157     rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
 1158     io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
 1159     if (!io)
 1160         return ENXIO;
 1161 
 1162     rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
 1163     ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
 1164     if (!ctlio) {
 1165         bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
 1166         return ENXIO;
 1167     }
 1168                 
 1169     for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
 1170         ch->r_io[i].res = io;
 1171         ch->r_io[i].offset = i + (unit10 ? 8 : 0);
 1172     }
 1173     ch->r_io[ATA_CONTROL].res = ctlio;
 1174     ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
 1175     ch->r_io[ATA_IDX_ADDR].res = io;
 1176     ata_default_registers(dev);
 1177     if (ctlr->r_res1) {
 1178         for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
 1179             ch->r_io[i].res = ctlr->r_res1;
 1180             ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
 1181         }
 1182     }
 1183     ch->flags |= ATA_NO_SLAVE;
 1184 
 1185     /* XXX SOS PHY handling awkward in ALI chip not supported yet */
 1186     ata_pci_hw(dev);
 1187     return 0;
 1188 }
 1189 
 1190 static void
 1191 ata_ali_reset(device_t dev)
 1192 {
 1193     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 1194     struct ata_channel *ch = device_get_softc(dev);
 1195     device_t *children;
 1196     int nchildren, i;
 1197 
 1198     ata_generic_reset(dev);
 1199 
 1200     /*
 1201      * workaround for datacorruption bug found on at least SUN Blade-100
 1202      * find the ISA function on the southbridge and disable then enable
 1203      * the ATA channel tristate buffer
 1204      */
 1205     if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
 1206         if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
 1207             for (i = 0; i < nchildren; i++) {
 1208                 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
 1209                     pci_write_config(children[i], 0x58, 
 1210                                      pci_read_config(children[i], 0x58, 1) &
 1211                                      ~(0x04 << ch->unit), 1);
 1212                     pci_write_config(children[i], 0x58, 
 1213                                      pci_read_config(children[i], 0x58, 1) |
 1214                                      (0x04 << ch->unit), 1);
 1215                     break;
 1216                 }
 1217             }
 1218             free(children, M_TEMP);
 1219         }
 1220     }
 1221 }
 1222 
 1223 static void
 1224 ata_ali_setmode(device_t dev, int mode)
 1225 {
 1226     device_t gparent = GRANDPARENT(dev);
 1227     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 1228     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1229     struct ata_device *atadev = device_get_softc(dev);
 1230     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 1231     int error;
 1232 
 1233     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 1234 
 1235     if (ctlr->chip->cfg2 & ALINEW) {
 1236         if (mode > ATA_UDMA2 &&
 1237             pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
 1238             ata_print_cable(dev, "controller");
 1239             mode = ATA_UDMA2;
 1240         }
 1241     }
 1242     else
 1243         mode = ata_check_80pin(dev, mode);
 1244 
 1245     if (ctlr->chip->cfg2 & ALIOLD) {
 1246         /* doesn't support ATAPI DMA on write */
 1247         ch->flags |= ATA_ATAPI_DMA_RO;
 1248         if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
 1249             /* doesn't support ATAPI DMA on two ATAPI devices */
 1250             device_printf(dev, "two atapi devices on this channel, no DMA\n");
 1251             mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
 1252         }
 1253     }
 1254 
 1255     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 1256 
 1257     if (bootverbose)
 1258         device_printf(dev, "%ssetting %s on %s chip\n",
 1259                    (error) ? "FAILURE " : "", 
 1260                    ata_mode2str(mode), ctlr->chip->text);
 1261     if (!error) {
 1262         if (mode >= ATA_UDMA0) {
 1263             u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
 1264             u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
 1265 
 1266             word54 &= ~(0x000f000f << (devno << 2));
 1267             word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
 1268             pci_write_config(gparent, 0x54, word54, 4);
 1269             pci_write_config(gparent, 0x58 + (ch->unit << 2),
 1270                              0x00310001, 4);
 1271         }
 1272         else {
 1273             u_int32_t piotimings[] =
 1274                 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
 1275                   0x00310001, 0x00440001, 0x00330001, 0x00310001};
 1276 
 1277             pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
 1278                                             ~(0x0008000f << (devno << 2)), 4);
 1279             pci_write_config(gparent, 0x58 + (ch->unit << 2),
 1280                              piotimings[ata_mode2idx(mode)], 4);
 1281         }
 1282         atadev->mode = mode;
 1283     }
 1284 }
 1285 
 1286 
 1287 /*
 1288  * American Micro Devices (AMD) chipset support functions
 1289  */
 1290 int
 1291 ata_amd_ident(device_t dev)
 1292 {
 1293     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1294     static struct ata_chip_id ids[] =
 1295     {{ ATA_AMD756,  0x00, AMDNVIDIA, 0x00,            ATA_UDMA4, "756" },
 1296      { ATA_AMD766,  0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
 1297      { ATA_AMD768,  0x00, AMDNVIDIA, AMDCABLE,        ATA_UDMA5, "768" },
 1298      { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE,        ATA_UDMA6, "8111" },
 1299      { ATA_AMD5536, 0x00, AMDNVIDIA, 0x00,            ATA_UDMA5, "CS5536" },
 1300      { 0, 0, 0, 0, 0, 0}};
 1301 
 1302     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 1303         return ENXIO;
 1304 
 1305     ata_set_desc(dev);
 1306     ctlr->chipinit = ata_amd_chipinit;
 1307     return 0;
 1308 }
 1309 
 1310 static int
 1311 ata_amd_chipinit(device_t dev)
 1312 {
 1313     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1314 
 1315     if (ata_setup_interrupt(dev))
 1316         return ENXIO;
 1317 
 1318     /* disable/set prefetch, postwrite */
 1319     if (ctlr->chip->cfg2 & AMDBUG)
 1320         pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
 1321     else
 1322         pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
 1323 
 1324     ctlr->setmode = ata_via_family_setmode;
 1325     return 0;
 1326 }
 1327 
 1328 
 1329 /*
 1330  * ATI chipset support functions
 1331  */
 1332 int
 1333 ata_ati_ident(device_t dev)
 1334 {
 1335     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1336     static struct ata_chip_id ids[] =
 1337     {{ ATA_ATI_IXP200,    0x00, 0, ATIPATA, ATA_UDMA5, "IXP200" },
 1338      { ATA_ATI_IXP300,    0x00, 0, ATIPATA, ATA_UDMA6, "IXP300" },
 1339      { ATA_ATI_IXP300_S1, 0x00, 0, ATISATA, ATA_SA150, "IXP300" },
 1340      { ATA_ATI_IXP400,    0x00, 0, ATIPATA, ATA_UDMA6, "IXP400" },
 1341      { ATA_ATI_IXP400_S1, 0x00, 0, ATISATA, ATA_SA150, "IXP400" },
 1342      { ATA_ATI_IXP400_S2, 0x00, 0, ATISATA, ATA_SA150, "IXP400" },
 1343      { ATA_ATI_IXP600,    0x00, 0, ATIPATA, ATA_UDMA6, "IXP600" },
 1344      { ATA_ATI_IXP600_S1, 0x00, 0, ATIAHCI, ATA_SA300, "IXP600" },
 1345      { ATA_ATI_IXP700,    0x00, 0, ATIPATA, ATA_UDMA6, "IXP700" },
 1346      { ATA_ATI_IXP700_S1, 0x00, 0, ATIAHCI, ATA_SA300, "IXP700" },
 1347      { 0, 0, 0, 0, 0, 0}};
 1348 
 1349     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 1350         return ENXIO;
 1351 
 1352     ata_set_desc(dev);
 1353 
 1354     switch (ctlr->chip->cfg2) {
 1355     case ATIPATA:
 1356         ctlr->chipinit = ata_ati_chipinit;
 1357         break;
 1358     case ATISATA:
 1359         /* the ATI SATA controller is actually a SiI 3112 controller */
 1360         ctlr->chip->cfg1 = SIIMEMIO;
 1361         ctlr->chipinit = ata_sii_chipinit;
 1362         break;
 1363     case ATIAHCI:
 1364         ctlr->chipinit = ata_ahci_chipinit;
 1365         break;
 1366     }
 1367     return 0;
 1368 }
 1369 
 1370 static int
 1371 ata_ati_chipinit(device_t dev)
 1372 {
 1373     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1374 
 1375     if (ata_setup_interrupt(dev))
 1376         return ENXIO;
 1377 
 1378     /* IXP600 & IXP700 only have 1 PATA channel */
 1379     if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
 1380         (ctlr->chip->chipid == ATA_ATI_IXP700))
 1381         ctlr->channels = 1;
 1382 
 1383     ctlr->setmode = ata_ati_setmode;
 1384     return 0;
 1385 }
 1386 
 1387 static void
 1388 ata_ati_setmode(device_t dev, int mode)
 1389 {
 1390     device_t gparent = GRANDPARENT(dev);
 1391     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 1392     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1393     struct ata_device *atadev = device_get_softc(dev);
 1394     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 1395     int offset = (devno ^ 0x01) << 3;
 1396     int error;
 1397     u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
 1398                               0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
 1399     u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
 1400 
 1401     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 1402 
 1403     mode = ata_check_80pin(dev, mode);
 1404 
 1405     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 1406 
 1407     if (bootverbose)
 1408         device_printf(dev, "%ssetting %s on %s chip\n",
 1409                       (error) ? "FAILURE " : "",
 1410                       ata_mode2str(mode), ctlr->chip->text);
 1411     if (!error) {
 1412         if (mode >= ATA_UDMA0) {
 1413             pci_write_config(gparent, 0x56, 
 1414                              (pci_read_config(gparent, 0x56, 2) &
 1415                               ~(0xf << (devno << 2))) |
 1416                              ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
 1417             pci_write_config(gparent, 0x54,
 1418                              pci_read_config(gparent, 0x54, 1) |
 1419                              (0x01 << devno), 1);
 1420             pci_write_config(gparent, 0x44, 
 1421                              (pci_read_config(gparent, 0x44, 4) &
 1422                               ~(0xff << offset)) |
 1423                              (dmatimings[2] << offset), 4);
 1424         }
 1425         else if (mode >= ATA_WDMA0) {
 1426             pci_write_config(gparent, 0x54,
 1427                              pci_read_config(gparent, 0x54, 1) &
 1428                               ~(0x01 << devno), 1);
 1429             pci_write_config(gparent, 0x44, 
 1430                              (pci_read_config(gparent, 0x44, 4) &
 1431                               ~(0xff << offset)) |
 1432                              (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
 1433         }
 1434         else
 1435             pci_write_config(gparent, 0x54,
 1436                              pci_read_config(gparent, 0x54, 1) &
 1437                              ~(0x01 << devno), 1);
 1438 
 1439         pci_write_config(gparent, 0x4a,
 1440                          (pci_read_config(gparent, 0x4a, 2) &
 1441                           ~(0xf << (devno << 2))) |
 1442                          (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
 1443         pci_write_config(gparent, 0x40, 
 1444                          (pci_read_config(gparent, 0x40, 4) &
 1445                           ~(0xff << offset)) |
 1446                          (piotimings[ata_mode2idx(mode)] << offset), 4);
 1447         atadev->mode = mode;
 1448     }
 1449 }
 1450 
 1451 
 1452 /*
 1453  * Cyrix chipset support functions
 1454  */
 1455 int
 1456 ata_cyrix_ident(device_t dev)
 1457 {
 1458     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1459 
 1460     if (pci_get_devid(dev) == ATA_CYRIX_5530) {
 1461         device_set_desc(dev, "Cyrix 5530 ATA33 controller");
 1462         ctlr->chipinit = ata_cyrix_chipinit;
 1463         return 0;
 1464     }
 1465     return ENXIO;
 1466 }
 1467 
 1468 static int
 1469 ata_cyrix_chipinit(device_t dev)
 1470 {
 1471     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1472 
 1473     if (ata_setup_interrupt(dev))
 1474         return ENXIO;
 1475 
 1476     if (ctlr->r_res1)
 1477         ctlr->setmode = ata_cyrix_setmode;
 1478     else
 1479         ctlr->setmode = ata_generic_setmode;
 1480     return 0;
 1481 }
 1482 
 1483 static void
 1484 ata_cyrix_setmode(device_t dev, int mode)
 1485 {
 1486     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1487     struct ata_device *atadev = device_get_softc(dev);
 1488     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 1489     u_int32_t piotiming[] = 
 1490         { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
 1491     u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
 1492     u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
 1493     int error;
 1494 
 1495     ch->dma->alignment = 16;
 1496     ch->dma->max_iosize = 64 * DEV_BSIZE;
 1497 
 1498     mode = ata_limit_mode(dev, mode, ATA_UDMA2);
 1499 
 1500     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 1501 
 1502     if (bootverbose)
 1503         device_printf(dev, "%ssetting %s on Cyrix chip\n",
 1504                       (error) ? "FAILURE " : "", ata_mode2str(mode));
 1505     if (!error) {
 1506         if (mode >= ATA_UDMA0) {
 1507             ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
 1508                      0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
 1509         }
 1510         else if (mode >= ATA_WDMA0) {
 1511             ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
 1512                      0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
 1513         }
 1514         else {
 1515             ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
 1516                      0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
 1517         }
 1518         atadev->mode = mode;
 1519     }
 1520 }
 1521 
 1522 
 1523 /*
 1524  * Cypress chipset support functions
 1525  */
 1526 int
 1527 ata_cypress_ident(device_t dev)
 1528 {
 1529     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1530 
 1531     /*
 1532      * the Cypress chip is a mess, it contains two ATA functions, but
 1533      * both channels are visible on the first one.
 1534      * simply ignore the second function for now, as the right
 1535      * solution (ignoring the second channel on the first function)
 1536      * doesn't work with the crappy ATA interrupt setup on the alpha.
 1537      */
 1538     if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
 1539         pci_get_function(dev) == 1 &&
 1540         pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
 1541         device_set_desc(dev, "Cypress 82C693 ATA controller");
 1542         ctlr->chipinit = ata_cypress_chipinit;
 1543         return 0;
 1544     }
 1545     return ENXIO;
 1546 }
 1547 
 1548 static int
 1549 ata_cypress_chipinit(device_t dev)
 1550 {
 1551     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1552 
 1553     if (ata_setup_interrupt(dev))
 1554         return ENXIO;
 1555 
 1556     ctlr->setmode = ata_cypress_setmode;
 1557     return 0;
 1558 }
 1559 
 1560 static void
 1561 ata_cypress_setmode(device_t dev, int mode)
 1562 {
 1563     device_t gparent = GRANDPARENT(dev);
 1564     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1565     struct ata_device *atadev = device_get_softc(dev);
 1566     int error;
 1567 
 1568     mode = ata_limit_mode(dev, mode, ATA_WDMA2);
 1569 
 1570     /* XXX SOS missing WDMA0+1 + PIO modes */
 1571     if (mode == ATA_WDMA2) { 
 1572         error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 1573         if (bootverbose)
 1574             device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
 1575                           error ? "FAILURE " : "");
 1576         if (!error) {
 1577             pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
 1578             atadev->mode = mode;
 1579             return;
 1580         }
 1581     }
 1582     /* we could set PIO mode timings, but we assume the BIOS did that */
 1583 }
 1584 
 1585 
 1586 /*
 1587  * HighPoint chipset support functions
 1588  */
 1589 int
 1590 ata_highpoint_ident(device_t dev)
 1591 {
 1592     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1593     struct ata_chip_id *idx;
 1594     static struct ata_chip_id ids[] =
 1595     {{ ATA_HPT374, 0x07, HPT374, 0x00,   ATA_UDMA6, "HPT374" },
 1596      { ATA_HPT372, 0x02, HPT372, 0x00,   ATA_UDMA6, "HPT372N" },
 1597      { ATA_HPT372, 0x01, HPT372, 0x00,   ATA_UDMA6, "HPT372" },
 1598      { ATA_HPT371, 0x01, HPT372, 0x00,   ATA_UDMA6, "HPT371" },
 1599      { ATA_HPT366, 0x05, HPT372, 0x00,   ATA_UDMA6, "HPT372" },
 1600      { ATA_HPT366, 0x03, HPT370, 0x00,   ATA_UDMA5, "HPT370" },
 1601      { ATA_HPT366, 0x02, HPT366, 0x00,   ATA_UDMA4, "HPT368" },
 1602      { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
 1603      { ATA_HPT302, 0x01, HPT372, 0x00,   ATA_UDMA6, "HPT302" },
 1604      { 0, 0, 0, 0, 0, 0}};
 1605     char buffer[64];
 1606 
 1607     if (!(idx = ata_match_chip(dev, ids)))
 1608         return ENXIO;
 1609 
 1610     strcpy(buffer, "HighPoint ");
 1611     strcat(buffer, idx->text);
 1612     if (idx->cfg1 == HPT374) {
 1613         if (pci_get_function(dev) == 0)
 1614             strcat(buffer, " (channel 0+1)");
 1615         if (pci_get_function(dev) == 1)
 1616             strcat(buffer, " (channel 2+3)");
 1617     }
 1618     sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
 1619     device_set_desc_copy(dev, buffer);
 1620     ctlr->chip = idx;
 1621     ctlr->chipinit = ata_highpoint_chipinit;
 1622     return 0;
 1623 }
 1624 
 1625 static int
 1626 ata_highpoint_chipinit(device_t dev)
 1627 {
 1628     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1629 
 1630     if (ata_setup_interrupt(dev))
 1631         return ENXIO;
 1632 
 1633     if (ctlr->chip->cfg2 == HPTOLD) {
 1634         /* disable interrupt prediction */
 1635         pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
 1636     }
 1637     else {
 1638         /* disable interrupt prediction */
 1639         pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
 1640         pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
 1641 
 1642         /* enable interrupts */
 1643         pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
 1644 
 1645         /* set clocks etc */
 1646         if (ctlr->chip->cfg1 < HPT372)
 1647             pci_write_config(dev, 0x5b, 0x22, 1);
 1648         else
 1649             pci_write_config(dev, 0x5b,
 1650                              (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
 1651     }
 1652     ctlr->allocate = ata_highpoint_allocate;
 1653     ctlr->setmode = ata_highpoint_setmode;
 1654     return 0;
 1655 }
 1656 
 1657 static int
 1658 ata_highpoint_allocate(device_t dev)
 1659 {
 1660     struct ata_channel *ch = device_get_softc(dev);
 1661 
 1662     /* setup the usual register normal pci style */
 1663     if (ata_pci_allocate(dev))
 1664         return ENXIO;
 1665 
 1666     ch->flags |= ATA_ALWAYS_DMASTAT;
 1667     return 0;
 1668 }
 1669 
 1670 static void
 1671 ata_highpoint_setmode(device_t dev, int mode)
 1672 {
 1673     device_t gparent = GRANDPARENT(dev);
 1674     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 1675     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1676     struct ata_device *atadev = device_get_softc(dev);
 1677     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 1678     int error;
 1679     u_int32_t timings33[][4] = {
 1680     /*    HPT366      HPT370      HPT372      HPT374               mode */
 1681         { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a },     /* PIO 0 */
 1682         { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 },     /* PIO 1 */
 1683         { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 },     /* PIO 2 */
 1684         { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 },     /* PIO 3 */
 1685         { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 },     /* PIO 4 */
 1686         { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea },     /* MWDMA 0 */
 1687         { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 },     /* MWDMA 1 */
 1688         { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 },     /* MWDMA 2 */
 1689         { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea },     /* UDMA 0 */
 1690         { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 },     /* UDMA 1 */
 1691         { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 },     /* UDMA 2 */
 1692         { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 },     /* UDMA 3 */
 1693         { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 },     /* UDMA 4 */
 1694         { 0,          0x16454e31, 0x1c8a9c62, 0x12848242 },     /* UDMA 5 */
 1695         { 0,          0,          0x1c869c62, 0x12808242 }      /* UDMA 6 */
 1696     };
 1697 
 1698     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 1699 
 1700     if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
 1701         mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
 1702 
 1703     mode = ata_highpoint_check_80pin(dev, mode);
 1704 
 1705     /*
 1706      * most if not all HPT chips cant really handle that the device is
 1707      * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
 1708      * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
 1709      */
 1710     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
 1711                            ata_limit_mode(dev, mode, ATA_UDMA5));
 1712     if (bootverbose)
 1713         device_printf(dev, "%ssetting %s on HighPoint chip\n",
 1714                       (error) ? "FAILURE " : "", ata_mode2str(mode));
 1715     if (!error)
 1716         pci_write_config(gparent, 0x40 + (devno << 2),
 1717                          timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
 1718     atadev->mode = mode;
 1719 }
 1720 
 1721 static int
 1722 ata_highpoint_check_80pin(device_t dev, int mode)
 1723 {
 1724     device_t gparent = GRANDPARENT(dev);
 1725     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 1726     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1727     u_int8_t reg, val, res;
 1728 
 1729     if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
 1730         reg = ch->unit ? 0x57 : 0x53;
 1731         val = pci_read_config(gparent, reg, 1);
 1732         pci_write_config(gparent, reg, val | 0x80, 1);
 1733     }
 1734     else {
 1735         reg = 0x5b;
 1736         val = pci_read_config(gparent, reg, 1);
 1737         pci_write_config(gparent, reg, val & 0xfe, 1);
 1738     }
 1739     res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
 1740     pci_write_config(gparent, reg, val, 1);
 1741 
 1742     if (mode > ATA_UDMA2 && res) {
 1743         ata_print_cable(dev, "controller");
 1744         mode = ATA_UDMA2;
 1745     }
 1746     return mode;
 1747 }
 1748 
 1749 
 1750 /*
 1751  * Intel chipset support functions
 1752  */
 1753 int
 1754 ata_intel_ident(device_t dev)
 1755 {
 1756     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1757     static struct ata_chip_id ids[] =
 1758     {{ ATA_I82371FB,     0,    0, 2, ATA_WDMA2, "PIIX" },
 1759      { ATA_I82371SB,     0,    0, 2, ATA_WDMA2, "PIIX3" },
 1760      { ATA_I82371AB,     0,    0, 2, ATA_UDMA2, "PIIX4" },
 1761      { ATA_I82443MX,     0,    0, 2, ATA_UDMA2, "PIIX4" },
 1762      { ATA_I82451NX,     0,    0, 2, ATA_UDMA2, "PIIX4" },
 1763      { ATA_I82801AB,     0,    0, 2, ATA_UDMA2, "ICH0" },
 1764      { ATA_I82801AA,     0,    0, 2, ATA_UDMA4, "ICH" },
 1765      { ATA_I82372FB,     0,    0, 2, ATA_UDMA4, "ICH" },
 1766      { ATA_I82801BA,     0,    0, 2, ATA_UDMA5, "ICH2" },
 1767      { ATA_I82801BA_1,   0,    0, 2, ATA_UDMA5, "ICH2" },
 1768      { ATA_I82801CA,     0,    0, 2, ATA_UDMA5, "ICH3" },
 1769      { ATA_I82801CA_1,   0,    0, 2, ATA_UDMA5, "ICH3" },
 1770      { ATA_I82801DB,     0,    0, 2, ATA_UDMA5, "ICH4" },
 1771      { ATA_I82801DB_1,   0,    0, 2, ATA_UDMA5, "ICH4" },
 1772      { ATA_I82801EB,     0,    0, 2, ATA_UDMA5, "ICH5" },
 1773      { ATA_I82801EB_S1,  0,    0, 2, ATA_SA150, "ICH5" },
 1774      { ATA_I82801EB_R1,  0,    0, 2, ATA_SA150, "ICH5" },
 1775      { ATA_I6300ESB,     0,    0, 2, ATA_UDMA5, "6300ESB" },
 1776      { ATA_I6300ESB_S1,  0,    0, 2, ATA_SA150, "6300ESB" },
 1777      { ATA_I6300ESB_R1,  0,    0, 2, ATA_SA150, "6300ESB" },
 1778      { ATA_I82801FB,     0,    0, 2, ATA_UDMA5, "ICH6" },
 1779      { ATA_I82801FB_S1,  0, AHCI, 0, ATA_SA150, "ICH6" },
 1780      { ATA_I82801FB_R1,  0, AHCI, 0, ATA_SA150, "ICH6" },
 1781      { ATA_I82801FBM,    0, AHCI, 0, ATA_SA150, "ICH6M" },
 1782      { ATA_I82801GB,     0,    0, 1, ATA_UDMA5, "ICH7" },
 1783      { ATA_I82801GB_S1,  0, AHCI, 0, ATA_SA300, "ICH7" },
 1784      { ATA_I82801GB_R1,  0, AHCI, 0, ATA_SA300, "ICH7" },
 1785      { ATA_I82801GB_AH,  0, AHCI, 0, ATA_SA300, "ICH7" },
 1786      { ATA_I82801GBM_S1, 0, AHCI, 0, ATA_SA300, "ICH7M" },
 1787      { ATA_I82801GBM_R1, 0, AHCI, 0, ATA_SA300, "ICH7M" },
 1788      { ATA_I82801GBM_AH, 0, AHCI, 0, ATA_SA300, "ICH7M" },
 1789      { ATA_I63XXESB2,    0,    0, 1, ATA_UDMA5, "63XXESB2" },
 1790      { ATA_I63XXESB2_S1, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
 1791      { ATA_I63XXESB2_S2, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
 1792      { ATA_I63XXESB2_R1, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
 1793      { ATA_I63XXESB2_R2, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
 1794      { ATA_I82801HB_S1,  0, AHCI, 0, ATA_SA300, "ICH8" },
 1795      { ATA_I82801HB_S2,  0, AHCI, 0, ATA_SA300, "ICH8" },
 1796      { ATA_I82801HB_R1,  0, AHCI, 0, ATA_SA300, "ICH8" },
 1797      { ATA_I82801HB_AH4, 0, AHCI, 0, ATA_SA300, "ICH8" },
 1798      { ATA_I82801HB_AH6, 0, AHCI, 0, ATA_SA300, "ICH8" },
 1799      { ATA_I82801HBM,    0,    0, 1, ATA_UDMA5, "ICH8M" },
 1800      { ATA_I82801HBM_S1, 0, AHCI, 0, ATA_SA300, "ICH8M" },
 1801      { ATA_I82801HBM_S2, 0, AHCI, 0, ATA_SA300, "ICH8M" },
 1802      { ATA_I82801HBM_S3, 0, AHCI, 0, ATA_SA300, "ICH8M" },
 1803      { ATA_I82801IB_S1,  0, AHCI, 0, ATA_SA300, "ICH9" },
 1804      { ATA_I82801IB_S2,  0, AHCI, 0, ATA_SA300, "ICH9" },
 1805      { ATA_I82801IB_AH2, 0, AHCI, 0, ATA_SA300, "ICH9" },
 1806      { ATA_I82801IB_AH4, 0, AHCI, 0, ATA_SA300, "ICH9" },
 1807      { ATA_I82801IB_AH6, 0, AHCI, 0, ATA_SA300, "ICH9" },
 1808      { ATA_I82801IB_R1,  0, AHCI, 0, ATA_SA300, "ICH9" },
 1809      { ATA_I82801JIB_S1, 0, AHCI, 0, ATA_SA300, "ICH10" },
 1810      { ATA_I82801JIB_AH, 0, AHCI, 0, ATA_SA300, "ICH10" },
 1811      { ATA_I82801JIB_R1, 0, AHCI, 0, ATA_SA300, "ICH10" },
 1812      { ATA_I82801JIB_S2, 0, AHCI, 0, ATA_SA300, "ICH10" },
 1813      { ATA_I82801JD_S1,  0, AHCI, 0, ATA_SA300, "ICH10" },
 1814      { ATA_I82801JD_AH,  0, AHCI, 0, ATA_SA300, "ICH10" },
 1815      { ATA_I82801JD_R1,  0, AHCI, 0, ATA_SA300, "ICH10" },
 1816      { ATA_I82801JD_S2,  0, AHCI, 0, ATA_SA300, "ICH10" },
 1817      { ATA_I31244,       0,    0, 2, ATA_SA150, "31244" },
 1818      { 0, 0, 0, 0, 0, 0}};
 1819 
 1820     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 1821         return ENXIO;
 1822 
 1823     ata_set_desc(dev);
 1824     ctlr->chipinit = ata_intel_chipinit;
 1825     return 0;
 1826 }
 1827 
 1828 static int
 1829 ata_intel_chipinit(device_t dev)
 1830 {
 1831     struct ata_pci_controller *ctlr = device_get_softc(dev);
 1832 
 1833     if (ata_setup_interrupt(dev))
 1834         return ENXIO;
 1835 
 1836     /* good old PIIX needs special treatment (not implemented) */
 1837     if (ctlr->chip->chipid == ATA_I82371FB) {
 1838         ctlr->setmode = ata_intel_old_setmode;
 1839     }
 1840 
 1841     /* the intel 31244 needs special care if in DPA mode */
 1842     else if (ctlr->chip->chipid == ATA_I31244) {
 1843         if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
 1844             ctlr->r_type2 = SYS_RES_MEMORY;
 1845             ctlr->r_rid2 = PCIR_BAR(0);
 1846             if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 1847                                                         &ctlr->r_rid2,
 1848                                                         RF_ACTIVE)))
 1849                 return ENXIO;
 1850             ctlr->channels = 4;
 1851             ctlr->allocate = ata_intel_31244_allocate;
 1852             ctlr->reset = ata_intel_31244_reset;
 1853         }
 1854         ctlr->setmode = ata_sata_setmode;
 1855     }
 1856 
 1857     /* non SATA intel chips goes here */
 1858     else if (ctlr->chip->max_dma < ATA_SA150) {
 1859         ctlr->channels = ctlr->chip->cfg2;
 1860         ctlr->allocate = ata_intel_allocate;
 1861         ctlr->setmode = ata_intel_new_setmode;
 1862     }
 1863 
 1864     /* SATA parts can be either compat or AHCI */
 1865     else {
 1866         /* force all ports active "the legacy way" */
 1867         pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
 1868 
 1869         ctlr->allocate = ata_intel_allocate;
 1870         ctlr->reset = ata_intel_reset;
 1871 
 1872         /* 
 1873          * if we have AHCI capability and AHCI or RAID mode enabled
 1874          * in BIOS we try for AHCI mode
 1875          */ 
 1876         if ((ctlr->chip->cfg1 == AHCI) &&
 1877             (pci_read_config(dev, 0x90, 1) & 0xc0) &&
 1878             (ata_ahci_chipinit(dev) != ENXIO))
 1879             return 0;
 1880         
 1881         /* if BAR(5) is IO it should point to SATA interface registers */
 1882         ctlr->r_type2 = SYS_RES_IOPORT;
 1883         ctlr->r_rid2 = PCIR_BAR(5);
 1884         if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 1885                                                    &ctlr->r_rid2, RF_ACTIVE)))
 1886             ctlr->setmode = ata_intel_sata_setmode;
 1887         else
 1888             ctlr->setmode = ata_sata_setmode;
 1889     }
 1890     return 0;
 1891 }
 1892 
 1893 static int
 1894 ata_intel_allocate(device_t dev)
 1895 {
 1896     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 1897     struct ata_channel *ch = device_get_softc(dev);
 1898 
 1899     /* setup the usual register normal pci style */
 1900     if (ata_pci_allocate(dev))
 1901         return ENXIO;
 1902 
 1903     /* if r_res2 is valid it points to SATA interface registers */
 1904     if (ctlr->r_res2) {
 1905         ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
 1906         ch->r_io[ATA_IDX_ADDR].offset = 0x00;
 1907         ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
 1908         ch->r_io[ATA_IDX_DATA].offset = 0x04;
 1909     }
 1910 
 1911     ch->flags |= ATA_ALWAYS_DMASTAT;
 1912     return 0;
 1913 }
 1914 
 1915 static void
 1916 ata_intel_reset(device_t dev)
 1917 {
 1918     device_t parent = device_get_parent(dev);
 1919     struct ata_pci_controller *ctlr = device_get_softc(parent);
 1920     struct ata_channel *ch = device_get_softc(dev);
 1921     int mask, timeout;
 1922 
 1923     /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
 1924     if (ctlr->chip->cfg1) {
 1925         mask = (0x0005 << ch->unit);
 1926     }
 1927     else {
 1928         /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
 1929         if (pci_read_config(parent, 0x90, 1) & 0x04)
 1930             mask = 0x0003;
 1931         else {
 1932             mask = (0x0001 << ch->unit);
 1933             /* XXX SOS should be in intel_allocate if we grow it */
 1934             ch->flags |= ATA_NO_SLAVE;
 1935         }
 1936     }
 1937     pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
 1938     DELAY(10);
 1939     pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
 1940 
 1941     /* wait up to 1 sec for "connect well" */
 1942     for (timeout = 0; timeout < 100 ; timeout++) {
 1943         if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
 1944             (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
 1945             break;
 1946         ata_udelay(10000);
 1947     }
 1948     ata_generic_reset(dev);
 1949 }
 1950 
 1951 static void
 1952 ata_intel_old_setmode(device_t dev, int mode)
 1953 {
 1954     /* NOT YET */
 1955 }
 1956 
 1957 static void
 1958 ata_intel_new_setmode(device_t dev, int mode)
 1959 {
 1960     device_t gparent = GRANDPARENT(dev);
 1961     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 1962     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 1963     struct ata_device *atadev = device_get_softc(dev);
 1964     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 1965     u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
 1966     u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
 1967     u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
 1968     u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
 1969     u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
 1970     u_int32_t mask40 = 0, new40 = 0;
 1971     u_int8_t mask44 = 0, new44 = 0;
 1972     int error;
 1973     u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
 1974                            0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
 1975 
 1976     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 1977 
 1978     if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
 1979         ata_print_cable(dev, "controller");
 1980         mode = ATA_UDMA2;
 1981     }
 1982 
 1983     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 1984 
 1985     if (bootverbose)
 1986         device_printf(dev, "%ssetting %s on %s chip\n",
 1987                       (error) ? "FAILURE " : "",
 1988                       ata_mode2str(mode), ctlr->chip->text);
 1989     if (!error) {
 1990         if (mode >= ATA_UDMA0) {
 1991             u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
 1992 
 1993             pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
 1994             pci_write_config(gparent, 0x4a,
 1995                              (reg4a & ~(0x3 << (devno << 2))) |
 1996                              (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
 1997         }
 1998         else {
 1999             pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
 2000             pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
 2001         }
 2002         reg54 |= 0x0400;
 2003         if (mode >= ATA_UDMA2)
 2004             reg54 |= (0x1 << devno);
 2005         else
 2006             reg54 &= ~(0x1 << devno);
 2007         if (mode >= ATA_UDMA5)
 2008             reg54 |= (0x1000 << devno);
 2009         else 
 2010             reg54 &= ~(0x1000 << devno);
 2011 
 2012         pci_write_config(gparent, 0x54, reg54, 2);
 2013 
 2014         reg40 &= ~0x00ff00ff;
 2015         reg40 |= 0x40774077;
 2016 
 2017         if (atadev->unit == ATA_MASTER) {
 2018             mask40 = 0x3300;
 2019             new40 = timings[ata_mode2idx(mode)] << 8;
 2020         }
 2021         else {
 2022             mask44 = 0x0f;
 2023             new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
 2024                     (timings[ata_mode2idx(mode)] & 0x03);
 2025         }
 2026         if (ch->unit) {
 2027             mask40 <<= 16;
 2028             new40 <<= 16;
 2029             mask44 <<= 4;
 2030             new44 <<= 4;
 2031         }
 2032         pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
 2033         pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
 2034 
 2035         atadev->mode = mode;
 2036     }
 2037 }
 2038 
 2039 static void
 2040 ata_intel_sata_setmode(device_t dev, int mode)
 2041 {
 2042     struct ata_device *atadev = device_get_softc(dev);
 2043 
 2044     if (atadev->param.satacapabilities != 0x0000 &&
 2045         atadev->param.satacapabilities != 0xffff) {
 2046 
 2047         struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 2048         int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 2049 
 2050         /* on some drives we need to set the transfer mode */
 2051         ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
 2052                        ata_limit_mode(dev, mode, ATA_UDMA6));
 2053 
 2054         /* set ATA_SSTATUS register offset */
 2055         ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
 2056 
 2057         /* query SATA STATUS for the speed */
 2058         if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
 2059             ATA_SS_CONWELL_GEN2)
 2060             atadev->mode = ATA_SA300;
 2061         else
 2062             atadev->mode = ATA_SA150;
 2063     }
 2064     else {
 2065         mode = ata_limit_mode(dev, mode, ATA_UDMA5);
 2066         if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
 2067             atadev->mode = mode;
 2068     }
 2069 }
 2070 
 2071 static int
 2072 ata_intel_31244_allocate(device_t dev)
 2073 {
 2074     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2075     struct ata_channel *ch = device_get_softc(dev);
 2076     int i;
 2077     int ch_offset;
 2078 
 2079     ch_offset = 0x200 + ch->unit * 0x200;
 2080 
 2081     for (i = ATA_DATA; i < ATA_MAX_RES; i++)
 2082         ch->r_io[i].res = ctlr->r_res2;
 2083 
 2084     /* setup ATA registers */
 2085     ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
 2086     ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
 2087     ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
 2088     ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
 2089     ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
 2090     ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
 2091     ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
 2092     ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
 2093     ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
 2094     ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
 2095     ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
 2096     ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
 2097 
 2098     /* setup DMA registers */
 2099     ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
 2100     ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
 2101     ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
 2102 
 2103     /* setup SATA registers */
 2104     ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
 2105     ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
 2106     ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
 2107 
 2108     ch->flags |= ATA_NO_SLAVE;
 2109     ata_pci_hw(dev);
 2110     ch->hw.status = ata_intel_31244_status;
 2111     ch->hw.tf_write = ata_intel_31244_tf_write;
 2112 
 2113     /* enable PHY state change interrupt */
 2114     ATA_OUTL(ctlr->r_res2, 0x4,
 2115              ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
 2116     return 0;
 2117 }
 2118 
 2119 static int
 2120 ata_intel_31244_status(device_t dev)
 2121 {
 2122     /* do we have any PHY events ? */
 2123     ata_sata_phy_check_events(dev);
 2124 
 2125     /* any drive action to take care of ? */
 2126     return ata_pci_status(dev);
 2127 }
 2128 
 2129 static void
 2130 ata_intel_31244_tf_write(struct ata_request *request)
 2131 {
 2132     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 2133     struct ata_device *atadev = device_get_softc(request->dev);
 2134 
 2135     if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 2136         ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
 2137         ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
 2138         ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
 2139                                       (request->u.ata.lba & 0x00ff));
 2140         ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
 2141                                        ((request->u.ata.lba >> 8) & 0x00ff));
 2142         ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 
 2143                                        ((request->u.ata.lba >> 16) & 0x00ff));
 2144         ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
 2145     }
 2146     else {
 2147         ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
 2148         ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
 2149         if (atadev->flags & ATA_D_USE_CHS) {
 2150             int heads, sectors;
 2151     
 2152             if (atadev->param.atavalid & ATA_FLAG_54_58) {
 2153                 heads = atadev->param.current_heads;
 2154                 sectors = atadev->param.current_sectors;
 2155             }
 2156             else {
 2157                 heads = atadev->param.heads;
 2158                 sectors = atadev->param.sectors;
 2159             }
 2160             ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
 2161             ATA_IDX_OUTB(ch, ATA_CYL_LSB,
 2162                          (request->u.ata.lba / (sectors * heads)));
 2163             ATA_IDX_OUTB(ch, ATA_CYL_MSB,
 2164                          (request->u.ata.lba / (sectors * heads)) >> 8);
 2165             ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 
 2166                          (((request->u.ata.lba% (sectors * heads)) /
 2167                            sectors) & 0xf));
 2168         }
 2169         else {
 2170             ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
 2171             ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
 2172             ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
 2173             ATA_IDX_OUTB(ch, ATA_DRIVE,
 2174                          ATA_D_IBM | ATA_D_LBA | atadev->unit |
 2175                          ((request->u.ata.lba >> 24) & 0x0f));
 2176         }
 2177     }
 2178 }
 2179 
 2180 static void
 2181 ata_intel_31244_reset(device_t dev)
 2182 {
 2183     if (ata_sata_phy_reset(dev))
 2184         ata_generic_reset(dev);
 2185 }
 2186 
 2187 
 2188 /*
 2189  * Integrated Technology Express Inc. (ITE) chipset support functions
 2190  */
 2191 int
 2192 ata_ite_ident(device_t dev)
 2193 {
 2194     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2195     static struct ata_chip_id ids[] =
 2196     {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" },
 2197      { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
 2198      { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
 2199      { 0, 0, 0, 0, 0, 0}};
 2200 
 2201     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 2202         return ENXIO;
 2203 
 2204     ata_set_desc(dev);
 2205     ctlr->chipinit = ata_ite_chipinit;
 2206     return 0;
 2207 }
 2208 
 2209 static int
 2210 ata_ite_chipinit(device_t dev)
 2211 {
 2212     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2213 
 2214     if (ata_setup_interrupt(dev))
 2215         return ENXIO;
 2216 
 2217     if (ctlr->chip->chipid == ATA_IT8213F) {
 2218         /* the ITE 8213F only has one channel */
 2219         ctlr->channels = 1;
 2220 
 2221         ctlr->setmode = ata_ite_8213_setmode;
 2222     }
 2223     else {
 2224         /* set PCI mode and 66Mhz reference clock */
 2225         pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
 2226 
 2227         /* set default active & recover timings */
 2228         pci_write_config(dev, 0x54, 0x31, 1);
 2229         pci_write_config(dev, 0x56, 0x31, 1);
 2230 
 2231         ctlr->setmode = ata_ite_821x_setmode;
 2232     }
 2233 
 2234     return 0;
 2235 }
 2236  
 2237 static void
 2238 ata_ite_821x_setmode(device_t dev, int mode)
 2239 {
 2240     device_t gparent = GRANDPARENT(dev);
 2241     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 2242     struct ata_device *atadev = device_get_softc(dev);
 2243     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 2244     int error;
 2245 
 2246     /* correct the mode for what the HW supports */
 2247     mode = ata_limit_mode(dev, mode, ATA_UDMA6);
 2248 
 2249     /* check the CBLID bits for 80 conductor cable detection */
 2250     if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
 2251                              (ch->unit ? (1<<3) : (1<<2)))) {
 2252         ata_print_cable(dev, "controller");
 2253         mode = ATA_UDMA2;
 2254     }
 2255 
 2256     /* set the wanted mode on the device */
 2257     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 2258 
 2259     if (bootverbose)
 2260         device_printf(dev, "%s setting %s on ITE8212F chip\n",
 2261                       (error) ? "failed" : "success", ata_mode2str(mode));
 2262 
 2263     /* if the device accepted the mode change, setup the HW accordingly */
 2264     if (!error) {
 2265         if (mode >= ATA_UDMA0) {
 2266             u_int8_t udmatiming[] =
 2267                 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
 2268 
 2269             /* enable UDMA mode */
 2270             pci_write_config(gparent, 0x50,
 2271                              pci_read_config(gparent, 0x50, 1) &
 2272                              ~(1 << (devno + 3)), 1);
 2273 
 2274             /* set UDMA timing */
 2275             pci_write_config(gparent,
 2276                              0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
 2277                              udmatiming[mode & ATA_MODE_MASK], 1);
 2278         }
 2279         else {
 2280             u_int8_t chtiming[] =
 2281                 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
 2282 
 2283             /* disable UDMA mode */
 2284             pci_write_config(gparent, 0x50,
 2285                              pci_read_config(gparent, 0x50, 1) |
 2286                              (1 << (devno + 3)), 1);
 2287 
 2288             /* set active and recover timing (shared between master & slave) */
 2289             if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
 2290                 chtiming[ata_mode2idx(mode)])
 2291                 pci_write_config(gparent, 0x54 + (ch->unit << 2),
 2292                                  chtiming[ata_mode2idx(mode)], 1);
 2293         }
 2294         atadev->mode = mode;
 2295     }
 2296 }
 2297 
 2298 static void
 2299 ata_ite_8213_setmode(device_t dev, int mode)
 2300 {
 2301     device_t gparent = GRANDPARENT(dev);
 2302     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 2303     struct ata_device *atadev = device_get_softc(dev);
 2304     u_int16_t reg40 = pci_read_config(gparent, 0x40, 2);
 2305     u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
 2306     u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
 2307     u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
 2308     u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
 2309     u_int16_t mask40 = 0, new40 = 0;
 2310     u_int8_t mask44 = 0, new44 = 0;
 2311     int devno = atadev->unit;
 2312     int error;
 2313     u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
 2314                            0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
 2315 
 2316     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 2317 
 2318     if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
 2319         ata_print_cable(dev, "controller");
 2320         mode = ATA_UDMA2;
 2321     }
 2322 
 2323     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 2324 
 2325     if (bootverbose)
 2326         device_printf(dev, "%ssetting %s on %s chip\n",
 2327                       (error) ? "FAILURE " : "",
 2328                       ata_mode2str(mode), ctlr->chip->text);
 2329     if (!error) {
 2330         if (mode >= ATA_UDMA0) {
 2331             u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
 2332 
 2333             pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
 2334             pci_write_config(gparent, 0x4a,
 2335                              (reg4a & ~(0x3 << (devno << 2))) |
 2336                              (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
 2337         }
 2338         else {
 2339             pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
 2340             pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
 2341         }
 2342         if (mode >= ATA_UDMA2)
 2343             reg54 |= (0x1 << devno);
 2344         else
 2345             reg54 &= ~(0x1 << devno);
 2346         if (mode >= ATA_UDMA5)
 2347             reg54 |= (0x1000 << devno);
 2348         else 
 2349             reg54 &= ~(0x1000 << devno);
 2350         pci_write_config(gparent, 0x54, reg54, 2);
 2351 
 2352         reg40 &= 0xff00;
 2353         reg40 |= 0x4033;
 2354         if (atadev->unit == ATA_MASTER) {
 2355             reg40 |= (ata_atapi(dev) ? 0x04 : 0x00);
 2356             mask40 = 0x3300;
 2357             new40 = timings[ata_mode2idx(mode)] << 8;
 2358         }
 2359         else {
 2360             reg40 |= (ata_atapi(dev) ? 0x40 : 0x00);
 2361             mask44 = 0x0f;
 2362             new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
 2363                     (timings[ata_mode2idx(mode)] & 0x03);
 2364         }
 2365         pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
 2366         pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
 2367 
 2368         atadev->mode = mode;
 2369     }
 2370 }
 2371 
 2372 
 2373 /*
 2374  * JMicron chipset support functions
 2375  */
 2376 int
 2377 ata_jmicron_ident(device_t dev)
 2378 {
 2379     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2380     struct ata_chip_id *idx;
 2381     static struct ata_chip_id ids[] =
 2382     {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
 2383      { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
 2384      { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
 2385      { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
 2386      { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
 2387      { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
 2388      { 0, 0, 0, 0, 0, 0}};
 2389     char buffer[64];
 2390 
 2391     if (!(idx = ata_match_chip(dev, ids)))
 2392         return ENXIO;
 2393 
 2394     if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
 2395         (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
 2396         sprintf(buffer, "JMicron %s %s controller",
 2397                 idx->text, ata_mode2str(ATA_UDMA6));
 2398     else
 2399         sprintf(buffer, "JMicron %s %s controller",
 2400                 idx->text, ata_mode2str(idx->max_dma));
 2401     device_set_desc_copy(dev, buffer);
 2402     ctlr->chip = idx;
 2403     ctlr->chipinit = ata_jmicron_chipinit;
 2404     return 0;
 2405 }
 2406 
 2407 static int
 2408 ata_jmicron_chipinit(device_t dev)
 2409 {
 2410     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2411     int error;
 2412 
 2413     if (ata_setup_interrupt(dev))
 2414         return ENXIO;
 2415 
 2416     /* do we have multiple PCI functions ? */
 2417     if (pci_read_config(dev, 0xdf, 1) & 0x40) {
 2418         /* are we on the AHCI part ? */
 2419         if (ata_ahci_chipinit(dev) != ENXIO)
 2420             return 0;
 2421 
 2422         /* otherwise we are on the PATA part */
 2423         ctlr->allocate = ata_pci_allocate;
 2424         ctlr->reset = ata_generic_reset;
 2425         ctlr->dmainit = ata_pci_dmainit;
 2426         ctlr->setmode = ata_jmicron_setmode;
 2427         ctlr->channels = ctlr->chip->cfg2;
 2428     }
 2429     else {
 2430         /* set controller configuration to a combined setup we support */
 2431         pci_write_config(dev, 0x40, 0x80c0a131, 4);
 2432         pci_write_config(dev, 0x80, 0x01200000, 4);
 2433 
 2434         if (ctlr->chip->cfg1 && (error = ata_ahci_chipinit(dev)))
 2435             return error;
 2436 
 2437         ctlr->allocate = ata_jmicron_allocate;
 2438         ctlr->reset = ata_jmicron_reset;
 2439         ctlr->dmainit = ata_jmicron_dmainit;
 2440         ctlr->setmode = ata_jmicron_setmode;
 2441 
 2442         /* set the number of HW channels */ 
 2443         ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
 2444     }
 2445     return 0;
 2446 }
 2447 
 2448 static int
 2449 ata_jmicron_allocate(device_t dev)
 2450 {
 2451     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2452     struct ata_channel *ch = device_get_softc(dev);
 2453     int error;
 2454 
 2455     if (ch->unit >= ctlr->chip->cfg1) {
 2456         ch->unit -= ctlr->chip->cfg1;
 2457         error = ata_pci_allocate(dev);
 2458         ch->unit += ctlr->chip->cfg1;
 2459     }
 2460     else
 2461         error = ata_ahci_allocate(dev);
 2462     return error;
 2463 }
 2464 
 2465 static void
 2466 ata_jmicron_reset(device_t dev)
 2467 {
 2468     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2469     struct ata_channel *ch = device_get_softc(dev);
 2470 
 2471     if (ch->unit >= ctlr->chip->cfg1)
 2472         ata_generic_reset(dev);
 2473     else
 2474         ata_ahci_reset(dev);
 2475 }
 2476 
 2477 static void
 2478 ata_jmicron_dmainit(device_t dev)
 2479 {
 2480     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2481     struct ata_channel *ch = device_get_softc(dev);
 2482 
 2483     if (ch->unit >= ctlr->chip->cfg1)
 2484         ata_pci_dmainit(dev);
 2485     else
 2486         ata_ahci_dmainit(dev);
 2487 }
 2488 
 2489 static void
 2490 ata_jmicron_setmode(device_t dev, int mode)
 2491 {
 2492     struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
 2493     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 2494 
 2495     if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
 2496         struct ata_device *atadev = device_get_softc(dev);
 2497 
 2498         /* check for 80pin cable present */
 2499         if (pci_read_config(dev, 0x40, 1) & 0x08)
 2500             mode = ata_limit_mode(dev, mode, ATA_UDMA2);
 2501         else
 2502             mode = ata_limit_mode(dev, mode, ATA_UDMA6);
 2503 
 2504         if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
 2505             atadev->mode = mode;
 2506     }
 2507     else
 2508         ata_sata_setmode(dev, mode);
 2509 }
 2510 
 2511 
 2512 /*
 2513  * Marvell chipset support functions
 2514  */
 2515 #define ATA_MV_HOST_BASE(ch) \
 2516         ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
 2517 #define ATA_MV_EDMA_BASE(ch) \
 2518         ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
 2519 
 2520 struct ata_marvell_response {
 2521     u_int16_t   tag;
 2522     u_int8_t    edma_status;
 2523     u_int8_t    dev_status;
 2524     u_int32_t   timestamp;
 2525 };
 2526 
 2527 struct ata_marvell_dma_prdentry {
 2528     u_int32_t addrlo;
 2529     u_int32_t count;
 2530     u_int32_t addrhi;
 2531     u_int32_t reserved;
 2532 };  
 2533 
 2534 int
 2535 ata_marvell_ident(device_t dev)
 2536 {
 2537     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2538     static struct ata_chip_id ids[] =
 2539     {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
 2540      { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
 2541      { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
 2542      { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
 2543      { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
 2544      { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
 2545      { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
 2546      { ATA_M88SX6121, 0, 1, MV61XX, ATA_UDMA6, "88SX6121" },
 2547      { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
 2548      { 0, 0, 0, 0, 0, 0}};
 2549 
 2550     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 2551         return ENXIO;
 2552 
 2553     ata_set_desc(dev);
 2554 
 2555     switch (ctlr->chip->cfg2) {
 2556     case MV50XX:
 2557     case MV60XX:
 2558         ctlr->chipinit = ata_marvell_edma_chipinit;
 2559         break;
 2560     case MV61XX:
 2561         ctlr->chipinit = ata_marvell_pata_chipinit;
 2562         break;
 2563     }
 2564     return 0;
 2565 }
 2566 
 2567 static int
 2568 ata_marvell_pata_chipinit(device_t dev)
 2569 {
 2570     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2571 
 2572     if (ata_setup_interrupt(dev))
 2573         return ENXIO;
 2574 
 2575     ctlr->allocate = ata_marvell_pata_allocate;
 2576     ctlr->setmode = ata_marvell_pata_setmode;
 2577     ctlr->channels = ctlr->chip->cfg1;
 2578     return 0;
 2579 }
 2580 
 2581 static int
 2582 ata_marvell_pata_allocate(device_t dev)
 2583 {
 2584     struct ata_channel *ch = device_get_softc(dev);
 2585  
 2586     /* setup the usual register normal pci style */
 2587     if (ata_pci_allocate(dev))
 2588         return ENXIO;
 2589  
 2590     /* dont use 32 bit PIO transfers */
 2591         ch->flags |= ATA_USE_16BIT;
 2592 
 2593     return 0;
 2594 }
 2595 
 2596 static void
 2597 ata_marvell_pata_setmode(device_t dev, int mode)
 2598 {
 2599     device_t gparent = GRANDPARENT(dev);
 2600     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 2601     struct ata_device *atadev = device_get_softc(dev);
 2602 
 2603     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 2604     mode = ata_check_80pin(dev, mode);
 2605     if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
 2606         atadev->mode = mode;
 2607 }
 2608 
 2609 static int
 2610 ata_marvell_edma_chipinit(device_t dev)
 2611 {
 2612     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2613 
 2614     if (ata_setup_interrupt(dev))
 2615         return ENXIO;
 2616 
 2617     ctlr->r_type1 = SYS_RES_MEMORY;
 2618     ctlr->r_rid1 = PCIR_BAR(0);
 2619     if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
 2620                                                 &ctlr->r_rid1, RF_ACTIVE)))
 2621         return ENXIO;
 2622 
 2623     /* mask all host controller interrupts */
 2624     ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
 2625 
 2626     /* mask all PCI interrupts */
 2627     ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
 2628 
 2629     ctlr->allocate = ata_marvell_edma_allocate;
 2630     ctlr->reset = ata_marvell_edma_reset;
 2631     ctlr->dmainit = ata_marvell_edma_dmainit;
 2632     ctlr->setmode = ata_sata_setmode;
 2633     ctlr->channels = ctlr->chip->cfg1;
 2634 
 2635     /* clear host controller interrupts */
 2636     ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
 2637     if (ctlr->chip->cfg1 > 4)
 2638         ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
 2639 
 2640     /* clear PCI interrupts */
 2641     ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
 2642 
 2643     /* unmask PCI interrupts we want */
 2644     ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
 2645 
 2646     /* unmask host controller interrupts we want */
 2647     ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
 2648              /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
 2649     return 0;
 2650 }
 2651 
 2652 static int
 2653 ata_marvell_edma_allocate(device_t dev)
 2654 {
 2655     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2656     struct ata_channel *ch = device_get_softc(dev);
 2657     u_int64_t work = ch->dma->work_bus;
 2658     int i;
 2659 
 2660     /* clear work area */
 2661     bzero(ch->dma->work, 1024+256);
 2662 
 2663     /* set legacy ATA resources */
 2664     for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
 2665         ch->r_io[i].res = ctlr->r_res1;
 2666         ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
 2667     }
 2668     ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
 2669     ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
 2670     ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
 2671     ata_default_registers(dev);
 2672 
 2673     /* set SATA resources */
 2674     switch (ctlr->chip->cfg2) {
 2675     case MV50XX:
 2676         ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
 2677         ch->r_io[ATA_SSTATUS].offset =  0x00100 + ATA_MV_HOST_BASE(ch);
 2678         ch->r_io[ATA_SERROR].res = ctlr->r_res1;
 2679         ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
 2680         ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
 2681         ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
 2682         break;
 2683     case MV60XX:
 2684         ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
 2685         ch->r_io[ATA_SSTATUS].offset =  0x02300 + ATA_MV_EDMA_BASE(ch);
 2686         ch->r_io[ATA_SERROR].res = ctlr->r_res1;
 2687         ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
 2688         ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
 2689         ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
 2690         ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
 2691         ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
 2692         break;
 2693     }
 2694 
 2695     ch->flags |= ATA_NO_SLAVE;
 2696     ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
 2697     ata_generic_hw(dev);
 2698     ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
 2699     ch->hw.end_transaction = ata_marvell_edma_end_transaction;
 2700     ch->hw.status = ata_marvell_edma_status;
 2701 
 2702     /* disable the EDMA machinery */
 2703     ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
 2704     DELAY(100000);       /* SOS should poll for disabled */
 2705 
 2706     /* set configuration to non-queued 128b read transfers stop on error */
 2707     ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
 2708 
 2709     /* request queue base high */
 2710     ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
 2711 
 2712     /* request queue in ptr */
 2713     ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
 2714 
 2715     /* request queue out ptr */
 2716     ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
 2717 
 2718     /* response queue base high */
 2719     work += 1024;
 2720     ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
 2721 
 2722     /* response queue in ptr */
 2723     ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
 2724 
 2725     /* response queue out ptr */
 2726     ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
 2727 
 2728     /* clear SATA error register */
 2729     ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
 2730 
 2731     /* clear any outstanding error interrupts */
 2732     ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
 2733 
 2734     /* unmask all error interrupts */
 2735     ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
 2736     
 2737     /* enable EDMA machinery */
 2738     ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
 2739     return 0;
 2740 }
 2741 
 2742 static int
 2743 ata_marvell_edma_status(device_t dev)
 2744 {
 2745     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2746     struct ata_channel *ch = device_get_softc(dev);
 2747     u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
 2748     int shift = (ch->unit << 1) + (ch->unit > 3);
 2749 
 2750     if (cause & (1 << shift)) {
 2751 
 2752         /* clear interrupt(s) */
 2753         ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
 2754 
 2755         /* do we have any PHY events ? */
 2756         ata_sata_phy_check_events(dev);
 2757     }
 2758 
 2759     /* do we have any device action ? */
 2760     return (cause & (2 << shift));
 2761 }
 2762 
 2763 /* must be called with ATA channel locked and state_mtx held */
 2764 static int
 2765 ata_marvell_edma_begin_transaction(struct ata_request *request)
 2766 {
 2767     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
 2768     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 2769     u_int32_t req_in;
 2770     u_int8_t *bytep;
 2771     u_int16_t *wordp;
 2772     u_int32_t *quadp;
 2773     int i, tag = 0x07;
 2774     int dummy, error, slot;
 2775 
 2776     /* only DMA R/W goes through the EMDA machine */
 2777     if (request->u.ata.command != ATA_READ_DMA &&
 2778         request->u.ata.command != ATA_WRITE_DMA) {
 2779 
 2780         /* disable the EDMA machinery */
 2781         if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
 2782             ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
 2783         return ata_begin_transaction(request);
 2784     }
 2785 
 2786     /* check for 48 bit access and convert if needed */
 2787     ata_modify_if_48bit(request);
 2788 
 2789     /* check sanity, setup SG list and DMA engine */
 2790     if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
 2791                                request->flags & ATA_R_READ, ch->dma->sg,
 2792                                &dummy))) {
 2793         device_printf(request->dev, "setting up DMA failed\n");
 2794         request->result = error;
 2795         return ATA_OP_FINISHED;
 2796     }
 2797 
 2798     /* get next free request queue slot */
 2799     req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
 2800     slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
 2801     bytep = (u_int8_t *)(ch->dma->work);
 2802     bytep += (slot << 5);
 2803     wordp = (u_int16_t *)bytep;
 2804     quadp = (u_int32_t *)bytep;
 2805 
 2806     /* fill in this request */
 2807     quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
 2808     quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
 2809     wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
 2810 
 2811     i = 10;
 2812     bytep[i++] = (request->u.ata.count >> 8) & 0xff;
 2813     bytep[i++] = 0x10 | ATA_COUNT;
 2814     bytep[i++] = request->u.ata.count & 0xff;
 2815     bytep[i++] = 0x10 | ATA_COUNT;
 2816 
 2817     bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
 2818     bytep[i++] = 0x10 | ATA_SECTOR;
 2819     bytep[i++] = request->u.ata.lba & 0xff;
 2820     bytep[i++] = 0x10 | ATA_SECTOR;
 2821 
 2822     bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
 2823     bytep[i++] = 0x10 | ATA_CYL_LSB;
 2824     bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
 2825     bytep[i++] = 0x10 | ATA_CYL_LSB;
 2826 
 2827     bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
 2828     bytep[i++] = 0x10 | ATA_CYL_MSB;
 2829     bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
 2830     bytep[i++] = 0x10 | ATA_CYL_MSB;
 2831 
 2832     bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
 2833     bytep[i++] = 0x10 | ATA_DRIVE;
 2834 
 2835     bytep[i++] = request->u.ata.command;
 2836     bytep[i++] = 0x90 | ATA_COMMAND;
 2837 
 2838     /* enable EDMA machinery if needed */
 2839     if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
 2840         ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
 2841         while (!(ATA_INL(ctlr->r_res1,
 2842                          0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
 2843             DELAY(10);
 2844     }
 2845 
 2846     /* tell EDMA it has a new request */
 2847     slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
 2848     req_in &= 0xfffffc00;
 2849     req_in += (slot << 5);
 2850     ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
 2851    
 2852     return ATA_OP_CONTINUES;
 2853 }
 2854 
 2855 /* must be called with ATA channel locked and state_mtx held */
 2856 static int
 2857 ata_marvell_edma_end_transaction(struct ata_request *request)
 2858 {
 2859     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
 2860     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 2861     int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
 2862     u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
 2863     int res;
 2864 
 2865     /* EDMA interrupt */
 2866     if ((icr & (0x0001 << (ch->unit & 3)))) {
 2867         struct ata_marvell_response *response;
 2868         u_int32_t rsp_in, rsp_out;
 2869         int slot;
 2870 
 2871         /* stop timeout */
 2872         callout_stop(&request->callout);
 2873 
 2874         /* get response ptr's */
 2875         rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
 2876         rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
 2877         slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
 2878         rsp_out &= 0xffffff00;
 2879         rsp_out += (slot << 3);
 2880         response = (struct ata_marvell_response *)
 2881                    (ch->dma->work + 1024 + (slot << 3));
 2882 
 2883         /* record status for this request */
 2884         request->status = response->dev_status;
 2885         request->error = 0; 
 2886 
 2887         /* ack response */
 2888         ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
 2889 
 2890         /* update progress */
 2891         if (!(request->status & ATA_S_ERROR) &&
 2892             !(request->flags & ATA_R_TIMEOUT))
 2893             request->donecount = request->bytecount;
 2894 
 2895         /* unload SG list */
 2896         ch->dma->unload(ch->dev);
 2897 
 2898         res = ATA_OP_FINISHED;
 2899     }
 2900 
 2901     /* legacy ATA interrupt */
 2902     else {
 2903         res = ata_end_transaction(request);
 2904     }
 2905 
 2906     /* ack interrupt */
 2907     ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
 2908     return res;
 2909 }
 2910 
 2911 static void
 2912 ata_marvell_edma_reset(device_t dev)
 2913 {
 2914     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2915     struct ata_channel *ch = device_get_softc(dev);
 2916 
 2917     /* disable the EDMA machinery */
 2918     ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
 2919     while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
 2920         DELAY(10);
 2921 
 2922     /* clear SATA error register */
 2923     ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
 2924 
 2925     /* clear any outstanding error interrupts */
 2926     ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
 2927 
 2928     /* unmask all error interrupts */
 2929     ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
 2930 
 2931     /* enable channel and test for devices */
 2932     if (ata_sata_phy_reset(dev))
 2933         ata_generic_reset(dev);
 2934 
 2935     /* enable EDMA machinery */
 2936     ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
 2937 }
 2938 
 2939 static void
 2940 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
 2941                            int error)
 2942 {
 2943     struct ata_dmasetprd_args *args = xsc;
 2944     struct ata_marvell_dma_prdentry *prd = args->dmatab;
 2945     int i;
 2946 
 2947     if ((args->error = error))
 2948         return;
 2949 
 2950     for (i = 0; i < nsegs; i++) {
 2951         prd[i].addrlo = htole32(segs[i].ds_addr);
 2952         prd[i].count = htole32(segs[i].ds_len);
 2953         prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
 2954     }
 2955     prd[i - 1].count |= htole32(ATA_DMA_EOT);
 2956     KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
 2957     args->nsegs = nsegs;
 2958 }
 2959 
 2960 static void
 2961 ata_marvell_edma_dmainit(device_t dev)
 2962 {
 2963     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 2964     struct ata_channel *ch = device_get_softc(dev);
 2965 
 2966     ata_dmainit(dev);
 2967     if (ch->dma) {
 2968         /* note start and stop are not used here */
 2969         ch->dma->setprd = ata_marvell_edma_dmasetprd;
 2970         
 2971         /* if 64bit support present adjust max address used */
 2972         if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
 2973             ch->dma->max_address = BUS_SPACE_MAXADDR;
 2974 
 2975         /* chip does not reliably do 64K DMA transfers */
 2976         ch->dma->max_iosize = 64 * DEV_BSIZE; 
 2977     }
 2978 }
 2979 
 2980 
 2981 /*
 2982  * National chipset support functions
 2983  */
 2984 int
 2985 ata_national_ident(device_t dev)
 2986 {
 2987     struct ata_pci_controller *ctlr = device_get_softc(dev);
 2988 
 2989     /* this chip is a clone of the Cyrix chip, bugs and all */
 2990     if (pci_get_devid(dev) == ATA_SC1100) {
 2991         device_set_desc(dev, "National Geode SC1100 ATA33 controller");
 2992         ctlr->chipinit = ata_national_chipinit;
 2993         return 0;
 2994     }
 2995     return ENXIO;
 2996 }
 2997     
 2998 static int
 2999 ata_national_chipinit(device_t dev)
 3000 {
 3001     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3002     
 3003     if (ata_setup_interrupt(dev))
 3004         return ENXIO;
 3005                     
 3006     ctlr->setmode = ata_national_setmode;
 3007     return 0;
 3008 }
 3009 
 3010 static void
 3011 ata_national_setmode(device_t dev, int mode)
 3012 {
 3013     device_t gparent = GRANDPARENT(dev);
 3014     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 3015     struct ata_device *atadev = device_get_softc(dev);
 3016     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 3017     u_int32_t piotiming[] =
 3018         { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
 3019           0x00803020, 0x20102010, 0x00100010,
 3020           0x00100010, 0x00100010, 0x00100010 };
 3021     u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
 3022     u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
 3023     int error;
 3024 
 3025     ch->dma->alignment = 16;
 3026     ch->dma->max_iosize = 64 * DEV_BSIZE;
 3027 
 3028     mode = ata_limit_mode(dev, mode, ATA_UDMA2);
 3029 
 3030     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 3031 
 3032     if (bootverbose)
 3033         device_printf(dev, "%s setting %s on National chip\n",
 3034                       (error) ? "failed" : "success", ata_mode2str(mode));
 3035     if (!error) {
 3036         if (mode >= ATA_UDMA0) {
 3037             pci_write_config(gparent, 0x44 + (devno << 3),
 3038                              udmatiming[mode & ATA_MODE_MASK], 4);
 3039         }
 3040         else if (mode >= ATA_WDMA0) {
 3041             pci_write_config(gparent, 0x44 + (devno << 3),
 3042                              dmatiming[mode & ATA_MODE_MASK], 4);
 3043         }
 3044         else {
 3045             pci_write_config(gparent, 0x44 + (devno << 3),
 3046                              pci_read_config(gparent, 0x44 + (devno << 3), 4) |
 3047                              0x80000000, 4);
 3048         }
 3049         pci_write_config(gparent, 0x40 + (devno << 3),
 3050                          piotiming[ata_mode2idx(mode)], 4);
 3051         atadev->mode = mode;
 3052     }
 3053 }
 3054 
 3055 
 3056 /*
 3057  * NetCell chipset support functions
 3058  */
 3059 int
 3060 ata_netcell_ident(device_t dev)
 3061 {
 3062     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3063 
 3064     if (pci_get_devid(dev) == ATA_NETCELL_SR) {
 3065         device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
 3066         ctlr->chipinit = ata_netcell_chipinit;
 3067         return 0;
 3068     }
 3069     return ENXIO;
 3070 }
 3071 
 3072 static int
 3073 ata_netcell_chipinit(device_t dev)
 3074 {
 3075     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3076 
 3077     if (ata_generic_chipinit(dev))
 3078         return ENXIO;
 3079 
 3080     ctlr->allocate = ata_netcell_allocate;
 3081     return 0;
 3082 }
 3083 
 3084 static int
 3085 ata_netcell_allocate(device_t dev)
 3086 {
 3087     struct ata_channel *ch = device_get_softc(dev);
 3088  
 3089     /* setup the usual register normal pci style */
 3090     if (ata_pci_allocate(dev))
 3091         return ENXIO;
 3092  
 3093     /* the NetCell only supports 16 bit PIO transfers */
 3094     ch->flags |= ATA_USE_16BIT;
 3095 
 3096     return 0;
 3097 }
 3098 
 3099 
 3100 /*
 3101  * nVidia chipset support functions
 3102  */
 3103 int
 3104 ata_nvidia_ident(device_t dev)
 3105 {
 3106     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3107     static struct ata_chip_id ids[] =
 3108     {{ ATA_NFORCE1,         0, AMDNVIDIA, NVIDIA,  ATA_UDMA5, "nForce" },
 3109      { ATA_NFORCE2,         0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce2" },
 3110      { ATA_NFORCE2_PRO,     0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce2 Pro" },
 3111      { ATA_NFORCE2_PRO_S1,  0, 0,         0,       ATA_SA150, "nForce2 Pro" },
 3112      { ATA_NFORCE3,         0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce3" },
 3113      { ATA_NFORCE3_PRO,     0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce3 Pro" },
 3114      { ATA_NFORCE3_PRO_S1,  0, 0,         0,       ATA_SA150, "nForce3 Pro" },
 3115      { ATA_NFORCE3_PRO_S2,  0, 0,         0,       ATA_SA150, "nForce3 Pro" },
 3116      { ATA_NFORCE_MCP04,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP" },
 3117      { ATA_NFORCE_MCP04_S1, 0, 0,         NV4,     ATA_SA150, "nForce MCP" },
 3118      { ATA_NFORCE_MCP04_S2, 0, 0,         NV4,     ATA_SA150, "nForce MCP" },
 3119      { ATA_NFORCE_CK804,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce CK804" },
 3120      { ATA_NFORCE_CK804_S1, 0, 0,         NV4,     ATA_SA300, "nForce CK804" },
 3121      { ATA_NFORCE_CK804_S2, 0, 0,         NV4,     ATA_SA300, "nForce CK804" },
 3122      { ATA_NFORCE_MCP51,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP51" },
 3123      { ATA_NFORCE_MCP51_S1, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP51" },
 3124      { ATA_NFORCE_MCP51_S2, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP51" },
 3125      { ATA_NFORCE_MCP55,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP55" },
 3126      { ATA_NFORCE_MCP55_S1, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP55" },
 3127      { ATA_NFORCE_MCP55_S2, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP55" },
 3128      { ATA_NFORCE_MCP61,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP61" },
 3129      { ATA_NFORCE_MCP61_S1, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP61" },
 3130      { ATA_NFORCE_MCP61_S2, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP61" },
 3131      { ATA_NFORCE_MCP61_S3, 0, 0,         NV4|NVQ, ATA_SA300, "nForce MCP61" },
 3132      { ATA_NFORCE_MCP65,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP65" },
 3133      { ATA_NFORCE_MCP67,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP67" },
 3134      { ATA_NFORCE_MCP67_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3135      { ATA_NFORCE_MCP67_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3136      { ATA_NFORCE_MCP67_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3137      { ATA_NFORCE_MCP67_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3138      { ATA_NFORCE_MCP67_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3139      { ATA_NFORCE_MCP67_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3140      { ATA_NFORCE_MCP67_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3141      { ATA_NFORCE_MCP67_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3142      { ATA_NFORCE_MCP67_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3143      { ATA_NFORCE_MCP67_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3144      { ATA_NFORCE_MCP67_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3145      { ATA_NFORCE_MCP67_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
 3146      { ATA_NFORCE_MCP73,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP73" },
 3147      { ATA_NFORCE_MCP73_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3148      { ATA_NFORCE_MCP73_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3149      { ATA_NFORCE_MCP73_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3150      { ATA_NFORCE_MCP73_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3151      { ATA_NFORCE_MCP73_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3152      { ATA_NFORCE_MCP73_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3153      { ATA_NFORCE_MCP73_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3154      { ATA_NFORCE_MCP73_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3155      { ATA_NFORCE_MCP73_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3156      { ATA_NFORCE_MCP73_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3157      { ATA_NFORCE_MCP73_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3158      { ATA_NFORCE_MCP73_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
 3159      { ATA_NFORCE_MCP77,    0, AMDNVIDIA, NVIDIA,  ATA_UDMA6, "nForce MCP77" },
 3160      { 0, 0, 0, 0, 0, 0}} ;
 3161 
 3162     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 3163         return ENXIO;
 3164 
 3165     ata_set_desc(dev);
 3166     if (ctlr->chip->cfg1 & NVAHCI)
 3167         ctlr->chipinit = ata_ahci_chipinit;
 3168     else
 3169         ctlr->chipinit = ata_nvidia_chipinit;
 3170     return 0;
 3171 }
 3172 
 3173 static int
 3174 ata_nvidia_chipinit(device_t dev)
 3175 {
 3176     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3177 
 3178     if (ata_setup_interrupt(dev))
 3179         return ENXIO;
 3180 
 3181     if (ctlr->chip->max_dma >= ATA_SA150) {
 3182         if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
 3183             ctlr->r_type2 = SYS_RES_IOPORT;
 3184         else
 3185             ctlr->r_type2 = SYS_RES_MEMORY;
 3186         ctlr->r_rid2 = PCIR_BAR(5);
 3187         if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 3188                                                    &ctlr->r_rid2, RF_ACTIVE))) {
 3189             int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
 3190 
 3191             ctlr->allocate = ata_nvidia_allocate;
 3192             ctlr->reset = ata_nvidia_reset;
 3193 
 3194             /* enable control access */
 3195             pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
 3196 
 3197             if (ctlr->chip->cfg2 & NVQ) {
 3198                 /* clear interrupt status */
 3199                 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
 3200 
 3201                 /* enable device and PHY state change interrupts */
 3202                 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
 3203 
 3204                 /* disable NCQ support */
 3205                 ATA_OUTL(ctlr->r_res2, 0x0400,
 3206                          ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
 3207             } 
 3208             else {
 3209                 /* clear interrupt status */
 3210                 ATA_OUTB(ctlr->r_res2, offset, 0xff);
 3211 
 3212                 /* enable device and PHY state change interrupts */
 3213                 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
 3214             }
 3215         }
 3216         ctlr->setmode = ata_sata_setmode;
 3217     }
 3218     else {
 3219         /* disable prefetch, postwrite */
 3220         pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
 3221         ctlr->setmode = ata_via_family_setmode;
 3222     }
 3223     return 0;
 3224 }
 3225 
 3226 static int
 3227 ata_nvidia_allocate(device_t dev)
 3228 {
 3229     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 3230     struct ata_channel *ch = device_get_softc(dev);
 3231 
 3232     /* setup the usual register normal pci style */
 3233     if (ata_pci_allocate(dev))
 3234         return ENXIO;
 3235 
 3236     ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
 3237     ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
 3238     ch->r_io[ATA_SERROR].res = ctlr->r_res2;
 3239     ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
 3240     ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
 3241     ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
 3242 
 3243     ch->hw.status = ata_nvidia_status;
 3244     ch->flags |= ATA_NO_SLAVE;
 3245 
 3246     return 0;
 3247 }
 3248 
 3249 static int 
 3250 ata_nvidia_status(device_t dev)
 3251 {
 3252     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 3253     struct ata_channel *ch = device_get_softc(dev);
 3254     int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
 3255     int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
 3256     u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
 3257 
 3258     /* do we have any PHY events ? */
 3259     if (istatus & (0x0c << shift))
 3260         ata_sata_phy_check_events(dev);
 3261 
 3262     /* clear interrupt(s) */
 3263     ATA_OUTB(ctlr->r_res2, offset,
 3264              (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
 3265 
 3266     /* do we have any device action ? */
 3267     return (istatus & (0x01 << shift));
 3268 }
 3269 
 3270 static void
 3271 ata_nvidia_reset(device_t dev)
 3272 {
 3273     if (ata_sata_phy_reset(dev))
 3274         ata_generic_reset(dev);
 3275 }
 3276 
 3277 
 3278 /*
 3279  * Promise chipset support functions
 3280  */
 3281 #define ATA_PDC_APKT_OFFSET     0x00000010 
 3282 #define ATA_PDC_HPKT_OFFSET     0x00000040
 3283 #define ATA_PDC_ASG_OFFSET      0x00000080
 3284 #define ATA_PDC_LSG_OFFSET      0x000000c0
 3285 #define ATA_PDC_HSG_OFFSET      0x00000100
 3286 #define ATA_PDC_CHN_OFFSET      0x00000400
 3287 #define ATA_PDC_BUF_BASE        0x00400000
 3288 #define ATA_PDC_BUF_OFFSET      0x00100000
 3289 #define ATA_PDC_MAX_HPKT        8
 3290 #define ATA_PDC_WRITE_REG       0x00
 3291 #define ATA_PDC_WRITE_CTL       0x0e
 3292 #define ATA_PDC_WRITE_END       0x08
 3293 #define ATA_PDC_WAIT_NBUSY      0x10
 3294 #define ATA_PDC_WAIT_READY      0x18
 3295 #define ATA_PDC_1B              0x20
 3296 #define ATA_PDC_2B              0x40
 3297 
 3298 struct host_packet {
 3299 u_int32_t                       addr;
 3300     TAILQ_ENTRY(host_packet)    chain;
 3301 };
 3302 
 3303 struct ata_promise_sx4 {
 3304     struct mtx                  mtx;
 3305     TAILQ_HEAD(, host_packet)   queue;
 3306     int                         busy;
 3307 };
 3308 
 3309 int
 3310 ata_promise_ident(device_t dev)
 3311 {
 3312     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3313     struct ata_chip_id *idx;
 3314     static struct ata_chip_id ids[] =
 3315     {{ ATA_PDC20246,  0, PROLD, 0x00,    ATA_UDMA2, "PDC20246" },
 3316      { ATA_PDC20262,  0, PRNEW, 0x00,    ATA_UDMA4, "PDC20262" },
 3317      { ATA_PDC20263,  0, PRNEW, 0x00,    ATA_UDMA4, "PDC20263" },
 3318      { ATA_PDC20265,  0, PRNEW, 0x00,    ATA_UDMA5, "PDC20265" },
 3319      { ATA_PDC20267,  0, PRNEW, 0x00,    ATA_UDMA5, "PDC20267" },
 3320      { ATA_PDC20268,  0, PRTX,  PRTX4,   ATA_UDMA5, "PDC20268" },
 3321      { ATA_PDC20269,  0, PRTX,  0x00,    ATA_UDMA6, "PDC20269" },
 3322      { ATA_PDC20270,  0, PRTX,  PRTX4,   ATA_UDMA5, "PDC20270" },
 3323      { ATA_PDC20271,  0, PRTX,  0x00,    ATA_UDMA6, "PDC20271" },
 3324      { ATA_PDC20275,  0, PRTX,  0x00,    ATA_UDMA6, "PDC20275" },
 3325      { ATA_PDC20276,  0, PRTX,  PRSX6K,  ATA_UDMA6, "PDC20276" },
 3326      { ATA_PDC20277,  0, PRTX,  0x00,    ATA_UDMA6, "PDC20277" },
 3327      { ATA_PDC20318,  0, PRMIO, PRSATA,  ATA_SA150, "PDC20318" },
 3328      { ATA_PDC20319,  0, PRMIO, PRSATA,  ATA_SA150, "PDC20319" },
 3329      { ATA_PDC20371,  0, PRMIO, PRCMBO,  ATA_SA150, "PDC20371" },
 3330      { ATA_PDC20375,  0, PRMIO, PRCMBO,  ATA_SA150, "PDC20375" },
 3331      { ATA_PDC20376,  0, PRMIO, PRCMBO,  ATA_SA150, "PDC20376" },
 3332      { ATA_PDC20377,  0, PRMIO, PRCMBO,  ATA_SA150, "PDC20377" },
 3333      { ATA_PDC20378,  0, PRMIO, PRCMBO,  ATA_SA150, "PDC20378" },
 3334      { ATA_PDC20379,  0, PRMIO, PRCMBO,  ATA_SA150, "PDC20379" },
 3335      { ATA_PDC20571,  0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
 3336      { ATA_PDC20575,  0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
 3337      { ATA_PDC20579,  0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
 3338      { ATA_PDC20771,  0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
 3339      { ATA_PDC40775,  0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
 3340      { ATA_PDC20617,  0, PRMIO, PRPATA,  ATA_UDMA6, "PDC20617" },
 3341      { ATA_PDC20618,  0, PRMIO, PRPATA,  ATA_UDMA6, "PDC20618" },
 3342      { ATA_PDC20619,  0, PRMIO, PRPATA,  ATA_UDMA6, "PDC20619" },
 3343      { ATA_PDC20620,  0, PRMIO, PRPATA,  ATA_UDMA6, "PDC20620" },
 3344      { ATA_PDC20621,  0, PRMIO, PRSX4X,  ATA_UDMA5, "PDC20621" },
 3345      { ATA_PDC20622,  0, PRMIO, PRSX4X,  ATA_SA150, "PDC20622" },
 3346      { ATA_PDC40518,  0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
 3347      { ATA_PDC40519,  0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
 3348      { ATA_PDC40718,  0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
 3349      { ATA_PDC40719,  0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
 3350      { ATA_PDC40779,  0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
 3351      { 0, 0, 0, 0, 0, 0}};
 3352     char buffer[64];
 3353     uintptr_t devid = 0;
 3354 
 3355     if (!(idx = ata_match_chip(dev, ids)))
 3356         return ENXIO;
 3357 
 3358     /* if we are on a SuperTrak SX6000 dont attach */
 3359     if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
 3360         !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
 3361                        GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
 3362         devid == ATA_I960RM) 
 3363         return ENXIO;
 3364 
 3365     strcpy(buffer, "Promise ");
 3366     strcat(buffer, idx->text);
 3367 
 3368     /* if we are on a FastTrak TX4, adjust the interrupt resource */
 3369     if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
 3370         !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
 3371                        GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
 3372         ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
 3373         static long start = 0, end = 0;
 3374 
 3375         if (pci_get_slot(dev) == 1) {
 3376             bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
 3377             strcat(buffer, " (channel 0+1)");
 3378         }
 3379         else if (pci_get_slot(dev) == 2 && start && end) {
 3380             bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
 3381             strcat(buffer, " (channel 2+3)");
 3382         }
 3383         else {
 3384             start = end = 0;
 3385         }
 3386     }
 3387     sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
 3388     device_set_desc_copy(dev, buffer);
 3389     ctlr->chip = idx;
 3390     ctlr->chipinit = ata_promise_chipinit;
 3391     return 0;
 3392 }
 3393 
 3394 static int
 3395 ata_promise_chipinit(device_t dev)
 3396 {
 3397     struct ata_pci_controller *ctlr = device_get_softc(dev);
 3398     int fake_reg, stat_reg;
 3399 
 3400     if (ata_setup_interrupt(dev))
 3401         return ENXIO;
 3402 
 3403     switch  (ctlr->chip->cfg1) {
 3404     case PRNEW:
 3405         /* setup clocks */
 3406         ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
 3407 
 3408         ctlr->dmainit = ata_promise_dmainit;
 3409         /* FALLTHROUGH */
 3410 
 3411     case PROLD:
 3412         /* enable burst mode */
 3413         ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
 3414         ctlr->allocate = ata_promise_allocate;
 3415         ctlr->setmode = ata_promise_setmode;
 3416         return 0;
 3417 
 3418     case PRTX:
 3419         ctlr->allocate = ata_promise_tx2_allocate;
 3420         ctlr->setmode = ata_promise_setmode;
 3421         return 0;
 3422 
 3423     case PRMIO:
 3424         ctlr->r_type1 = SYS_RES_MEMORY;
 3425         ctlr->r_rid1 = PCIR_BAR(4);
 3426         if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
 3427                                                     &ctlr->r_rid1, RF_ACTIVE)))
 3428             goto failnfree;
 3429 
 3430         ctlr->r_type2 = SYS_RES_MEMORY;
 3431         ctlr->r_rid2 = PCIR_BAR(3);
 3432         if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 3433                                                     &ctlr->r_rid2, RF_ACTIVE)))
 3434             goto failnfree;
 3435 
 3436         if (ctlr->chip->cfg2 == PRSX4X) {
 3437             struct ata_promise_sx4 *hpkt;
 3438             u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
 3439 
 3440             if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
 3441                 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
 3442                                ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
 3443                 device_printf(dev, "unable to setup interrupt\n");
 3444                 goto failnfree;
 3445             }
 3446 
 3447             /* print info about cache memory */
 3448             device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
 3449                           (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
 3450                           ((dimm >> 24) & 0xff),
 3451                           ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
 3452                           " ECC enabled" : "" );
 3453 
 3454             /* adjust cache memory parameters */
 3455             ATA_OUTL(ctlr->r_res2, 0x000c000c, 
 3456                      (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
 3457 
 3458             /* setup host packet controls */
 3459             hpkt = malloc(sizeof(struct ata_promise_sx4),
 3460                           M_TEMP, M_NOWAIT | M_ZERO);
 3461             mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
 3462             TAILQ_INIT(&hpkt->queue);
 3463             hpkt->busy = 0;
 3464             device_set_ivars(dev, hpkt);
 3465             ctlr->allocate = ata_promise_mio_allocate;
 3466             ctlr->reset = ata_promise_mio_reset;
 3467             ctlr->dmainit = ata_promise_mio_dmainit;
 3468             ctlr->setmode = ata_promise_setmode;
 3469             ctlr->channels = 4;
 3470             return 0;
 3471         }
 3472 
 3473         /* mio type controllers need an interrupt intercept */
 3474         if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
 3475             bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
 3476                                ata_promise_mio_intr, ctlr, &ctlr->handle)) {
 3477                 device_printf(dev, "unable to setup interrupt\n");
 3478                 goto failnfree;
 3479         }
 3480 
 3481         switch (ctlr->chip->cfg2) {
 3482         case PRPATA:
 3483             ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
 3484                              ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
 3485             goto sata150;
 3486         case PRCMBO:
 3487             ctlr->channels = 3;
 3488             goto sata150;
 3489         case PRSATA:
 3490             ctlr->channels = 4;
 3491 sata150:
 3492             fake_reg = 0x60;
 3493             stat_reg = 0x6c;
 3494             break;
 3495 
 3496         case PRCMBO2: 
 3497             ctlr->channels = 3;
 3498             goto sataii;
 3499         case PRSATA2:
 3500         default:
 3501             ctlr->channels = 4;
 3502 sataii:
 3503             fake_reg = 0x54;
 3504             stat_reg = 0x60;
 3505             break;
 3506         }
 3507 
 3508         /* prime fake interrupt register */
 3509         ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
 3510 
 3511         /* clear SATA status and unmask interrupts */
 3512         ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
 3513 
 3514         /* enable "long burst lenght" on gen2 chips */
 3515         if ((ctlr->chip->cfg2 == PRSATA2) || (ctlr->chip->cfg2 == PRCMBO2))
 3516             ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
 3517 
 3518         ctlr->allocate = ata_promise_mio_allocate;
 3519         ctlr->reset = ata_promise_mio_reset;
 3520         ctlr->dmainit = ata_promise_mio_dmainit;
 3521         ctlr->setmode = ata_promise_mio_setmode;
 3522 
 3523         return 0;
 3524     }
 3525 
 3526 failnfree:
 3527     if (ctlr->r_res2)
 3528         bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
 3529     if (ctlr->r_res1)
 3530         bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
 3531     return ENXIO;
 3532 }
 3533 
 3534 static int
 3535 ata_promise_allocate(device_t dev)
 3536 {
 3537     struct ata_channel *ch = device_get_softc(dev);
 3538 
 3539     if (ata_pci_allocate(dev))
 3540         return ENXIO;
 3541 
 3542     ch->hw.status = ata_promise_status;
 3543     return 0;
 3544 }
 3545 
 3546 static int
 3547 ata_promise_status(device_t dev)
 3548 {
 3549     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 3550     struct ata_channel *ch = device_get_softc(dev);
 3551 
 3552     if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
 3553         return ata_pci_status(dev);
 3554     }
 3555     return 0;
 3556 }
 3557 
 3558 static int
 3559 ata_promise_dmastart(device_t dev)
 3560 {
 3561     struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
 3562     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 3563     struct ata_device *atadev  = device_get_softc(dev);
 3564 
 3565     if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 3566         ATA_OUTB(ctlr->r_res1, 0x11,
 3567                  ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
 3568         ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
 3569                  ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
 3570                  (ch->dma->cur_iosize >> 1));
 3571     }
 3572     ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
 3573                  (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
 3574     ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
 3575     ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
 3576                  ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
 3577                  ATA_BMCMD_START_STOP);
 3578     ch->flags |= ATA_DMA_ACTIVE;
 3579     return 0;
 3580 }
 3581 
 3582 static int
 3583 ata_promise_dmastop(device_t dev)
 3584 {
 3585     struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
 3586     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 3587     struct ata_device *atadev  = device_get_softc(dev);
 3588     int error;
 3589 
 3590     if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 3591         ATA_OUTB(ctlr->r_res1, 0x11,
 3592                  ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
 3593         ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
 3594     }
 3595     error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
 3596     ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
 3597                  ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
 3598     ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 
 3599     ch->flags &= ~ATA_DMA_ACTIVE;
 3600     return error;
 3601 }
 3602 
 3603 static void
 3604 ata_promise_dmareset(device_t dev)
 3605 {
 3606     struct ata_channel *ch = device_get_softc(dev);
 3607 
 3608     ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
 3609                  ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
 3610     ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 
 3611     ch->flags &= ~ATA_DMA_ACTIVE;
 3612 }
 3613 
 3614 static void
 3615 ata_promise_dmainit(device_t dev)
 3616 {
 3617     struct ata_channel *ch = device_get_softc(dev);
 3618 
 3619     ata_dmainit(dev);
 3620     if (ch->dma) {
 3621         ch->dma->start = ata_promise_dmastart;
 3622         ch->dma->stop = ata_promise_dmastop;
 3623         ch->dma->reset = ata_promise_dmareset;
 3624     }
 3625 }
 3626 
 3627 static void
 3628 ata_promise_setmode(device_t dev, int mode)
 3629 {
 3630     device_t gparent = GRANDPARENT(dev);
 3631     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 3632     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 3633     struct ata_device *atadev = device_get_softc(dev);
 3634     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 3635     int error;
 3636     u_int32_t timings[][2] = {
 3637     /*    PROLD       PRNEW                mode */
 3638         { 0x004ff329, 0x004fff2f },     /* PIO 0 */
 3639         { 0x004fec25, 0x004ff82a },     /* PIO 1 */
 3640         { 0x004fe823, 0x004ff026 },     /* PIO 2 */
 3641         { 0x004fe622, 0x004fec24 },     /* PIO 3 */
 3642         { 0x004fe421, 0x004fe822 },     /* PIO 4 */
 3643         { 0x004567f3, 0x004acef6 },     /* MWDMA 0 */
 3644         { 0x004467f3, 0x0048cef6 },     /* MWDMA 1 */
 3645         { 0x004367f3, 0x0046cef6 },     /* MWDMA 2 */
 3646         { 0x004367f3, 0x0046cef6 },     /* UDMA 0 */
 3647         { 0x004247f3, 0x00448ef6 },     /* UDMA 1 */
 3648         { 0x004127f3, 0x00436ef6 },     /* UDMA 2 */
 3649         { 0,          0x00424ef6 },     /* UDMA 3 */
 3650         { 0,          0x004127f3 },     /* UDMA 4 */
 3651         { 0,          0x004127f3 }      /* UDMA 5 */
 3652     };
 3653 
 3654     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 3655 
 3656     switch (ctlr->chip->cfg1) {
 3657     case PROLD:
 3658     case PRNEW:
 3659         if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
 3660                                  (ch->unit ? 1 << 11 : 1 << 10))) {
 3661             ata_print_cable(dev, "controller");
 3662             mode = ATA_UDMA2;
 3663         }
 3664         if (ata_atapi(dev) && mode > ATA_PIO_MAX)
 3665             mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
 3666         break;
 3667 
 3668     case PRTX:
 3669         ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
 3670         if (mode > ATA_UDMA2 &&
 3671             ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
 3672             ata_print_cable(dev, "controller");
 3673             mode = ATA_UDMA2;
 3674         }
 3675         break;
 3676    
 3677     case PRMIO:
 3678         if (mode > ATA_UDMA2 &&
 3679             (ATA_INL(ctlr->r_res2,
 3680                      (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
 3681                      (ch->unit << 7)) & 0x01000000)) {
 3682             ata_print_cable(dev, "controller");
 3683             mode = ATA_UDMA2;
 3684         }
 3685         break;
 3686     }
 3687 
 3688     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 3689 
 3690     if (bootverbose)
 3691         device_printf(dev, "%ssetting %s on %s chip\n",
 3692                      (error) ? "FAILURE " : "",
 3693                      ata_mode2str(mode), ctlr->chip->text);
 3694     if (!error) {
 3695         if (ctlr->chip->cfg1 < PRTX)
 3696             pci_write_config(gparent, 0x60 + (devno << 2),
 3697                              timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
 3698         atadev->mode = mode;
 3699     }
 3700     return;
 3701 }
 3702 
 3703 static int
 3704 ata_promise_tx2_allocate(device_t dev)
 3705 {
 3706     struct ata_channel *ch = device_get_softc(dev);
 3707 
 3708     if (ata_pci_allocate(dev))
 3709         return ENXIO;
 3710 
 3711     ch->hw.status = ata_promise_tx2_status;
 3712     return 0;
 3713 }
 3714 
 3715 static int
 3716 ata_promise_tx2_status(device_t dev)
 3717 {
 3718     struct ata_channel *ch = device_get_softc(dev);
 3719 
 3720     ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
 3721     if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
 3722         return ata_pci_status(dev);
 3723     }
 3724     return 0;
 3725 }
 3726 
 3727 static int
 3728 ata_promise_mio_allocate(device_t dev)
 3729 {
 3730     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 3731     struct ata_channel *ch = device_get_softc(dev);
 3732     int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
 3733     int i;
 3734  
 3735     for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
 3736         ch->r_io[i].res = ctlr->r_res2;
 3737         ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 
 3738     }
 3739     ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
 3740     ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
 3741     ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
 3742     ata_default_registers(dev);
 3743     if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
 3744         ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
 3745         ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
 3746         ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
 3747         ch->r_io[ATA_SERROR].res = ctlr->r_res2;
 3748         ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
 3749         ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
 3750         ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
 3751         ch->flags |= ATA_NO_SLAVE;
 3752     }
 3753     ch->flags |= ATA_USE_16BIT;
 3754 
 3755     ata_generic_hw(dev);
 3756     if (ctlr->chip->cfg2 & PRSX4X) {
 3757         ch->hw.command = ata_promise_sx4_command;
 3758     }
 3759     else {
 3760         ch->hw.command = ata_promise_mio_command;
 3761         ch->hw.status = ata_promise_mio_status;
 3762      }
 3763     return 0;
 3764 }
 3765 
 3766 static void
 3767 ata_promise_mio_intr(void *data)
 3768 {
 3769     struct ata_pci_controller *ctlr = data;
 3770     struct ata_channel *ch;
 3771     u_int32_t vector;
 3772     int unit, fake_reg;
 3773 
 3774     switch (ctlr->chip->cfg2) {
 3775     case PRPATA:
 3776     case PRCMBO:
 3777     case PRSATA:
 3778         fake_reg = 0x60;
 3779         break;
 3780     case PRCMBO2: 
 3781     case PRSATA2:
 3782     default:
 3783         fake_reg = 0x54;
 3784         break;
 3785     }
 3786 
 3787     /*
 3788      * since reading interrupt status register on early "mio" chips
 3789      * clears the status bits we cannot read it for each channel later on
 3790      * in the generic interrupt routine.
 3791      * store the bits in an unused register in the chip so we can read
 3792      * it from there safely to get around this "feature".
 3793      */
 3794     vector = ATA_INL(ctlr->r_res2, 0x040);
 3795     ATA_OUTL(ctlr->r_res2, 0x040, vector);
 3796     ATA_OUTL(ctlr->r_res2, fake_reg, vector);
 3797 
 3798     for (unit = 0; unit < ctlr->channels; unit++) {
 3799         if ((ch = ctlr->interrupt[unit].argument))
 3800             ctlr->interrupt[unit].function(ch);
 3801     }
 3802 
 3803     ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
 3804 }
 3805 
 3806 static int
 3807 ata_promise_mio_status(device_t dev)
 3808 {
 3809     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 3810     struct ata_channel *ch = device_get_softc(dev);
 3811     struct ata_connect_task *tp;
 3812     u_int32_t fake_reg, stat_reg, vector, status;
 3813 
 3814     switch (ctlr->chip->cfg2) {
 3815     case PRPATA:
 3816     case PRCMBO:
 3817     case PRSATA:
 3818         fake_reg = 0x60;
 3819         stat_reg = 0x6c;
 3820         break;
 3821     case PRCMBO2: 
 3822     case PRSATA2:
 3823     default:
 3824         fake_reg = 0x54;
 3825         stat_reg = 0x60;
 3826         break;
 3827     }
 3828 
 3829     /* read and acknowledge interrupt */
 3830     vector = ATA_INL(ctlr->r_res2, fake_reg);
 3831 
 3832     /* read and clear interface status */
 3833     status = ATA_INL(ctlr->r_res2, stat_reg);
 3834     ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
 3835 
 3836     /* check for and handle disconnect events */
 3837     if ((status & (0x00000001 << ch->unit)) &&
 3838         (tp = (struct ata_connect_task *)
 3839               malloc(sizeof(struct ata_connect_task),
 3840                      M_ATA, M_NOWAIT | M_ZERO))) {
 3841 
 3842         if (bootverbose)
 3843             device_printf(ch->dev, "DISCONNECT requested\n");
 3844         tp->action = ATA_C_DETACH;
 3845         tp->dev = ch->dev;
 3846         TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
 3847         taskqueue_enqueue(taskqueue_thread, &tp->task);
 3848     }
 3849 
 3850     /* check for and handle connect events */
 3851     if ((status & (0x00000010 << ch->unit)) &&
 3852         (tp = (struct ata_connect_task *)
 3853               malloc(sizeof(struct ata_connect_task),
 3854                      M_ATA, M_NOWAIT | M_ZERO))) {
 3855 
 3856         if (bootverbose)
 3857             device_printf(ch->dev, "CONNECT requested\n");
 3858         tp->action = ATA_C_ATTACH;
 3859         tp->dev = ch->dev;
 3860         TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
 3861         taskqueue_enqueue(taskqueue_thread, &tp->task);
 3862     }
 3863 
 3864     /* do we have any device action ? */
 3865     return (vector & (1 << (ch->unit + 1)));
 3866 }
 3867 
 3868 static int
 3869 ata_promise_mio_command(struct ata_request *request)
 3870 {
 3871     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
 3872     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 3873     u_int32_t *wordp = (u_int32_t *)ch->dma->work;
 3874 
 3875     ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
 3876 
 3877     /* XXX SOS add ATAPI commands support later */
 3878     switch (request->u.ata.command) {
 3879     default:
 3880         return ata_generic_command(request);
 3881 
 3882     case ATA_READ_DMA:
 3883     case ATA_READ_DMA48:
 3884         wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
 3885         break;
 3886 
 3887     case ATA_WRITE_DMA:
 3888     case ATA_WRITE_DMA48:
 3889         wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
 3890         break;
 3891     }
 3892     wordp[1] = htole32(ch->dma->sg_bus);
 3893     wordp[2] = 0;
 3894     ata_promise_apkt((u_int8_t*)wordp, request);
 3895 
 3896     ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
 3897     return 0;
 3898 }
 3899 
 3900 static void
 3901 ata_promise_mio_reset(device_t dev)
 3902 {
 3903     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 3904     struct ata_channel *ch = device_get_softc(dev);
 3905     struct ata_promise_sx4 *hpktp;
 3906 
 3907     switch (ctlr->chip->cfg2) {
 3908     case PRSX4X:
 3909 
 3910         /* softreset channel ATA module */
 3911         hpktp = device_get_ivars(ctlr->dev);
 3912         ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
 3913         ata_udelay(1000);
 3914         ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
 3915                  (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
 3916                   ~0x00003f9f) | (ch->unit + 1));
 3917 
 3918         /* softreset HOST module */ /* XXX SOS what about other outstandings */
 3919         mtx_lock(&hpktp->mtx);
 3920         ATA_OUTL(ctlr->r_res2, 0xc012c,
 3921                  (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
 3922         DELAY(10);
 3923         ATA_OUTL(ctlr->r_res2, 0xc012c,
 3924                  (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
 3925         hpktp->busy = 0;
 3926         mtx_unlock(&hpktp->mtx);
 3927         ata_generic_reset(dev);
 3928         break;
 3929 
 3930     case PRPATA:
 3931     case PRCMBO:
 3932     case PRSATA:
 3933         if ((ctlr->chip->cfg2 == PRSATA) ||
 3934             ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
 3935 
 3936             /* mask plug/unplug intr */
 3937             ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
 3938         }
 3939 
 3940         /* softreset channels ATA module */
 3941         ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
 3942         ata_udelay(10000);
 3943         ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
 3944                  (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
 3945                   ~0x00003f9f) | (ch->unit + 1));
 3946 
 3947         if ((ctlr->chip->cfg2 == PRSATA) ||
 3948             ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
 3949 
 3950             if (ata_sata_phy_reset(dev))
 3951                 ata_generic_reset(dev);
 3952 
 3953             /* reset and enable plug/unplug intr */
 3954             ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
 3955         }
 3956         else
 3957             ata_generic_reset(dev);
 3958         break;
 3959 
 3960     case PRCMBO2:
 3961     case PRSATA2:
 3962         if ((ctlr->chip->cfg2 == PRSATA2) ||
 3963             ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
 3964             /* set portmultiplier port */
 3965             ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
 3966 
 3967             /* mask plug/unplug intr */
 3968             ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
 3969         }
 3970 
 3971         /* softreset channels ATA module */
 3972         ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
 3973         ata_udelay(10000);
 3974         ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
 3975                  (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
 3976                   ~0x00003f9f) | (ch->unit + 1));
 3977 
 3978         if ((ctlr->chip->cfg2 == PRSATA2) ||
 3979             ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
 3980 
 3981             /* set PHY mode to "improved" */
 3982             ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
 3983                      (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
 3984                      ~0x00000003) | 0x00000001);
 3985 
 3986             if (ata_sata_phy_reset(dev))
 3987                 ata_generic_reset(dev);
 3988 
 3989             /* reset and enable plug/unplug intr */
 3990             ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
 3991 
 3992             /* set portmultiplier port */
 3993             ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
 3994         }
 3995         else
 3996             ata_generic_reset(dev);
 3997         break;
 3998 
 3999     }
 4000 }
 4001 
 4002 static void
 4003 ata_promise_mio_dmainit(device_t dev)
 4004 {
 4005     struct ata_channel *ch = device_get_softc(dev);
 4006 
 4007     /* note start and stop are not used here */
 4008     ata_dmainit(dev);
 4009     if (ch->dma) 
 4010         ch->dma->setprd = ata_promise_mio_setprd;
 4011 }
 4012 
 4013 
 4014 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
 4015 static void 
 4016 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
 4017 {
 4018     struct ata_dmasetprd_args *args = xsc;
 4019     struct ata_dma_prdentry *prd = args->dmatab;
 4020     int i;
 4021 
 4022     if ((args->error = error))
 4023         return;
 4024 
 4025     for (i = 0; i < nsegs; i++) {
 4026         prd[i].addr = htole32(segs[i].ds_addr);
 4027         prd[i].count = htole32(segs[i].ds_len);
 4028     }
 4029     if (segs[i - 1].ds_len > MAXLASTSGSIZE) {
 4030         //printf("split last SG element of %u\n", segs[i - 1].ds_len);
 4031         prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE);
 4032         prd[i].count = htole32(MAXLASTSGSIZE);
 4033         prd[i].addr = htole32(segs[i - 1].ds_addr +
 4034                               (segs[i - 1].ds_len - MAXLASTSGSIZE));
 4035         nsegs++;
 4036         i++;
 4037     }
 4038     prd[i - 1].count |= htole32(ATA_DMA_EOT);
 4039     KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
 4040     args->nsegs = nsegs;
 4041 }
 4042 
 4043 static void
 4044 ata_promise_mio_setmode(device_t dev, int mode)
 4045 {
 4046     device_t gparent = GRANDPARENT(dev);
 4047     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 4048     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 4049 
 4050     if ( (ctlr->chip->cfg2 == PRSATA) ||
 4051         ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
 4052         (ctlr->chip->cfg2 == PRSATA2) ||
 4053         ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
 4054         ata_sata_setmode(dev, mode);
 4055     else
 4056         ata_promise_setmode(dev, mode);
 4057 }
 4058 
 4059 static void
 4060 ata_promise_sx4_intr(void *data)
 4061 {
 4062     struct ata_pci_controller *ctlr = data;
 4063     struct ata_channel *ch;
 4064     u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
 4065     int unit;
 4066 
 4067     for (unit = 0; unit < ctlr->channels; unit++) {
 4068         if (vector & (1 << (unit + 1)))
 4069             if ((ch = ctlr->interrupt[unit].argument))
 4070                 ctlr->interrupt[unit].function(ch);
 4071         if (vector & (1 << (unit + 5)))
 4072             if ((ch = ctlr->interrupt[unit].argument))
 4073                 ata_promise_queue_hpkt(ctlr,
 4074                                        htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
 4075                                                ATA_PDC_HPKT_OFFSET));
 4076         if (vector & (1 << (unit + 9))) {
 4077             ata_promise_next_hpkt(ctlr);
 4078             if ((ch = ctlr->interrupt[unit].argument))
 4079                 ctlr->interrupt[unit].function(ch);
 4080         }
 4081         if (vector & (1 << (unit + 13))) {
 4082             ata_promise_next_hpkt(ctlr);
 4083             if ((ch = ctlr->interrupt[unit].argument))
 4084                 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
 4085                          htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
 4086                          ATA_PDC_APKT_OFFSET));
 4087         }
 4088     }
 4089 }
 4090 
 4091 static int
 4092 ata_promise_sx4_command(struct ata_request *request)
 4093 {
 4094     device_t gparent = GRANDPARENT(request->dev);
 4095     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 4096     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 4097     struct ata_dma_prdentry *prd = ch->dma->sg;
 4098     caddr_t window = rman_get_virtual(ctlr->r_res1);
 4099     u_int32_t *wordp;
 4100     int i, idx, length = 0;
 4101 
 4102     /* XXX SOS add ATAPI commands support later */
 4103     switch (request->u.ata.command) {    
 4104 
 4105     default:
 4106         return -1;
 4107 
 4108     case ATA_ATA_IDENTIFY:
 4109     case ATA_READ:
 4110     case ATA_READ48:
 4111     case ATA_READ_MUL:
 4112     case ATA_READ_MUL48:
 4113     case ATA_WRITE:
 4114     case ATA_WRITE48:
 4115     case ATA_WRITE_MUL:
 4116     case ATA_WRITE_MUL48:
 4117         ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
 4118         return ata_generic_command(request);
 4119 
 4120     case ATA_SETFEATURES:
 4121     case ATA_FLUSHCACHE:
 4122     case ATA_FLUSHCACHE48:
 4123     case ATA_SLEEP:
 4124     case ATA_SET_MULTI:
 4125         wordp = (u_int32_t *)
 4126             (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
 4127         wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
 4128         wordp[1] = 0;
 4129         wordp[2] = 0;
 4130         ata_promise_apkt((u_int8_t *)wordp, request);
 4131         ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
 4132         ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
 4133         ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
 4134                  htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
 4135         return 0;
 4136 
 4137     case ATA_READ_DMA:
 4138     case ATA_READ_DMA48:
 4139     case ATA_WRITE_DMA:
 4140     case ATA_WRITE_DMA48:
 4141         wordp = (u_int32_t *)
 4142             (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
 4143         i = idx = 0;
 4144         do {
 4145             wordp[idx++] = prd[i].addr;
 4146             wordp[idx++] = prd[i].count;
 4147             length += (prd[i].count & ~ATA_DMA_EOT);
 4148         } while (!(prd[i++].count & ATA_DMA_EOT));
 4149 
 4150         wordp = (u_int32_t *)
 4151             (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
 4152         wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
 4153         wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
 4154 
 4155         wordp = (u_int32_t *)
 4156             (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
 4157         wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
 4158         wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
 4159 
 4160         wordp = (u_int32_t *)
 4161             (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
 4162         if (request->flags & ATA_R_READ)
 4163             wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
 4164         if (request->flags & ATA_R_WRITE)
 4165             wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
 4166         wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
 4167         wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
 4168         wordp[3] = 0;
 4169 
 4170         wordp = (u_int32_t *)
 4171             (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
 4172         if (request->flags & ATA_R_READ)
 4173             wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
 4174         if (request->flags & ATA_R_WRITE)
 4175             wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
 4176         wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
 4177         wordp[2] = 0;
 4178         ata_promise_apkt((u_int8_t *)wordp, request);
 4179         ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
 4180 
 4181         if (request->flags & ATA_R_READ) {
 4182             ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
 4183             ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
 4184             ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
 4185                 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
 4186         }
 4187         if (request->flags & ATA_R_WRITE) {
 4188             ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
 4189             ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
 4190             ata_promise_queue_hpkt(ctlr,
 4191                 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
 4192         }
 4193         return 0;
 4194     }
 4195 }
 4196 
 4197 static int
 4198 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
 4199 { 
 4200     struct ata_device *atadev = device_get_softc(request->dev);
 4201     int i = 12;
 4202 
 4203     bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
 4204     bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
 4205     bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
 4206     bytep[i++] = ATA_A_4BIT;
 4207 
 4208     if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 4209         bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
 4210         bytep[i++] = request->u.ata.feature >> 8;
 4211         bytep[i++] = request->u.ata.feature;
 4212         bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
 4213         bytep[i++] = request->u.ata.count >> 8;
 4214         bytep[i++] = request->u.ata.count;
 4215         bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
 4216         bytep[i++] = request->u.ata.lba >> 24;
 4217         bytep[i++] = request->u.ata.lba;
 4218         bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
 4219         bytep[i++] = request->u.ata.lba >> 32;
 4220         bytep[i++] = request->u.ata.lba >> 8;
 4221         bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
 4222         bytep[i++] = request->u.ata.lba >> 40;
 4223         bytep[i++] = request->u.ata.lba >> 16;
 4224         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
 4225         bytep[i++] = ATA_D_LBA | atadev->unit;
 4226     }
 4227     else {
 4228         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
 4229         bytep[i++] = request->u.ata.feature;
 4230         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
 4231         bytep[i++] = request->u.ata.count;
 4232         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
 4233         bytep[i++] = request->u.ata.lba;
 4234         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
 4235         bytep[i++] = request->u.ata.lba >> 8;
 4236         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
 4237         bytep[i++] = request->u.ata.lba >> 16;
 4238         bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
 4239         bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
 4240                    ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
 4241     }
 4242     bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
 4243     bytep[i++] = request->u.ata.command;
 4244     return i;
 4245 }
 4246 
 4247 static void
 4248 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
 4249 {
 4250     struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
 4251 
 4252     mtx_lock(&hpktp->mtx);
 4253     if (hpktp->busy) {
 4254         struct host_packet *hp = 
 4255             malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
 4256         hp->addr = hpkt;
 4257         TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
 4258     }
 4259     else {
 4260         hpktp->busy = 1;
 4261         ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
 4262     }
 4263     mtx_unlock(&hpktp->mtx);
 4264 }
 4265 
 4266 static void
 4267 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
 4268 {
 4269     struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
 4270     struct host_packet *hp;
 4271 
 4272     mtx_lock(&hpktp->mtx);
 4273     if ((hp = TAILQ_FIRST(&hpktp->queue))) {
 4274         TAILQ_REMOVE(&hpktp->queue, hp, chain);
 4275         ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
 4276         free(hp, M_TEMP);
 4277     }
 4278     else
 4279         hpktp->busy = 0;
 4280     mtx_unlock(&hpktp->mtx);
 4281 }
 4282 
 4283 
 4284 /*
 4285  * ServerWorks chipset support functions
 4286  */
 4287 int
 4288 ata_serverworks_ident(device_t dev)
 4289 {
 4290     struct ata_pci_controller *ctlr = device_get_softc(dev);
 4291     static struct ata_chip_id ids[] =
 4292     {{ ATA_ROSB4,     0x00, SWKS33,  0, ATA_UDMA2, "ROSB4" },
 4293      { ATA_CSB5,      0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
 4294      { ATA_CSB5,      0x00, SWKS66,  0, ATA_UDMA4, "CSB5" },
 4295      { ATA_CSB6,      0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
 4296      { ATA_CSB6_1,    0x00, SWKS66,  0, ATA_UDMA4, "CSB6" },
 4297      { ATA_HT1000,    0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
 4298      { ATA_HT1000_S1, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
 4299      { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
 4300      { ATA_K2,        0x00, SWKSMIO, 4, ATA_SA150, "K2" },
 4301      { ATA_FRODO4,    0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
 4302      { ATA_FRODO8,    0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
 4303      { 0, 0, 0, 0, 0, 0}};
 4304 
 4305     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 4306         return ENXIO;
 4307 
 4308     ata_set_desc(dev);
 4309     ctlr->chipinit = ata_serverworks_chipinit;
 4310     return 0;
 4311 }
 4312 
 4313 static int
 4314 ata_serverworks_chipinit(device_t dev)
 4315 {
 4316     struct ata_pci_controller *ctlr = device_get_softc(dev);
 4317 
 4318     if (ata_setup_interrupt(dev))
 4319         return ENXIO;
 4320 
 4321     if (ctlr->chip->cfg1 == SWKSMIO) {
 4322         ctlr->r_type2 = SYS_RES_MEMORY;
 4323         ctlr->r_rid2 = PCIR_BAR(5);
 4324         if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 4325                                                     &ctlr->r_rid2, RF_ACTIVE)))
 4326             return ENXIO;
 4327 
 4328         ctlr->channels = ctlr->chip->cfg2;
 4329         ctlr->allocate = ata_serverworks_allocate;
 4330         ctlr->setmode = ata_sata_setmode;
 4331         return 0;
 4332     }
 4333     else if (ctlr->chip->cfg1 == SWKS33) {
 4334         device_t *children;
 4335         int nchildren, i;
 4336 
 4337         /* locate the ISA part in the southbridge and enable UDMA33 */
 4338         if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
 4339             for (i = 0; i < nchildren; i++) {
 4340                 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
 4341                     pci_write_config(children[i], 0x64,
 4342                                      (pci_read_config(children[i], 0x64, 4) &
 4343                                       ~0x00002000) | 0x00004000, 4);
 4344                     break;
 4345                 }
 4346             }
 4347             free(children, M_TEMP);
 4348         }
 4349     }
 4350     else {
 4351         pci_write_config(dev, 0x5a,
 4352                          (pci_read_config(dev, 0x5a, 1) & ~0x40) |
 4353                          (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
 4354     }
 4355     ctlr->setmode = ata_serverworks_setmode;
 4356     return 0;
 4357 }
 4358 
 4359 static int
 4360 ata_serverworks_allocate(device_t dev)
 4361 {
 4362     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 4363     struct ata_channel *ch = device_get_softc(dev);
 4364     int ch_offset;
 4365     int i;
 4366 
 4367     ch_offset = ch->unit * 0x100;
 4368 
 4369     for (i = ATA_DATA; i < ATA_MAX_RES; i++)
 4370         ch->r_io[i].res = ctlr->r_res2;
 4371 
 4372     /* setup ATA registers */
 4373     ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
 4374     ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
 4375     ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
 4376     ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
 4377     ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
 4378     ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
 4379     ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
 4380     ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
 4381     ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
 4382     ata_default_registers(dev);
 4383 
 4384     /* setup DMA registers */
 4385     ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
 4386     ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
 4387     ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
 4388 
 4389     /* setup SATA registers */
 4390     ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
 4391     ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
 4392     ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
 4393 
 4394     ch->flags |= ATA_NO_SLAVE;
 4395     ata_pci_hw(dev);
 4396     ch->hw.tf_read = ata_serverworks_tf_read;
 4397     ch->hw.tf_write = ata_serverworks_tf_write;
 4398 
 4399     /* chip does not reliably do 64K DMA transfers */
 4400     if (ch->dma)
 4401         ch->dma->max_iosize = 64 * DEV_BSIZE;
 4402 
 4403     return 0;
 4404 }
 4405 
 4406 static void
 4407 ata_serverworks_tf_read(struct ata_request *request)
 4408 {
 4409     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 4410     struct ata_device *atadev = device_get_softc(request->dev);
 4411 
 4412     if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 4413         u_int16_t temp;
 4414 
 4415         request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
 4416         temp = ATA_IDX_INW(ch, ATA_SECTOR);
 4417         request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
 4418                              ((u_int64_t)(temp & 0xff00) << 24);
 4419         temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
 4420         request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
 4421                               ((u_int64_t)(temp & 0xff00) << 32);
 4422         temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
 4423         request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
 4424                               ((u_int64_t)(temp & 0xff00) << 40);
 4425     }
 4426     else {
 4427         request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
 4428         request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
 4429                              ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
 4430                              ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
 4431                              ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
 4432     }
 4433 }
 4434 
 4435 static void
 4436 ata_serverworks_tf_write(struct ata_request *request)
 4437 {
 4438     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 4439     struct ata_device *atadev = device_get_softc(request->dev);
 4440 
 4441     if (atadev->flags & ATA_D_48BIT_ACTIVE) {
 4442         ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
 4443         ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
 4444         ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
 4445                                       (request->u.ata.lba & 0x00ff));
 4446         ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
 4447                                        ((request->u.ata.lba >> 8) & 0x00ff));
 4448         ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 
 4449                                        ((request->u.ata.lba >> 16) & 0x00ff));
 4450         ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
 4451     }
 4452     else {
 4453         ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
 4454         ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
 4455         if (atadev->flags & ATA_D_USE_CHS) {
 4456             int heads, sectors;
 4457     
 4458             if (atadev->param.atavalid & ATA_FLAG_54_58) {
 4459                 heads = atadev->param.current_heads;
 4460                 sectors = atadev->param.current_sectors;
 4461             }
 4462             else {
 4463                 heads = atadev->param.heads;
 4464                 sectors = atadev->param.sectors;
 4465             }
 4466             ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
 4467             ATA_IDX_OUTW(ch, ATA_CYL_LSB,
 4468                          (request->u.ata.lba / (sectors * heads)));
 4469             ATA_IDX_OUTW(ch, ATA_CYL_MSB,
 4470                          (request->u.ata.lba / (sectors * heads)) >> 8);
 4471             ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 
 4472                          (((request->u.ata.lba% (sectors * heads)) /
 4473                            sectors) & 0xf));
 4474         }
 4475         else {
 4476             ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
 4477             ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
 4478             ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
 4479             ATA_IDX_OUTW(ch, ATA_DRIVE,
 4480                          ATA_D_IBM | ATA_D_LBA | atadev->unit |
 4481                          ((request->u.ata.lba >> 24) & 0x0f));
 4482         }
 4483     }
 4484 }
 4485 
 4486 static void
 4487 ata_serverworks_setmode(device_t dev, int mode)
 4488 {
 4489     device_t gparent = GRANDPARENT(dev);
 4490     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 4491     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 4492     struct ata_device *atadev = device_get_softc(dev);
 4493     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 4494     int offset = (devno ^ 0x01) << 3;
 4495     int error;
 4496     u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
 4497                               0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
 4498     u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
 4499 
 4500     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 4501 
 4502     mode = ata_check_80pin(dev, mode);
 4503 
 4504     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 4505 
 4506     if (bootverbose)
 4507         device_printf(dev, "%ssetting %s on %s chip\n",
 4508                       (error) ? "FAILURE " : "",
 4509                       ata_mode2str(mode), ctlr->chip->text);
 4510     if (!error) {
 4511         if (mode >= ATA_UDMA0) {
 4512             pci_write_config(gparent, 0x56, 
 4513                              (pci_read_config(gparent, 0x56, 2) &
 4514                               ~(0xf << (devno << 2))) |
 4515                              ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
 4516             pci_write_config(gparent, 0x54,
 4517                              pci_read_config(gparent, 0x54, 1) |
 4518                              (0x01 << devno), 1);
 4519             pci_write_config(gparent, 0x44, 
 4520                              (pci_read_config(gparent, 0x44, 4) &
 4521                               ~(0xff << offset)) |
 4522                              (dmatimings[2] << offset), 4);
 4523         }
 4524         else if (mode >= ATA_WDMA0) {
 4525             pci_write_config(gparent, 0x54,
 4526                              pci_read_config(gparent, 0x54, 1) &
 4527                               ~(0x01 << devno), 1);
 4528             pci_write_config(gparent, 0x44, 
 4529                              (pci_read_config(gparent, 0x44, 4) &
 4530                               ~(0xff << offset)) |
 4531                              (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
 4532         }
 4533         else
 4534             pci_write_config(gparent, 0x54,
 4535                              pci_read_config(gparent, 0x54, 1) &
 4536                              ~(0x01 << devno), 1);
 4537 
 4538         pci_write_config(gparent, 0x40, 
 4539                          (pci_read_config(gparent, 0x40, 4) &
 4540                           ~(0xff << offset)) |
 4541                          (piotimings[ata_mode2idx(mode)] << offset), 4);
 4542         atadev->mode = mode;
 4543     }
 4544 }
 4545 
 4546 
 4547 /*
 4548  * Silicon Image Inc. (SiI) (former CMD) chipset support functions
 4549  */
 4550 int
 4551 ata_sii_ident(device_t dev)
 4552 {
 4553     struct ata_pci_controller *ctlr = device_get_softc(dev);
 4554     static struct ata_chip_id ids[] =
 4555     {{ ATA_SII3114,   0x00, SIIMEMIO, SII4CH,    ATA_SA150, "SiI 3114" },
 4556      { ATA_SII3512,   0x02, SIIMEMIO, 0,         ATA_SA150, "SiI 3512" },
 4557      { ATA_SII3112,   0x02, SIIMEMIO, 0,         ATA_SA150, "SiI 3112" },
 4558      { ATA_SII3112_1, 0x02, SIIMEMIO, 0,         ATA_SA150, "SiI 3112" },
 4559      { ATA_SII3512,   0x00, SIIMEMIO, SIIBUG,    ATA_SA150, "SiI 3512" },
 4560      { ATA_SII3112,   0x00, SIIMEMIO, SIIBUG,    ATA_SA150, "SiI 3112" },
 4561      { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG,    ATA_SA150, "SiI 3112" },
 4562      { ATA_SII3124,   0x00, SIIPRBIO, SII4CH,    ATA_SA300, "SiI 3124" },
 4563      { ATA_SII3132,   0x00, SIIPRBIO, 0,         ATA_SA300, "SiI 3132" },
 4564      { ATA_SII3132_1, 0x00, SIIPRBIO, 0,         ATA_SA300, "SiI 3132" },
 4565      { ATA_SII0680,   0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
 4566      { ATA_CMD649,    0x00, 0,        SIIINTR,   ATA_UDMA5, "CMD 649" },
 4567      { ATA_CMD648,    0x00, 0,        SIIINTR,   ATA_UDMA4, "CMD 648" },
 4568      { ATA_CMD646,    0x07, 0,        0,         ATA_UDMA2, "CMD 646U2" },
 4569      { ATA_CMD646,    0x00, 0,        0,         ATA_WDMA2, "CMD 646" },
 4570      { 0, 0, 0, 0, 0, 0}};
 4571 
 4572     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 4573         return ENXIO;
 4574 
 4575     ata_set_desc(dev);
 4576     ctlr->chipinit = ata_sii_chipinit;
 4577     return 0;
 4578 }
 4579 
 4580 static int
 4581 ata_sii_chipinit(device_t dev)
 4582 {
 4583     struct ata_pci_controller *ctlr = device_get_softc(dev);
 4584 
 4585     if (ata_setup_interrupt(dev))
 4586         return ENXIO;
 4587 
 4588     switch (ctlr->chip->cfg1) {
 4589     case SIIPRBIO:
 4590         ctlr->r_type1 = SYS_RES_MEMORY;
 4591         ctlr->r_rid1 = PCIR_BAR(0);
 4592         if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
 4593                                                     &ctlr->r_rid1, RF_ACTIVE)))
 4594             return ENXIO;
 4595 
 4596         ctlr->r_rid2 = PCIR_BAR(2);
 4597         ctlr->r_type2 = SYS_RES_MEMORY;
 4598         if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 4599                                                     &ctlr->r_rid2, RF_ACTIVE))){
 4600             bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
 4601             return ENXIO;
 4602         }
 4603         ctlr->allocate = ata_siiprb_allocate;
 4604         ctlr->reset = ata_siiprb_reset;
 4605         ctlr->dmainit = ata_siiprb_dmainit;
 4606         ctlr->setmode = ata_sata_setmode;
 4607         ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
 4608 
 4609         /* reset controller */
 4610         ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
 4611         DELAY(10000);
 4612         ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
 4613         break;
 4614 
 4615     case SIIMEMIO:
 4616         ctlr->r_type2 = SYS_RES_MEMORY;
 4617         ctlr->r_rid2 = PCIR_BAR(5);
 4618         if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 4619                                                     &ctlr->r_rid2, RF_ACTIVE))){
 4620             if (ctlr->chip->chipid != ATA_SII0680 ||
 4621                             (pci_read_config(dev, 0x8a, 1) & 1))
 4622                 return ENXIO;
 4623         }
 4624 
 4625         if (ctlr->chip->cfg2 & SIISETCLK) {
 4626             if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
 4627                 pci_write_config(dev, 0x8a,
 4628                                  (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
 4629             if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
 4630                 device_printf(dev, "%s could not set ATA133 clock\n",
 4631                               ctlr->chip->text);
 4632         }
 4633 
 4634         /* if we have 4 channels enable the second set */
 4635         if (ctlr->chip->cfg2 & SII4CH) {
 4636             ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
 4637             ctlr->channels = 4;
 4638         }
 4639 
 4640         /* dont block interrupts from any channel */
 4641         pci_write_config(dev, 0x48,
 4642                          (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
 4643 
 4644         /* enable PCI interrupt as BIOS might not */
 4645         pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
 4646 
 4647         if (ctlr->r_res2)
 4648             ctlr->allocate = ata_sii_allocate;
 4649 
 4650         if (ctlr->chip->max_dma >= ATA_SA150) {
 4651             ctlr->reset = ata_sii_reset;
 4652             ctlr->setmode = ata_sata_setmode;
 4653         }
 4654         else
 4655             ctlr->setmode = ata_sii_setmode;
 4656         break;
 4657     
 4658     default:
 4659         if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
 4660             device_printf(dev, "HW has secondary channel disabled\n");
 4661             ctlr->channels = 1;
 4662         }    
 4663 
 4664         /* enable interrupt as BIOS might not */
 4665         pci_write_config(dev, 0x71, 0x01, 1);
 4666 
 4667         ctlr->allocate = ata_cmd_allocate;
 4668         ctlr->setmode = ata_cmd_setmode;
 4669         break;
 4670     }
 4671     return 0;
 4672 }
 4673 
 4674 static int
 4675 ata_cmd_allocate(device_t dev)
 4676 {
 4677     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 4678     struct ata_channel *ch = device_get_softc(dev);
 4679 
 4680     /* setup the usual register normal pci style */
 4681     if (ata_pci_allocate(dev))
 4682         return ENXIO;
 4683 
 4684     if (ctlr->chip->cfg2 & SIIINTR)
 4685         ch->hw.status = ata_cmd_status;
 4686 
 4687     return 0;
 4688 }
 4689 
 4690 static int
 4691 ata_cmd_status(device_t dev)
 4692 {
 4693     struct ata_channel *ch = device_get_softc(dev);
 4694     u_int8_t reg71;
 4695 
 4696     if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
 4697          (ch->unit ? 0x08 : 0x04))) {
 4698         pci_write_config(device_get_parent(ch->dev), 0x71,
 4699                          reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
 4700         return ata_pci_status(dev);
 4701     }
 4702     return 0;
 4703 }
 4704 
 4705 static void
 4706 ata_cmd_setmode(device_t dev, int mode)
 4707 {
 4708     device_t gparent = GRANDPARENT(dev);
 4709     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 4710     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 4711     struct ata_device *atadev = device_get_softc(dev);
 4712     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 4713     int error;
 4714 
 4715     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 4716 
 4717     mode = ata_check_80pin(dev, mode);
 4718 
 4719     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 4720 
 4721     if (bootverbose)
 4722         device_printf(dev, "%ssetting %s on %s chip\n",
 4723                       (error) ? "FAILURE " : "",
 4724                       ata_mode2str(mode), ctlr->chip->text);
 4725     if (!error) {
 4726         int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
 4727         int ureg = ch->unit ? 0x7b : 0x73;
 4728 
 4729         if (mode >= ATA_UDMA0) {        
 4730             int udmatimings[][2] = { { 0x31,  0xc2 }, { 0x21,  0x82 },
 4731                                      { 0x11,  0x42 }, { 0x25,  0x8a },
 4732                                      { 0x15,  0x4a }, { 0x05,  0x0a } };
 4733 
 4734             u_int8_t umode = pci_read_config(gparent, ureg, 1);
 4735 
 4736             umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
 4737             umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
 4738             pci_write_config(gparent, ureg, umode, 1);
 4739         }
 4740         else if (mode >= ATA_WDMA0) { 
 4741             int dmatimings[] = { 0x87, 0x32, 0x3f };
 4742 
 4743             pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
 4744             pci_write_config(gparent, ureg, 
 4745                              pci_read_config(gparent, ureg, 1) &
 4746                              ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
 4747         }
 4748         else {
 4749            int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
 4750             pci_write_config(gparent, treg,
 4751                              piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
 4752             pci_write_config(gparent, ureg, 
 4753                              pci_read_config(gparent, ureg, 1) &
 4754                              ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
 4755         }
 4756         atadev->mode = mode;
 4757     }
 4758 }
 4759 
 4760 static int
 4761 ata_sii_allocate(device_t dev)
 4762 {
 4763     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 4764     struct ata_channel *ch = device_get_softc(dev);
 4765     int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
 4766     int i;
 4767 
 4768     for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
 4769         ch->r_io[i].res = ctlr->r_res2;
 4770         ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
 4771     }
 4772     ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
 4773     ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
 4774     ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
 4775     ata_default_registers(dev);
 4776 
 4777     ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
 4778     ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
 4779     ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
 4780     ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
 4781     ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
 4782     ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
 4783 
 4784     if (ctlr->chip->max_dma >= ATA_SA150) {
 4785         ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
 4786         ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
 4787         ch->r_io[ATA_SERROR].res = ctlr->r_res2;
 4788         ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
 4789         ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
 4790         ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
 4791         ch->flags |= ATA_NO_SLAVE;
 4792 
 4793         /* enable PHY state change interrupt */
 4794         ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
 4795     }
 4796 
 4797     if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
 4798         /* work around errata in early chips */
 4799         ch->dma->boundary = 8192;
 4800         ch->dma->segsize = 15 * DEV_BSIZE;
 4801     }
 4802 
 4803     ata_pci_hw(dev);
 4804     ch->hw.status = ata_sii_status;
 4805     return 0;
 4806 }
 4807 
 4808 static int
 4809 ata_sii_status(device_t dev)
 4810 {
 4811     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 4812     struct ata_channel *ch = device_get_softc(dev);
 4813     int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
 4814     int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
 4815 
 4816     /* do we have any PHY events ? */
 4817     if (ctlr->chip->max_dma >= ATA_SA150 &&
 4818         (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
 4819         ata_sata_phy_check_events(dev);
 4820 
 4821     if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
 4822         return ata_pci_status(dev);
 4823     else
 4824         return 0;
 4825 }
 4826 
 4827 static void
 4828 ata_sii_reset(device_t dev)
 4829 {
 4830     if (ata_sata_phy_reset(dev))
 4831         ata_generic_reset(dev);
 4832 }
 4833 
 4834 static void
 4835 ata_sii_setmode(device_t dev, int mode)
 4836 {
 4837     device_t gparent = GRANDPARENT(dev);
 4838     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 4839     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 4840     struct ata_device *atadev = device_get_softc(dev);
 4841     int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
 4842     int mreg = ch->unit ? 0x84 : 0x80;
 4843     int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
 4844     int mval = pci_read_config(gparent, mreg, 1) & ~mask;
 4845     int error;
 4846 
 4847     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 4848 
 4849     if (ctlr->chip->cfg2 & SIISETCLK) {
 4850         if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
 4851                                  (ch->unit ? 0x02 : 0x01))) {
 4852             ata_print_cable(dev, "controller");
 4853             mode = ATA_UDMA2;
 4854         }
 4855     }
 4856     else
 4857         mode = ata_check_80pin(dev, mode);
 4858 
 4859     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 4860 
 4861     if (bootverbose)
 4862         device_printf(dev, "%ssetting %s on %s chip\n",
 4863                       (error) ? "FAILURE " : "",
 4864                       ata_mode2str(mode), ctlr->chip->text);
 4865     if (error)
 4866         return;
 4867 
 4868     if (mode >= ATA_UDMA0) {
 4869         u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
 4870         u_int8_t ureg = 0xac + rego;
 4871 
 4872         pci_write_config(gparent, mreg,
 4873                          mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
 4874         pci_write_config(gparent, ureg, 
 4875                          (pci_read_config(gparent, ureg, 1) & ~0x3f) |
 4876                          udmatimings[mode & ATA_MODE_MASK], 1);
 4877 
 4878     }
 4879     else if (mode >= ATA_WDMA0) {
 4880         u_int8_t dreg = 0xa8 + rego;
 4881         u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
 4882 
 4883         pci_write_config(gparent, mreg,
 4884                          mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
 4885         pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
 4886 
 4887     }
 4888     else {
 4889         u_int8_t preg = 0xa4 + rego;
 4890         u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
 4891 
 4892         pci_write_config(gparent, mreg,
 4893                          mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
 4894         pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
 4895     }
 4896     atadev->mode = mode;
 4897 }
 4898 
 4899 
 4900 struct ata_siiprb_dma_prdentry {
 4901     u_int64_t addr;
 4902     u_int32_t count;
 4903     u_int32_t control;
 4904 } __packed;
 4905 
 4906 struct ata_siiprb_ata_command {
 4907     struct ata_siiprb_dma_prdentry prd[126];
 4908 } __packed;
 4909 
 4910 struct ata_siiprb_atapi_command {
 4911     u_int8_t ccb[16];
 4912     struct ata_siiprb_dma_prdentry prd[125];
 4913 } __packed;
 4914 
 4915 struct ata_siiprb_command {
 4916     u_int16_t control;
 4917     u_int16_t protocol_override;
 4918     u_int32_t transfer_count;
 4919     u_int8_t fis[24];
 4920     union {
 4921         struct ata_siiprb_ata_command ata;
 4922         struct ata_siiprb_atapi_command atapi;
 4923     } u;
 4924 } __packed;
 4925 
 4926 static int
 4927 ata_siiprb_allocate(device_t dev)
 4928 {
 4929     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 4930     struct ata_channel *ch = device_get_softc(dev);
 4931     int offset = ch->unit * 0x2000;
 4932 
 4933     /* set the SATA resources */
 4934     ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
 4935     ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
 4936     ch->r_io[ATA_SERROR].res = ctlr->r_res2;
 4937     ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
 4938     ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
 4939     ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
 4940     ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
 4941     ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
 4942    
 4943     ch->hw.begin_transaction = ata_siiprb_begin_transaction;
 4944     ch->hw.end_transaction = ata_siiprb_end_transaction;
 4945     ch->hw.status = ata_siiprb_status;
 4946     ch->hw.command = NULL;      /* not used here */
 4947     return 0;
 4948 }
 4949 
 4950 static int
 4951 ata_siiprb_status(device_t dev)
 4952 {
 4953     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 4954     struct ata_channel *ch = device_get_softc(dev);
 4955     u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
 4956     int offset = ch->unit * 0x2000;
 4957 
 4958     if (action & (1 << ch->unit)) {
 4959         u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
 4960 
 4961         /* do we have any PHY events ? */
 4962         ata_sata_phy_check_events(dev);
 4963 
 4964         /* clear interrupt(s) */
 4965         ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
 4966 
 4967         /* do we have any device action ? */
 4968         return (istatus & 0x00000003);
 4969     }
 4970     return 0;
 4971 }
 4972 
 4973 static int
 4974 ata_siiprb_begin_transaction(struct ata_request *request)
 4975 {
 4976     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
 4977     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 4978     struct ata_siiprb_command *prb;
 4979     struct ata_siiprb_dma_prdentry *prd;
 4980     int offset = ch->unit * 0x2000;
 4981     u_int64_t prb_bus;
 4982     int tag = 0, dummy;
 4983 
 4984     /* SOS XXX */
 4985     if (request->u.ata.command == ATA_DEVICE_RESET) {
 4986         request->result = 0;
 4987         return ATA_OP_FINISHED;
 4988     }
 4989 
 4990     /* check for 48 bit access and convert if needed */
 4991     ata_modify_if_48bit(request);
 4992 
 4993     /* get a piece of the workspace for this request */
 4994     prb = (struct ata_siiprb_command *)
 4995         (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
 4996 
 4997     /* set basic prd options ata/atapi etc etc */
 4998     bzero(prb, sizeof(struct ata_siiprb_command));
 4999 
 5000     /* setup the FIS for this request */
 5001     if (!ata_request2fis_h2d(request, &prb->fis[0])) {
 5002         device_printf(request->dev, "setting up SATA FIS failed\n");
 5003         request->result = EIO;
 5004         return ATA_OP_FINISHED;
 5005     }
 5006 
 5007     /* setup transfer type */
 5008     if (request->flags & ATA_R_ATAPI) {
 5009         struct ata_device *atadev = device_get_softc(request->dev);
 5010 
 5011         bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
 5012         if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
 5013             ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
 5014         else
 5015             ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
 5016         if (request->flags & ATA_R_READ)
 5017             prb->control = htole16(0x0010);
 5018         if (request->flags & ATA_R_WRITE)
 5019             prb->control = htole16(0x0020);
 5020         prd = &prb->u.atapi.prd[0];
 5021     }
 5022     else
 5023         prd = &prb->u.ata.prd[0];
 5024 
 5025     /* if request moves data setup and load SG list */
 5026     if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
 5027         if (ch->dma->load(ch->dev, request->data, request->bytecount,
 5028                           request->flags & ATA_R_READ, prd, &dummy)) {
 5029             device_printf(request->dev, "setting up DMA failed\n");
 5030             request->result = EIO;
 5031             return ATA_OP_FINISHED;
 5032         }
 5033     }
 5034 
 5035     /* activate the prb */
 5036     prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
 5037     ATA_OUTL(ctlr->r_res2,
 5038              0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
 5039     ATA_OUTL(ctlr->r_res2,
 5040              0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
 5041 
 5042     /* start the timeout */
 5043     callout_reset(&request->callout, request->timeout * hz,
 5044                   (timeout_t*)ata_timeout, request);
 5045     return ATA_OP_CONTINUES;
 5046 }
 5047 
 5048 static int
 5049 ata_siiprb_end_transaction(struct ata_request *request)
 5050 {
 5051     struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
 5052     struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
 5053     struct ata_siiprb_command *prb;
 5054     int offset = ch->unit * 0x2000;
 5055     int error, timeout, tag = 0;
 5056 
 5057     /* kill the timeout */
 5058     callout_stop(&request->callout);
 5059     
 5060     prb = (struct ata_siiprb_command *)
 5061         ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
 5062 
 5063     /* any controller errors flagged ? */
 5064     if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
 5065         if (bootverbose)
 5066             printf("ata_siiprb_end_transaction %s error=%08x\n",
 5067                    ata_cmd2str(request), error);
 5068 
 5069         /* if device error status get details */
 5070         if (error == 1 || error == 2) {
 5071             request->status = prb->fis[2];
 5072             if (request->status & ATA_S_ERROR)
 5073                 request->error = prb->fis[3];
 5074         }
 5075 
 5076         /* SOS XXX handle other controller errors here */
 5077 
 5078         /* initialize port */
 5079         ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
 5080 
 5081         /* poll for port ready */
 5082         for (timeout = 0; timeout < 1000; timeout++) {
 5083             DELAY(1000);
 5084             if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
 5085                 break;
 5086         }
 5087         if (bootverbose) {
 5088             if (timeout >= 1000)
 5089                 device_printf(ch->dev, "port initialize timeout\n");
 5090             else
 5091                 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
 5092         }
 5093     }
 5094 
 5095     /* update progress */
 5096     if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
 5097         if (request->flags & ATA_R_READ)
 5098             request->donecount = prb->transfer_count;
 5099         else
 5100             request->donecount = request->bytecount;
 5101     }
 5102 
 5103     /* release SG list etc */
 5104     ch->dma->unload(ch->dev);
 5105 
 5106     return ATA_OP_FINISHED;
 5107 }
 5108 
 5109 static void
 5110 ata_siiprb_reset(device_t dev)
 5111 {
 5112     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 5113     struct ata_channel *ch = device_get_softc(dev);
 5114     int offset = ch->unit * 0x2000;
 5115     struct ata_siiprb_command *prb;
 5116     u_int64_t prb_bus;
 5117     u_int32_t status, signature;
 5118     int timeout, tag = 0;
 5119 
 5120     /* reset channel HW */
 5121     ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
 5122     DELAY(1000);
 5123     ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
 5124     DELAY(10000);
 5125 
 5126     /* poll for channel ready */
 5127     for (timeout = 0; timeout < 1000; timeout++) {
 5128         if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
 5129             break;
 5130         DELAY(1000);
 5131     }
 5132 
 5133     if (bootverbose) {
 5134         if (timeout >= 1000)
 5135             device_printf(ch->dev, "channel HW reset timeout\n");
 5136         else
 5137             device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
 5138     }
 5139 
 5140     /* reset phy */
 5141     if (!ata_sata_phy_reset(dev)) {
 5142         if (bootverbose)
 5143             device_printf(ch->dev, "phy reset found no device\n");
 5144         ch->devices = 0;
 5145         goto finish;
 5146     }
 5147 
 5148     /* get a piece of the workspace for a soft reset request */
 5149     prb = (struct ata_siiprb_command *)
 5150         (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
 5151     bzero(prb, sizeof(struct ata_siiprb_command));
 5152     prb->control = htole16(0x0080);
 5153 
 5154     /* activate the soft reset prb */
 5155     prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
 5156     ATA_OUTL(ctlr->r_res2,
 5157              0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
 5158     ATA_OUTL(ctlr->r_res2,
 5159              0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
 5160 
 5161     /* poll for command finished */
 5162     for (timeout = 0; timeout < 10000; timeout++) {
 5163         DELAY(1000);
 5164         if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
 5165             break;
 5166     }
 5167     if (timeout >= 1000) {
 5168         device_printf(ch->dev, "reset timeout - no device found\n");
 5169         ch->devices = 0;
 5170         goto finish;
 5171     }
 5172     if (bootverbose)
 5173         device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
 5174                         timeout, status);
 5175 
 5176     /* find out whats there */
 5177     prb = (struct ata_siiprb_command *)
 5178         ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
 5179     signature =
 5180         prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
 5181     if (bootverbose)
 5182         device_printf(ch->dev, "SIGNATURE=%08x\n", signature);
 5183     switch (signature) {
 5184     case 0x00000101:
 5185         ch->devices = ATA_ATA_MASTER;
 5186         break;
 5187     case 0x96690101:
 5188         ch->devices = ATA_PORTMULTIPLIER;
 5189         device_printf(ch->dev, "Portmultipliers not supported yet\n");
 5190         ch->devices = 0;
 5191         break;
 5192     case 0xeb140101:
 5193         ch->devices = ATA_ATAPI_MASTER;
 5194         break;
 5195     default:
 5196         ch->devices = 0;
 5197     }
 5198     if (bootverbose)
 5199         device_printf(dev, "siiprb_reset devices=0x%b\n", ch->devices,
 5200                       "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
 5201 
 5202 finish:
 5203     /* clear interrupt(s) */
 5204     ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
 5205 
 5206     /* require explicit interrupt ack */
 5207     ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
 5208 
 5209     /* 64bit mode */
 5210     ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
 5211 
 5212     /* enable interrupts wanted */
 5213     ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
 5214 }
 5215 
 5216 static void
 5217 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
 5218 {
 5219     struct ata_dmasetprd_args *args = xsc;
 5220     struct ata_siiprb_dma_prdentry *prd = args->dmatab;
 5221     int i;
 5222 
 5223     if ((args->error = error))
 5224         return;
 5225 
 5226     for (i = 0; i < nsegs; i++) {
 5227         prd[i].addr = htole64(segs[i].ds_addr);
 5228         prd[i].count = htole32(segs[i].ds_len);
 5229     }
 5230     prd[i - 1].control = htole32(ATA_DMA_EOT);
 5231     KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
 5232     args->nsegs = nsegs;
 5233 }
 5234 
 5235 static void
 5236 ata_siiprb_dmainit(device_t dev)
 5237 {
 5238     struct ata_channel *ch = device_get_softc(dev);
 5239 
 5240     ata_dmainit(dev);
 5241     if (ch->dma) {
 5242         /* note start and stop are not used here */
 5243         ch->dma->setprd = ata_siiprb_dmasetprd;
 5244         ch->dma->max_address = BUS_SPACE_MAXADDR;
 5245     }
 5246 }
 5247 
 5248 
 5249 /*
 5250  * Silicon Integrated Systems Corp. (SiS) chipset support functions
 5251  */
 5252 int
 5253 ata_sis_ident(device_t dev)
 5254 {
 5255     struct ata_pci_controller *ctlr = device_get_softc(dev);
 5256     struct ata_chip_id *idx;
 5257     static struct ata_chip_id ids[] =
 5258     {{ ATA_SIS182,  0x00, SISSATA,   0, ATA_SA150, "182" }, /* south */
 5259      { ATA_SIS181,  0x00, SISSATA,   0, ATA_SA150, "181" }, /* south */
 5260      { ATA_SIS180,  0x00, SISSATA,   0, ATA_SA150, "180" }, /* south */
 5261      { ATA_SIS965,  0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
 5262      { ATA_SIS964,  0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
 5263      { ATA_SIS963,  0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
 5264      { ATA_SIS962,  0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
 5265 
 5266      { ATA_SIS745,  0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
 5267      { ATA_SIS735,  0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
 5268      { ATA_SIS733,  0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
 5269      { ATA_SIS730,  0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
 5270 
 5271      { ATA_SIS635,  0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
 5272      { ATA_SIS633,  0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
 5273      { ATA_SIS630,  0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
 5274      { ATA_SIS630,  0x00, SIS66,     0, ATA_UDMA4, "630" }, /* 1chip */
 5275      { ATA_SIS620,  0x00, SIS66,     0, ATA_UDMA4, "620" }, /* 1chip */
 5276 
 5277      { ATA_SIS550,  0x00, SIS66,     0, ATA_UDMA5, "550" },
 5278      { ATA_SIS540,  0x00, SIS66,     0, ATA_UDMA4, "540" },
 5279      { ATA_SIS530,  0x00, SIS66,     0, ATA_UDMA4, "530" },
 5280 
 5281      { ATA_SIS5513, 0xc2, SIS33,     1, ATA_UDMA2, "5513" },
 5282      { ATA_SIS5513, 0x00, SIS33,     1, ATA_WDMA2, "5513" },
 5283      { 0, 0, 0, 0, 0, 0 }};
 5284     char buffer[64];
 5285     int found = 0;
 5286 
 5287     if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 
 5288         return ENXIO;
 5289 
 5290     if (idx->cfg2 && !found) {
 5291         u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
 5292 
 5293         pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
 5294         if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
 5295             found = 1;
 5296             idx->cfg1 = SIS133NEW;
 5297             idx->max_dma = ATA_UDMA6;
 5298             sprintf(buffer, "SiS 962/963 %s controller",
 5299                     ata_mode2str(idx->max_dma));
 5300         }
 5301         pci_write_config(dev, 0x57, reg57, 1);
 5302     }
 5303     if (idx->cfg2 && !found) {
 5304         u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
 5305 
 5306         pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
 5307         if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
 5308             struct ata_chip_id id[] =
 5309                 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
 5310 
 5311             found = 1;
 5312             if (ata_find_chip(dev, id, pci_get_slot(dev))) {
 5313                 idx->cfg1 = SIS133OLD;
 5314                 idx->max_dma = ATA_UDMA6;
 5315             }
 5316             else {
 5317                 idx->cfg1 = SIS100NEW;
 5318                 idx->max_dma = ATA_UDMA5;
 5319             }
 5320             sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
 5321         }
 5322         pci_write_config(dev, 0x4a, reg4a, 1);
 5323     }
 5324     if (!found)
 5325         sprintf(buffer,"SiS %s %s controller",
 5326                 idx->text, ata_mode2str(idx->max_dma));
 5327 
 5328     device_set_desc_copy(dev, buffer);
 5329     ctlr->chip = idx;
 5330     ctlr->chipinit = ata_sis_chipinit;
 5331     return 0;
 5332 }
 5333 
 5334 static int
 5335 ata_sis_chipinit(device_t dev)
 5336 {
 5337     struct ata_pci_controller *ctlr = device_get_softc(dev);
 5338 
 5339     if (ata_setup_interrupt(dev))
 5340         return ENXIO;
 5341     
 5342     switch (ctlr->chip->cfg1) {
 5343     case SIS33:
 5344         break;
 5345     case SIS66:
 5346     case SIS100OLD:
 5347         pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
 5348         break;
 5349     case SIS100NEW:
 5350     case SIS133OLD:
 5351         pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
 5352         break;
 5353     case SIS133NEW:
 5354         pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
 5355         pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
 5356         break;
 5357     case SISSATA:
 5358         ctlr->r_type2 = SYS_RES_IOPORT;
 5359         ctlr->r_rid2 = PCIR_BAR(5);
 5360         if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 5361                                                    &ctlr->r_rid2, RF_ACTIVE))) {
 5362             ctlr->allocate = ata_sis_allocate;
 5363             ctlr->reset = ata_sis_reset;
 5364         }
 5365         ctlr->setmode = ata_sata_setmode;
 5366         return 0;
 5367     default:
 5368         return ENXIO;
 5369     }
 5370     ctlr->setmode = ata_sis_setmode;
 5371     return 0;
 5372 }
 5373 
 5374 static int
 5375 ata_sis_allocate(device_t dev)
 5376 {
 5377     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 5378     struct ata_channel *ch = device_get_softc(dev);
 5379     int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
 5380 
 5381     /* setup the usual register normal pci style */
 5382     if (ata_pci_allocate(dev))
 5383         return ENXIO;
 5384 
 5385     ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
 5386     ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
 5387     ch->r_io[ATA_SERROR].res = ctlr->r_res2;
 5388     ch->r_io[ATA_SERROR].offset = 0x04 + offset;
 5389     ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
 5390     ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
 5391     ch->flags |= ATA_NO_SLAVE;
 5392 
 5393     /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
 5394     /* XXX SOS unknown how to enable PHY state change interrupt */
 5395     return 0;
 5396 }
 5397 
 5398 static void
 5399 ata_sis_reset(device_t dev)
 5400 {
 5401     if (ata_sata_phy_reset(dev))
 5402         ata_generic_reset(dev);
 5403 }
 5404 
 5405 static void
 5406 ata_sis_setmode(device_t dev, int mode)
 5407 {
 5408     device_t gparent = GRANDPARENT(dev);
 5409     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 5410     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 5411     struct ata_device *atadev = device_get_softc(dev);
 5412     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 5413     int error;
 5414 
 5415     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 5416 
 5417     if (ctlr->chip->cfg1 == SIS133NEW) {
 5418         if (mode > ATA_UDMA2 &&
 5419             pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
 5420             ata_print_cable(dev, "controller");
 5421             mode = ATA_UDMA2;
 5422         }
 5423     }
 5424     else {
 5425         if (mode > ATA_UDMA2 &&
 5426             pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
 5427             ata_print_cable(dev, "controller");
 5428             mode = ATA_UDMA2;
 5429         }
 5430     }
 5431 
 5432     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 5433 
 5434     if (bootverbose)
 5435         device_printf(dev, "%ssetting %s on %s chip\n",
 5436                       (error) ? "FAILURE " : "",
 5437                       ata_mode2str(mode), ctlr->chip->text);
 5438     if (!error) {
 5439         switch (ctlr->chip->cfg1) {
 5440         case SIS133NEW: {
 5441             u_int32_t timings[] = 
 5442                 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
 5443                   0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
 5444                   0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
 5445             u_int32_t reg;
 5446 
 5447             reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
 5448             pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
 5449             break;
 5450             }
 5451         case SIS133OLD: {
 5452             u_int16_t timings[] =
 5453              { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
 5454                0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
 5455                   
 5456             u_int16_t reg = 0x40 + (devno << 1);
 5457 
 5458             pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
 5459             break;
 5460             }
 5461         case SIS100NEW: {
 5462             u_int16_t timings[] =
 5463                 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
 5464                   0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
 5465             u_int16_t reg = 0x40 + (devno << 1);
 5466 
 5467             pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
 5468             break;
 5469             }
 5470         case SIS100OLD:
 5471         case SIS66:
 5472         case SIS33: {
 5473             u_int16_t timings[] =
 5474                 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
 5475                   0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
 5476             u_int16_t reg = 0x40 + (devno << 1);
 5477 
 5478             pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
 5479             break;
 5480             }
 5481         }
 5482         atadev->mode = mode;
 5483     }
 5484 }
 5485 
 5486 
 5487 /* VIA Technologies Inc. chipset support functions */
 5488 int
 5489 ata_via_ident(device_t dev)
 5490 {
 5491     struct ata_pci_controller *ctlr = device_get_softc(dev);
 5492     static struct ata_chip_id ids[] =
 5493     {{ ATA_VIA82C586, 0x02, VIA33,  0x00,    ATA_UDMA2, "82C586B" },
 5494      { ATA_VIA82C586, 0x00, VIA33,  0x00,    ATA_WDMA2, "82C586" },
 5495      { ATA_VIA82C596, 0x12, VIA66,  VIACLK,  ATA_UDMA4, "82C596B" },
 5496      { ATA_VIA82C596, 0x00, VIA33,  0x00,    ATA_UDMA2, "82C596" },
 5497      { ATA_VIA82C686, 0x40, VIA100, VIABUG,  ATA_UDMA5, "82C686B"},
 5498      { ATA_VIA82C686, 0x10, VIA66,  VIACLK,  ATA_UDMA4, "82C686A" },
 5499      { ATA_VIA82C686, 0x00, VIA33,  0x00,    ATA_UDMA2, "82C686" },
 5500      { ATA_VIA8231,   0x00, VIA100, VIABUG,  ATA_UDMA5, "8231" },
 5501      { ATA_VIA8233,   0x00, VIA100, 0x00,    ATA_UDMA5, "8233" },
 5502      { ATA_VIA8233C,  0x00, VIA100, 0x00,    ATA_UDMA5, "8233C" },
 5503      { ATA_VIA8233A,  0x00, VIA133, 0x00,    ATA_UDMA6, "8233A" },
 5504      { ATA_VIA8235,   0x00, VIA133, 0x00,    ATA_UDMA6, "8235" },
 5505      { ATA_VIA8237,   0x00, VIA133, 0x00,    ATA_UDMA6, "8237" },
 5506      { ATA_VIA8237A,  0x00, VIA133, 0x00,    ATA_UDMA6, "8237A" },
 5507      { ATA_VIA8237S,  0x00, VIA133, 0x00,    ATA_UDMA6, "8237S" },
 5508      { ATA_VIA8251,   0x00, VIA133, 0x00,    ATA_UDMA6, "8251" },
 5509      { 0, 0, 0, 0, 0, 0 }};
 5510     static struct ata_chip_id new_ids[] =
 5511     {{ ATA_VIA6410,   0x00, 0,      0x00,    ATA_UDMA6, "6410" },
 5512      { ATA_VIA6420,   0x00, 7,      0x00,    ATA_SA150, "6420" },
 5513      { ATA_VIA6421,   0x00, 6,      VIABAR,  ATA_SA150, "6421" },
 5514      { ATA_VIA8237A,  0x00, 7,      0x00,    ATA_SA150, "8237A" },
 5515      { ATA_VIA8237S,  0x00, 7,      0x00,    ATA_SA150, "8237S" },
 5516      { ATA_VIA8251,   0x00, 0,      VIAAHCI, ATA_SA300, "8251" },
 5517      { 0, 0, 0, 0, 0, 0 }};
 5518 
 5519     if (pci_get_devid(dev) == ATA_VIA82C571) {
 5520         if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 
 5521             return ENXIO;
 5522     }
 5523     else {
 5524         if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 
 5525             return ENXIO;
 5526     }
 5527 
 5528     ata_set_desc(dev);
 5529     ctlr->chipinit = ata_via_chipinit;
 5530     return 0;
 5531 }
 5532 
 5533 static int
 5534 ata_via_chipinit(device_t dev)
 5535 {
 5536     struct ata_pci_controller *ctlr = device_get_softc(dev);
 5537 
 5538     if (ata_setup_interrupt(dev))
 5539         return ENXIO;
 5540     
 5541     if (ctlr->chip->max_dma >= ATA_SA150) {
 5542         /* do we have AHCI capability ? */
 5543         if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
 5544             return 0;
 5545 
 5546         ctlr->r_type2 = SYS_RES_IOPORT;
 5547         ctlr->r_rid2 = PCIR_BAR(5);
 5548         if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
 5549                                                    &ctlr->r_rid2, RF_ACTIVE))) {
 5550             ctlr->allocate = ata_via_allocate;
 5551             ctlr->reset = ata_via_reset;
 5552         }
 5553 
 5554         if (ctlr->chip->cfg2 & VIABAR) {
 5555             ctlr->channels = 3;
 5556             ctlr->setmode = ata_via_setmode;
 5557         }
 5558         else
 5559             ctlr->setmode = ata_sata_setmode;
 5560         return 0;
 5561     }
 5562 
 5563     /* prepare for ATA-66 on the 82C686a and 82C596b */
 5564     if (ctlr->chip->cfg2 & VIACLK)
 5565         pci_write_config(dev, 0x50, 0x030b030b, 4);       
 5566 
 5567     /* the southbridge might need the data corruption fix */
 5568     if (ctlr->chip->cfg2 & VIABUG)
 5569         ata_via_southbridge_fixup(dev);
 5570 
 5571     /* set fifo configuration half'n'half */
 5572     pci_write_config(dev, 0x43, 
 5573                      (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
 5574 
 5575     /* set status register read retry */
 5576     pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
 5577 
 5578     /* set DMA read & end-of-sector fifo flush */
 5579     pci_write_config(dev, 0x46, 
 5580                      (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
 5581 
 5582     /* set sector size */
 5583     pci_write_config(dev, 0x60, DEV_BSIZE, 2);
 5584     pci_write_config(dev, 0x68, DEV_BSIZE, 2);
 5585 
 5586     ctlr->setmode = ata_via_family_setmode;
 5587     return 0;
 5588 }
 5589 
 5590 static int
 5591 ata_via_allocate(device_t dev)
 5592 {
 5593     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 5594     struct ata_channel *ch = device_get_softc(dev);
 5595 
 5596     /* newer SATA chips has resources in one BAR for each channel */
 5597     if (ctlr->chip->cfg2 & VIABAR) {
 5598         struct resource *r_io;
 5599         int i, rid;
 5600                 
 5601         rid = PCIR_BAR(ch->unit);
 5602         if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
 5603                                             SYS_RES_IOPORT,
 5604                                             &rid, RF_ACTIVE)))
 5605             return ENXIO;
 5606 
 5607         for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
 5608             ch->r_io[i].res = r_io;
 5609             ch->r_io[i].offset = i;
 5610         }
 5611         ch->r_io[ATA_CONTROL].res = r_io;
 5612         ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
 5613         ch->r_io[ATA_IDX_ADDR].res = r_io;
 5614         ata_default_registers(dev);
 5615         for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
 5616             ch->r_io[i].res = ctlr->r_res1;
 5617             ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
 5618         }
 5619         ata_pci_hw(dev);
 5620         if (ch->unit >= 2)
 5621             return 0;
 5622     }
 5623     else {
 5624         /* setup the usual register normal pci style */
 5625         if (ata_pci_allocate(dev))
 5626             return ENXIO;
 5627     }
 5628 
 5629     ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
 5630     ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
 5631     ch->r_io[ATA_SERROR].res = ctlr->r_res2;
 5632     ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
 5633     ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
 5634     ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
 5635     ch->flags |= ATA_NO_SLAVE;
 5636 
 5637     /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
 5638     /* XXX SOS unknown how to enable PHY state change interrupt */
 5639     return 0;
 5640 }
 5641 
 5642 static void
 5643 ata_via_reset(device_t dev)
 5644 {
 5645     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 5646     struct ata_channel *ch = device_get_softc(dev);
 5647 
 5648     if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
 5649         ata_generic_reset(dev);
 5650     else
 5651         if (ata_sata_phy_reset(dev))
 5652             ata_generic_reset(dev);
 5653 }
 5654 
 5655 static void
 5656 ata_via_setmode(device_t dev, int mode)
 5657 {
 5658     device_t gparent = GRANDPARENT(dev);
 5659     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 5660     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 5661     struct ata_device *atadev = device_get_softc(dev);
 5662     int error;
 5663 
 5664     if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
 5665         u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
 5666                                    0x65, 0x32, 0x20,
 5667                                    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
 5668         u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
 5669 
 5670         mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
 5671         error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 5672         if (bootverbose)
 5673             device_printf(dev, "%ssetting %s on %s chip\n",
 5674                           (error) ? "FAILURE " : "", ata_mode2str(mode),
 5675                           ctlr->chip->text);
 5676         if (!error) {
 5677             pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
 5678             if (mode >= ATA_UDMA0)
 5679                 pci_write_config(gparent, 0xb3,
 5680                                  dma_timings[mode & ATA_MODE_MASK], 1);
 5681             atadev->mode = mode;
 5682         }
 5683     }
 5684     else
 5685         ata_sata_setmode(dev, mode);
 5686 }
 5687 
 5688 static void
 5689 ata_via_southbridge_fixup(device_t dev)
 5690 {
 5691     device_t *children;
 5692     int nchildren, i;
 5693 
 5694     if (device_get_children(device_get_parent(dev), &children, &nchildren))
 5695         return;
 5696 
 5697     for (i = 0; i < nchildren; i++) {
 5698         if (pci_get_devid(children[i]) == ATA_VIA8363 ||
 5699             pci_get_devid(children[i]) == ATA_VIA8371 ||
 5700             pci_get_devid(children[i]) == ATA_VIA8662 ||
 5701             pci_get_devid(children[i]) == ATA_VIA8361) {
 5702             u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
 5703 
 5704             if ((reg76 & 0xf0) != 0xd0) {
 5705                 device_printf(dev,
 5706                 "Correcting VIA config for southbridge data corruption bug\n");
 5707                 pci_write_config(children[i], 0x75, 0x80, 1);
 5708                 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
 5709             }
 5710             break;
 5711         }
 5712     }
 5713     free(children, M_TEMP);
 5714 }
 5715 
 5716 
 5717 /* common code for VIA, AMD & nVidia */
 5718 static void
 5719 ata_via_family_setmode(device_t dev, int mode)
 5720 {
 5721     device_t gparent = GRANDPARENT(dev);
 5722     struct ata_pci_controller *ctlr = device_get_softc(gparent);
 5723     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 5724     struct ata_device *atadev = device_get_softc(dev);
 5725     u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
 5726                            0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
 5727     int modes[][7] = {
 5728         { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 },   /* VIA ATA33 */
 5729         { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 },   /* VIA ATA66 */
 5730         { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 },   /* VIA ATA100 */
 5731         { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 },   /* VIA ATA133 */
 5732         { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }};  /* AMD/nVIDIA */
 5733     int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
 5734     int reg = 0x53 - devno;
 5735     int error;
 5736 
 5737     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 5738 
 5739     if (ctlr->chip->cfg2 & AMDCABLE) {
 5740         if (mode > ATA_UDMA2 &&
 5741             !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
 5742             ata_print_cable(dev, "controller");
 5743             mode = ATA_UDMA2;
 5744         }
 5745     }
 5746     else 
 5747         mode = ata_check_80pin(dev, mode);
 5748 
 5749     if (ctlr->chip->cfg2 & NVIDIA)
 5750         reg += 0x10;
 5751 
 5752     if (ctlr->chip->cfg1 != VIA133)
 5753         pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
 5754 
 5755     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 5756 
 5757     if (bootverbose)
 5758         device_printf(dev, "%ssetting %s on %s chip\n",
 5759                       (error) ? "FAILURE " : "", ata_mode2str(mode),
 5760                       ctlr->chip->text);
 5761     if (!error) {
 5762         if (mode >= ATA_UDMA0)
 5763             pci_write_config(gparent, reg,
 5764                              modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
 5765         else
 5766             pci_write_config(gparent, reg, 0x8b, 1);
 5767         atadev->mode = mode;
 5768     }
 5769 }
 5770 
 5771 
 5772 /* misc functions */
 5773 static void
 5774 ata_set_desc(device_t dev)
 5775 {
 5776     struct ata_pci_controller *ctlr = device_get_softc(dev);
 5777     char buffer[128];
 5778 
 5779     sprintf(buffer, "%s %s %s controller",
 5780             ata_pcivendor2str(dev), ctlr->chip->text, 
 5781             ata_mode2str(ctlr->chip->max_dma));
 5782     device_set_desc_copy(dev, buffer);
 5783 }
 5784 
 5785 static struct ata_chip_id *
 5786 ata_match_chip(device_t dev, struct ata_chip_id *index)
 5787 {
 5788     while (index->chipid != 0) {
 5789         if (pci_get_devid(dev) == index->chipid &&
 5790             pci_get_revid(dev) >= index->chiprev)
 5791             return index;
 5792         index++;
 5793     }
 5794     return NULL;
 5795 }
 5796 
 5797 static struct ata_chip_id *
 5798 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
 5799 {
 5800     device_t *children;
 5801     int nchildren, i;
 5802 
 5803     if (device_get_children(device_get_parent(dev), &children, &nchildren))
 5804         return 0;
 5805 
 5806     while (index->chipid != 0) {
 5807         for (i = 0; i < nchildren; i++) {
 5808             if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 
 5809                  (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
 5810                 pci_get_devid(children[i]) == index->chipid &&
 5811                 pci_get_revid(children[i]) >= index->chiprev) {
 5812                 free(children, M_TEMP);
 5813                 return index;
 5814             }
 5815         }
 5816         index++;
 5817     }
 5818     free(children, M_TEMP);
 5819     return NULL;
 5820 }
 5821 
 5822 static int
 5823 ata_setup_interrupt(device_t dev)
 5824 {
 5825     struct ata_pci_controller *ctlr = device_get_softc(dev);
 5826     int rid = ATA_IRQ_RID;
 5827 
 5828     if (!ata_legacy(dev)) {
 5829         if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 5830                                                    RF_SHAREABLE | RF_ACTIVE))) {
 5831             device_printf(dev, "unable to map interrupt\n");
 5832             return ENXIO;
 5833         }
 5834         if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
 5835                             ata_generic_intr, ctlr, &ctlr->handle))) {
 5836             /* SOS XXX release r_irq */
 5837             device_printf(dev, "unable to setup interrupt\n");
 5838             return ENXIO;
 5839         }
 5840     }
 5841     return 0;
 5842 }
 5843 
 5844 struct ata_serialize {
 5845     struct mtx  locked_mtx;
 5846     int         locked_ch;
 5847     int         restart_ch;
 5848 };
 5849 
 5850 static int
 5851 ata_serialize(device_t dev, int flags)
 5852 {
 5853     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
 5854     struct ata_channel *ch = device_get_softc(dev);
 5855     struct ata_serialize *serial;
 5856     static int inited = 0;
 5857     int res;
 5858 
 5859     if (!inited) {
 5860         serial = malloc(sizeof(struct ata_serialize),
 5861                               M_TEMP, M_NOWAIT | M_ZERO);
 5862         mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF); 
 5863         serial->locked_ch = -1;
 5864         serial->restart_ch = -1;
 5865         device_set_ivars(ctlr->dev, serial);
 5866         inited = 1;
 5867     }
 5868     else
 5869         serial = device_get_ivars(ctlr->dev);
 5870 
 5871     mtx_lock(&serial->locked_mtx);
 5872     switch (flags) {
 5873     case ATA_LF_LOCK:
 5874         if (serial->locked_ch == -1)
 5875             serial->locked_ch = ch->unit;
 5876         if (serial->locked_ch != ch->unit)
 5877             serial->restart_ch = ch->unit;
 5878         break;
 5879 
 5880     case ATA_LF_UNLOCK:
 5881         if (serial->locked_ch == ch->unit) {
 5882             serial->locked_ch = -1;
 5883             if (serial->restart_ch != -1) {
 5884                 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
 5885                     serial->restart_ch = -1;
 5886                     mtx_unlock(&serial->locked_mtx);
 5887                     ata_start(ch->dev);
 5888                     return -1;
 5889                 }
 5890             }
 5891         }
 5892         break;
 5893 
 5894     case ATA_LF_WHICH:
 5895         break;
 5896     }
 5897     res = serial->locked_ch;
 5898     mtx_unlock(&serial->locked_mtx);
 5899     return res;
 5900 }
 5901 
 5902 static void
 5903 ata_print_cable(device_t dev, u_int8_t *who)
 5904 {
 5905     device_printf(dev,
 5906                   "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
 5907 }
 5908 
 5909 static int
 5910 ata_atapi(device_t dev)
 5911 {
 5912     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 5913     struct ata_device *atadev = device_get_softc(dev);
 5914 
 5915     return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
 5916             (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
 5917 }
 5918 
 5919 static int
 5920 ata_check_80pin(device_t dev, int mode)
 5921 {
 5922     struct ata_device *atadev = device_get_softc(dev);
 5923 
 5924     if (!ata_dma_check_80pin) {
 5925         if (bootverbose)
 5926             device_printf(dev, "Skipping 80pin cable check\n");
 5927         return mode;
 5928     }
 5929 
 5930     if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
 5931         ata_print_cable(dev, "device");
 5932         mode = ATA_UDMA2;
 5933     }
 5934     return mode;
 5935 }
 5936 
 5937 static int
 5938 ata_mode2idx(int mode)
 5939 {
 5940     if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
 5941          return (mode & ATA_MODE_MASK) + 8;
 5942     if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
 5943          return (mode & ATA_MODE_MASK) + 5;
 5944     return (mode & ATA_MODE_MASK) - ATA_PIO0;
 5945 }

Cache object: 57d12e9c7eacb0e657451a5e27d91c77


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