1 /*-
2 * Copyright (c) 1998 - 2003 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.28 2003/05/19 13:42:23 sos Exp $
29 */
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/ata.h>
36 #include <sys/bus.h>
37 #include <sys/malloc.h>
38 #include <machine/stdarg.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
41 #include <sys/rman.h>
42 #include <pci/pcivar.h>
43 #include <pci/pcireg.h>
44 #include <dev/ata/ata-all.h>
45 #include <dev/ata/ata-pci.h>
46
47 /* misc defines */
48 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
49 #define ATAPI_DEVICE(atadev) \
50 ((atadev->unit == ATA_MASTER && \
51 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
52 (atadev->unit == ATA_SLAVE && \
53 atadev->channel->devices & ATA_ATAPI_SLAVE))
54
55 /* local prototypes */
56 static int ata_generic_chipinit(device_t);
57 static void ata_generic_intr(void *);
58 static void ata_generic_setmode(struct ata_device *, int);
59 static int ata_acard_chipinit(device_t);
60 static void ata_acard_intr(void *);
61 static void ata_acard_850_setmode(struct ata_device *, int);
62 static void ata_acard_86X_setmode(struct ata_device *, int);
63 static int ata_ali_chipinit(device_t);
64 static void ata_ali_setmode(struct ata_device *, int);
65 static int ata_amd_chipinit(device_t);
66 static int ata_cyrix_chipinit(device_t);
67 static void ata_cyrix_setmode(struct ata_device *, int);
68 static int ata_cypress_chipinit(device_t);
69 static void ata_cypress_setmode(struct ata_device *, int);
70 static int ata_highpoint_chipinit(device_t);
71 static void ata_highpoint_intr(void *);
72 static void ata_highpoint_setmode(struct ata_device *, int);
73 static int ata_highpoint_check_80pin(struct ata_device *, int);
74 static int ata_intel_chipinit(device_t);
75 static void ata_intel_old_setmode(struct ata_device *, int);
76 static void ata_intel_new_setmode(struct ata_device *, int);
77 static int ata_nvidia_chipinit(device_t);
78 static int ata_via_chipinit(device_t);
79 static void ata_via_family_setmode(struct ata_device *, int);
80 static void ata_via_southbridge_fixup(device_t);
81 static int ata_promise_chipinit(device_t);
82 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
83 static void ata_promise_old_intr(void *);
84 static void ata_promise_tx2_intr(void *);
85 static void ata_promise_mio_intr(void *);
86 static void ata_promise_setmode(struct ata_device *, int);
87 static int ata_promise_old_dmainit(struct ata_channel *);
88 static int ata_promise_old_dmastart(struct ata_channel *, caddr_t, int32_t,int);
89 static int ata_promise_old_dmastop(struct ata_channel *);
90 static int ata_promise_mio_dmainit(struct ata_channel *);
91 static int ata_promise_mio_dmastart(struct ata_channel *, caddr_t, int32_t,int);
92 static int ata_promise_mio_dmastop(struct ata_channel *);
93 static int ata_serverworks_chipinit(device_t);
94 static void ata_serverworks_setmode(struct ata_device *, int);
95 static int ata_sii_chipinit(device_t);
96 static void ata_cmd_intr(void *);
97 static void ata_sii_setmode(struct ata_device *, int);
98 static void ata_cmd_setmode(struct ata_device *, int);
99 static int ata_sis_chipinit(device_t);
100 static void ata_sis_setmode(struct ata_device *, int);
101 static int ata_mode2idx(int);
102 static int ata_check_80pin(struct ata_device *, int);
103 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
104 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
105 static int ata_default_interrupt(device_t);
106 static void ata_pci_serialize(struct ata_channel *, int);
107
108 /* generic or unknown ATA chipset init code */
109 int
110 ata_generic_ident(device_t dev)
111 {
112 struct ata_pci_controller *ctlr = device_get_softc(dev);
113
114 device_set_desc(dev, "GENERIC ATA controller");
115 ctlr->chipinit = ata_generic_chipinit;
116 return 0;
117 }
118
119 static int
120 ata_generic_chipinit(device_t dev)
121 {
122 struct ata_pci_controller *ctlr = device_get_softc(dev);
123
124 if (ata_default_interrupt(dev))
125 return ENXIO;
126 ctlr->setmode = ata_generic_setmode;
127 return 0;
128 }
129
130 static void
131 ata_generic_intr(void *data)
132 {
133 struct ata_pci_controller *ctlr = data;
134 struct ata_channel *ch;
135 u_int8_t dmastat;
136 int unit;
137
138 /* implement this as a toggle instead to balance load XXX */
139 for (unit = 0; unit < 2; unit++) {
140 if (!(ch = ctlr->interrupt[unit].argument))
141 continue;
142 if (ch->dma->flags & ATA_DMA_ACTIVE) {
143 if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
144 ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
145 continue;
146 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
147 DELAY(1);
148 }
149 ctlr->interrupt[unit].function(ch);
150 }
151 }
152
153 static void
154 ata_generic_setmode(struct ata_device *atadev, int mode)
155 {
156 if (mode >= ATA_DMA)
157 atadev->mode = ATA_DMA;
158 else
159 atadev->mode = ATA_PIO;
160 return;
161 }
162
163 /*
164 * Acard chipset support functions
165 */
166 int
167 ata_acard_ident(device_t dev)
168 {
169 struct ata_pci_controller *ctlr = device_get_softc(dev);
170 struct ata_chip_id *idx;
171 static struct ata_chip_id ids[] =
172 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
173 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
174 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
175 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
176 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
177 { 0, 0, 0, 0, 0, 0}};
178 char buffer[64];
179
180 if (!(idx = ata_match_chip(dev, ids)))
181 return ENXIO;
182
183 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
184 device_set_desc_copy(dev, buffer);
185 ctlr->chip = idx;
186 ctlr->chipinit = ata_acard_chipinit;
187 return 0;
188 }
189
190 static int
191 ata_acard_chipinit(device_t dev)
192 {
193 struct ata_pci_controller *ctlr = device_get_softc(dev);
194 int rid = ATA_IRQ_RID;
195
196 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
197 RF_SHAREABLE | RF_ACTIVE))) {
198 device_printf(dev, "unable to map interrupt\n");
199 return ENXIO;
200 }
201 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
202 ata_acard_intr, ctlr, &ctlr->handle))) {
203 device_printf(dev, "unable to setup interrupt\n");
204 return ENXIO;
205 }
206 if (ctlr->chip->cfg1 == ATPOLD) {
207 ctlr->setmode = ata_acard_850_setmode;
208 ctlr->locking = ata_pci_serialize;
209 }
210 else
211 ctlr->setmode = ata_acard_86X_setmode;
212 return 0;
213 }
214
215 static void
216 ata_acard_intr(void *data)
217 {
218 struct ata_pci_controller *ctlr = data;
219 struct ata_channel *ch;
220 u_int8_t dmastat;
221 int unit;
222
223 /* implement this as a toggle instead to balance load XXX */
224 for (unit = 0; unit < 2; unit++) {
225 if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit)
226 continue;
227 ch = ctlr->interrupt[unit].argument;
228 if (ch->dma->flags & ATA_DMA_ACTIVE) {
229 if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
230 ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
231 continue;
232 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
233 DELAY(1);
234 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
235 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
236 DELAY(1);
237 }
238 ctlr->interrupt[unit].function(ch);
239 }
240 }
241
242 static void
243 ata_acard_850_setmode(struct ata_device *atadev, int mode)
244 {
245 device_t parent = device_get_parent(atadev->channel->dev);
246 struct ata_pci_controller *ctlr = device_get_softc(parent);
247 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
248 int error;
249
250 mode = ata_limit_mode(atadev, mode,
251 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
252
253 /* XXX missing WDMA0+1 + PIO modes */
254 if (mode >= ATA_WDMA2) {
255 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
256 mode, ATA_C_F_SETXFER, ATA_WAIT_READY);
257 if (bootverbose)
258 ata_prtdev(atadev, "%s setting %s on %s chip\n",
259 (error) ? "failed" : "success",
260 ata_mode2str(mode), ctlr->chip->text);
261 if (!error) {
262 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
263
264 reg54 &= ~(0x03 << (devno << 1));
265 if (mode >= ATA_UDMA0)
266 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
267 pci_write_config(parent, 0x54, reg54, 1);
268 pci_write_config(parent, 0x4a, 0xa6, 1);
269 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
270 atadev->mode = mode;
271 return;
272 }
273 }
274 /* we could set PIO mode timings, but we assume the BIOS did that */
275 }
276
277 static void
278 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
279 {
280 device_t parent = device_get_parent(atadev->channel->dev);
281 struct ata_pci_controller *ctlr = device_get_softc(parent);
282 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
283 int error;
284
285
286 mode = ata_limit_mode(atadev, mode,
287 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
288
289 mode = ata_check_80pin(atadev, mode);
290
291 /* XXX missing WDMA0+1 + PIO modes */
292 if (mode >= ATA_WDMA2) {
293 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
294 mode, ATA_C_F_SETXFER, ATA_WAIT_READY);
295 if (bootverbose)
296 ata_prtdev(atadev, "%s setting %s on %s chip\n",
297 (error) ? "failed" : "success",
298 ata_mode2str(mode), ctlr->chip->text);
299 if (!error) {
300 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
301
302 reg44 &= ~(0x000f << (devno << 2));
303 if (mode >= ATA_UDMA0)
304 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
305 pci_write_config(parent, 0x44, reg44, 2);
306 pci_write_config(parent, 0x4a, 0xa6, 1);
307 pci_write_config(parent, 0x40 + devno, 0x31, 1);
308 atadev->mode = mode;
309 return;
310 }
311 }
312 /* we could set PIO mode timings, but we assume the BIOS did that */
313 }
314
315 /*
316 * Acer Labs Inc (ALI) chipset support functions
317 */
318 int
319 ata_ali_ident(device_t dev)
320 {
321 struct ata_pci_controller *ctlr = device_get_softc(dev);
322 struct ata_chip_id *idx;
323 static struct ata_chip_id ids[] =
324 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
325 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
326 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
327 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
328 { 0, 0, 0, 0, 0, 0}};
329 char buffer[64];
330
331 if (!(idx = ata_match_chip(dev, ids)))
332 return ENXIO;
333
334 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
335 device_set_desc_copy(dev, buffer);
336 ctlr->chip = idx;
337 ctlr->chipinit = ata_ali_chipinit;
338 return 0;
339 }
340
341 static int
342 ata_ali_chipinit(device_t dev)
343 {
344 struct ata_pci_controller *ctlr = device_get_softc(dev);
345
346 if (ata_default_interrupt(dev))
347 return ENXIO;
348
349 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
350 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
351
352 /* enable cable detection and UDMA support on newer chips */
353 if (ctlr->chip->cfg2 & ALINEW)
354 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
355 ctlr->setmode = ata_ali_setmode;
356 return 0;
357 }
358
359 static void
360 ata_ali_setmode(struct ata_device *atadev, int mode)
361 {
362 device_t parent = device_get_parent(atadev->channel->dev);
363 struct ata_pci_controller *ctlr = device_get_softc(parent);
364 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
365 int error;
366
367 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
368
369 if (ctlr->chip->cfg2 & ALINEW) {
370 if (mode > ATA_UDMA2 &&
371 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
372 ata_prtdev(atadev,
373 "DMA limited to UDMA33, non-ATA66 cable or device\n");
374 mode = ATA_UDMA2;
375 }
376 }
377 else
378 mode = ata_check_80pin(atadev, mode);
379
380 if (ctlr->chip->cfg2 & ALIOLD) {
381 /* doesn't support ATAPI DMA on write */
382 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
383 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
384 atadev->channel->devices & ATA_ATAPI_SLAVE) {
385 /* doesn't support ATAPI DMA on two ATAPI devices */
386 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
387 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
388 }
389 }
390
391 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
392 ATA_C_F_SETXFER, ATA_WAIT_READY);
393 if (bootverbose)
394 ata_prtdev(atadev, "%s setting %s on %s chip\n",
395 (error) ? "failed" : "success",
396 ata_mode2str(mode), ctlr->chip->text);
397 if (!error) {
398 if (mode >= ATA_UDMA0) {
399 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
400 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
401
402 word54 &= ~(0x000f000f << (devno << 2));
403 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
404 pci_write_config(parent, 0x54, word54, 4);
405 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
406 0x00310001, 4);
407 }
408 else {
409 u_int32_t piotimings[] =
410 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
411 0x00310001, 0x00440001, 0x00330001, 0x00310001};
412
413 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
414 ~(0x0008000f << (devno << 2)), 4);
415 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
416 piotimings[ata_mode2idx(mode)], 4);
417 }
418 atadev->mode = mode;
419 }
420 }
421
422 /*
423 * American Micro Devices (AMD) support function
424 */
425 int
426 ata_amd_ident(device_t dev)
427 {
428 struct ata_pci_controller *ctlr = device_get_softc(dev);
429 struct ata_chip_id *idx;
430 static struct ata_chip_id ids[] =
431 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
432 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
433 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
434 { ATA_AMD8111, 0x00, AMDNVIDIA, 0x00, ATA_UDMA6, "AMD 8111" },
435 { 0, 0, 0, 0, 0, 0}};
436 char buffer[64];
437
438 if (!(idx = ata_match_chip(dev, ids)))
439 return ENXIO;
440
441 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
442 device_set_desc_copy(dev, buffer);
443 ctlr->chip = idx;
444 ctlr->chipinit = ata_amd_chipinit;
445 return 0;
446 }
447
448 static int
449 ata_amd_chipinit(device_t dev)
450 {
451 struct ata_pci_controller *ctlr = device_get_softc(dev);
452
453 if (ata_default_interrupt(dev))
454 return ENXIO;
455
456 /* set prefetch, postwrite */
457 if (ctlr->chip->cfg2 & AMDBUG)
458 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
459 else
460 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
461
462 ctlr->setmode = ata_via_family_setmode;
463 return 0;
464 }
465
466 /*
467 * Cyrix chipset support functions
468 */
469 int
470 ata_cyrix_ident(device_t dev)
471 {
472 struct ata_pci_controller *ctlr = device_get_softc(dev);
473
474 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
475 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
476 ctlr->chipinit = ata_cyrix_chipinit;
477 return 0;
478 }
479 return ENXIO;
480 }
481
482 static int
483 ata_cyrix_chipinit(device_t dev)
484 {
485 struct ata_pci_controller *ctlr = device_get_softc(dev);
486
487 if (ata_default_interrupt(dev))
488 return ENXIO;
489
490 if (ctlr->r_io1)
491 ctlr->setmode = ata_cyrix_setmode;
492 else
493 ctlr->setmode = ata_generic_setmode;
494 return 0;
495 }
496
497 static void
498 ata_cyrix_setmode(struct ata_device *atadev, int mode)
499 {
500 struct ata_channel *ch = atadev->channel;
501 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
502 u_int32_t piotiming[] =
503 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
504 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
505 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
506 int error;
507
508 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
509 atadev->channel->dma->alignment = 16;
510
511 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
512 ATA_C_F_SETXFER, ATA_WAIT_READY);
513 if (bootverbose)
514 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
515 (error) ? "failed" : "success", ata_mode2str(mode));
516 if (!error) {
517 if (mode >= ATA_UDMA0) {
518 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
519 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
520 }
521 else if (mode >= ATA_WDMA0) {
522 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
523 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
524 }
525 else {
526 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
527 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
528 }
529 atadev->mode = mode;
530 }
531 }
532
533 /*
534 * Cypress chipset support functions
535 */
536 int
537 ata_cypress_ident(device_t dev)
538 {
539 struct ata_pci_controller *ctlr = device_get_softc(dev);
540
541 /*
542 * the Cypress chip is a mess, it contains two ATA functions, but
543 * both channels are visible on the first one.
544 * simply ignore the second function for now, as the right
545 * solution (ignoring the second channel on the first function)
546 * doesn't work with the crappy ATA interrupt setup on the alpha.
547 */
548 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
549 pci_get_function(dev) == 1 &&
550 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
551 device_set_desc(dev, "Cypress 82C693 ATA controller");
552 ctlr->chipinit = ata_cypress_chipinit;
553 return 0;
554 }
555 return ENXIO;
556 }
557
558 static int
559 ata_cypress_chipinit(device_t dev)
560 {
561 struct ata_pci_controller *ctlr = device_get_softc(dev);
562
563 if (ata_default_interrupt(dev))
564 return ENXIO;
565
566 ctlr->setmode = ata_cypress_setmode;
567 return 0;
568 }
569
570 static void
571 ata_cypress_setmode(struct ata_device *atadev, int mode)
572 {
573 device_t parent = device_get_parent(atadev->channel->dev);
574 int error;
575
576 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
577
578 /* XXX missing WDMA0+1 + PIO modes */
579 if (mode == ATA_WDMA2) {
580 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
581 ATA_C_F_SETXFER, ATA_WAIT_READY);
582 if (bootverbose)
583 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
584 error ? "failed" : "success");
585 if (!error) {
586 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
587 atadev->mode = mode;
588 return;
589 }
590 }
591 /* we could set PIO mode timings, but we assume the BIOS did that */
592 }
593
594 /*
595 * HighPoint chipset support functions
596 */
597 int
598 ata_highpoint_ident(device_t dev)
599 {
600 struct ata_pci_controller *ctlr = device_get_softc(dev);
601 struct ata_chip_id *idx;
602 static struct ata_chip_id ids[] =
603 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
604 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
605 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
606 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
607 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
608 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
609 { 0, 0, 0, 0, 0, 0}};
610 char buffer[64];
611
612 if (!(idx = ata_match_chip(dev, ids)))
613 return ENXIO;
614
615 strcpy(buffer, idx->text);
616 if (idx->cfg1 == HPT374) {
617 if (pci_get_function(dev) == 0)
618 strcat(buffer, " (channel 0+1)");
619 else if (pci_get_function(dev) == 1)
620 strcat(buffer, " (channel 2+3)");
621 }
622 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
623 device_set_desc_copy(dev, buffer);
624 ctlr->chip = idx;
625 ctlr->chipinit = ata_highpoint_chipinit;
626 return 0;
627 }
628
629 static int
630 ata_highpoint_chipinit(device_t dev)
631 {
632 struct ata_pci_controller *ctlr = device_get_softc(dev);
633 int rid = ATA_IRQ_RID;
634
635 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
636 RF_SHAREABLE | RF_ACTIVE))) {
637 device_printf(dev, "unable to map interrupt\n");
638 return ENXIO;
639 }
640 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
641 ata_highpoint_intr, ctlr, &ctlr->handle))) {
642 device_printf(dev, "unable to setup interrupt\n");
643 return ENXIO;
644 }
645
646 if (ctlr->chip->cfg2 == HPTOLD) {
647 /* turn off interrupt prediction */
648 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
649 }
650 else {
651 /* turn off interrupt prediction */
652 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
653 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
654
655 /* turn on interrupts */
656 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
657
658 /* set clocks etc */
659 if (ctlr->chip->cfg1 < HPT372)
660 pci_write_config(dev, 0x5b, 0x22, 1);
661 else
662 pci_write_config(dev, 0x5b,
663 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
664 }
665 ctlr->setmode = ata_highpoint_setmode;
666 return 0;
667 }
668
669 static void
670 ata_highpoint_intr(void *data)
671 {
672 struct ata_pci_controller *ctlr = data;
673 struct ata_channel *ch;
674 u_int8_t dmastat;
675 int unit;
676
677 /* implement this as a toggle instead to balance load XXX */
678 for (unit = 0; unit < 2; unit++) {
679 if (!(ch = ctlr->interrupt[unit].argument))
680 continue;
681 if (((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) &
682 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT))!=ATA_BMSTAT_INTERRUPT)
683 continue;
684 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
685 DELAY(1);
686 ctlr->interrupt[unit].function(ch);
687 }
688 }
689
690 static void
691 ata_highpoint_setmode(struct ata_device *atadev, int mode)
692 {
693 device_t parent = device_get_parent(atadev->channel->dev);
694 struct ata_pci_controller *ctlr = device_get_softc(parent);
695 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
696 int error;
697 u_int32_t timings33[][4] = {
698 /* HPT366 HPT370 HPT372 HPT374 mode */
699 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
700 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
701 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
702 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
703 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
704 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
705 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
706 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
707 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
708 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
709 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
710 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
711 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
712 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
713 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
714 };
715
716 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
717
718 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
719 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
720
721 mode = ata_highpoint_check_80pin(atadev, mode);
722
723 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
724 ATA_C_F_SETXFER, ATA_WAIT_READY);
725 if (bootverbose)
726 ata_prtdev(atadev, "%s setting %s on HighPoint chip\n",
727 (error) ? "failed" : "success", ata_mode2str(mode));
728 if (!error)
729 pci_write_config(parent, 0x40 + (devno << 2),
730 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
731 atadev->mode = mode;
732 }
733
734 static int
735 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
736 {
737 device_t parent = device_get_parent(atadev->channel->dev);
738 struct ata_pci_controller *ctlr = device_get_softc(parent);
739 u_int8_t reg, val, res;
740
741 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
742 reg = atadev->channel->unit ? 0x57 : 0x53;
743 val = pci_read_config(parent, reg, 1);
744 pci_write_config(parent, reg, val | 0x80, 1);
745 }
746 else {
747 reg = 0x5b;
748 val = pci_read_config(parent, reg, 1);
749 pci_write_config(parent, reg, val & 0xfe, 1);
750 }
751 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
752 pci_write_config(parent, reg, val, 1);
753
754 if (mode > ATA_UDMA2 && res) {
755 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
756 mode = ATA_UDMA2;
757 }
758 return mode;
759 }
760
761 /*
762 * Intel chipset support functions
763 */
764 int
765 ata_intel_ident(device_t dev)
766 {
767 struct ata_pci_controller *ctlr = device_get_softc(dev);
768 struct ata_chip_id *idx;
769 static struct ata_chip_id ids[] =
770 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
771 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
772 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
773 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
774 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
775 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
776 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
777 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
778 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
779 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
780 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
781 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
782 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
783 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
784 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
785 { ATA_I82801EB_1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" },
786 { 0, 0, 0, 0, 0, 0}};
787 char buffer[64];
788
789 if (!(idx = ata_match_chip(dev, ids)))
790 return ENXIO;
791
792 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
793 device_set_desc_copy(dev, buffer);
794 ctlr->chip = idx;
795 ctlr->chipinit = ata_intel_chipinit;
796 return 0;
797 }
798
799 static int
800 ata_intel_chipinit(device_t dev)
801 {
802 struct ata_pci_controller *ctlr = device_get_softc(dev);
803
804 if (ata_default_interrupt(dev))
805 return ENXIO;
806
807 if (ctlr->chip->chipid == ATA_I82371FB)
808 ctlr->setmode = ata_intel_old_setmode;
809 else
810 ctlr->setmode = ata_intel_new_setmode;
811 return 0;
812 }
813
814 static void
815 ata_intel_old_setmode(struct ata_device *atadev, int mode)
816 {
817 /* NOT YET */
818 }
819
820 static void
821 ata_intel_new_setmode(struct ata_device *atadev, int mode)
822 {
823 device_t parent = device_get_parent(atadev->channel->dev);
824 struct ata_pci_controller *ctlr = device_get_softc(parent);
825 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
826 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
827 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
828 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
829 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
830 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
831 u_int32_t mask40 = 0, new40 = 0;
832 u_int8_t mask44 = 0, new44 = 0;
833 int error;
834 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
835 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
836
837 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
838
839 if (mode >= ATA_SA150) {
840 atadev->mode = mode;
841 return;
842 }
843
844 if (ctlr->chip->max_dma && mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
845 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
846 mode = ATA_UDMA2;
847 }
848
849 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
850 ATA_C_F_SETXFER, ATA_WAIT_READY);
851 if (bootverbose)
852 ata_prtdev(atadev, "%s setting %s on %s chip\n",
853 (error) ? "failed" : "success",
854 ata_mode2str(mode), ctlr->chip->text);
855 if (!error) {
856 if (mode >= ATA_UDMA0) {
857 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
858 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
859 (0x01 + !(mode & 0x01)), 2);
860 }
861 else {
862 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
863 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
864 }
865 if (mode >= ATA_UDMA2)
866 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
867 else
868 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
869
870 if (mode >= ATA_UDMA5)
871 pci_write_config(parent, 0x54, reg54 | (0x10000 << devno), 2);
872 else
873 pci_write_config(parent, 0x54, reg54 & ~(0x10000 << devno), 2);
874
875 reg40 &= ~0x00ff00ff;
876 reg40 |= 0x40774077;
877
878 if (atadev->unit == ATA_MASTER) {
879 mask40 = 0x3300;
880 new40 = timings[ata_mode2idx(mode)] << 8;
881 }
882 else {
883 mask44 = 0x0f;
884 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
885 (timings[ata_mode2idx(mode)] & 0x03);
886 }
887 if (atadev->channel->unit) {
888 mask40 <<= 16;
889 new40 <<= 16;
890 mask44 <<= 4;
891 new44 <<= 4;
892 }
893 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
894 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
895 atadev->mode = mode;
896 }
897 }
898
899 /*
900 * nVidia chipset support functions
901 */
902 int
903 ata_nvidia_ident(device_t dev)
904 {
905 struct ata_pci_controller *ctlr = device_get_softc(dev);
906 struct ata_chip_id *idx;
907 static struct ata_chip_id ids[] =
908 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA5, "nVidia nForce" },
909 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA6, "nVidia nForce2" },
910 { 0, 0, 0, 0, 0, 0}};
911 char buffer[64];
912
913 if (!(idx = ata_match_chip(dev, ids)))
914 return ENXIO;
915
916 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
917 device_set_desc_copy(dev, buffer);
918 ctlr->chip = idx;
919 ctlr->chipinit = ata_nvidia_chipinit;
920 return 0;
921 }
922
923 static int
924 ata_nvidia_chipinit(device_t dev)
925 {
926 struct ata_pci_controller *ctlr = device_get_softc(dev);
927
928 if (ata_default_interrupt(dev))
929 return ENXIO;
930
931 /* set prefetch, postwrite */
932 if (ctlr->chip->cfg2 & AMDBUG)
933 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
934 else
935 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) | 0xf0, 1);
936
937 ctlr->setmode = ata_via_family_setmode;
938 return 0;
939 }
940
941 /*
942 * Promise chipset support functions
943 */
944 int
945 ata_promise_ident(device_t dev)
946 {
947 struct ata_pci_controller *ctlr = device_get_softc(dev);
948 struct ata_chip_id *idx;
949 static struct ata_chip_id ids[] =
950 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
951 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
952 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
953 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
954 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
955 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
956 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
957 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
958 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
959 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
960 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
961 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
962 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
963 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
964 { ATA_PDC20371, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20371" },
965 { ATA_PDC20375, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20375" },
966 { ATA_PDC20376, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20376" },
967 { ATA_PDC20377, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20377" },
968 { ATA_PDC20378, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20378" },
969 { ATA_PDC20379, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20379" },
970 { ATA_PDC20617, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20617" },
971 { ATA_PDC20618, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20618" },
972 { ATA_PDC20619, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20619" },
973 { ATA_PDC20620, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20620" },
974 { 0, 0, 0, 0, 0, 0}};
975 char buffer[64];
976 uintptr_t devid = 0;
977
978 if (!(idx = ata_match_chip(dev, ids)))
979 return ENXIO;
980
981 /* if we are on a SuperTrak SX6000 dont attach */
982 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
983 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
984 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
985 devid == ATA_I960RM)
986 return ENXIO;
987
988 strcpy(buffer, idx->text);
989 /* if we are on a FastTrak TX4, adjust the interrupt resource */
990 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
991 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
992 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
993 devid == ATA_DEC_21150) {
994 static long start = 0, end = 0;
995
996 if (pci_get_slot(dev) == 1) {
997 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
998 strcat(buffer, " (channel 0+1)");
999 }
1000 else if (pci_get_slot(dev) == 2 && start && end) {
1001 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1002 start = end = 0;
1003 strcat(buffer, " (channel 2+3)");
1004 }
1005 else {
1006 start = end = 0;
1007 }
1008 }
1009 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1010 device_set_desc_copy(dev, buffer);
1011 ctlr->chip = idx;
1012 ctlr->chipinit = ata_promise_chipinit;
1013 return 0;
1014 }
1015
1016 static int
1017 ata_promise_chipinit(device_t dev)
1018 {
1019 struct ata_pci_controller *ctlr = device_get_softc(dev);
1020 int rid = ATA_IRQ_RID;
1021
1022 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1023 RF_SHAREABLE | RF_ACTIVE))) {
1024 device_printf(dev, "unable to map interrupt\n");
1025 return ENXIO;
1026 }
1027
1028 switch (ctlr->chip->cfg1) {
1029 case PRNEW:
1030 ctlr->dmainit = ata_promise_old_dmainit;
1031 /* FALLTHROUGH */
1032
1033 case PROLD:
1034 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
1035 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1036 device_printf(dev, "unable to setup interrupt\n");
1037 return ENXIO;
1038 }
1039 break;
1040
1041 case PRTX:
1042 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
1043 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1044 device_printf(dev, "unable to setup interrupt\n");
1045 return ENXIO;
1046 }
1047 break;
1048
1049 case PRMIO:
1050 rid = 0x1c;
1051 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1052 0, ~0, 1, RF_ACTIVE)))
1053 return ENXIO;
1054
1055 ctlr->dmainit = ata_promise_mio_dmainit;
1056 ctlr->allocate = ata_promise_mio_allocate;
1057
1058 if (ctlr->chip->cfg2 & PRDUAL) {
1059 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x01) > 0) +
1060 ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 2;
1061 }
1062 else if (ctlr->chip->cfg2 & PRSATA) {
1063 ATA_OUTL(ctlr->r_io2, 0x06c, 0x00ff0033);
1064 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 3;
1065 }
1066 else
1067 ctlr->channels = 4;
1068
1069 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
1070 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1071 device_printf(dev, "unable to setup interrupt\n");
1072 return ENXIO;
1073 }
1074 break;
1075 }
1076 ctlr->setmode = ata_promise_setmode;
1077 return 0;
1078 }
1079
1080 static int
1081 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1082 {
1083 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1084 int i;
1085
1086 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1087 ch->r_io[i].res = ctlr->r_io2;
1088 ch->r_io[i].offset = 0x200 + (i << 2) + (ch->unit << 7);
1089 }
1090 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1091 ch->r_io[ATA_ALTSTAT].offset = 0x238 + (ch->unit << 7);
1092 ch->r_io[ATA_BMCTL_PORT].res = ctlr->r_io2;
1093 ch->r_io[ATA_BMCTL_PORT].offset = 0x260 + (ch->unit << 7);
1094 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1095 ch->r_io[ATA_BMDTP_PORT].offset = 0x244 + (ch->unit << 7);
1096 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1097 ch->r_io[ATA_BMDEVSPEC_0].offset = (ch->unit << 2);
1098 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1099
1100 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1101 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00000f8f) | ch->unit);
1102 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1103
1104 ch->flags |= ATA_NO_SLAVE;
1105 ctlr->dmainit(ch);
1106 return 0;
1107 }
1108
1109 static void
1110 ata_promise_old_intr(void *data)
1111 {
1112 struct ata_pci_controller *ctlr = data;
1113 struct ata_channel *ch;
1114 u_int8_t dmastat;
1115 int unit;
1116
1117 /* implement this as a toggle instead to balance load XXX */
1118 for (unit = 0; unit < 2; unit++) {
1119 if (!(ch = ctlr->interrupt[unit].argument))
1120 continue;
1121 if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
1122 if (ch->dma->flags & ATA_DMA_ACTIVE) {
1123 if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
1124 ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
1125 continue;
1126 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
1127 DELAY(1);
1128 }
1129 ctlr->interrupt[unit].function(ch);
1130 }
1131 }
1132 }
1133
1134 static void
1135 ata_promise_tx2_intr(void *data)
1136 {
1137 struct ata_pci_controller *ctlr = data;
1138 struct ata_channel *ch;
1139 u_int8_t dmastat;
1140 int unit;
1141
1142 /* implement this as a toggle instead to balance load XXX */
1143 for (unit = 0; unit < 2; unit++) {
1144 if (!(ch = ctlr->interrupt[unit].argument))
1145 continue;
1146 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1147 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1148 if (ch->dma->flags & ATA_DMA_ACTIVE) {
1149 if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
1150 ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
1151 continue;
1152 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
1153 DELAY(1);
1154 }
1155 ctlr->interrupt[unit].function(ch);
1156 }
1157 }
1158 }
1159
1160 static void
1161 ata_promise_mio_intr(void *data)
1162 {
1163 struct ata_pci_controller *ctlr = data;
1164 struct ata_channel *ch;
1165 u_int32_t irq_vector;
1166 int unit;
1167
1168 irq_vector = ATA_INL(ctlr->r_io2, 0x0040);
1169 for (unit = 0; unit < ctlr->channels; unit++) {
1170 if (irq_vector & (1 << unit)) {
1171 if ((ch = ctlr->interrupt[unit].argument)) {
1172 ctlr->interrupt[unit].function(ch);
1173 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1174 }
1175 }
1176 }
1177 }
1178
1179 static void
1180 ata_promise_setmode(struct ata_device *atadev, int mode)
1181 {
1182 device_t parent = device_get_parent(atadev->channel->dev);
1183 struct ata_pci_controller *ctlr = device_get_softc(parent);
1184 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1185 int error;
1186 u_int32_t timings33[][2] = {
1187 /* PROLD PRNEW mode */
1188 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
1189 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
1190 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
1191 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
1192 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
1193 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
1194 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
1195 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
1196 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
1197 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
1198 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
1199 { 0, 0x00424ef6 }, /* UDMA 3 */
1200 { 0, 0x004127f3 }, /* UDMA 4 */
1201 { 0, 0x004127f3 } /* UDMA 5 */
1202 };
1203
1204 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1205
1206 switch (ctlr->chip->cfg1) {
1207 case PROLD:
1208 case PRNEW:
1209 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
1210 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
1211 ata_prtdev(atadev,
1212 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1213 mode = ATA_UDMA2;
1214 }
1215 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
1216 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
1217 break;
1218
1219 case PRTX:
1220 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
1221 if (mode > ATA_UDMA2 &&
1222 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
1223 ata_prtdev(atadev,
1224 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1225 mode = ATA_UDMA2;
1226 }
1227 break;
1228
1229 case PRMIO:
1230 if (mode > ATA_UDMA2 &&
1231 (ATA_IDX_INL(atadev->channel, ATA_BMCTL_PORT) & 0x01000000)) {
1232 ata_prtdev(atadev,
1233 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1234 mode = ATA_UDMA2;
1235 }
1236 break;
1237 }
1238
1239 if (mode >= ATA_SA150) {
1240 atadev->mode = mode;
1241 return;
1242 }
1243
1244 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
1245 ATA_C_F_SETXFER, ATA_WAIT_READY);
1246 if (bootverbose)
1247 ata_prtdev(atadev, "%s setting %s on %s chip\n",
1248 (error) ? "failed" : "success",
1249 ata_mode2str(mode), ctlr->chip->text);
1250 if (!error) {
1251 if (ctlr->chip->cfg1 < PRTX)
1252 pci_write_config(device_get_parent(atadev->channel->dev),
1253 0x60 + (devno << 2),
1254 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
1255 atadev->mode = mode;
1256 }
1257 return;
1258 }
1259
1260 static int
1261 ata_promise_old_dmainit(struct ata_channel *ch)
1262 {
1263 int error;
1264
1265 if ((error = ata_dmainit(ch)))
1266 return error;
1267
1268 ch->dma->start = ata_promise_old_dmastart;
1269 ch->dma->stop = ata_promise_old_dmastop;
1270 return 0;
1271 }
1272
1273 static int
1274 ata_promise_old_dmastart(struct ata_channel *ch,
1275 caddr_t data, int32_t count, int dir)
1276 {
1277 struct ata_pci_controller *ctlr =
1278 device_get_softc(device_get_parent(ch->dev));
1279 int error;
1280
1281 if ((error = ata_dmastart(ch, data, count, dir)))
1282 return error;
1283 if (ch->flags & ATA_48BIT_ACTIVE) {
1284 ATA_OUTB(ctlr->r_io1, 0x11,
1285 ATA_INB(ctlr->r_io1, 0x11) | (ch->unit ? 0x08 : 0x02));
1286 ATA_OUTL(ctlr->r_io1, 0x20,
1287 (dir ? 0x05000000 : 0x06000000) | (count >> 1));
1288 }
1289 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1290 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1291 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1292 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1293 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1294 ATA_IDX_INB(ch, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1295 return error;
1296 }
1297
1298 static int
1299 ata_promise_old_dmastop(struct ata_channel *ch)
1300 {
1301 struct ata_pci_controller *ctlr =
1302 device_get_softc(device_get_parent(ch->dev));
1303 int error;
1304
1305 if (ch->flags & ATA_48BIT_ACTIVE) {
1306 ATA_OUTB(ctlr->r_io1, 0x11,
1307 ATA_INB(ctlr->r_io1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
1308 ATA_OUTL(ctlr->r_io1, 0x20, 0);
1309 }
1310 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
1311 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1312 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1313 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1314 ata_dmastop(ch);
1315 return error;
1316 }
1317
1318 static int
1319 ata_promise_mio_dmainit(struct ata_channel *ch)
1320 {
1321 int error;
1322
1323 if ((error = ata_dmainit(ch)))
1324 return error;
1325
1326 ch->dma->start = ata_promise_mio_dmastart;
1327 ch->dma->stop = ata_promise_mio_dmastop;
1328 return 0;
1329 }
1330
1331 static int
1332 ata_promise_mio_dmastart(struct ata_channel *ch,
1333 caddr_t data, int32_t count, int dir)
1334 {
1335 int error;
1336
1337 if ((error = ata_dmastart(ch, data, count, dir)))
1338 return error;
1339
1340 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1341 ATA_IDX_OUTL(ch, ATA_BMCTL_PORT,
1342 (ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x000000c0) |
1343 ((dir) ? 0x00000080 : 0x000000c0));
1344 return error;
1345 }
1346
1347 static int
1348 ata_promise_mio_dmastop(struct ata_channel *ch)
1349 {
1350 ATA_IDX_OUTL(ch, ATA_BMCTL_PORT,
1351 ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x00000080);
1352 return ata_dmastop(ch);
1353 }
1354
1355 /*
1356 * ServerWorks chipset support functions
1357 */
1358 int
1359 ata_serverworks_ident(device_t dev)
1360 {
1361 struct ata_pci_controller *ctlr = device_get_softc(dev);
1362 struct ata_chip_id *idx;
1363 static struct ata_chip_id ids[] =
1364 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
1365 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
1366 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
1367 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
1368 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
1369 { 0, 0, 0, 0, 0, 0}};
1370 char buffer[64];
1371
1372 if (!(idx = ata_match_chip(dev, ids)))
1373 return ENXIO;
1374
1375 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1376 device_set_desc_copy(dev, buffer);
1377 ctlr->chip = idx;
1378 ctlr->chipinit = ata_serverworks_chipinit;
1379 return 0;
1380 }
1381
1382 static int
1383 ata_serverworks_chipinit(device_t dev)
1384 {
1385 struct ata_pci_controller *ctlr = device_get_softc(dev);
1386
1387 if (ata_default_interrupt(dev))
1388 return ENXIO;
1389
1390 if (ctlr->chip->cfg1 > SWKS33)
1391 pci_write_config(dev, 0x5a,
1392 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
1393 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
1394 else
1395 pci_write_config(dev, 0x64,
1396 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
1397 0x00004000, 4);
1398 ctlr->setmode = ata_serverworks_setmode;
1399 return 0;
1400 }
1401
1402 static void
1403 ata_serverworks_setmode(struct ata_device *atadev, int mode)
1404 {
1405 device_t parent = device_get_parent(atadev->channel->dev);
1406 struct ata_pci_controller *ctlr = device_get_softc(parent);
1407 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1408 int offset = devno ^ 0x01;
1409 int error;
1410 u_int8_t timings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1411 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1412
1413 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1414
1415 mode = ata_check_80pin(atadev, mode);
1416
1417 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
1418 ATA_C_F_SETXFER, ATA_WAIT_READY);
1419 if (bootverbose)
1420 ata_prtdev(atadev, "%s setting %s on %s chip\n",
1421 (error) ? "failed" : "success",
1422 ata_mode2str(mode), ctlr->chip->text);
1423 if (!error) {
1424 if (mode >= ATA_UDMA0) {
1425 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) |
1426 (0x01 << devno), 1);
1427 pci_write_config(parent, 0x56,
1428 (pci_read_config(parent, 0x56, 2) &
1429 ~(0xf << (devno << 2))) |
1430 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1431 }
1432 else
1433 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) |
1434 ~(0x01 << devno), 1);
1435 pci_write_config(parent, 0x44,
1436 (pci_read_config(parent, 0x44, 4) &
1437 ~(0xff << (offset << 8))) |
1438 (timings[ata_mode2idx(mode)] << (offset << 8)), 4);
1439 atadev->mode = mode;
1440 }
1441 }
1442
1443 /*
1444 * Silicon Image (former CMD) chipset support functions
1445 */
1446 int
1447 ata_sii_ident(device_t dev)
1448 {
1449 struct ata_pci_controller *ctlr = device_get_softc(dev);
1450 struct ata_chip_id *idx;
1451 static struct ata_chip_id ids[] =
1452 {{ ATA_SII0680, 0x00, 0, SII_SETCLK, ATA_UDMA6, "SiI 0680" },
1453 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "CMD 649" },
1454 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "CMD 648" },
1455 { ATA_CMD646, 0x07, 0, SII_ENINTR, ATA_UDMA2, "CMD 646U2" },
1456 { ATA_CMD646, 0x00, 0, SII_ENINTR, ATA_WDMA2, "CMD 646" },
1457 { 0, 0, 0, 0, 0, 0}};
1458 char buffer[64];
1459
1460 if (!(idx = ata_match_chip(dev, ids)))
1461 return ENXIO;
1462
1463 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1464 device_set_desc_copy(dev, buffer);
1465 ctlr->chip = idx;
1466 ctlr->chipinit = ata_sii_chipinit;
1467 return 0;
1468 }
1469
1470 static int
1471 ata_sii_chipinit(device_t dev)
1472 {
1473 struct ata_pci_controller *ctlr = device_get_softc(dev);
1474 int rid = ATA_IRQ_RID;
1475
1476 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1477 RF_SHAREABLE | RF_ACTIVE))) {
1478 device_printf(dev, "unable to map interrupt\n");
1479 return ENXIO;
1480 }
1481 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
1482 ctlr->chip->cfg2 & SII_INTR ?
1483 ata_cmd_intr : ata_generic_intr,
1484 ctlr, &ctlr->handle))) {
1485 device_printf(dev, "unable to setup interrupt\n");
1486 return ENXIO;
1487 }
1488
1489 if (ctlr->chip->cfg2 & SII_ENINTR)
1490 pci_write_config(dev, 0x71, 0x01, 1);
1491
1492 if (ctlr->chip->cfg2 & SII_SETCLK) {
1493 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1494 pci_write_config(dev, 0x8a,
1495 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
1496 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1497 device_printf(dev, "%s could not set ATA133 clock\n",
1498 ctlr->chip->text);
1499 ctlr->setmode = ata_sii_setmode;
1500 }
1501 else
1502 ctlr->setmode = ata_cmd_setmode;
1503 return 0;
1504 }
1505
1506 static void
1507 ata_cmd_intr(void *data)
1508 {
1509 struct ata_pci_controller *ctlr = data;
1510 struct ata_channel *ch;
1511 u_int8_t dmastat;
1512 int unit;
1513
1514 /* implement this as a toggle instead to balance load XXX */
1515 for (unit = 0; unit < 2; unit++) {
1516 if (!(ch = ctlr->interrupt[unit].argument))
1517 continue;
1518 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
1519 (ch->unit ? 0x08 : 0x04)))
1520 continue;
1521 pci_write_config(device_get_parent(ch->dev), 0x71,
1522 (ch->unit ? 0x08 : 0x04), 1);
1523 if (ch->dma->flags & ATA_DMA_ACTIVE) {
1524 if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
1525 ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
1526 continue;
1527 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
1528 DELAY(1);
1529 }
1530 ctlr->interrupt[unit].function(ch);
1531 }
1532 }
1533
1534 static void
1535 ata_sii_setmode(struct ata_device *atadev, int mode)
1536 {
1537 device_t parent = device_get_parent(atadev->channel->dev);
1538 struct ata_pci_controller *ctlr = device_get_softc(parent);
1539 int devno = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
1540 int mreg = atadev->channel->unit ? 0x84 : 0x80;
1541 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
1542 int mval = pci_read_config(parent, mreg, 1) & ~mask;
1543 int error;
1544
1545 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1546
1547 mode = ata_check_80pin(atadev, mode);
1548
1549 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
1550 ATA_C_F_SETXFER, ATA_WAIT_READY);
1551 if (bootverbose)
1552 ata_prtdev(atadev, "%s setting %s on %s chip\n",
1553 (error) ? "failed" : "success",
1554 ata_mode2str(mode), ctlr->chip->text);
1555 if (!error) {
1556 if (mode >= ATA_UDMA0) {
1557 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1558 u_int8_t ureg = 0xac + devno;
1559
1560 pci_write_config(parent, mreg,
1561 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
1562 pci_write_config(parent, ureg,
1563 (pci_read_config(parent, ureg, 1) & 0x3f) |
1564 udmatimings[mode & ATA_MODE_MASK], 1);
1565
1566 }
1567 else if (mode >= ATA_WDMA0) {
1568 u_int8_t dreg = 0xa8 + devno;
1569 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
1570
1571 pci_write_config(parent, mreg,
1572 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
1573 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
1574
1575 }
1576 else {
1577 u_int8_t preg = 0xa4 + devno;
1578 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
1579
1580 pci_write_config(parent, mreg,
1581 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
1582 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
1583 }
1584 atadev->mode = mode;
1585 }
1586 }
1587
1588 static void
1589 ata_cmd_setmode(struct ata_device *atadev, int mode)
1590 {
1591 device_t parent = device_get_parent(atadev->channel->dev);
1592 struct ata_pci_controller *ctlr = device_get_softc(parent);
1593 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1594 int error;
1595
1596 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1597
1598 mode = ata_check_80pin(atadev, mode);
1599
1600 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
1601 ATA_C_F_SETXFER, ATA_WAIT_READY);
1602 if (bootverbose)
1603 ata_prtdev(atadev, "%s setting %s on %s chip\n",
1604 (error) ? "failed" : "success",
1605 ata_mode2str(mode), ctlr->chip->text);
1606 if (!error) {
1607 int treg = 0x54 + (devno < 3) ? (devno << 1) : 7;
1608 int ureg = atadev->channel->unit ? 0x7b : 0x73;
1609
1610 if (mode >= ATA_UDMA0) {
1611 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
1612 { 0x11, 0x42 }, { 0x25, 0x8a },
1613 { 0x15, 0x4a }, { 0x05, 0x0a } };
1614
1615 u_int8_t umode = pci_read_config(parent, ureg, 1);
1616
1617 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
1618 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
1619 pci_write_config(parent, ureg, umode, 1);
1620 }
1621 else if (mode >= ATA_WDMA0) {
1622 int dmatimings[] = { 0x87, 0x32, 0x3f };
1623
1624 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
1625 pci_write_config(parent, ureg,
1626 pci_read_config(parent, ureg, 1) &
1627 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1628 }
1629 else {
1630 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1631 pci_write_config(parent, treg,
1632 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
1633 pci_write_config(parent, ureg,
1634 pci_read_config(parent, ureg, 1) &
1635 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1636 }
1637 atadev->mode = mode;
1638 }
1639 }
1640
1641 /*
1642 * SiS chipset support functions
1643 */
1644 int
1645 ata_sis_ident(device_t dev)
1646 {
1647 struct ata_pci_controller *ctlr = device_get_softc(dev);
1648 struct ata_chip_id *idx;
1649 static struct ata_chip_id ids[] =
1650 {{ ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
1651 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
1652
1653 { ATA_SIS755, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 755" }, /* ext south */
1654 { ATA_SIS752, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 752" }, /* unknown */
1655 { ATA_SIS751, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 751" }, /* unknown */
1656 { ATA_SIS750, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 750" }, /* unknown */
1657 { ATA_SIS748, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 748" }, /* unknown */
1658 { ATA_SIS746, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 746" }, /* ext south */
1659 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
1660 { ATA_SIS740, 0x00, SIS_SOUTH, 0, ATA_UDMA5, "SiS 740" }, /* ext south */
1661 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
1662 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
1663 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
1664
1665 { ATA_SIS658, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 658" }, /* ext south */
1666 { ATA_SIS655, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 655" }, /* ext south */
1667 { ATA_SIS652, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 652" }, /* unknown */
1668 { ATA_SIS651, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 651" }, /* ext south */
1669 { ATA_SIS650, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 650" }, /* ext south */
1670 { ATA_SIS648, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 648" }, /* ext south */
1671 { ATA_SIS646, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645DX"},/* ext south */
1672 { ATA_SIS645, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645" }, /* ext south */
1673 { ATA_SIS640, 0x00, SIS_SOUTH, 0, ATA_UDMA4, "SiS 640" }, /* ext south */
1674 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
1675 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
1676 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
1677 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
1678 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
1679
1680 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
1681 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
1682 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
1683
1684 { ATA_SIS5513, 0xc2, SIS33, 0, ATA_UDMA2, "SiS 5513" },
1685 { ATA_SIS5513, 0x00, SIS33, 0, ATA_WDMA2, "SiS 5513" },
1686 { 0, 0, 0, 0, 0, 0 }};
1687 char buffer[64];
1688
1689 if (!(idx = ata_find_chip(dev, ids, -1)))
1690 return ENXIO;
1691
1692 if (idx->cfg1 == SIS_SOUTH) {
1693 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) & 0x7f, 1);
1694 if (pci_read_config(dev, 0x00, 4) == ATA_SIS5518) {
1695 idx->cfg1 = SIS133NEW;
1696 sprintf(buffer, "SiS 96X %s controller",ata_mode2str(idx->max_dma));
1697 }
1698 else {
1699 struct ata_chip_id id[] =
1700 {{ ATA_SISSOUTH, 0x10, 0, 0, ATA_UDMA6, "SiS 961" },
1701 { 0, 0, 0, 0, 0, 0 }};
1702
1703 if (ata_find_chip(dev, id, pci_get_slot(dev)))
1704 idx->cfg1 = SIS133OLD;
1705 else {
1706 idx->max_dma = ATA_UDMA5;
1707 idx->cfg1 = SIS100NEW;
1708 }
1709 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
1710 }
1711 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) | 0x80, 1);
1712 }
1713 else
1714 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
1715 device_set_desc_copy(dev, buffer);
1716 ctlr->chip = idx;
1717 ctlr->chipinit = ata_sis_chipinit;
1718 return 0;
1719 }
1720
1721 static int
1722 ata_sis_chipinit(device_t dev)
1723 {
1724 struct ata_pci_controller *ctlr = device_get_softc(dev);
1725
1726 if (ata_default_interrupt(dev))
1727 return ENXIO;
1728
1729 switch (ctlr->chip->cfg1) {
1730 case SIS33:
1731 break;
1732 case SIS66:
1733 case SIS100OLD:
1734 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) | 0x04, 1);
1735 break;
1736 case SIS100NEW:
1737 case SIS133OLD:
1738 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) | 0x01, 1);
1739 break;
1740 case SIS133NEW:
1741 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) & 0xfff7, 2);
1742 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) & 0xfff7, 2);
1743 break;
1744 default:
1745 return ENXIO;
1746 }
1747 ctlr->setmode = ata_sis_setmode;
1748 return 0;
1749 }
1750
1751 static void
1752 ata_sis_setmode(struct ata_device *atadev, int mode)
1753 {
1754 device_t parent = device_get_parent(atadev->channel->dev);
1755 struct ata_pci_controller *ctlr = device_get_softc(parent);
1756 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1757 int error;
1758
1759 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1760
1761 if (ctlr->chip->cfg1 == SIS133NEW) {
1762 if (mode > ATA_UDMA2 &&
1763 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
1764 ata_prtdev(atadev,
1765 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1766 mode = ATA_UDMA2;
1767 }
1768 }
1769 else {
1770 if (mode > ATA_UDMA2 &&
1771 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
1772 ata_prtdev(atadev,
1773 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1774 mode = ATA_UDMA2;
1775 }
1776 }
1777
1778 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
1779 ATA_C_F_SETXFER, ATA_WAIT_READY);
1780 if (bootverbose)
1781 ata_prtdev(atadev, "%s setting %s on %s chip\n",
1782 (error) ? "failed" : "success",
1783 ata_mode2str(mode), ctlr->chip->text);
1784 if (!error) {
1785 switch (ctlr->chip->cfg1) {
1786 case SIS133NEW: {
1787 u_int32_t timings[] =
1788 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1789 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1790 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1791 u_int32_t reg;
1792
1793 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
1794 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
1795 break;
1796 }
1797 case SIS133OLD: {
1798 u_int16_t timings[] =
1799 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1800 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1801
1802 u_int16_t reg = 0x40 + (devno << 1);
1803
1804 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
1805 break;
1806 }
1807 case SIS100NEW: {
1808 u_int16_t timings[] =
1809 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
1810 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
1811 u_int16_t reg = 0x40 + (devno << 1);
1812
1813 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
1814 break;
1815 }
1816 case SIS100OLD:
1817 case SIS66:
1818 case SIS33: {
1819 u_int16_t timings[] =
1820 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
1821 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1822 u_int16_t reg = 0x40 + (devno << 1);
1823
1824 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
1825 break;
1826 }
1827 }
1828 atadev->mode = mode;
1829 }
1830 }
1831
1832 /* VIA chipsets */
1833 int
1834 ata_via_ident(device_t dev)
1835 {
1836 struct ata_pci_controller *ctlr = device_get_softc(dev);
1837 struct ata_chip_id *idx;
1838 static struct ata_chip_id ids[] =
1839 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
1840 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
1841 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
1842 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
1843 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
1844 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
1845 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
1846 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
1847 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
1848 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
1849 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
1850 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
1851 { 0, 0, 0, 0, 0, 0 }};
1852 char buffer[64];
1853
1854 if (!(idx = ata_find_chip(dev, ids, pci_get_slot(dev))))
1855 return ENXIO;
1856
1857 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1858 device_set_desc_copy(dev, buffer);
1859 ctlr->chip = idx;
1860 ctlr->chipinit = ata_via_chipinit;
1861 return 0;
1862 }
1863
1864 static int
1865 ata_via_chipinit(device_t dev)
1866 {
1867 struct ata_pci_controller *ctlr = device_get_softc(dev);
1868
1869 if (ata_default_interrupt(dev))
1870 return ENXIO;
1871
1872 /* prepare for ATA-66 on the 82C686a and 82C596b */
1873 if (ctlr->chip->cfg2 & VIACLK)
1874 pci_write_config(dev, 0x50, 0x030b030b, 4);
1875
1876 /* the southbridge might need the data corruption fix */
1877 if (ctlr->chip->cfg2 & VIABUG)
1878 ata_via_southbridge_fixup(dev);
1879
1880 /* set prefetch, postwrite */
1881 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1882
1883 /* set fifo configuration half'n'half */
1884 pci_write_config(dev, 0x43,
1885 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
1886
1887 /* set status register read retry */
1888 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
1889
1890 /* set DMA read & end-of-sector fifo flush */
1891 pci_write_config(dev, 0x46,
1892 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
1893
1894 /* set sector size */
1895 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
1896 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
1897
1898 ctlr->setmode = ata_via_family_setmode;
1899 return 0;
1900 }
1901
1902 static void
1903 ata_via_southbridge_fixup(device_t dev)
1904 {
1905 device_t *children;
1906 int nchildren, i;
1907
1908 if (device_get_children(device_get_parent(dev), &children, &nchildren))
1909 return;
1910
1911 for (i = 0; i < nchildren; i++) {
1912 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
1913 pci_get_devid(children[i]) == ATA_VIA8371 ||
1914 pci_get_devid(children[i]) == ATA_VIA8662 ||
1915 pci_get_devid(children[i]) == ATA_VIA8361) {
1916 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
1917
1918 if ((reg76 & 0xf0) != 0xd0) {
1919 device_printf(dev,
1920 "Correcting VIA config for southbridge data corruption bug\n");
1921 pci_write_config(children[i], 0x75, 0x80, 1);
1922 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
1923 }
1924 break;
1925 }
1926 }
1927 free(children, M_TEMP);
1928 }
1929
1930 /* common code for VIA, AMD & nVidia */
1931 static void
1932 ata_via_family_setmode(struct ata_device *atadev, int mode)
1933 {
1934 device_t parent = device_get_parent(atadev->channel->dev);
1935 struct ata_pci_controller *ctlr = device_get_softc(parent);
1936 u_int8_t timings[] = { 0xff, 0xff, 0xff, 0x55, 0x51, 0xff, 0x55, 0x51,
1937 0x51, 0x51, 0x51, 0x51, 0x51, 0x51 };
1938 int modes[][7] = {
1939 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
1940 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
1941 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
1942 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
1943 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
1944 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1945 int reg = 0x53 - devno;
1946 int error;
1947
1948 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1949
1950 if (ctlr->chip->cfg2 & AMDCABLE) {
1951 if (mode > ATA_UDMA2 && !pci_read_config(parent, 0x42, 1) & (1<<devno)){
1952 ata_prtdev(atadev,
1953 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1954 mode = ATA_UDMA2;
1955 }
1956 }
1957 else
1958 mode = ata_check_80pin(atadev, mode);
1959
1960 if (ctlr->chip->cfg2 & NVIDIA)
1961 reg += 0x10;
1962
1963 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
1964
1965 error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
1966 ATA_C_F_SETXFER, ATA_WAIT_READY);
1967 if (bootverbose)
1968 ata_prtdev(atadev, "%s setting %s on %s chip\n",
1969 (error) ? "failed" : "success", ata_mode2str(mode),
1970 ctlr->chip->text);
1971 if (!error) {
1972 if (mode >= ATA_UDMA0)
1973 pci_write_config(parent, reg,
1974 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
1975 else
1976 pci_write_config(parent, reg, 0x8b, 1);
1977 atadev->mode = mode;
1978 }
1979 }
1980
1981 /* misc functions */
1982 static int
1983 ata_mode2idx(int mode)
1984 {
1985 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
1986 return (mode & ATA_MODE_MASK) + 8;
1987 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
1988 return (mode & ATA_MODE_MASK) + 5;
1989 return (mode & ATA_MODE_MASK) - ATA_PIO0;
1990 }
1991
1992 static int
1993 ata_check_80pin(struct ata_device *atadev, int mode)
1994 {
1995 if (mode > ATA_UDMA2 && !atadev->param->hwres_cblid) {
1996 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
1997 mode = ATA_UDMA2;
1998 }
1999 return mode;
2000 }
2001
2002 static struct ata_chip_id *
2003 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2004 {
2005 device_t *children;
2006 int nchildren, i;
2007
2008 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2009 return 0;
2010
2011 while (index->chipid != 0) {
2012 for (i = 0; i < nchildren; i++) {
2013 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || slot < 0)&&
2014 pci_get_devid(children[i]) == index->chipid &&
2015 pci_get_revid(children[i]) >= index->chiprev) {
2016 free(children, M_TEMP);
2017 return index;
2018 }
2019 }
2020 index++;
2021 }
2022 free(children, M_TEMP);
2023 return NULL;
2024 }
2025
2026 static struct ata_chip_id *
2027 ata_match_chip(device_t dev, struct ata_chip_id *index)
2028 {
2029 while (index->chipid != 0) {
2030 if (pci_get_devid(dev) == index->chipid &&
2031 pci_get_revid(dev) >= index->chiprev)
2032 return index;
2033 index++;
2034 }
2035 return NULL;
2036 }
2037
2038 static int
2039 ata_default_interrupt(device_t dev)
2040 {
2041 struct ata_pci_controller *ctlr = device_get_softc(dev);
2042 int rid = ATA_IRQ_RID;
2043
2044 if (!ATA_MASTERDEV(dev)) {
2045 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2046 RF_SHAREABLE | RF_ACTIVE))) {
2047 device_printf(dev, "unable to map interrupt\n");
2048 return ENXIO;
2049 }
2050 if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
2051 ata_generic_intr, ctlr, &ctlr->handle))) {
2052 device_printf(dev, "unable to setup interrupt\n");
2053 return ENXIO;
2054 }
2055 }
2056 return 0;
2057 }
2058
2059 static void
2060 ata_pci_serialize(struct ata_channel *ch, int flags)
2061 {
2062 struct ata_pci_controller *scp =
2063 device_get_softc(device_get_parent(ch->dev));
2064
2065 switch (flags) {
2066 case ATA_LF_LOCK:
2067 if (scp->locked_ch == ch->unit)
2068 break;
2069 while (!atomic_cmpset_acq_int(&scp->locked_ch, -1, ch->unit))
2070 tsleep(ch->locking, PRIBIO, "atasrl", 1);
2071 break;
2072
2073 case ATA_LF_UNLOCK:
2074 if (scp->locked_ch == -1 || scp->locked_ch != ch->unit)
2075 break;
2076 atomic_store_rel_int(&scp->locked_ch, -1);
2077 wakeup(ch->locking);
2078 break;
2079 }
2080 return;
2081 }
Cache object: fd0c4ace83440d7a440463f4eb023f92
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