1 /*-
2 * Copyright (c) 1998 - 2004 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.48.2.3 2004/02/11 08:47:21 scottl Exp $");
31
32 #include "opt_ata.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/ata.h>
38 #include <sys/bus.h>
39 #include <sys/malloc.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51
52 /* misc defines */
53 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
54 #define ATAPI_DEVICE(atadev) \
55 ((atadev->unit == ATA_MASTER && \
56 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
57 (atadev->unit == ATA_SLAVE && \
58 atadev->channel->devices & ATA_ATAPI_SLAVE))
59
60 /* local prototypes */
61 static int ata_generic_chipinit(device_t);
62 static void ata_generic_intr(void *);
63 static void ata_generic_setmode(struct ata_device *, int);
64 static int ata_acard_chipinit(device_t);
65 static void ata_acard_intr(void *);
66 static void ata_acard_850_setmode(struct ata_device *, int);
67 static void ata_acard_86X_setmode(struct ata_device *, int);
68 static int ata_ali_chipinit(device_t);
69 static void ata_ali_setmode(struct ata_device *, int);
70 static int ata_amd_chipinit(device_t);
71 static int ata_cyrix_chipinit(device_t);
72 static void ata_cyrix_setmode(struct ata_device *, int);
73 static int ata_cypress_chipinit(device_t);
74 static void ata_cypress_setmode(struct ata_device *, int);
75 static int ata_highpoint_chipinit(device_t);
76 static void ata_highpoint_intr(void *);
77 static void ata_highpoint_setmode(struct ata_device *, int);
78 static int ata_highpoint_check_80pin(struct ata_device *, int);
79 static int ata_intel_chipinit(device_t);
80 static void ata_intel_old_setmode(struct ata_device *, int);
81 static void ata_intel_new_setmode(struct ata_device *, int);
82 static int ata_national_chipinit(device_t);
83 static void ata_national_setmode(struct ata_device *, int);
84 static int ata_nvidia_chipinit(device_t);
85 static int ata_via_chipinit(device_t);
86 static void ata_via_family_setmode(struct ata_device *, int);
87 static void ata_via_southbridge_fixup(device_t);
88 static int ata_promise_chipinit(device_t);
89 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
90 static void ata_promise_old_intr(void *);
91 static void ata_promise_tx2_intr(void *);
92 static void ata_promise_mio_intr(void *);
93 static void ata_promise_setmode(struct ata_device *, int);
94 static void ata_promise_new_dmainit(struct ata_channel *);
95 static int ata_promise_new_dmastart(struct ata_channel *);
96 static int ata_promise_new_dmastop(struct ata_channel *);
97 static void ata_promise_mio_dmainit(struct ata_channel *);
98 static int ata_promise_mio_dmastart(struct ata_channel *);
99 static int ata_promise_mio_dmastop(struct ata_channel *);
100 static int ata_serverworks_chipinit(device_t);
101 static void ata_serverworks_setmode(struct ata_device *, int);
102 static int ata_sii_chipinit(device_t);
103 static int ata_sii_mio_allocate(device_t, struct ata_channel *);
104 static void ata_sii_reset(struct ata_channel *);
105 static void ata_sii_intr(void *);
106 static void ata_cmd_intr(void *);
107 static void ata_cmd_old_intr(void *);
108 static void ata_sii_setmode(struct ata_device *, int);
109 static void ata_cmd_setmode(struct ata_device *, int);
110 static int ata_sis_chipinit(device_t);
111 static void ata_sis_setmode(struct ata_device *, int);
112 static int ata_check_80pin(struct ata_device *, int);
113 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
114 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
115 static int ata_setup_interrupt(device_t);
116 static void ata_serialize(struct ata_channel *, int);
117 static int ata_mode2idx(int);
118
119 /* generic or unknown ATA chipset init code */
120 int
121 ata_generic_ident(device_t dev)
122 {
123 struct ata_pci_controller *ctlr = device_get_softc(dev);
124
125 device_set_desc(dev, "GENERIC ATA controller");
126 ctlr->chipinit = ata_generic_chipinit;
127 return 0;
128 }
129
130 static int
131 ata_generic_chipinit(device_t dev)
132 {
133 struct ata_pci_controller *ctlr = device_get_softc(dev);
134
135 if (ata_setup_interrupt(dev))
136 return ENXIO;
137 ctlr->setmode = ata_generic_setmode;
138 return 0;
139 }
140
141 static void
142 ata_generic_intr(void *data)
143 {
144 struct ata_pci_controller *ctlr = data;
145 struct ata_channel *ch;
146 int unit;
147
148 /* implement this as a toggle instead to balance load XXX */
149 for (unit = 0; unit < 2; unit++) {
150 if (!(ch = ctlr->interrupt[unit].argument))
151 continue;
152 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
153 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
154
155 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
156 ATA_BMSTAT_INTERRUPT)
157 continue;
158 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
159 DELAY(1);
160 }
161 ctlr->interrupt[unit].function(ch);
162 }
163 }
164
165 static void
166 ata_generic_setmode(struct ata_device *atadev, int mode)
167 {
168 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
169 mode = ata_check_80pin(atadev, mode);
170 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
171 atadev->mode = mode;
172 }
173
174 static void
175 ata_sata_setmode(struct ata_device *atadev, int mode)
176 {
177 /*
178 * we limit the transfer mode to UDMA5/ATA100 as some chips/drive
179 * comboes that use the Marvell SATA->PATA converters has trouble
180 * with UDMA6/ATA133. This doesn't really matter as real SATA
181 * devices doesn't use this anyway.
182 */
183 mode = ata_limit_mode(atadev, mode, ATA_UDMA5);
184 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
185 atadev->mode = mode;
186 }
187
188 /*
189 * Acard chipset support functions
190 */
191 int
192 ata_acard_ident(device_t dev)
193 {
194 struct ata_pci_controller *ctlr = device_get_softc(dev);
195 struct ata_chip_id *idx;
196 static struct ata_chip_id ids[] =
197 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
198 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
199 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
200 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
201 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
202 { 0, 0, 0, 0, 0, 0}};
203 char buffer[64];
204
205 if (!(idx = ata_match_chip(dev, ids)))
206 return ENXIO;
207
208 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
209 device_set_desc_copy(dev, buffer);
210 ctlr->chip = idx;
211 ctlr->chipinit = ata_acard_chipinit;
212 return 0;
213 }
214
215 static int
216 ata_acard_chipinit(device_t dev)
217 {
218 struct ata_pci_controller *ctlr = device_get_softc(dev);
219 int rid = ATA_IRQ_RID;
220
221 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
222 RF_SHAREABLE | RF_ACTIVE))) {
223 device_printf(dev, "unable to map interrupt\n");
224 return ENXIO;
225 }
226 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
227 ata_acard_intr, ctlr, &ctlr->handle))) {
228 device_printf(dev, "unable to setup interrupt\n");
229 return ENXIO;
230 }
231 if (ctlr->chip->cfg1 == ATPOLD) {
232 ctlr->setmode = ata_acard_850_setmode;
233 ctlr->locking = ata_serialize;
234 }
235 else
236 ctlr->setmode = ata_acard_86X_setmode;
237 return 0;
238 }
239
240 static void
241 ata_acard_intr(void *data)
242 {
243 struct ata_pci_controller *ctlr = data;
244 struct ata_channel *ch;
245 int unit;
246
247 /* implement this as a toggle instead to balance load XXX */
248 for (unit = 0; unit < 2; unit++) {
249 if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit)
250 continue;
251 if (!(ch = ctlr->interrupt[unit].argument))
252 continue;
253 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
254 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
255
256 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
257 ATA_BMSTAT_INTERRUPT)
258 continue;
259 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
260 DELAY(1);
261 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
262 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
263 DELAY(1);
264 }
265 ctlr->interrupt[unit].function(ch);
266 }
267 }
268
269 static void
270 ata_acard_850_setmode(struct ata_device *atadev, int mode)
271 {
272 device_t parent = device_get_parent(atadev->channel->dev);
273 struct ata_pci_controller *ctlr = device_get_softc(parent);
274 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
275 int error;
276
277 mode = ata_limit_mode(atadev, mode,
278 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
279
280 /* XXX missing WDMA0+1 + PIO modes */
281 if (mode >= ATA_WDMA2) {
282 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
283 if (bootverbose)
284 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
285 (error) ? "FAILURE " : "",
286 ata_mode2str(mode), ctlr->chip->text);
287 if (!error) {
288 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
289
290 reg54 &= ~(0x03 << (devno << 1));
291 if (mode >= ATA_UDMA0)
292 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
293 pci_write_config(parent, 0x54, reg54, 1);
294 pci_write_config(parent, 0x4a, 0xa6, 1);
295 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
296 atadev->mode = mode;
297 return;
298 }
299 }
300 /* we could set PIO mode timings, but we assume the BIOS did that */
301 }
302
303 static void
304 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
305 {
306 device_t parent = device_get_parent(atadev->channel->dev);
307 struct ata_pci_controller *ctlr = device_get_softc(parent);
308 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
309 int error;
310
311
312 mode = ata_limit_mode(atadev, mode,
313 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
314
315 mode = ata_check_80pin(atadev, mode);
316
317 /* XXX missing WDMA0+1 + PIO modes */
318 if (mode >= ATA_WDMA2) {
319 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
320 if (bootverbose)
321 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
322 (error) ? "FAILURE " : "",
323 ata_mode2str(mode), ctlr->chip->text);
324 if (!error) {
325 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
326
327 reg44 &= ~(0x000f << (devno << 2));
328 if (mode >= ATA_UDMA0)
329 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
330 pci_write_config(parent, 0x44, reg44, 2);
331 pci_write_config(parent, 0x4a, 0xa6, 1);
332 pci_write_config(parent, 0x40 + devno, 0x31, 1);
333 atadev->mode = mode;
334 return;
335 }
336 }
337 /* we could set PIO mode timings, but we assume the BIOS did that */
338 }
339
340 /*
341 * Acer Labs Inc (ALI) chipset support functions
342 */
343 int
344 ata_ali_ident(device_t dev)
345 {
346 struct ata_pci_controller *ctlr = device_get_softc(dev);
347 struct ata_chip_id *idx;
348 static struct ata_chip_id ids[] =
349 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
350 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
351 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
352 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
353 { 0, 0, 0, 0, 0, 0}};
354 char buffer[64];
355
356 if (!(idx = ata_match_chip(dev, ids)))
357 return ENXIO;
358
359 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
360 device_set_desc_copy(dev, buffer);
361 ctlr->chip = idx;
362 ctlr->chipinit = ata_ali_chipinit;
363 return 0;
364 }
365
366 static int
367 ata_ali_chipinit(device_t dev)
368 {
369 struct ata_pci_controller *ctlr = device_get_softc(dev);
370
371 if (ata_setup_interrupt(dev))
372 return ENXIO;
373
374 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
375 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
376
377 /* enable cable detection and UDMA support on newer chips */
378 if (ctlr->chip->cfg2 & ALINEW)
379 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
380 ctlr->setmode = ata_ali_setmode;
381 return 0;
382 }
383
384 static void
385 ata_ali_setmode(struct ata_device *atadev, int mode)
386 {
387 device_t parent = device_get_parent(atadev->channel->dev);
388 struct ata_pci_controller *ctlr = device_get_softc(parent);
389 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
390 int error;
391
392 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
393
394 if (ctlr->chip->cfg2 & ALINEW) {
395 if (mode > ATA_UDMA2 &&
396 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
397 ata_prtdev(atadev,
398 "DMA limited to UDMA33, non-ATA66 cable or device\n");
399 mode = ATA_UDMA2;
400 }
401 }
402 else
403 mode = ata_check_80pin(atadev, mode);
404
405 if (ctlr->chip->cfg2 & ALIOLD) {
406 /* doesn't support ATAPI DMA on write */
407 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
408 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
409 atadev->channel->devices & ATA_ATAPI_SLAVE) {
410 /* doesn't support ATAPI DMA on two ATAPI devices */
411 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
412 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
413 }
414 }
415
416 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
417
418 if (bootverbose)
419 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
420 (error) ? "FAILURE " : "",
421 ata_mode2str(mode), ctlr->chip->text);
422 if (!error) {
423 if (mode >= ATA_UDMA0) {
424 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
425 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
426
427 word54 &= ~(0x000f000f << (devno << 2));
428 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
429 pci_write_config(parent, 0x54, word54, 4);
430 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
431 0x00310001, 4);
432 }
433 else {
434 u_int32_t piotimings[] =
435 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
436 0x00310001, 0x00440001, 0x00330001, 0x00310001};
437
438 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
439 ~(0x0008000f << (devno << 2)), 4);
440 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
441 piotimings[ata_mode2idx(mode)], 4);
442 }
443 atadev->mode = mode;
444 }
445 }
446
447 /*
448 * American Micro Devices (AMD) support functions
449 */
450 int
451 ata_amd_ident(device_t dev)
452 {
453 struct ata_pci_controller *ctlr = device_get_softc(dev);
454 struct ata_chip_id *idx;
455 static struct ata_chip_id ids[] =
456 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
457 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
458 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
459 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
460 { 0, 0, 0, 0, 0, 0}};
461 char buffer[64];
462
463 if (!(idx = ata_match_chip(dev, ids)))
464 return ENXIO;
465
466 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
467 device_set_desc_copy(dev, buffer);
468 ctlr->chip = idx;
469 ctlr->chipinit = ata_amd_chipinit;
470 return 0;
471 }
472
473 static int
474 ata_amd_chipinit(device_t dev)
475 {
476 struct ata_pci_controller *ctlr = device_get_softc(dev);
477
478 if (ata_setup_interrupt(dev))
479 return ENXIO;
480
481 /* set prefetch, postwrite */
482 if (ctlr->chip->cfg2 & AMDBUG)
483 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
484 else
485 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
486
487 ctlr->setmode = ata_via_family_setmode;
488 return 0;
489 }
490
491 /*
492 * Cyrix chipset support functions
493 */
494 int
495 ata_cyrix_ident(device_t dev)
496 {
497 struct ata_pci_controller *ctlr = device_get_softc(dev);
498
499 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
500 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
501 ctlr->chipinit = ata_cyrix_chipinit;
502 return 0;
503 }
504 return ENXIO;
505 }
506
507 static int
508 ata_cyrix_chipinit(device_t dev)
509 {
510 struct ata_pci_controller *ctlr = device_get_softc(dev);
511
512 if (ata_setup_interrupt(dev))
513 return ENXIO;
514
515 if (ctlr->r_io1)
516 ctlr->setmode = ata_cyrix_setmode;
517 else
518 ctlr->setmode = ata_generic_setmode;
519 return 0;
520 }
521
522 static void
523 ata_cyrix_setmode(struct ata_device *atadev, int mode)
524 {
525 struct ata_channel *ch = atadev->channel;
526 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
527 u_int32_t piotiming[] =
528 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
529 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
530 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
531 int error;
532
533 atadev->channel->dma->alignment = 16;
534 atadev->channel->dma->max_iosize = 63 * 1024;
535
536 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
537
538 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
539
540 if (bootverbose)
541 ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n",
542 (error) ? "FAILURE " : "", ata_mode2str(mode));
543 if (!error) {
544 if (mode >= ATA_UDMA0) {
545 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
546 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
547 }
548 else if (mode >= ATA_WDMA0) {
549 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
550 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
551 }
552 else {
553 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
554 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
555 }
556 atadev->mode = mode;
557 }
558 }
559
560 /*
561 * Cypress chipset support functions
562 */
563 int
564 ata_cypress_ident(device_t dev)
565 {
566 struct ata_pci_controller *ctlr = device_get_softc(dev);
567
568 /*
569 * the Cypress chip is a mess, it contains two ATA functions, but
570 * both channels are visible on the first one.
571 * simply ignore the second function for now, as the right
572 * solution (ignoring the second channel on the first function)
573 * doesn't work with the crappy ATA interrupt setup on the alpha.
574 */
575 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
576 pci_get_function(dev) == 1 &&
577 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
578 device_set_desc(dev, "Cypress 82C693 ATA controller");
579 ctlr->chipinit = ata_cypress_chipinit;
580 return 0;
581 }
582 return ENXIO;
583 }
584
585 static int
586 ata_cypress_chipinit(device_t dev)
587 {
588 struct ata_pci_controller *ctlr = device_get_softc(dev);
589
590 if (ata_setup_interrupt(dev))
591 return ENXIO;
592
593 ctlr->setmode = ata_cypress_setmode;
594 return 0;
595 }
596
597 static void
598 ata_cypress_setmode(struct ata_device *atadev, int mode)
599 {
600 device_t parent = device_get_parent(atadev->channel->dev);
601 int error;
602
603 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
604
605 /* XXX missing WDMA0+1 + PIO modes */
606 if (mode == ATA_WDMA2) {
607 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
608 if (bootverbose)
609 ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n",
610 error ? "FAILURE " : "");
611 if (!error) {
612 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
613 atadev->mode = mode;
614 return;
615 }
616 }
617 /* we could set PIO mode timings, but we assume the BIOS did that */
618 }
619
620 /*
621 * HighPoint chipset support functions
622 */
623 int
624 ata_highpoint_ident(device_t dev)
625 {
626 struct ata_pci_controller *ctlr = device_get_softc(dev);
627 struct ata_chip_id *idx;
628 static struct ata_chip_id ids[] =
629 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
630 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
631 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
632 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
633 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
634 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
635 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
636 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
637 { 0, 0, 0, 0, 0, 0}};
638 char buffer[64];
639
640 if (!(idx = ata_match_chip(dev, ids)))
641 return ENXIO;
642
643 strcpy(buffer, idx->text);
644 if (idx->cfg1 == HPT374) {
645 if (pci_get_function(dev) == 0)
646 strcat(buffer, " (channel 0+1)");
647 else if (pci_get_function(dev) == 1)
648 strcat(buffer, " (channel 2+3)");
649 }
650 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
651 device_set_desc_copy(dev, buffer);
652 ctlr->chip = idx;
653 ctlr->chipinit = ata_highpoint_chipinit;
654 return 0;
655 }
656
657 static int
658 ata_highpoint_chipinit(device_t dev)
659 {
660 struct ata_pci_controller *ctlr = device_get_softc(dev);
661 int rid = ATA_IRQ_RID;
662
663 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
664 RF_SHAREABLE | RF_ACTIVE))) {
665 device_printf(dev, "unable to map interrupt\n");
666 return ENXIO;
667 }
668 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
669 ata_highpoint_intr, ctlr, &ctlr->handle))) {
670 device_printf(dev, "unable to setup interrupt\n");
671 return ENXIO;
672 }
673
674 if (ctlr->chip->cfg2 == HPTOLD) {
675 /* turn off interrupt prediction */
676 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
677 }
678 else {
679 /* turn off interrupt prediction */
680 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
681 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
682
683 /* turn on interrupts */
684 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
685
686 /* set clocks etc */
687 if (ctlr->chip->cfg1 < HPT372)
688 pci_write_config(dev, 0x5b, 0x22, 1);
689 else
690 pci_write_config(dev, 0x5b,
691 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
692 }
693 ctlr->setmode = ata_highpoint_setmode;
694 return 0;
695 }
696
697 static void
698 ata_highpoint_intr(void *data)
699 {
700 struct ata_pci_controller *ctlr = data;
701 struct ata_channel *ch;
702 int unit;
703
704 /* implement this as a toggle instead to balance load XXX */
705 for (unit = 0; unit < 2; unit++) {
706 if (!(ch = ctlr->interrupt[unit].argument))
707 continue;
708 if (ch->dma) {
709 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
710
711 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
712 ATA_BMSTAT_INTERRUPT)
713 continue;
714 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
715 DELAY(1);
716 }
717 ctlr->interrupt[unit].function(ch);
718 }
719 }
720
721 static void
722 ata_highpoint_setmode(struct ata_device *atadev, int mode)
723 {
724 device_t parent = device_get_parent(atadev->channel->dev);
725 struct ata_pci_controller *ctlr = device_get_softc(parent);
726 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
727 int error;
728 u_int32_t timings33[][4] = {
729 /* HPT366 HPT370 HPT372 HPT374 mode */
730 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
731 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
732 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
733 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
734 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
735 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
736 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
737 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
738 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
739 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
740 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
741 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
742 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
743 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
744 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
745 };
746
747 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
748
749 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
750 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
751
752 mode = ata_highpoint_check_80pin(atadev, mode);
753
754 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
755
756 if (bootverbose)
757 ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n",
758 (error) ? "FAILURE " : "", ata_mode2str(mode));
759 if (!error)
760 pci_write_config(parent, 0x40 + (devno << 2),
761 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
762 atadev->mode = mode;
763 }
764
765 static int
766 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
767 {
768 device_t parent = device_get_parent(atadev->channel->dev);
769 struct ata_pci_controller *ctlr = device_get_softc(parent);
770 u_int8_t reg, val, res;
771
772 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
773 reg = atadev->channel->unit ? 0x57 : 0x53;
774 val = pci_read_config(parent, reg, 1);
775 pci_write_config(parent, reg, val | 0x80, 1);
776 }
777 else {
778 reg = 0x5b;
779 val = pci_read_config(parent, reg, 1);
780 pci_write_config(parent, reg, val & 0xfe, 1);
781 }
782 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
783 pci_write_config(parent, reg, val, 1);
784
785 if (mode > ATA_UDMA2 && res) {
786 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
787 mode = ATA_UDMA2;
788 }
789 return mode;
790 }
791
792 /*
793 * Intel chipset support functions
794 */
795 int
796 ata_intel_ident(device_t dev)
797 {
798 struct ata_pci_controller *ctlr = device_get_softc(dev);
799 struct ata_chip_id *idx;
800 static struct ata_chip_id ids[] =
801 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
802 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
803 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
804 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
805 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
806 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
807 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
808 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
809 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
810 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
811 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
812 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
813 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
814 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
815 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
816 { ATA_I82801EB_1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" },
817 { 0, 0, 0, 0, 0, 0}};
818 char buffer[64];
819
820 if (!(idx = ata_match_chip(dev, ids)))
821 return ENXIO;
822
823 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
824 device_set_desc_copy(dev, buffer);
825 ctlr->chip = idx;
826 ctlr->chipinit = ata_intel_chipinit;
827 return 0;
828 }
829
830 static int
831 ata_intel_chipinit(device_t dev)
832 {
833 struct ata_pci_controller *ctlr = device_get_softc(dev);
834
835 if (ata_setup_interrupt(dev))
836 return ENXIO;
837
838 if (ctlr->chip->chipid == ATA_I82371FB)
839 ctlr->setmode = ata_intel_old_setmode;
840 else if (ctlr->chip->max_dma < ATA_SA150)
841 ctlr->setmode = ata_intel_new_setmode;
842 else
843 ctlr->setmode = ata_sata_setmode;
844 return 0;
845 }
846
847 static void
848 ata_intel_old_setmode(struct ata_device *atadev, int mode)
849 {
850 /* NOT YET */
851 }
852
853 static void
854 ata_intel_new_setmode(struct ata_device *atadev, int mode)
855 {
856 device_t parent = device_get_parent(atadev->channel->dev);
857 struct ata_pci_controller *ctlr = device_get_softc(parent);
858 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
859 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
860 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
861 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
862 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
863 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
864 u_int32_t mask40 = 0, new40 = 0;
865 u_int8_t mask44 = 0, new44 = 0;
866 int error;
867 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
868 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
869
870 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
871
872 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
873 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
874 mode = ATA_UDMA2;
875 }
876
877 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
878
879 if (bootverbose)
880 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
881 (error) ? "FAILURE " : "",
882 ata_mode2str(mode), ctlr->chip->text);
883 if (error)
884 return;
885
886 if (mode >= ATA_UDMA0) {
887 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
888 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
889 (0x01 + !(mode & 0x01)), 2);
890 }
891 else {
892 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
893 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
894 }
895 if (mode >= ATA_UDMA2)
896 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
897 else
898 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
899
900 if (mode >= ATA_UDMA5)
901 pci_write_config(parent, 0x54, reg54 | (0x10000 << devno), 2);
902 else
903 pci_write_config(parent, 0x54, reg54 & ~(0x10000 << devno), 2);
904
905 reg40 &= ~0x00ff00ff;
906 reg40 |= 0x40774077;
907
908 if (atadev->unit == ATA_MASTER) {
909 mask40 = 0x3300;
910 new40 = timings[ata_mode2idx(mode)] << 8;
911 }
912 else {
913 mask44 = 0x0f;
914 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
915 (timings[ata_mode2idx(mode)] & 0x03);
916 }
917 if (atadev->channel->unit) {
918 mask40 <<= 16;
919 new40 <<= 16;
920 mask44 <<= 4;
921 new44 <<= 4;
922 }
923 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
924 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
925
926 atadev->mode = mode;
927 }
928
929 /*
930 * National chipset support functions
931 */
932 int
933 ata_national_ident(device_t dev)
934 {
935 struct ata_pci_controller *ctlr = device_get_softc(dev);
936
937 /* this chip is a clone of the Cyrix chip, bugs and all */
938 if (pci_get_devid(dev) == ATA_SC1100) {
939 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
940 ctlr->chipinit = ata_national_chipinit;
941 return 0;
942 }
943 return ENXIO;
944 }
945
946 static device_t nat_host = NULL;
947
948 static int
949 ata_national_chipinit(device_t dev)
950 {
951 struct ata_pci_controller *ctlr = device_get_softc(dev);
952 device_t *children;
953 int nchildren, i;
954
955 if (ata_setup_interrupt(dev))
956 return ENXIO;
957
958 /* locate the ISA part in the southbridge and enable UDMA33 */
959 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
960 for (i = 0; i < nchildren; i++) {
961 if (pci_get_devid(children[i]) == 0x0510100b) {
962 nat_host = children[i];
963 break;
964 }
965 }
966 free(children, M_TEMP);
967 }
968 ctlr->setmode = ata_national_setmode;
969 return 0;
970 }
971
972 static void
973 ata_national_setmode(struct ata_device *atadev, int mode)
974 {
975 device_t parent = device_get_parent(atadev->channel->dev);
976 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
977 u_int32_t piotiming[] =
978 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
979 0x00803020, 0x20102010, 0x00100010,
980 0x00100010, 0x00100010, 0x00100010 };
981 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
982 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
983 int error;
984
985 atadev->channel->dma->alignment = 16;
986 atadev->channel->dma->max_iosize = 63 * 1024;
987
988 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
989
990 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
991
992 if (bootverbose)
993 ata_prtdev(atadev, "%s setting %s on National chip\n",
994 (error) ? "failed" : "success", ata_mode2str(mode));
995 if (!error) {
996 if (mode >= ATA_UDMA0) {
997 pci_write_config(parent, 0x44 + (devno << 3),
998 udmatiming[mode & ATA_MODE_MASK], 4);
999 }
1000 else if (mode >= ATA_WDMA0) {
1001 pci_write_config(parent, 0x44 + (devno << 3),
1002 dmatiming[mode & ATA_MODE_MASK], 4);
1003 }
1004 else {
1005 pci_write_config(parent, 0x44 + (devno << 3),
1006 pci_read_config(parent, 0x44 + (devno << 3), 4) |
1007 0x80000000, 4);
1008 }
1009 pci_write_config(parent, 0x40 + (devno << 3),
1010 piotiming[ata_mode2idx(mode)], 4);
1011 atadev->mode = mode;
1012 }
1013 }
1014
1015 /*
1016 * nVidia chipset support functions
1017 */
1018 int
1019 ata_nvidia_ident(device_t dev)
1020 {
1021 struct ata_pci_controller *ctlr = device_get_softc(dev);
1022 struct ata_chip_id *idx;
1023 static struct ata_chip_id ids[] =
1024 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA5, "nVidia nForce" },
1025 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA6, "nVidia nForce2" },
1026 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
1027 { 0, 0, 0, 0, 0, 0}};
1028 char buffer[64];
1029
1030 if (!(idx = ata_match_chip(dev, ids)))
1031 return ENXIO;
1032
1033 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1034 device_set_desc_copy(dev, buffer);
1035 ctlr->chip = idx;
1036 ctlr->chipinit = ata_nvidia_chipinit;
1037 return 0;
1038 }
1039
1040 static int
1041 ata_nvidia_chipinit(device_t dev)
1042 {
1043 struct ata_pci_controller *ctlr = device_get_softc(dev);
1044
1045 if (ata_setup_interrupt(dev))
1046 return ENXIO;
1047
1048 /* set prefetch, postwrite */
1049 if (ctlr->chip->cfg2 & AMDBUG)
1050 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
1051 else
1052 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) | 0xf0, 1);
1053
1054 ctlr->setmode = ata_via_family_setmode;
1055 return 0;
1056 }
1057
1058 /*
1059 * Promise chipset support functions
1060 */
1061 int
1062 ata_promise_ident(device_t dev)
1063 {
1064 struct ata_pci_controller *ctlr = device_get_softc(dev);
1065 struct ata_chip_id *idx;
1066 static struct ata_chip_id ids[] =
1067 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
1068 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
1069 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
1070 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
1071 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
1072 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
1073 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
1074 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
1075 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
1076 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
1077 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
1078 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
1079 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
1080 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
1081 { ATA_PDC20371, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20371" },
1082 { ATA_PDC20375, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20375" },
1083 { ATA_PDC20376, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20376" },
1084 { ATA_PDC20377, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20377" },
1085 { ATA_PDC20378, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20378" },
1086 { ATA_PDC20379, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20379" },
1087 { ATA_PDC20617, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20617" },
1088 { ATA_PDC20618, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20618" },
1089 { ATA_PDC20619, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20619" },
1090 { ATA_PDC20620, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20620" },
1091 { 0, 0, 0, 0, 0, 0}};
1092 char buffer[64];
1093 uintptr_t devid = 0;
1094
1095 if (!(idx = ata_match_chip(dev, ids)))
1096 return ENXIO;
1097
1098 /* if we are on a SuperTrak SX6000 dont attach */
1099 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1100 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1101 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1102 devid == ATA_I960RM)
1103 return ENXIO;
1104
1105 strcpy(buffer, idx->text);
1106 /* if we are on a FastTrak TX4, adjust the interrupt resource */
1107 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1108 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1109 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1110 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
1111 static long start = 0, end = 0;
1112
1113 if (pci_get_slot(dev) == 1) {
1114 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
1115 strcat(buffer, " (channel 0+1)");
1116 }
1117 else if (pci_get_slot(dev) == 2 && start && end) {
1118 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1119 start = end = 0;
1120 strcat(buffer, " (channel 2+3)");
1121 }
1122 else {
1123 start = end = 0;
1124 }
1125 }
1126 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1127 device_set_desc_copy(dev, buffer);
1128 ctlr->chip = idx;
1129 ctlr->chipinit = ata_promise_chipinit;
1130 return 0;
1131 }
1132
1133 static int
1134 ata_promise_chipinit(device_t dev)
1135 {
1136 struct ata_pci_controller *ctlr = device_get_softc(dev);
1137 int rid = ATA_IRQ_RID;
1138
1139 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1140 RF_SHAREABLE | RF_ACTIVE))) {
1141 device_printf(dev, "unable to map interrupt\n");
1142 return ENXIO;
1143 }
1144
1145 switch (ctlr->chip->cfg1) {
1146 case PRNEW:
1147 /* setup clocks */
1148 ATA_OUTB(ctlr->r_io1, 0x11, ATA_INB(ctlr->r_io1, 0x11) | 0x0a);
1149
1150 ctlr->dmainit = ata_promise_new_dmainit;
1151 /* FALLTHROUGH */
1152
1153 case PROLD:
1154 /* enable burst mode */
1155 ATA_OUTB(ctlr->r_io1, 0x1f, ATA_INB(ctlr->r_io1, 0x1f) | 0x01);
1156
1157 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1158 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1159 device_printf(dev, "unable to setup interrupt\n");
1160 return ENXIO;
1161 }
1162 break;
1163
1164 case PRTX:
1165 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1166 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1167 device_printf(dev, "unable to setup interrupt\n");
1168 return ENXIO;
1169 }
1170 break;
1171
1172 case PRMIO:
1173 rid = 0x1c;
1174 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1175 0, ~0, 1, RF_ACTIVE)))
1176 return ENXIO;
1177
1178 ctlr->dmainit = ata_promise_mio_dmainit;
1179 ctlr->allocate = ata_promise_mio_allocate;
1180
1181 if (ctlr->chip->cfg2 & PRDUAL) {
1182 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x01) > 0) +
1183 ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 2;
1184 }
1185 else if (ctlr->chip->cfg2 & PRSATA) {
1186 ATA_OUTL(ctlr->r_io2, 0x06c, 0x00ff0033);
1187 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 3;
1188 }
1189 else
1190 ctlr->channels = 4;
1191
1192 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1193 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1194 device_printf(dev, "unable to setup interrupt\n");
1195 return ENXIO;
1196 }
1197 break;
1198 }
1199
1200 ctlr->setmode = ata_promise_setmode;
1201 return 0;
1202 }
1203
1204 static int
1205 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1206 {
1207 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1208 int i;
1209
1210 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1211 ch->r_io[i].res = ctlr->r_io2;
1212 ch->r_io[i].offset = 0x200 + (i << 2) + (ch->unit << 7);
1213 }
1214 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1215 ch->r_io[ATA_ALTSTAT].offset = 0x238 + (ch->unit << 7);
1216 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_io2;
1217 ch->r_io[ATA_BMCMD_PORT].offset = 0x260 + (ch->unit << 7);
1218 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1219 ch->r_io[ATA_BMDTP_PORT].offset = 0x244 + (ch->unit << 7);
1220 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1221 ch->r_io[ATA_BMDEVSPEC_0].offset = ((ch->unit + 1) << 2);
1222 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1223
1224 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1225 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00003f9f) |
1226 (ch->unit + 1));
1227 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1228
1229 ch->flags |= (ATA_NO_SLAVE | ATA_USE_16BIT);
1230 ctlr->dmainit(ch);
1231 return 0;
1232 }
1233
1234 static void
1235 ata_promise_old_intr(void *data)
1236 {
1237 struct ata_pci_controller *ctlr = data;
1238 struct ata_channel *ch;
1239 int unit;
1240
1241 /* implement this as a toggle instead to balance load XXX */
1242 for (unit = 0; unit < 2; unit++) {
1243 if (!(ch = ctlr->interrupt[unit].argument))
1244 continue;
1245 if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
1246 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1247 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1248
1249 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1250 ATA_BMSTAT_INTERRUPT)
1251 continue;
1252 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1253 DELAY(1);
1254 }
1255 ctlr->interrupt[unit].function(ch);
1256 }
1257 }
1258 }
1259
1260 static void
1261 ata_promise_tx2_intr(void *data)
1262 {
1263 struct ata_pci_controller *ctlr = data;
1264 struct ata_channel *ch;
1265 int unit;
1266
1267 /* implement this as a toggle instead to balance load XXX */
1268 for (unit = 0; unit < 2; unit++) {
1269 if (!(ch = ctlr->interrupt[unit].argument))
1270 continue;
1271 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1272 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1273 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1274 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1275
1276 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1277 ATA_BMSTAT_INTERRUPT)
1278 continue;
1279 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1280 DELAY(1);
1281 }
1282 ctlr->interrupt[unit].function(ch);
1283 }
1284 }
1285 }
1286
1287 static void
1288 ata_promise_mio_intr(void *data)
1289 {
1290 struct ata_pci_controller *ctlr = data;
1291 struct ata_channel *ch;
1292 u_int32_t irq_vector;
1293 int unit;
1294
1295 irq_vector = ATA_INL(ctlr->r_io2, 0x0040);
1296 for (unit = 0; unit < ctlr->channels; unit++) {
1297 if (irq_vector & (1 << (unit + 1))) {
1298 if ((ch = ctlr->interrupt[unit].argument)) {
1299 ctlr->interrupt[unit].function(ch);
1300 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1301 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00003f9f) |
1302 (ch->unit + 1));
1303 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1304 }
1305 }
1306 }
1307 }
1308
1309 static void
1310 ata_promise_setmode(struct ata_device *atadev, int mode)
1311 {
1312 device_t parent = device_get_parent(atadev->channel->dev);
1313 struct ata_pci_controller *ctlr = device_get_softc(parent);
1314 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1315 int error;
1316 u_int32_t timings33[][2] = {
1317 /* PROLD PRNEW mode */
1318 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
1319 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
1320 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
1321 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
1322 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
1323 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
1324 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
1325 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
1326 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
1327 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
1328 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
1329 { 0, 0x00424ef6 }, /* UDMA 3 */
1330 { 0, 0x004127f3 }, /* UDMA 4 */
1331 { 0, 0x004127f3 } /* UDMA 5 */
1332 };
1333
1334 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1335
1336 switch (ctlr->chip->cfg1) {
1337 case PROLD:
1338 case PRNEW:
1339 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
1340 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
1341 ata_prtdev(atadev,
1342 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1343 mode = ATA_UDMA2;
1344 }
1345 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
1346 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
1347 break;
1348
1349 case PRTX:
1350 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
1351 if (mode > ATA_UDMA2 &&
1352 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
1353 ata_prtdev(atadev,
1354 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1355 mode = ATA_UDMA2;
1356 }
1357 break;
1358
1359 case PRMIO:
1360 if (mode > ATA_UDMA2 &&
1361 (ATA_IDX_INL(atadev->channel, ATA_BMCMD_PORT) & 0x01000000)) {
1362 ata_prtdev(atadev,
1363 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1364 mode = ATA_UDMA2;
1365 }
1366 break;
1367 }
1368
1369 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1370
1371 if (bootverbose)
1372 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1373 (error) ? "FAILURE " : "",
1374 ata_mode2str(mode), ctlr->chip->text);
1375 if (!error) {
1376 if (ctlr->chip->cfg1 < PRTX)
1377 pci_write_config(parent, 0x60 + (devno << 2),
1378 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
1379 atadev->mode = mode;
1380 }
1381 return;
1382 }
1383
1384 static void
1385 ata_promise_new_dmainit(struct ata_channel *ch)
1386 {
1387 ata_dmainit(ch);
1388 if (ch->dma) {
1389 ch->dma->start = ata_promise_new_dmastart;
1390 ch->dma->stop = ata_promise_new_dmastop;
1391 }
1392 }
1393
1394 static int
1395 ata_promise_new_dmastart(struct ata_channel *ch)
1396 {
1397 struct ata_pci_controller *ctlr =
1398 device_get_softc(device_get_parent(ch->dev));
1399
1400 if (ch->flags & ATA_48BIT_ACTIVE) {
1401 ATA_OUTB(ctlr->r_io1, 0x11,
1402 ATA_INB(ctlr->r_io1, 0x11) | (ch->unit ? 0x08 : 0x02));
1403 ATA_OUTL(ctlr->r_io1, 0x20,
1404 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
1405 (ch->dma->cur_iosize >> 1));
1406 }
1407 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1408 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1409 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1410 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1411 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
1412 ATA_BMCMD_START_STOP);
1413 return 0;
1414 }
1415
1416 static int
1417 ata_promise_new_dmastop(struct ata_channel *ch)
1418 {
1419 struct ata_pci_controller *ctlr =
1420 device_get_softc(device_get_parent(ch->dev));
1421 int error;
1422
1423 if (ch->flags & ATA_48BIT_ACTIVE) {
1424 ATA_OUTB(ctlr->r_io1, 0x11,
1425 ATA_INB(ctlr->r_io1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
1426 ATA_OUTL(ctlr->r_io1, 0x20, 0);
1427 }
1428 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
1429 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1430 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1431 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1432 return error;
1433 }
1434
1435 static void
1436 ata_promise_mio_dmainit(struct ata_channel *ch)
1437 {
1438 ata_dmainit(ch);
1439 if (ch->dma) {
1440 ch->dma->start = ata_promise_mio_dmastart;
1441 ch->dma->stop = ata_promise_mio_dmastop;
1442 }
1443 }
1444
1445 static int
1446 ata_promise_mio_dmastart(struct ata_channel *ch)
1447 {
1448 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1449 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1450 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x000000c0) |
1451 ((ch->dma->flags & ATA_DMA_READ) ? 0x00000080 : 0x000000c0));
1452 return 0;
1453 }
1454
1455 static int
1456 ata_promise_mio_dmastop(struct ata_channel *ch)
1457 {
1458 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1459 ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00000080);
1460 return 0;
1461 }
1462
1463 /*
1464 * ServerWorks chipset support functions
1465 */
1466 int
1467 ata_serverworks_ident(device_t dev)
1468 {
1469 struct ata_pci_controller *ctlr = device_get_softc(dev);
1470 struct ata_chip_id *idx;
1471 static struct ata_chip_id ids[] =
1472 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
1473 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
1474 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
1475 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
1476 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
1477 { 0, 0, 0, 0, 0, 0}};
1478 char buffer[64];
1479
1480 if (!(idx = ata_match_chip(dev, ids)))
1481 return ENXIO;
1482
1483 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1484 device_set_desc_copy(dev, buffer);
1485 ctlr->chip = idx;
1486 ctlr->chipinit = ata_serverworks_chipinit;
1487 return 0;
1488 }
1489
1490 static int
1491 ata_serverworks_chipinit(device_t dev)
1492 {
1493 struct ata_pci_controller *ctlr = device_get_softc(dev);
1494
1495 if (ata_setup_interrupt(dev))
1496 return ENXIO;
1497
1498 if (ctlr->chip->cfg1 == SWKS33) {
1499 device_t *children;
1500 int nchildren, i;
1501
1502 /* locate the ISA part in the southbridge and enable UDMA33 */
1503 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1504 for (i = 0; i < nchildren; i++) {
1505 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
1506 pci_write_config(children[i], 0x64,
1507 (pci_read_config(children[i], 0x64, 4) &
1508 ~0x00002000) | 0x00004000, 4);
1509 break;
1510 }
1511 }
1512 free(children, M_TEMP);
1513 }
1514 }
1515 else {
1516 pci_write_config(dev, 0x5a,
1517 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
1518 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
1519 }
1520 ctlr->setmode = ata_serverworks_setmode;
1521 return 0;
1522 }
1523
1524 static void
1525 ata_serverworks_setmode(struct ata_device *atadev, int mode)
1526 {
1527 device_t parent = device_get_parent(atadev->channel->dev);
1528 struct ata_pci_controller *ctlr = device_get_softc(parent);
1529 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1530 int offset = devno ^ 0x01;
1531 int error;
1532 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1533 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1534 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1535
1536 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1537
1538 mode = ata_check_80pin(atadev, mode);
1539
1540 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1541
1542 if (bootverbose)
1543 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1544 (error) ? "FAILURE " : "",
1545 ata_mode2str(mode), ctlr->chip->text);
1546 if (!error) {
1547 if (mode >= ATA_UDMA0) {
1548 pci_write_config(parent, 0x56,
1549 (pci_read_config(parent, 0x56, 2) &
1550 ~(0xf << (devno << 2))) |
1551 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1552
1553 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) |
1554 (0x01 << devno), 1);
1555 pci_write_config(parent, 0x44,
1556 (pci_read_config(parent, 0x44, 4) &
1557 ~(0xff << (offset << 8))) |
1558 (dmatimings[2] << (offset << 8)), 4);
1559 }
1560 else if (mode >= ATA_WDMA0) {
1561 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) &
1562 ~(0x01 << devno), 1);
1563 pci_write_config(parent, 0x44,
1564 (pci_read_config(parent, 0x44, 4) &
1565 ~(0xff << (offset << 8))) |
1566 (dmatimings[mode & ATA_MODE_MASK]<<(offset<<8)),4);
1567 }
1568 else
1569 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) &
1570 ~(0x01 << devno), 1);
1571
1572 pci_write_config(parent, 0x40,
1573 (pci_read_config(parent, 0x40, 4) &
1574 ~(0xff << (offset << 8))) |
1575 (piotimings[ata_mode2idx(mode)] << (offset << 8)), 4);
1576 atadev->mode = mode;
1577 }
1578 }
1579
1580 /*
1581 * Silicon Image (former CMD) chipset support functions
1582 */
1583 int
1584 ata_sii_ident(device_t dev)
1585 {
1586 struct ata_pci_controller *ctlr = device_get_softc(dev);
1587 struct ata_chip_id *idx;
1588 static struct ata_chip_id ids[] =
1589 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
1590 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
1591 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
1592 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
1593 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
1594 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
1595 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
1596 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
1597 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
1598 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
1599 { 0, 0, 0, 0, 0, 0}};
1600 char buffer[64];
1601
1602 if (!(idx = ata_match_chip(dev, ids)))
1603 return ENXIO;
1604
1605 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1606 device_set_desc_copy(dev, buffer);
1607 ctlr->chip = idx;
1608 ctlr->chipinit = ata_sii_chipinit;
1609 return 0;
1610 }
1611
1612 static int
1613 ata_sii_chipinit(device_t dev)
1614 {
1615 struct ata_pci_controller *ctlr = device_get_softc(dev);
1616 int rid = ATA_IRQ_RID;
1617
1618 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1619 RF_SHAREABLE | RF_ACTIVE))) {
1620 device_printf(dev, "unable to map interrupt\n");
1621 return ENXIO;
1622 }
1623
1624 if (ctlr->chip->cfg1 == SIIMEMIO) {
1625 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1626 ata_sii_intr, ctlr, &ctlr->handle))) {
1627 device_printf(dev, "unable to setup interrupt\n");
1628 return ENXIO;
1629 }
1630
1631 rid = 0x24;
1632 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1633 0, ~0, 1, RF_ACTIVE)))
1634 return ENXIO;
1635
1636 if (ctlr->chip->cfg2 & SIISETCLK) {
1637 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1638 pci_write_config(dev, 0x8a,
1639 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
1640 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1641 device_printf(dev, "%s could not set ATA133 clock\n",
1642 ctlr->chip->text);
1643 }
1644
1645 if (ctlr->chip->cfg2 & SII4CH)
1646 ctlr->channels = 4;
1647
1648 /* enable interrupt as BIOS might not */
1649 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
1650
1651 /* setup chipset defaults as BIOS might not */
1652 #if 0
1653 pci_write_config(dev, 0xa2, 0x328a, 2);
1654 pci_write_config(dev, 0xa4, 0x328a328a, 4);
1655 pci_write_config(dev, 0xa8, 0x22082208, 4);
1656 pci_write_config(dev, 0xac, 0x40094009, 4);
1657 pci_write_config(dev, 0xe2, 0x328a, 2);
1658 pci_write_config(dev, 0xe4, 0x328a328a, 4);
1659 pci_write_config(dev, 0xe8, 0x22082208, 4);
1660 pci_write_config(dev, 0xec, 0x40094009, 4);
1661 #endif
1662 ctlr->allocate = ata_sii_mio_allocate;
1663 if (ctlr->chip->max_dma >= ATA_SA150)
1664 ctlr->setmode = ata_sata_setmode;
1665 else
1666 ctlr->setmode = ata_sii_setmode;
1667 }
1668 else {
1669 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1670 ctlr->chip->cfg2 & SIIINTR ?
1671 ata_cmd_intr : ata_cmd_old_intr,
1672 ctlr, &ctlr->handle))) {
1673 device_printf(dev, "unable to setup interrupt\n");
1674 return ENXIO;
1675 }
1676
1677 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
1678 device_printf(dev, "HW has secondary channel disabled\n");
1679 ctlr->channels = 1;
1680 }
1681
1682 /* enable interrupt as BIOS might not */
1683 pci_write_config(dev, 0x71, 0x01, 1);
1684
1685 ctlr->setmode = ata_cmd_setmode;
1686 }
1687 return 0;
1688 }
1689
1690 static int
1691 ata_sii_mio_allocate(device_t dev, struct ata_channel *ch)
1692 {
1693 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1694 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1695 int i;
1696
1697 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1698 ch->r_io[i].res = ctlr->r_io2;
1699 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 9);
1700 }
1701 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1702 ch->r_io[ATA_ALTSTAT].offset = 0x8a + (unit01 << 6) + (unit10 << 9);
1703 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_io2;
1704 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 9);
1705 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_io2;
1706 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 9);
1707 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1708 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 9);
1709 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1710 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 9);
1711 ch->r_io[ATA_BMDEVSPEC_1].res = ctlr->r_io2;
1712 ch->r_io[ATA_BMDEVSPEC_1].offset = 0x100 + (unit01 << 7) + (unit10 << 9);
1713 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1714
1715 if (ctlr->chip->max_dma >= ATA_SA150)
1716 ch->flags |= ATA_NO_SLAVE;
1717
1718 ctlr->dmainit(ch);
1719 if (ctlr->chip->cfg2 & SIIBUG)
1720 ch->dma->boundary = 8 * 1024;
1721
1722 ch->reset = ata_sii_reset;
1723
1724 return 0;
1725 }
1726
1727 static void
1728 ata_sii_reset(struct ata_channel *ch)
1729 {
1730 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000001);
1731 DELAY(25000);
1732 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000000);
1733 }
1734
1735 static void
1736 ata_sii_intr(void *data)
1737 {
1738 struct ata_pci_controller *ctlr = data;
1739 struct ata_channel *ch;
1740 int unit;
1741
1742 /* implement this as a toggle instead to balance load XXX */
1743 for (unit = 0; unit < 2; unit++) {
1744 if (!(ch = ctlr->interrupt[unit].argument))
1745 continue;
1746 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
1747 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1748 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1749
1750 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
1751 continue;
1752 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1753 DELAY(1);
1754 }
1755 ctlr->interrupt[unit].function(ch);
1756 }
1757 }
1758 }
1759
1760 static void
1761 ata_cmd_intr(void *data)
1762 {
1763 struct ata_pci_controller *ctlr = data;
1764 struct ata_channel *ch;
1765 u_int8_t reg71;
1766 int unit;
1767
1768 /* implement this as a toggle instead to balance load XXX */
1769 for (unit = 0; unit < 2; unit++) {
1770 if (!(ch = ctlr->interrupt[unit].argument))
1771 continue;
1772 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
1773 (ch->unit ? 0x08 : 0x04))) {
1774 pci_write_config(device_get_parent(ch->dev), 0x71,
1775 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
1776 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1777 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1778
1779 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1780 ATA_BMSTAT_INTERRUPT)
1781 continue;
1782 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1783 DELAY(1);
1784 }
1785 ctlr->interrupt[unit].function(ch);
1786 }
1787 }
1788 }
1789
1790 static void
1791 ata_cmd_old_intr(void *data)
1792 {
1793 struct ata_pci_controller *ctlr = data;
1794 struct ata_channel *ch;
1795 int unit;
1796
1797 /* implement this as a toggle instead to balance load XXX */
1798 for (unit = 0; unit < 2; unit++) {
1799 if (!(ch = ctlr->interrupt[unit].argument))
1800 continue;
1801 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1802 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1803
1804 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1805 ATA_BMSTAT_INTERRUPT)
1806 continue;
1807 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1808 DELAY(1);
1809 }
1810 ctlr->interrupt[unit].function(ch);
1811 }
1812 }
1813
1814 static void
1815 ata_sii_setmode(struct ata_device *atadev, int mode)
1816 {
1817 device_t parent = device_get_parent(atadev->channel->dev);
1818 struct ata_pci_controller *ctlr = device_get_softc(parent);
1819 int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
1820 int mreg = atadev->channel->unit ? 0x84 : 0x80;
1821 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
1822 int mval = pci_read_config(parent, mreg, 1) & ~mask;
1823 int error;
1824
1825 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1826
1827 if (ctlr->chip->cfg2 & SIISETCLK) {
1828 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
1829 (atadev->channel->unit ? 0x02 : 0x01))) {
1830 ata_prtdev(atadev,
1831 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1832 mode = ATA_UDMA2;
1833 }
1834 }
1835 else
1836 mode = ata_check_80pin(atadev, mode);
1837
1838 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1839
1840 if (bootverbose)
1841 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1842 (error) ? "FAILURE " : "",
1843 ata_mode2str(mode), ctlr->chip->text);
1844 if (error)
1845 return;
1846
1847 if (mode >= ATA_UDMA0) {
1848 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1849 u_int8_t ureg = 0xac + rego;
1850
1851 pci_write_config(parent, mreg,
1852 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
1853 pci_write_config(parent, ureg,
1854 (pci_read_config(parent, ureg, 1) & ~0x3f) |
1855 udmatimings[mode & ATA_MODE_MASK], 1);
1856
1857 }
1858 else if (mode >= ATA_WDMA0) {
1859 u_int8_t dreg = 0xa8 + rego;
1860 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
1861
1862 pci_write_config(parent, mreg,
1863 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
1864 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
1865
1866 }
1867 else {
1868 u_int8_t preg = 0xa4 + rego;
1869 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
1870
1871 pci_write_config(parent, mreg,
1872 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
1873 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
1874 }
1875 atadev->mode = mode;
1876 }
1877
1878 static void
1879 ata_cmd_setmode(struct ata_device *atadev, int mode)
1880 {
1881 device_t parent = device_get_parent(atadev->channel->dev);
1882 struct ata_pci_controller *ctlr = device_get_softc(parent);
1883 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1884 int error;
1885
1886 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1887
1888 mode = ata_check_80pin(atadev, mode);
1889
1890 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1891
1892 if (bootverbose)
1893 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1894 (error) ? "FAILURE " : "",
1895 ata_mode2str(mode), ctlr->chip->text);
1896 if (!error) {
1897 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
1898 int ureg = atadev->channel->unit ? 0x7b : 0x73;
1899
1900 if (mode >= ATA_UDMA0) {
1901 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
1902 { 0x11, 0x42 }, { 0x25, 0x8a },
1903 { 0x15, 0x4a }, { 0x05, 0x0a } };
1904
1905 u_int8_t umode = pci_read_config(parent, ureg, 1);
1906
1907 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
1908 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
1909 pci_write_config(parent, ureg, umode, 1);
1910 }
1911 else if (mode >= ATA_WDMA0) {
1912 int dmatimings[] = { 0x87, 0x32, 0x3f };
1913
1914 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
1915 pci_write_config(parent, ureg,
1916 pci_read_config(parent, ureg, 1) &
1917 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1918 }
1919 else {
1920 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1921 pci_write_config(parent, treg,
1922 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
1923 pci_write_config(parent, ureg,
1924 pci_read_config(parent, ureg, 1) &
1925 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1926 }
1927 atadev->mode = mode;
1928 }
1929 }
1930
1931 /*
1932 * SiS chipset support functions
1933 */
1934 int
1935 ata_sis_ident(device_t dev)
1936 {
1937 struct ata_pci_controller *ctlr = device_get_softc(dev);
1938 struct ata_chip_id *idx;
1939 static struct ata_chip_id ids[] =
1940 {{ ATA_SIS964_1,0x00, SISSATA, 0, ATA_SA150, "SiS 964" }, /* south */
1941 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 964" }, /* south */
1942 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
1943 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
1944
1945 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
1946 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
1947 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
1948 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
1949
1950 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
1951 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
1952 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
1953 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
1954 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
1955
1956 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
1957 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
1958 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
1959
1960 { ATA_SIS5513, 0xc2, SIS33, 0, ATA_UDMA2, "SiS 5513" },
1961 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "SiS 5513" },
1962 { 0, 0, 0, 0, 0, 0 }};
1963 char buffer[64];
1964
1965 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
1966 return ENXIO;
1967
1968 if (idx->cfg2) {
1969 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) & 0x7f, 1);
1970 if (pci_read_config(dev, 0x00, 4) == ATA_SIS5518) {
1971 idx->cfg1 = SIS133NEW;
1972 idx->max_dma = ATA_UDMA6;
1973 sprintf(buffer, "SiS 962/963 %s controller",
1974 ata_mode2str(idx->max_dma));
1975 }
1976 else {
1977 struct ata_chip_id id[] =
1978 {{ ATA_SISSOUTH, 0x10, 0, 0, ATA_UDMA6, "SiS 961" },
1979 { 0, 0, 0, 0, 0, 0 }};
1980
1981 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
1982 idx->cfg1 = SIS133OLD;
1983 idx->max_dma = ATA_UDMA6;
1984 }
1985 else {
1986 idx->cfg1 = SIS100NEW;
1987 idx->max_dma = ATA_UDMA5;
1988 }
1989 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
1990 }
1991 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) | 0x80, 1);
1992 }
1993 else
1994 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
1995 device_set_desc_copy(dev, buffer);
1996 ctlr->chip = idx;
1997 ctlr->chipinit = ata_sis_chipinit;
1998 return 0;
1999 }
2000
2001 static int
2002 ata_sis_chipinit(device_t dev)
2003 {
2004 struct ata_pci_controller *ctlr = device_get_softc(dev);
2005
2006 if (ata_setup_interrupt(dev))
2007 return ENXIO;
2008
2009 switch (ctlr->chip->cfg1) {
2010 case SIS33:
2011 break;
2012 case SIS66:
2013 case SIS100OLD:
2014 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) | 0x04, 1);
2015 break;
2016 case SIS100NEW:
2017 case SIS133OLD:
2018 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) | 0x01, 1);
2019 break;
2020 case SIS133NEW:
2021 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) & 0xfff7, 2);
2022 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) & 0xfff7, 2);
2023 break;
2024 case SISSATA:
2025 pci_write_config(dev, 0x04, pci_read_config(dev, 0x04, 2) & ~0x0400, 2);
2026 ctlr->setmode = ata_sata_setmode;
2027 return 0;
2028 default:
2029 return ENXIO;
2030 }
2031 ctlr->setmode = ata_sis_setmode;
2032 return 0;
2033 }
2034
2035 static void
2036 ata_sis_setmode(struct ata_device *atadev, int mode)
2037 {
2038 device_t parent = device_get_parent(atadev->channel->dev);
2039 struct ata_pci_controller *ctlr = device_get_softc(parent);
2040 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2041 int error;
2042
2043 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2044
2045 if (ctlr->chip->cfg1 == SIS133NEW) {
2046 if (mode > ATA_UDMA2 &&
2047 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
2048 ata_prtdev(atadev,
2049 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2050 mode = ATA_UDMA2;
2051 }
2052 }
2053 else {
2054 if (mode > ATA_UDMA2 &&
2055 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
2056 ata_prtdev(atadev,
2057 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2058 mode = ATA_UDMA2;
2059 }
2060 }
2061
2062 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2063
2064 if (bootverbose)
2065 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2066 (error) ? "FAILURE " : "",
2067 ata_mode2str(mode), ctlr->chip->text);
2068 if (!error) {
2069 switch (ctlr->chip->cfg1) {
2070 case SIS133NEW: {
2071 u_int32_t timings[] =
2072 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
2073 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
2074 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
2075 u_int32_t reg;
2076
2077 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
2078 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
2079 break;
2080 }
2081 case SIS133OLD: {
2082 u_int16_t timings[] =
2083 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
2084 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
2085
2086 u_int16_t reg = 0x40 + (devno << 1);
2087
2088 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2089 break;
2090 }
2091 case SIS100NEW: {
2092 u_int16_t timings[] =
2093 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
2094 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2095 u_int16_t reg = 0x40 + (devno << 1);
2096
2097 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2098 break;
2099 }
2100 case SIS100OLD:
2101 case SIS66:
2102 case SIS33: {
2103 u_int16_t timings[] =
2104 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
2105 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
2106 u_int16_t reg = 0x40 + (devno << 1);
2107
2108 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2109 break;
2110 }
2111 }
2112 atadev->mode = mode;
2113 }
2114 }
2115
2116 /* VIA chipsets */
2117 int
2118 ata_via_ident(device_t dev)
2119 {
2120 struct ata_pci_controller *ctlr = device_get_softc(dev);
2121 struct ata_chip_id *idx;
2122 static struct ata_chip_id ids[] =
2123 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
2124 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
2125 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
2126 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
2127 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
2128 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
2129 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
2130 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
2131 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
2132 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
2133 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
2134 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
2135 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
2136 { 0, 0, 0, 0, 0, 0 }};
2137 static struct ata_chip_id new_ids[] =
2138 {{ ATA_VIA8237_1, 0x00, 0x00, 0x00, ATA_SA150, "VIA 8237" },
2139 { 0, 0, 0, 0, 0, 0 }};
2140 char buffer[64];
2141
2142 if (pci_get_devid(dev) == ATA_VIA82C571) {
2143 if (!(idx = ata_find_chip(dev, ids, -99)))
2144 return ENXIO;
2145 }
2146 else {
2147 if (!(idx = ata_match_chip(dev, new_ids)))
2148 return ENXIO;
2149 }
2150
2151 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2152 device_set_desc_copy(dev, buffer);
2153 ctlr->chip = idx;
2154 ctlr->chipinit = ata_via_chipinit;
2155 return 0;
2156 }
2157
2158 static int
2159 ata_via_chipinit(device_t dev)
2160 {
2161 struct ata_pci_controller *ctlr = device_get_softc(dev);
2162
2163 if (ata_setup_interrupt(dev))
2164 return ENXIO;
2165
2166 if (ctlr->chip->max_dma >= ATA_SA150) {
2167 ctlr->setmode = ata_sata_setmode;
2168 return 0;
2169 }
2170
2171 /* prepare for ATA-66 on the 82C686a and 82C596b */
2172 if (ctlr->chip->cfg2 & VIACLK)
2173 pci_write_config(dev, 0x50, 0x030b030b, 4);
2174
2175 /* the southbridge might need the data corruption fix */
2176 if (ctlr->chip->cfg2 & VIABUG)
2177 ata_via_southbridge_fixup(dev);
2178
2179 /* set prefetch, postwrite */
2180 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
2181
2182 /* set fifo configuration half'n'half */
2183 pci_write_config(dev, 0x43,
2184 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
2185
2186 /* set status register read retry */
2187 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
2188
2189 /* set DMA read & end-of-sector fifo flush */
2190 pci_write_config(dev, 0x46,
2191 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
2192
2193 /* set sector size */
2194 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
2195 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
2196
2197 ctlr->setmode = ata_via_family_setmode;
2198 return 0;
2199 }
2200
2201 static void
2202 ata_via_southbridge_fixup(device_t dev)
2203 {
2204 device_t *children;
2205 int nchildren, i;
2206
2207 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2208 return;
2209
2210 for (i = 0; i < nchildren; i++) {
2211 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
2212 pci_get_devid(children[i]) == ATA_VIA8371 ||
2213 pci_get_devid(children[i]) == ATA_VIA8662 ||
2214 pci_get_devid(children[i]) == ATA_VIA8361) {
2215 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
2216
2217 if ((reg76 & 0xf0) != 0xd0) {
2218 device_printf(dev,
2219 "Correcting VIA config for southbridge data corruption bug\n");
2220 pci_write_config(children[i], 0x75, 0x80, 1);
2221 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
2222 }
2223 break;
2224 }
2225 }
2226 free(children, M_TEMP);
2227 }
2228
2229 /* common code for VIA, AMD & nVidia */
2230 static void
2231 ata_via_family_setmode(struct ata_device *atadev, int mode)
2232 {
2233 device_t parent = device_get_parent(atadev->channel->dev);
2234 struct ata_pci_controller *ctlr = device_get_softc(parent);
2235 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
2236 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
2237 int modes[][7] = {
2238 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2239 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2240 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2241 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
2242 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
2243 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2244 int reg = 0x53 - devno;
2245 int error;
2246
2247 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2248
2249 if (ctlr->chip->cfg2 & AMDCABLE) {
2250 if (mode > ATA_UDMA2 &&
2251 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
2252 ata_prtdev(atadev,
2253 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2254 mode = ATA_UDMA2;
2255 }
2256 }
2257 else
2258 mode = ata_check_80pin(atadev, mode);
2259
2260 if (ctlr->chip->cfg2 & NVIDIA)
2261 reg += 0x10;
2262
2263 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
2264
2265 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2266
2267 if (bootverbose)
2268 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2269 (error) ? "FAILURE " : "", ata_mode2str(mode),
2270 ctlr->chip->text);
2271 if (!error) {
2272 if (mode >= ATA_UDMA0)
2273 pci_write_config(parent, reg,
2274 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2275 else
2276 pci_write_config(parent, reg, 0x8b, 1);
2277 atadev->mode = mode;
2278 }
2279 }
2280
2281 /* misc functions */
2282 static struct ata_chip_id *
2283 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2284 {
2285 device_t *children;
2286 int nchildren, i;
2287
2288 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2289 return 0;
2290
2291 while (index->chipid != 0) {
2292 for (i = 0; i < nchildren; i++) {
2293 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
2294 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
2295 pci_get_devid(children[i]) == index->chipid &&
2296 pci_get_revid(children[i]) >= index->chiprev) {
2297 free(children, M_TEMP);
2298 return index;
2299 }
2300 }
2301 index++;
2302 }
2303 free(children, M_TEMP);
2304 return NULL;
2305 }
2306
2307 static struct ata_chip_id *
2308 ata_match_chip(device_t dev, struct ata_chip_id *index)
2309 {
2310 while (index->chipid != 0) {
2311 if (pci_get_devid(dev) == index->chipid &&
2312 pci_get_revid(dev) >= index->chiprev)
2313 return index;
2314 index++;
2315 }
2316 return NULL;
2317 }
2318
2319 static int
2320 ata_setup_interrupt(device_t dev)
2321 {
2322 struct ata_pci_controller *ctlr = device_get_softc(dev);
2323 int rid = ATA_IRQ_RID;
2324
2325 if (!ATA_MASTERDEV(dev)) {
2326 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2327 RF_SHAREABLE | RF_ACTIVE))) {
2328 device_printf(dev, "unable to map interrupt\n");
2329 return ENXIO;
2330 }
2331 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2332 ata_generic_intr, ctlr, &ctlr->handle))) {
2333 device_printf(dev, "unable to setup interrupt\n");
2334 return ENXIO;
2335 }
2336 }
2337 return 0;
2338 }
2339
2340 static void
2341 ata_serialize(struct ata_channel *ch, int flags)
2342 {
2343 struct ata_pci_controller *scp =
2344 device_get_softc(device_get_parent(ch->dev));
2345
2346 switch (flags) {
2347 case ATA_LF_LOCK:
2348 if (scp->locked_ch == ch->unit)
2349 break;
2350 while (!atomic_cmpset_acq_int(&scp->locked_ch, -1, ch->unit))
2351 tsleep(ch->locking, PRIBIO, "atasrl", 1);
2352 break;
2353
2354 case ATA_LF_UNLOCK:
2355 if (scp->locked_ch == -1 || scp->locked_ch != ch->unit)
2356 break;
2357 atomic_store_rel_int(&scp->locked_ch, -1);
2358 wakeup(ch->locking);
2359 break;
2360 }
2361 return;
2362 }
2363
2364 static int
2365 ata_check_80pin(struct ata_device *atadev, int mode)
2366 {
2367 if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) {
2368 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
2369 mode = ATA_UDMA2;
2370 }
2371 return mode;
2372 }
2373
2374 static int
2375 ata_mode2idx(int mode)
2376 {
2377 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
2378 return (mode & ATA_MODE_MASK) + 8;
2379 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
2380 return (mode & ATA_MODE_MASK) + 5;
2381 return (mode & ATA_MODE_MASK) - ATA_PIO0;
2382 }
Cache object: 0816a1ccb0f93ff3ff9e745853be19eb
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